mirror of
https://github.com/garrettsworkshop/GR8RAM.git
synced 2024-06-08 11:10:54 +00:00
79dd794f45
For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
7 lines
298 B
Plaintext
Executable File
7 lines
298 B
Plaintext
Executable File
start_full_compilation:s:00:00:26
|
|
start_analysis_synthesis:s:00:00:10-start_full_compilation
|
|
start_analysis_elaboration:s-start_full_compilation
|
|
start_fitter:s:00:00:05-start_full_compilation
|
|
start_assembler:s:00:00:05-start_full_compilation
|
|
start_timing_analyzer:s:00:00:06-start_full_compilation
|