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79dd794f45
For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
47 lines
2.9 KiB
Plaintext
47 lines
2.9 KiB
Plaintext
--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="MAX7000S" LPM_DIRECTION="ADD" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=8 ONE_INPUT_IS_CONSTANT="YES" cin dataa datab result
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--VERSION_BEGIN 13.0 cbx_cycloneii 2013:06:12:18:03:40:SJ cbx_lpm_add_sub 2013:06:12:18:03:40:SJ cbx_mgl 2013:06:12:18:04:42:SJ cbx_stratix 2013:06:12:18:03:40:SJ cbx_stratixii 2013:06:12:18:03:40:SJ VERSION_END
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-- Copyright (C) 1991-2013 Altera Corporation
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-- Your use of Altera Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Altera Program License
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-- Subscription Agreement, Altera MegaCore Function License
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-- Agreement, or other applicable license agreement, including,
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-- without limitation, that your use is for the sole purpose of
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-- programming logic devices manufactured by Altera and sold by
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-- Altera or its authorized distributors. Please refer to the
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-- applicable agreement for further details.
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FUNCTION carry_sum (cin, sin)
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RETURNS ( cout, sout);
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--synthesis_resources = lut 9
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SUBDESIGN add_sub_rnh
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(
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cin : input;
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dataa[7..0] : input;
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datab[7..0] : input;
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result[7..0] : output;
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)
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VARIABLE
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add_sub_cella[7..0] : carry_sum;
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external_cin_cell : carry_sum;
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datab_node[7..0] : WIRE;
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main_cin_wire : WIRE;
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BEGIN
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add_sub_cella[].cin = ( ((dataa[7..7] & datab_node[7..7]) # ((dataa[7..7] # datab_node[7..7]) & add_sub_cella[6].cout)), ((dataa[6..6] & datab_node[6..6]) # ((dataa[6..6] # datab_node[6..6]) & add_sub_cella[5].cout)), ((dataa[5..5] & datab_node[5..5]) # ((dataa[5..5] # datab_node[5..5]) & add_sub_cella[4].cout)), ((dataa[4..4] & datab_node[4..4]) # ((dataa[4..4] # datab_node[4..4]) & add_sub_cella[3].cout)), ((dataa[3..3] & datab_node[3..3]) # ((dataa[3..3] # datab_node[3..3]) & add_sub_cella[2].cout)), ((dataa[2..2] & datab_node[2..2]) # ((dataa[2..2] # datab_node[2..2]) & add_sub_cella[1].cout)), ((dataa[1..1] & datab_node[1..1]) # ((dataa[1..1] # datab_node[1..1]) & add_sub_cella[0].cout)), ((dataa[0..0] & datab_node[0..0]) # ((dataa[0..0] # datab_node[0..0]) & main_cin_wire)));
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add_sub_cella[].sin = ( ((dataa[7..7] $ datab_node[7..7]) $ add_sub_cella[6].cout), ((dataa[6..6] $ datab_node[6..6]) $ add_sub_cella[5].cout), ((dataa[5..5] $ datab_node[5..5]) $ add_sub_cella[4].cout), ((dataa[4..4] $ datab_node[4..4]) $ add_sub_cella[3].cout), ((dataa[3..3] $ datab_node[3..3]) $ add_sub_cella[2].cout), ((dataa[2..2] $ datab_node[2..2]) $ add_sub_cella[1].cout), ((dataa[1..1] $ datab_node[1..1]) $ add_sub_cella[0].cout), ((dataa[0..0] $ datab_node[0..0]) $ main_cin_wire));
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external_cin_cell.cin = cin;
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external_cin_cell.sin = B"0";
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datab_node[] = datab[];
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main_cin_wire = external_cin_cell.cout;
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result[] = add_sub_cella[].sout;
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END;
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--VALID FILE
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