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For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
10 lines
317 B
Plaintext
Executable File
10 lines
317 B
Plaintext
Executable File
Fitter Status : Successful - Fri Oct 18 15:02:00 2019
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Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
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Revision Name : GR8RAM
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Top-level Entity Name : GR8RAM
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Family : MAX7000S
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Device : EPM7128SLC84-15
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Timing Models : Final
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Total macrocells : 105 / 128 ( 82 % )
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Total pins : 65 / 68 ( 96 % )
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