550 lines
14 KiB
Verilog
550 lines
14 KiB
Verilog
module GR8RAM(C25M, PHI0, nRES, nRESout,
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nIOSEL, nDEVSEL, nIOSTRB,
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SetFW,
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RA, nWE, RD, RDdir,
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SBA, SA, nRCS, nRAS, nCAS, nSWE, DQML, DQMH, RCKE, SD,
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nFCS, FCK, MISO, MOSI);
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/* Clock signals */
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input C25M, PHI0;
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reg PHI0r1, PHI0r2;
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always @(posedge C25M) begin PHI0r1 <= PHI0; PHI0r2 <= PHI0r1; end
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/* Reset/brown-out detect synchronized inputs */
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input nRES;
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reg nRESr0, nRESr;
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always @(posedge C25M) begin nRESr0 <= nRES; nRESr <= nRESr0; end
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/* Long state counter: counts from 0 to $3FFF */
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reg [13:0] LS = 0;
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always @(posedge C25M) begin if (PS==15) LS <= LS+1; end
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/* Init state */
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output reg nRESout = 0;
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reg [2:0] IS = 0;
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always @(posedge C25M) begin
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if (IS==7) nRESout <= 1;
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else if (PS==15) begin
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if (LS==14'h1FCE) IS <= 1; // PC all + load mode
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else if (LS==14'h1FCF) IS <= 4; // AREF pause, SPI select
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else if (LS==14'h1FFA) IS <= 5; // SPI flash command
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else if (LS==14'h1FFF) IS <= 6; // Flash load driver
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else if (LS==14'h3FFF) IS <= 7; // Operating mode
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end
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end
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/* Apple IO area select signals */
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input nIOSEL, nDEVSEL, nIOSTRB;
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/* Apple address bus */
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input [15:0] RA; input nWE;
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/* Apple select signals */
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wire ROMSpecSEL = RA[15:12]==4'hC && RA[11:8]!=4'h0;
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wire BankSpecSEL = RA[3:0]==4'hF;
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wire REGSpecSEL = RA[15:12]==4'hC && RA[11:8]==4'h0 && RA[7] && REGEN;
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wire RAMSpecSEL = REGSpecSEL && RA[3:0]==4'h3 && (~SetLim1M || Addr[23:20]==0) && (~SetLim8M || ~Addr[23]);
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wire AddrHSpecSEL = REGSpecSEL && RA[3:0]==4'h2;
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wire AddrMSpecSEL = REGSpecSEL && RA[3:0]==4'h1;
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wire AddrLSpecSEL = REGSpecSEL && RA[3:0]==4'h0;
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reg ROMSpecSELr, RAMSpecSELr, nWEr;
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wire BankSEL = REGEN && ~nDEVSEL && BankSpecSEL;
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wire RAMSEL = ~nDEVSEL && RAMSpecSELr;
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wire RAMWR = RAMSEL && ~nWEr;
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wire AddrHSEL = REGEN && ~nDEVSEL && AddrHSpecSEL;
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wire AddrMSEL = REGEN && ~nDEVSEL && AddrMSpecSEL;
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wire AddrLSEL = REGEN && ~nDEVSEL && AddrLSpecSEL;
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always @(posedge PHI0) begin
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ROMSpecSELr <= ROMSpecSEL;
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RAMSpecSELr <= RAMSpecSEL;
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nWEr <= nWE;
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end
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/* IOROMEN and REGEN control */
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reg IOROMEN = 0;
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reg REGEN = 0;
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always @(posedge C25M, negedge nRESr) begin
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if (~nRESr) begin
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IOROMEN <= 0;
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REGEN <= 0;
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end else if (PS==8 && ~nIOSTRB && RA[10:0]==11'h7FF) begin
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IOROMEN <= 0;
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end else if (PS==8 && ~nIOSEL) begin
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IOROMEN <= 1;
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REGEN <= 1;
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end
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end
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/* Apple data bus */
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inout [7:0] RD = RDdir ? 8'bZ : RDD[7:0];
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reg [7:0] RDD;
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output RDdir = ~(PHI0r2 && nWE && PHI0 &&
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(~nDEVSEL || ~nIOSEL || (~nIOSTRB && IOROMEN)));
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/* Slinky address registers */
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reg [23:0] Addr = 0;
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reg AddrIncL = 0;
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reg AddrIncM = 0;
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reg AddrIncH = 0;
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always @(posedge C25M, negedge nRESr) begin
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if (~nRESr) begin
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Addr[23:0] <= 24'h000000;
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AddrIncL <= 0;
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AddrIncM <= 0;
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AddrIncH <= 0;
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end else begin
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if (PS==8 && RAMSEL) AddrIncL <= 1;
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else AddrIncL <= 0;
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if (PS==8 && AddrLSEL && ~nWEr) begin
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Addr[7:0] <= RD[7:0];
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AddrIncM <= Addr[7] && ~RD[7];
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end else if (AddrIncL) begin
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Addr[7:0] <= Addr[7:0]+1;
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AddrIncM <= Addr[7:0]==8'hFF;
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end else AddrIncM <= 0;
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if (PS==8 && AddrMSEL && ~nWEr) begin
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Addr[15:8] <= RD[7:0];
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AddrIncH <= Addr[15] && ~RD[7];
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end else if (AddrIncM) begin
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Addr[15:8] <= Addr[15:8]+1;
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AddrIncH <= Addr[15:8]==8'hFF;
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end else AddrIncH <= 0;
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if (PS==8 && AddrHSEL && ~nWEr) begin
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Addr[23:16] <= RD[7:0];
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end else if (AddrIncH) begin
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Addr[23:16] <= Addr[23:16]+1;
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end
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end
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end
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/* ROM bank register */
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reg Bank = 0;
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always @(posedge C25M, negedge nRESr) begin
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if (~nRESr) Bank <= 0;
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else if (PS==8 && BankSEL && ~nWEr) begin
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Bank <= RD[0];
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end
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end
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/* SPI flash */
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output nFCS = ~FCS;
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reg FCS = 0;
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output reg FCK = 0;
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inout MOSI = MOSIOE ? MOSIout : 1'bZ;
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reg MOSIOE = 0;
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reg MOSIout;
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input MISO;
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always @(posedge C25M) begin
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case (PS[3:0])
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0: begin // NOP CKE
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FCK <= 1'b1;
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end 1: begin // ACT
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FCK <= ~(IS==5 || IS==6);
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end 2: begin // RD
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FCK <= 1'b1;
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end 3: begin // NOP CKE
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FCK <= ~(IS==5 || IS==6);
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end 4: begin // NOP CKE
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FCK <= 1'b1;
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end 5: begin // NOP CKE
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FCK <= ~(IS==5 || IS==6);
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end 6: begin // NOP CKE
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FCK <= 1'b1;
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end 7: begin // NOP CKE
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FCK <= ~(IS==5 || IS==6);
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end 8: begin // WR AP
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FCK <= 1'b1;
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end 9: begin // NOP CKE
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FCK <= ~(IS==5);
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end 10: begin // PC all
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FCK <= 1'b1;
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end 11: begin // AREF
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FCK <= ~(IS==5);
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end 12: begin // NOP CKE
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FCK <= 1'b1;
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end 13: begin // NOP CKE
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FCK <= ~(IS==5);
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end 14: begin // NOP CKE
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FCK <= 1'b1;
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end 15: begin // NOP CKE
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FCK <= ~(IS==5);
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end
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endcase
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FCS <= IS==4 || IS==5 || IS==6;
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MOSIOE <= IS==5;
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end
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always @(posedge C25M) begin
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case (PS[3:0])
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1, 2: begin
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case (LS[2:0])
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3'h3: MOSIout <= 1'b0; // Command bit 7
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3'h4: MOSIout <= 1'b0; // Address bit 23
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3'h5: MOSIout <= 1'b0; // Address bit 15
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3'h6: MOSIout <= 1'b0; // Address bit 7
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default MOSIout <= 1'b0;
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endcase
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end 3, 4: begin
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case (LS[2:0])
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3'h3: MOSIout <= 1'b0; // Command bit 6
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3'h4: MOSIout <= 1'b0; // Address bit 22
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3'h5: MOSIout <= SetFW[1]; // Address bit 14
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3'h6: MOSIout <= 1'b0; // Address bit 6
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default MOSIout <= 1'b0;
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endcase
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end 5, 6: begin
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case (LS[2:0])
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3'h3: MOSIout <= 1'b1; // Command bit 5
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3'h4: MOSIout <= 1'b0; // Address bit 21
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3'h5: MOSIout <= SetFW[0]; // Address bit 13
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3'h6: MOSIout <= 1'b0; // Address bit 5
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default MOSIout <= 1'b0;
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endcase
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end 7, 8: begin
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case (LS[2:0])
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3'h3: MOSIout <= 1'b1; // Command bit 4
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3'h4: MOSIout <= 1'b0; // Address bit 20
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3'h5: MOSIout <= 1'b0; // Address bit 12
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3'h6: MOSIout <= 1'b0; // Address bit 4
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default MOSIout <= 1'b0;
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endcase
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end 9, 10: begin
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case (LS[2:0])
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3'h3: MOSIout <= 1'b1; // Command bit 3
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3'h4: MOSIout <= 1'b0; // Address bit 19
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3'h5: MOSIout <= 1'b0; // Address bit 11
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3'h6: MOSIout <= 1'b0; // Address bit 3
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default MOSIout <= 1'b0;
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endcase
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end 11, 12: begin
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case (LS[2:0])
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3'h3: MOSIout <= 1'b0; // Command bit 2
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3'h4: MOSIout <= 1'b0; // Address bit 18
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3'h5: MOSIout <= 1'b0; // Address bit 10
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3'h6: MOSIout <= 1'b0; // Address bit 2
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default MOSIout <= 1'b0;
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endcase
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end 13, 14: begin
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case (LS[2:0])
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3'h3: MOSIout <= 1'b1; // Command bit 1
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3'h4: MOSIout <= 1'b0; // Address bit 16
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3'h5: MOSIout <= 1'b0; // Address bit 9
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3'h6: MOSIout <= 1'b0; // Address bit 1
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default MOSIout <= 1'b0;
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endcase
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end 15, 0: begin
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case (LS[2:0])
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3'h3: MOSIout <= 1'b1; // Command bit 0
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3'h4: MOSIout <= 1'b0; // Address bit 15
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3'h5: MOSIout <= 1'b0; // Address bit 7
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3'h6: MOSIout <= 1'b0; // Address bit 0
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default MOSIout <= 1'b0;
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endcase
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end
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endcase
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end
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input [1:0] SetFW;
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wire SetRF = SetFW[1:0] != 2'b11;
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wire SetLim1M = SetFW[1];
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wire SetLim8M = SetFW[1:0] != 2'b00;
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/* SDRAM data bus */
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inout [7:0] SD = SDOE ? WRD[7:0] : 8'bZ;
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reg [7:0] WRD;
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reg SDOE = 0;
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always @(posedge C25M) begin
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case (PS[3:0])
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0: begin // NOP CKE
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if (IS==6) WRD[7:0] <= { MISO, MOSI, WRD[5:0] };
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else WRD[7:0] <= RD[7:0];
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end 1: begin // ACT
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end 2: begin // RD
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if (IS==6) WRD[7:0] <= { MISO, MOSI, WRD[5:0] };
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else WRD[7:0] <= RD[7:0];
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end 3: begin // NOP CKE
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end 4: begin // NOP CKE
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if (AddrLSpecSEL) RDD[7:0] <= Addr[7:0];
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else if (AddrMSpecSEL) RDD[7:0] <= Addr[15:8];
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else if (AddrHSpecSEL && SetRF) RDD[7:0] <= Addr[23:16];
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else if (AddrHSpecSEL && ~SetRF) RDD[7:0] <= {4'hF, Addr[19:16]};
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else RDD[7:0] <= SD[7:0];
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if (IS==6) WRD[7:0] <= { MISO, MOSI, WRD[5:0] };
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else WRD[7:0] <= RD[7:0];
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end 5: begin // NOP CKE
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end 6: begin // NOP CKE
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if (IS==6) WRD[7:0] <= { MISO, MOSI, WRD[5:0] };
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else WRD[7:0] <= RD[7:0];
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end 7: begin // NOP CKE
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end 8: begin // WR AP
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if (IS==6) WRD[7:0] <= { MISO, MOSI, WRD[5:0] };
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else WRD[7:0] <= RD[7:0];
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end 9: begin // NOP CKE
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end 10: begin // PC all
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if (IS==6) WRD[7:0] <= { MISO, MOSI, WRD[5:0] };
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else WRD[7:0] <= RD[7:0];
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end 11: begin // AREF
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end 12: begin // NOP CKE
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if (IS==6) WRD[7:0] <= { MISO, MOSI, WRD[5:0] };
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else WRD[7:0] <= RD[7:0];
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end 13: begin // NOP CKE
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end 14: begin // NOP CKE
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if (IS==6) WRD[7:0] <= { MISO, MOSI, WRD[5:0] };
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else WRD[7:0] <= RD[7:0];
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end 15: begin // NOP CKE
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end
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endcase
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end
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reg [3:0] PS = 0;
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wire PSStart = PS==0 && PHI0r1 && ~PHI0r2;
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always @(posedge C25M) begin
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if (PSStart) PS <= 1;
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else if (PS==0) PS <= 0;
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else PS <= PS+1;
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end
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/* SDRAM address/command */
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output reg RCKE = 1;
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output reg nRCS = 1;
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output reg nRAS = 1;
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output reg nCAS = 1;
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output reg nSWE = 1;
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wire RefReqd = LS[1:0] == 2'b11;
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always @(posedge C25M) begin
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case (PS[3:0])
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0: begin // NOP CKE / CKD
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RCKE <= PSStart;
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nRCS <= 1'b1;
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nRAS <= 1'b1;
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nCAS <= 1'b1;
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nSWE <= 1'b1;
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SDOE <= 0;
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end 1: begin // ACT CKE / NOP CKD
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RCKE <= IS==6 || (((ROMSpecSELr && nWEr) || RAMSpecSELr) && IS==7);
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nRCS <= ~(IS==6 || (((ROMSpecSELr && nWEr) || RAMSpecSELr) && IS==7));
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nRAS <= 1'b0;
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nCAS <= 1'b1;
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nSWE <= 1'b1;
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SDOE <= 0;
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end 2: begin // RD CKE / NOP CKD
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RCKE <= (ROMSpecSELr || RAMSpecSELr) && nWEr && IS==7;
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nRCS <= ~((ROMSpecSELr || RAMSpecSELr) && nWEr && IS==7);
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nRAS <= 1'b1;
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nCAS <= 1'b0;
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nSWE <= 1'b1;
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SDOE <= 0;
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end 3: begin // NOP CKE / CKD
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RCKE <= (ROMSpecSELr || RAMSpecSELr) && nWEr && IS==7;
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nRCS <= 1'b1;
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nRAS <= 1'b1;
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nCAS <= 1'b1;
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nSWE <= 1'b1;
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SDOE <= 0;
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end 4: begin // NOP CKD
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RCKE <= 1'b0;
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nRCS <= 1'b1;
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nRAS <= 1'b1;
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nCAS <= 1'b1;
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nSWE <= 1'b1;
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SDOE <= 0;
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end 5: begin // NOP CKD
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RCKE <= 1'b0;
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nRCS <= 1'b1;
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nRAS <= 1'b1;
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nCAS <= 1'b1;
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nSWE <= 1'b1;
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SDOE <= 0;
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end 6: begin // NOP CKD
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RCKE <= 1'b0;
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nRCS <= 1'b1;
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nRAS <= 1'b1;
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nCAS <= 1'b1;
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nSWE <= 1'b1;
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SDOE <= 0;
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end 7: begin // NOP CKE / CKD
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RCKE <= IS==6 || (RAMWR && IS==7);
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nRCS <= 1'b1;
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nRAS <= 1'b1;
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nCAS <= 1'b1;
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nSWE <= 1'b1;
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SDOE <= 0;
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end 8: begin // WR AP / NOP CKE (WR AP)
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// NOP CKD / WR AP
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RCKE <= IS==6 || (RAMWR && IS==7);
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nRCS <= ~(IS==6 || (RAMWR && IS==7));
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nRAS <= 1'b1;
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nCAS <= 1'b0;
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nSWE <= 1'b0;
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SDOE <= IS==6 || (RAMWR && IS==7);
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end 9: begin // NOP CKE / NOP CKD
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RCKE <= (IS==6) || ((ROMSpecSELr || RAMSpecSELr) && IS==7) ||
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(RefReqd && (IS==4 || IS==5 || IS==6 || IS==7));
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nRCS <= 1'b1;
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nRAS <= 1'b1;
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nCAS <= 1'b1;
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nSWE <= 1'b1;
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SDOE <= 0;
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end 10: begin // PC all / NOP CKD (PC all)
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RCKE <= (IS==6) || ((ROMSpecSELr || RAMSpecSELr) && IS==7) ||
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(RefReqd && (IS==4 || IS==5 || IS==6 || IS==7));
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nRCS <= ~((IS==6) || ((ROMSpecSELr || RAMSpecSELr) && IS==7) ||
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(RefReqd && (IS==4 || IS==5 || IS==6 || IS==7)));
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nRAS <= 1'b0;
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nCAS <= 1'b1;
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nSWE <= 1'b0;
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SDOE <= 0;
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end 11: begin // AREF / NOP CKD (AREF)
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RCKE <= RefReqd && (IS==4 || IS==5 || IS==6 || IS==7);
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nRCS <= ~(RefReqd && (IS==4 || IS==5 || IS==6 || IS==7));
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nRAS <= 1'b0;
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nCAS <= 1'b0;
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nSWE <= 1'b1;
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SDOE <= 0;
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end 12: begin // NOP CKD
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RCKE <= 1'b0;
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nRCS <= 1'b1;
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nRAS <= 1'b1;
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nCAS <= 1'b1;
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nSWE <= 1'b1;
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SDOE <= 0;
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end 13: begin // NOP CKD
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RCKE <= 1'b0;
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nRCS <= 1'b1;
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nRAS <= 1'b1;
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nCAS <= 1'b1;
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nSWE <= 1'b1;
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SDOE <= 0;
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end 14: begin // NOP CKD
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RCKE <= 1'b0;
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nRCS <= 1'b1;
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nRAS <= 1'b1;
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nCAS <= 1'b1;
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nSWE <= 1'b1;
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SDOE <= 0;
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end 15: begin // NOP CKD
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RCKE <= 1'b0;
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nRCS <= 1'b1;
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nRAS <= 1'b1;
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nCAS <= 1'b1;
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nSWE <= 1'b1;
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SDOE <= 0;
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end
|
|
endcase
|
|
end
|
|
output reg DQML = 1;
|
|
output reg DQMH = 1;
|
|
output reg [1:0] SBA;
|
|
output reg [12:0] SA;
|
|
always @(posedge C25M) begin
|
|
case (PS[3:0])
|
|
0: begin // NOP CKE
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
SBA[1:0] <= 2'b00;
|
|
SA[12:0] <= 13'b0011000100000;
|
|
end 1: begin // ACT
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
if (IS==6) begin
|
|
SBA[1:0] <= { 2'b10 };
|
|
SA[12:0] <= { 10'b0011000100, LS[12:10] };
|
|
end else if (RAMSpecSELr) begin
|
|
SBA[1:0] <= { 1'b0, Addr[23] && SetRF };
|
|
SA[12:0] <= { SetRF ? Addr [22:20] : 3'b000, Addr[19:10]};
|
|
end else begin
|
|
SBA[1:0] <= 2'b10;
|
|
SA[12:0] <= { 10'b0011000100, Bank, RA[11:10] };
|
|
end
|
|
end 2: begin // RD
|
|
if (RAMSpecSELr) begin
|
|
SBA[1:0] <= { 1'b0, Addr[23] && SetRF };
|
|
SA[12:0] <= { 4'b0011, Addr[9:1] };
|
|
DQML <= Addr[0];
|
|
DQMH <= ~Addr[0];
|
|
end else begin
|
|
SBA[1:0] <= 2'b10;
|
|
SA[12:0] <= { 4'b0011, RA[9:1]};
|
|
DQML <= RA[0];
|
|
DQMH <= ~RA[0];
|
|
end
|
|
end 3: begin // NOP CKE
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
SBA[1:0] <= 2'b00;
|
|
SA[12:0] <= 13'b0011000100000;
|
|
end 4: begin // NOP CKE
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
SBA[1:0] <= 2'b00;
|
|
SA[12:0] <= 13'b0011000100000;
|
|
end 5: begin // NOP CKE
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
SBA[1:0] <= 2'b00;
|
|
SA[12:0] <= 13'b0011000100000;
|
|
end 6: begin // NOP CKE
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
SBA[1:0] <= 2'b00;
|
|
SA[12:0] <= 13'b0011000100000;
|
|
end 7: begin // NOP CKE
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
SBA[1:0] <= 2'b00;
|
|
SA[12:0] <= 13'b0011000100000;
|
|
end 8: begin // WR AP
|
|
if (IS==6) begin
|
|
SBA[1:0] <= 2'b10;
|
|
SA[12:0] <= { 4'b0011, LS[9:1] };
|
|
DQML <= LS[0];
|
|
DQMH <= ~LS[0];
|
|
end else begin
|
|
SBA[1:0] <= { 1'b0, Addr[23] && SetLim8M && SetRF };
|
|
SA[12:0] <= { 4'b0011, Addr[9:1] };
|
|
DQML <= Addr[0];
|
|
DQMH <= ~Addr[0];
|
|
end
|
|
end 9: begin // NOP CKE
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
SBA[1:0] <= 2'b00;
|
|
SA[12:0] <= 13'b0011000100000;
|
|
end 10: begin // PC all
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
SBA[1:0] <= 2'b00;
|
|
SA[12:0] <= 13'b0011000100000;
|
|
end 11: begin // AREF / load mode
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
SBA[1:0] <= 2'b00;
|
|
SA[12:0] <= 13'b0001000100000;
|
|
end 12: begin // NOP CKE
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
SBA[1:0] <= 2'b00;
|
|
SA[12:0] <= 13'b0011000100000;
|
|
end 13: begin // NOP CKE
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
SBA[1:0] <= 2'b00;
|
|
SA[12:0] <= 13'b0011000100000;
|
|
end 14: begin // NOP CKE
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
SBA[1:0] <= 2'b00;
|
|
SA[12:0] <= 13'b0011000100000;
|
|
end 15: begin // NOP CKE
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
SBA[1:0] <= 2'b00;
|
|
SA[12:0] <= 13'b0011000100000;
|
|
end
|
|
endcase
|
|
end
|
|
endmodule
|