mirror of
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GW4203C.1.0 RC3
This commit is contained in:
Zane Kaminski
parent
1a345d9d5e
commit
466f7ebf17
CPLD
LCMXO2-1200HC-NODHGR
RAM2E_LCMXO2_1200HC_tcl.html
impl1
RAM2E_LCMXO2_1200HC_impl1.altRAM2E_LCMXO2_1200HC_impl1.areasrrRAM2E_LCMXO2_1200HC_impl1.bgnRAM2E_LCMXO2_1200HC_impl1.ediRAM2E_LCMXO2_1200HC_impl1.jedRAM2E_LCMXO2_1200HC_impl1.mrpRAM2E_LCMXO2_1200HC_impl1.padRAM2E_LCMXO2_1200HC_impl1.prfRAM2E_LCMXO2_1200HC_impl1.srrRAM2E_LCMXO2_1200HC_impl1_bgn.htmlRAM2E_LCMXO2_1200HC_impl1_cck.rptRAM2E_LCMXO2_1200HC_impl1_mrp.htmlRAM2E_LCMXO2_1200HC_impl1_pad.htmlRAM2E_LCMXO2_1200HC_impl1_par.htmlRAM2E_LCMXO2_1200HC_impl1_scck.rptRAM2E_LCMXO2_1200HC_impl1_summary.htmlRAM2E_LCMXO2_1200HC_impl1_synplify.htmlhdla_gen_hierarchy.html
promote.xmlLCMXO2-1200HC
RAM2E_LCMXO2_1200HC_tcl.html
impl1
RAM2E_LCMXO2_1200HC_impl1.altRAM2E_LCMXO2_1200HC_impl1.areasrrRAM2E_LCMXO2_1200HC_impl1.bgnRAM2E_LCMXO2_1200HC_impl1.ediRAM2E_LCMXO2_1200HC_impl1.jedRAM2E_LCMXO2_1200HC_impl1.mrpRAM2E_LCMXO2_1200HC_impl1.padRAM2E_LCMXO2_1200HC_impl1.prfRAM2E_LCMXO2_1200HC_impl1.srrRAM2E_LCMXO2_1200HC_impl1_bgn.htmlRAM2E_LCMXO2_1200HC_impl1_cck.rptRAM2E_LCMXO2_1200HC_impl1_mrp.htmlRAM2E_LCMXO2_1200HC_impl1_pad.htmlRAM2E_LCMXO2_1200HC_impl1_par.htmlRAM2E_LCMXO2_1200HC_impl1_scck.rptRAM2E_LCMXO2_1200HC_impl1_summary.htmlRAM2E_LCMXO2_1200HC_impl1_synplify.htmlhdla_gen_hierarchy.html
promote.xmlLCMXO2-640HC-NODHGR
RAM2E_LCMXO2_640HC_tcl.html
impl1
RAM2E_LCMXO2_640HC_impl1.altRAM2E_LCMXO2_640HC_impl1.areasrrRAM2E_LCMXO2_640HC_impl1.bgnRAM2E_LCMXO2_640HC_impl1.ediRAM2E_LCMXO2_640HC_impl1.jedRAM2E_LCMXO2_640HC_impl1.mrpRAM2E_LCMXO2_640HC_impl1.padRAM2E_LCMXO2_640HC_impl1.prfRAM2E_LCMXO2_640HC_impl1.srrRAM2E_LCMXO2_640HC_impl1_bgn.htmlRAM2E_LCMXO2_640HC_impl1_cck.rptRAM2E_LCMXO2_640HC_impl1_mrp.htmlRAM2E_LCMXO2_640HC_impl1_pad.htmlRAM2E_LCMXO2_640HC_impl1_par.htmlRAM2E_LCMXO2_640HC_impl1_scck.rptRAM2E_LCMXO2_640HC_impl1_summary.htmlRAM2E_LCMXO2_640HC_impl1_synplify.htmlhdla_gen_hierarchy.html
promote.xmlLCMXO2-640HC
RAM2E_LCMXO2_640HC_tcl.html
impl1
RAM2E_LCMXO2_640HC_impl1.altRAM2E_LCMXO2_640HC_impl1.areasrrRAM2E_LCMXO2_640HC_impl1.bgnRAM2E_LCMXO2_640HC_impl1.ediRAM2E_LCMXO2_640HC_impl1.jedRAM2E_LCMXO2_640HC_impl1.mrpRAM2E_LCMXO2_640HC_impl1.padRAM2E_LCMXO2_640HC_impl1.prfRAM2E_LCMXO2_640HC_impl1.srrRAM2E_LCMXO2_640HC_impl1_bgn.htmlRAM2E_LCMXO2_640HC_impl1_cck.rptRAM2E_LCMXO2_640HC_impl1_mrp.htmlRAM2E_LCMXO2_640HC_impl1_pad.htmlRAM2E_LCMXO2_640HC_impl1_par.htmlRAM2E_LCMXO2_640HC_impl1_scck.rptRAM2E_LCMXO2_640HC_impl1_summary.htmlRAM2E_LCMXO2_640HC_impl1_synplify.htmlhdla_gen_hierarchy.html
promote.xmlMAXII-NODHGR/output_files
RAM2E.asm.rptRAM2E.doneRAM2E.fit.rptRAM2E.fit.summaryRAM2E.flow.rptRAM2E.map.rptRAM2E.map.summaryRAM2E.pofRAM2E.sta.rptRAM2E.sta.summaryRAM2E.svf
MAXII/output_files
70
CPLD/LCMXO2-1200HC-NODHGR/RAM2E_LCMXO2_1200HC_tcl.html
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70
CPLD/LCMXO2-1200HC-NODHGR/RAM2E_LCMXO2_1200HC_tcl.html
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<HTML>
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<HEAD><TITLE>Lattice TCL Log</TITLE>
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<STYLE TYPE="text/css">
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<!--
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body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
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h1 {
font-weight: bold;
margin-top: 24px;
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border-bottom: 3px solid #000; font-size: 1em;
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h2 {
font-weight: bold;
margin-top: 18px;
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font-size: 0.90em;
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h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
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p {
font-size:78%;
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margin-top: 4px;
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a {
color:#013C9A;
text-decoration:none;
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a:visited {
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a:hover, a:active {
text-decoration:underline;
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</HEAD>
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<PRE><A name="pn240608044452"></A><B><U><big>pn240608044452</big></U></B>
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#Start recording tcl command: 6/7/2024 20:49:43
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#Project Location: //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC-NODHGR; Project name: RAM2E_LCMXO2_1200HC
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prj_project open "//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC-NODHGR/RAM2E_LCMXO2_1200HC.ldf"
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prj_run Export -impl impl1 -forceAll
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#Stop recording: 6/8/2024 04:44:52
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</PRE></FONT>
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</BODY>
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</HTML>
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@ -1,6 +1,6 @@
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NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
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NOTE All Rights Reserved *
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NOTE DATE CREATED: Fri Jun 07 20:50:28 2024 *
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NOTE DATE CREATED: Fri Jul 12 16:08:52 2024 *
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NOTE DESIGN NAME: RAM2E *
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NOTE DEVICE NAME: LCMXO2-1200HC-4TQFP100 *
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NOTE PIN ASSIGNMENTS *
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@ -1,7 +1,7 @@
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----------------------------------------------------------------------
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Report for cell RAM2E.verilog
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Register bits: 125 of 1280 (10%)
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Register bits: 124 of 1280 (10%)
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PIC Latch: 0
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I/O cells: 70
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Cell usage:
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@ -9,7 +9,7 @@ I/O cells: 70
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BB 8 100.0
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CCU2D 9 100.0
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EFB 1 100.0
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FD1P3AX 58 100.0
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FD1P3AX 57 100.0
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FD1P3IX 1 100.0
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FD1S3AX 31 100.0
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FD1S3AY 4 100.0
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@ -22,7 +22,8 @@ I/O cells: 70
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OFS1P3BX 6 100.0
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OFS1P3DX 12 100.0
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OFS1P3IX 3 100.0
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ORCALUT4 275 100.0
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ORCALUT4 268 100.0
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PFUMX 10 100.0
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PUR 1 100.0
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VHI 3 100.0
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VLO 3 100.0
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@ -30,23 +31,24 @@ SUB MODULES
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RAM2E_UFM 1 100.0
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REFB 1 100.0
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TOTAL 494
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TOTAL 496
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----------------------------------------------------------------------
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Report for cell RAM2E_UFM.netlist
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Instance path: ram2e_ufm
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Cell usage:
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cell count Res Usage(%)
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EFB 1 100.0
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FD1P3AX 29 50.0
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FD1P3AX 29 50.9
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FD1P3IX 1 100.0
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FD1S3IX 1 11.1
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ORCALUT4 268 97.5
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ORCALUT4 260 97.0
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PFUMX 10 100.0
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VHI 2 66.7
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VLO 2 66.7
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SUB MODULES
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REFB 1 100.0
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TOTAL 305
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TOTAL 307
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----------------------------------------------------------------------
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Report for cell REFB.netlist
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Instance path: ram2e_ufm.ufmefb
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@ -4,10 +4,10 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
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Fri Jun 07 20:50:24 2024
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Fri Jul 12 16:08:44 2024
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Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC-NODHGR -w -jedec -gui RAM2E_LCMXO2_1200HC_impl1.ncd RAM2E_LCMXO2_1200HC_impl1.prf
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Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC-NODHGR -w -jedec -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC-NODHGR/promote.xml RAM2E_LCMXO2_1200HC_impl1.ncd RAM2E_LCMXO2_1200HC_impl1.prf
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Loading design for application Bitgen from file RAM2E_LCMXO2_1200HC_impl1.ncd.
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Design name: RAM2E
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@ -82,5 +82,5 @@ Available General Purpose Flash Memory: 511 Pages (Page 0 to Page 510).
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Initialized UFM Pages: 321 Pages (Page 190 to Page 510).
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Total CPU Time: 3 secs
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Total REAL Time: 4 secs
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Total REAL Time: 8 secs
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Peak Memory Usage: 275 MB
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -10,25 +10,26 @@ Command line: map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 4 -oc Commercial
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RAM2E_LCMXO2_1200HC_impl1.prf -mp RAM2E_LCMXO2_1200HC_impl1.mrp -lpf //Mac/
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iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC-NODHGR/impl1/RAM2E_LCMXO2_1200HC_impl
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1_synplify.lpf -lpf //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf -c 0
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-gui
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-gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC-NODHGR/promote.xml
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Target Vendor: LATTICE
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Target Device: LCMXO2-1200HCTQFP100
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Target Performance: 4
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Mapper: xo2c00, version: Diamond (64-bit) 3.11.3.469
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Mapped on: 06/07/24 20:50:05
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Mapped on: 07/12/24 16:07:54
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Design Summary
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--------------
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Number of registers: 125 out of 1520 (8%)
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PFU registers: 103 out of 1280 (8%)
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Number of registers: 124 out of 1520 (8%)
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PFU registers: 102 out of 1280 (8%)
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PIO registers: 22 out of 240 (9%)
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Number of SLICEs: 148 out of 640 (23%)
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SLICEs as Logic/ROM: 148 out of 640 (23%)
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Number of SLICEs: 145 out of 640 (23%)
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SLICEs as Logic/ROM: 145 out of 640 (23%)
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SLICEs as RAM: 0 out of 480 (0%)
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SLICEs as Carry: 9 out of 640 (1%)
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Number of LUT4s: 296 out of 1280 (23%)
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Number used as logic LUTs: 278
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Number of LUT4s: 289 out of 1280 (23%)
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Number used as logic LUTs: 271
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Number used as distributed RAM: 0
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Number used as ripple logic: 18
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Number used as shift registers: 0
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@ -58,53 +59,54 @@ Design Summary
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2. Number of logic LUT4s does not include count of distributed RAM and
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ripple logic.
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Number of clocks: 2
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Net C14M_c: 85 loads, 63 rising, 22 falling (Driver: PIO C14M )
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Net PHI1_c: 3 loads, 0 rising, 3 falling (Driver: PIO PHI1 )
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Net C14M_c: 84 loads, 62 rising, 22 falling (Driver: PIO C14M )
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Page 1
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Design: RAM2E Date: 06/07/24 20:50:05
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Design: RAM2E Date: 07/12/24 16:07:54
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Design Summary (cont)
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---------------------
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Net PHI1_c: 3 loads, 0 rising, 3 falling (Driver: PIO PHI1 )
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Number of Clock Enables: 13
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Net N_117_i: 2 loads, 0 LSLICEs
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Net RWBank14: 11 loads, 11 LSLICEs
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Net N_347_i: 2 loads, 0 LSLICEs
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Net RWBank14: 10 loads, 10 LSLICEs
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Net ram2e_ufm/wb_adr_0_sqmuxa_1_i: 1 loads, 1 LSLICEs
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Net un9_VOE_0_a2_0_a2: 1 loads, 1 LSLICEs
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Net un6_DOEEN_0_a2_0_a2: 2 loads, 2 LSLICEs
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Net ram2e_ufm/un1_wb_adr_0_sqmuxa_2_i[0]: 8 loads, 8 LSLICEs
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Net ram2e_ufm/un1_wb_cyc_stb_0_sqmuxa_1_i[0]: 1 loads, 1 LSLICEs
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Net ram2e_ufm/N_111: 1 loads, 1 LSLICEs
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Net ram2e_ufm/N_104: 4 loads, 4 LSLICEs
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Net ram2e_ufm/N_98: 1 loads, 1 LSLICEs
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Net un1_CKE48_0_i: 6 loads, 6 LSLICEs
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Net N_389_i: 2 loads, 0 LSLICEs
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Net ram2e_ufm/N_63: 1 loads, 1 LSLICEs
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Net ram2e_ufm/un1_wb_adr_0_sqmuxa_2_i_0[0]: 8 loads, 8 LSLICEs
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Net ram2e_ufm/un1_CmdBitbangMXO212_1_i[0]: 1 loads, 1 LSLICEs
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Net ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0[0]: 4 loads, 4 LSLICEs
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Net ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0[0]: 1 loads, 1 LSLICEs
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Net un9_VOE_0_a2: 1 loads, 1 LSLICEs
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Net un1_CKE48_i: 6 loads, 6 LSLICEs
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Net N_346_i: 2 loads, 0 LSLICEs
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Net Vout3: 8 loads, 0 LSLICEs
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Number of LSRs: 8
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Net N_148: 2 loads, 2 LSLICEs
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Net N_430_i: 2 loads, 0 LSLICEs
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Number of LSRs: 9
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Net un1_CS_0_sqmuxa_i: 2 loads, 2 LSLICEs
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Net ram2e_ufm.wb_rst13: 2 loads, 0 LSLICEs
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Net RC7: 2 loads, 2 LSLICEs
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Net S[2]: 2 loads, 2 LSLICEs
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Net S[1]: 1 loads, 1 LSLICEs
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Net ram2e_ufm/wb_rst: 1 loads, 0 LSLICEs
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Net ram2e_ufm/nRWE_0_i_o3_RNIP8E61: 1 loads, 1 LSLICEs
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Net N_530: 1 loads, 0 LSLICEs
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Net N_301_i: 1 loads, 1 LSLICEs
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Net ram2e_ufm/wb_rst6_i: 1 loads, 1 LSLICEs
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Net N_523_1: 1 loads, 0 LSLICEs
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Net N_727_0: 1 loads, 1 LSLICEs
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Net RATc_i: 1 loads, 1 LSLICEs
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Number of nets driven by tri-state buffers: 0
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Top 10 highest fanout non-clock nets:
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Net S[2]: 60 loads
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Net S[3]: 48 loads
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Net S[1]: 46 loads
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Net S[0]: 31 loads
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Net FS[11]: 24 loads
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Net FS[10]: 23 loads
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Net FS[12]: 23 loads
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Net FS[9]: 23 loads
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Net FS[13]: 21 loads
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Net FS[8]: 18 loads
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Net S[2]: 51 loads
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Net S[1]: 44 loads
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Net S[3]: 40 loads
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Net S[0]: 32 loads
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Net FS[8]: 29 loads
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Net FS[9]: 26 loads
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Net FS[10]: 25 loads
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Net FS[11]: 23 loads
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Net FS[13]: 20 loads
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Net ram2e_ufm.wb_rst13: 17 loads
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@ -124,18 +126,18 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
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Controller, GSR, Hardened User SPI Port, Hardened Primary User I2C Port.
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Functionality is restored after the Flash Memory (UFM/Configuration)
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Interface is disabled using Disable Configuration Interface command 0x26
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followed by Bypass command 0xFF.
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WARNING - map: IO buffer missing for top level port nWE80...logic will be
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Page 2
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Design: RAM2E Date: 06/07/24 20:50:05
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Design: RAM2E Date: 07/12/24 16:07:54
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Design Errors/Warnings (cont)
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-----------------------------
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followed by Bypass command 0xFF.
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WARNING - map: IO buffer missing for top level port nWE80...logic will be
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discarded.
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IO (PIO) Attributes
|
||||
@ -190,19 +192,19 @@ IO (PIO) Attributes
|
||||
| RAout[2] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RAout[1] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RAout[0] | OUTPUT | LVCMOS33 | |
|
||||
|
||||
Page 3
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 06/07/24 20:50:05
|
||||
Design: RAM2E Date: 07/12/24 16:07:54
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RAout[0] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| BA[1] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| BA[0] | OUTPUT | LVCMOS33 | OUT |
|
||||
@ -256,19 +258,19 @@ IO (PIO) Attributes (cont)
|
||||
| Din[7] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[6] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[5] | INPUT | LVCMOS33 | |
|
||||
|
||||
Page 4
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 06/07/24 20:50:05
|
||||
Design: RAM2E Date: 07/12/24 16:07:54
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[5] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[4] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[3] | INPUT | LVCMOS33 | |
|
||||
@ -322,18 +324,18 @@ Signal FS_s_0_COUT[15] undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/CFGWAKE undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/wbc_ufm_irq undriven or does not drive anything -
|
||||
clipped.
|
||||
Signal ram2e_ufm/ufmefb/TCOC undriven or does not drive anything - clipped.
|
||||
|
||||
Page 5
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 06/07/24 20:50:05
|
||||
Design: RAM2E Date: 07/12/24 16:07:54
|
||||
|
||||
Removed logic (cont)
|
||||
--------------------
|
||||
clipped.
|
||||
Signal ram2e_ufm/ufmefb/TCOC undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/TCINT undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIIRQO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPICSNEN undriven or does not drive anything - clipped.
|
||||
@ -388,18 +390,18 @@ Signal ram2e_ufm/ufmefb/PLLCLKO undriven or does not drive anything - clipped.
|
||||
Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped.
|
||||
Signal N_1 undriven or does not drive anything - clipped.
|
||||
Block RefReq.CN was optimized away.
|
||||
Block RDOE_RNIAM8C was optimized away.
|
||||
Block nCASout.CN was optimized away.
|
||||
|
||||
Page 6
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 06/07/24 20:50:05
|
||||
Design: RAM2E Date: 07/12/24 16:07:54
|
||||
|
||||
Removed logic (cont)
|
||||
--------------------
|
||||
Block RDOE_RNIAM8C was optimized away.
|
||||
Block nCASout.CN was optimized away.
|
||||
Block ram2e_ufm/ufmefb/VCC was optimized away.
|
||||
Block ram2e_ufm/ufmefb/GND was optimized away.
|
||||
|
||||
@ -452,14 +454,78 @@ Instance Name: ram2e_ufm/ufmefb/EFBInst_0
|
||||
Run Time and Memory Usage
|
||||
-------------------------
|
||||
|
||||
Total CPU Time: 0 secs
|
||||
Total REAL Time: 2 secs
|
||||
Peak Memory Usage: 64 MB
|
||||
|
||||
Total CPU Time: 1 secs
|
||||
Total REAL Time: 8 secs
|
||||
|
||||
Page 7
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 07/12/24 16:07:54
|
||||
|
||||
Run Time and Memory Usage (cont)
|
||||
--------------------------------
|
||||
Peak Memory Usage: 65 MB
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Page 8
|
||||
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
|
||||
@ -6,7 +6,7 @@ Performance Grade: 4
|
||||
PACKAGE: TQFP100
|
||||
Package Status: Final Version 1.42
|
||||
|
||||
Fri Jun 07 20:50:15 2024
|
||||
Fri Jul 12 16:08:20 2024
|
||||
|
||||
Pinout by Port Name:
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
@ -311,5 +311,5 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Fri Jun 07 20:50:20 2024
|
||||
Fri Jul 12 16:08:32 2024
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
SCHEMATIC START ;
|
||||
# map: version Diamond (64-bit) 3.11.3.469 -- WARNING: Map write only section -- Fri Jun 07 20:50:06 2024
|
||||
# map: version Diamond (64-bit) 3.11.3.469 -- WARNING: Map write only section -- Fri Jul 12 16:07:57 2024
|
||||
|
||||
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
|
||||
LOCATE COMP "RD[0]" SITE "36" ;
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
#OS: Windows 8 6.2
|
||||
#Hostname: ZANEMACWIN11
|
||||
|
||||
# Fri Jun 7 20:49:56 2024
|
||||
# Fri Jul 12 16:07:01 2024
|
||||
|
||||
#Implementation: impl1
|
||||
|
||||
@ -52,6 +52,7 @@ Synopsys Verilog Compiler, Version comp2018q2p1, Build 461R, Built Apr 1 2019 0
|
||||
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC-NODHGR\REFB.v" (library work)
|
||||
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\DHGR-OFF.v" (library work)
|
||||
Verilog syntax check successful!
|
||||
File \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v changed - recompiling
|
||||
Selecting top level module RAM2E
|
||||
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
|
||||
Running optimization stage 1 on VHI .......
|
||||
@ -77,12 +78,12 @@ Running optimization stage 2 on EFB .......
|
||||
Running optimization stage 2 on VLO .......
|
||||
Running optimization stage 2 on VHI .......
|
||||
|
||||
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)
|
||||
At c_ver Exit (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
Process took 0h:00m:05s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Fri Jun 7 20:49:57 2024
|
||||
# Fri Jul 12 16:07:10 2024
|
||||
|
||||
###########################################################]
|
||||
|
||||
@ -102,13 +103,14 @@ Implementation : impl1
|
||||
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
File \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC-NODHGR\impl1\synwork\layer0.srs changed - recompiling
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Fri Jun 7 20:49:57 2024
|
||||
# Fri Jul 12 16:07:11 2024
|
||||
|
||||
###########################################################]
|
||||
|
||||
@ -118,12 +120,12 @@ For a summary of runtime and memory usage for all design units, please see file:
|
||||
|
||||
@END
|
||||
|
||||
At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
|
||||
At c_hdl Exit (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
Process took 0h:00m:08s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Fri Jun 7 20:49:57 2024
|
||||
# Fri Jul 12 16:07:11 2024
|
||||
|
||||
###########################################################]
|
||||
|
||||
@ -143,18 +145,17 @@ Database state : \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC-NODHGR\impl1\synwor
|
||||
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
File \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC-NODHGR\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_comp.srs changed - recompiling
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Fri Jun 7 20:49:58 2024
|
||||
# Fri Jul 12 16:07:14 2024
|
||||
|
||||
###########################################################]
|
||||
Premap Report
|
||||
|
||||
# Fri Jun 7 20:49:58 2024
|
||||
# Fri Jul 12 16:07:14 2024
|
||||
|
||||
|
||||
Copyright (C) 1994-2018 Synopsys, Inc.
|
||||
@ -199,7 +200,7 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h
|
||||
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":21:4:21:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
|
||||
@N: MH105 |UMR3 is only supported for HAPS-80.
|
||||
@N: MH105 |UMR3 is only supported for HAPS-80.
|
||||
@N: BN115 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":140:9:140:12|Removing instance dhgr (in view: work.RAM2E(verilog)) of type view:work.DHGR(verilog) because it does not drive other instances.
|
||||
@N: BN115 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":136:9:136:12|Removing instance dhgr (in view: work.RAM2E(verilog)) of type view:work.DHGR(verilog) because it does not drive other instances.
|
||||
syn_allowed_resources : blockrams=7 set on top level netlist RAM2E
|
||||
|
||||
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
|
||||
@ -212,7 +213,7 @@ Clock Summary
|
||||
Start Requested Requested Clock Clock Clock
|
||||
Level Clock Frequency Period Type Group Load
|
||||
-----------------------------------------------------------------------------------------------
|
||||
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 121
|
||||
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 120
|
||||
|
||||
0 - System 100.0 MHz 10.000 system system_clkgroup 0
|
||||
|
||||
@ -227,7 +228,7 @@ Clock Load Summary
|
||||
Clock Source Clock Pin Non-clock Pin Non-clock Pin
|
||||
Clock Load Pin Seq Example Seq Example Comb Example
|
||||
--------------------------------------------------------------------------------------------
|
||||
C14M 121 C14M(port) RAT.C - un1_C14M.I[0](inv)
|
||||
C14M 120 C14M(port) RAT.C - un1_C14M.I[0](inv)
|
||||
|
||||
System 0 - - - -
|
||||
|
||||
@ -247,14 +248,14 @@ Number of ICG latches not removed: 0
|
||||
|
||||
#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
|
||||
|
||||
2 non-gated/non-generated clock tree(s) driving 125 clock pin(s) of sequential element(s)
|
||||
2 non-gated/non-generated clock tree(s) driving 124 clock pin(s) of sequential element(s)
|
||||
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
|
||||
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
|
||||
|
||||
=========================== Non-Gated/Non-Generated Clocks ============================
|
||||
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
|
||||
---------------------------------------------------------------------------------------
|
||||
@KP:ckid0_0 C14M port 121 PHI1r
|
||||
@KP:ckid0_0 C14M port 120 PHI1r
|
||||
@KP:ckid0_1 PHI1 Unconstrained_port 4 RC[2:0]
|
||||
=======================================================================================
|
||||
|
||||
@ -264,27 +265,25 @@ Clock Tree ID Driving Element Drive Element Type Fanout Sample I
|
||||
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
|
||||
Finished Pre Mapping Phase.
|
||||
|
||||
Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
|
||||
Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
|
||||
|
||||
|
||||
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
|
||||
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
|
||||
|
||||
None
|
||||
None
|
||||
|
||||
Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
|
||||
Finished constraint checker (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
|
||||
|
||||
Pre-mapping successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB)
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Fri Jun 7 20:49:59 2024
|
||||
Process took 0h:00m:04s realtime, 0h:00m:01s cputime
|
||||
# Fri Jul 12 16:07:19 2024
|
||||
|
||||
###########################################################]
|
||||
Map & Optimize Report
|
||||
|
||||
# Fri Jun 7 20:50:00 2024
|
||||
# Fri Jul 12 16:07:22 2024
|
||||
|
||||
|
||||
Copyright (C) 1994-2018 Synopsys, Inc.
|
||||
@ -313,18 +312,18 @@ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:0
|
||||
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
|
||||
|
||||
|
||||
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
|
||||
Mapper Initialization Complete (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
|
||||
|
||||
|
||||
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
|
||||
Start loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
|
||||
|
||||
|
||||
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
|
||||
Finished loading timing files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
|
||||
|
||||
@N: MF284 |Setting synthesis effort to medium for the design
|
||||
|
||||
|
||||
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
|
||||
Starting Optimization and Mapping (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
|
||||
|
||||
|
||||
Available hyper_sources - for debug and ip models
|
||||
@ -333,61 +332,61 @@ Available hyper_sources - for debug and ip models
|
||||
@N: FX493 |Applying initial value "00000000" on instance RWBank[7:0].
|
||||
@N: FX493 |Applying initial value "0000" on instance S[3:0].
|
||||
|
||||
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)
|
||||
Finished RTL optimizations (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)
|
||||
|
||||
@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":14:23:14:28|Found counter in view:work.RAM2E(verilog) instance FS[15:0]
|
||||
|
||||
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 142MB)
|
||||
Starting factoring (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 142MB)
|
||||
|
||||
|
||||
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
|
||||
Finished factoring (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
|
||||
|
||||
|
||||
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
|
||||
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
|
||||
|
||||
|
||||
Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
|
||||
Starting Early Timing Optimization (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
|
||||
|
||||
|
||||
Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
|
||||
Finished Early Timing Optimization (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
|
||||
|
||||
|
||||
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
|
||||
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
|
||||
|
||||
|
||||
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
|
||||
Finished preparing to map (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 147MB)
|
||||
|
||||
|
||||
Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
|
||||
Finished technology mapping (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
|
||||
|
||||
Pass CPU time Worst Slack Luts / Registers
|
||||
------------------------------------------------------------
|
||||
1 0h:00m:01s 6.90ns 281 / 125
|
||||
1 0h:00m:01s 6.90ns 280 / 124
|
||||
|
||||
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
|
||||
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
|
||||
|
||||
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
|
||||
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":171:4:171:9|Boundary register BA_1_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
||||
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":171:4:171:9|Boundary register BA_0_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
||||
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":168:4:168:9|Boundary register BA_1_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
||||
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":168:4:168:9|Boundary register BA_0_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
||||
|
||||
Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 158MB peak: 160MB)
|
||||
Finished restoring hierarchy (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:01s; Memory used current: 158MB peak: 160MB)
|
||||
|
||||
|
||||
Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 122MB peak: 160MB)
|
||||
Start Writing Netlists (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:01s; Memory used current: 122MB peak: 160MB)
|
||||
|
||||
Writing Analyst data base \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC-NODHGR\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_m.srm
|
||||
|
||||
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 158MB peak: 160MB)
|
||||
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:02s; Memory used current: 157MB peak: 160MB)
|
||||
|
||||
Writing EDIF Netlist and constraint files
|
||||
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC-NODHGR\impl1\RAM2E_LCMXO2_1200HC_impl1.edi
|
||||
N-2018.03L-SP1-1
|
||||
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
|
||||
|
||||
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 162MB peak: 164MB)
|
||||
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:02s; Memory used current: 161MB peak: 163MB)
|
||||
|
||||
|
||||
Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 164MB)
|
||||
Start final timing analysis (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:03s; Memory used current: 160MB peak: 163MB)
|
||||
|
||||
@W: MT246 :"\\mac\icloud\repos\ram2e\cpld\lcmxo2-1200hc-nodhgr\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
|
||||
@N: MT615 |Found clock C14M with period 69.84ns
|
||||
@ -395,7 +394,7 @@ Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:0
|
||||
|
||||
|
||||
##### START OF TIMING REPORT #####[
|
||||
# Timing Report written on Fri Jun 7 20:50:03 2024
|
||||
# Timing Report written on Fri Jul 12 16:07:38 2024
|
||||
#
|
||||
|
||||
|
||||
@ -420,9 +419,9 @@ Worst slack in design: 6.897
|
||||
Requested Estimated Requested Estimated Clock Clock
|
||||
Starting Clock Frequency Frequency Period Period Slack Type Group
|
||||
----------------------------------------------------------------------------------------------------------------------
|
||||
C14M 14.3 MHz 112.1 MHz 69.841 8.918 31.599 declared default_clkgroup
|
||||
C14M 14.3 MHz 120.3 MHz 69.841 8.314 31.675 declared default_clkgroup
|
||||
RAM2E|PHI1 100.0 MHz 322.2 MHz 10.000 3.103 6.897 inferred Inferred_clkgroup_0
|
||||
System 100.0 MHz NA 10.000 NA 67.088 system system_clkgroup
|
||||
System 100.0 MHz NA 10.000 NA 66.719 system system_clkgroup
|
||||
======================================================================================================================
|
||||
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
|
||||
|
||||
@ -437,9 +436,9 @@ Clocks | rise to rise | fall to fall | rise
|
||||
----------------------------------------------------------------------------------------------------------------
|
||||
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
|
||||
----------------------------------------------------------------------------------------------------------------
|
||||
System C14M | 69.841 67.088 | No paths - | No paths - | No paths -
|
||||
System C14M | 69.841 66.719 | No paths - | No paths - | No paths -
|
||||
C14M System | 69.841 68.797 | No paths - | No paths - | No paths -
|
||||
C14M C14M | 69.841 60.923 | No paths - | 34.920 31.599 | No paths -
|
||||
C14M C14M | 69.841 61.527 | No paths - | 34.920 31.675 | No paths -
|
||||
RAM2E|PHI1 C14M | No paths - | No paths - | No paths - | Diff grp -
|
||||
RAM2E|PHI1 RAM2E|PHI1 | No paths - | 10.000 6.897 | No paths - | No paths -
|
||||
================================================================================================================
|
||||
@ -468,10 +467,10 @@ Starting Points with Worst Slack
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
---------------------------------------------------------------------------
|
||||
S[2] C14M FD1S3AX Q S[2] 1.366 31.599
|
||||
S[3] C14M FD1S3AX Q S[3] 1.345 31.619
|
||||
S[1] C14M FD1S3AX Q S[1] 1.344 31.800
|
||||
S[0] C14M FD1S3AX Q S[0] 1.305 31.838
|
||||
S[2] C14M FD1S3AX Q S[2] 1.353 31.675
|
||||
S[3] C14M FD1S3AX Q S[3] 1.337 31.691
|
||||
S[0] C14M FD1S3AX Q S[0] 1.319 32.182
|
||||
S[1] C14M FD1S3AX Q S[1] 1.344 32.656
|
||||
RA[0] C14M FD1P3AX Q RA[0] 1.108 33.707
|
||||
RA[3] C14M FD1P3AX Q RA[3] 1.108 33.707
|
||||
RA[1] C14M FD1P3AX Q RA[1] 1.044 33.771
|
||||
@ -484,21 +483,21 @@ RA[5] C14M FD1P3AX Q RA[5] 1.044 33.771
|
||||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
-----------------------------------------------------------------------------------
|
||||
VOE_i_0io C14M OFS1P3IX CD N_530 34.118 31.599
|
||||
VOE_i_0io C14M OFS1P3IX D VOE_ic_i 35.009 31.800
|
||||
Vout_0io[0] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[1] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[2] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[3] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[4] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[5] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[6] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[7] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
===================================================================================
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------------
|
||||
VOE_i_0io C14M OFS1P3IX CD N_523_1 34.118 31.675
|
||||
RAT C14M FD1S3IX CD RATc_i 34.118 32.147
|
||||
Vout_0io[0] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[1] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[2] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[3] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[4] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[5] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[6] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[7] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
==================================================================================
|
||||
|
||||
|
||||
|
||||
@ -512,9 +511,9 @@ Path information for path number 1:
|
||||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
= Required time: 34.118
|
||||
|
||||
- Propagation time: 2.519
|
||||
- Propagation time: 2.442
|
||||
- Clock delay at starting point: 0.000 (ideal)
|
||||
= Slack (non-critical) : 31.599
|
||||
= Slack (non-critical) : 31.675
|
||||
|
||||
Number of logic level(s): 1
|
||||
Starting point: S[2] / Q
|
||||
@ -522,16 +521,16 @@ Path information for path number 1:
|
||||
The start point is clocked by C14M [rising] on pin CK
|
||||
The end point is clocked by C14M [falling] on pin SCLK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
------------------------------------------------------------------------------------------------------------
|
||||
S[2] FD1S3AX Q Out 1.366 1.366 -
|
||||
S[2] Net - - - - 58
|
||||
ram2e_ufm.un1_wb_adr_0_sqmuxa_2_0_a2_0[0] ORCALUT4 A In 0.000 1.366 -
|
||||
ram2e_ufm.un1_wb_adr_0_sqmuxa_2_0_a2_0[0] ORCALUT4 Z Out 1.153 2.519 -
|
||||
N_530 Net - - - - 3
|
||||
VOE_i_0io OFS1P3IX CD In 0.000 2.519 -
|
||||
============================================================================================================
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
---------------------------------------------------------------------------------------
|
||||
S[2] FD1S3AX Q Out 1.353 1.353 -
|
||||
S[2] Net - - - - 50
|
||||
ram2e_ufm.VOE_2_0_a2 ORCALUT4 A In 0.000 1.353 -
|
||||
ram2e_ufm.VOE_2_0_a2 ORCALUT4 Z Out 1.089 2.442 -
|
||||
N_523_1 Net - - - - 2
|
||||
VOE_i_0io OFS1P3IX CD In 0.000 2.442 -
|
||||
=======================================================================================
|
||||
|
||||
|
||||
|
||||
@ -620,7 +619,7 @@ Starting Points with Worst Slack
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
---------------------------------------------------------------------------------------------------
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBACKO wb_ack 0.000 67.088
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBACKO wb_ack 0.000 66.719
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO0 wb_dato[0] 0.000 69.313
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000 69.313
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO2 wb_dato[2] 0.000 69.313
|
||||
@ -635,21 +634,21 @@ ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO7 wb_dato[7]
|
||||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------------------
|
||||
ram2e_ufm.RWMask[0] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[1] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[2] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[3] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[4] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[5] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[6] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[7] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.LEDEN System FD1P3AX SP N_98 69.369 67.736
|
||||
ram2e_ufm.wb_cyc_stb System FD1P3AX SP N_111 69.369 67.736
|
||||
========================================================================================
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
---------------------------------------------------------------------------------------------------------------
|
||||
ram2e_ufm.wb_cyc_stb System FD1P3AX SP un1_CmdBitbangMXO212_1_i[0] 69.369 66.719
|
||||
ram2e_ufm.LEDEN System FD1P3AX SP un1_LEDEN_0_sqmuxa_1_i_0[0] 69.369 67.736
|
||||
ram2e_ufm.RWMask[0] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[1] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[2] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[3] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[4] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[5] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[6] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[7] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
===============================================================================================================
|
||||
|
||||
|
||||
|
||||
@ -663,30 +662,33 @@ Path information for path number 1:
|
||||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
= Required time: 69.369
|
||||
|
||||
- Propagation time: 2.282
|
||||
- Propagation time: 2.650
|
||||
- Clock delay at starting point: 0.000 (ideal)
|
||||
- Estimated clock delay at start point: -0.000
|
||||
= Slack (non-critical) : 67.088
|
||||
= Slack (non-critical) : 66.719
|
||||
|
||||
Number of logic level(s): 2
|
||||
Number of logic level(s): 3
|
||||
Starting point: ram2e_ufm.ufmefb.EFBInst_0 / WBACKO
|
||||
Ending point: ram2e_ufm.RWMask[0] / SP
|
||||
Ending point: ram2e_ufm.wb_cyc_stb / SP
|
||||
The start point is clocked by System [rising]
|
||||
The end point is clocked by C14M [rising] on pin CK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
----------------------------------------------------------------------------------------------------------------
|
||||
ram2e_ufm.ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 -
|
||||
wb_ack Net - - - - 5
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] ORCALUT4 B In 0.000 0.000 -
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] ORCALUT4 Z Out 1.017 1.017 -
|
||||
un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] Net - - - - 1
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 D In 0.000 1.017 -
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 Z Out 1.265 2.282 -
|
||||
N_104 Net - - - - 8
|
||||
ram2e_ufm.RWMask[0] FD1P3AX SP In 0.000 2.282 -
|
||||
================================================================================================================
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
---------------------------------------------------------------------------------------------------------------
|
||||
ram2e_ufm.ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 -
|
||||
wb_ack Net - - - - 4
|
||||
ram2e_ufm.un1_CmdBitbangMXO212_1_0_0_tz[0] ORCALUT4 B In 0.000 0.000 -
|
||||
ram2e_ufm.un1_CmdBitbangMXO212_1_0_0_tz[0] ORCALUT4 Z Out 1.017 1.017 -
|
||||
un1_CmdBitbangMXO212_1_0_0_tz[0] Net - - - - 1
|
||||
ram2e_ufm.un1_CmdBitbangMXO212_1_0_0_0[0] ORCALUT4 C In 0.000 1.017 -
|
||||
ram2e_ufm.un1_CmdBitbangMXO212_1_0_0_0[0] ORCALUT4 Z Out 1.017 2.034 -
|
||||
un1_CmdBitbangMXO212_1_0_0_0[0] Net - - - - 1
|
||||
ram2e_ufm.wb_cyc_stb_RNO_0 ORCALUT4 A In 0.000 2.034 -
|
||||
ram2e_ufm.wb_cyc_stb_RNO_0 ORCALUT4 Z Out 0.617 2.650 -
|
||||
un1_CmdBitbangMXO212_1_i[0] Net - - - - 1
|
||||
ram2e_ufm.wb_cyc_stb FD1P3AX SP In 0.000 2.650 -
|
||||
===============================================================================================================
|
||||
|
||||
|
||||
|
||||
@ -695,16 +697,16 @@ ram2e_ufm.RWMask[0] FD1P3AX SP In
|
||||
Timing exceptions that could not be applied
|
||||
None
|
||||
|
||||
Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 164MB)
|
||||
Finished final timing analysis (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 163MB)
|
||||
|
||||
|
||||
Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 164MB)
|
||||
Finished timing report (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 163MB)
|
||||
|
||||
---------------------------------------
|
||||
Resource Usage Report
|
||||
Part: lcmxo2_1200hc-4
|
||||
|
||||
Register bits: 125 of 1280 (10%)
|
||||
Register bits: 124 of 1280 (10%)
|
||||
PIC Latch: 0
|
||||
I/O cells: 70
|
||||
|
||||
@ -713,7 +715,7 @@ Details:
|
||||
BB: 8
|
||||
CCU2D: 9
|
||||
EFB: 1
|
||||
FD1P3AX: 58
|
||||
FD1P3AX: 57
|
||||
FD1P3IX: 1
|
||||
FD1S3AX: 31
|
||||
FD1S3AY: 4
|
||||
@ -726,15 +728,16 @@ OB: 41
|
||||
OFS1P3BX: 6
|
||||
OFS1P3DX: 12
|
||||
OFS1P3IX: 3
|
||||
ORCALUT4: 275
|
||||
ORCALUT4: 268
|
||||
PFUMX: 10
|
||||
PUR: 1
|
||||
VHI: 3
|
||||
VLO: 3
|
||||
Mapper successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 32MB peak: 164MB)
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:03s; Memory used current: 32MB peak: 163MB)
|
||||
|
||||
Process took 0h:00m:03s realtime, 0h:00m:03s cputime
|
||||
# Fri Jun 7 20:50:03 2024
|
||||
Process took 0h:00m:18s realtime, 0h:00m:03s cputime
|
||||
# Fri Jul 12 16:07:42 2024
|
||||
|
||||
###########################################################]
|
||||
|
||||
@ -0,0 +1,152 @@
|
||||
<HTML>
|
||||
<HEAD><TITLE>Bitgen Report</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Bgn"></A>BITGEN: Bitstream Generator Diamond (64-bit) 3.11.3.469
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Fri Jun 07 20:50:24 2024
|
||||
|
||||
|
||||
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC-NODHGR -w -jedec -gui RAM2E_LCMXO2_1200HC_impl1.ncd RAM2E_LCMXO2_1200HC_impl1.prf
|
||||
|
||||
Loading design for application Bitgen from file RAM2E_LCMXO2_1200HC_impl1.ncd.
|
||||
Design name: RAM2E
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-1200HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application Bitgen from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.11_x64/ispfpga.
|
||||
Package Status: Final Version 1.42.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
|
||||
Running DRC.
|
||||
DRC detected 0 errors and 0 warnings.
|
||||
Reading Preference File from RAM2E_LCMXO2_1200HC_impl1.prf.
|
||||
|
||||
<A name="bgn_ps"></A>
|
||||
<B><U><big>Preference Summary:</big></U></B>
|
||||
|
||||
+---------------------------------+---------------------------------+
|
||||
| Preference | Current Setting |
|
||||
+---------------------------------+---------------------------------+
|
||||
| RamCfg | Reset** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MCCLK_FREQ | 2.08** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| CONFIG_SECURE | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| INBUF | ON** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| JTAG_PORT | ENABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SDM_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SLAVE_SPI_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MASTER_SPI_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| I2C_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MUX_CONFIGURATION_PORTS | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| CONFIGURATION | CFG** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| COMPRESS_CONFIG | ON** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MY_ASSP | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| ONE_TIME_PROGRAM | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| ENABLE_TRANSFR | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SHAREDEBRINIT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| BACKGROUND_RECONFIG | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
* Default setting.
|
||||
** The specified setting matches the default setting.
|
||||
|
||||
|
||||
Creating bit map...
|
||||
|
||||
Bitstream Status: Final Version 1.95.
|
||||
|
||||
Saving bit stream in "RAM2E_LCMXO2_1200HC_impl1.jed".
|
||||
|
||||
===========
|
||||
UFM Summary.
|
||||
===========
|
||||
UFM Size: 511 Pages (128*511 Bits).
|
||||
UFM Utilization: General Purpose Flash Memory.
|
||||
|
||||
Available General Purpose Flash Memory: 511 Pages (Page 0 to Page 510).
|
||||
Initialized UFM Pages: 321 Pages (Page 190 to Page 510).
|
||||
|
||||
Total CPU Time: 3 secs
|
||||
Total REAL Time: 4 secs
|
||||
Peak Memory Usage: 275 MB
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
@ -13,7 +13,7 @@ Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
|
||||
# Written on Fri Jun 7 20:49:59 2024
|
||||
# Written on Fri Jul 12 16:07:16 2024
|
||||
|
||||
##### DESIGN INFO #######################################################
|
||||
|
||||
|
||||
@ -18,24 +18,25 @@ Command line: map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 4 -oc Commercial
|
||||
RAM2E_LCMXO2_1200HC_impl1.prf -mp RAM2E_LCMXO2_1200HC_impl1.mrp -lpf //Mac/
|
||||
iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC-NODHGR/impl1/RAM2E_LCMXO2_1200HC_impl
|
||||
1_synplify.lpf -lpf //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf -c 0
|
||||
-gui
|
||||
-gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC-NODHGR/promote.xml
|
||||
|
||||
Target Vendor: LATTICE
|
||||
Target Device: LCMXO2-1200HCTQFP100
|
||||
Target Performance: 4
|
||||
Mapper: xo2c00, version: Diamond (64-bit) 3.11.3.469
|
||||
Mapped on: 06/07/24 20:50:05
|
||||
Mapped on: 07/12/24 16:07:54
|
||||
|
||||
|
||||
<A name="mrp_ds"></A><B><U><big>Design Summary</big></U></B>
|
||||
Number of registers: 125 out of 1520 (8%)
|
||||
PFU registers: 103 out of 1280 (8%)
|
||||
Number of registers: 124 out of 1520 (8%)
|
||||
PFU registers: 102 out of 1280 (8%)
|
||||
PIO registers: 22 out of 240 (9%)
|
||||
Number of SLICEs: 148 out of 640 (23%)
|
||||
SLICEs as Logic/ROM: 148 out of 640 (23%)
|
||||
Number of SLICEs: 145 out of 640 (23%)
|
||||
SLICEs as Logic/ROM: 145 out of 640 (23%)
|
||||
SLICEs as RAM: 0 out of 480 (0%)
|
||||
SLICEs as Carry: 9 out of 640 (1%)
|
||||
Number of LUT4s: 296 out of 1280 (23%)
|
||||
Number used as logic LUTs: 278
|
||||
Number of LUT4s: 289 out of 1280 (23%)
|
||||
Number used as logic LUTs: 271
|
||||
Number used as distributed RAM: 0
|
||||
Number used as ripple logic: 18
|
||||
Number used as shift registers: 0
|
||||
@ -65,44 +66,45 @@ Mapped on: 06/07/24 20:50:05
|
||||
2. Number of logic LUT4s does not include count of distributed RAM and
|
||||
ripple logic.
|
||||
Number of clocks: 2
|
||||
Net C14M_c: 85 loads, 63 rising, 22 falling (Driver: PIO C14M )
|
||||
Net PHI1_c: 3 loads, 0 rising, 3 falling (Driver: PIO PHI1 )
|
||||
Net C14M_c: 84 loads, 62 rising, 22 falling (Driver: PIO C14M )
|
||||
|
||||
Net PHI1_c: 3 loads, 0 rising, 3 falling (Driver: PIO PHI1 )
|
||||
Number of Clock Enables: 13
|
||||
Net N_117_i: 2 loads, 0 LSLICEs
|
||||
Net RWBank14: 11 loads, 11 LSLICEs
|
||||
Net N_347_i: 2 loads, 0 LSLICEs
|
||||
Net RWBank14: 10 loads, 10 LSLICEs
|
||||
Net ram2e_ufm/wb_adr_0_sqmuxa_1_i: 1 loads, 1 LSLICEs
|
||||
Net un9_VOE_0_a2_0_a2: 1 loads, 1 LSLICEs
|
||||
Net un6_DOEEN_0_a2_0_a2: 2 loads, 2 LSLICEs
|
||||
Net ram2e_ufm/un1_wb_adr_0_sqmuxa_2_i[0]: 8 loads, 8 LSLICEs
|
||||
Net ram2e_ufm/un1_wb_cyc_stb_0_sqmuxa_1_i[0]: 1 loads, 1 LSLICEs
|
||||
Net ram2e_ufm/N_111: 1 loads, 1 LSLICEs
|
||||
Net ram2e_ufm/N_104: 4 loads, 4 LSLICEs
|
||||
Net ram2e_ufm/N_98: 1 loads, 1 LSLICEs
|
||||
Net un1_CKE48_0_i: 6 loads, 6 LSLICEs
|
||||
Net N_389_i: 2 loads, 0 LSLICEs
|
||||
Net ram2e_ufm/N_63: 1 loads, 1 LSLICEs
|
||||
Net ram2e_ufm/un1_wb_adr_0_sqmuxa_2_i_0[0]: 8 loads, 8 LSLICEs
|
||||
Net ram2e_ufm/un1_CmdBitbangMXO212_1_i[0]: 1 loads, 1 LSLICEs
|
||||
Net ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0[0]: 4 loads, 4 LSLICEs
|
||||
Net ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0[0]: 1 loads, 1 LSLICEs
|
||||
Net un9_VOE_0_a2: 1 loads, 1 LSLICEs
|
||||
Net un1_CKE48_i: 6 loads, 6 LSLICEs
|
||||
Net N_346_i: 2 loads, 0 LSLICEs
|
||||
Net Vout3: 8 loads, 0 LSLICEs
|
||||
Number of LSRs: 8
|
||||
Net N_148: 2 loads, 2 LSLICEs
|
||||
Net N_430_i: 2 loads, 0 LSLICEs
|
||||
Number of LSRs: 9
|
||||
Net un1_CS_0_sqmuxa_i: 2 loads, 2 LSLICEs
|
||||
Net ram2e_ufm.wb_rst13: 2 loads, 0 LSLICEs
|
||||
Net RC7: 2 loads, 2 LSLICEs
|
||||
Net S[2]: 2 loads, 2 LSLICEs
|
||||
Net S[1]: 1 loads, 1 LSLICEs
|
||||
Net ram2e_ufm/wb_rst: 1 loads, 0 LSLICEs
|
||||
Net ram2e_ufm/nRWE_0_i_o3_RNIP8E61: 1 loads, 1 LSLICEs
|
||||
Net N_530: 1 loads, 0 LSLICEs
|
||||
Net N_301_i: 1 loads, 1 LSLICEs
|
||||
Net ram2e_ufm/wb_rst6_i: 1 loads, 1 LSLICEs
|
||||
Net N_523_1: 1 loads, 0 LSLICEs
|
||||
Net N_727_0: 1 loads, 1 LSLICEs
|
||||
Net RATc_i: 1 loads, 1 LSLICEs
|
||||
Number of nets driven by tri-state buffers: 0
|
||||
Top 10 highest fanout non-clock nets:
|
||||
Net S[2]: 60 loads
|
||||
Net S[3]: 48 loads
|
||||
Net S[1]: 46 loads
|
||||
Net S[0]: 31 loads
|
||||
Net FS[11]: 24 loads
|
||||
Net FS[10]: 23 loads
|
||||
Net FS[12]: 23 loads
|
||||
Net FS[9]: 23 loads
|
||||
Net FS[13]: 21 loads
|
||||
Net FS[8]: 18 loads
|
||||
Net S[2]: 51 loads
|
||||
Net S[1]: 44 loads
|
||||
Net S[3]: 40 loads
|
||||
Net S[0]: 32 loads
|
||||
Net FS[8]: 29 loads
|
||||
Net FS[9]: 26 loads
|
||||
Net FS[10]: 25 loads
|
||||
Net FS[11]: 23 loads
|
||||
Net FS[13]: 20 loads
|
||||
Net ram2e_ufm.wb_rst13: 17 loads
|
||||
|
||||
|
||||
|
||||
@ -124,9 +126,9 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
||||
Controller, GSR, Hardened User SPI Port, Hardened Primary User I2C Port.
|
||||
Functionality is restored after the Flash Memory (UFM/Configuration)
|
||||
Interface is disabled using Disable Configuration Interface command 0x26
|
||||
|
||||
followed by Bypass command 0xFF.
|
||||
WARNING - map: IO buffer missing for top level port nWE80...logic will be
|
||||
|
||||
discarded.
|
||||
|
||||
|
||||
@ -182,9 +184,9 @@ WARNING - map: IO buffer missing for top level port nWE80...logic will be
|
||||
| RAout[2] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RAout[1] | OUTPUT | LVCMOS33 | |
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RAout[0] | OUTPUT | LVCMOS33 | |
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| BA[1] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
@ -239,9 +241,9 @@ WARNING - map: IO buffer missing for top level port nWE80...logic will be
|
||||
| Din[7] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[6] | INPUT | LVCMOS33 | |
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[5] | INPUT | LVCMOS33 | |
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[4] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
@ -297,9 +299,9 @@ Signal FS_s_0_COUT[15] undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/CFGWAKE undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/wbc_ufm_irq undriven or does not drive anything -
|
||||
|
||||
clipped.
|
||||
Signal ram2e_ufm/ufmefb/TCOC undriven or does not drive anything - clipped.
|
||||
|
||||
Signal ram2e_ufm/ufmefb/TCINT undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIIRQO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPICSNEN undriven or does not drive anything - clipped.
|
||||
@ -354,9 +356,9 @@ Signal ram2e_ufm/ufmefb/PLLCLKO undriven or does not drive anything - clipped.
|
||||
Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped.
|
||||
Signal N_1 undriven or does not drive anything - clipped.
|
||||
Block RefReq.CN was optimized away.
|
||||
|
||||
Block RDOE_RNIAM8C was optimized away.
|
||||
Block nCASout.CN was optimized away.
|
||||
|
||||
Block ram2e_ufm/ufmefb/VCC was optimized away.
|
||||
Block ram2e_ufm/ufmefb/GND was optimized away.
|
||||
|
||||
@ -414,13 +416,68 @@ Instance Name: ram2e_ufm/ufmefb/EFBInst_0
|
||||
<A name="mrp_runtime"></A><B><U><big>Run Time and Memory Usage</big></U></B>
|
||||
-------------------------
|
||||
|
||||
Total CPU Time: 0 secs
|
||||
Total REAL Time: 2 secs
|
||||
Peak Memory Usage: 64 MB
|
||||
Total CPU Time: 1 secs
|
||||
Total REAL Time: 8 secs
|
||||
|
||||
Peak Memory Usage: 65 MB
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
|
||||
@ -14,7 +14,7 @@ Performance Grade: 4
|
||||
PACKAGE: TQFP100
|
||||
Package Status: Final Version 1.42
|
||||
|
||||
Fri Jun 07 20:50:15 2024
|
||||
Fri Jul 12 16:08:20 2024
|
||||
|
||||
Pinout by Port Name:
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
@ -320,7 +320,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Fri Jun 07 20:50:20 2024
|
||||
Fri Jul 12 16:08:32 2024
|
||||
|
||||
|
||||
|
||||
|
||||
@ -12,11 +12,12 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Fri Jun 07 20:50:07 2024
|
||||
Fri Jul 12 16:08:03 2024
|
||||
|
||||
C:/lscc/diamond/3.11_x64/ispfpga\bin\nt64\par -f RAM2E_LCMXO2_1200HC_impl1.p2t
|
||||
RAM2E_LCMXO2_1200HC_impl1_map.ncd RAM2E_LCMXO2_1200HC_impl1.dir
|
||||
RAM2E_LCMXO2_1200HC_impl1.prf -gui
|
||||
RAM2E_LCMXO2_1200HC_impl1.prf -gui -msgset
|
||||
//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC-NODHGR/promote.xml
|
||||
|
||||
|
||||
Preference file: RAM2E_LCMXO2_1200HC_impl1.prf.
|
||||
@ -25,22 +26,22 @@ Preference file: RAM2E_LCMXO2_1200HC_impl1.prf.
|
||||
Level/ Number Worst Timing Worst Timing Run NCD
|
||||
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
|
||||
---------- -------- ----- ------ ----------- ----------- ---- ------
|
||||
5_1 * 0 56.210 0 0.326 0 17 Completed
|
||||
5_1 * 0 56.179 0 0.319 0 38 Completed
|
||||
* : Design saved.
|
||||
|
||||
Total (real) run time for 1-seed: 17 secs
|
||||
Total (real) run time for 1-seed: 40 secs
|
||||
|
||||
par done!
|
||||
|
||||
Note: user must run 'Trace' for timing closure signoff.
|
||||
|
||||
Lattice Place and Route Report for Design "RAM2E_LCMXO2_1200HC_impl1_map.ncd"
|
||||
Fri Jun 07 20:50:07 2024
|
||||
Fri Jul 12 16:08:04 2024
|
||||
|
||||
|
||||
<A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
|
||||
PAR: Place And Route Diamond (64-bit) 3.11.3.469.
|
||||
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF RAM2E_LCMXO2_1200HC_impl1_map.ncd RAM2E_LCMXO2_1200HC_impl1.dir/5_1.ncd RAM2E_LCMXO2_1200HC_impl1.prf
|
||||
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC-NODHGR/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF RAM2E_LCMXO2_1200HC_impl1_map.ncd RAM2E_LCMXO2_1200HC_impl1.dir/5_1.ncd RAM2E_LCMXO2_1200HC_impl1.prf
|
||||
Preference file: RAM2E_LCMXO2_1200HC_impl1.prf.
|
||||
Placement level-cost: 5-1.
|
||||
Routing Iterations: 6
|
||||
@ -66,39 +67,39 @@ Ignore Preference Error(s): True
|
||||
70+4(JTAG)/80 93% bonded
|
||||
IOLOGIC 22/108 20% used
|
||||
|
||||
SLICE 148/640 23% used
|
||||
SLICE 145/640 22% used
|
||||
|
||||
EFB 1/1 100% used
|
||||
|
||||
|
||||
Number of Signals: 465
|
||||
Number of Connections: 1330
|
||||
Number of Signals: 447
|
||||
Number of Connections: 1292
|
||||
|
||||
Pin Constraint Summary:
|
||||
70 out of 70 pins locked (100% locked).
|
||||
|
||||
The following 1 signal is selected to use the primary clock routing resources:
|
||||
C14M_c (driver: C14M, clk load #: 85)
|
||||
C14M_c (driver: C14M, clk load #: 84)
|
||||
|
||||
WARNING - par: Signal "C14M_c" is selected to use Primary clock resources. However, its driver comp "C14M" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
|
||||
The following 1 signal is selected to use the secondary clock routing resources:
|
||||
RWBank14 (driver: ram2e_ufm/SLICE_82, clk load #: 0, sr load #: 0, ce load #: 11)
|
||||
RWBank14 (driver: ram2e_ufm/SLICE_89, clk load #: 0, sr load #: 0, ce load #: 10)
|
||||
|
||||
No signal is selected as Global Set/Reset.
|
||||
Starting Placer Phase 0.
|
||||
.......
|
||||
Finished Placer Phase 0. REAL time: 2 secs
|
||||
........
|
||||
Finished Placer Phase 0. REAL time: 4 secs
|
||||
|
||||
Starting Placer Phase 1.
|
||||
....................
|
||||
Placer score = 84481.
|
||||
Finished Placer Phase 1. REAL time: 8 secs
|
||||
Placer score = 83226.
|
||||
Finished Placer Phase 1. REAL time: 15 secs
|
||||
|
||||
Starting Placer Phase 2.
|
||||
.
|
||||
Placer score = 83723
|
||||
Finished Placer Phase 2. REAL time: 8 secs
|
||||
Placer score = 83139
|
||||
Finished Placer Phase 2. REAL time: 15 secs
|
||||
|
||||
|
||||
|
||||
@ -112,8 +113,8 @@ Global Clock Resources:
|
||||
DCC : 0 out of 8 (0%)
|
||||
|
||||
Global Clocks:
|
||||
PRIMARY "C14M_c" from comp "C14M" on PIO site "62 (PR5D)", clk load = 85
|
||||
SECONDARY "RWBank14" from F0 on comp "ram2e_ufm/SLICE_82" on site "R7C12A", clk load = 0, ce load = 11, sr load = 0
|
||||
PRIMARY "C14M_c" from comp "C14M" on PIO site "62 (PR5D)", clk load = 84
|
||||
SECONDARY "RWBank14" from F0 on comp "ram2e_ufm/SLICE_89" on site "R7C12C", clk load = 0, ce load = 10, sr load = 0
|
||||
|
||||
PRIMARY : 1 out of 8 (12%)
|
||||
SECONDARY: 1 out of 8 (12%)
|
||||
@ -140,20 +141,20 @@ I/O Bank Usage Summary:
|
||||
| 3 | 20 / 20 (100%) | 3.3V | - |
|
||||
+----------+----------------+------------+-----------+
|
||||
|
||||
Total placer CPU time: 7 secs
|
||||
Total placer CPU time: 8 secs
|
||||
|
||||
Dumping design to file RAM2E_LCMXO2_1200HC_impl1.dir/5_1.ncd.
|
||||
|
||||
0 connections routed; 1330 unrouted.
|
||||
0 connections routed; 1292 unrouted.
|
||||
Starting router resource preassignment
|
||||
WARNING - par: The driver of primary clock net C14M_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
|
||||
|
||||
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
|
||||
Signal=PHI1_c loads=5 clock_loads=3
|
||||
|
||||
Completed router resource preassignment. Real time: 14 secs
|
||||
Completed router resource preassignment. Real time: 29 secs
|
||||
|
||||
Start NBR router at 20:50:21 06/07/24
|
||||
Start NBR router at 16:08:33 07/12/24
|
||||
|
||||
*****************************************************************
|
||||
Info: NBR allows conflicts(one node used by more than one signal)
|
||||
@ -168,35 +169,35 @@ Note: NBR uses a different method to calculate timing slacks. The
|
||||
your design.
|
||||
*****************************************************************
|
||||
|
||||
Start NBR special constraint process at 20:50:21 06/07/24
|
||||
Start NBR special constraint process at 16:08:33 07/12/24
|
||||
|
||||
Start NBR section for initial routing at 20:50:21 06/07/24
|
||||
Start NBR section for initial routing at 16:08:33 07/12/24
|
||||
Level 4, iteration 1
|
||||
19(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 56.222ns/0.000ns; real time: 15 secs
|
||||
14(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 56.179ns/0.000ns; real time: 37 secs
|
||||
|
||||
Info: Initial congestion level at 75% usage is 0
|
||||
Info: Initial congestion area at 75% usage is 0 (0.00%)
|
||||
|
||||
Start NBR section for normal routing at 20:50:22 06/07/24
|
||||
Start NBR section for normal routing at 16:08:41 07/12/24
|
||||
Level 4, iteration 1
|
||||
6(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 56.222ns/0.000ns; real time: 15 secs
|
||||
Estimated worst slack/total negative slack<setup>: 56.179ns/0.000ns; real time: 37 secs
|
||||
Level 4, iteration 2
|
||||
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 56.210ns/0.000ns; real time: 15 secs
|
||||
Estimated worst slack/total negative slack<setup>: 56.179ns/0.000ns; real time: 37 secs
|
||||
Level 4, iteration 3
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 56.210ns/0.000ns; real time: 15 secs
|
||||
Estimated worst slack/total negative slack<setup>: 56.179ns/0.000ns; real time: 37 secs
|
||||
|
||||
Start NBR section for setup/hold timing optimization with effort level 3 at 20:50:22 06/07/24
|
||||
Start NBR section for setup/hold timing optimization with effort level 3 at 16:08:41 07/12/24
|
||||
|
||||
Start NBR section for re-routing at 20:50:23 06/07/24
|
||||
Start NBR section for re-routing at 16:08:41 07/12/24
|
||||
Level 4, iteration 1
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 56.210ns/0.000ns; real time: 16 secs
|
||||
Estimated worst slack/total negative slack<setup>: 56.179ns/0.000ns; real time: 37 secs
|
||||
|
||||
Start NBR section for post-routing at 20:50:23 06/07/24
|
||||
Start NBR section for post-routing at 16:08:41 07/12/24
|
||||
|
||||
End NBR router with 0 unrouted connection
|
||||
|
||||
@ -204,7 +205,7 @@ NBR Summary
|
||||
-----------
|
||||
Number of unrouted connections : 0 (0.00%)
|
||||
Number of connections with timing violations : 0 (0.00%)
|
||||
Estimated worst slack<setup> : 56.210ns
|
||||
Estimated worst slack<setup> : 56.179ns
|
||||
Timing score<setup> : 0
|
||||
-----------
|
||||
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
|
||||
@ -215,9 +216,9 @@ WARNING - par: The following clock signals will be routed by using generic routi
|
||||
Signal=PHI1_c loads=5 clock_loads=3
|
||||
|
||||
Total CPU time 14 secs
|
||||
Total REAL time: 16 secs
|
||||
Total REAL time: 38 secs
|
||||
Completely routed.
|
||||
End of route. 1330 routed (100.00%); 0 unrouted.
|
||||
End of route. 1292 routed (100.00%); 0 unrouted.
|
||||
|
||||
Hold time timing score: 0, hold timing errors: 0
|
||||
|
||||
@ -231,14 +232,14 @@ All signals are completely routed.
|
||||
|
||||
PAR_SUMMARY::Run status = Completed
|
||||
PAR_SUMMARY::Number of unrouted conns = 0
|
||||
PAR_SUMMARY::Worst slack<setup/<ns>> = 56.210
|
||||
PAR_SUMMARY::Worst slack<setup/<ns>> = 56.179
|
||||
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
|
||||
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.326
|
||||
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.319
|
||||
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
|
||||
PAR_SUMMARY::Number of errors = 0
|
||||
|
||||
Total CPU time to completion: 14 secs
|
||||
Total REAL time to completion: 17 secs
|
||||
Total REAL time to completion: 39 secs
|
||||
|
||||
par done!
|
||||
|
||||
|
||||
@ -13,7 +13,7 @@ Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
|
||||
# Written on Fri Jun 7 20:49:58 2024
|
||||
# Written on Fri Jul 12 16:07:14 2024
|
||||
|
||||
##### FILES SYNTAX CHECKED ##############################################
|
||||
Constraint File(s): "\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc"
|
||||
@ -33,7 +33,7 @@ Clock Summary
|
||||
Start Requested Requested Clock Clock Clock
|
||||
Level Clock Frequency Period Type Group Load
|
||||
-----------------------------------------------------------------------------------------------
|
||||
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 121
|
||||
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 120
|
||||
|
||||
0 - System 100.0 MHz 10.000 system system_clkgroup 0
|
||||
|
||||
@ -47,7 +47,7 @@ Clock Load Summary
|
||||
Clock Source Clock Pin Non-clock Pin Non-clock Pin
|
||||
Clock Load Pin Seq Example Seq Example Comb Example
|
||||
--------------------------------------------------------------------------------------------
|
||||
C14M 121 C14M(port) RAT.C - un1_C14M.I[0](inv)
|
||||
C14M 120 C14M(port) RAT.C - un1_C14M.I[0](inv)
|
||||
|
||||
System 0 - - - -
|
||||
|
||||
|
||||
@ -62,7 +62,7 @@
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Updated:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2024/06/07 20:50:28</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2024/07/12 16:08:52</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Location:</SPAN></TD>
|
||||
|
||||
@ -12,7 +12,7 @@
|
||||
#OS: Windows 8 6.2
|
||||
#Hostname: ZANEMACWIN11
|
||||
|
||||
# Fri Jun 7 20:49:56 2024
|
||||
# Fri Jul 12 16:07:01 2024
|
||||
|
||||
#Implementation: impl1
|
||||
|
||||
@ -61,6 +61,7 @@ Synopsys Verilog Compiler, Version comp2018q2p1, Build 461R, Built Apr 1 2019 0
|
||||
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC-NODHGR\REFB.v" (library work)
|
||||
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\DHGR-OFF.v" (library work)
|
||||
Verilog syntax check successful!
|
||||
File \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v changed - recompiling
|
||||
Selecting top level module RAM2E
|
||||
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
|
||||
Running optimization stage 1 on VHI .......
|
||||
@ -86,12 +87,12 @@ Running optimization stage 2 on EFB .......
|
||||
Running optimization stage 2 on VLO .......
|
||||
Running optimization stage 2 on VHI .......
|
||||
|
||||
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)
|
||||
At c_ver Exit (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
Process took 0h:00m:05s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Fri Jun 7 20:49:57 2024
|
||||
# Fri Jul 12 16:07:10 2024
|
||||
|
||||
###########################################################]
|
||||
|
||||
@ -111,13 +112,14 @@ Implementation : impl1
|
||||
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
File \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC-NODHGR\impl1\synwork\layer0.srs changed - recompiling
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Fri Jun 7 20:49:57 2024
|
||||
# Fri Jul 12 16:07:11 2024
|
||||
|
||||
###########################################################]
|
||||
|
||||
@ -127,12 +129,12 @@ For a summary of runtime and memory usage for all design units, please see file:
|
||||
|
||||
@END
|
||||
|
||||
At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
|
||||
At c_hdl Exit (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
Process took 0h:00m:08s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Fri Jun 7 20:49:57 2024
|
||||
# Fri Jul 12 16:07:11 2024
|
||||
|
||||
###########################################################]
|
||||
|
||||
@ -152,18 +154,17 @@ Database state : \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC-NODHGR\impl1\synwor
|
||||
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
File \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC-NODHGR\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_comp.srs changed - recompiling
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Fri Jun 7 20:49:58 2024
|
||||
# Fri Jul 12 16:07:14 2024
|
||||
|
||||
###########################################################]
|
||||
Premap Report
|
||||
|
||||
# Fri Jun 7 20:49:58 2024
|
||||
# Fri Jul 12 16:07:14 2024
|
||||
|
||||
|
||||
Copyright (C) 1994-2018 Synopsys, Inc.
|
||||
@ -208,7 +209,7 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h
|
||||
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":21:4:21:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
|
||||
@N: MH105 |UMR3 is only supported for HAPS-80.
|
||||
@N: MH105 |UMR3 is only supported for HAPS-80.
|
||||
@N: BN115 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":140:9:140:12|Removing instance dhgr (in view: work.RAM2E(verilog)) of type view:work.DHGR(verilog) because it does not drive other instances.
|
||||
@N: BN115 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":136:9:136:12|Removing instance dhgr (in view: work.RAM2E(verilog)) of type view:work.DHGR(verilog) because it does not drive other instances.
|
||||
syn_allowed_resources : blockrams=7 set on top level netlist RAM2E
|
||||
|
||||
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
|
||||
@ -221,7 +222,7 @@ Clock Summary
|
||||
Start Requested Requested Clock Clock Clock
|
||||
Level Clock Frequency Period Type Group Load
|
||||
-----------------------------------------------------------------------------------------------
|
||||
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 121
|
||||
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 120
|
||||
|
||||
0 - System 100.0 MHz 10.000 system system_clkgroup 0
|
||||
|
||||
@ -236,7 +237,7 @@ Clock Load Summary
|
||||
Clock Source Clock Pin Non-clock Pin Non-clock Pin
|
||||
Clock Load Pin Seq Example Seq Example Comb Example
|
||||
--------------------------------------------------------------------------------------------
|
||||
C14M 121 C14M(port) RAT.C - un1_C14M.I[0](inv)
|
||||
C14M 120 C14M(port) RAT.C - un1_C14M.I[0](inv)
|
||||
|
||||
System 0 - - - -
|
||||
|
||||
@ -256,14 +257,14 @@ Number of ICG latches not removed: 0
|
||||
|
||||
#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
|
||||
|
||||
2 non-gated/non-generated clock tree(s) driving 125 clock pin(s) of sequential element(s)
|
||||
2 non-gated/non-generated clock tree(s) driving 124 clock pin(s) of sequential element(s)
|
||||
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
|
||||
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
|
||||
|
||||
=========================== Non-Gated/Non-Generated Clocks ============================
|
||||
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
|
||||
---------------------------------------------------------------------------------------
|
||||
@KP:ckid0_0 C14M port 121 PHI1r
|
||||
@KP:ckid0_0 C14M port 120 PHI1r
|
||||
@KP:ckid0_1 PHI1 Unconstrained_port 4 RC[2:0]
|
||||
=======================================================================================
|
||||
|
||||
@ -273,27 +274,25 @@ Clock Tree ID Driving Element Drive Element Type Fanout Sample I
|
||||
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
|
||||
Finished Pre Mapping Phase.
|
||||
|
||||
Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
|
||||
Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
|
||||
|
||||
|
||||
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
|
||||
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
|
||||
|
||||
None
|
||||
None
|
||||
|
||||
Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
|
||||
Finished constraint checker (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
|
||||
|
||||
Pre-mapping successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB)
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Fri Jun 7 20:49:59 2024
|
||||
Process took 0h:00m:04s realtime, 0h:00m:01s cputime
|
||||
# Fri Jul 12 16:07:19 2024
|
||||
|
||||
###########################################################]
|
||||
Map & Optimize Report
|
||||
|
||||
# Fri Jun 7 20:50:00 2024
|
||||
# Fri Jul 12 16:07:22 2024
|
||||
|
||||
|
||||
Copyright (C) 1994-2018 Synopsys, Inc.
|
||||
@ -322,18 +321,18 @@ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:0
|
||||
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
|
||||
|
||||
|
||||
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
|
||||
Mapper Initialization Complete (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
|
||||
|
||||
|
||||
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
|
||||
Start loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
|
||||
|
||||
|
||||
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
|
||||
Finished loading timing files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
|
||||
|
||||
@N: MF284 |Setting synthesis effort to medium for the design
|
||||
|
||||
|
||||
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
|
||||
Starting Optimization and Mapping (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
|
||||
|
||||
|
||||
Available hyper_sources - for debug and ip models
|
||||
@ -342,61 +341,61 @@ Available hyper_sources - for debug and ip models
|
||||
@N: FX493 |Applying initial value "00000000" on instance RWBank[7:0].
|
||||
@N: FX493 |Applying initial value "0000" on instance S[3:0].
|
||||
|
||||
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)
|
||||
Finished RTL optimizations (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)
|
||||
|
||||
@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":14:23:14:28|Found counter in view:work.RAM2E(verilog) instance FS[15:0]
|
||||
|
||||
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 142MB)
|
||||
Starting factoring (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 142MB)
|
||||
|
||||
|
||||
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
|
||||
Finished factoring (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
|
||||
|
||||
|
||||
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
|
||||
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
|
||||
|
||||
|
||||
Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
|
||||
Starting Early Timing Optimization (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
|
||||
|
||||
|
||||
Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
|
||||
Finished Early Timing Optimization (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
|
||||
|
||||
|
||||
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
|
||||
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
|
||||
|
||||
|
||||
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
|
||||
Finished preparing to map (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 147MB)
|
||||
|
||||
|
||||
Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
|
||||
Finished technology mapping (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
|
||||
|
||||
Pass CPU time Worst Slack Luts / Registers
|
||||
------------------------------------------------------------
|
||||
1 0h:00m:01s 6.90ns 281 / 125
|
||||
1 0h:00m:01s 6.90ns 280 / 124
|
||||
|
||||
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
|
||||
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
|
||||
|
||||
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
|
||||
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":171:4:171:9|Boundary register BA_1_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
||||
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":171:4:171:9|Boundary register BA_0_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
||||
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":168:4:168:9|Boundary register BA_1_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
||||
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":168:4:168:9|Boundary register BA_0_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
||||
|
||||
Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 158MB peak: 160MB)
|
||||
Finished restoring hierarchy (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:01s; Memory used current: 158MB peak: 160MB)
|
||||
|
||||
|
||||
Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 122MB peak: 160MB)
|
||||
Start Writing Netlists (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:01s; Memory used current: 122MB peak: 160MB)
|
||||
|
||||
Writing Analyst data base \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC-NODHGR\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_m.srm
|
||||
|
||||
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 158MB peak: 160MB)
|
||||
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:02s; Memory used current: 157MB peak: 160MB)
|
||||
|
||||
Writing EDIF Netlist and constraint files
|
||||
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC-NODHGR\impl1\RAM2E_LCMXO2_1200HC_impl1.edi
|
||||
N-2018.03L-SP1-1
|
||||
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
|
||||
|
||||
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 162MB peak: 164MB)
|
||||
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:02s; Memory used current: 161MB peak: 163MB)
|
||||
|
||||
|
||||
Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 164MB)
|
||||
Start final timing analysis (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:03s; Memory used current: 160MB peak: 163MB)
|
||||
|
||||
@W: MT246 :"\\mac\icloud\repos\ram2e\cpld\lcmxo2-1200hc-nodhgr\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
|
||||
@N: MT615 |Found clock C14M with period 69.84ns
|
||||
@ -404,7 +403,7 @@ Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:0
|
||||
|
||||
|
||||
##### START OF TIMING REPORT #####[
|
||||
# Timing Report written on Fri Jun 7 20:50:03 2024
|
||||
# Timing Report written on Fri Jul 12 16:07:38 2024
|
||||
#
|
||||
|
||||
|
||||
@ -429,9 +428,9 @@ Worst slack in design: 6.897
|
||||
Requested Estimated Requested Estimated Clock Clock
|
||||
Starting Clock Frequency Frequency Period Period Slack Type Group
|
||||
----------------------------------------------------------------------------------------------------------------------
|
||||
C14M 14.3 MHz 112.1 MHz 69.841 8.918 31.599 declared default_clkgroup
|
||||
C14M 14.3 MHz 120.3 MHz 69.841 8.314 31.675 declared default_clkgroup
|
||||
RAM2E|PHI1 100.0 MHz 322.2 MHz 10.000 3.103 6.897 inferred Inferred_clkgroup_0
|
||||
System 100.0 MHz NA 10.000 NA 67.088 system system_clkgroup
|
||||
System 100.0 MHz NA 10.000 NA 66.719 system system_clkgroup
|
||||
======================================================================================================================
|
||||
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
|
||||
|
||||
@ -446,9 +445,9 @@ Clocks | rise to rise | fall to fall | rise
|
||||
----------------------------------------------------------------------------------------------------------------
|
||||
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
|
||||
----------------------------------------------------------------------------------------------------------------
|
||||
System C14M | 69.841 67.088 | No paths - | No paths - | No paths -
|
||||
System C14M | 69.841 66.719 | No paths - | No paths - | No paths -
|
||||
C14M System | 69.841 68.797 | No paths - | No paths - | No paths -
|
||||
C14M C14M | 69.841 60.923 | No paths - | 34.920 31.599 | No paths -
|
||||
C14M C14M | 69.841 61.527 | No paths - | 34.920 31.675 | No paths -
|
||||
RAM2E|PHI1 C14M | No paths - | No paths - | No paths - | Diff grp -
|
||||
RAM2E|PHI1 RAM2E|PHI1 | No paths - | 10.000 6.897 | No paths - | No paths -
|
||||
================================================================================================================
|
||||
@ -477,10 +476,10 @@ Starting Points with Worst Slack
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
---------------------------------------------------------------------------
|
||||
S[2] C14M FD1S3AX Q S[2] 1.366 31.599
|
||||
S[3] C14M FD1S3AX Q S[3] 1.345 31.619
|
||||
S[1] C14M FD1S3AX Q S[1] 1.344 31.800
|
||||
S[0] C14M FD1S3AX Q S[0] 1.305 31.838
|
||||
S[2] C14M FD1S3AX Q S[2] 1.353 31.675
|
||||
S[3] C14M FD1S3AX Q S[3] 1.337 31.691
|
||||
S[0] C14M FD1S3AX Q S[0] 1.319 32.182
|
||||
S[1] C14M FD1S3AX Q S[1] 1.344 32.656
|
||||
RA[0] C14M FD1P3AX Q RA[0] 1.108 33.707
|
||||
RA[3] C14M FD1P3AX Q RA[3] 1.108 33.707
|
||||
RA[1] C14M FD1P3AX Q RA[1] 1.044 33.771
|
||||
@ -493,21 +492,21 @@ RA[5] C14M FD1P3AX Q RA[5] 1.044 33.771
|
||||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
-----------------------------------------------------------------------------------
|
||||
VOE_i_0io C14M OFS1P3IX CD N_530 34.118 31.599
|
||||
VOE_i_0io C14M OFS1P3IX D VOE_ic_i 35.009 31.800
|
||||
Vout_0io[0] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[1] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[2] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[3] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[4] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[5] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[6] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[7] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
===================================================================================
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------------
|
||||
VOE_i_0io C14M OFS1P3IX CD N_523_1 34.118 31.675
|
||||
RAT C14M FD1S3IX CD RATc_i 34.118 32.147
|
||||
Vout_0io[0] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[1] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[2] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[3] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[4] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[5] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[6] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[7] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
==================================================================================
|
||||
|
||||
|
||||
|
||||
@ -521,9 +520,9 @@ Path information for path number 1:
|
||||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
= Required time: 34.118
|
||||
|
||||
- Propagation time: 2.519
|
||||
- Propagation time: 2.442
|
||||
- Clock delay at starting point: 0.000 (ideal)
|
||||
= Slack (non-critical) : 31.599
|
||||
= Slack (non-critical) : 31.675
|
||||
|
||||
Number of logic level(s): 1
|
||||
Starting point: S[2] / Q
|
||||
@ -531,16 +530,16 @@ Path information for path number 1:
|
||||
The start point is clocked by C14M [rising] on pin CK
|
||||
The end point is clocked by C14M [falling] on pin SCLK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
------------------------------------------------------------------------------------------------------------
|
||||
S[2] FD1S3AX Q Out 1.366 1.366 -
|
||||
S[2] Net - - - - 58
|
||||
ram2e_ufm.un1_wb_adr_0_sqmuxa_2_0_a2_0[0] ORCALUT4 A In 0.000 1.366 -
|
||||
ram2e_ufm.un1_wb_adr_0_sqmuxa_2_0_a2_0[0] ORCALUT4 Z Out 1.153 2.519 -
|
||||
N_530 Net - - - - 3
|
||||
VOE_i_0io OFS1P3IX CD In 0.000 2.519 -
|
||||
============================================================================================================
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
---------------------------------------------------------------------------------------
|
||||
S[2] FD1S3AX Q Out 1.353 1.353 -
|
||||
S[2] Net - - - - 50
|
||||
ram2e_ufm.VOE_2_0_a2 ORCALUT4 A In 0.000 1.353 -
|
||||
ram2e_ufm.VOE_2_0_a2 ORCALUT4 Z Out 1.089 2.442 -
|
||||
N_523_1 Net - - - - 2
|
||||
VOE_i_0io OFS1P3IX CD In 0.000 2.442 -
|
||||
=======================================================================================
|
||||
|
||||
|
||||
|
||||
@ -629,7 +628,7 @@ Starting Points with Worst Slack
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
---------------------------------------------------------------------------------------------------
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBACKO wb_ack 0.000 67.088
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBACKO wb_ack 0.000 66.719
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO0 wb_dato[0] 0.000 69.313
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000 69.313
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO2 wb_dato[2] 0.000 69.313
|
||||
@ -644,21 +643,21 @@ ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO7 wb_dato[7]
|
||||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------------------
|
||||
ram2e_ufm.RWMask[0] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[1] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[2] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[3] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[4] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[5] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[6] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[7] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.LEDEN System FD1P3AX SP N_98 69.369 67.736
|
||||
ram2e_ufm.wb_cyc_stb System FD1P3AX SP N_111 69.369 67.736
|
||||
========================================================================================
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
---------------------------------------------------------------------------------------------------------------
|
||||
ram2e_ufm.wb_cyc_stb System FD1P3AX SP un1_CmdBitbangMXO212_1_i[0] 69.369 66.719
|
||||
ram2e_ufm.LEDEN System FD1P3AX SP un1_LEDEN_0_sqmuxa_1_i_0[0] 69.369 67.736
|
||||
ram2e_ufm.RWMask[0] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[1] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[2] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[3] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[4] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[5] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[6] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[7] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
===============================================================================================================
|
||||
|
||||
|
||||
|
||||
@ -672,30 +671,33 @@ Path information for path number 1:
|
||||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
= Required time: 69.369
|
||||
|
||||
- Propagation time: 2.282
|
||||
- Propagation time: 2.650
|
||||
- Clock delay at starting point: 0.000 (ideal)
|
||||
- Estimated clock delay at start point: -0.000
|
||||
= Slack (non-critical) : 67.088
|
||||
= Slack (non-critical) : 66.719
|
||||
|
||||
Number of logic level(s): 2
|
||||
Number of logic level(s): 3
|
||||
Starting point: ram2e_ufm.ufmefb.EFBInst_0 / WBACKO
|
||||
Ending point: ram2e_ufm.RWMask[0] / SP
|
||||
Ending point: ram2e_ufm.wb_cyc_stb / SP
|
||||
The start point is clocked by System [rising]
|
||||
The end point is clocked by C14M [rising] on pin CK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
----------------------------------------------------------------------------------------------------------------
|
||||
ram2e_ufm.ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 -
|
||||
wb_ack Net - - - - 5
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] ORCALUT4 B In 0.000 0.000 -
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] ORCALUT4 Z Out 1.017 1.017 -
|
||||
un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] Net - - - - 1
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 D In 0.000 1.017 -
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 Z Out 1.265 2.282 -
|
||||
N_104 Net - - - - 8
|
||||
ram2e_ufm.RWMask[0] FD1P3AX SP In 0.000 2.282 -
|
||||
================================================================================================================
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
---------------------------------------------------------------------------------------------------------------
|
||||
ram2e_ufm.ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 -
|
||||
wb_ack Net - - - - 4
|
||||
ram2e_ufm.un1_CmdBitbangMXO212_1_0_0_tz[0] ORCALUT4 B In 0.000 0.000 -
|
||||
ram2e_ufm.un1_CmdBitbangMXO212_1_0_0_tz[0] ORCALUT4 Z Out 1.017 1.017 -
|
||||
un1_CmdBitbangMXO212_1_0_0_tz[0] Net - - - - 1
|
||||
ram2e_ufm.un1_CmdBitbangMXO212_1_0_0_0[0] ORCALUT4 C In 0.000 1.017 -
|
||||
ram2e_ufm.un1_CmdBitbangMXO212_1_0_0_0[0] ORCALUT4 Z Out 1.017 2.034 -
|
||||
un1_CmdBitbangMXO212_1_0_0_0[0] Net - - - - 1
|
||||
ram2e_ufm.wb_cyc_stb_RNO_0 ORCALUT4 A In 0.000 2.034 -
|
||||
ram2e_ufm.wb_cyc_stb_RNO_0 ORCALUT4 Z Out 0.617 2.650 -
|
||||
un1_CmdBitbangMXO212_1_i[0] Net - - - - 1
|
||||
ram2e_ufm.wb_cyc_stb FD1P3AX SP In 0.000 2.650 -
|
||||
===============================================================================================================
|
||||
|
||||
|
||||
|
||||
@ -704,16 +706,16 @@ ram2e_ufm.RWMask[0] FD1P3AX SP In
|
||||
Timing exceptions that could not be applied
|
||||
None
|
||||
|
||||
Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 164MB)
|
||||
Finished final timing analysis (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 163MB)
|
||||
|
||||
|
||||
Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 164MB)
|
||||
Finished timing report (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 163MB)
|
||||
|
||||
---------------------------------------
|
||||
Resource Usage Report
|
||||
Part: lcmxo2_1200hc-4
|
||||
|
||||
Register bits: 125 of 1280 (10%)
|
||||
Register bits: 124 of 1280 (10%)
|
||||
PIC Latch: 0
|
||||
I/O cells: 70
|
||||
|
||||
@ -722,7 +724,7 @@ Details:
|
||||
BB: 8
|
||||
CCU2D: 9
|
||||
EFB: 1
|
||||
FD1P3AX: 58
|
||||
FD1P3AX: 57
|
||||
FD1P3IX: 1
|
||||
FD1S3AX: 31
|
||||
FD1S3AY: 4
|
||||
@ -735,16 +737,17 @@ OB: 41
|
||||
OFS1P3BX: 6
|
||||
OFS1P3DX: 12
|
||||
OFS1P3IX: 3
|
||||
ORCALUT4: 275
|
||||
ORCALUT4: 268
|
||||
PFUMX: 10
|
||||
PUR: 1
|
||||
VHI: 3
|
||||
VLO: 3
|
||||
Mapper successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 32MB peak: 164MB)
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:03s; Memory used current: 32MB peak: 163MB)
|
||||
|
||||
Process took 0h:00m:03s realtime, 0h:00m:03s cputime
|
||||
# Fri Jun 7 20:50:03 2024
|
||||
Process took 0h:00m:18s realtime, 0h:00m:03s cputime
|
||||
# Fri Jul 12 16:07:42 2024
|
||||
|
||||
###########################################################]
|
||||
|
||||
|
||||
@ -2,17 +2,19 @@
|
||||
Starting: parse design source files
|
||||
(VERI-1482) Analyzing Verilog file C:/lscc/diamond/3.11_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v
|
||||
(VERI-1482) Analyzing Verilog file //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v
|
||||
WARNING - //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v(140,9-140,25) (VERI-1362) CmdRWMaskSet is already implicitly declared on line 131
|
||||
WARNING - //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v(141,9-141,22) (VERI-1362) CmdLEDSet is already implicitly declared on line 131
|
||||
(VERI-1482) Analyzing Verilog file //Mac/iCloud/Repos/RAM2E/CPLD/UFM-LCMXO2.v
|
||||
(VERI-1482) Analyzing Verilog file //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC-NODHGR/REFB.v
|
||||
(VERI-1482) Analyzing Verilog file //Mac/iCloud/Repos/RAM2E/CPLD/DHGR-OFF.v
|
||||
INFO - //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v(1,8-1,13) (VERI-1018) compiling module RAM2E
|
||||
INFO - //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v(1,1-479,10) (VERI-9000) elaborating module 'RAM2E'
|
||||
INFO - //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v(1,1-476,10) (VERI-9000) elaborating module 'RAM2E'
|
||||
INFO - //Mac/iCloud/Repos/RAM2E/CPLD/UFM-LCMXO2.v(1,1-335,10) (VERI-9000) elaborating module 'RAM2E_UFM_uniq_1'
|
||||
INFO - //Mac/iCloud/Repos/RAM2E/CPLD/DHGR-OFF.v(1,1-1,68) (VERI-9000) elaborating module 'DHGR_uniq_1'
|
||||
INFO - //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC-NODHGR/REFB.v(8,1-113,10) (VERI-9000) elaborating module 'REFB_uniq_1'
|
||||
INFO - C:/lscc/diamond/3.11_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_1'
|
||||
INFO - C:/lscc/diamond/3.11_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_1'
|
||||
INFO - C:/lscc/diamond/3.11_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1800,1-1872,10) (VERI-9000) elaborating module 'EFB_uniq_1'
|
||||
Done: design load finished with (0) errors, and (0) warnings
|
||||
Done: design load finished with (0) errors, and (2) warnings
|
||||
|
||||
</PRE></BODY></HTML>
|
||||
@ -1,3 +1,3 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<userSetting name="//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC-NODHGR/promote.xml" version="Diamond (64-bit) 3.11.3.469" date="Sat Jun 08 04:44:52 2024" vendor="Lattice Semiconductor Corporation" >
|
||||
<userSetting name="//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC-NODHGR/promote.xml" version="Diamond (64-bit) 3.11.3.469" date="Fri Jul 12 16:09:34 2024" vendor="Lattice Semiconductor Corporation" >
|
||||
</userSetting>
|
||||
|
||||
70
CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC_tcl.html
Normal file
70
CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC_tcl.html
Normal file
@ -0,0 +1,70 @@
|
||||
<HTML>
|
||||
<HEAD><TITLE>Lattice TCL Log</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="pn240608044451"></A><B><U><big>pn240608044451</big></U></B>
|
||||
#Start recording tcl command: 6/7/2024 20:49:34
|
||||
#Project Location: //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC; Project name: RAM2E_LCMXO2_1200HC
|
||||
prj_project open "//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC.ldf"
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
#Stop recording: 6/8/2024 04:44:51
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
@ -1,6 +1,6 @@
|
||||
NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
|
||||
NOTE All Rights Reserved *
|
||||
NOTE DATE CREATED: Fri Jun 07 20:50:35 2024 *
|
||||
NOTE DATE CREATED: Fri Jul 12 16:09:06 2024 *
|
||||
NOTE DESIGN NAME: RAM2E *
|
||||
NOTE DEVICE NAME: LCMXO2-1200HC-4TQFP100 *
|
||||
NOTE PIN ASSIGNMENTS *
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
----------------------------------------------------------------------
|
||||
Report for cell RAM2E.verilog
|
||||
|
||||
Register bits: 125 of 1280 (10%)
|
||||
Register bits: 124 of 1280 (10%)
|
||||
PIC Latch: 0
|
||||
I/O cells: 70
|
||||
Cell usage:
|
||||
@ -9,7 +9,7 @@ I/O cells: 70
|
||||
BB 8 100.0
|
||||
CCU2D 9 100.0
|
||||
EFB 1 100.0
|
||||
FD1P3AX 58 100.0
|
||||
FD1P3AX 57 100.0
|
||||
FD1P3IX 1 100.0
|
||||
FD1S3AX 31 100.0
|
||||
FD1S3AY 4 100.0
|
||||
@ -22,7 +22,8 @@ I/O cells: 70
|
||||
OFS1P3BX 6 100.0
|
||||
OFS1P3DX 12 100.0
|
||||
OFS1P3IX 3 100.0
|
||||
ORCALUT4 275 100.0
|
||||
ORCALUT4 268 100.0
|
||||
PFUMX 10 100.0
|
||||
PUR 1 100.0
|
||||
VHI 3 100.0
|
||||
VLO 3 100.0
|
||||
@ -30,23 +31,24 @@ SUB MODULES
|
||||
RAM2E_UFM 1 100.0
|
||||
REFB 1 100.0
|
||||
|
||||
TOTAL 494
|
||||
TOTAL 496
|
||||
----------------------------------------------------------------------
|
||||
Report for cell RAM2E_UFM.netlist
|
||||
Instance path: ram2e_ufm
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
EFB 1 100.0
|
||||
FD1P3AX 29 50.0
|
||||
FD1P3AX 29 50.9
|
||||
FD1P3IX 1 100.0
|
||||
FD1S3IX 1 11.1
|
||||
ORCALUT4 268 97.5
|
||||
ORCALUT4 260 97.0
|
||||
PFUMX 10 100.0
|
||||
VHI 2 66.7
|
||||
VLO 2 66.7
|
||||
SUB MODULES
|
||||
REFB 1 100.0
|
||||
|
||||
TOTAL 305
|
||||
TOTAL 307
|
||||
----------------------------------------------------------------------
|
||||
Report for cell REFB.netlist
|
||||
Instance path: ram2e_ufm.ufmefb
|
||||
|
||||
@ -4,10 +4,10 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Fri Jun 07 20:50:31 2024
|
||||
Fri Jul 12 16:09:00 2024
|
||||
|
||||
|
||||
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC -w -jedec -gui RAM2E_LCMXO2_1200HC_impl1.ncd RAM2E_LCMXO2_1200HC_impl1.prf
|
||||
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC -w -jedec -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1.ncd RAM2E_LCMXO2_1200HC_impl1.prf
|
||||
|
||||
Loading design for application Bitgen from file RAM2E_LCMXO2_1200HC_impl1.ncd.
|
||||
Design name: RAM2E
|
||||
@ -81,6 +81,6 @@ UFM Utilization: General Purpose Flash Memory.
|
||||
Available General Purpose Flash Memory: 511 Pages (Page 0 to Page 510).
|
||||
Initialized UFM Pages: 321 Pages (Page 190 to Page 510).
|
||||
|
||||
Total CPU Time: 3 secs
|
||||
Total REAL Time: 4 secs
|
||||
Total CPU Time: 4 secs
|
||||
Total REAL Time: 6 secs
|
||||
Peak Memory Usage: 275 MB
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -9,25 +9,26 @@ Command line: map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 4 -oc Commercial
|
||||
RAM2E_LCMXO2_1200HC_impl1.ngd -o RAM2E_LCMXO2_1200HC_impl1_map.ncd -pr
|
||||
RAM2E_LCMXO2_1200HC_impl1.prf -mp RAM2E_LCMXO2_1200HC_impl1.mrp -lpf //Mac/
|
||||
iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_synpl
|
||||
ify.lpf -lpf //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf -c 0 -gui
|
||||
ify.lpf -lpf //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf -c 0 -gui
|
||||
-msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml
|
||||
Target Vendor: LATTICE
|
||||
Target Device: LCMXO2-1200HCTQFP100
|
||||
Target Performance: 4
|
||||
Mapper: xo2c00, version: Diamond (64-bit) 3.11.3.469
|
||||
Mapped on: 06/07/24 20:50:13
|
||||
Mapped on: 07/12/24 16:08:07
|
||||
|
||||
Design Summary
|
||||
--------------
|
||||
|
||||
Number of registers: 125 out of 1520 (8%)
|
||||
PFU registers: 103 out of 1280 (8%)
|
||||
Number of registers: 124 out of 1520 (8%)
|
||||
PFU registers: 102 out of 1280 (8%)
|
||||
PIO registers: 22 out of 240 (9%)
|
||||
Number of SLICEs: 148 out of 640 (23%)
|
||||
SLICEs as Logic/ROM: 148 out of 640 (23%)
|
||||
Number of SLICEs: 145 out of 640 (23%)
|
||||
SLICEs as Logic/ROM: 145 out of 640 (23%)
|
||||
SLICEs as RAM: 0 out of 480 (0%)
|
||||
SLICEs as Carry: 9 out of 640 (1%)
|
||||
Number of LUT4s: 295 out of 1280 (23%)
|
||||
Number used as logic LUTs: 277
|
||||
Number of LUT4s: 288 out of 1280 (23%)
|
||||
Number used as logic LUTs: 270
|
||||
Number used as distributed RAM: 0
|
||||
Number used as ripple logic: 18
|
||||
Number used as shift registers: 0
|
||||
@ -57,53 +58,54 @@ Design Summary
|
||||
2. Number of logic LUT4s does not include count of distributed RAM and
|
||||
ripple logic.
|
||||
Number of clocks: 2
|
||||
Net C14M_c: 85 loads, 63 rising, 22 falling (Driver: PIO C14M )
|
||||
Net C14M_c: 84 loads, 62 rising, 22 falling (Driver: PIO C14M )
|
||||
Net PHI1_c: 3 loads, 0 rising, 3 falling (Driver: PIO PHI1 )
|
||||
Number of Clock Enables: 13
|
||||
|
||||
Page 1
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 06/07/24 20:50:13
|
||||
Design: RAM2E Date: 07/12/24 16:08:07
|
||||
|
||||
Design Summary (cont)
|
||||
---------------------
|
||||
Net N_117_i: 2 loads, 0 LSLICEs
|
||||
Net RWBank14: 11 loads, 11 LSLICEs
|
||||
Number of Clock Enables: 13
|
||||
Net N_347_i: 2 loads, 0 LSLICEs
|
||||
Net RWBank14: 10 loads, 10 LSLICEs
|
||||
Net ram2e_ufm/wb_adr_0_sqmuxa_1_i: 1 loads, 1 LSLICEs
|
||||
Net un9_VOE_0_a2_0_a2: 1 loads, 1 LSLICEs
|
||||
Net un6_DOEEN_0_a2_0_a2: 2 loads, 2 LSLICEs
|
||||
Net ram2e_ufm/un1_wb_adr_0_sqmuxa_2_i[0]: 8 loads, 8 LSLICEs
|
||||
Net ram2e_ufm/un1_wb_cyc_stb_0_sqmuxa_1_i[0]: 1 loads, 1 LSLICEs
|
||||
Net ram2e_ufm/N_111: 1 loads, 1 LSLICEs
|
||||
Net ram2e_ufm/N_104: 4 loads, 4 LSLICEs
|
||||
Net ram2e_ufm/N_98: 1 loads, 1 LSLICEs
|
||||
Net un1_CKE48_0_i: 6 loads, 6 LSLICEs
|
||||
Net N_389_i: 2 loads, 0 LSLICEs
|
||||
Net ram2e_ufm/N_63: 1 loads, 1 LSLICEs
|
||||
Net ram2e_ufm/un1_wb_adr_0_sqmuxa_2_i_0[0]: 8 loads, 8 LSLICEs
|
||||
Net ram2e_ufm/un1_CmdBitbangMXO212_1_i[0]: 1 loads, 1 LSLICEs
|
||||
Net ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0[0]: 4 loads, 4 LSLICEs
|
||||
Net ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0[0]: 1 loads, 1 LSLICEs
|
||||
Net un9_VOE_0_a2: 1 loads, 1 LSLICEs
|
||||
Net un1_CKE48_i: 6 loads, 6 LSLICEs
|
||||
Net N_346_i: 2 loads, 0 LSLICEs
|
||||
Net Vout3: 8 loads, 0 LSLICEs
|
||||
Number of LSRs: 8
|
||||
Net N_148: 2 loads, 2 LSLICEs
|
||||
Net N_430_i: 2 loads, 0 LSLICEs
|
||||
Number of LSRs: 9
|
||||
Net un1_CS_0_sqmuxa_i: 2 loads, 2 LSLICEs
|
||||
Net ram2e_ufm.wb_rst13: 2 loads, 0 LSLICEs
|
||||
Net RC7: 2 loads, 2 LSLICEs
|
||||
Net S[2]: 2 loads, 2 LSLICEs
|
||||
Net S[1]: 1 loads, 1 LSLICEs
|
||||
Net ram2e_ufm/wb_rst: 1 loads, 0 LSLICEs
|
||||
Net ram2e_ufm/nRWE_0_i_o3_RNIP8E61: 1 loads, 1 LSLICEs
|
||||
Net N_530: 1 loads, 0 LSLICEs
|
||||
Net N_301_i: 1 loads, 1 LSLICEs
|
||||
Net ram2e_ufm/wb_rst6_i: 1 loads, 1 LSLICEs
|
||||
Net N_523_1: 1 loads, 0 LSLICEs
|
||||
Net N_727_0: 1 loads, 1 LSLICEs
|
||||
Net RATc_i: 1 loads, 1 LSLICEs
|
||||
Number of nets driven by tri-state buffers: 0
|
||||
Top 10 highest fanout non-clock nets:
|
||||
Net S[2]: 60 loads
|
||||
Net S[3]: 48 loads
|
||||
Net S[1]: 46 loads
|
||||
Net S[0]: 31 loads
|
||||
Net FS[11]: 24 loads
|
||||
Net FS[10]: 23 loads
|
||||
Net FS[12]: 23 loads
|
||||
Net FS[9]: 23 loads
|
||||
Net FS[13]: 21 loads
|
||||
Net FS[8]: 18 loads
|
||||
Net S[2]: 51 loads
|
||||
Net S[1]: 44 loads
|
||||
Net S[3]: 40 loads
|
||||
Net S[0]: 32 loads
|
||||
Net FS[8]: 29 loads
|
||||
Net FS[9]: 26 loads
|
||||
Net FS[10]: 25 loads
|
||||
Net FS[11]: 23 loads
|
||||
Net FS[13]: 20 loads
|
||||
Net ram2e_ufm.wb_rst13: 17 loads
|
||||
|
||||
|
||||
|
||||
@ -124,16 +126,18 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
||||
Functionality is restored after the Flash Memory (UFM/Configuration)
|
||||
Interface is disabled using Disable Configuration Interface command 0x26
|
||||
followed by Bypass command 0xFF.
|
||||
WARNING - map: IO buffer missing for top level port nWE80...logic will be
|
||||
discarded.
|
||||
|
||||
Page 2
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 06/07/24 20:50:13
|
||||
Design: RAM2E Date: 07/12/24 16:08:07
|
||||
|
||||
Design Errors/Warnings (cont)
|
||||
-----------------------------
|
||||
WARNING - map: IO buffer missing for top level port nWE80...logic will be
|
||||
discarded.
|
||||
|
||||
IO (PIO) Attributes
|
||||
-------------------
|
||||
@ -187,10 +191,6 @@ IO (PIO) Attributes
|
||||
| RAout[2] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RAout[1] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RAout[0] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| BA[1] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
Page 3
|
||||
@ -198,10 +198,14 @@ IO (PIO) Attributes
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 06/07/24 20:50:13
|
||||
Design: RAM2E Date: 07/12/24 16:08:07
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
| RAout[0] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| BA[1] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| BA[0] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRWEout | OUTPUT | LVCMOS33 | OUT |
|
||||
@ -253,10 +257,6 @@ IO (PIO) Attributes (cont)
|
||||
| Din[7] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[6] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[5] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[4] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
Page 4
|
||||
@ -264,10 +264,14 @@ IO (PIO) Attributes (cont)
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 06/07/24 20:50:13
|
||||
Design: RAM2E Date: 07/12/24 16:08:07
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
| Din[5] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[4] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[3] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[2] | INPUT | LVCMOS33 | |
|
||||
@ -320,20 +324,20 @@ Signal ram2e_ufm/ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/CFGWAKE undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/wbc_ufm_irq undriven or does not drive anything -
|
||||
clipped.
|
||||
Signal ram2e_ufm/ufmefb/TCOC undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/TCINT undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIIRQO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPICSNEN undriven or does not drive anything - clipped.
|
||||
|
||||
Page 5
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 06/07/24 20:50:13
|
||||
Design: RAM2E Date: 07/12/24 16:08:07
|
||||
|
||||
Removed logic (cont)
|
||||
--------------------
|
||||
Signal ram2e_ufm/ufmefb/TCOC undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/TCINT undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIIRQO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPICSNEN undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
|
||||
@ -386,20 +390,20 @@ Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped.
|
||||
Signal N_1 undriven or does not drive anything - clipped.
|
||||
Block RefReq.CN was optimized away.
|
||||
Block RDOE_RNIAM8C was optimized away.
|
||||
Block nCASout.CN was optimized away.
|
||||
Block ram2e_ufm/ufmefb/VCC was optimized away.
|
||||
Block ram2e_ufm/ufmefb/GND was optimized away.
|
||||
|
||||
|
||||
Page 6
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 06/07/24 20:50:13
|
||||
Design: RAM2E Date: 07/12/24 16:08:07
|
||||
|
||||
Removed logic (cont)
|
||||
--------------------
|
||||
Block nCASout.CN was optimized away.
|
||||
Block ram2e_ufm/ufmefb/VCC was optimized away.
|
||||
Block ram2e_ufm/ufmefb/GND was optimized away.
|
||||
|
||||
|
||||
|
||||
Embedded Functional Block Connection Summary
|
||||
@ -449,15 +453,77 @@ Instance Name: ram2e_ufm/ufmefb/EFBInst_0
|
||||
Run Time and Memory Usage
|
||||
-------------------------
|
||||
|
||||
Total CPU Time: 0 secs
|
||||
Total REAL Time: 2 secs
|
||||
Total CPU Time: 1 secs
|
||||
Total REAL Time: 12 secs
|
||||
Peak Memory Usage: 64 MB
|
||||
|
||||
Page 7
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 07/12/24 16:08:07
|
||||
|
||||
Run Time and Memory Usage (cont)
|
||||
--------------------------------
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Page 7
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Page 8
|
||||
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
|
||||
@ -6,7 +6,7 @@ Performance Grade: 4
|
||||
PACKAGE: TQFP100
|
||||
Package Status: Final Version 1.42
|
||||
|
||||
Fri Jun 07 20:50:24 2024
|
||||
Fri Jul 12 16:08:36 2024
|
||||
|
||||
Pinout by Port Name:
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
@ -311,5 +311,5 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Fri Jun 07 20:50:28 2024
|
||||
Fri Jul 12 16:08:42 2024
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
SCHEMATIC START ;
|
||||
# map: version Diamond (64-bit) 3.11.3.469 -- WARNING: Map write only section -- Fri Jun 07 20:50:14 2024
|
||||
# map: version Diamond (64-bit) 3.11.3.469 -- WARNING: Map write only section -- Fri Jul 12 16:08:08 2024
|
||||
|
||||
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
|
||||
LOCATE COMP "RD[0]" SITE "36" ;
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
#OS: Windows 8 6.2
|
||||
#Hostname: ZANEMACWIN11
|
||||
|
||||
# Fri Jun 7 20:50:04 2024
|
||||
# Fri Jul 12 16:07:08 2024
|
||||
|
||||
#Implementation: impl1
|
||||
|
||||
@ -52,6 +52,7 @@ Synopsys Verilog Compiler, Version comp2018q2p1, Build 461R, Built Apr 1 2019 0
|
||||
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\REFB.v" (library work)
|
||||
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\DHGR-ON.v" (library work)
|
||||
Verilog syntax check successful!
|
||||
File \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v changed - recompiling
|
||||
Selecting top level module RAM2E
|
||||
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
|
||||
Running optimization stage 1 on VHI .......
|
||||
@ -77,12 +78,12 @@ Running optimization stage 2 on EFB .......
|
||||
Running optimization stage 2 on VLO .......
|
||||
Running optimization stage 2 on VHI .......
|
||||
|
||||
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)
|
||||
At c_ver Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
Process took 0h:00m:03s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Fri Jun 7 20:50:05 2024
|
||||
# Fri Jul 12 16:07:14 2024
|
||||
|
||||
###########################################################]
|
||||
|
||||
@ -102,13 +103,14 @@ Implementation : impl1
|
||||
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
File \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\layer0.srs changed - recompiling
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Fri Jun 7 20:50:05 2024
|
||||
# Fri Jul 12 16:07:14 2024
|
||||
|
||||
###########################################################]
|
||||
|
||||
@ -118,12 +120,12 @@ For a summary of runtime and memory usage for all design units, please see file:
|
||||
|
||||
@END
|
||||
|
||||
At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
|
||||
At c_hdl Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
Process took 0h:00m:04s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Fri Jun 7 20:50:05 2024
|
||||
# Fri Jul 12 16:07:14 2024
|
||||
|
||||
###########################################################]
|
||||
|
||||
@ -143,18 +145,17 @@ Database state : \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\|impl
|
||||
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
File \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_comp.srs changed - recompiling
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 68MB)
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 68MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Fri Jun 7 20:50:07 2024
|
||||
# Fri Jul 12 16:07:18 2024
|
||||
|
||||
###########################################################]
|
||||
Premap Report
|
||||
|
||||
# Fri Jun 7 20:50:07 2024
|
||||
# Fri Jul 12 16:07:19 2024
|
||||
|
||||
|
||||
Copyright (C) 1994-2018 Synopsys, Inc.
|
||||
@ -183,26 +184,26 @@ Printing clock summary report in "\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\i
|
||||
@N: MF248 |Running in 64-bit mode.
|
||||
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
|
||||
|
||||
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
|
||||
Design Input Complete (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
|
||||
|
||||
|
||||
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
|
||||
Mapper Initialization Complete (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
|
||||
|
||||
|
||||
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB)
|
||||
Start loading timing files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB)
|
||||
|
||||
|
||||
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB)
|
||||
Finished loading timing files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB)
|
||||
|
||||
@N: MF284 |Setting synthesis effort to medium for the design
|
||||
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
|
||||
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":21:4:21:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
|
||||
@N: MH105 |UMR3 is only supported for HAPS-80.
|
||||
@N: MH105 |UMR3 is only supported for HAPS-80.
|
||||
@N: BN115 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":140:9:140:12|Removing instance dhgr (in view: work.RAM2E(verilog)) of type view:work.DHGR(verilog) because it does not drive other instances.
|
||||
@N: BN115 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":136:9:136:12|Removing instance dhgr (in view: work.RAM2E(verilog)) of type view:work.DHGR(verilog) because it does not drive other instances.
|
||||
syn_allowed_resources : blockrams=7 set on top level netlist RAM2E
|
||||
|
||||
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
|
||||
Finished netlist restructuring (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
|
||||
|
||||
|
||||
|
||||
@ -212,7 +213,7 @@ Clock Summary
|
||||
Start Requested Requested Clock Clock Clock
|
||||
Level Clock Frequency Period Type Group Load
|
||||
-----------------------------------------------------------------------------------------------
|
||||
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 121
|
||||
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 120
|
||||
|
||||
0 - System 100.0 MHz 10.000 system system_clkgroup 0
|
||||
|
||||
@ -227,7 +228,7 @@ Clock Load Summary
|
||||
Clock Source Clock Pin Non-clock Pin Non-clock Pin
|
||||
Clock Load Pin Seq Example Seq Example Comb Example
|
||||
--------------------------------------------------------------------------------------------
|
||||
C14M 121 C14M(port) RAT.C - un1_C14M.I[0](inv)
|
||||
C14M 120 C14M(port) RAT.C - un1_C14M.I[0](inv)
|
||||
|
||||
System 0 - - - -
|
||||
|
||||
@ -247,14 +248,14 @@ Number of ICG latches not removed: 0
|
||||
|
||||
#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
|
||||
|
||||
2 non-gated/non-generated clock tree(s) driving 125 clock pin(s) of sequential element(s)
|
||||
2 non-gated/non-generated clock tree(s) driving 124 clock pin(s) of sequential element(s)
|
||||
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
|
||||
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
|
||||
|
||||
=========================== Non-Gated/Non-Generated Clocks ============================
|
||||
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
|
||||
---------------------------------------------------------------------------------------
|
||||
@KP:ckid0_0 C14M port 121 PHI1r
|
||||
@KP:ckid0_0 C14M port 120 PHI1r
|
||||
@KP:ckid0_1 PHI1 Unconstrained_port 4 RC[2:0]
|
||||
=======================================================================================
|
||||
|
||||
@ -264,27 +265,25 @@ Clock Tree ID Driving Element Drive Element Type Fanout Sample I
|
||||
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
|
||||
Finished Pre Mapping Phase.
|
||||
|
||||
Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
|
||||
Starting constraint checker (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
|
||||
|
||||
|
||||
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
|
||||
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
|
||||
|
||||
None
|
||||
None
|
||||
|
||||
Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
|
||||
Finished constraint checker (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
|
||||
|
||||
Pre-mapping successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB)
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Fri Jun 7 20:50:08 2024
|
||||
Process took 0h:00m:08s realtime, 0h:00m:01s cputime
|
||||
# Fri Jul 12 16:07:28 2024
|
||||
|
||||
###########################################################]
|
||||
Map & Optimize Report
|
||||
|
||||
# Fri Jun 7 20:50:08 2024
|
||||
# Fri Jul 12 16:07:30 2024
|
||||
|
||||
|
||||
Copyright (C) 1994-2018 Synopsys, Inc.
|
||||
@ -310,21 +309,21 @@ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:0
|
||||
@N: MF248 |Running in 64-bit mode.
|
||||
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
|
||||
|
||||
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
|
||||
Design Input Complete (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
|
||||
|
||||
|
||||
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
|
||||
Mapper Initialization Complete (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
|
||||
|
||||
|
||||
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
|
||||
Start loading timing files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
|
||||
|
||||
|
||||
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
|
||||
Finished loading timing files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
|
||||
|
||||
@N: MF284 |Setting synthesis effort to medium for the design
|
||||
|
||||
|
||||
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
|
||||
Starting Optimization and Mapping (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
|
||||
|
||||
|
||||
Available hyper_sources - for debug and ip models
|
||||
@ -333,61 +332,61 @@ Available hyper_sources - for debug and ip models
|
||||
@N: FX493 |Applying initial value "00000000" on instance RWBank[7:0].
|
||||
@N: FX493 |Applying initial value "0000" on instance S[3:0].
|
||||
|
||||
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)
|
||||
Finished RTL optimizations (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)
|
||||
|
||||
@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":14:23:14:28|Found counter in view:work.RAM2E(verilog) instance FS[15:0]
|
||||
|
||||
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 142MB)
|
||||
Starting factoring (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 142MB)
|
||||
|
||||
|
||||
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
|
||||
Finished factoring (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
|
||||
|
||||
|
||||
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
|
||||
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
|
||||
|
||||
|
||||
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
|
||||
Starting Early Timing Optimization (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
|
||||
|
||||
|
||||
Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
|
||||
Finished Early Timing Optimization (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
|
||||
|
||||
|
||||
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
|
||||
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
|
||||
|
||||
|
||||
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
|
||||
Finished preparing to map (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 147MB)
|
||||
|
||||
|
||||
Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
|
||||
Finished technology mapping (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
|
||||
|
||||
Pass CPU time Worst Slack Luts / Registers
|
||||
------------------------------------------------------------
|
||||
1 0h:00m:01s 6.90ns 281 / 125
|
||||
1 0h:00m:01s 6.90ns 280 / 124
|
||||
|
||||
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
|
||||
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
|
||||
|
||||
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
|
||||
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":171:4:171:9|Boundary register BA_1_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
||||
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":171:4:171:9|Boundary register BA_0_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
||||
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":168:4:168:9|Boundary register BA_1_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
||||
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":168:4:168:9|Boundary register BA_0_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
||||
|
||||
Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 158MB peak: 160MB)
|
||||
Finished restoring hierarchy (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:01s; Memory used current: 158MB peak: 160MB)
|
||||
|
||||
|
||||
Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 122MB peak: 160MB)
|
||||
Start Writing Netlists (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:01s; Memory used current: 122MB peak: 160MB)
|
||||
|
||||
Writing Analyst data base \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_m.srm
|
||||
|
||||
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 158MB peak: 160MB)
|
||||
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:02s; Memory used current: 157MB peak: 160MB)
|
||||
|
||||
Writing EDIF Netlist and constraint files
|
||||
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1.edi
|
||||
N-2018.03L-SP1-1
|
||||
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
|
||||
|
||||
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 162MB peak: 164MB)
|
||||
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 163MB)
|
||||
|
||||
|
||||
Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 161MB peak: 164MB)
|
||||
Start final timing analysis (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:03s; Memory used current: 160MB peak: 163MB)
|
||||
|
||||
@W: MT246 :"\\mac\icloud\repos\ram2e\cpld\lcmxo2-1200hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
|
||||
@N: MT615 |Found clock C14M with period 69.84ns
|
||||
@ -395,7 +394,7 @@ Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:0
|
||||
|
||||
|
||||
##### START OF TIMING REPORT #####[
|
||||
# Timing Report written on Fri Jun 7 20:50:12 2024
|
||||
# Timing Report written on Fri Jul 12 16:07:46 2024
|
||||
#
|
||||
|
||||
|
||||
@ -420,9 +419,9 @@ Worst slack in design: 6.897
|
||||
Requested Estimated Requested Estimated Clock Clock
|
||||
Starting Clock Frequency Frequency Period Period Slack Type Group
|
||||
----------------------------------------------------------------------------------------------------------------------
|
||||
C14M 14.3 MHz 112.1 MHz 69.841 8.918 31.599 declared default_clkgroup
|
||||
C14M 14.3 MHz 120.3 MHz 69.841 8.314 31.675 declared default_clkgroup
|
||||
RAM2E|PHI1 100.0 MHz 322.2 MHz 10.000 3.103 6.897 inferred Inferred_clkgroup_0
|
||||
System 100.0 MHz NA 10.000 NA 67.088 system system_clkgroup
|
||||
System 100.0 MHz NA 10.000 NA 66.719 system system_clkgroup
|
||||
======================================================================================================================
|
||||
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
|
||||
|
||||
@ -437,9 +436,9 @@ Clocks | rise to rise | fall to fall | rise
|
||||
----------------------------------------------------------------------------------------------------------------
|
||||
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
|
||||
----------------------------------------------------------------------------------------------------------------
|
||||
System C14M | 69.841 67.088 | No paths - | No paths - | No paths -
|
||||
System C14M | 69.841 66.719 | No paths - | No paths - | No paths -
|
||||
C14M System | 69.841 68.797 | No paths - | No paths - | No paths -
|
||||
C14M C14M | 69.841 60.923 | No paths - | 34.920 31.599 | No paths -
|
||||
C14M C14M | 69.841 61.527 | No paths - | 34.920 31.675 | No paths -
|
||||
RAM2E|PHI1 C14M | No paths - | No paths - | No paths - | Diff grp -
|
||||
RAM2E|PHI1 RAM2E|PHI1 | No paths - | 10.000 6.897 | No paths - | No paths -
|
||||
================================================================================================================
|
||||
@ -468,10 +467,10 @@ Starting Points with Worst Slack
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
---------------------------------------------------------------------------
|
||||
S[2] C14M FD1S3AX Q S[2] 1.366 31.599
|
||||
S[3] C14M FD1S3AX Q S[3] 1.345 31.619
|
||||
S[1] C14M FD1S3AX Q S[1] 1.344 31.800
|
||||
S[0] C14M FD1S3AX Q S[0] 1.305 31.838
|
||||
S[2] C14M FD1S3AX Q S[2] 1.353 31.675
|
||||
S[3] C14M FD1S3AX Q S[3] 1.337 31.691
|
||||
S[0] C14M FD1S3AX Q S[0] 1.319 32.182
|
||||
S[1] C14M FD1S3AX Q S[1] 1.344 32.656
|
||||
RA[0] C14M FD1P3AX Q RA[0] 1.108 33.707
|
||||
RA[3] C14M FD1P3AX Q RA[3] 1.108 33.707
|
||||
RA[1] C14M FD1P3AX Q RA[1] 1.044 33.771
|
||||
@ -484,21 +483,21 @@ RA[5] C14M FD1P3AX Q RA[5] 1.044 33.771
|
||||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
-----------------------------------------------------------------------------------
|
||||
VOE_i_0io C14M OFS1P3IX CD N_530 34.118 31.599
|
||||
VOE_i_0io C14M OFS1P3IX D VOE_ic_i 35.009 31.800
|
||||
Vout_0io[0] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[1] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[2] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[3] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[4] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[5] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[6] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[7] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
===================================================================================
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------------
|
||||
VOE_i_0io C14M OFS1P3IX CD N_523_1 34.118 31.675
|
||||
RAT C14M FD1S3IX CD RATc_i 34.118 32.147
|
||||
Vout_0io[0] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[1] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[2] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[3] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[4] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[5] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[6] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[7] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
==================================================================================
|
||||
|
||||
|
||||
|
||||
@ -512,9 +511,9 @@ Path information for path number 1:
|
||||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
= Required time: 34.118
|
||||
|
||||
- Propagation time: 2.519
|
||||
- Propagation time: 2.442
|
||||
- Clock delay at starting point: 0.000 (ideal)
|
||||
= Slack (non-critical) : 31.599
|
||||
= Slack (non-critical) : 31.675
|
||||
|
||||
Number of logic level(s): 1
|
||||
Starting point: S[2] / Q
|
||||
@ -522,16 +521,16 @@ Path information for path number 1:
|
||||
The start point is clocked by C14M [rising] on pin CK
|
||||
The end point is clocked by C14M [falling] on pin SCLK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
------------------------------------------------------------------------------------------------------------
|
||||
S[2] FD1S3AX Q Out 1.366 1.366 -
|
||||
S[2] Net - - - - 58
|
||||
ram2e_ufm.un1_wb_adr_0_sqmuxa_2_0_a2_0[0] ORCALUT4 A In 0.000 1.366 -
|
||||
ram2e_ufm.un1_wb_adr_0_sqmuxa_2_0_a2_0[0] ORCALUT4 Z Out 1.153 2.519 -
|
||||
N_530 Net - - - - 3
|
||||
VOE_i_0io OFS1P3IX CD In 0.000 2.519 -
|
||||
============================================================================================================
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
---------------------------------------------------------------------------------------
|
||||
S[2] FD1S3AX Q Out 1.353 1.353 -
|
||||
S[2] Net - - - - 50
|
||||
ram2e_ufm.VOE_2_0_a2 ORCALUT4 A In 0.000 1.353 -
|
||||
ram2e_ufm.VOE_2_0_a2 ORCALUT4 Z Out 1.089 2.442 -
|
||||
N_523_1 Net - - - - 2
|
||||
VOE_i_0io OFS1P3IX CD In 0.000 2.442 -
|
||||
=======================================================================================
|
||||
|
||||
|
||||
|
||||
@ -620,7 +619,7 @@ Starting Points with Worst Slack
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
---------------------------------------------------------------------------------------------------
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBACKO wb_ack 0.000 67.088
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBACKO wb_ack 0.000 66.719
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO0 wb_dato[0] 0.000 69.313
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000 69.313
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO2 wb_dato[2] 0.000 69.313
|
||||
@ -635,21 +634,21 @@ ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO7 wb_dato[7]
|
||||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------------------
|
||||
ram2e_ufm.RWMask[0] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[1] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[2] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[3] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[4] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[5] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[6] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[7] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.LEDEN System FD1P3AX SP N_98 69.369 67.736
|
||||
ram2e_ufm.wb_cyc_stb System FD1P3AX SP N_111 69.369 67.736
|
||||
========================================================================================
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
---------------------------------------------------------------------------------------------------------------
|
||||
ram2e_ufm.wb_cyc_stb System FD1P3AX SP un1_CmdBitbangMXO212_1_i[0] 69.369 66.719
|
||||
ram2e_ufm.LEDEN System FD1P3AX SP un1_LEDEN_0_sqmuxa_1_i_0[0] 69.369 67.736
|
||||
ram2e_ufm.RWMask[0] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[1] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[2] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[3] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[4] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[5] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[6] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[7] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
===============================================================================================================
|
||||
|
||||
|
||||
|
||||
@ -663,30 +662,33 @@ Path information for path number 1:
|
||||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
= Required time: 69.369
|
||||
|
||||
- Propagation time: 2.282
|
||||
- Propagation time: 2.650
|
||||
- Clock delay at starting point: 0.000 (ideal)
|
||||
- Estimated clock delay at start point: -0.000
|
||||
= Slack (non-critical) : 67.088
|
||||
= Slack (non-critical) : 66.719
|
||||
|
||||
Number of logic level(s): 2
|
||||
Number of logic level(s): 3
|
||||
Starting point: ram2e_ufm.ufmefb.EFBInst_0 / WBACKO
|
||||
Ending point: ram2e_ufm.RWMask[0] / SP
|
||||
Ending point: ram2e_ufm.wb_cyc_stb / SP
|
||||
The start point is clocked by System [rising]
|
||||
The end point is clocked by C14M [rising] on pin CK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
----------------------------------------------------------------------------------------------------------------
|
||||
ram2e_ufm.ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 -
|
||||
wb_ack Net - - - - 5
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] ORCALUT4 B In 0.000 0.000 -
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] ORCALUT4 Z Out 1.017 1.017 -
|
||||
un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] Net - - - - 1
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 D In 0.000 1.017 -
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 Z Out 1.265 2.282 -
|
||||
N_104 Net - - - - 8
|
||||
ram2e_ufm.RWMask[0] FD1P3AX SP In 0.000 2.282 -
|
||||
================================================================================================================
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
---------------------------------------------------------------------------------------------------------------
|
||||
ram2e_ufm.ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 -
|
||||
wb_ack Net - - - - 4
|
||||
ram2e_ufm.un1_CmdBitbangMXO212_1_0_0_tz[0] ORCALUT4 B In 0.000 0.000 -
|
||||
ram2e_ufm.un1_CmdBitbangMXO212_1_0_0_tz[0] ORCALUT4 Z Out 1.017 1.017 -
|
||||
un1_CmdBitbangMXO212_1_0_0_tz[0] Net - - - - 1
|
||||
ram2e_ufm.un1_CmdBitbangMXO212_1_0_0_0[0] ORCALUT4 C In 0.000 1.017 -
|
||||
ram2e_ufm.un1_CmdBitbangMXO212_1_0_0_0[0] ORCALUT4 Z Out 1.017 2.034 -
|
||||
un1_CmdBitbangMXO212_1_0_0_0[0] Net - - - - 1
|
||||
ram2e_ufm.wb_cyc_stb_RNO_0 ORCALUT4 A In 0.000 2.034 -
|
||||
ram2e_ufm.wb_cyc_stb_RNO_0 ORCALUT4 Z Out 0.617 2.650 -
|
||||
un1_CmdBitbangMXO212_1_i[0] Net - - - - 1
|
||||
ram2e_ufm.wb_cyc_stb FD1P3AX SP In 0.000 2.650 -
|
||||
===============================================================================================================
|
||||
|
||||
|
||||
|
||||
@ -695,16 +697,16 @@ ram2e_ufm.RWMask[0] FD1P3AX SP In
|
||||
Timing exceptions that could not be applied
|
||||
None
|
||||
|
||||
Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 161MB peak: 164MB)
|
||||
Finished final timing analysis (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 163MB)
|
||||
|
||||
|
||||
Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 161MB peak: 164MB)
|
||||
Finished timing report (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 163MB)
|
||||
|
||||
---------------------------------------
|
||||
Resource Usage Report
|
||||
Part: lcmxo2_1200hc-4
|
||||
|
||||
Register bits: 125 of 1280 (10%)
|
||||
Register bits: 124 of 1280 (10%)
|
||||
PIC Latch: 0
|
||||
I/O cells: 70
|
||||
|
||||
@ -713,7 +715,7 @@ Details:
|
||||
BB: 8
|
||||
CCU2D: 9
|
||||
EFB: 1
|
||||
FD1P3AX: 58
|
||||
FD1P3AX: 57
|
||||
FD1P3IX: 1
|
||||
FD1S3AX: 31
|
||||
FD1S3AY: 4
|
||||
@ -726,15 +728,16 @@ OB: 41
|
||||
OFS1P3BX: 6
|
||||
OFS1P3DX: 12
|
||||
OFS1P3IX: 3
|
||||
ORCALUT4: 275
|
||||
ORCALUT4: 268
|
||||
PFUMX: 10
|
||||
PUR: 1
|
||||
VHI: 3
|
||||
VLO: 3
|
||||
Mapper successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 33MB peak: 164MB)
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:03s; Memory used current: 33MB peak: 163MB)
|
||||
|
||||
Process took 0h:00m:03s realtime, 0h:00m:02s cputime
|
||||
# Fri Jun 7 20:50:12 2024
|
||||
Process took 0h:00m:16s realtime, 0h:00m:03s cputime
|
||||
# Fri Jul 12 16:07:48 2024
|
||||
|
||||
###########################################################]
|
||||
|
||||
152
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_bgn.html
Normal file
152
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_bgn.html
Normal file
@ -0,0 +1,152 @@
|
||||
<HTML>
|
||||
<HEAD><TITLE>Bitgen Report</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Bgn"></A>BITGEN: Bitstream Generator Diamond (64-bit) 3.11.3.469
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Fri Jun 07 20:50:31 2024
|
||||
|
||||
|
||||
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC -w -jedec -gui RAM2E_LCMXO2_1200HC_impl1.ncd RAM2E_LCMXO2_1200HC_impl1.prf
|
||||
|
||||
Loading design for application Bitgen from file RAM2E_LCMXO2_1200HC_impl1.ncd.
|
||||
Design name: RAM2E
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-1200HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application Bitgen from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.11_x64/ispfpga.
|
||||
Package Status: Final Version 1.42.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
|
||||
Running DRC.
|
||||
DRC detected 0 errors and 0 warnings.
|
||||
Reading Preference File from RAM2E_LCMXO2_1200HC_impl1.prf.
|
||||
|
||||
<A name="bgn_ps"></A>
|
||||
<B><U><big>Preference Summary:</big></U></B>
|
||||
|
||||
+---------------------------------+---------------------------------+
|
||||
| Preference | Current Setting |
|
||||
+---------------------------------+---------------------------------+
|
||||
| RamCfg | Reset** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MCCLK_FREQ | 2.08** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| CONFIG_SECURE | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| INBUF | ON** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| JTAG_PORT | ENABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SDM_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SLAVE_SPI_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MASTER_SPI_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| I2C_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MUX_CONFIGURATION_PORTS | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| CONFIGURATION | CFG** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| COMPRESS_CONFIG | ON** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MY_ASSP | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| ONE_TIME_PROGRAM | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| ENABLE_TRANSFR | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SHAREDEBRINIT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| BACKGROUND_RECONFIG | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
* Default setting.
|
||||
** The specified setting matches the default setting.
|
||||
|
||||
|
||||
Creating bit map...
|
||||
|
||||
Bitstream Status: Final Version 1.95.
|
||||
|
||||
Saving bit stream in "RAM2E_LCMXO2_1200HC_impl1.jed".
|
||||
|
||||
===========
|
||||
UFM Summary.
|
||||
===========
|
||||
UFM Size: 511 Pages (128*511 Bits).
|
||||
UFM Utilization: General Purpose Flash Memory.
|
||||
|
||||
Available General Purpose Flash Memory: 511 Pages (Page 0 to Page 510).
|
||||
Initialized UFM Pages: 321 Pages (Page 190 to Page 510).
|
||||
|
||||
Total CPU Time: 3 secs
|
||||
Total REAL Time: 4 secs
|
||||
Peak Memory Usage: 275 MB
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
@ -13,7 +13,7 @@ Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
|
||||
# Written on Fri Jun 7 20:50:08 2024
|
||||
# Written on Fri Jul 12 16:07:27 2024
|
||||
|
||||
##### DESIGN INFO #######################################################
|
||||
|
||||
|
||||
@ -17,24 +17,25 @@ Command line: map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 4 -oc Commercial
|
||||
RAM2E_LCMXO2_1200HC_impl1.ngd -o RAM2E_LCMXO2_1200HC_impl1_map.ncd -pr
|
||||
RAM2E_LCMXO2_1200HC_impl1.prf -mp RAM2E_LCMXO2_1200HC_impl1.mrp -lpf //Mac/
|
||||
iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_synpl
|
||||
ify.lpf -lpf //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf -c 0 -gui
|
||||
ify.lpf -lpf //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf -c 0 -gui
|
||||
-msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml
|
||||
Target Vendor: LATTICE
|
||||
Target Device: LCMXO2-1200HCTQFP100
|
||||
Target Performance: 4
|
||||
Mapper: xo2c00, version: Diamond (64-bit) 3.11.3.469
|
||||
Mapped on: 06/07/24 20:50:13
|
||||
Mapped on: 07/12/24 16:08:07
|
||||
|
||||
|
||||
<A name="mrp_ds"></A><B><U><big>Design Summary</big></U></B>
|
||||
Number of registers: 125 out of 1520 (8%)
|
||||
PFU registers: 103 out of 1280 (8%)
|
||||
Number of registers: 124 out of 1520 (8%)
|
||||
PFU registers: 102 out of 1280 (8%)
|
||||
PIO registers: 22 out of 240 (9%)
|
||||
Number of SLICEs: 148 out of 640 (23%)
|
||||
SLICEs as Logic/ROM: 148 out of 640 (23%)
|
||||
Number of SLICEs: 145 out of 640 (23%)
|
||||
SLICEs as Logic/ROM: 145 out of 640 (23%)
|
||||
SLICEs as RAM: 0 out of 480 (0%)
|
||||
SLICEs as Carry: 9 out of 640 (1%)
|
||||
Number of LUT4s: 295 out of 1280 (23%)
|
||||
Number used as logic LUTs: 277
|
||||
Number of LUT4s: 288 out of 1280 (23%)
|
||||
Number used as logic LUTs: 270
|
||||
Number used as distributed RAM: 0
|
||||
Number used as ripple logic: 18
|
||||
Number used as shift registers: 0
|
||||
@ -64,44 +65,45 @@ Mapped on: 06/07/24 20:50:13
|
||||
2. Number of logic LUT4s does not include count of distributed RAM and
|
||||
ripple logic.
|
||||
Number of clocks: 2
|
||||
Net C14M_c: 85 loads, 63 rising, 22 falling (Driver: PIO C14M )
|
||||
Net C14M_c: 84 loads, 62 rising, 22 falling (Driver: PIO C14M )
|
||||
Net PHI1_c: 3 loads, 0 rising, 3 falling (Driver: PIO PHI1 )
|
||||
Number of Clock Enables: 13
|
||||
|
||||
Net N_117_i: 2 loads, 0 LSLICEs
|
||||
Net RWBank14: 11 loads, 11 LSLICEs
|
||||
Number of Clock Enables: 13
|
||||
Net N_347_i: 2 loads, 0 LSLICEs
|
||||
Net RWBank14: 10 loads, 10 LSLICEs
|
||||
Net ram2e_ufm/wb_adr_0_sqmuxa_1_i: 1 loads, 1 LSLICEs
|
||||
Net un9_VOE_0_a2_0_a2: 1 loads, 1 LSLICEs
|
||||
Net un6_DOEEN_0_a2_0_a2: 2 loads, 2 LSLICEs
|
||||
Net ram2e_ufm/un1_wb_adr_0_sqmuxa_2_i[0]: 8 loads, 8 LSLICEs
|
||||
Net ram2e_ufm/un1_wb_cyc_stb_0_sqmuxa_1_i[0]: 1 loads, 1 LSLICEs
|
||||
Net ram2e_ufm/N_111: 1 loads, 1 LSLICEs
|
||||
Net ram2e_ufm/N_104: 4 loads, 4 LSLICEs
|
||||
Net ram2e_ufm/N_98: 1 loads, 1 LSLICEs
|
||||
Net un1_CKE48_0_i: 6 loads, 6 LSLICEs
|
||||
Net N_389_i: 2 loads, 0 LSLICEs
|
||||
Net ram2e_ufm/N_63: 1 loads, 1 LSLICEs
|
||||
Net ram2e_ufm/un1_wb_adr_0_sqmuxa_2_i_0[0]: 8 loads, 8 LSLICEs
|
||||
Net ram2e_ufm/un1_CmdBitbangMXO212_1_i[0]: 1 loads, 1 LSLICEs
|
||||
Net ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0[0]: 4 loads, 4 LSLICEs
|
||||
Net ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0[0]: 1 loads, 1 LSLICEs
|
||||
Net un9_VOE_0_a2: 1 loads, 1 LSLICEs
|
||||
Net un1_CKE48_i: 6 loads, 6 LSLICEs
|
||||
Net N_346_i: 2 loads, 0 LSLICEs
|
||||
Net Vout3: 8 loads, 0 LSLICEs
|
||||
Number of LSRs: 8
|
||||
Net N_148: 2 loads, 2 LSLICEs
|
||||
Net N_430_i: 2 loads, 0 LSLICEs
|
||||
Number of LSRs: 9
|
||||
Net un1_CS_0_sqmuxa_i: 2 loads, 2 LSLICEs
|
||||
Net ram2e_ufm.wb_rst13: 2 loads, 0 LSLICEs
|
||||
Net RC7: 2 loads, 2 LSLICEs
|
||||
Net S[2]: 2 loads, 2 LSLICEs
|
||||
Net S[1]: 1 loads, 1 LSLICEs
|
||||
Net ram2e_ufm/wb_rst: 1 loads, 0 LSLICEs
|
||||
Net ram2e_ufm/nRWE_0_i_o3_RNIP8E61: 1 loads, 1 LSLICEs
|
||||
Net N_530: 1 loads, 0 LSLICEs
|
||||
Net N_301_i: 1 loads, 1 LSLICEs
|
||||
Net ram2e_ufm/wb_rst6_i: 1 loads, 1 LSLICEs
|
||||
Net N_523_1: 1 loads, 0 LSLICEs
|
||||
Net N_727_0: 1 loads, 1 LSLICEs
|
||||
Net RATc_i: 1 loads, 1 LSLICEs
|
||||
Number of nets driven by tri-state buffers: 0
|
||||
Top 10 highest fanout non-clock nets:
|
||||
Net S[2]: 60 loads
|
||||
Net S[3]: 48 loads
|
||||
Net S[1]: 46 loads
|
||||
Net S[0]: 31 loads
|
||||
Net FS[11]: 24 loads
|
||||
Net FS[10]: 23 loads
|
||||
Net FS[12]: 23 loads
|
||||
Net FS[9]: 23 loads
|
||||
Net FS[13]: 21 loads
|
||||
Net FS[8]: 18 loads
|
||||
Net S[2]: 51 loads
|
||||
Net S[1]: 44 loads
|
||||
Net S[3]: 40 loads
|
||||
Net S[0]: 32 loads
|
||||
Net FS[8]: 29 loads
|
||||
Net FS[9]: 26 loads
|
||||
Net FS[10]: 25 loads
|
||||
Net FS[11]: 23 loads
|
||||
Net FS[13]: 20 loads
|
||||
Net ram2e_ufm.wb_rst13: 17 loads
|
||||
|
||||
|
||||
|
||||
@ -124,12 +126,12 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
||||
Functionality is restored after the Flash Memory (UFM/Configuration)
|
||||
Interface is disabled using Disable Configuration Interface command 0x26
|
||||
followed by Bypass command 0xFF.
|
||||
|
||||
WARNING - map: IO buffer missing for top level port nWE80...logic will be
|
||||
discarded.
|
||||
|
||||
|
||||
|
||||
|
||||
<A name="mrp_ioa"></A><B><U><big>IO (PIO) Attributes</big></U></B>
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
@ -182,11 +184,11 @@ WARNING - map: IO buffer missing for top level port nWE80...logic will be
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RAout[1] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
| RAout[0] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| BA[1] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
| BA[0] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRWEout | OUTPUT | LVCMOS33 | OUT |
|
||||
@ -239,11 +241,11 @@ WARNING - map: IO buffer missing for top level port nWE80...logic will be
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[6] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
| Din[5] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[4] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
| Din[3] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[2] | INPUT | LVCMOS33 | |
|
||||
@ -297,11 +299,11 @@ Signal ram2e_ufm/ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/CFGWAKE undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/wbc_ufm_irq undriven or does not drive anything -
|
||||
clipped.
|
||||
|
||||
Signal ram2e_ufm/ufmefb/TCOC undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/TCINT undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIIRQO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPICSNEN undriven or does not drive anything - clipped.
|
||||
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
|
||||
@ -354,11 +356,11 @@ Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped.
|
||||
Signal N_1 undriven or does not drive anything - clipped.
|
||||
Block RefReq.CN was optimized away.
|
||||
Block RDOE_RNIAM8C was optimized away.
|
||||
|
||||
Block nCASout.CN was optimized away.
|
||||
Block ram2e_ufm/ufmefb/VCC was optimized away.
|
||||
Block ram2e_ufm/ufmefb/GND was optimized away.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@ -413,9 +415,10 @@ Instance Name: ram2e_ufm/ufmefb/EFBInst_0
|
||||
<A name="mrp_runtime"></A><B><U><big>Run Time and Memory Usage</big></U></B>
|
||||
-------------------------
|
||||
|
||||
Total CPU Time: 0 secs
|
||||
Total REAL Time: 2 secs
|
||||
Total CPU Time: 1 secs
|
||||
Total REAL Time: 12 secs
|
||||
Peak Memory Usage: 64 MB
|
||||
|
||||
|
||||
|
||||
|
||||
@ -423,6 +426,58 @@ Instance Name: ram2e_ufm/ufmefb/EFBInst_0
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
|
||||
@ -14,7 +14,7 @@ Performance Grade: 4
|
||||
PACKAGE: TQFP100
|
||||
Package Status: Final Version 1.42
|
||||
|
||||
Fri Jun 07 20:50:24 2024
|
||||
Fri Jul 12 16:08:36 2024
|
||||
|
||||
Pinout by Port Name:
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
@ -320,7 +320,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Fri Jun 07 20:50:28 2024
|
||||
Fri Jul 12 16:08:42 2024
|
||||
|
||||
|
||||
|
||||
|
||||
@ -12,11 +12,12 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Fri Jun 07 20:50:15 2024
|
||||
Fri Jul 12 16:08:22 2024
|
||||
|
||||
C:/lscc/diamond/3.11_x64/ispfpga\bin\nt64\par -f RAM2E_LCMXO2_1200HC_impl1.p2t
|
||||
RAM2E_LCMXO2_1200HC_impl1_map.ncd RAM2E_LCMXO2_1200HC_impl1.dir
|
||||
RAM2E_LCMXO2_1200HC_impl1.prf -gui
|
||||
RAM2E_LCMXO2_1200HC_impl1.prf -gui -msgset
|
||||
//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml
|
||||
|
||||
|
||||
Preference file: RAM2E_LCMXO2_1200HC_impl1.prf.
|
||||
@ -25,22 +26,22 @@ Preference file: RAM2E_LCMXO2_1200HC_impl1.prf.
|
||||
Level/ Number Worst Timing Worst Timing Run NCD
|
||||
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
|
||||
---------- -------- ----- ------ ----------- ----------- ---- ------
|
||||
5_1 * 0 54.468 0 0.379 0 16 Completed
|
||||
5_1 * 0 55.594 0 0.379 0 34 Completed
|
||||
* : Design saved.
|
||||
|
||||
Total (real) run time for 1-seed: 16 secs
|
||||
Total (real) run time for 1-seed: 36 secs
|
||||
|
||||
par done!
|
||||
|
||||
Note: user must run 'Trace' for timing closure signoff.
|
||||
|
||||
Lattice Place and Route Report for Design "RAM2E_LCMXO2_1200HC_impl1_map.ncd"
|
||||
Fri Jun 07 20:50:15 2024
|
||||
Fri Jul 12 16:08:23 2024
|
||||
|
||||
|
||||
<A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
|
||||
PAR: Place And Route Diamond (64-bit) 3.11.3.469.
|
||||
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF RAM2E_LCMXO2_1200HC_impl1_map.ncd RAM2E_LCMXO2_1200HC_impl1.dir/5_1.ncd RAM2E_LCMXO2_1200HC_impl1.prf
|
||||
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF RAM2E_LCMXO2_1200HC_impl1_map.ncd RAM2E_LCMXO2_1200HC_impl1.dir/5_1.ncd RAM2E_LCMXO2_1200HC_impl1.prf
|
||||
Preference file: RAM2E_LCMXO2_1200HC_impl1.prf.
|
||||
Placement level-cost: 5-1.
|
||||
Routing Iterations: 6
|
||||
@ -66,39 +67,39 @@ Ignore Preference Error(s): True
|
||||
70+4(JTAG)/80 93% bonded
|
||||
IOLOGIC 22/108 20% used
|
||||
|
||||
SLICE 148/640 23% used
|
||||
SLICE 145/640 22% used
|
||||
|
||||
EFB 1/1 100% used
|
||||
|
||||
|
||||
Number of Signals: 464
|
||||
Number of Connections: 1330
|
||||
Number of Signals: 446
|
||||
Number of Connections: 1292
|
||||
|
||||
Pin Constraint Summary:
|
||||
70 out of 70 pins locked (100% locked).
|
||||
|
||||
The following 1 signal is selected to use the primary clock routing resources:
|
||||
C14M_c (driver: C14M, clk load #: 85)
|
||||
C14M_c (driver: C14M, clk load #: 84)
|
||||
|
||||
WARNING - par: Signal "C14M_c" is selected to use Primary clock resources. However, its driver comp "C14M" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
|
||||
The following 1 signal is selected to use the secondary clock routing resources:
|
||||
RWBank14 (driver: ram2e_ufm/SLICE_82, clk load #: 0, sr load #: 0, ce load #: 11)
|
||||
RWBank14 (driver: ram2e_ufm/SLICE_89, clk load #: 0, sr load #: 0, ce load #: 10)
|
||||
|
||||
No signal is selected as Global Set/Reset.
|
||||
Starting Placer Phase 0.
|
||||
........
|
||||
Finished Placer Phase 0. REAL time: 2 secs
|
||||
Finished Placer Phase 0. REAL time: 3 secs
|
||||
|
||||
Starting Placer Phase 1.
|
||||
....................
|
||||
Placer score = 86293.
|
||||
Finished Placer Phase 1. REAL time: 9 secs
|
||||
Placer score = 83662.
|
||||
Finished Placer Phase 1. REAL time: 12 secs
|
||||
|
||||
Starting Placer Phase 2.
|
||||
.
|
||||
Placer score = 85792
|
||||
Finished Placer Phase 2. REAL time: 9 secs
|
||||
Placer score = 83395
|
||||
Finished Placer Phase 2. REAL time: 12 secs
|
||||
|
||||
|
||||
|
||||
@ -112,8 +113,8 @@ Global Clock Resources:
|
||||
DCC : 0 out of 8 (0%)
|
||||
|
||||
Global Clocks:
|
||||
PRIMARY "C14M_c" from comp "C14M" on PIO site "62 (PR5D)", clk load = 85
|
||||
SECONDARY "RWBank14" from F0 on comp "ram2e_ufm/SLICE_82" on site "R7C14A", clk load = 0, ce load = 11, sr load = 0
|
||||
PRIMARY "C14M_c" from comp "C14M" on PIO site "62 (PR5D)", clk load = 84
|
||||
SECONDARY "RWBank14" from F0 on comp "ram2e_ufm/SLICE_89" on site "R7C14C", clk load = 0, ce load = 10, sr load = 0
|
||||
|
||||
PRIMARY : 1 out of 8 (12%)
|
||||
SECONDARY: 1 out of 8 (12%)
|
||||
@ -144,16 +145,16 @@ Total placer CPU time: 7 secs
|
||||
|
||||
Dumping design to file RAM2E_LCMXO2_1200HC_impl1.dir/5_1.ncd.
|
||||
|
||||
0 connections routed; 1330 unrouted.
|
||||
0 connections routed; 1292 unrouted.
|
||||
Starting router resource preassignment
|
||||
WARNING - par: The driver of primary clock net C14M_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
|
||||
|
||||
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
|
||||
Signal=PHI1_c loads=5 clock_loads=3
|
||||
|
||||
Completed router resource preassignment. Real time: 14 secs
|
||||
Completed router resource preassignment. Real time: 20 secs
|
||||
|
||||
Start NBR router at 20:50:29 06/07/24
|
||||
Start NBR router at 16:08:43 07/12/24
|
||||
|
||||
*****************************************************************
|
||||
Info: NBR allows conflicts(one node used by more than one signal)
|
||||
@ -168,35 +169,35 @@ Note: NBR uses a different method to calculate timing slacks. The
|
||||
your design.
|
||||
*****************************************************************
|
||||
|
||||
Start NBR special constraint process at 20:50:29 06/07/24
|
||||
Start NBR special constraint process at 16:08:43 07/12/24
|
||||
|
||||
Start NBR section for initial routing at 20:50:29 06/07/24
|
||||
Start NBR section for initial routing at 16:08:43 07/12/24
|
||||
Level 4, iteration 1
|
||||
25(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 54.468ns/0.000ns; real time: 15 secs
|
||||
22(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 55.594ns/0.000ns; real time: 29 secs
|
||||
|
||||
Info: Initial congestion level at 75% usage is 0
|
||||
Info: Initial congestion area at 75% usage is 0 (0.00%)
|
||||
|
||||
Start NBR section for normal routing at 20:50:30 06/07/24
|
||||
Start NBR section for normal routing at 16:08:52 07/12/24
|
||||
Level 4, iteration 1
|
||||
5(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 54.468ns/0.000ns; real time: 15 secs
|
||||
8(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 55.594ns/0.000ns; real time: 31 secs
|
||||
Level 4, iteration 2
|
||||
5(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 54.468ns/0.000ns; real time: 15 secs
|
||||
2(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 55.594ns/0.000ns; real time: 32 secs
|
||||
Level 4, iteration 3
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 54.468ns/0.000ns; real time: 15 secs
|
||||
Estimated worst slack/total negative slack<setup>: 55.594ns/0.000ns; real time: 32 secs
|
||||
|
||||
Start NBR section for setup/hold timing optimization with effort level 3 at 20:50:30 06/07/24
|
||||
Start NBR section for setup/hold timing optimization with effort level 3 at 16:08:55 07/12/24
|
||||
|
||||
Start NBR section for re-routing at 20:50:30 06/07/24
|
||||
Start NBR section for re-routing at 16:08:55 07/12/24
|
||||
Level 4, iteration 1
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 54.468ns/0.000ns; real time: 15 secs
|
||||
Estimated worst slack/total negative slack<setup>: 55.594ns/0.000ns; real time: 32 secs
|
||||
|
||||
Start NBR section for post-routing at 20:50:30 06/07/24
|
||||
Start NBR section for post-routing at 16:08:55 07/12/24
|
||||
|
||||
End NBR router with 0 unrouted connection
|
||||
|
||||
@ -204,7 +205,7 @@ NBR Summary
|
||||
-----------
|
||||
Number of unrouted connections : 0 (0.00%)
|
||||
Number of connections with timing violations : 0 (0.00%)
|
||||
Estimated worst slack<setup> : 54.468ns
|
||||
Estimated worst slack<setup> : 55.594ns
|
||||
Timing score<setup> : 0
|
||||
-----------
|
||||
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
|
||||
@ -215,9 +216,9 @@ WARNING - par: The following clock signals will be routed by using generic routi
|
||||
Signal=PHI1_c loads=5 clock_loads=3
|
||||
|
||||
Total CPU time 13 secs
|
||||
Total REAL time: 16 secs
|
||||
Total REAL time: 34 secs
|
||||
Completely routed.
|
||||
End of route. 1330 routed (100.00%); 0 unrouted.
|
||||
End of route. 1292 routed (100.00%); 0 unrouted.
|
||||
|
||||
Hold time timing score: 0, hold timing errors: 0
|
||||
|
||||
@ -231,14 +232,14 @@ All signals are completely routed.
|
||||
|
||||
PAR_SUMMARY::Run status = Completed
|
||||
PAR_SUMMARY::Number of unrouted conns = 0
|
||||
PAR_SUMMARY::Worst slack<setup/<ns>> = 54.468
|
||||
PAR_SUMMARY::Worst slack<setup/<ns>> = 55.594
|
||||
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
|
||||
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.379
|
||||
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
|
||||
PAR_SUMMARY::Number of errors = 0
|
||||
|
||||
Total CPU time to completion: 13 secs
|
||||
Total REAL time to completion: 16 secs
|
||||
Total CPU time to completion: 14 secs
|
||||
Total REAL time to completion: 35 secs
|
||||
|
||||
par done!
|
||||
|
||||
|
||||
@ -13,7 +13,7 @@ Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
|
||||
# Written on Fri Jun 7 20:50:07 2024
|
||||
# Written on Fri Jul 12 16:07:21 2024
|
||||
|
||||
##### FILES SYNTAX CHECKED ##############################################
|
||||
Constraint File(s): "\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc"
|
||||
@ -33,7 +33,7 @@ Clock Summary
|
||||
Start Requested Requested Clock Clock Clock
|
||||
Level Clock Frequency Period Type Group Load
|
||||
-----------------------------------------------------------------------------------------------
|
||||
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 121
|
||||
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 120
|
||||
|
||||
0 - System 100.0 MHz 10.000 system system_clkgroup 0
|
||||
|
||||
@ -47,7 +47,7 @@ Clock Load Summary
|
||||
Clock Source Clock Pin Non-clock Pin Non-clock Pin
|
||||
Clock Load Pin Seq Example Seq Example Comb Example
|
||||
--------------------------------------------------------------------------------------------
|
||||
C14M 121 C14M(port) RAT.C - un1_C14M.I[0](inv)
|
||||
C14M 120 C14M(port) RAT.C - un1_C14M.I[0](inv)
|
||||
|
||||
System 0 - - - -
|
||||
|
||||
|
||||
@ -62,7 +62,7 @@
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Updated:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2024/06/07 20:50:35</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2024/07/12 16:09:06</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Location:</SPAN></TD>
|
||||
|
||||
@ -12,7 +12,7 @@
|
||||
#OS: Windows 8 6.2
|
||||
#Hostname: ZANEMACWIN11
|
||||
|
||||
# Fri Jun 7 20:50:04 2024
|
||||
# Fri Jul 12 16:07:08 2024
|
||||
|
||||
#Implementation: impl1
|
||||
|
||||
@ -61,6 +61,7 @@ Synopsys Verilog Compiler, Version comp2018q2p1, Build 461R, Built Apr 1 2019 0
|
||||
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\REFB.v" (library work)
|
||||
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\DHGR-ON.v" (library work)
|
||||
Verilog syntax check successful!
|
||||
File \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v changed - recompiling
|
||||
Selecting top level module RAM2E
|
||||
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
|
||||
Running optimization stage 1 on VHI .......
|
||||
@ -86,12 +87,12 @@ Running optimization stage 2 on EFB .......
|
||||
Running optimization stage 2 on VLO .......
|
||||
Running optimization stage 2 on VHI .......
|
||||
|
||||
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)
|
||||
At c_ver Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
Process took 0h:00m:03s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Fri Jun 7 20:50:05 2024
|
||||
# Fri Jul 12 16:07:14 2024
|
||||
|
||||
###########################################################]
|
||||
|
||||
@ -111,13 +112,14 @@ Implementation : impl1
|
||||
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
File \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\layer0.srs changed - recompiling
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Fri Jun 7 20:50:05 2024
|
||||
# Fri Jul 12 16:07:14 2024
|
||||
|
||||
###########################################################]
|
||||
|
||||
@ -127,12 +129,12 @@ For a summary of runtime and memory usage for all design units, please see file:
|
||||
|
||||
@END
|
||||
|
||||
At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
|
||||
At c_hdl Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
Process took 0h:00m:04s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Fri Jun 7 20:50:05 2024
|
||||
# Fri Jul 12 16:07:14 2024
|
||||
|
||||
###########################################################]
|
||||
|
||||
@ -152,18 +154,17 @@ Database state : \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\|impl
|
||||
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
File \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_comp.srs changed - recompiling
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 68MB)
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 68MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Fri Jun 7 20:50:07 2024
|
||||
# Fri Jul 12 16:07:18 2024
|
||||
|
||||
###########################################################]
|
||||
Premap Report
|
||||
|
||||
# Fri Jun 7 20:50:07 2024
|
||||
# Fri Jul 12 16:07:19 2024
|
||||
|
||||
|
||||
Copyright (C) 1994-2018 Synopsys, Inc.
|
||||
@ -192,26 +193,26 @@ Printing clock summary report in "\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\i
|
||||
@N: MF248 |Running in 64-bit mode.
|
||||
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
|
||||
|
||||
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
|
||||
Design Input Complete (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
|
||||
|
||||
|
||||
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
|
||||
Mapper Initialization Complete (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
|
||||
|
||||
|
||||
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB)
|
||||
Start loading timing files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB)
|
||||
|
||||
|
||||
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB)
|
||||
Finished loading timing files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB)
|
||||
|
||||
@N: MF284 |Setting synthesis effort to medium for the design
|
||||
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
|
||||
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":21:4:21:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
|
||||
@N: MH105 |UMR3 is only supported for HAPS-80.
|
||||
@N: MH105 |UMR3 is only supported for HAPS-80.
|
||||
@N: BN115 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":140:9:140:12|Removing instance dhgr (in view: work.RAM2E(verilog)) of type view:work.DHGR(verilog) because it does not drive other instances.
|
||||
@N: BN115 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":136:9:136:12|Removing instance dhgr (in view: work.RAM2E(verilog)) of type view:work.DHGR(verilog) because it does not drive other instances.
|
||||
syn_allowed_resources : blockrams=7 set on top level netlist RAM2E
|
||||
|
||||
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
|
||||
Finished netlist restructuring (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
|
||||
|
||||
|
||||
|
||||
@ -221,7 +222,7 @@ Clock Summary
|
||||
Start Requested Requested Clock Clock Clock
|
||||
Level Clock Frequency Period Type Group Load
|
||||
-----------------------------------------------------------------------------------------------
|
||||
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 121
|
||||
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 120
|
||||
|
||||
0 - System 100.0 MHz 10.000 system system_clkgroup 0
|
||||
|
||||
@ -236,7 +237,7 @@ Clock Load Summary
|
||||
Clock Source Clock Pin Non-clock Pin Non-clock Pin
|
||||
Clock Load Pin Seq Example Seq Example Comb Example
|
||||
--------------------------------------------------------------------------------------------
|
||||
C14M 121 C14M(port) RAT.C - un1_C14M.I[0](inv)
|
||||
C14M 120 C14M(port) RAT.C - un1_C14M.I[0](inv)
|
||||
|
||||
System 0 - - - -
|
||||
|
||||
@ -256,14 +257,14 @@ Number of ICG latches not removed: 0
|
||||
|
||||
#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
|
||||
|
||||
2 non-gated/non-generated clock tree(s) driving 125 clock pin(s) of sequential element(s)
|
||||
2 non-gated/non-generated clock tree(s) driving 124 clock pin(s) of sequential element(s)
|
||||
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
|
||||
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
|
||||
|
||||
=========================== Non-Gated/Non-Generated Clocks ============================
|
||||
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
|
||||
---------------------------------------------------------------------------------------
|
||||
@KP:ckid0_0 C14M port 121 PHI1r
|
||||
@KP:ckid0_0 C14M port 120 PHI1r
|
||||
@KP:ckid0_1 PHI1 Unconstrained_port 4 RC[2:0]
|
||||
=======================================================================================
|
||||
|
||||
@ -273,27 +274,25 @@ Clock Tree ID Driving Element Drive Element Type Fanout Sample I
|
||||
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
|
||||
Finished Pre Mapping Phase.
|
||||
|
||||
Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
|
||||
Starting constraint checker (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
|
||||
|
||||
|
||||
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
|
||||
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
|
||||
|
||||
None
|
||||
None
|
||||
|
||||
Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
|
||||
Finished constraint checker (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
|
||||
|
||||
Pre-mapping successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB)
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Fri Jun 7 20:50:08 2024
|
||||
Process took 0h:00m:08s realtime, 0h:00m:01s cputime
|
||||
# Fri Jul 12 16:07:28 2024
|
||||
|
||||
###########################################################]
|
||||
Map & Optimize Report
|
||||
|
||||
# Fri Jun 7 20:50:08 2024
|
||||
# Fri Jul 12 16:07:30 2024
|
||||
|
||||
|
||||
Copyright (C) 1994-2018 Synopsys, Inc.
|
||||
@ -319,21 +318,21 @@ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:0
|
||||
@N: MF248 |Running in 64-bit mode.
|
||||
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
|
||||
|
||||
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
|
||||
Design Input Complete (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
|
||||
|
||||
|
||||
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
|
||||
Mapper Initialization Complete (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
|
||||
|
||||
|
||||
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
|
||||
Start loading timing files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
|
||||
|
||||
|
||||
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
|
||||
Finished loading timing files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
|
||||
|
||||
@N: MF284 |Setting synthesis effort to medium for the design
|
||||
|
||||
|
||||
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
|
||||
Starting Optimization and Mapping (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
|
||||
|
||||
|
||||
Available hyper_sources - for debug and ip models
|
||||
@ -342,61 +341,61 @@ Available hyper_sources - for debug and ip models
|
||||
@N: FX493 |Applying initial value "00000000" on instance RWBank[7:0].
|
||||
@N: FX493 |Applying initial value "0000" on instance S[3:0].
|
||||
|
||||
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)
|
||||
Finished RTL optimizations (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)
|
||||
|
||||
@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":14:23:14:28|Found counter in view:work.RAM2E(verilog) instance FS[15:0]
|
||||
|
||||
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 142MB)
|
||||
Starting factoring (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 142MB)
|
||||
|
||||
|
||||
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
|
||||
Finished factoring (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
|
||||
|
||||
|
||||
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
|
||||
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
|
||||
|
||||
|
||||
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
|
||||
Starting Early Timing Optimization (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
|
||||
|
||||
|
||||
Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
|
||||
Finished Early Timing Optimization (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
|
||||
|
||||
|
||||
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
|
||||
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
|
||||
|
||||
|
||||
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
|
||||
Finished preparing to map (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 147MB)
|
||||
|
||||
|
||||
Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
|
||||
Finished technology mapping (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
|
||||
|
||||
Pass CPU time Worst Slack Luts / Registers
|
||||
------------------------------------------------------------
|
||||
1 0h:00m:01s 6.90ns 281 / 125
|
||||
1 0h:00m:01s 6.90ns 280 / 124
|
||||
|
||||
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
|
||||
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
|
||||
|
||||
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
|
||||
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":171:4:171:9|Boundary register BA_1_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
||||
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":171:4:171:9|Boundary register BA_0_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
||||
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":168:4:168:9|Boundary register BA_1_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
||||
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":168:4:168:9|Boundary register BA_0_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
||||
|
||||
Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 158MB peak: 160MB)
|
||||
Finished restoring hierarchy (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:01s; Memory used current: 158MB peak: 160MB)
|
||||
|
||||
|
||||
Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 122MB peak: 160MB)
|
||||
Start Writing Netlists (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:01s; Memory used current: 122MB peak: 160MB)
|
||||
|
||||
Writing Analyst data base \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_m.srm
|
||||
|
||||
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 158MB peak: 160MB)
|
||||
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:02s; Memory used current: 157MB peak: 160MB)
|
||||
|
||||
Writing EDIF Netlist and constraint files
|
||||
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1.edi
|
||||
N-2018.03L-SP1-1
|
||||
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
|
||||
|
||||
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 162MB peak: 164MB)
|
||||
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 163MB)
|
||||
|
||||
|
||||
Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 161MB peak: 164MB)
|
||||
Start final timing analysis (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:03s; Memory used current: 160MB peak: 163MB)
|
||||
|
||||
@W: MT246 :"\\mac\icloud\repos\ram2e\cpld\lcmxo2-1200hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
|
||||
@N: MT615 |Found clock C14M with period 69.84ns
|
||||
@ -404,7 +403,7 @@ Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:0
|
||||
|
||||
|
||||
##### START OF TIMING REPORT #####[
|
||||
# Timing Report written on Fri Jun 7 20:50:12 2024
|
||||
# Timing Report written on Fri Jul 12 16:07:46 2024
|
||||
#
|
||||
|
||||
|
||||
@ -429,9 +428,9 @@ Worst slack in design: 6.897
|
||||
Requested Estimated Requested Estimated Clock Clock
|
||||
Starting Clock Frequency Frequency Period Period Slack Type Group
|
||||
----------------------------------------------------------------------------------------------------------------------
|
||||
C14M 14.3 MHz 112.1 MHz 69.841 8.918 31.599 declared default_clkgroup
|
||||
C14M 14.3 MHz 120.3 MHz 69.841 8.314 31.675 declared default_clkgroup
|
||||
RAM2E|PHI1 100.0 MHz 322.2 MHz 10.000 3.103 6.897 inferred Inferred_clkgroup_0
|
||||
System 100.0 MHz NA 10.000 NA 67.088 system system_clkgroup
|
||||
System 100.0 MHz NA 10.000 NA 66.719 system system_clkgroup
|
||||
======================================================================================================================
|
||||
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
|
||||
|
||||
@ -446,9 +445,9 @@ Clocks | rise to rise | fall to fall | rise
|
||||
----------------------------------------------------------------------------------------------------------------
|
||||
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
|
||||
----------------------------------------------------------------------------------------------------------------
|
||||
System C14M | 69.841 67.088 | No paths - | No paths - | No paths -
|
||||
System C14M | 69.841 66.719 | No paths - | No paths - | No paths -
|
||||
C14M System | 69.841 68.797 | No paths - | No paths - | No paths -
|
||||
C14M C14M | 69.841 60.923 | No paths - | 34.920 31.599 | No paths -
|
||||
C14M C14M | 69.841 61.527 | No paths - | 34.920 31.675 | No paths -
|
||||
RAM2E|PHI1 C14M | No paths - | No paths - | No paths - | Diff grp -
|
||||
RAM2E|PHI1 RAM2E|PHI1 | No paths - | 10.000 6.897 | No paths - | No paths -
|
||||
================================================================================================================
|
||||
@ -477,10 +476,10 @@ Starting Points with Worst Slack
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
---------------------------------------------------------------------------
|
||||
S[2] C14M FD1S3AX Q S[2] 1.366 31.599
|
||||
S[3] C14M FD1S3AX Q S[3] 1.345 31.619
|
||||
S[1] C14M FD1S3AX Q S[1] 1.344 31.800
|
||||
S[0] C14M FD1S3AX Q S[0] 1.305 31.838
|
||||
S[2] C14M FD1S3AX Q S[2] 1.353 31.675
|
||||
S[3] C14M FD1S3AX Q S[3] 1.337 31.691
|
||||
S[0] C14M FD1S3AX Q S[0] 1.319 32.182
|
||||
S[1] C14M FD1S3AX Q S[1] 1.344 32.656
|
||||
RA[0] C14M FD1P3AX Q RA[0] 1.108 33.707
|
||||
RA[3] C14M FD1P3AX Q RA[3] 1.108 33.707
|
||||
RA[1] C14M FD1P3AX Q RA[1] 1.044 33.771
|
||||
@ -493,21 +492,21 @@ RA[5] C14M FD1P3AX Q RA[5] 1.044 33.771
|
||||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
-----------------------------------------------------------------------------------
|
||||
VOE_i_0io C14M OFS1P3IX CD N_530 34.118 31.599
|
||||
VOE_i_0io C14M OFS1P3IX D VOE_ic_i 35.009 31.800
|
||||
Vout_0io[0] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[1] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[2] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[3] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[4] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[5] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[6] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[7] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
===================================================================================
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------------
|
||||
VOE_i_0io C14M OFS1P3IX CD N_523_1 34.118 31.675
|
||||
RAT C14M FD1S3IX CD RATc_i 34.118 32.147
|
||||
Vout_0io[0] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[1] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[2] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[3] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[4] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[5] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[6] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[7] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
==================================================================================
|
||||
|
||||
|
||||
|
||||
@ -521,9 +520,9 @@ Path information for path number 1:
|
||||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
= Required time: 34.118
|
||||
|
||||
- Propagation time: 2.519
|
||||
- Propagation time: 2.442
|
||||
- Clock delay at starting point: 0.000 (ideal)
|
||||
= Slack (non-critical) : 31.599
|
||||
= Slack (non-critical) : 31.675
|
||||
|
||||
Number of logic level(s): 1
|
||||
Starting point: S[2] / Q
|
||||
@ -531,16 +530,16 @@ Path information for path number 1:
|
||||
The start point is clocked by C14M [rising] on pin CK
|
||||
The end point is clocked by C14M [falling] on pin SCLK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
------------------------------------------------------------------------------------------------------------
|
||||
S[2] FD1S3AX Q Out 1.366 1.366 -
|
||||
S[2] Net - - - - 58
|
||||
ram2e_ufm.un1_wb_adr_0_sqmuxa_2_0_a2_0[0] ORCALUT4 A In 0.000 1.366 -
|
||||
ram2e_ufm.un1_wb_adr_0_sqmuxa_2_0_a2_0[0] ORCALUT4 Z Out 1.153 2.519 -
|
||||
N_530 Net - - - - 3
|
||||
VOE_i_0io OFS1P3IX CD In 0.000 2.519 -
|
||||
============================================================================================================
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
---------------------------------------------------------------------------------------
|
||||
S[2] FD1S3AX Q Out 1.353 1.353 -
|
||||
S[2] Net - - - - 50
|
||||
ram2e_ufm.VOE_2_0_a2 ORCALUT4 A In 0.000 1.353 -
|
||||
ram2e_ufm.VOE_2_0_a2 ORCALUT4 Z Out 1.089 2.442 -
|
||||
N_523_1 Net - - - - 2
|
||||
VOE_i_0io OFS1P3IX CD In 0.000 2.442 -
|
||||
=======================================================================================
|
||||
|
||||
|
||||
|
||||
@ -629,7 +628,7 @@ Starting Points with Worst Slack
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
---------------------------------------------------------------------------------------------------
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBACKO wb_ack 0.000 67.088
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBACKO wb_ack 0.000 66.719
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO0 wb_dato[0] 0.000 69.313
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000 69.313
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO2 wb_dato[2] 0.000 69.313
|
||||
@ -644,21 +643,21 @@ ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO7 wb_dato[7]
|
||||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------------------
|
||||
ram2e_ufm.RWMask[0] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[1] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[2] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[3] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[4] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[5] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[6] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[7] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.LEDEN System FD1P3AX SP N_98 69.369 67.736
|
||||
ram2e_ufm.wb_cyc_stb System FD1P3AX SP N_111 69.369 67.736
|
||||
========================================================================================
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
---------------------------------------------------------------------------------------------------------------
|
||||
ram2e_ufm.wb_cyc_stb System FD1P3AX SP un1_CmdBitbangMXO212_1_i[0] 69.369 66.719
|
||||
ram2e_ufm.LEDEN System FD1P3AX SP un1_LEDEN_0_sqmuxa_1_i_0[0] 69.369 67.736
|
||||
ram2e_ufm.RWMask[0] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[1] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[2] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[3] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[4] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[5] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[6] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[7] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
===============================================================================================================
|
||||
|
||||
|
||||
|
||||
@ -672,30 +671,33 @@ Path information for path number 1:
|
||||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
= Required time: 69.369
|
||||
|
||||
- Propagation time: 2.282
|
||||
- Propagation time: 2.650
|
||||
- Clock delay at starting point: 0.000 (ideal)
|
||||
- Estimated clock delay at start point: -0.000
|
||||
= Slack (non-critical) : 67.088
|
||||
= Slack (non-critical) : 66.719
|
||||
|
||||
Number of logic level(s): 2
|
||||
Number of logic level(s): 3
|
||||
Starting point: ram2e_ufm.ufmefb.EFBInst_0 / WBACKO
|
||||
Ending point: ram2e_ufm.RWMask[0] / SP
|
||||
Ending point: ram2e_ufm.wb_cyc_stb / SP
|
||||
The start point is clocked by System [rising]
|
||||
The end point is clocked by C14M [rising] on pin CK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
----------------------------------------------------------------------------------------------------------------
|
||||
ram2e_ufm.ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 -
|
||||
wb_ack Net - - - - 5
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] ORCALUT4 B In 0.000 0.000 -
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] ORCALUT4 Z Out 1.017 1.017 -
|
||||
un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] Net - - - - 1
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 D In 0.000 1.017 -
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 Z Out 1.265 2.282 -
|
||||
N_104 Net - - - - 8
|
||||
ram2e_ufm.RWMask[0] FD1P3AX SP In 0.000 2.282 -
|
||||
================================================================================================================
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
---------------------------------------------------------------------------------------------------------------
|
||||
ram2e_ufm.ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 -
|
||||
wb_ack Net - - - - 4
|
||||
ram2e_ufm.un1_CmdBitbangMXO212_1_0_0_tz[0] ORCALUT4 B In 0.000 0.000 -
|
||||
ram2e_ufm.un1_CmdBitbangMXO212_1_0_0_tz[0] ORCALUT4 Z Out 1.017 1.017 -
|
||||
un1_CmdBitbangMXO212_1_0_0_tz[0] Net - - - - 1
|
||||
ram2e_ufm.un1_CmdBitbangMXO212_1_0_0_0[0] ORCALUT4 C In 0.000 1.017 -
|
||||
ram2e_ufm.un1_CmdBitbangMXO212_1_0_0_0[0] ORCALUT4 Z Out 1.017 2.034 -
|
||||
un1_CmdBitbangMXO212_1_0_0_0[0] Net - - - - 1
|
||||
ram2e_ufm.wb_cyc_stb_RNO_0 ORCALUT4 A In 0.000 2.034 -
|
||||
ram2e_ufm.wb_cyc_stb_RNO_0 ORCALUT4 Z Out 0.617 2.650 -
|
||||
un1_CmdBitbangMXO212_1_i[0] Net - - - - 1
|
||||
ram2e_ufm.wb_cyc_stb FD1P3AX SP In 0.000 2.650 -
|
||||
===============================================================================================================
|
||||
|
||||
|
||||
|
||||
@ -704,16 +706,16 @@ ram2e_ufm.RWMask[0] FD1P3AX SP In
|
||||
Timing exceptions that could not be applied
|
||||
None
|
||||
|
||||
Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 161MB peak: 164MB)
|
||||
Finished final timing analysis (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 163MB)
|
||||
|
||||
|
||||
Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 161MB peak: 164MB)
|
||||
Finished timing report (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 163MB)
|
||||
|
||||
---------------------------------------
|
||||
Resource Usage Report
|
||||
Part: lcmxo2_1200hc-4
|
||||
|
||||
Register bits: 125 of 1280 (10%)
|
||||
Register bits: 124 of 1280 (10%)
|
||||
PIC Latch: 0
|
||||
I/O cells: 70
|
||||
|
||||
@ -722,7 +724,7 @@ Details:
|
||||
BB: 8
|
||||
CCU2D: 9
|
||||
EFB: 1
|
||||
FD1P3AX: 58
|
||||
FD1P3AX: 57
|
||||
FD1P3IX: 1
|
||||
FD1S3AX: 31
|
||||
FD1S3AY: 4
|
||||
@ -735,16 +737,17 @@ OB: 41
|
||||
OFS1P3BX: 6
|
||||
OFS1P3DX: 12
|
||||
OFS1P3IX: 3
|
||||
ORCALUT4: 275
|
||||
ORCALUT4: 268
|
||||
PFUMX: 10
|
||||
PUR: 1
|
||||
VHI: 3
|
||||
VLO: 3
|
||||
Mapper successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 33MB peak: 164MB)
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:03s; Memory used current: 33MB peak: 163MB)
|
||||
|
||||
Process took 0h:00m:03s realtime, 0h:00m:02s cputime
|
||||
# Fri Jun 7 20:50:12 2024
|
||||
Process took 0h:00m:16s realtime, 0h:00m:03s cputime
|
||||
# Fri Jul 12 16:07:48 2024
|
||||
|
||||
###########################################################]
|
||||
|
||||
|
||||
@ -2,17 +2,19 @@
|
||||
Starting: parse design source files
|
||||
(VERI-1482) Analyzing Verilog file C:/lscc/diamond/3.11_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v
|
||||
(VERI-1482) Analyzing Verilog file //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v
|
||||
WARNING - //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v(140,9-140,25) (VERI-1362) CmdRWMaskSet is already implicitly declared on line 131
|
||||
WARNING - //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v(141,9-141,22) (VERI-1362) CmdLEDSet is already implicitly declared on line 131
|
||||
(VERI-1482) Analyzing Verilog file //Mac/iCloud/Repos/RAM2E/CPLD/UFM-LCMXO2.v
|
||||
(VERI-1482) Analyzing Verilog file //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/REFB.v
|
||||
(VERI-1482) Analyzing Verilog file //Mac/iCloud/Repos/RAM2E/CPLD/DHGR-ON.v
|
||||
INFO - //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v(1,8-1,13) (VERI-1018) compiling module RAM2E
|
||||
INFO - //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v(1,1-479,10) (VERI-9000) elaborating module 'RAM2E'
|
||||
INFO - //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v(1,1-476,10) (VERI-9000) elaborating module 'RAM2E'
|
||||
INFO - //Mac/iCloud/Repos/RAM2E/CPLD/UFM-LCMXO2.v(1,1-335,10) (VERI-9000) elaborating module 'RAM2E_UFM_uniq_1'
|
||||
INFO - //Mac/iCloud/Repos/RAM2E/CPLD/DHGR-ON.v(1,1-1,68) (VERI-9000) elaborating module 'DHGR_uniq_1'
|
||||
INFO - //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/REFB.v(8,1-113,10) (VERI-9000) elaborating module 'REFB_uniq_1'
|
||||
INFO - C:/lscc/diamond/3.11_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_1'
|
||||
INFO - C:/lscc/diamond/3.11_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_1'
|
||||
INFO - C:/lscc/diamond/3.11_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1800,1-1872,10) (VERI-9000) elaborating module 'EFB_uniq_1'
|
||||
Done: design load finished with (0) errors, and (0) warnings
|
||||
Done: design load finished with (0) errors, and (2) warnings
|
||||
|
||||
</PRE></BODY></HTML>
|
||||
@ -1,3 +1,3 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<userSetting name="//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml" version="Diamond (64-bit) 3.11.3.469" date="Sat Jun 08 04:44:51 2024" vendor="Lattice Semiconductor Corporation" >
|
||||
<userSetting name="//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml" version="Diamond (64-bit) 3.11.3.469" date="Fri Jul 12 16:10:19 2024" vendor="Lattice Semiconductor Corporation" >
|
||||
</userSetting>
|
||||
|
||||
70
CPLD/LCMXO2-640HC-NODHGR/RAM2E_LCMXO2_640HC_tcl.html
Normal file
70
CPLD/LCMXO2-640HC-NODHGR/RAM2E_LCMXO2_640HC_tcl.html
Normal file
@ -0,0 +1,70 @@
|
||||
<HTML>
|
||||
<HEAD><TITLE>Lattice TCL Log</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="pn240608044453"></A><B><U><big>pn240608044453</big></U></B>
|
||||
#Start recording tcl command: 6/7/2024 20:49:46
|
||||
#Project Location: //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC-NODHGR; Project name: RAM2E_LCMXO2_640HC
|
||||
prj_project open "//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC-NODHGR/RAM2E_LCMXO2_640HC.ldf"
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
#Stop recording: 6/8/2024 04:44:53
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
@ -1,6 +1,6 @@
|
||||
NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
|
||||
NOTE All Rights Reserved *
|
||||
NOTE DATE CREATED: Fri Jun 07 20:50:20 2024 *
|
||||
NOTE DATE CREATED: Fri Jul 12 16:08:40 2024 *
|
||||
NOTE DESIGN NAME: RAM2E *
|
||||
NOTE DEVICE NAME: LCMXO2-640HC-4TQFP100 *
|
||||
NOTE PIN ASSIGNMENTS *
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
----------------------------------------------------------------------
|
||||
Report for cell RAM2E.verilog
|
||||
|
||||
Register bits: 125 of 640 (20%)
|
||||
Register bits: 124 of 640 (19%)
|
||||
PIC Latch: 0
|
||||
I/O cells: 70
|
||||
Cell usage:
|
||||
@ -9,7 +9,7 @@ I/O cells: 70
|
||||
BB 8 100.0
|
||||
CCU2D 9 100.0
|
||||
EFB 1 100.0
|
||||
FD1P3AX 58 100.0
|
||||
FD1P3AX 57 100.0
|
||||
FD1P3IX 1 100.0
|
||||
FD1S3AX 31 100.0
|
||||
FD1S3AY 4 100.0
|
||||
@ -22,7 +22,8 @@ I/O cells: 70
|
||||
OFS1P3BX 6 100.0
|
||||
OFS1P3DX 12 100.0
|
||||
OFS1P3IX 3 100.0
|
||||
ORCALUT4 275 100.0
|
||||
ORCALUT4 268 100.0
|
||||
PFUMX 10 100.0
|
||||
PUR 1 100.0
|
||||
VHI 3 100.0
|
||||
VLO 3 100.0
|
||||
@ -30,23 +31,24 @@ SUB MODULES
|
||||
RAM2E_UFM 1 100.0
|
||||
REFB 1 100.0
|
||||
|
||||
TOTAL 494
|
||||
TOTAL 496
|
||||
----------------------------------------------------------------------
|
||||
Report for cell RAM2E_UFM.netlist
|
||||
Instance path: ram2e_ufm
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
EFB 1 100.0
|
||||
FD1P3AX 29 50.0
|
||||
FD1P3AX 29 50.9
|
||||
FD1P3IX 1 100.0
|
||||
FD1S3IX 1 11.1
|
||||
ORCALUT4 268 97.5
|
||||
ORCALUT4 260 97.0
|
||||
PFUMX 10 100.0
|
||||
VHI 2 66.7
|
||||
VLO 2 66.7
|
||||
SUB MODULES
|
||||
REFB 1 100.0
|
||||
|
||||
TOTAL 305
|
||||
TOTAL 307
|
||||
----------------------------------------------------------------------
|
||||
Report for cell REFB.netlist
|
||||
Instance path: ram2e_ufm.ufmefb
|
||||
|
||||
@ -4,10 +4,10 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Fri Jun 07 20:50:16 2024
|
||||
Fri Jul 12 16:08:36 2024
|
||||
|
||||
|
||||
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC-NODHGR -w -jedec -gui RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf
|
||||
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC-NODHGR -w -jedec -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC-NODHGR/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf
|
||||
|
||||
Loading design for application Bitgen from file RAM2E_LCMXO2_640HC_impl1.ncd.
|
||||
Design name: RAM2E
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -2,7 +2,7 @@
|
||||
NOTE Diamond (64-bit) 3.11.3.469 JEDEC Compatible Fuse File.*
|
||||
NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation.*
|
||||
NOTE All Rights Reserved.*
|
||||
NOTE DATE CREATED: Fri Jun 07 20:50:17 2024*
|
||||
NOTE DATE CREATED: Fri Jul 12 16:08:37 2024*
|
||||
NOTE DESIGN NAME: RAM2E_LCMXO2_640HC_impl1.ncd*
|
||||
NOTE DEVICE NAME: LCMXO2-640HC-4TQFP100*
|
||||
NOTE JEDEC FILE STATUS: Final Version 1.95*
|
||||
@ -82,423 +82,423 @@ QF171904*
|
||||
G0*
|
||||
F0*
|
||||
L000000
|
||||
11111111111111111011110110110011111111111111111100111011000000000000000000000000000000100000000000000000000000000000010100101000
|
||||
00001001001100000000011001010000010010001111111101000110000000000000000000000000101110001110000000000000110101110000000000000000
|
||||
11111111111111111011110110110011111111111111111100111011000000000000000000000000000000100000000000000000000000000011000001010000
|
||||
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|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000010001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000001001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000100011000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010100100000100011000
|
||||
00000000100010000100000000000000000000000001000100100110000100011000000000000000000000000000000000000000000000000000000000001000
|
||||
01100100000010000110010010011000010000001001100000010000100100001000000010010010010000000000000000010010000100000010001100010011
|
||||
00000000000000000000000000000000000000000000000000000000000000000000100011000010010100000001001110000010011100001101110000000000
|
||||
00000100000000000100100100111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100111000000
|
||||
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|
||||
01000001000100000010001000000000000000010000010001100001000011011001001110000000000000000000000000000000000000000000000000000000
|
||||
00010000100000100001000000000000000000000000000000000000000000000011001000101001100000000000000000000000000000000000000000000000
|
||||
00000000000000000000100011000001000100000000000010001100010011100000100111000000000000000010010100000000000000000000000000000000
|
||||
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|
||||
00000000000000000000000000000000000000001001100000000000000000000000000000010010100100010000000000000000000010111000000100010000
|
||||
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|
||||
00000000010000100001000001010100000000000000000000000000000000000000000000000000100011000001001000000000000000000000000010010100
|
||||
01001110000000100000000000000100100000100010001000010010011110010100000000000000000000000000000000000000000000000000000000000000
|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
00000000000000000000000000000000000000000000000000000000000010001100001000000000001110010000001001110100000110001100000000000000
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
00010000000000000000000000000000000100011100010100010001001011010110000000000000000000000000000000000000000000000000000000000000
|
||||
01000000001000000010010100000000101101100010100111001100100100100011000000001000110000000010001001010010000000000000000010100110
|
||||
01010000000000000000000000000000000000000000000000000001000100000110011001011010001000010010000010001000011001000101001100000100
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
00000000000000000000000000000000000000000000101010000001011000000110001000110001100001100010001001110100000100110011001001010000
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
00000000000000000000000000000000100010110000101000100100110010010010010110011100000110000101000001100010100100011000100001111011
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
00100110010010010010110011100100101100101100011000011001000010010011001000001100100100100111111001000010010010010010001011100001
|
||||
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|
||||
00000000000000000000000000000000000000100110101101110010001001000001001100111010011010000110111010011010011001000110100111100100
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11001001100000011011000101001000000110001110010011000011000011100000000101001010100100000000000000000000000000000000001101001111
|
||||
00000000000000001000100000000000000000000000100000011001001101001101110001000001000011001011000011100000011001011001100111000110
|
||||
00010100010011111001100101010111001111001111001110000100001100111000000000001001110000000000010001100000000000010001000000000000
|
||||
01100111100001001100000000010001000000000000000000000000001001111000100111001000010001101100100010100111010010010011010010010001
|
||||
01110001000010000110010001001011000000100001000000000000000000000000000000000000000000000000001100001111001100111000010001100000
|
||||
00001001110000000000000000000000000010000110000011100001000001111100100110010000111000110000110011001010000110001010010100001101
|
||||
10010010011110100110001100100110000001001110100010000000000000000000001011100000000000000001100000111000001001011001110000000000
|
||||
00000000000000000000000000001110010000100011100111100110100001010001010011000100101101100100011100111010100110011000010011000000
|
||||
00000000000000000000000000000000000000000010000000000000000100100000000000000000000101100000000000000000010010001110000001100001
|
||||
10011000011000010101000000100110111001001010110011100010011100001010110000001100111000110010110111000011101101100000000100011000
|
||||
01000100001001110000000000000000000000000000000000000000001111101000000010000000000000000000000000000100010100111000000100101100
|
||||
10001110000100100110100001010000011010001000100001011101000000101101110110001010011100001100011001111000100010011000000010001001
|
||||
00010010011101001000100010010011100000000000000000000000000100100100111001110000100111100000000000000001000010000000000000000000
|
||||
00000000000100001001000011000001100100001110011100000100001110110000001000010100011111001000001001010010011111100010101001100000
|
||||
11110010000010000110111001111000000010001100010011001000110000000000010000110011100000000000100110011001001000000000000000001000
|
||||
01100111000000001011100000000000000000000000000100101011100001001001001001100011000100011001001001010011011000001100100010100010
|
||||
10101001000100000000100101000101011100011100011011010001001001111110010101111000010011100010000110100010010011100000000000000000
|
||||
00000010010000000000000001000000000000000000000000000000000000000000001000001000011110000100010010110001010001010000010011010011
|
||||
11101010010110000110010001010101100010001010010010000011100100001000110100001100010000011001001001001000100101000100100010010100
|
||||
00000000000000000000000000010001000000000011110000000011011010000100110000000000000000000000000000000100000100101010010010011110
|
||||
01010001000001000010011001010110101001100001100111000110001000110000101001100001000000000100010010011101001110100010011100001010
|
||||
00000000000000000000000000101100001000001111000000000000001001110000000000000000000000000000000000000010101101001110001100011000
|
||||
10011110011000010011110001010010110001100111000010010011011100011001000110001100011000100011100011001001100100011010000101001100
|
||||
00000000000000000000000000001000100100110010011000000100011011000110000010000110011100000000000000000000000000000100100100111100
|
||||
10100011001001000110001100010011101000101100010100100011101010100001010000110100111100100000110100001010010010011000100110100110
|
||||
10111110100110001101101000100100111110001010011010001001110001000010001010011100000000000000000000000001001100011000110000000000
|
||||
00100100000010011100000000000000000000000000000000010110101001101000001001101011111000011110001101111000001011000000111010100010
|
||||
00000100110100110010000111000100011110100000111000100001000110100000000010010001001010010010010010001001010000000000000000000000
|
||||
00001001001000100100111101011000000000000000000000000000000000000000000010111101111111110110010111101110111011111110111001100001
|
||||
11110100001010001110101010011011011111100000011011001110111100110011010110110011101111111010000111111111010110111101111111111111
|
||||
10111100100101101111111111111111011010010011110111111111111110111100100101101111111111111111010100100000000000000000000000000000
|
||||
01001100000000000000000000000000000000000000000011110011011001001010001010001000111110111010111110111010010010100011111111101000
|
||||
11111101111110100010010011001000110010100011101010101001001010111010001000111010000001100111110110000110111101111001100111101111
|
||||
01100001101111100110011111011000011011110111100110011110111101100001101111100110011111010001100000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000001111111010010100010100001010001010000111100110111011101111000111110001000111011101101010
|
||||
00101000100011111011101111000011110101000101000011001110110001101111111110000110111101111001100111101111011000011011111001100111
|
||||
11011000011011110111100110011110111101100001101111100110011111110001100000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000001100110010011110111111101001111011111010101001000111100111111001100110111000010111101100110111101111111001100111
|
||||
01010111011101111110011110111111111011011100110110111111100011111111001101000001111011111111111111011110000010110111111111111111
|
||||
10110100000111101111111111111101111000001011011111111010000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000010011100110000001110010010001111110000000011000100010010011100100000001001110010000000001000001111010011100100100011111
|
||||
10001001101101000100000111101001110010010001111110001001101101000100000111101000000000000000000000000000000000110000001111110000
|
||||
00000000000000000000000000000000000000100100000000000001000001010011010010001000000000010001010100110010100000000000000000000100
|
||||
00000000000000000000000000000000000000000010011001000011001100000000000000000000000010001000000000000010000100000000001000101000
|
||||
00010010000000000010001000000001001110000100110111010000000000000001001011001100000000000000000000000000001101100000001001100000
|
||||
00000000000000000000000000000000100010000001000010000000000000000000000000000001010101001000000000000101010100100000000000000000
|
||||
00010011100000000011100100000100000000000000000000000000000011110000000000000000010000000000000000100111000000000001000000000001
|
||||
00010000100011011000101000000000000010010000000000000000000000000000000000000000000000000000110010010000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000110011110000100001100110000000000000000000000010000110011000000
|
||||
00000000000000000010001000000000000000000000000000000000000100010000010000100000000000000001100001111000011001111001001110010011
|
||||
00000000000000000000000010011000000000000000000000000000000000000000100011000000000000000000000000000000000000000000110000111100
|
||||
01100000011100111010000000000000000000000000000110010010110001010011100000000001011110000000000010000000000000000000100101000000
|
||||
00000000000000100000000001001000000000000000000001000010000000000000000000000000000000000000000000000000010011011110010000010010
|
||||
00000000101110000000000010010000000000000000000000000000000000000000000001100111100110001100010000100001000000000000000000000000
|
||||
00001000000000000010111001010100000000011010011000010011100000000100101000000000010011110111000000000000000000000000000000000010
|
||||
00011100001111000110011110011100100000000000000000000000000000000000000000010001001001110000000010010010011000000000000000000000
|
||||
00000000000000000000000000000000100110000011000011110000000100001000000000000000000000000000000000000010010101001001011000000000
|
||||
01000100110101100010011001100000011000001001000000000000000000000000000000000000000000010010000000000000011001111000000000000001
|
||||
00100000000000000000000000000000000000000000000000010000100000000000000000000000001001110000000000000000010011101001110100010011
|
||||
00001111001100111000000000000000000000000000000000000000000000000000000000000001000110000000000000000100010000000000000000000000
|
||||
00000100010001000000000000100101000000000000000000000000000000000000000000000000000000000001001010000000000000000000000001001000
|
||||
00000100001100111001011100000001001001010100010111100000001001111010100000000000100110000000000000000000000000000000000000000001
|
||||
01100000010000000000000000010110000001000000000000000000000000000000000000000000001111001000000000000000000000000000000000000000
|
||||
01000000000000010000100000000000000000000000000000000000000000000000000100010000001000100001001101001100001001000000000000000000
|
||||
00000000000000000000000010001000010011100001001100000000000000001011000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000100001001000000101111100100000000000000000000000000000000000000000000000001000000000000000
|
||||
00000000000000000000000000000000000000000000000010001000100000000000000000101100000001011000000000000000000000000000000000000000
|
||||
00000001001110010001100000111110000000100011000000000000000000000001101000100010011000000000000100110000000010000000010011000000
|
||||
00000000000000001001000110101100000000000010001101001101000001001100000000000000001010100000000000100111001001000100110000000000
|
||||
00000000000000100100000000000110011100001001000000000010011010100100100011000000000000000000001000110000000000010010100000000000
|
||||
00000010001100000010010100000000000000000000000000100110000000000100010000100101000000100111100010100100100010000000000000000000
|
||||
00000000000000000001001000000000000000001001000101010000001100011000001101000100011011100000000000000000000000001000100000000000
|
||||
10011110001101001100000010000100010011001110110000100110000000000000000000000010011100000000000101010000000000000000101001001000
|
||||
01000000001110010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000100001000000000000000000000000000000000000000000000000000000000000000000010000
|
||||
10000000000000000000000010000100000000000000000000000110011001000000000000000000000000100001000000000000000000000001000010000000
|
||||
00111111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000100000010011110110110010100000000000100101100001000000000010010110000100000000000000000000001001011000
|
||||
01000000000010010110000100000000000000000000000000000000000000000000000000010001111011000000000000001000000100110000000000100000
|
||||
01001100000000000000000000000010011000000000000100110000000000000000000000000000000000000000000000000000000110001000111100000101
|
||||
00000000000000010011110000100000000001001111000010000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000001000000100111000000000010000100010010100000001000010001001010000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000110001000111010000011001100000000101011110001100010000011111110011111100000000000010101111000110001
|
||||
00000111111100111111000000000000000000000000100010100100110001100111101000011110100000000000010001010010011000110011110100001111
|
||||
01000000000000000000000000000000000000000000000000000000000001100011001111110000111111000000000000101011110001100010000011111110
|
||||
01111110000000000001010111100011000100000111111100111111000000000000000000000000001100011001111110000111111000000000000001100011
|
||||
00111111000011111100000000000000000000000000000000000000000001001110000000000000000010011100000000000000000000000001010111100011
|
||||
00011000110011110000001100111000000000000010101111000110001100011001111000000110011100000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000001000011000111000111001111001110101011110001100011000110011110000001100111010101111000110001
|
||||
10001100111100000011001110000000000000101011110001100011000110011110000001100111000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000100011000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00100001000000000000000000000000000000000000000000000000000000000000000000010000100000000000000000000000100001000000000000000000
|
||||
00000110011001000000000000000000000000100001000000000000000000000001000010000000001111110000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000100111101100100
|
||||
10100000000000100101100001000000000010010110000100000000000000000000001001011000010000000000100101100001000000000000000000000000
|
||||
00000000000000000000000000010001111011000000000000001000000100110000000000100000010011000000000000000000000000100110000000000001
|
||||
00110000000000000000000000000000000000000000000000000000000110001000111100000101000000000000000100111100001000000000010011110000
|
||||
10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000001001110000000000100001000100101
|
||||
00000001000010001001010000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100010001110100000
|
||||
11001100000000101101110001100010000011111110011111100000000000010110111000110001000001111111001111110000000000000000000000001000
|
||||
10100100110001100111101000011110100000000000010001010010011000110011110100001111010000000000000000000000000000000000000000000000
|
||||
00000000000001100011001111110000111111000000000000101101110001100010000011111110011111100000000000010110111000110001000001111111
|
||||
00111111000000000000000000000000001100011001111110000111111000000000000001100011001111110000111111000000000000000000000000000000
|
||||
00000000000001001110000000000000000010011100000000000000000000000001011011100011000110001100111100000011001110000000000000101101
|
||||
11000110001100011001111000000110011100000000000000000000000000000000000000000000000000000000000000000000000000000000010000110001
|
||||
11000111001111001110101101110001100011000110011110000001100111010110111000110001100011001111000000110011100000000000001011011100
|
||||
01100011000110011110000001100111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000110
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000001000001000110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000001000011000110000000000000000000000000000000010010100000000000000011100010100000010000100110100101111111111111111
|
||||
11111111111111111111111111111111111111111111111111000010100000000000000000000000000000000000000000000000000000000010101010100111
|
||||
00100010000000000000000000000000010000000000000000000000000000001111111111111111111111111111111101011110000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000010001100000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000110001100000000000000000000
|
||||
00000000000010010100000000000000011100010100000000001011101111101111111111111111111111111111111111111111111111111111111111111111
|
||||
11000010100000000000000000000000000000000000000000000000000000000010101010100111001000100000000000000000000000000100000000000000
|
||||
00000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111101011110000000000000000000000000
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
*
|
||||
NOTE END CONFIG DATA*
|
||||
L52992
|
||||
L52352
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
@ -1432,10 +1432,10 @@ L171648
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
*
|
||||
C9E6F*
|
||||
C8CD3*
|
||||
NOTE FEATURE_ROW*
|
||||
E0000000000000000000000000000000000000000000000000000000000000000
|
||||
0000010001100000*
|
||||
NOTE User Electronic Signature Data*
|
||||
UH00000000*
|
||||
56E0
|
||||
55A6
|
||||
|
||||
@ -9,25 +9,26 @@ Command line: map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial
|
||||
RAM2E_LCMXO2_640HC_impl1.ngd -o RAM2E_LCMXO2_640HC_impl1_map.ncd -pr
|
||||
RAM2E_LCMXO2_640HC_impl1.prf -mp RAM2E_LCMXO2_640HC_impl1.mrp -lpf //Mac/iC
|
||||
loud/Repos/RAM2E/CPLD/LCMXO2-640HC-NODHGR/impl1/RAM2E_LCMXO2_640HC_impl1_sy
|
||||
nplify.lpf -lpf //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf -c 0 -gui
|
||||
nplify.lpf -lpf //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf -c 0 -gui
|
||||
-msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC-NODHGR/promote.xml
|
||||
Target Vendor: LATTICE
|
||||
Target Device: LCMXO2-640HCTQFP100
|
||||
Target Performance: 4
|
||||
Mapper: xo2c00, version: Diamond (64-bit) 3.11.3.469
|
||||
Mapped on: 06/07/24 20:49:58
|
||||
Mapped on: 07/12/24 16:07:45
|
||||
|
||||
Design Summary
|
||||
--------------
|
||||
|
||||
Number of registers: 125 out of 877 (14%)
|
||||
PFU registers: 103 out of 640 (16%)
|
||||
Number of registers: 124 out of 877 (14%)
|
||||
PFU registers: 102 out of 640 (16%)
|
||||
PIO registers: 22 out of 237 (9%)
|
||||
Number of SLICEs: 148 out of 320 (46%)
|
||||
SLICEs as Logic/ROM: 148 out of 320 (46%)
|
||||
Number of SLICEs: 145 out of 320 (45%)
|
||||
SLICEs as Logic/ROM: 145 out of 320 (45%)
|
||||
SLICEs as RAM: 0 out of 240 (0%)
|
||||
SLICEs as Carry: 9 out of 320 (3%)
|
||||
Number of LUT4s: 296 out of 640 (46%)
|
||||
Number used as logic LUTs: 278
|
||||
Number of LUT4s: 289 out of 640 (45%)
|
||||
Number used as logic LUTs: 271
|
||||
Number used as distributed RAM: 0
|
||||
Number used as ripple logic: 18
|
||||
Number used as shift registers: 0
|
||||
@ -51,53 +52,54 @@ Design Summary
|
||||
2. Number of logic LUT4s does not include count of distributed RAM and
|
||||
ripple logic.
|
||||
Number of clocks: 2
|
||||
Net C14M_c: 85 loads, 63 rising, 22 falling (Driver: PIO C14M )
|
||||
Net C14M_c: 84 loads, 62 rising, 22 falling (Driver: PIO C14M )
|
||||
Net PHI1_c: 3 loads, 0 rising, 3 falling (Driver: PIO PHI1 )
|
||||
Number of Clock Enables: 13
|
||||
Net N_117_i: 2 loads, 0 LSLICEs
|
||||
Net RWBank14: 11 loads, 11 LSLICEs
|
||||
Net N_347_i: 2 loads, 0 LSLICEs
|
||||
Net RWBank14: 10 loads, 10 LSLICEs
|
||||
Net ram2e_ufm/wb_adr_0_sqmuxa_1_i: 1 loads, 1 LSLICEs
|
||||
Net un9_VOE_0_a2_0_a2: 1 loads, 1 LSLICEs
|
||||
Net un6_DOEEN_0_a2_0_a2: 2 loads, 2 LSLICEs
|
||||
Net ram2e_ufm/un1_wb_adr_0_sqmuxa_2_i[0]: 8 loads, 8 LSLICEs
|
||||
Net ram2e_ufm/N_63: 1 loads, 1 LSLICEs
|
||||
|
||||
Page 1
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 06/07/24 20:49:58
|
||||
Design: RAM2E Date: 07/12/24 16:07:45
|
||||
|
||||
Design Summary (cont)
|
||||
---------------------
|
||||
Net ram2e_ufm/un1_wb_cyc_stb_0_sqmuxa_1_i[0]: 1 loads, 1 LSLICEs
|
||||
Net ram2e_ufm/N_111: 1 loads, 1 LSLICEs
|
||||
Net ram2e_ufm/N_104: 4 loads, 4 LSLICEs
|
||||
Net ram2e_ufm/N_98: 1 loads, 1 LSLICEs
|
||||
Net un1_CKE48_0_i: 6 loads, 6 LSLICEs
|
||||
Net N_389_i: 2 loads, 0 LSLICEs
|
||||
Net ram2e_ufm/un1_wb_adr_0_sqmuxa_2_i_0[0]: 8 loads, 8 LSLICEs
|
||||
Net ram2e_ufm/un1_CmdBitbangMXO212_1_i[0]: 1 loads, 1 LSLICEs
|
||||
Net ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0[0]: 4 loads, 4 LSLICEs
|
||||
Net ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0[0]: 1 loads, 1 LSLICEs
|
||||
Net un9_VOE_0_a2: 1 loads, 1 LSLICEs
|
||||
Net un1_CKE48_i: 6 loads, 6 LSLICEs
|
||||
Net N_346_i: 2 loads, 0 LSLICEs
|
||||
Net Vout3: 8 loads, 0 LSLICEs
|
||||
Number of LSRs: 8
|
||||
Net N_148: 2 loads, 2 LSLICEs
|
||||
Net N_430_i: 2 loads, 0 LSLICEs
|
||||
Number of LSRs: 9
|
||||
Net un1_CS_0_sqmuxa_i: 2 loads, 2 LSLICEs
|
||||
Net ram2e_ufm.wb_rst13: 2 loads, 0 LSLICEs
|
||||
Net RC7: 2 loads, 2 LSLICEs
|
||||
Net S[2]: 2 loads, 2 LSLICEs
|
||||
Net S[1]: 1 loads, 1 LSLICEs
|
||||
Net ram2e_ufm/wb_rst: 1 loads, 0 LSLICEs
|
||||
Net ram2e_ufm/nRWE_0_i_o3_RNIP8E61: 1 loads, 1 LSLICEs
|
||||
Net N_530: 1 loads, 0 LSLICEs
|
||||
Net N_301_i: 1 loads, 1 LSLICEs
|
||||
Net ram2e_ufm/wb_rst6_i: 1 loads, 1 LSLICEs
|
||||
Net N_523_1: 1 loads, 0 LSLICEs
|
||||
Net N_727_0: 1 loads, 1 LSLICEs
|
||||
Net RATc_i: 1 loads, 1 LSLICEs
|
||||
Number of nets driven by tri-state buffers: 0
|
||||
Top 10 highest fanout non-clock nets:
|
||||
Net S[2]: 60 loads
|
||||
Net S[3]: 48 loads
|
||||
Net S[1]: 46 loads
|
||||
Net S[0]: 31 loads
|
||||
Net FS[11]: 24 loads
|
||||
Net FS[10]: 23 loads
|
||||
Net FS[12]: 23 loads
|
||||
Net FS[9]: 23 loads
|
||||
Net FS[13]: 21 loads
|
||||
Net FS[8]: 18 loads
|
||||
Net S[2]: 51 loads
|
||||
Net S[1]: 44 loads
|
||||
Net S[3]: 40 loads
|
||||
Net S[0]: 32 loads
|
||||
Net FS[8]: 29 loads
|
||||
Net FS[9]: 26 loads
|
||||
Net FS[10]: 25 loads
|
||||
Net FS[11]: 23 loads
|
||||
Net FS[13]: 20 loads
|
||||
Net ram2e_ufm.wb_rst13: 17 loads
|
||||
|
||||
|
||||
|
||||
@ -121,21 +123,22 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
||||
WARNING - map: IO buffer missing for top level port nWE80...logic will be
|
||||
discarded.
|
||||
|
||||
IO (PIO) Attributes
|
||||
-------------------
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| IO Name | Direction | Levelmode | IO |
|
||||
|
||||
|
||||
|
||||
Page 2
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 06/07/24 20:49:58
|
||||
Design: RAM2E Date: 07/12/24 16:07:45
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
IO (PIO) Attributes
|
||||
-------------------
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| IO Name | Direction | Levelmode | IO |
|
||||
| | | IO_TYPE | Register |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[0] | BIDIR | LVCMOS33 | |
|
||||
@ -189,19 +192,19 @@ IO (PIO) Attributes (cont)
|
||||
| BA[1] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| BA[0] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRWEout | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
Page 3
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 06/07/24 20:49:58
|
||||
Design: RAM2E Date: 07/12/24 16:07:45
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRWEout | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nCASout | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRASout | OUTPUT | LVCMOS33 | OUT |
|
||||
@ -255,19 +258,19 @@ IO (PIO) Attributes (cont)
|
||||
| Din[4] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[3] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[2] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
Page 4
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 06/07/24 20:49:58
|
||||
Design: RAM2E Date: 07/12/24 16:07:45
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[2] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[1] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[0] | INPUT | LVCMOS33 | |
|
||||
@ -321,19 +324,19 @@ Signal ram2e_ufm/ufmefb/TCINT undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIIRQO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPICSNEN undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
|
||||
|
||||
Page 5
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 06/07/24 20:49:58
|
||||
Design: RAM2E Date: 07/12/24 16:07:45
|
||||
|
||||
Removed logic (cont)
|
||||
--------------------
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
|
||||
@ -388,15 +391,13 @@ Block ram2e_ufm/ufmefb/GND was optimized away.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Page 6
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 06/07/24 20:49:58
|
||||
Design: RAM2E Date: 07/12/24 16:07:45
|
||||
|
||||
|
||||
Embedded Functional Block Connection Summary
|
||||
--------------------------------------------
|
||||
@ -446,7 +447,7 @@ Run Time and Memory Usage
|
||||
-------------------------
|
||||
|
||||
Total CPU Time: 0 secs
|
||||
Total REAL Time: 0 secs
|
||||
Total REAL Time: 2 secs
|
||||
Peak Memory Usage: 59 MB
|
||||
|
||||
|
||||
@ -456,7 +457,6 @@ Run Time and Memory Usage
|
||||
|
||||
|
||||
|
||||
|
||||
Page 7
|
||||
|
||||
|
||||
|
||||
@ -6,7 +6,7 @@ Performance Grade: 4
|
||||
PACKAGE: TQFP100
|
||||
Package Status: Final Version 1.39
|
||||
|
||||
Fri Jun 07 20:50:08 2024
|
||||
Fri Jul 12 16:08:09 2024
|
||||
|
||||
Pinout by Port Name:
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
@ -283,5 +283,5 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Fri Jun 07 20:50:12 2024
|
||||
Fri Jul 12 16:08:21 2024
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
SCHEMATIC START ;
|
||||
# map: version Diamond (64-bit) 3.11.3.469 -- WARNING: Map write only section -- Fri Jun 07 20:49:59 2024
|
||||
# map: version Diamond (64-bit) 3.11.3.469 -- WARNING: Map write only section -- Fri Jul 12 16:07:47 2024
|
||||
|
||||
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
|
||||
LOCATE COMP "RD[0]" SITE "36" ;
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
#OS: Windows 8 6.2
|
||||
#Hostname: ZANEMACWIN11
|
||||
|
||||
# Fri Jun 7 20:49:50 2024
|
||||
# Fri Jul 12 16:07:05 2024
|
||||
|
||||
#Implementation: impl1
|
||||
|
||||
@ -52,6 +52,7 @@ Synopsys Verilog Compiler, Version comp2018q2p1, Build 461R, Built Apr 1 2019 0
|
||||
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC-NODHGR\REFB.v" (library work)
|
||||
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\DHGR-OFF.v" (library work)
|
||||
Verilog syntax check successful!
|
||||
File \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v changed - recompiling
|
||||
Selecting top level module RAM2E
|
||||
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
|
||||
Running optimization stage 1 on VHI .......
|
||||
@ -77,12 +78,12 @@ Running optimization stage 2 on EFB .......
|
||||
Running optimization stage 2 on VLO .......
|
||||
Running optimization stage 2 on VHI .......
|
||||
|
||||
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)
|
||||
At c_ver Exit (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
Process took 0h:00m:05s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Fri Jun 7 20:49:51 2024
|
||||
# Fri Jul 12 16:07:11 2024
|
||||
|
||||
###########################################################]
|
||||
|
||||
@ -102,13 +103,14 @@ Implementation : impl1
|
||||
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
File \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC-NODHGR\impl1\synwork\layer0.srs changed - recompiling
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Fri Jun 7 20:49:51 2024
|
||||
# Fri Jul 12 16:07:12 2024
|
||||
|
||||
###########################################################]
|
||||
|
||||
@ -118,12 +120,12 @@ For a summary of runtime and memory usage for all design units, please see file:
|
||||
|
||||
@END
|
||||
|
||||
At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
|
||||
At c_hdl Exit (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
Process took 0h:00m:06s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Fri Jun 7 20:49:51 2024
|
||||
# Fri Jul 12 16:07:12 2024
|
||||
|
||||
###########################################################]
|
||||
|
||||
@ -143,18 +145,17 @@ Database state : \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC-NODHGR\impl1\synwork
|
||||
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
File \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC-NODHGR\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_comp.srs changed - recompiling
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Fri Jun 7 20:49:52 2024
|
||||
# Fri Jul 12 16:07:14 2024
|
||||
|
||||
###########################################################]
|
||||
Premap Report
|
||||
|
||||
# Fri Jun 7 20:49:53 2024
|
||||
# Fri Jul 12 16:07:14 2024
|
||||
|
||||
|
||||
Copyright (C) 1994-2018 Synopsys, Inc.
|
||||
@ -199,7 +200,7 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h
|
||||
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":21:4:21:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
|
||||
@N: MH105 |UMR3 is only supported for HAPS-80.
|
||||
@N: MH105 |UMR3 is only supported for HAPS-80.
|
||||
@N: BN115 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":140:9:140:12|Removing instance dhgr (in view: work.RAM2E(verilog)) of type view:work.DHGR(verilog) because it does not drive other instances.
|
||||
@N: BN115 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":136:9:136:12|Removing instance dhgr (in view: work.RAM2E(verilog)) of type view:work.DHGR(verilog) because it does not drive other instances.
|
||||
syn_allowed_resources : blockrams=2 set on top level netlist RAM2E
|
||||
|
||||
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
|
||||
@ -212,7 +213,7 @@ Clock Summary
|
||||
Start Requested Requested Clock Clock Clock
|
||||
Level Clock Frequency Period Type Group Load
|
||||
-----------------------------------------------------------------------------------------------
|
||||
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 121
|
||||
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 120
|
||||
|
||||
0 - System 100.0 MHz 10.000 system system_clkgroup 0
|
||||
|
||||
@ -227,7 +228,7 @@ Clock Load Summary
|
||||
Clock Source Clock Pin Non-clock Pin Non-clock Pin
|
||||
Clock Load Pin Seq Example Seq Example Comb Example
|
||||
--------------------------------------------------------------------------------------------
|
||||
C14M 121 C14M(port) RAT.C - un1_C14M.I[0](inv)
|
||||
C14M 120 C14M(port) RAT.C - un1_C14M.I[0](inv)
|
||||
|
||||
System 0 - - - -
|
||||
|
||||
@ -247,14 +248,14 @@ Number of ICG latches not removed: 0
|
||||
|
||||
#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
|
||||
|
||||
2 non-gated/non-generated clock tree(s) driving 125 clock pin(s) of sequential element(s)
|
||||
2 non-gated/non-generated clock tree(s) driving 124 clock pin(s) of sequential element(s)
|
||||
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
|
||||
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
|
||||
|
||||
=========================== Non-Gated/Non-Generated Clocks ============================
|
||||
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
|
||||
---------------------------------------------------------------------------------------
|
||||
@KP:ckid0_0 C14M port 121 PHI1r
|
||||
@KP:ckid0_0 C14M port 120 PHI1r
|
||||
@KP:ckid0_1 PHI1 Unconstrained_port 4 RC[2:0]
|
||||
=======================================================================================
|
||||
|
||||
@ -264,27 +265,25 @@ Clock Tree ID Driving Element Drive Element Type Fanout Sample I
|
||||
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
|
||||
Finished Pre Mapping Phase.
|
||||
|
||||
Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
|
||||
Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
|
||||
|
||||
|
||||
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
|
||||
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
|
||||
|
||||
None
|
||||
None
|
||||
|
||||
Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
|
||||
Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
|
||||
|
||||
Pre-mapping successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB)
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Fri Jun 7 20:49:53 2024
|
||||
Process took 0h:00m:02s realtime, 0h:00m:01s cputime
|
||||
# Fri Jul 12 16:07:18 2024
|
||||
|
||||
###########################################################]
|
||||
Map & Optimize Report
|
||||
|
||||
# Fri Jun 7 20:49:53 2024
|
||||
# Fri Jul 12 16:07:21 2024
|
||||
|
||||
|
||||
Copyright (C) 1994-2018 Synopsys, Inc.
|
||||
@ -319,12 +318,12 @@ Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0
|
||||
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
|
||||
|
||||
|
||||
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
|
||||
Finished loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
|
||||
|
||||
@N: MF284 |Setting synthesis effort to medium for the design
|
||||
|
||||
|
||||
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
|
||||
Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
|
||||
|
||||
|
||||
Available hyper_sources - for debug and ip models
|
||||
@ -333,61 +332,61 @@ Available hyper_sources - for debug and ip models
|
||||
@N: FX493 |Applying initial value "00000000" on instance RWBank[7:0].
|
||||
@N: FX493 |Applying initial value "0000" on instance S[3:0].
|
||||
|
||||
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)
|
||||
Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)
|
||||
|
||||
@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":14:23:14:28|Found counter in view:work.RAM2E(verilog) instance FS[15:0]
|
||||
|
||||
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 142MB)
|
||||
Starting factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 142MB)
|
||||
|
||||
|
||||
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
|
||||
Finished factoring (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
|
||||
|
||||
|
||||
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
|
||||
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
|
||||
|
||||
|
||||
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
|
||||
Starting Early Timing Optimization (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
|
||||
|
||||
|
||||
Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
|
||||
Finished Early Timing Optimization (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
|
||||
|
||||
|
||||
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
|
||||
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
|
||||
|
||||
|
||||
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
|
||||
Finished preparing to map (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 147MB)
|
||||
|
||||
|
||||
Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
|
||||
Finished technology mapping (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
|
||||
|
||||
Pass CPU time Worst Slack Luts / Registers
|
||||
------------------------------------------------------------
|
||||
1 0h:00m:01s 6.90ns 281 / 125
|
||||
1 0h:00m:01s 6.90ns 280 / 124
|
||||
|
||||
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
|
||||
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
|
||||
|
||||
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
|
||||
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":171:4:171:9|Boundary register BA_1_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
||||
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":171:4:171:9|Boundary register BA_0_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
||||
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":168:4:168:9|Boundary register BA_1_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
||||
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":168:4:168:9|Boundary register BA_0_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
||||
|
||||
Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 158MB peak: 160MB)
|
||||
Finished restoring hierarchy (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:01s; Memory used current: 158MB peak: 160MB)
|
||||
|
||||
|
||||
Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 122MB peak: 160MB)
|
||||
Start Writing Netlists (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:01s; Memory used current: 122MB peak: 160MB)
|
||||
|
||||
Writing Analyst data base \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC-NODHGR\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_m.srm
|
||||
|
||||
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 158MB peak: 160MB)
|
||||
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:02s; Memory used current: 157MB peak: 160MB)
|
||||
|
||||
Writing EDIF Netlist and constraint files
|
||||
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC-NODHGR\impl1\RAM2E_LCMXO2_640HC_impl1.edi
|
||||
N-2018.03L-SP1-1
|
||||
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
|
||||
|
||||
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 162MB peak: 164MB)
|
||||
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:02s; Memory used current: 161MB peak: 163MB)
|
||||
|
||||
|
||||
Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 161MB peak: 164MB)
|
||||
Start final timing analysis (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:03s; Memory used current: 160MB peak: 163MB)
|
||||
|
||||
@W: MT246 :"\\mac\icloud\repos\ram2e\cpld\lcmxo2-640hc-nodhgr\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
|
||||
@N: MT615 |Found clock C14M with period 69.84ns
|
||||
@ -395,7 +394,7 @@ Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:0
|
||||
|
||||
|
||||
##### START OF TIMING REPORT #####[
|
||||
# Timing Report written on Fri Jun 7 20:49:57 2024
|
||||
# Timing Report written on Fri Jul 12 16:07:33 2024
|
||||
#
|
||||
|
||||
|
||||
@ -420,9 +419,9 @@ Worst slack in design: 6.897
|
||||
Requested Estimated Requested Estimated Clock Clock
|
||||
Starting Clock Frequency Frequency Period Period Slack Type Group
|
||||
----------------------------------------------------------------------------------------------------------------------
|
||||
C14M 14.3 MHz 112.1 MHz 69.841 8.918 31.599 declared default_clkgroup
|
||||
C14M 14.3 MHz 120.3 MHz 69.841 8.314 31.675 declared default_clkgroup
|
||||
RAM2E|PHI1 100.0 MHz 322.2 MHz 10.000 3.103 6.897 inferred Inferred_clkgroup_0
|
||||
System 100.0 MHz NA 10.000 NA 67.088 system system_clkgroup
|
||||
System 100.0 MHz NA 10.000 NA 66.719 system system_clkgroup
|
||||
======================================================================================================================
|
||||
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
|
||||
|
||||
@ -437,9 +436,9 @@ Clocks | rise to rise | fall to fall | rise
|
||||
----------------------------------------------------------------------------------------------------------------
|
||||
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
|
||||
----------------------------------------------------------------------------------------------------------------
|
||||
System C14M | 69.841 67.088 | No paths - | No paths - | No paths -
|
||||
System C14M | 69.841 66.719 | No paths - | No paths - | No paths -
|
||||
C14M System | 69.841 68.797 | No paths - | No paths - | No paths -
|
||||
C14M C14M | 69.841 60.923 | No paths - | 34.920 31.599 | No paths -
|
||||
C14M C14M | 69.841 61.527 | No paths - | 34.920 31.675 | No paths -
|
||||
RAM2E|PHI1 C14M | No paths - | No paths - | No paths - | Diff grp -
|
||||
RAM2E|PHI1 RAM2E|PHI1 | No paths - | 10.000 6.897 | No paths - | No paths -
|
||||
================================================================================================================
|
||||
@ -468,10 +467,10 @@ Starting Points with Worst Slack
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
---------------------------------------------------------------------------
|
||||
S[2] C14M FD1S3AX Q S[2] 1.366 31.599
|
||||
S[3] C14M FD1S3AX Q S[3] 1.345 31.619
|
||||
S[1] C14M FD1S3AX Q S[1] 1.344 31.800
|
||||
S[0] C14M FD1S3AX Q S[0] 1.305 31.838
|
||||
S[2] C14M FD1S3AX Q S[2] 1.353 31.675
|
||||
S[3] C14M FD1S3AX Q S[3] 1.337 31.691
|
||||
S[0] C14M FD1S3AX Q S[0] 1.319 32.182
|
||||
S[1] C14M FD1S3AX Q S[1] 1.344 32.656
|
||||
RA[0] C14M FD1P3AX Q RA[0] 1.108 33.707
|
||||
RA[3] C14M FD1P3AX Q RA[3] 1.108 33.707
|
||||
RA[1] C14M FD1P3AX Q RA[1] 1.044 33.771
|
||||
@ -484,21 +483,21 @@ RA[5] C14M FD1P3AX Q RA[5] 1.044 33.771
|
||||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
-----------------------------------------------------------------------------------
|
||||
VOE_i_0io C14M OFS1P3IX CD N_530 34.118 31.599
|
||||
VOE_i_0io C14M OFS1P3IX D VOE_ic_i 35.009 31.800
|
||||
Vout_0io[0] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[1] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[2] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[3] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[4] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[5] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[6] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[7] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
===================================================================================
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------------
|
||||
VOE_i_0io C14M OFS1P3IX CD N_523_1 34.118 31.675
|
||||
RAT C14M FD1S3IX CD RATc_i 34.118 32.147
|
||||
Vout_0io[0] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[1] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[2] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[3] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[4] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[5] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[6] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[7] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
==================================================================================
|
||||
|
||||
|
||||
|
||||
@ -512,9 +511,9 @@ Path information for path number 1:
|
||||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
= Required time: 34.118
|
||||
|
||||
- Propagation time: 2.519
|
||||
- Propagation time: 2.442
|
||||
- Clock delay at starting point: 0.000 (ideal)
|
||||
= Slack (non-critical) : 31.599
|
||||
= Slack (non-critical) : 31.675
|
||||
|
||||
Number of logic level(s): 1
|
||||
Starting point: S[2] / Q
|
||||
@ -522,16 +521,16 @@ Path information for path number 1:
|
||||
The start point is clocked by C14M [rising] on pin CK
|
||||
The end point is clocked by C14M [falling] on pin SCLK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
------------------------------------------------------------------------------------------------------------
|
||||
S[2] FD1S3AX Q Out 1.366 1.366 -
|
||||
S[2] Net - - - - 58
|
||||
ram2e_ufm.un1_wb_adr_0_sqmuxa_2_0_a2_0[0] ORCALUT4 A In 0.000 1.366 -
|
||||
ram2e_ufm.un1_wb_adr_0_sqmuxa_2_0_a2_0[0] ORCALUT4 Z Out 1.153 2.519 -
|
||||
N_530 Net - - - - 3
|
||||
VOE_i_0io OFS1P3IX CD In 0.000 2.519 -
|
||||
============================================================================================================
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
---------------------------------------------------------------------------------------
|
||||
S[2] FD1S3AX Q Out 1.353 1.353 -
|
||||
S[2] Net - - - - 50
|
||||
ram2e_ufm.VOE_2_0_a2 ORCALUT4 A In 0.000 1.353 -
|
||||
ram2e_ufm.VOE_2_0_a2 ORCALUT4 Z Out 1.089 2.442 -
|
||||
N_523_1 Net - - - - 2
|
||||
VOE_i_0io OFS1P3IX CD In 0.000 2.442 -
|
||||
=======================================================================================
|
||||
|
||||
|
||||
|
||||
@ -620,7 +619,7 @@ Starting Points with Worst Slack
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
---------------------------------------------------------------------------------------------------
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBACKO wb_ack 0.000 67.088
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBACKO wb_ack 0.000 66.719
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO0 wb_dato[0] 0.000 69.313
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000 69.313
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO2 wb_dato[2] 0.000 69.313
|
||||
@ -635,21 +634,21 @@ ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO7 wb_dato[7]
|
||||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------------------
|
||||
ram2e_ufm.RWMask[0] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[1] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[2] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[3] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[4] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[5] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[6] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[7] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.LEDEN System FD1P3AX SP N_98 69.369 67.736
|
||||
ram2e_ufm.wb_cyc_stb System FD1P3AX SP N_111 69.369 67.736
|
||||
========================================================================================
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
---------------------------------------------------------------------------------------------------------------
|
||||
ram2e_ufm.wb_cyc_stb System FD1P3AX SP un1_CmdBitbangMXO212_1_i[0] 69.369 66.719
|
||||
ram2e_ufm.LEDEN System FD1P3AX SP un1_LEDEN_0_sqmuxa_1_i_0[0] 69.369 67.736
|
||||
ram2e_ufm.RWMask[0] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[1] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[2] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[3] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[4] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[5] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[6] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[7] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
===============================================================================================================
|
||||
|
||||
|
||||
|
||||
@ -663,30 +662,33 @@ Path information for path number 1:
|
||||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
= Required time: 69.369
|
||||
|
||||
- Propagation time: 2.282
|
||||
- Propagation time: 2.650
|
||||
- Clock delay at starting point: 0.000 (ideal)
|
||||
- Estimated clock delay at start point: -0.000
|
||||
= Slack (non-critical) : 67.088
|
||||
= Slack (non-critical) : 66.719
|
||||
|
||||
Number of logic level(s): 2
|
||||
Number of logic level(s): 3
|
||||
Starting point: ram2e_ufm.ufmefb.EFBInst_0 / WBACKO
|
||||
Ending point: ram2e_ufm.RWMask[0] / SP
|
||||
Ending point: ram2e_ufm.wb_cyc_stb / SP
|
||||
The start point is clocked by System [rising]
|
||||
The end point is clocked by C14M [rising] on pin CK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
----------------------------------------------------------------------------------------------------------------
|
||||
ram2e_ufm.ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 -
|
||||
wb_ack Net - - - - 5
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] ORCALUT4 B In 0.000 0.000 -
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] ORCALUT4 Z Out 1.017 1.017 -
|
||||
un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] Net - - - - 1
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 D In 0.000 1.017 -
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 Z Out 1.265 2.282 -
|
||||
N_104 Net - - - - 8
|
||||
ram2e_ufm.RWMask[0] FD1P3AX SP In 0.000 2.282 -
|
||||
================================================================================================================
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
---------------------------------------------------------------------------------------------------------------
|
||||
ram2e_ufm.ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 -
|
||||
wb_ack Net - - - - 4
|
||||
ram2e_ufm.un1_CmdBitbangMXO212_1_0_0_tz[0] ORCALUT4 B In 0.000 0.000 -
|
||||
ram2e_ufm.un1_CmdBitbangMXO212_1_0_0_tz[0] ORCALUT4 Z Out 1.017 1.017 -
|
||||
un1_CmdBitbangMXO212_1_0_0_tz[0] Net - - - - 1
|
||||
ram2e_ufm.un1_CmdBitbangMXO212_1_0_0_0[0] ORCALUT4 C In 0.000 1.017 -
|
||||
ram2e_ufm.un1_CmdBitbangMXO212_1_0_0_0[0] ORCALUT4 Z Out 1.017 2.034 -
|
||||
un1_CmdBitbangMXO212_1_0_0_0[0] Net - - - - 1
|
||||
ram2e_ufm.wb_cyc_stb_RNO_0 ORCALUT4 A In 0.000 2.034 -
|
||||
ram2e_ufm.wb_cyc_stb_RNO_0 ORCALUT4 Z Out 0.617 2.650 -
|
||||
un1_CmdBitbangMXO212_1_i[0] Net - - - - 1
|
||||
ram2e_ufm.wb_cyc_stb FD1P3AX SP In 0.000 2.650 -
|
||||
===============================================================================================================
|
||||
|
||||
|
||||
|
||||
@ -695,16 +697,16 @@ ram2e_ufm.RWMask[0] FD1P3AX SP In
|
||||
Timing exceptions that could not be applied
|
||||
None
|
||||
|
||||
Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 161MB peak: 164MB)
|
||||
Finished final timing analysis (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 163MB)
|
||||
|
||||
|
||||
Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 161MB peak: 164MB)
|
||||
Finished timing report (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 163MB)
|
||||
|
||||
---------------------------------------
|
||||
Resource Usage Report
|
||||
Part: lcmxo2_640hc-4
|
||||
|
||||
Register bits: 125 of 640 (20%)
|
||||
Register bits: 124 of 640 (19%)
|
||||
PIC Latch: 0
|
||||
I/O cells: 70
|
||||
|
||||
@ -713,7 +715,7 @@ Details:
|
||||
BB: 8
|
||||
CCU2D: 9
|
||||
EFB: 1
|
||||
FD1P3AX: 58
|
||||
FD1P3AX: 57
|
||||
FD1P3IX: 1
|
||||
FD1S3AX: 31
|
||||
FD1S3AY: 4
|
||||
@ -726,15 +728,16 @@ OB: 41
|
||||
OFS1P3BX: 6
|
||||
OFS1P3DX: 12
|
||||
OFS1P3IX: 3
|
||||
ORCALUT4: 275
|
||||
ORCALUT4: 268
|
||||
PFUMX: 10
|
||||
PUR: 1
|
||||
VHI: 3
|
||||
VLO: 3
|
||||
Mapper successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 32MB peak: 164MB)
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:03s; Memory used current: 32MB peak: 163MB)
|
||||
|
||||
Process took 0h:00m:03s realtime, 0h:00m:03s cputime
|
||||
# Fri Jun 7 20:49:57 2024
|
||||
Process took 0h:00m:14s realtime, 0h:00m:03s cputime
|
||||
# Fri Jul 12 16:07:38 2024
|
||||
|
||||
###########################################################]
|
||||
|
||||
152
CPLD/LCMXO2-640HC-NODHGR/impl1/RAM2E_LCMXO2_640HC_impl1_bgn.html
Normal file
152
CPLD/LCMXO2-640HC-NODHGR/impl1/RAM2E_LCMXO2_640HC_impl1_bgn.html
Normal file
@ -0,0 +1,152 @@
|
||||
<HTML>
|
||||
<HEAD><TITLE>Bitgen Report</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
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border-bottom: 3px solid #000; font-size: 1em;
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margin-bottom: 5px;
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color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
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a:hover, a:active {
text-decoration:underline;
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.pass
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.fail
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.comment
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}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Bgn"></A>BITGEN: Bitstream Generator Diamond (64-bit) 3.11.3.469
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Fri Jun 07 20:50:16 2024
|
||||
|
||||
|
||||
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC-NODHGR -w -jedec -gui RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf
|
||||
|
||||
Loading design for application Bitgen from file RAM2E_LCMXO2_640HC_impl1.ncd.
|
||||
Design name: RAM2E
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-640HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application Bitgen from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.11_x64/ispfpga.
|
||||
Package Status: Final Version 1.39.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
|
||||
Running DRC.
|
||||
DRC detected 0 errors and 0 warnings.
|
||||
Reading Preference File from RAM2E_LCMXO2_640HC_impl1.prf.
|
||||
|
||||
<A name="bgn_ps"></A>
|
||||
<B><U><big>Preference Summary:</big></U></B>
|
||||
|
||||
+---------------------------------+---------------------------------+
|
||||
| Preference | Current Setting |
|
||||
+---------------------------------+---------------------------------+
|
||||
| RamCfg | Reset** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MCCLK_FREQ | 2.08** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| CONFIG_SECURE | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| INBUF | ON** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| JTAG_PORT | ENABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SDM_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SLAVE_SPI_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MASTER_SPI_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| I2C_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MUX_CONFIGURATION_PORTS | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| CONFIGURATION | CFG** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| COMPRESS_CONFIG | ON** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MY_ASSP | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| ONE_TIME_PROGRAM | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| ENABLE_TRANSFR | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SHAREDEBRINIT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| BACKGROUND_RECONFIG | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
* Default setting.
|
||||
** The specified setting matches the default setting.
|
||||
|
||||
|
||||
Creating bit map...
|
||||
|
||||
Bitstream Status: Final Version 1.95.
|
||||
|
||||
Saving bit stream in "RAM2E_LCMXO2_640HC_impl1.jed".
|
||||
|
||||
===========
|
||||
UFM Summary.
|
||||
===========
|
||||
UFM Size: 191 Pages (128*191 Bits).
|
||||
UFM Utilization: General Purpose Flash Memory.
|
||||
|
||||
Available General Purpose Flash Memory: 191 Pages (Page 0 to Page 190).
|
||||
Initialized UFM Pages: 1 Page (Page 190).
|
||||
|
||||
Total CPU Time: 3 secs
|
||||
Total REAL Time: 4 secs
|
||||
Peak Memory Usage: 267 MB
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
@ -13,7 +13,7 @@ Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
|
||||
# Written on Fri Jun 7 20:49:53 2024
|
||||
# Written on Fri Jul 12 16:07:16 2024
|
||||
|
||||
##### DESIGN INFO #######################################################
|
||||
|
||||
|
||||
@ -17,24 +17,25 @@ Command line: map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial
|
||||
RAM2E_LCMXO2_640HC_impl1.ngd -o RAM2E_LCMXO2_640HC_impl1_map.ncd -pr
|
||||
RAM2E_LCMXO2_640HC_impl1.prf -mp RAM2E_LCMXO2_640HC_impl1.mrp -lpf //Mac/iC
|
||||
loud/Repos/RAM2E/CPLD/LCMXO2-640HC-NODHGR/impl1/RAM2E_LCMXO2_640HC_impl1_sy
|
||||
nplify.lpf -lpf //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf -c 0 -gui
|
||||
nplify.lpf -lpf //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf -c 0 -gui
|
||||
-msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC-NODHGR/promote.xml
|
||||
Target Vendor: LATTICE
|
||||
Target Device: LCMXO2-640HCTQFP100
|
||||
Target Performance: 4
|
||||
Mapper: xo2c00, version: Diamond (64-bit) 3.11.3.469
|
||||
Mapped on: 06/07/24 20:49:58
|
||||
Mapped on: 07/12/24 16:07:45
|
||||
|
||||
|
||||
<A name="mrp_ds"></A><B><U><big>Design Summary</big></U></B>
|
||||
Number of registers: 125 out of 877 (14%)
|
||||
PFU registers: 103 out of 640 (16%)
|
||||
Number of registers: 124 out of 877 (14%)
|
||||
PFU registers: 102 out of 640 (16%)
|
||||
PIO registers: 22 out of 237 (9%)
|
||||
Number of SLICEs: 148 out of 320 (46%)
|
||||
SLICEs as Logic/ROM: 148 out of 320 (46%)
|
||||
Number of SLICEs: 145 out of 320 (45%)
|
||||
SLICEs as Logic/ROM: 145 out of 320 (45%)
|
||||
SLICEs as RAM: 0 out of 240 (0%)
|
||||
SLICEs as Carry: 9 out of 320 (3%)
|
||||
Number of LUT4s: 296 out of 640 (46%)
|
||||
Number used as logic LUTs: 278
|
||||
Number of LUT4s: 289 out of 640 (45%)
|
||||
Number used as logic LUTs: 271
|
||||
Number used as distributed RAM: 0
|
||||
Number used as ripple logic: 18
|
||||
Number used as shift registers: 0
|
||||
@ -58,44 +59,45 @@ Mapped on: 06/07/24 20:49:58
|
||||
2. Number of logic LUT4s does not include count of distributed RAM and
|
||||
ripple logic.
|
||||
Number of clocks: 2
|
||||
Net C14M_c: 85 loads, 63 rising, 22 falling (Driver: PIO C14M )
|
||||
Net C14M_c: 84 loads, 62 rising, 22 falling (Driver: PIO C14M )
|
||||
Net PHI1_c: 3 loads, 0 rising, 3 falling (Driver: PIO PHI1 )
|
||||
Number of Clock Enables: 13
|
||||
Net N_117_i: 2 loads, 0 LSLICEs
|
||||
Net RWBank14: 11 loads, 11 LSLICEs
|
||||
Net N_347_i: 2 loads, 0 LSLICEs
|
||||
Net RWBank14: 10 loads, 10 LSLICEs
|
||||
Net ram2e_ufm/wb_adr_0_sqmuxa_1_i: 1 loads, 1 LSLICEs
|
||||
Net un9_VOE_0_a2_0_a2: 1 loads, 1 LSLICEs
|
||||
Net un6_DOEEN_0_a2_0_a2: 2 loads, 2 LSLICEs
|
||||
Net ram2e_ufm/un1_wb_adr_0_sqmuxa_2_i[0]: 8 loads, 8 LSLICEs
|
||||
Net ram2e_ufm/N_63: 1 loads, 1 LSLICEs
|
||||
|
||||
Net ram2e_ufm/un1_wb_cyc_stb_0_sqmuxa_1_i[0]: 1 loads, 1 LSLICEs
|
||||
Net ram2e_ufm/N_111: 1 loads, 1 LSLICEs
|
||||
Net ram2e_ufm/N_104: 4 loads, 4 LSLICEs
|
||||
Net ram2e_ufm/N_98: 1 loads, 1 LSLICEs
|
||||
Net un1_CKE48_0_i: 6 loads, 6 LSLICEs
|
||||
Net N_389_i: 2 loads, 0 LSLICEs
|
||||
Net ram2e_ufm/un1_wb_adr_0_sqmuxa_2_i_0[0]: 8 loads, 8 LSLICEs
|
||||
Net ram2e_ufm/un1_CmdBitbangMXO212_1_i[0]: 1 loads, 1 LSLICEs
|
||||
Net ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0[0]: 4 loads, 4 LSLICEs
|
||||
Net ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0[0]: 1 loads, 1 LSLICEs
|
||||
Net un9_VOE_0_a2: 1 loads, 1 LSLICEs
|
||||
Net un1_CKE48_i: 6 loads, 6 LSLICEs
|
||||
Net N_346_i: 2 loads, 0 LSLICEs
|
||||
Net Vout3: 8 loads, 0 LSLICEs
|
||||
Number of LSRs: 8
|
||||
Net N_148: 2 loads, 2 LSLICEs
|
||||
Net N_430_i: 2 loads, 0 LSLICEs
|
||||
Number of LSRs: 9
|
||||
Net un1_CS_0_sqmuxa_i: 2 loads, 2 LSLICEs
|
||||
Net ram2e_ufm.wb_rst13: 2 loads, 0 LSLICEs
|
||||
Net RC7: 2 loads, 2 LSLICEs
|
||||
Net S[2]: 2 loads, 2 LSLICEs
|
||||
Net S[1]: 1 loads, 1 LSLICEs
|
||||
Net ram2e_ufm/wb_rst: 1 loads, 0 LSLICEs
|
||||
Net ram2e_ufm/nRWE_0_i_o3_RNIP8E61: 1 loads, 1 LSLICEs
|
||||
Net N_530: 1 loads, 0 LSLICEs
|
||||
Net N_301_i: 1 loads, 1 LSLICEs
|
||||
Net ram2e_ufm/wb_rst6_i: 1 loads, 1 LSLICEs
|
||||
Net N_523_1: 1 loads, 0 LSLICEs
|
||||
Net N_727_0: 1 loads, 1 LSLICEs
|
||||
Net RATc_i: 1 loads, 1 LSLICEs
|
||||
Number of nets driven by tri-state buffers: 0
|
||||
Top 10 highest fanout non-clock nets:
|
||||
Net S[2]: 60 loads
|
||||
Net S[3]: 48 loads
|
||||
Net S[1]: 46 loads
|
||||
Net S[0]: 31 loads
|
||||
Net FS[11]: 24 loads
|
||||
Net FS[10]: 23 loads
|
||||
Net FS[12]: 23 loads
|
||||
Net FS[9]: 23 loads
|
||||
Net FS[13]: 21 loads
|
||||
Net FS[8]: 18 loads
|
||||
Net S[2]: 51 loads
|
||||
Net S[1]: 44 loads
|
||||
Net S[3]: 40 loads
|
||||
Net S[0]: 32 loads
|
||||
Net FS[8]: 29 loads
|
||||
Net FS[9]: 26 loads
|
||||
Net FS[10]: 25 loads
|
||||
Net FS[11]: 23 loads
|
||||
Net FS[13]: 20 loads
|
||||
Net ram2e_ufm.wb_rst13: 17 loads
|
||||
|
||||
|
||||
|
||||
@ -123,11 +125,14 @@ WARNING - map: IO buffer missing for top level port nWE80...logic will be
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<A name="mrp_ioa"></A><B><U><big>IO (PIO) Attributes</big></U></B>
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| IO Name | Direction | Levelmode | IO |
|
||||
|
||||
| | | IO_TYPE | Register |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[0] | BIDIR | LVCMOS33 | |
|
||||
@ -181,10 +186,10 @@ WARNING - map: IO buffer missing for top level port nWE80...logic will be
|
||||
| BA[1] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| BA[0] | OUTPUT | LVCMOS33 | OUT |
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRWEout | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
| nCASout | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRASout | OUTPUT | LVCMOS33 | OUT |
|
||||
@ -238,10 +243,10 @@ WARNING - map: IO buffer missing for top level port nWE80...logic will be
|
||||
| Din[4] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[3] | INPUT | LVCMOS33 | |
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[2] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
| Din[1] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[0] | INPUT | LVCMOS33 | |
|
||||
@ -296,10 +301,10 @@ Signal ram2e_ufm/ufmefb/TCINT undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIIRQO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPICSNEN undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
|
||||
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
|
||||
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
|
||||
@ -357,8 +362,6 @@ Block ram2e_ufm/ufmefb/GND was optimized away.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<A name="mrp_efb"></A><B><U><big>Embedded Functional Block Connection Summary</big></U></B>
|
||||
|
||||
Desired WISHBONE clock frequency: 14.4 MHz
|
||||
@ -410,7 +413,7 @@ Instance Name: ram2e_ufm/ufmefb/EFBInst_0
|
||||
-------------------------
|
||||
|
||||
Total CPU Time: 0 secs
|
||||
Total REAL Time: 0 secs
|
||||
Total REAL Time: 2 secs
|
||||
Peak Memory Usage: 59 MB
|
||||
|
||||
|
||||
@ -422,7 +425,6 @@ Instance Name: ram2e_ufm/ufmefb/EFBInst_0
|
||||
|
||||
|
||||
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
|
||||
@ -14,7 +14,7 @@ Performance Grade: 4
|
||||
PACKAGE: TQFP100
|
||||
Package Status: Final Version 1.39
|
||||
|
||||
Fri Jun 07 20:50:08 2024
|
||||
Fri Jul 12 16:08:09 2024
|
||||
|
||||
Pinout by Port Name:
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
@ -292,7 +292,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Fri Jun 07 20:50:12 2024
|
||||
Fri Jul 12 16:08:21 2024
|
||||
|
||||
|
||||
|
||||
|
||||
@ -12,11 +12,12 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Fri Jun 07 20:49:59 2024
|
||||
Fri Jul 12 16:07:51 2024
|
||||
|
||||
C:/lscc/diamond/3.11_x64/ispfpga\bin\nt64\par -f RAM2E_LCMXO2_640HC_impl1.p2t
|
||||
RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.dir
|
||||
RAM2E_LCMXO2_640HC_impl1.prf -gui
|
||||
RAM2E_LCMXO2_640HC_impl1.prf -gui -msgset
|
||||
//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC-NODHGR/promote.xml
|
||||
|
||||
|
||||
Preference file: RAM2E_LCMXO2_640HC_impl1.prf.
|
||||
@ -25,22 +26,22 @@ Preference file: RAM2E_LCMXO2_640HC_impl1.prf.
|
||||
Level/ Number Worst Timing Worst Timing Run NCD
|
||||
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
|
||||
---------- -------- ----- ------ ----------- ----------- ---- ------
|
||||
5_1 * 0 56.334 0 0.379 0 16 Completed
|
||||
5_1 * 0 55.130 0 0.379 0 44 Completed
|
||||
* : Design saved.
|
||||
|
||||
Total (real) run time for 1-seed: 16 secs
|
||||
Total (real) run time for 1-seed: 44 secs
|
||||
|
||||
par done!
|
||||
|
||||
Note: user must run 'Trace' for timing closure signoff.
|
||||
|
||||
Lattice Place and Route Report for Design "RAM2E_LCMXO2_640HC_impl1_map.ncd"
|
||||
Fri Jun 07 20:49:59 2024
|
||||
Fri Jul 12 16:07:51 2024
|
||||
|
||||
|
||||
<A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
|
||||
PAR: Place And Route Diamond (64-bit) 3.11.3.469.
|
||||
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2E_LCMXO2_640HC_impl1.prf
|
||||
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC-NODHGR/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2E_LCMXO2_640HC_impl1.prf
|
||||
Preference file: RAM2E_LCMXO2_640HC_impl1.prf.
|
||||
Placement level-cost: 5-1.
|
||||
Routing Iterations: 6
|
||||
@ -66,39 +67,39 @@ Ignore Preference Error(s): True
|
||||
70+4(JTAG)/79 94% bonded
|
||||
IOLOGIC 22/80 27% used
|
||||
|
||||
SLICE 148/320 46% used
|
||||
SLICE 145/320 45% used
|
||||
|
||||
EFB 1/1 100% used
|
||||
|
||||
|
||||
Number of Signals: 465
|
||||
Number of Connections: 1330
|
||||
Number of Signals: 447
|
||||
Number of Connections: 1292
|
||||
|
||||
Pin Constraint Summary:
|
||||
70 out of 70 pins locked (100% locked).
|
||||
|
||||
The following 1 signal is selected to use the primary clock routing resources:
|
||||
C14M_c (driver: C14M, clk load #: 85)
|
||||
C14M_c (driver: C14M, clk load #: 84)
|
||||
|
||||
WARNING - par: Signal "C14M_c" is selected to use Primary clock resources. However, its driver comp "C14M" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
|
||||
The following 1 signal is selected to use the secondary clock routing resources:
|
||||
RWBank14 (driver: ram2e_ufm/SLICE_82, clk load #: 0, sr load #: 0, ce load #: 11)
|
||||
RWBank14 (driver: ram2e_ufm/SLICE_89, clk load #: 0, sr load #: 0, ce load #: 10)
|
||||
|
||||
No signal is selected as Global Set/Reset.
|
||||
Starting Placer Phase 0.
|
||||
............
|
||||
Finished Placer Phase 0. REAL time: 2 secs
|
||||
Finished Placer Phase 0. REAL time: 6 secs
|
||||
|
||||
Starting Placer Phase 1.
|
||||
.....................
|
||||
Placer score = 71540.
|
||||
Finished Placer Phase 1. REAL time: 9 secs
|
||||
Placer score = 69147.
|
||||
Finished Placer Phase 1. REAL time: 17 secs
|
||||
|
||||
Starting Placer Phase 2.
|
||||
.
|
||||
Placer score = 70933
|
||||
Finished Placer Phase 2. REAL time: 9 secs
|
||||
Placer score = 69051
|
||||
Finished Placer Phase 2. REAL time: 18 secs
|
||||
|
||||
|
||||
|
||||
@ -111,8 +112,8 @@ Global Clock Resources:
|
||||
DCC : 0 out of 8 (0%)
|
||||
|
||||
Global Clocks:
|
||||
PRIMARY "C14M_c" from comp "C14M" on PIO site "62 (PR5D)", clk load = 85
|
||||
SECONDARY "RWBank14" from F0 on comp "ram2e_ufm/SLICE_82" on site "R2C9D", clk load = 0, ce load = 11, sr load = 0
|
||||
PRIMARY "C14M_c" from comp "C14M" on PIO site "62 (PR5D)", clk load = 84
|
||||
SECONDARY "RWBank14" from F0 on comp "ram2e_ufm/SLICE_89" on site "R6C8A", clk load = 0, ce load = 10, sr load = 0
|
||||
|
||||
PRIMARY : 1 out of 8 (12%)
|
||||
SECONDARY: 1 out of 8 (12%)
|
||||
@ -140,16 +141,16 @@ Total placer CPU time: 8 secs
|
||||
|
||||
Dumping design to file RAM2E_LCMXO2_640HC_impl1.dir/5_1.ncd.
|
||||
|
||||
0 connections routed; 1330 unrouted.
|
||||
0 connections routed; 1292 unrouted.
|
||||
Starting router resource preassignment
|
||||
WARNING - par: The driver of primary clock net C14M_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
|
||||
|
||||
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
|
||||
Signal=PHI1_c loads=5 clock_loads=3
|
||||
|
||||
Completed router resource preassignment. Real time: 14 secs
|
||||
Completed router resource preassignment. Real time: 31 secs
|
||||
|
||||
Start NBR router at 20:50:13 06/07/24
|
||||
Start NBR router at 16:08:22 07/12/24
|
||||
|
||||
*****************************************************************
|
||||
Info: NBR allows conflicts(one node used by more than one signal)
|
||||
@ -164,32 +165,38 @@ Note: NBR uses a different method to calculate timing slacks. The
|
||||
your design.
|
||||
*****************************************************************
|
||||
|
||||
Start NBR special constraint process at 20:50:13 06/07/24
|
||||
Start NBR special constraint process at 16:08:22 07/12/24
|
||||
|
||||
Start NBR section for initial routing at 20:50:13 06/07/24
|
||||
Start NBR section for initial routing at 16:08:22 07/12/24
|
||||
Level 4, iteration 1
|
||||
17(0.04%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 56.334ns/0.000ns; real time: 15 secs
|
||||
15(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 56.455ns/0.000ns; real time: 42 secs
|
||||
|
||||
Info: Initial congestion level at 75% usage is 0
|
||||
Info: Initial congestion area at 75% usage is 0 (0.00%)
|
||||
|
||||
Start NBR section for normal routing at 20:50:14 06/07/24
|
||||
Start NBR section for normal routing at 16:08:33 07/12/24
|
||||
Level 4, iteration 1
|
||||
7(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 56.334ns/0.000ns; real time: 15 secs
|
||||
6(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 56.455ns/0.000ns; real time: 42 secs
|
||||
Level 4, iteration 2
|
||||
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 55.130ns/0.000ns; real time: 42 secs
|
||||
Level 4, iteration 3
|
||||
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 55.130ns/0.000ns; real time: 42 secs
|
||||
Level 4, iteration 4
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 56.334ns/0.000ns; real time: 15 secs
|
||||
Estimated worst slack/total negative slack<setup>: 55.130ns/0.000ns; real time: 42 secs
|
||||
|
||||
Start NBR section for setup/hold timing optimization with effort level 3 at 20:50:14 06/07/24
|
||||
Start NBR section for setup/hold timing optimization with effort level 3 at 16:08:33 07/12/24
|
||||
|
||||
Start NBR section for re-routing at 20:50:14 06/07/24
|
||||
Start NBR section for re-routing at 16:08:34 07/12/24
|
||||
Level 4, iteration 1
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 56.334ns/0.000ns; real time: 15 secs
|
||||
Estimated worst slack/total negative slack<setup>: 55.130ns/0.000ns; real time: 43 secs
|
||||
|
||||
Start NBR section for post-routing at 20:50:14 06/07/24
|
||||
Start NBR section for post-routing at 16:08:34 07/12/24
|
||||
|
||||
End NBR router with 0 unrouted connection
|
||||
|
||||
@ -197,7 +204,7 @@ NBR Summary
|
||||
-----------
|
||||
Number of unrouted connections : 0 (0.00%)
|
||||
Number of connections with timing violations : 0 (0.00%)
|
||||
Estimated worst slack<setup> : 56.334ns
|
||||
Estimated worst slack<setup> : 55.130ns
|
||||
Timing score<setup> : 0
|
||||
-----------
|
||||
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
|
||||
@ -208,9 +215,9 @@ WARNING - par: The following clock signals will be routed by using generic routi
|
||||
Signal=PHI1_c loads=5 clock_loads=3
|
||||
|
||||
Total CPU time 13 secs
|
||||
Total REAL time: 16 secs
|
||||
Total REAL time: 44 secs
|
||||
Completely routed.
|
||||
End of route. 1330 routed (100.00%); 0 unrouted.
|
||||
End of route. 1292 routed (100.00%); 0 unrouted.
|
||||
|
||||
Hold time timing score: 0, hold timing errors: 0
|
||||
|
||||
@ -224,14 +231,14 @@ All signals are completely routed.
|
||||
|
||||
PAR_SUMMARY::Run status = Completed
|
||||
PAR_SUMMARY::Number of unrouted conns = 0
|
||||
PAR_SUMMARY::Worst slack<setup/<ns>> = 56.334
|
||||
PAR_SUMMARY::Worst slack<setup/<ns>> = 55.130
|
||||
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
|
||||
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.379
|
||||
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
|
||||
PAR_SUMMARY::Number of errors = 0
|
||||
|
||||
Total CPU time to completion: 13 secs
|
||||
Total REAL time to completion: 16 secs
|
||||
Total CPU time to completion: 14 secs
|
||||
Total REAL time to completion: 44 secs
|
||||
|
||||
par done!
|
||||
|
||||
|
||||
@ -13,7 +13,7 @@ Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
|
||||
# Written on Fri Jun 7 20:49:53 2024
|
||||
# Written on Fri Jul 12 16:07:14 2024
|
||||
|
||||
##### FILES SYNTAX CHECKED ##############################################
|
||||
Constraint File(s): "\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc"
|
||||
@ -33,7 +33,7 @@ Clock Summary
|
||||
Start Requested Requested Clock Clock Clock
|
||||
Level Clock Frequency Period Type Group Load
|
||||
-----------------------------------------------------------------------------------------------
|
||||
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 121
|
||||
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 120
|
||||
|
||||
0 - System 100.0 MHz 10.000 system system_clkgroup 0
|
||||
|
||||
@ -47,7 +47,7 @@ Clock Load Summary
|
||||
Clock Source Clock Pin Non-clock Pin Non-clock Pin
|
||||
Clock Load Pin Seq Example Seq Example Comb Example
|
||||
--------------------------------------------------------------------------------------------
|
||||
C14M 121 C14M(port) RAT.C - un1_C14M.I[0](inv)
|
||||
C14M 120 C14M(port) RAT.C - un1_C14M.I[0](inv)
|
||||
|
||||
System 0 - - - -
|
||||
|
||||
|
||||
@ -62,7 +62,7 @@
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Updated:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2024/06/07 20:50:21</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2024/07/12 16:08:40</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Location:</SPAN></TD>
|
||||
|
||||
@ -12,7 +12,7 @@
|
||||
#OS: Windows 8 6.2
|
||||
#Hostname: ZANEMACWIN11
|
||||
|
||||
# Fri Jun 7 20:49:50 2024
|
||||
# Fri Jul 12 16:07:05 2024
|
||||
|
||||
#Implementation: impl1
|
||||
|
||||
@ -61,6 +61,7 @@ Synopsys Verilog Compiler, Version comp2018q2p1, Build 461R, Built Apr 1 2019 0
|
||||
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC-NODHGR\REFB.v" (library work)
|
||||
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\DHGR-OFF.v" (library work)
|
||||
Verilog syntax check successful!
|
||||
File \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v changed - recompiling
|
||||
Selecting top level module RAM2E
|
||||
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
|
||||
Running optimization stage 1 on VHI .......
|
||||
@ -86,12 +87,12 @@ Running optimization stage 2 on EFB .......
|
||||
Running optimization stage 2 on VLO .......
|
||||
Running optimization stage 2 on VHI .......
|
||||
|
||||
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)
|
||||
At c_ver Exit (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
Process took 0h:00m:05s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Fri Jun 7 20:49:51 2024
|
||||
# Fri Jul 12 16:07:11 2024
|
||||
|
||||
###########################################################]
|
||||
|
||||
@ -111,13 +112,14 @@ Implementation : impl1
|
||||
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
File \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC-NODHGR\impl1\synwork\layer0.srs changed - recompiling
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Fri Jun 7 20:49:51 2024
|
||||
# Fri Jul 12 16:07:12 2024
|
||||
|
||||
###########################################################]
|
||||
|
||||
@ -127,12 +129,12 @@ For a summary of runtime and memory usage for all design units, please see file:
|
||||
|
||||
@END
|
||||
|
||||
At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
|
||||
At c_hdl Exit (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
Process took 0h:00m:06s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Fri Jun 7 20:49:51 2024
|
||||
# Fri Jul 12 16:07:12 2024
|
||||
|
||||
###########################################################]
|
||||
|
||||
@ -152,18 +154,17 @@ Database state : \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC-NODHGR\impl1\synwork
|
||||
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
File \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC-NODHGR\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_comp.srs changed - recompiling
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Fri Jun 7 20:49:52 2024
|
||||
# Fri Jul 12 16:07:14 2024
|
||||
|
||||
###########################################################]
|
||||
Premap Report
|
||||
|
||||
# Fri Jun 7 20:49:53 2024
|
||||
# Fri Jul 12 16:07:14 2024
|
||||
|
||||
|
||||
Copyright (C) 1994-2018 Synopsys, Inc.
|
||||
@ -208,7 +209,7 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h
|
||||
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":21:4:21:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
|
||||
@N: MH105 |UMR3 is only supported for HAPS-80.
|
||||
@N: MH105 |UMR3 is only supported for HAPS-80.
|
||||
@N: BN115 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":140:9:140:12|Removing instance dhgr (in view: work.RAM2E(verilog)) of type view:work.DHGR(verilog) because it does not drive other instances.
|
||||
@N: BN115 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":136:9:136:12|Removing instance dhgr (in view: work.RAM2E(verilog)) of type view:work.DHGR(verilog) because it does not drive other instances.
|
||||
syn_allowed_resources : blockrams=2 set on top level netlist RAM2E
|
||||
|
||||
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
|
||||
@ -221,7 +222,7 @@ Clock Summary
|
||||
Start Requested Requested Clock Clock Clock
|
||||
Level Clock Frequency Period Type Group Load
|
||||
-----------------------------------------------------------------------------------------------
|
||||
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 121
|
||||
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 120
|
||||
|
||||
0 - System 100.0 MHz 10.000 system system_clkgroup 0
|
||||
|
||||
@ -236,7 +237,7 @@ Clock Load Summary
|
||||
Clock Source Clock Pin Non-clock Pin Non-clock Pin
|
||||
Clock Load Pin Seq Example Seq Example Comb Example
|
||||
--------------------------------------------------------------------------------------------
|
||||
C14M 121 C14M(port) RAT.C - un1_C14M.I[0](inv)
|
||||
C14M 120 C14M(port) RAT.C - un1_C14M.I[0](inv)
|
||||
|
||||
System 0 - - - -
|
||||
|
||||
@ -256,14 +257,14 @@ Number of ICG latches not removed: 0
|
||||
|
||||
#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
|
||||
|
||||
2 non-gated/non-generated clock tree(s) driving 125 clock pin(s) of sequential element(s)
|
||||
2 non-gated/non-generated clock tree(s) driving 124 clock pin(s) of sequential element(s)
|
||||
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
|
||||
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
|
||||
|
||||
=========================== Non-Gated/Non-Generated Clocks ============================
|
||||
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
|
||||
---------------------------------------------------------------------------------------
|
||||
@KP:ckid0_0 C14M port 121 PHI1r
|
||||
@KP:ckid0_0 C14M port 120 PHI1r
|
||||
@KP:ckid0_1 PHI1 Unconstrained_port 4 RC[2:0]
|
||||
=======================================================================================
|
||||
|
||||
@ -273,27 +274,25 @@ Clock Tree ID Driving Element Drive Element Type Fanout Sample I
|
||||
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
|
||||
Finished Pre Mapping Phase.
|
||||
|
||||
Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
|
||||
Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
|
||||
|
||||
|
||||
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
|
||||
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
|
||||
|
||||
None
|
||||
None
|
||||
|
||||
Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
|
||||
Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
|
||||
|
||||
Pre-mapping successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB)
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Fri Jun 7 20:49:53 2024
|
||||
Process took 0h:00m:02s realtime, 0h:00m:01s cputime
|
||||
# Fri Jul 12 16:07:18 2024
|
||||
|
||||
###########################################################]
|
||||
Map & Optimize Report
|
||||
|
||||
# Fri Jun 7 20:49:53 2024
|
||||
# Fri Jul 12 16:07:21 2024
|
||||
|
||||
|
||||
Copyright (C) 1994-2018 Synopsys, Inc.
|
||||
@ -328,12 +327,12 @@ Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0
|
||||
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
|
||||
|
||||
|
||||
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
|
||||
Finished loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
|
||||
|
||||
@N: MF284 |Setting synthesis effort to medium for the design
|
||||
|
||||
|
||||
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
|
||||
Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
|
||||
|
||||
|
||||
Available hyper_sources - for debug and ip models
|
||||
@ -342,61 +341,61 @@ Available hyper_sources - for debug and ip models
|
||||
@N: FX493 |Applying initial value "00000000" on instance RWBank[7:0].
|
||||
@N: FX493 |Applying initial value "0000" on instance S[3:0].
|
||||
|
||||
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)
|
||||
Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)
|
||||
|
||||
@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":14:23:14:28|Found counter in view:work.RAM2E(verilog) instance FS[15:0]
|
||||
|
||||
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 142MB)
|
||||
Starting factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 142MB)
|
||||
|
||||
|
||||
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
|
||||
Finished factoring (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
|
||||
|
||||
|
||||
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
|
||||
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
|
||||
|
||||
|
||||
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
|
||||
Starting Early Timing Optimization (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
|
||||
|
||||
|
||||
Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
|
||||
Finished Early Timing Optimization (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
|
||||
|
||||
|
||||
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
|
||||
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
|
||||
|
||||
|
||||
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
|
||||
Finished preparing to map (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 147MB)
|
||||
|
||||
|
||||
Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
|
||||
Finished technology mapping (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
|
||||
|
||||
Pass CPU time Worst Slack Luts / Registers
|
||||
------------------------------------------------------------
|
||||
1 0h:00m:01s 6.90ns 281 / 125
|
||||
1 0h:00m:01s 6.90ns 280 / 124
|
||||
|
||||
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
|
||||
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
|
||||
|
||||
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
|
||||
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":171:4:171:9|Boundary register BA_1_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
||||
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":171:4:171:9|Boundary register BA_0_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
||||
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":168:4:168:9|Boundary register BA_1_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
||||
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":168:4:168:9|Boundary register BA_0_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
||||
|
||||
Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 158MB peak: 160MB)
|
||||
Finished restoring hierarchy (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:01s; Memory used current: 158MB peak: 160MB)
|
||||
|
||||
|
||||
Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 122MB peak: 160MB)
|
||||
Start Writing Netlists (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:01s; Memory used current: 122MB peak: 160MB)
|
||||
|
||||
Writing Analyst data base \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC-NODHGR\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_m.srm
|
||||
|
||||
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 158MB peak: 160MB)
|
||||
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:02s; Memory used current: 157MB peak: 160MB)
|
||||
|
||||
Writing EDIF Netlist and constraint files
|
||||
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC-NODHGR\impl1\RAM2E_LCMXO2_640HC_impl1.edi
|
||||
N-2018.03L-SP1-1
|
||||
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
|
||||
|
||||
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 162MB peak: 164MB)
|
||||
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:02s; Memory used current: 161MB peak: 163MB)
|
||||
|
||||
|
||||
Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 161MB peak: 164MB)
|
||||
Start final timing analysis (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:03s; Memory used current: 160MB peak: 163MB)
|
||||
|
||||
@W: MT246 :"\\mac\icloud\repos\ram2e\cpld\lcmxo2-640hc-nodhgr\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
|
||||
@N: MT615 |Found clock C14M with period 69.84ns
|
||||
@ -404,7 +403,7 @@ Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:0
|
||||
|
||||
|
||||
##### START OF TIMING REPORT #####[
|
||||
# Timing Report written on Fri Jun 7 20:49:57 2024
|
||||
# Timing Report written on Fri Jul 12 16:07:33 2024
|
||||
#
|
||||
|
||||
|
||||
@ -429,9 +428,9 @@ Worst slack in design: 6.897
|
||||
Requested Estimated Requested Estimated Clock Clock
|
||||
Starting Clock Frequency Frequency Period Period Slack Type Group
|
||||
----------------------------------------------------------------------------------------------------------------------
|
||||
C14M 14.3 MHz 112.1 MHz 69.841 8.918 31.599 declared default_clkgroup
|
||||
C14M 14.3 MHz 120.3 MHz 69.841 8.314 31.675 declared default_clkgroup
|
||||
RAM2E|PHI1 100.0 MHz 322.2 MHz 10.000 3.103 6.897 inferred Inferred_clkgroup_0
|
||||
System 100.0 MHz NA 10.000 NA 67.088 system system_clkgroup
|
||||
System 100.0 MHz NA 10.000 NA 66.719 system system_clkgroup
|
||||
======================================================================================================================
|
||||
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
|
||||
|
||||
@ -446,9 +445,9 @@ Clocks | rise to rise | fall to fall | rise
|
||||
----------------------------------------------------------------------------------------------------------------
|
||||
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
|
||||
----------------------------------------------------------------------------------------------------------------
|
||||
System C14M | 69.841 67.088 | No paths - | No paths - | No paths -
|
||||
System C14M | 69.841 66.719 | No paths - | No paths - | No paths -
|
||||
C14M System | 69.841 68.797 | No paths - | No paths - | No paths -
|
||||
C14M C14M | 69.841 60.923 | No paths - | 34.920 31.599 | No paths -
|
||||
C14M C14M | 69.841 61.527 | No paths - | 34.920 31.675 | No paths -
|
||||
RAM2E|PHI1 C14M | No paths - | No paths - | No paths - | Diff grp -
|
||||
RAM2E|PHI1 RAM2E|PHI1 | No paths - | 10.000 6.897 | No paths - | No paths -
|
||||
================================================================================================================
|
||||
@ -477,10 +476,10 @@ Starting Points with Worst Slack
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
---------------------------------------------------------------------------
|
||||
S[2] C14M FD1S3AX Q S[2] 1.366 31.599
|
||||
S[3] C14M FD1S3AX Q S[3] 1.345 31.619
|
||||
S[1] C14M FD1S3AX Q S[1] 1.344 31.800
|
||||
S[0] C14M FD1S3AX Q S[0] 1.305 31.838
|
||||
S[2] C14M FD1S3AX Q S[2] 1.353 31.675
|
||||
S[3] C14M FD1S3AX Q S[3] 1.337 31.691
|
||||
S[0] C14M FD1S3AX Q S[0] 1.319 32.182
|
||||
S[1] C14M FD1S3AX Q S[1] 1.344 32.656
|
||||
RA[0] C14M FD1P3AX Q RA[0] 1.108 33.707
|
||||
RA[3] C14M FD1P3AX Q RA[3] 1.108 33.707
|
||||
RA[1] C14M FD1P3AX Q RA[1] 1.044 33.771
|
||||
@ -493,21 +492,21 @@ RA[5] C14M FD1P3AX Q RA[5] 1.044 33.771
|
||||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
-----------------------------------------------------------------------------------
|
||||
VOE_i_0io C14M OFS1P3IX CD N_530 34.118 31.599
|
||||
VOE_i_0io C14M OFS1P3IX D VOE_ic_i 35.009 31.800
|
||||
Vout_0io[0] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[1] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[2] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[3] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[4] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[5] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[6] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[7] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
===================================================================================
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------------
|
||||
VOE_i_0io C14M OFS1P3IX CD N_523_1 34.118 31.675
|
||||
RAT C14M FD1S3IX CD RATc_i 34.118 32.147
|
||||
Vout_0io[0] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[1] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[2] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[3] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[4] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[5] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[6] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[7] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
==================================================================================
|
||||
|
||||
|
||||
|
||||
@ -521,9 +520,9 @@ Path information for path number 1:
|
||||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
= Required time: 34.118
|
||||
|
||||
- Propagation time: 2.519
|
||||
- Propagation time: 2.442
|
||||
- Clock delay at starting point: 0.000 (ideal)
|
||||
= Slack (non-critical) : 31.599
|
||||
= Slack (non-critical) : 31.675
|
||||
|
||||
Number of logic level(s): 1
|
||||
Starting point: S[2] / Q
|
||||
@ -531,16 +530,16 @@ Path information for path number 1:
|
||||
The start point is clocked by C14M [rising] on pin CK
|
||||
The end point is clocked by C14M [falling] on pin SCLK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
------------------------------------------------------------------------------------------------------------
|
||||
S[2] FD1S3AX Q Out 1.366 1.366 -
|
||||
S[2] Net - - - - 58
|
||||
ram2e_ufm.un1_wb_adr_0_sqmuxa_2_0_a2_0[0] ORCALUT4 A In 0.000 1.366 -
|
||||
ram2e_ufm.un1_wb_adr_0_sqmuxa_2_0_a2_0[0] ORCALUT4 Z Out 1.153 2.519 -
|
||||
N_530 Net - - - - 3
|
||||
VOE_i_0io OFS1P3IX CD In 0.000 2.519 -
|
||||
============================================================================================================
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
---------------------------------------------------------------------------------------
|
||||
S[2] FD1S3AX Q Out 1.353 1.353 -
|
||||
S[2] Net - - - - 50
|
||||
ram2e_ufm.VOE_2_0_a2 ORCALUT4 A In 0.000 1.353 -
|
||||
ram2e_ufm.VOE_2_0_a2 ORCALUT4 Z Out 1.089 2.442 -
|
||||
N_523_1 Net - - - - 2
|
||||
VOE_i_0io OFS1P3IX CD In 0.000 2.442 -
|
||||
=======================================================================================
|
||||
|
||||
|
||||
|
||||
@ -629,7 +628,7 @@ Starting Points with Worst Slack
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
---------------------------------------------------------------------------------------------------
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBACKO wb_ack 0.000 67.088
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBACKO wb_ack 0.000 66.719
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO0 wb_dato[0] 0.000 69.313
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000 69.313
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO2 wb_dato[2] 0.000 69.313
|
||||
@ -644,21 +643,21 @@ ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO7 wb_dato[7]
|
||||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------------------
|
||||
ram2e_ufm.RWMask[0] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[1] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[2] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[3] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[4] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[5] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[6] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[7] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.LEDEN System FD1P3AX SP N_98 69.369 67.736
|
||||
ram2e_ufm.wb_cyc_stb System FD1P3AX SP N_111 69.369 67.736
|
||||
========================================================================================
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
---------------------------------------------------------------------------------------------------------------
|
||||
ram2e_ufm.wb_cyc_stb System FD1P3AX SP un1_CmdBitbangMXO212_1_i[0] 69.369 66.719
|
||||
ram2e_ufm.LEDEN System FD1P3AX SP un1_LEDEN_0_sqmuxa_1_i_0[0] 69.369 67.736
|
||||
ram2e_ufm.RWMask[0] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[1] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[2] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[3] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[4] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[5] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[6] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[7] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
===============================================================================================================
|
||||
|
||||
|
||||
|
||||
@ -672,30 +671,33 @@ Path information for path number 1:
|
||||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
= Required time: 69.369
|
||||
|
||||
- Propagation time: 2.282
|
||||
- Propagation time: 2.650
|
||||
- Clock delay at starting point: 0.000 (ideal)
|
||||
- Estimated clock delay at start point: -0.000
|
||||
= Slack (non-critical) : 67.088
|
||||
= Slack (non-critical) : 66.719
|
||||
|
||||
Number of logic level(s): 2
|
||||
Number of logic level(s): 3
|
||||
Starting point: ram2e_ufm.ufmefb.EFBInst_0 / WBACKO
|
||||
Ending point: ram2e_ufm.RWMask[0] / SP
|
||||
Ending point: ram2e_ufm.wb_cyc_stb / SP
|
||||
The start point is clocked by System [rising]
|
||||
The end point is clocked by C14M [rising] on pin CK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
----------------------------------------------------------------------------------------------------------------
|
||||
ram2e_ufm.ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 -
|
||||
wb_ack Net - - - - 5
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] ORCALUT4 B In 0.000 0.000 -
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] ORCALUT4 Z Out 1.017 1.017 -
|
||||
un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] Net - - - - 1
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 D In 0.000 1.017 -
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 Z Out 1.265 2.282 -
|
||||
N_104 Net - - - - 8
|
||||
ram2e_ufm.RWMask[0] FD1P3AX SP In 0.000 2.282 -
|
||||
================================================================================================================
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
---------------------------------------------------------------------------------------------------------------
|
||||
ram2e_ufm.ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 -
|
||||
wb_ack Net - - - - 4
|
||||
ram2e_ufm.un1_CmdBitbangMXO212_1_0_0_tz[0] ORCALUT4 B In 0.000 0.000 -
|
||||
ram2e_ufm.un1_CmdBitbangMXO212_1_0_0_tz[0] ORCALUT4 Z Out 1.017 1.017 -
|
||||
un1_CmdBitbangMXO212_1_0_0_tz[0] Net - - - - 1
|
||||
ram2e_ufm.un1_CmdBitbangMXO212_1_0_0_0[0] ORCALUT4 C In 0.000 1.017 -
|
||||
ram2e_ufm.un1_CmdBitbangMXO212_1_0_0_0[0] ORCALUT4 Z Out 1.017 2.034 -
|
||||
un1_CmdBitbangMXO212_1_0_0_0[0] Net - - - - 1
|
||||
ram2e_ufm.wb_cyc_stb_RNO_0 ORCALUT4 A In 0.000 2.034 -
|
||||
ram2e_ufm.wb_cyc_stb_RNO_0 ORCALUT4 Z Out 0.617 2.650 -
|
||||
un1_CmdBitbangMXO212_1_i[0] Net - - - - 1
|
||||
ram2e_ufm.wb_cyc_stb FD1P3AX SP In 0.000 2.650 -
|
||||
===============================================================================================================
|
||||
|
||||
|
||||
|
||||
@ -704,16 +706,16 @@ ram2e_ufm.RWMask[0] FD1P3AX SP In
|
||||
Timing exceptions that could not be applied
|
||||
None
|
||||
|
||||
Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 161MB peak: 164MB)
|
||||
Finished final timing analysis (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 163MB)
|
||||
|
||||
|
||||
Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 161MB peak: 164MB)
|
||||
Finished timing report (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 163MB)
|
||||
|
||||
---------------------------------------
|
||||
Resource Usage Report
|
||||
Part: lcmxo2_640hc-4
|
||||
|
||||
Register bits: 125 of 640 (20%)
|
||||
Register bits: 124 of 640 (19%)
|
||||
PIC Latch: 0
|
||||
I/O cells: 70
|
||||
|
||||
@ -722,7 +724,7 @@ Details:
|
||||
BB: 8
|
||||
CCU2D: 9
|
||||
EFB: 1
|
||||
FD1P3AX: 58
|
||||
FD1P3AX: 57
|
||||
FD1P3IX: 1
|
||||
FD1S3AX: 31
|
||||
FD1S3AY: 4
|
||||
@ -735,16 +737,17 @@ OB: 41
|
||||
OFS1P3BX: 6
|
||||
OFS1P3DX: 12
|
||||
OFS1P3IX: 3
|
||||
ORCALUT4: 275
|
||||
ORCALUT4: 268
|
||||
PFUMX: 10
|
||||
PUR: 1
|
||||
VHI: 3
|
||||
VLO: 3
|
||||
Mapper successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 32MB peak: 164MB)
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:03s; Memory used current: 32MB peak: 163MB)
|
||||
|
||||
Process took 0h:00m:03s realtime, 0h:00m:03s cputime
|
||||
# Fri Jun 7 20:49:57 2024
|
||||
Process took 0h:00m:14s realtime, 0h:00m:03s cputime
|
||||
# Fri Jul 12 16:07:38 2024
|
||||
|
||||
###########################################################]
|
||||
|
||||
|
||||
@ -2,17 +2,19 @@
|
||||
Starting: parse design source files
|
||||
(VERI-1482) Analyzing Verilog file C:/lscc/diamond/3.11_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v
|
||||
(VERI-1482) Analyzing Verilog file //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v
|
||||
WARNING - //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v(140,9-140,25) (VERI-1362) CmdRWMaskSet is already implicitly declared on line 131
|
||||
WARNING - //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v(141,9-141,22) (VERI-1362) CmdLEDSet is already implicitly declared on line 131
|
||||
(VERI-1482) Analyzing Verilog file //Mac/iCloud/Repos/RAM2E/CPLD/UFM-LCMXO2.v
|
||||
(VERI-1482) Analyzing Verilog file //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC-NODHGR/REFB.v
|
||||
(VERI-1482) Analyzing Verilog file //Mac/iCloud/Repos/RAM2E/CPLD/DHGR-OFF.v
|
||||
INFO - //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v(1,8-1,13) (VERI-1018) compiling module RAM2E
|
||||
INFO - //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v(1,1-479,10) (VERI-9000) elaborating module 'RAM2E'
|
||||
INFO - //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v(1,1-476,10) (VERI-9000) elaborating module 'RAM2E'
|
||||
INFO - //Mac/iCloud/Repos/RAM2E/CPLD/UFM-LCMXO2.v(1,1-335,10) (VERI-9000) elaborating module 'RAM2E_UFM_uniq_1'
|
||||
INFO - //Mac/iCloud/Repos/RAM2E/CPLD/DHGR-OFF.v(1,1-1,68) (VERI-9000) elaborating module 'DHGR_uniq_1'
|
||||
INFO - //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC-NODHGR/REFB.v(8,1-113,10) (VERI-9000) elaborating module 'REFB_uniq_1'
|
||||
INFO - C:/lscc/diamond/3.11_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_1'
|
||||
INFO - C:/lscc/diamond/3.11_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_1'
|
||||
INFO - C:/lscc/diamond/3.11_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1800,1-1872,10) (VERI-9000) elaborating module 'EFB_uniq_1'
|
||||
Done: design load finished with (0) errors, and (0) warnings
|
||||
Done: design load finished with (0) errors, and (2) warnings
|
||||
|
||||
</PRE></BODY></HTML>
|
||||
@ -1,3 +1,3 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<userSetting name="//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC-NODHGR/promote.xml" version="Diamond (64-bit) 3.11.3.469" date="Sat Jun 08 04:44:53 2024" vendor="Lattice Semiconductor Corporation" >
|
||||
<userSetting name="//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC-NODHGR/promote.xml" version="Diamond (64-bit) 3.11.3.469" date="Fri Jul 12 16:10:17 2024" vendor="Lattice Semiconductor Corporation" >
|
||||
</userSetting>
|
||||
|
||||
70
CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC_tcl.html
Normal file
70
CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC_tcl.html
Normal file
@ -0,0 +1,70 @@
|
||||
<HTML>
|
||||
<HEAD><TITLE>Lattice TCL Log</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="pn240608044451"></A><B><U><big>pn240608044451</big></U></B>
|
||||
#Start recording tcl command: 6/7/2024 20:49:37
|
||||
#Project Location: //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC; Project name: RAM2E_LCMXO2_640HC
|
||||
prj_project open "//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC.ldf"
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
#Stop recording: 6/8/2024 04:44:51
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
@ -1,6 +1,6 @@
|
||||
NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
|
||||
NOTE All Rights Reserved *
|
||||
NOTE DATE CREATED: Fri Jun 07 20:50:29 2024 *
|
||||
NOTE DATE CREATED: Fri Jul 12 16:08:57 2024 *
|
||||
NOTE DESIGN NAME: RAM2E *
|
||||
NOTE DEVICE NAME: LCMXO2-640HC-4TQFP100 *
|
||||
NOTE PIN ASSIGNMENTS *
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
----------------------------------------------------------------------
|
||||
Report for cell RAM2E.verilog
|
||||
|
||||
Register bits: 125 of 640 (20%)
|
||||
Register bits: 124 of 640 (19%)
|
||||
PIC Latch: 0
|
||||
I/O cells: 70
|
||||
Cell usage:
|
||||
@ -9,7 +9,7 @@ I/O cells: 70
|
||||
BB 8 100.0
|
||||
CCU2D 9 100.0
|
||||
EFB 1 100.0
|
||||
FD1P3AX 58 100.0
|
||||
FD1P3AX 57 100.0
|
||||
FD1P3IX 1 100.0
|
||||
FD1S3AX 31 100.0
|
||||
FD1S3AY 4 100.0
|
||||
@ -22,7 +22,8 @@ I/O cells: 70
|
||||
OFS1P3BX 6 100.0
|
||||
OFS1P3DX 12 100.0
|
||||
OFS1P3IX 3 100.0
|
||||
ORCALUT4 275 100.0
|
||||
ORCALUT4 268 100.0
|
||||
PFUMX 10 100.0
|
||||
PUR 1 100.0
|
||||
VHI 3 100.0
|
||||
VLO 3 100.0
|
||||
@ -30,23 +31,24 @@ SUB MODULES
|
||||
RAM2E_UFM 1 100.0
|
||||
REFB 1 100.0
|
||||
|
||||
TOTAL 494
|
||||
TOTAL 496
|
||||
----------------------------------------------------------------------
|
||||
Report for cell RAM2E_UFM.netlist
|
||||
Instance path: ram2e_ufm
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
EFB 1 100.0
|
||||
FD1P3AX 29 50.0
|
||||
FD1P3AX 29 50.9
|
||||
FD1P3IX 1 100.0
|
||||
FD1S3IX 1 11.1
|
||||
ORCALUT4 268 97.5
|
||||
ORCALUT4 260 97.0
|
||||
PFUMX 10 100.0
|
||||
VHI 2 66.7
|
||||
VLO 2 66.7
|
||||
SUB MODULES
|
||||
REFB 1 100.0
|
||||
|
||||
TOTAL 305
|
||||
TOTAL 307
|
||||
----------------------------------------------------------------------
|
||||
Report for cell REFB.netlist
|
||||
Instance path: ram2e_ufm.ufmefb
|
||||
|
||||
@ -4,10 +4,10 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Fri Jun 07 20:50:26 2024
|
||||
Fri Jul 12 16:08:51 2024
|
||||
|
||||
|
||||
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC -w -jedec -gui RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf
|
||||
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC -w -jedec -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf
|
||||
|
||||
Loading design for application Bitgen from file RAM2E_LCMXO2_640HC_impl1.ncd.
|
||||
Design name: RAM2E
|
||||
@ -82,5 +82,5 @@ Available General Purpose Flash Memory: 191 Pages (Page 0 to Page 190).
|
||||
Initialized UFM Pages: 1 Page (Page 190).
|
||||
|
||||
Total CPU Time: 3 secs
|
||||
Total REAL Time: 3 secs
|
||||
Total REAL Time: 6 secs
|
||||
Peak Memory Usage: 267 MB
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -2,7 +2,7 @@
|
||||
NOTE Diamond (64-bit) 3.11.3.469 JEDEC Compatible Fuse File.*
|
||||
NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation.*
|
||||
NOTE All Rights Reserved.*
|
||||
NOTE DATE CREATED: Fri Jun 07 20:50:26 2024*
|
||||
NOTE DATE CREATED: Fri Jul 12 16:08:52 2024*
|
||||
NOTE DESIGN NAME: RAM2E_LCMXO2_640HC_impl1.ncd*
|
||||
NOTE DEVICE NAME: LCMXO2-640HC-4TQFP100*
|
||||
NOTE JEDEC FILE STATUS: Final Version 1.95*
|
||||
@ -82,424 +82,424 @@ QF171904*
|
||||
G0*
|
||||
F0*
|
||||
L000000
|
||||
11111111111111111011110110110011111111111111111100111011000000000000000000000000000000100000000000000000000000001001000000110000
|
||||
00010001010100000000010100000110010010001111111101000110000000000000000000000000101110001110000000000000110101110000000000000000
|
||||
11111111111111111011110110110011111111111111111100111011000000000000000000000000000000100000000000000000000000001001000000010001
|
||||
00000011001100000000010101010000010010001111111101000110000000000000000000000000101110001110000000000000110101110000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000010001000000000000000000000000100010000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000010010000000000000000000000000100100000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000010001100000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000100010000000000000000100111000001000100000000000000000000000000000000000000000000000000000000000000000000
|
||||
10000000000001000010010000100000100001000000000000100100000001001000011000101011001111001100000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000100011000001001011001010000001001110000000010011110010100001001110100100000001000000000010000
|
||||
10000001001000000000000000000000000000000000000000000000000000000000000000001001110000010010000000000010011100000100000000000010
|
||||
01100001001100100001000100110000010010000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000
|
||||
00000010001000100110000000000000000000100001110100000100001000001000001011000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000100100100100000000000000000000000000000000000000001110000010000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000010000110010110011000000000100111000000100111010001100000100001000100100011000000110001001010001000101001
|
||||
01000000000000000000000000000000000000000000000000000000000000000000000000000000000100011000000000000000100111001001010000010001
|
||||
10000100000000010100100000000000000000000000000000000000000000000000000000000000000000000000000000001001110000000100110000000000
|
||||
10011100000000000011010011000001001100000000000000000000000000000000000000000000000000000000000000000000000000000001010100000000
|
||||
01000101001110100001101001000000000001001001001011001010101010000010000010101100000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000010000100100011000101111000000000000101101000001000010000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000001010010001001110000100000000000100110000010000100000010011010001010010000000001001101001
|
||||
00000000000000000000000000000000000000000000000000000000000000000000100010000000000000000100111010011000000000000000000000000000
|
||||
10011000010001001000000000000000000000000000000000000000000000000000000000000000000000000000000000010001000000000000100010111100
|
||||
10000000000000000011000110010100011000001000100000000000000000000000000000000000000000000000000000001001110100101000000100111001
|
||||
00000000000000000010001100000000110000001100000000000010010000000010000001001000010000000000000000000000000000000000000000000000
|
||||
00000000000100010001001000010101100000000101100001010110000000000000010110000000000000000010010100010011000100010000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100101000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000001001101001100000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000100001100110000000010111000000000000000000000000010001100000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000010000100000000000101001110011100010010000000
|
||||
00000000000000000000000000000000000000000000000000000000000000100001100001000001000000000000000000000001001010000000000000100100
|
||||
01001010100011000000000000000000000000000000000000000000000000000000000000000000000000010011110011100001110000100000001000010000
|
||||
00000000000000000001001010000100100101001101001000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000001001100000100011010000110000110011001000010000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000010101010011100000100000000000000000100100000001000110000000111000010000100000100101000000000000000000000000000000000
|
||||
00000000000000000000000000000000101110000001001010000010000100001100001101110011100000000100010000100010100010100101000000000100
|
||||
01001001010000000000000000001010011001010000000000000000000000000000000000000000000000000000001000110100100001000011110000010110
|
||||
10010010000000000110011001010011000001100110110100110110010000100011001000101101000001001000110000000010000010010000000000000000
|
||||
00000100100000000010011000000000000000000000000000000000000000000000100110100111000001000110110010100000001001110010010010011010
|
||||
01110000100110100111010011001011101001100100110000000001001011101000100000000000000000000010011010001100000000000000000000000000
|
||||
00000000000000000000001100100001101010000000000000000010110110000000001011010001001000100000100010101111100100100101000000010000
|
||||
00000000000000000000010010010011000000000000000000000000000000000000000000001000100000001000100000101110010010100000000011001000
|
||||
01000001100100001100010000100010000010010000000100010000001001000000000000000000000000000110011110000000000000000000000000000000
|
||||
00000100000000000100000001000111000100001000011110000010100110100110100001100111001010110000100100010010101110001000011001000101
|
||||
10100010100001100010010100110001011000110100001010011000001000011001100000000000000000000000000001100111100000000000000000000000
|
||||
00000000000000000000100000110010100000100110100111000000000010000110010101100101000001001100010011001100010100100110010011011001
|
||||
01000001010010010001101001101001100100111000000000000000000000000011000011110000000001000101001110000000000000000000000000000000
|
||||
00000100001001100100001010111101000110001001000000100000100010000101101100010111011010000010110110000101001000011000101011000000
|
||||
01001100101011010000100010001000000000000000000000000000000000000000000000000000000000000000000000000001000001100110010001100010
|
||||
01010010001101001010110101110011110010001011110100000000100001100001010001110001010011111000100101000101010111000011100001100010
|
||||
01001010111100100100100111100111100110100101000000001101010010000000000000000000000000000110011110010010010000100000000000000000
|
||||
00000000000000000000000000000001001010001100001011001111000000011100100110100001100000111110101010011011100001000100000101110100
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01101010010000000000000000000000000000000010011100101001000100000010011100110001010011100100101100011000110010010001001111000011
|
||||
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|
||||
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|
||||
10001010010000110011010011110101011010000011000101001001101000011100110001001101001010010010001011101000001110001011010010010000
|
||||
01100100100110010000101001000011001001001100001001010011110011001000001101000001000000000000000100101100010011100001001100000110
|
||||
00000000000000000000000000000000000000000000000000110110011010100000000111111000000101000100001110011111111001000100110101111110
|
||||
10000111110111011110100000101000110111111101001101010000111111001110100001000001010000110111011111111100000010100001111111110101
|
||||
00001010000011110111011111110000001011000000000000000000000100110000000000000000000000000000000000000000000000000100100111110111
|
||||
01100110011000100100110010001010111111000011001111111110111010000010010011000110011100101111100011110100110011111111011001001111
|
||||
10111010100010001111011111111010001001001100001001111111110110001111001100111111111110001101111111100011110111011111000011111011
|
||||
00111000100011110111011001011010001110111011100100111011111100101000111100110000110011100110001100000000000000000000000000000000
|
||||
00000000000000000000000000000000001110101010110011001110001100010100011110100001000100010010001011110101000101000010100011111100
|
||||
00100010011001100110110010010011100010001000101010000100100111111010011101110111000101111111110101000100101111110111110110110001
|
||||
11010001110101010011111100010011110111011110101010001001000000000000000000000000011110000000000000000000000000000000000000000000
|
||||
00011011001101010001010100001110011001111101110101100000111100111100001100000111001100001110111111110111111101111111000111101000
|
||||
00110011001111100010000111001010011100010000111111111010011110000111111100001110011001011111111100011110011101111111100100110111
|
||||
11011011111001100010100000101000111100111100000000000000000000000000000000000000000000000000000000000000000000000000000000101101
|
||||
10010001110000100001000000010011100101101100100010011100100001001001110010110110110010001010011000100000001001110010000000100111
|
||||
00000000000000000000101101111100000000000100110010000101000010000000000000000000000000000000000000000000100100000000100011000100
|
||||
10100000000000011001100010000000000000000100001000000000000000110010010001001110000000000100111001100001010100110000000000000000
|
||||
00000100011000000000000000000000000000001001100100001110100100100000000001000011001100110001001000100001100110000000000000000000
|
||||
00000000001000011101000010000000001101110000010011011010001000000000000000000000000000000000000000110010100000001001001001100000
|
||||
00000010001110011000010011010001010011100010011001100100100000100110000000000000000000000000000001001100010000010011100000100111
|
||||
10000010000000000000000000000000010010100000000000000000000010011000000000000010010000100000000001000000001001110100000000000000
|
||||
00001000000000000000000001100100101110000101000010011000001001011000010000000000000000000000000000000000000000110001100000000100
|
||||
10100001001011000110001011111100111000000101011000000100000000001000010000000000000000000000000001100100100000000110011110000100
|
||||
01100000000000000000000100011000000100011000000000010001110011001000011001101001110001000011001100010011000000001000011001100000
|
||||
10000110011010000101001110100001100110010011000000010011000001001100000000000000010000110011000011000011110000000110011110010011
|
||||
10100110100110000000000000000000010010100000000000000000010010100010001110011010100100000000100110011001000011001100001001001001
|
||||
10000100110100010000010011010000010010010001100000100100000010010000000000000000010011000011010011110000010000110011110000010000
|
||||
00000000000000000000000000001001010000000000100110000001001001000110000100011001000001000111001101000011001000001001011001000010
|
||||
00000011100001000010000000010011000000000000000010110100000000011001001010000110111000000100001000000000000001000000000000000000
|
||||
00000100111000000000010001010001000001110110000001001100100011010001010000110100110111100010000100000010101100000000000000000000
|
||||
00000000000000000000000001100111100110001100000000100000000000000000000000000000010001000000000001000011000001100100010111000001
|
||||
01010010100011001001110100000111000100001101100000100011000010011010001100000010001000000100010100000000000000001001100000000000
|
||||
01000001000010000110000011011000011110000110011110010011101000011001110000000000000000000000000000000000000001000100100011110100
|
||||
01001001110010110001000100001001111000110110100001000010001110000100000000000000000000000000000000000000000000110100111100000000
|
||||
00000000100010000000000000000000000000000000110010000111000001101001010001000001000011000110001000001001101100010011100101000100
|
||||
01100000001001110000010011100000000000100011000000000000100010000000000001100111100000000000000000000000000000000000000000000010
|
||||
00011001111001011000011001100011000100100010010001001110011011000001001100001000111001111101000001000000000000000000000000000000
|
||||
00000000000001100001111000110011100000000100111000000000000000000010001100000000000000001001010110000011010111110001100100000110
|
||||
01001101001100000110010010110000011000111000001101000001010010000000000000000000000000000000000000000000011000001110000000100101
|
||||
10011100000000000000000000000000000000000000000100100010010110011000010010100100111000110000100111000110001001100100000100110110
|
||||
01000101110000100100001001010010001001110100010100111001010010000000000000000000000000000010000000000000000100100000100010000000
|
||||
00000000000000100110000000000000000000101011101011111010000000101100110010100110011000100101010010110000001111010000100001100011
|
||||
10001110000110110100101011001000010000010110100000000000000000000000000000000000001111101000010010000000000000000000000000000000
|
||||
00000010010000010000100000010010011000101001000101000011000000010001011000010101000011010100001000001110000100010010000100010010
|
||||
01110100000010001001001110000000000000000000000000010010010011100111000010011110000000000000100101000000000000000000000000000000
|
||||
00000100101000000111001011011100100101010010001000011001101000100010000000010000110010101110101000101110101010011101000000100110
|
||||
01000110001001100110000110000000000000100001100111000000000001001100110010010000000000000000000011001010000100001100111000000000
|
||||
00000000000000000000000000100101110100000110011100111010000110010101000010010001110010110011110011100100010100000100101111000010
|
||||
00001000110100110100111100010010001101001101010010000000000000000000000010010000000000000100000000000000000101100000000000000000
|
||||
00000000000000010011010001010101110001010010100001100001110010011101001011100101010110011101010010110000010011001100101000100000
|
||||
10010011110000001000111110000101100100011001000100001001000100101100111000000000000000000000000000010001000000000011110000000000
|
||||
11010000010000001001000000000000000101001000000000001000100001000111001011001011010011000011001101000011011001010110000010010111
|
||||
00111010100001100111010011101011001011100000100010010011101000001010011000100100111000000001000000000000000000000001011000010000
|
||||
01111000000000000010011101000111100011000010000100000000000000000000000010011100000001000111001110011110000110010000111100011001
|
||||
00011000110010011011010000100100101001001110100011000100010010001110000010010101001100110000110010000000100110000000000000000000
|
||||
00000000000100010010011001001100000010000111100001000110001100000000010010100000000000000000000000001001100010000100010011010011
|
||||
00100000010011100010010001000101000100100111000100011010011001101010100100011100011010011001100010100100010111000100001000101111
|
||||
00100000000001000010000000000000010001000100110001100011000000000010010001001101001100100111000000000000000000000001000100000000
|
||||
01101001100100111000100110100011101011100000111010000001001101000101110101001101010100001100111010001110000011011100001000110100
|
||||
11000110000101010000110011110000111001001011001000100101100111001001000100101000000000000000000000001000000010010010001001001111
|
||||
10000011000000000000000000000000000000000000000000000000000001010001111111011011111111001111101111011100010001111111010010100011
|
||||
11011101010100011111101110110000110111110011000111000001110101101101100110111111111011000010011110111111111111110111100100101101
|
||||
11111111111111101101001001111011111111111111011110010010110111111111111111101010010000000000000000000000000000001001100000000000
|
||||
00000000000000000000000000000000000001111111110101000100100111001100010100010001101111111010100100111001100111110111011000111111
|
||||
11101101001001100001111110100010010001111100010001011011001000110011111011000011011110111100110011110111101100001101111100110011
|
||||
11101100001101111011110011001111011110110000110111110011001111101000110000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000010001111110111110110110111011011111111000101100001100111111110001110011001111111100101010001100110011100100
|
||||
11011001101010000110101010111111101010101000110111111111000011011110111100110011110111101100001101111100110011111011000011011110
|
||||
11110011001111011110110000110111110011001111111000110000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000110000101111010111110110000110011011011110110000110011111111000101000111111100101100110011110011011101111111110111011111101
|
||||
00110110101111101111011111111111110011010000011110111111111111110111100000101101111111111111111011010000011110111111111111110111
|
||||
10000010110111111110100000000000000000000000000000000000000000000000000000000000000000000000000000001011011001000100111001011011
|
||||
00100010011100100000010001111110001000010110110010001001110100000111101001110010010001111110001001101101000100000111101001110010
|
||||
01000111111000100110110100010000011110100000000000000000000000000000000010110111110000000000010000000000000000000000000000000000
|
||||
00000001000001010011010010000000001001001010011001010000000000000000000010000000000000100111000000000000000000000000000000100110
|
||||
01000011001100000000000000000000000010000100000000000010000100000000000001001000000000000000000000000100110100101000000000010010
|
||||
11001100000000000000000000000000001101100000001101000100000000000000000000000000000000000000000000000000100010000000000000000000
|
||||
00000010111110010000001000010000010101010010000000000000000000010011100000101111010000000000000000000000000000010000100000000000
|
||||
00000000000001101000001000000000000000000000010001110000100000000000010010000000000000000000000000000000000000000000000000001100
|
||||
10010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100111100001000011001100000000
|
||||
00000000000000010000110011000000000000000000000000000000000000000000000000000000000000100010000000000000000000000110000111100000
|
||||
01100111100100111001001100000000000000000000000010011000000000000010010000000000000000000000000000000000000000000000000000000000
|
||||
00000000000011000011110001011011001110100000000000000000000000000001100100101000000000000100010111010000000000000000000000000000
|
||||
00000000000000000000000100000000000000000000000000000000010000100000000000000000000000000000000000000010001101001100000000100100
|
||||
10001110011001001110000000000000000000100100000000000000000000000000000000000000011001111001100011000000001000000000000000000000
|
||||
00100001000010000000000000100101010010000000001000010100011010010100000000000000000001001111100101000000000000000000000000000000
|
||||
00000010000111000011110001100111100101111000000000000000000000000000000000000000000000000010010111010001000101010000000000000000
|
||||
00000000000000000000000000000000000100110000011000011110000000000000000000000000000100001000000000000011001001000101111000000011
|
||||
10000010000010110000000000000000000000000000000000000000000000000001001000000000011001111000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000010011100000000000000000100111010011101000100110000111100001100111000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000100010000000000000010010100000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000001001000000001000011001110011001010000000001001001010
|
||||
10001010110000000010011100000000000000000000000000000000000000000000000001011000000000000000000000000000000000000000000000000000
|
||||
00000000000000000011110010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
01001010100010000100110100110000001001000000000000000000000000000000000000000000000000000000000000100010000100001100110000000100
|
||||
01000000000000000000000000000000010111100000000000000000000000000000000000000000000000000000000000010101100000000010000000000000
|
||||
00010000000000000000000000000000000000100001000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000100111001000110000000001111100000001000110100110000000000000000000000110010100000000000000001
|
||||
00110000000010000001000110101010000000000000000000000100011011010110000000000001000110100110000000000000000001001100000000100111
|
||||
00000000000000000000000000001001110000000001101100100011000110000000000000001000110000000000000000000000000000000010010100000000
|
||||
00000000010001101001010000100101000010001100000000000000000000000100100000000010001000000000000100010010011000000000000000000000
|
||||
00000000000000000100100000000000000000100100010111100000001100011000001100111000011101000000000000000000000000001100010100000000
|
||||
00001001111000100100111000000000110100010001110100000100110000000000000000000001001000100111000000000001010100000000000000001010
|
||||
01001000010000000010111100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000100001000000000000000000000001000010000000000000000000000000000000000000000000
|
||||
00010000100000000000000000000000100001000000000000000000000001100110010000000000000000000000001100110010000000000000000000000001
|
||||
00001000000000000011111100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000010000001001111100001001100101000000000001001011000010000000000100101100001000000000000
|
||||
00000000001001011000010000000000100101100001000000000000000000000000000000000000000000000001000111101100000000000000100000010011
|
||||
00000000001000000100110000000000000000000000001001100000000000010011000000000000000000000000000000000000000000000000000000010111
|
||||
01110000010100000000000000010011110000100000000001001111000010000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000010000001001110000000000100001000100101000000010000100010010100000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000001011101101000001100110000000011000001101100011000100000111111100111111000000000000110000011
|
||||
01100011000100000111111100111111000000000000000000000000100010100100110001100111101000011110100000000000010001010010011000110011
|
||||
11010000111101000000000000000000000000000000000000000000000000000000011000110011111100001111110000000000001100000110110001100010
|
||||
00001111111001111110000000000001100000110110001100010000011111110011111100000000000000000000000000110001100111111000011111100000
|
||||
00000000011000110011111100001111110000000000000000000000000000000000000000000100111000000000000000001001110000000000000000000000
|
||||
00011000001101100011000110001100111100000011001110000000000000110000011011000110001100011001111000000110011100000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000001000011000111000111001111001110110000011011000110001100011001111000
|
||||
00011001110110000011011000110001100011001111000000110011100000000000001100000110110001100011000110011110000001100111000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000010001100000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000100000100011000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000100001100011000000000000000000000000000000001001010000000000000001110001
|
||||
01000000111010011010011011111111111111111111111111111111111111111111111111111111111111111100001010000000000000000000000000000000
|
||||
01000000010010110000000111111111111111111111111111111111111111111111111111111111111111111100001010000000000000000000000000000000
|
||||
00000000000000000000000000101010101001110010001000000000000000000000000001000000000000000000000000000000111111111111111111111111
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111101011110000000000000000000000000
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
*
|
||||
NOTE END CONFIG DATA*
|
||||
L53120
|
||||
L52352
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
@ -1432,10 +1432,10 @@ L171648
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
*
|
||||
CAE1F*
|
||||
C863D*
|
||||
NOTE FEATURE_ROW*
|
||||
E0000000000000000000000000000000000000000000000000000000000000000
|
||||
0000010001100000*
|
||||
NOTE User Electronic Signature Data*
|
||||
UH00000000*
|
||||
571D
|
||||
557C
|
||||
|
||||
@ -9,25 +9,26 @@ Command line: map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial
|
||||
RAM2E_LCMXO2_640HC_impl1.ngd -o RAM2E_LCMXO2_640HC_impl1_map.ncd -pr
|
||||
RAM2E_LCMXO2_640HC_impl1.prf -mp RAM2E_LCMXO2_640HC_impl1.mrp -lpf //Mac/iC
|
||||
loud/Repos/RAM2E/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_synplify.
|
||||
lpf -lpf //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf -c 0 -gui
|
||||
lpf -lpf //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf -c 0 -gui -msgset
|
||||
//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml
|
||||
Target Vendor: LATTICE
|
||||
Target Device: LCMXO2-640HCTQFP100
|
||||
Target Performance: 4
|
||||
Mapper: xo2c00, version: Diamond (64-bit) 3.11.3.469
|
||||
Mapped on: 06/07/24 20:50:09
|
||||
Mapped on: 07/12/24 16:08:05
|
||||
|
||||
Design Summary
|
||||
--------------
|
||||
|
||||
Number of registers: 125 out of 877 (14%)
|
||||
PFU registers: 103 out of 640 (16%)
|
||||
Number of registers: 124 out of 877 (14%)
|
||||
PFU registers: 102 out of 640 (16%)
|
||||
PIO registers: 22 out of 237 (9%)
|
||||
Number of SLICEs: 148 out of 320 (46%)
|
||||
SLICEs as Logic/ROM: 148 out of 320 (46%)
|
||||
Number of SLICEs: 145 out of 320 (45%)
|
||||
SLICEs as Logic/ROM: 145 out of 320 (45%)
|
||||
SLICEs as RAM: 0 out of 240 (0%)
|
||||
SLICEs as Carry: 9 out of 320 (3%)
|
||||
Number of LUT4s: 295 out of 640 (46%)
|
||||
Number used as logic LUTs: 277
|
||||
Number of LUT4s: 288 out of 640 (45%)
|
||||
Number used as logic LUTs: 270
|
||||
Number used as distributed RAM: 0
|
||||
Number used as ripple logic: 18
|
||||
Number used as shift registers: 0
|
||||
@ -51,53 +52,54 @@ Design Summary
|
||||
2. Number of logic LUT4s does not include count of distributed RAM and
|
||||
ripple logic.
|
||||
Number of clocks: 2
|
||||
Net C14M_c: 85 loads, 63 rising, 22 falling (Driver: PIO C14M )
|
||||
Net C14M_c: 84 loads, 62 rising, 22 falling (Driver: PIO C14M )
|
||||
Net PHI1_c: 3 loads, 0 rising, 3 falling (Driver: PIO PHI1 )
|
||||
Number of Clock Enables: 13
|
||||
Net N_117_i: 2 loads, 0 LSLICEs
|
||||
Net RWBank14: 11 loads, 11 LSLICEs
|
||||
Net N_347_i: 2 loads, 0 LSLICEs
|
||||
Net RWBank14: 10 loads, 10 LSLICEs
|
||||
Net ram2e_ufm/wb_adr_0_sqmuxa_1_i: 1 loads, 1 LSLICEs
|
||||
Net un9_VOE_0_a2_0_a2: 1 loads, 1 LSLICEs
|
||||
Net un6_DOEEN_0_a2_0_a2: 2 loads, 2 LSLICEs
|
||||
Net ram2e_ufm/un1_wb_adr_0_sqmuxa_2_i[0]: 8 loads, 8 LSLICEs
|
||||
Net ram2e_ufm/N_63: 1 loads, 1 LSLICEs
|
||||
|
||||
Page 1
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 06/07/24 20:50:09
|
||||
Design: RAM2E Date: 07/12/24 16:08:05
|
||||
|
||||
Design Summary (cont)
|
||||
---------------------
|
||||
Net ram2e_ufm/un1_wb_cyc_stb_0_sqmuxa_1_i[0]: 1 loads, 1 LSLICEs
|
||||
Net ram2e_ufm/N_111: 1 loads, 1 LSLICEs
|
||||
Net ram2e_ufm/N_104: 4 loads, 4 LSLICEs
|
||||
Net ram2e_ufm/N_98: 1 loads, 1 LSLICEs
|
||||
Net un1_CKE48_0_i: 6 loads, 6 LSLICEs
|
||||
Net N_389_i: 2 loads, 0 LSLICEs
|
||||
Net ram2e_ufm/un1_wb_adr_0_sqmuxa_2_i_0[0]: 8 loads, 8 LSLICEs
|
||||
Net ram2e_ufm/un1_CmdBitbangMXO212_1_i[0]: 1 loads, 1 LSLICEs
|
||||
Net ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0[0]: 4 loads, 4 LSLICEs
|
||||
Net ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0[0]: 1 loads, 1 LSLICEs
|
||||
Net un9_VOE_0_a2: 1 loads, 1 LSLICEs
|
||||
Net un1_CKE48_i: 6 loads, 6 LSLICEs
|
||||
Net N_346_i: 2 loads, 0 LSLICEs
|
||||
Net Vout3: 8 loads, 0 LSLICEs
|
||||
Number of LSRs: 8
|
||||
Net N_148: 2 loads, 2 LSLICEs
|
||||
Net N_430_i: 2 loads, 0 LSLICEs
|
||||
Number of LSRs: 9
|
||||
Net un1_CS_0_sqmuxa_i: 2 loads, 2 LSLICEs
|
||||
Net ram2e_ufm.wb_rst13: 2 loads, 0 LSLICEs
|
||||
Net RC7: 2 loads, 2 LSLICEs
|
||||
Net S[2]: 2 loads, 2 LSLICEs
|
||||
Net S[1]: 1 loads, 1 LSLICEs
|
||||
Net ram2e_ufm/wb_rst: 1 loads, 0 LSLICEs
|
||||
Net ram2e_ufm/nRWE_0_i_o3_RNIP8E61: 1 loads, 1 LSLICEs
|
||||
Net N_530: 1 loads, 0 LSLICEs
|
||||
Net N_301_i: 1 loads, 1 LSLICEs
|
||||
Net ram2e_ufm/wb_rst6_i: 1 loads, 1 LSLICEs
|
||||
Net N_523_1: 1 loads, 0 LSLICEs
|
||||
Net N_727_0: 1 loads, 1 LSLICEs
|
||||
Net RATc_i: 1 loads, 1 LSLICEs
|
||||
Number of nets driven by tri-state buffers: 0
|
||||
Top 10 highest fanout non-clock nets:
|
||||
Net S[2]: 60 loads
|
||||
Net S[3]: 48 loads
|
||||
Net S[1]: 46 loads
|
||||
Net S[0]: 31 loads
|
||||
Net FS[11]: 24 loads
|
||||
Net FS[10]: 23 loads
|
||||
Net FS[12]: 23 loads
|
||||
Net FS[9]: 23 loads
|
||||
Net FS[13]: 21 loads
|
||||
Net FS[8]: 18 loads
|
||||
Net S[2]: 51 loads
|
||||
Net S[1]: 44 loads
|
||||
Net S[3]: 40 loads
|
||||
Net S[0]: 32 loads
|
||||
Net FS[8]: 29 loads
|
||||
Net FS[9]: 26 loads
|
||||
Net FS[10]: 25 loads
|
||||
Net FS[11]: 23 loads
|
||||
Net FS[13]: 20 loads
|
||||
Net ram2e_ufm.wb_rst13: 17 loads
|
||||
|
||||
|
||||
|
||||
@ -121,21 +123,22 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
||||
WARNING - map: IO buffer missing for top level port nWE80...logic will be
|
||||
discarded.
|
||||
|
||||
IO (PIO) Attributes
|
||||
-------------------
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| IO Name | Direction | Levelmode | IO |
|
||||
|
||||
|
||||
|
||||
Page 2
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 06/07/24 20:50:09
|
||||
Design: RAM2E Date: 07/12/24 16:08:05
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
IO (PIO) Attributes
|
||||
-------------------
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| IO Name | Direction | Levelmode | IO |
|
||||
| | | IO_TYPE | Register |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[0] | BIDIR | LVCMOS33 | |
|
||||
@ -189,19 +192,19 @@ IO (PIO) Attributes (cont)
|
||||
| BA[1] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| BA[0] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRWEout | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
Page 3
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 06/07/24 20:50:09
|
||||
Design: RAM2E Date: 07/12/24 16:08:05
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRWEout | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nCASout | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRASout | OUTPUT | LVCMOS33 | OUT |
|
||||
@ -255,19 +258,19 @@ IO (PIO) Attributes (cont)
|
||||
| Din[4] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[3] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[2] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
Page 4
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 06/07/24 20:50:09
|
||||
Design: RAM2E Date: 07/12/24 16:08:05
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[2] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[1] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[0] | INPUT | LVCMOS33 | |
|
||||
@ -321,19 +324,19 @@ Signal ram2e_ufm/ufmefb/TCINT undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIIRQO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPICSNEN undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
|
||||
|
||||
Page 5
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 06/07/24 20:50:09
|
||||
Design: RAM2E Date: 07/12/24 16:08:05
|
||||
|
||||
Removed logic (cont)
|
||||
--------------------
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
|
||||
@ -388,15 +391,13 @@ Block ram2e_ufm/ufmefb/GND was optimized away.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Page 6
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 06/07/24 20:50:09
|
||||
Design: RAM2E Date: 07/12/24 16:08:05
|
||||
|
||||
|
||||
Embedded Functional Block Connection Summary
|
||||
--------------------------------------------
|
||||
@ -446,7 +447,7 @@ Run Time and Memory Usage
|
||||
-------------------------
|
||||
|
||||
Total CPU Time: 0 secs
|
||||
Total REAL Time: 0 secs
|
||||
Total REAL Time: 3 secs
|
||||
Peak Memory Usage: 59 MB
|
||||
|
||||
|
||||
@ -456,7 +457,6 @@ Run Time and Memory Usage
|
||||
|
||||
|
||||
|
||||
|
||||
Page 7
|
||||
|
||||
|
||||
|
||||
@ -6,7 +6,7 @@ Performance Grade: 4
|
||||
PACKAGE: TQFP100
|
||||
Package Status: Final Version 1.39
|
||||
|
||||
Fri Jun 07 20:50:19 2024
|
||||
Fri Jul 12 16:08:27 2024
|
||||
|
||||
Pinout by Port Name:
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
@ -283,5 +283,5 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Fri Jun 07 20:50:23 2024
|
||||
Fri Jul 12 16:08:36 2024
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
SCHEMATIC START ;
|
||||
# map: version Diamond (64-bit) 3.11.3.469 -- WARNING: Map write only section -- Fri Jun 07 20:50:09 2024
|
||||
# map: version Diamond (64-bit) 3.11.3.469 -- WARNING: Map write only section -- Fri Jul 12 16:08:06 2024
|
||||
|
||||
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
|
||||
LOCATE COMP "RD[0]" SITE "36" ;
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
#OS: Windows 8 6.2
|
||||
#Hostname: ZANEMACWIN11
|
||||
|
||||
# Fri Jun 7 20:50:00 2024
|
||||
# Fri Jul 12 16:07:07 2024
|
||||
|
||||
#Implementation: impl1
|
||||
|
||||
@ -52,6 +52,7 @@ Synopsys Verilog Compiler, Version comp2018q2p1, Build 461R, Built Apr 1 2019 0
|
||||
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\REFB.v" (library work)
|
||||
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\DHGR-ON.v" (library work)
|
||||
Verilog syntax check successful!
|
||||
File \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v changed - recompiling
|
||||
Selecting top level module RAM2E
|
||||
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
|
||||
Running optimization stage 1 on VHI .......
|
||||
@ -77,12 +78,12 @@ Running optimization stage 2 on EFB .......
|
||||
Running optimization stage 2 on VLO .......
|
||||
Running optimization stage 2 on VHI .......
|
||||
|
||||
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)
|
||||
At c_ver Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
Process took 0h:00m:04s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Fri Jun 7 20:50:00 2024
|
||||
# Fri Jul 12 16:07:12 2024
|
||||
|
||||
###########################################################]
|
||||
|
||||
@ -102,13 +103,14 @@ Implementation : impl1
|
||||
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
File \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\synwork\layer0.srs changed - recompiling
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Fri Jun 7 20:50:00 2024
|
||||
# Fri Jul 12 16:07:12 2024
|
||||
|
||||
###########################################################]
|
||||
|
||||
@ -118,12 +120,12 @@ For a summary of runtime and memory usage for all design units, please see file:
|
||||
|
||||
@END
|
||||
|
||||
At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
|
||||
At c_hdl Exit (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
Process took 0h:00m:05s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Fri Jun 7 20:50:00 2024
|
||||
# Fri Jul 12 16:07:12 2024
|
||||
|
||||
###########################################################]
|
||||
|
||||
@ -143,18 +145,17 @@ Database state : \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\synwork\|impl1
|
||||
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
File \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_comp.srs changed - recompiling
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 68MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Fri Jun 7 20:50:02 2024
|
||||
# Fri Jul 12 16:07:15 2024
|
||||
|
||||
###########################################################]
|
||||
Premap Report
|
||||
|
||||
# Fri Jun 7 20:50:02 2024
|
||||
# Fri Jul 12 16:07:17 2024
|
||||
|
||||
|
||||
Copyright (C) 1994-2018 Synopsys, Inc.
|
||||
@ -183,26 +184,26 @@ Printing clock summary report in "\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\im
|
||||
@N: MF248 |Running in 64-bit mode.
|
||||
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
|
||||
|
||||
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
|
||||
Design Input Complete (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
|
||||
|
||||
|
||||
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
|
||||
Mapper Initialization Complete (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
|
||||
|
||||
|
||||
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB)
|
||||
Start loading timing files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB)
|
||||
|
||||
|
||||
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
|
||||
Finished loading timing files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
|
||||
|
||||
@N: MF284 |Setting synthesis effort to medium for the design
|
||||
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
|
||||
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":21:4:21:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
|
||||
@N: MH105 |UMR3 is only supported for HAPS-80.
|
||||
@N: MH105 |UMR3 is only supported for HAPS-80.
|
||||
@N: BN115 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":140:9:140:12|Removing instance dhgr (in view: work.RAM2E(verilog)) of type view:work.DHGR(verilog) because it does not drive other instances.
|
||||
@N: BN115 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":136:9:136:12|Removing instance dhgr (in view: work.RAM2E(verilog)) of type view:work.DHGR(verilog) because it does not drive other instances.
|
||||
syn_allowed_resources : blockrams=2 set on top level netlist RAM2E
|
||||
|
||||
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
|
||||
Finished netlist restructuring (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
|
||||
|
||||
|
||||
|
||||
@ -212,7 +213,7 @@ Clock Summary
|
||||
Start Requested Requested Clock Clock Clock
|
||||
Level Clock Frequency Period Type Group Load
|
||||
-----------------------------------------------------------------------------------------------
|
||||
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 121
|
||||
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 120
|
||||
|
||||
0 - System 100.0 MHz 10.000 system system_clkgroup 0
|
||||
|
||||
@ -227,7 +228,7 @@ Clock Load Summary
|
||||
Clock Source Clock Pin Non-clock Pin Non-clock Pin
|
||||
Clock Load Pin Seq Example Seq Example Comb Example
|
||||
--------------------------------------------------------------------------------------------
|
||||
C14M 121 C14M(port) RAT.C - un1_C14M.I[0](inv)
|
||||
C14M 120 C14M(port) RAT.C - un1_C14M.I[0](inv)
|
||||
|
||||
System 0 - - - -
|
||||
|
||||
@ -247,14 +248,14 @@ Number of ICG latches not removed: 0
|
||||
|
||||
#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
|
||||
|
||||
2 non-gated/non-generated clock tree(s) driving 125 clock pin(s) of sequential element(s)
|
||||
2 non-gated/non-generated clock tree(s) driving 124 clock pin(s) of sequential element(s)
|
||||
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
|
||||
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
|
||||
|
||||
=========================== Non-Gated/Non-Generated Clocks ============================
|
||||
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
|
||||
---------------------------------------------------------------------------------------
|
||||
@KP:ckid0_0 C14M port 121 PHI1r
|
||||
@KP:ckid0_0 C14M port 120 PHI1r
|
||||
@KP:ckid0_1 PHI1 Unconstrained_port 4 RC[2:0]
|
||||
=======================================================================================
|
||||
|
||||
@ -264,27 +265,25 @@ Clock Tree ID Driving Element Drive Element Type Fanout Sample I
|
||||
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
|
||||
Finished Pre Mapping Phase.
|
||||
|
||||
Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
|
||||
Starting constraint checker (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
|
||||
|
||||
|
||||
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
|
||||
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
|
||||
|
||||
None
|
||||
None
|
||||
|
||||
Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
|
||||
Finished constraint checker (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
|
||||
|
||||
Pre-mapping successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 143MB)
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 143MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Fri Jun 7 20:50:03 2024
|
||||
Process took 0h:00m:10s realtime, 0h:00m:01s cputime
|
||||
# Fri Jul 12 16:07:28 2024
|
||||
|
||||
###########################################################]
|
||||
Map & Optimize Report
|
||||
|
||||
# Fri Jun 7 20:50:03 2024
|
||||
# Fri Jul 12 16:07:31 2024
|
||||
|
||||
|
||||
Copyright (C) 1994-2018 Synopsys, Inc.
|
||||
@ -324,7 +323,7 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h
|
||||
@N: MF284 |Setting synthesis effort to medium for the design
|
||||
|
||||
|
||||
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
|
||||
Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
|
||||
|
||||
|
||||
Available hyper_sources - for debug and ip models
|
||||
@ -333,61 +332,61 @@ Available hyper_sources - for debug and ip models
|
||||
@N: FX493 |Applying initial value "00000000" on instance RWBank[7:0].
|
||||
@N: FX493 |Applying initial value "0000" on instance S[3:0].
|
||||
|
||||
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)
|
||||
Finished RTL optimizations (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)
|
||||
|
||||
@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":14:23:14:28|Found counter in view:work.RAM2E(verilog) instance FS[15:0]
|
||||
|
||||
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 142MB)
|
||||
Starting factoring (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 142MB)
|
||||
|
||||
|
||||
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
|
||||
Finished factoring (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
|
||||
|
||||
|
||||
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
|
||||
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
|
||||
|
||||
|
||||
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
|
||||
Starting Early Timing Optimization (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
|
||||
|
||||
|
||||
Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
|
||||
Finished Early Timing Optimization (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
|
||||
|
||||
|
||||
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
|
||||
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
|
||||
|
||||
|
||||
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
|
||||
Finished preparing to map (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 147MB)
|
||||
|
||||
|
||||
Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
|
||||
Finished technology mapping (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
|
||||
|
||||
Pass CPU time Worst Slack Luts / Registers
|
||||
------------------------------------------------------------
|
||||
1 0h:00m:01s 6.90ns 281 / 125
|
||||
1 0h:00m:01s 6.90ns 280 / 124
|
||||
|
||||
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
|
||||
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
|
||||
|
||||
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
|
||||
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":171:4:171:9|Boundary register BA_1_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
||||
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":171:4:171:9|Boundary register BA_0_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
||||
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":168:4:168:9|Boundary register BA_1_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
||||
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":168:4:168:9|Boundary register BA_0_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
||||
|
||||
Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 158MB peak: 160MB)
|
||||
Finished restoring hierarchy (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:02s; Memory used current: 158MB peak: 160MB)
|
||||
|
||||
|
||||
Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 122MB peak: 160MB)
|
||||
Start Writing Netlists (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:02s; Memory used current: 122MB peak: 160MB)
|
||||
|
||||
Writing Analyst data base \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_m.srm
|
||||
|
||||
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 158MB peak: 160MB)
|
||||
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:02s; Memory used current: 157MB peak: 160MB)
|
||||
|
||||
Writing EDIF Netlist and constraint files
|
||||
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1.edi
|
||||
N-2018.03L-SP1-1
|
||||
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
|
||||
|
||||
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 162MB peak: 164MB)
|
||||
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 163MB)
|
||||
|
||||
|
||||
Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 164MB)
|
||||
Start final timing analysis (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:03s; Memory used current: 160MB peak: 163MB)
|
||||
|
||||
@W: MT246 :"\\mac\icloud\repos\ram2e\cpld\lcmxo2-640hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
|
||||
@N: MT615 |Found clock C14M with period 69.84ns
|
||||
@ -395,7 +394,7 @@ Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:0
|
||||
|
||||
|
||||
##### START OF TIMING REPORT #####[
|
||||
# Timing Report written on Fri Jun 7 20:50:06 2024
|
||||
# Timing Report written on Fri Jul 12 16:07:45 2024
|
||||
#
|
||||
|
||||
|
||||
@ -420,9 +419,9 @@ Worst slack in design: 6.897
|
||||
Requested Estimated Requested Estimated Clock Clock
|
||||
Starting Clock Frequency Frequency Period Period Slack Type Group
|
||||
----------------------------------------------------------------------------------------------------------------------
|
||||
C14M 14.3 MHz 112.1 MHz 69.841 8.918 31.599 declared default_clkgroup
|
||||
C14M 14.3 MHz 120.3 MHz 69.841 8.314 31.675 declared default_clkgroup
|
||||
RAM2E|PHI1 100.0 MHz 322.2 MHz 10.000 3.103 6.897 inferred Inferred_clkgroup_0
|
||||
System 100.0 MHz NA 10.000 NA 67.088 system system_clkgroup
|
||||
System 100.0 MHz NA 10.000 NA 66.719 system system_clkgroup
|
||||
======================================================================================================================
|
||||
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
|
||||
|
||||
@ -437,9 +436,9 @@ Clocks | rise to rise | fall to fall | rise
|
||||
----------------------------------------------------------------------------------------------------------------
|
||||
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
|
||||
----------------------------------------------------------------------------------------------------------------
|
||||
System C14M | 69.841 67.088 | No paths - | No paths - | No paths -
|
||||
System C14M | 69.841 66.719 | No paths - | No paths - | No paths -
|
||||
C14M System | 69.841 68.797 | No paths - | No paths - | No paths -
|
||||
C14M C14M | 69.841 60.923 | No paths - | 34.920 31.599 | No paths -
|
||||
C14M C14M | 69.841 61.527 | No paths - | 34.920 31.675 | No paths -
|
||||
RAM2E|PHI1 C14M | No paths - | No paths - | No paths - | Diff grp -
|
||||
RAM2E|PHI1 RAM2E|PHI1 | No paths - | 10.000 6.897 | No paths - | No paths -
|
||||
================================================================================================================
|
||||
@ -468,10 +467,10 @@ Starting Points with Worst Slack
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
---------------------------------------------------------------------------
|
||||
S[2] C14M FD1S3AX Q S[2] 1.366 31.599
|
||||
S[3] C14M FD1S3AX Q S[3] 1.345 31.619
|
||||
S[1] C14M FD1S3AX Q S[1] 1.344 31.800
|
||||
S[0] C14M FD1S3AX Q S[0] 1.305 31.838
|
||||
S[2] C14M FD1S3AX Q S[2] 1.353 31.675
|
||||
S[3] C14M FD1S3AX Q S[3] 1.337 31.691
|
||||
S[0] C14M FD1S3AX Q S[0] 1.319 32.182
|
||||
S[1] C14M FD1S3AX Q S[1] 1.344 32.656
|
||||
RA[0] C14M FD1P3AX Q RA[0] 1.108 33.707
|
||||
RA[3] C14M FD1P3AX Q RA[3] 1.108 33.707
|
||||
RA[1] C14M FD1P3AX Q RA[1] 1.044 33.771
|
||||
@ -484,21 +483,21 @@ RA[5] C14M FD1P3AX Q RA[5] 1.044 33.771
|
||||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
-----------------------------------------------------------------------------------
|
||||
VOE_i_0io C14M OFS1P3IX CD N_530 34.118 31.599
|
||||
VOE_i_0io C14M OFS1P3IX D VOE_ic_i 35.009 31.800
|
||||
Vout_0io[0] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[1] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[2] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[3] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[4] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[5] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[6] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[7] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
===================================================================================
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------------
|
||||
VOE_i_0io C14M OFS1P3IX CD N_523_1 34.118 31.675
|
||||
RAT C14M FD1S3IX CD RATc_i 34.118 32.147
|
||||
Vout_0io[0] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[1] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[2] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[3] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[4] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[5] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[6] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[7] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
==================================================================================
|
||||
|
||||
|
||||
|
||||
@ -512,9 +511,9 @@ Path information for path number 1:
|
||||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
= Required time: 34.118
|
||||
|
||||
- Propagation time: 2.519
|
||||
- Propagation time: 2.442
|
||||
- Clock delay at starting point: 0.000 (ideal)
|
||||
= Slack (non-critical) : 31.599
|
||||
= Slack (non-critical) : 31.675
|
||||
|
||||
Number of logic level(s): 1
|
||||
Starting point: S[2] / Q
|
||||
@ -522,16 +521,16 @@ Path information for path number 1:
|
||||
The start point is clocked by C14M [rising] on pin CK
|
||||
The end point is clocked by C14M [falling] on pin SCLK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
------------------------------------------------------------------------------------------------------------
|
||||
S[2] FD1S3AX Q Out 1.366 1.366 -
|
||||
S[2] Net - - - - 58
|
||||
ram2e_ufm.un1_wb_adr_0_sqmuxa_2_0_a2_0[0] ORCALUT4 A In 0.000 1.366 -
|
||||
ram2e_ufm.un1_wb_adr_0_sqmuxa_2_0_a2_0[0] ORCALUT4 Z Out 1.153 2.519 -
|
||||
N_530 Net - - - - 3
|
||||
VOE_i_0io OFS1P3IX CD In 0.000 2.519 -
|
||||
============================================================================================================
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
---------------------------------------------------------------------------------------
|
||||
S[2] FD1S3AX Q Out 1.353 1.353 -
|
||||
S[2] Net - - - - 50
|
||||
ram2e_ufm.VOE_2_0_a2 ORCALUT4 A In 0.000 1.353 -
|
||||
ram2e_ufm.VOE_2_0_a2 ORCALUT4 Z Out 1.089 2.442 -
|
||||
N_523_1 Net - - - - 2
|
||||
VOE_i_0io OFS1P3IX CD In 0.000 2.442 -
|
||||
=======================================================================================
|
||||
|
||||
|
||||
|
||||
@ -620,7 +619,7 @@ Starting Points with Worst Slack
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
---------------------------------------------------------------------------------------------------
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBACKO wb_ack 0.000 67.088
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBACKO wb_ack 0.000 66.719
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO0 wb_dato[0] 0.000 69.313
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000 69.313
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO2 wb_dato[2] 0.000 69.313
|
||||
@ -635,21 +634,21 @@ ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO7 wb_dato[7]
|
||||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------------------
|
||||
ram2e_ufm.RWMask[0] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[1] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[2] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[3] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[4] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[5] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[6] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[7] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.LEDEN System FD1P3AX SP N_98 69.369 67.736
|
||||
ram2e_ufm.wb_cyc_stb System FD1P3AX SP N_111 69.369 67.736
|
||||
========================================================================================
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
---------------------------------------------------------------------------------------------------------------
|
||||
ram2e_ufm.wb_cyc_stb System FD1P3AX SP un1_CmdBitbangMXO212_1_i[0] 69.369 66.719
|
||||
ram2e_ufm.LEDEN System FD1P3AX SP un1_LEDEN_0_sqmuxa_1_i_0[0] 69.369 67.736
|
||||
ram2e_ufm.RWMask[0] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[1] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[2] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[3] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[4] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[5] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[6] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[7] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
===============================================================================================================
|
||||
|
||||
|
||||
|
||||
@ -663,30 +662,33 @@ Path information for path number 1:
|
||||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
= Required time: 69.369
|
||||
|
||||
- Propagation time: 2.282
|
||||
- Propagation time: 2.650
|
||||
- Clock delay at starting point: 0.000 (ideal)
|
||||
- Estimated clock delay at start point: -0.000
|
||||
= Slack (non-critical) : 67.088
|
||||
= Slack (non-critical) : 66.719
|
||||
|
||||
Number of logic level(s): 2
|
||||
Number of logic level(s): 3
|
||||
Starting point: ram2e_ufm.ufmefb.EFBInst_0 / WBACKO
|
||||
Ending point: ram2e_ufm.RWMask[0] / SP
|
||||
Ending point: ram2e_ufm.wb_cyc_stb / SP
|
||||
The start point is clocked by System [rising]
|
||||
The end point is clocked by C14M [rising] on pin CK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
----------------------------------------------------------------------------------------------------------------
|
||||
ram2e_ufm.ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 -
|
||||
wb_ack Net - - - - 5
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] ORCALUT4 B In 0.000 0.000 -
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] ORCALUT4 Z Out 1.017 1.017 -
|
||||
un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] Net - - - - 1
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 D In 0.000 1.017 -
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 Z Out 1.265 2.282 -
|
||||
N_104 Net - - - - 8
|
||||
ram2e_ufm.RWMask[0] FD1P3AX SP In 0.000 2.282 -
|
||||
================================================================================================================
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
---------------------------------------------------------------------------------------------------------------
|
||||
ram2e_ufm.ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 -
|
||||
wb_ack Net - - - - 4
|
||||
ram2e_ufm.un1_CmdBitbangMXO212_1_0_0_tz[0] ORCALUT4 B In 0.000 0.000 -
|
||||
ram2e_ufm.un1_CmdBitbangMXO212_1_0_0_tz[0] ORCALUT4 Z Out 1.017 1.017 -
|
||||
un1_CmdBitbangMXO212_1_0_0_tz[0] Net - - - - 1
|
||||
ram2e_ufm.un1_CmdBitbangMXO212_1_0_0_0[0] ORCALUT4 C In 0.000 1.017 -
|
||||
ram2e_ufm.un1_CmdBitbangMXO212_1_0_0_0[0] ORCALUT4 Z Out 1.017 2.034 -
|
||||
un1_CmdBitbangMXO212_1_0_0_0[0] Net - - - - 1
|
||||
ram2e_ufm.wb_cyc_stb_RNO_0 ORCALUT4 A In 0.000 2.034 -
|
||||
ram2e_ufm.wb_cyc_stb_RNO_0 ORCALUT4 Z Out 0.617 2.650 -
|
||||
un1_CmdBitbangMXO212_1_i[0] Net - - - - 1
|
||||
ram2e_ufm.wb_cyc_stb FD1P3AX SP In 0.000 2.650 -
|
||||
===============================================================================================================
|
||||
|
||||
|
||||
|
||||
@ -695,16 +697,16 @@ ram2e_ufm.RWMask[0] FD1P3AX SP In
|
||||
Timing exceptions that could not be applied
|
||||
None
|
||||
|
||||
Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 164MB)
|
||||
Finished final timing analysis (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 163MB)
|
||||
|
||||
|
||||
Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 164MB)
|
||||
Finished timing report (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 163MB)
|
||||
|
||||
---------------------------------------
|
||||
Resource Usage Report
|
||||
Part: lcmxo2_640hc-4
|
||||
|
||||
Register bits: 125 of 640 (20%)
|
||||
Register bits: 124 of 640 (19%)
|
||||
PIC Latch: 0
|
||||
I/O cells: 70
|
||||
|
||||
@ -713,7 +715,7 @@ Details:
|
||||
BB: 8
|
||||
CCU2D: 9
|
||||
EFB: 1
|
||||
FD1P3AX: 58
|
||||
FD1P3AX: 57
|
||||
FD1P3IX: 1
|
||||
FD1S3AX: 31
|
||||
FD1S3AY: 4
|
||||
@ -726,15 +728,16 @@ OB: 41
|
||||
OFS1P3BX: 6
|
||||
OFS1P3DX: 12
|
||||
OFS1P3IX: 3
|
||||
ORCALUT4: 275
|
||||
ORCALUT4: 268
|
||||
PFUMX: 10
|
||||
PUR: 1
|
||||
VHI: 3
|
||||
VLO: 3
|
||||
Mapper successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 33MB peak: 164MB)
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:03s; Memory used current: 33MB peak: 163MB)
|
||||
|
||||
Process took 0h:00m:03s realtime, 0h:00m:03s cputime
|
||||
# Fri Jun 7 20:50:07 2024
|
||||
Process took 0h:00m:15s realtime, 0h:00m:03s cputime
|
||||
# Fri Jul 12 16:07:49 2024
|
||||
|
||||
###########################################################]
|
||||
|
||||
152
CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_bgn.html
Normal file
152
CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_bgn.html
Normal file
@ -0,0 +1,152 @@
|
||||
<HTML>
|
||||
<HEAD><TITLE>Bitgen Report</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Bgn"></A>BITGEN: Bitstream Generator Diamond (64-bit) 3.11.3.469
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Fri Jun 07 20:50:26 2024
|
||||
|
||||
|
||||
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC -w -jedec -gui RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf
|
||||
|
||||
Loading design for application Bitgen from file RAM2E_LCMXO2_640HC_impl1.ncd.
|
||||
Design name: RAM2E
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-640HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application Bitgen from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.11_x64/ispfpga.
|
||||
Package Status: Final Version 1.39.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
|
||||
Running DRC.
|
||||
DRC detected 0 errors and 0 warnings.
|
||||
Reading Preference File from RAM2E_LCMXO2_640HC_impl1.prf.
|
||||
|
||||
<A name="bgn_ps"></A>
|
||||
<B><U><big>Preference Summary:</big></U></B>
|
||||
|
||||
+---------------------------------+---------------------------------+
|
||||
| Preference | Current Setting |
|
||||
+---------------------------------+---------------------------------+
|
||||
| RamCfg | Reset** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MCCLK_FREQ | 2.08** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| CONFIG_SECURE | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| INBUF | ON** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| JTAG_PORT | ENABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SDM_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SLAVE_SPI_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MASTER_SPI_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| I2C_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MUX_CONFIGURATION_PORTS | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| CONFIGURATION | CFG** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| COMPRESS_CONFIG | ON** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MY_ASSP | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| ONE_TIME_PROGRAM | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| ENABLE_TRANSFR | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SHAREDEBRINIT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| BACKGROUND_RECONFIG | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
* Default setting.
|
||||
** The specified setting matches the default setting.
|
||||
|
||||
|
||||
Creating bit map...
|
||||
|
||||
Bitstream Status: Final Version 1.95.
|
||||
|
||||
Saving bit stream in "RAM2E_LCMXO2_640HC_impl1.jed".
|
||||
|
||||
===========
|
||||
UFM Summary.
|
||||
===========
|
||||
UFM Size: 191 Pages (128*191 Bits).
|
||||
UFM Utilization: General Purpose Flash Memory.
|
||||
|
||||
Available General Purpose Flash Memory: 191 Pages (Page 0 to Page 190).
|
||||
Initialized UFM Pages: 1 Page (Page 190).
|
||||
|
||||
Total CPU Time: 3 secs
|
||||
Total REAL Time: 3 secs
|
||||
Peak Memory Usage: 267 MB
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
@ -13,7 +13,7 @@ Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
|
||||
# Written on Fri Jun 7 20:50:03 2024
|
||||
# Written on Fri Jul 12 16:07:24 2024
|
||||
|
||||
##### DESIGN INFO #######################################################
|
||||
|
||||
|
||||
@ -17,24 +17,25 @@ Command line: map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial
|
||||
RAM2E_LCMXO2_640HC_impl1.ngd -o RAM2E_LCMXO2_640HC_impl1_map.ncd -pr
|
||||
RAM2E_LCMXO2_640HC_impl1.prf -mp RAM2E_LCMXO2_640HC_impl1.mrp -lpf //Mac/iC
|
||||
loud/Repos/RAM2E/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_synplify.
|
||||
lpf -lpf //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf -c 0 -gui
|
||||
lpf -lpf //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf -c 0 -gui -msgset
|
||||
//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml
|
||||
Target Vendor: LATTICE
|
||||
Target Device: LCMXO2-640HCTQFP100
|
||||
Target Performance: 4
|
||||
Mapper: xo2c00, version: Diamond (64-bit) 3.11.3.469
|
||||
Mapped on: 06/07/24 20:50:09
|
||||
Mapped on: 07/12/24 16:08:05
|
||||
|
||||
|
||||
<A name="mrp_ds"></A><B><U><big>Design Summary</big></U></B>
|
||||
Number of registers: 125 out of 877 (14%)
|
||||
PFU registers: 103 out of 640 (16%)
|
||||
Number of registers: 124 out of 877 (14%)
|
||||
PFU registers: 102 out of 640 (16%)
|
||||
PIO registers: 22 out of 237 (9%)
|
||||
Number of SLICEs: 148 out of 320 (46%)
|
||||
SLICEs as Logic/ROM: 148 out of 320 (46%)
|
||||
Number of SLICEs: 145 out of 320 (45%)
|
||||
SLICEs as Logic/ROM: 145 out of 320 (45%)
|
||||
SLICEs as RAM: 0 out of 240 (0%)
|
||||
SLICEs as Carry: 9 out of 320 (3%)
|
||||
Number of LUT4s: 295 out of 640 (46%)
|
||||
Number used as logic LUTs: 277
|
||||
Number of LUT4s: 288 out of 640 (45%)
|
||||
Number used as logic LUTs: 270
|
||||
Number used as distributed RAM: 0
|
||||
Number used as ripple logic: 18
|
||||
Number used as shift registers: 0
|
||||
@ -58,44 +59,45 @@ Mapped on: 06/07/24 20:50:09
|
||||
2. Number of logic LUT4s does not include count of distributed RAM and
|
||||
ripple logic.
|
||||
Number of clocks: 2
|
||||
Net C14M_c: 85 loads, 63 rising, 22 falling (Driver: PIO C14M )
|
||||
Net C14M_c: 84 loads, 62 rising, 22 falling (Driver: PIO C14M )
|
||||
Net PHI1_c: 3 loads, 0 rising, 3 falling (Driver: PIO PHI1 )
|
||||
Number of Clock Enables: 13
|
||||
Net N_117_i: 2 loads, 0 LSLICEs
|
||||
Net RWBank14: 11 loads, 11 LSLICEs
|
||||
Net N_347_i: 2 loads, 0 LSLICEs
|
||||
Net RWBank14: 10 loads, 10 LSLICEs
|
||||
Net ram2e_ufm/wb_adr_0_sqmuxa_1_i: 1 loads, 1 LSLICEs
|
||||
Net un9_VOE_0_a2_0_a2: 1 loads, 1 LSLICEs
|
||||
Net un6_DOEEN_0_a2_0_a2: 2 loads, 2 LSLICEs
|
||||
Net ram2e_ufm/un1_wb_adr_0_sqmuxa_2_i[0]: 8 loads, 8 LSLICEs
|
||||
Net ram2e_ufm/N_63: 1 loads, 1 LSLICEs
|
||||
|
||||
Net ram2e_ufm/un1_wb_cyc_stb_0_sqmuxa_1_i[0]: 1 loads, 1 LSLICEs
|
||||
Net ram2e_ufm/N_111: 1 loads, 1 LSLICEs
|
||||
Net ram2e_ufm/N_104: 4 loads, 4 LSLICEs
|
||||
Net ram2e_ufm/N_98: 1 loads, 1 LSLICEs
|
||||
Net un1_CKE48_0_i: 6 loads, 6 LSLICEs
|
||||
Net N_389_i: 2 loads, 0 LSLICEs
|
||||
Net ram2e_ufm/un1_wb_adr_0_sqmuxa_2_i_0[0]: 8 loads, 8 LSLICEs
|
||||
Net ram2e_ufm/un1_CmdBitbangMXO212_1_i[0]: 1 loads, 1 LSLICEs
|
||||
Net ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0[0]: 4 loads, 4 LSLICEs
|
||||
Net ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0[0]: 1 loads, 1 LSLICEs
|
||||
Net un9_VOE_0_a2: 1 loads, 1 LSLICEs
|
||||
Net un1_CKE48_i: 6 loads, 6 LSLICEs
|
||||
Net N_346_i: 2 loads, 0 LSLICEs
|
||||
Net Vout3: 8 loads, 0 LSLICEs
|
||||
Number of LSRs: 8
|
||||
Net N_148: 2 loads, 2 LSLICEs
|
||||
Net N_430_i: 2 loads, 0 LSLICEs
|
||||
Number of LSRs: 9
|
||||
Net un1_CS_0_sqmuxa_i: 2 loads, 2 LSLICEs
|
||||
Net ram2e_ufm.wb_rst13: 2 loads, 0 LSLICEs
|
||||
Net RC7: 2 loads, 2 LSLICEs
|
||||
Net S[2]: 2 loads, 2 LSLICEs
|
||||
Net S[1]: 1 loads, 1 LSLICEs
|
||||
Net ram2e_ufm/wb_rst: 1 loads, 0 LSLICEs
|
||||
Net ram2e_ufm/nRWE_0_i_o3_RNIP8E61: 1 loads, 1 LSLICEs
|
||||
Net N_530: 1 loads, 0 LSLICEs
|
||||
Net N_301_i: 1 loads, 1 LSLICEs
|
||||
Net ram2e_ufm/wb_rst6_i: 1 loads, 1 LSLICEs
|
||||
Net N_523_1: 1 loads, 0 LSLICEs
|
||||
Net N_727_0: 1 loads, 1 LSLICEs
|
||||
Net RATc_i: 1 loads, 1 LSLICEs
|
||||
Number of nets driven by tri-state buffers: 0
|
||||
Top 10 highest fanout non-clock nets:
|
||||
Net S[2]: 60 loads
|
||||
Net S[3]: 48 loads
|
||||
Net S[1]: 46 loads
|
||||
Net S[0]: 31 loads
|
||||
Net FS[11]: 24 loads
|
||||
Net FS[10]: 23 loads
|
||||
Net FS[12]: 23 loads
|
||||
Net FS[9]: 23 loads
|
||||
Net FS[13]: 21 loads
|
||||
Net FS[8]: 18 loads
|
||||
Net S[2]: 51 loads
|
||||
Net S[1]: 44 loads
|
||||
Net S[3]: 40 loads
|
||||
Net S[0]: 32 loads
|
||||
Net FS[8]: 29 loads
|
||||
Net FS[9]: 26 loads
|
||||
Net FS[10]: 25 loads
|
||||
Net FS[11]: 23 loads
|
||||
Net FS[13]: 20 loads
|
||||
Net ram2e_ufm.wb_rst13: 17 loads
|
||||
|
||||
|
||||
|
||||
@ -123,11 +125,14 @@ WARNING - map: IO buffer missing for top level port nWE80...logic will be
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<A name="mrp_ioa"></A><B><U><big>IO (PIO) Attributes</big></U></B>
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| IO Name | Direction | Levelmode | IO |
|
||||
|
||||
| | | IO_TYPE | Register |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[0] | BIDIR | LVCMOS33 | |
|
||||
@ -181,10 +186,10 @@ WARNING - map: IO buffer missing for top level port nWE80...logic will be
|
||||
| BA[1] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| BA[0] | OUTPUT | LVCMOS33 | OUT |
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRWEout | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
| nCASout | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRASout | OUTPUT | LVCMOS33 | OUT |
|
||||
@ -238,10 +243,10 @@ WARNING - map: IO buffer missing for top level port nWE80...logic will be
|
||||
| Din[4] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[3] | INPUT | LVCMOS33 | |
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[2] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
| Din[1] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[0] | INPUT | LVCMOS33 | |
|
||||
@ -296,10 +301,10 @@ Signal ram2e_ufm/ufmefb/TCINT undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIIRQO undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPICSNEN undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
|
||||
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
|
||||
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
|
||||
Signal ram2e_ufm/ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
|
||||
@ -357,8 +362,6 @@ Block ram2e_ufm/ufmefb/GND was optimized away.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<A name="mrp_efb"></A><B><U><big>Embedded Functional Block Connection Summary</big></U></B>
|
||||
|
||||
Desired WISHBONE clock frequency: 14.4 MHz
|
||||
@ -410,7 +413,7 @@ Instance Name: ram2e_ufm/ufmefb/EFBInst_0
|
||||
-------------------------
|
||||
|
||||
Total CPU Time: 0 secs
|
||||
Total REAL Time: 0 secs
|
||||
Total REAL Time: 3 secs
|
||||
Peak Memory Usage: 59 MB
|
||||
|
||||
|
||||
@ -422,7 +425,6 @@ Instance Name: ram2e_ufm/ufmefb/EFBInst_0
|
||||
|
||||
|
||||
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
|
||||
@ -14,7 +14,7 @@ Performance Grade: 4
|
||||
PACKAGE: TQFP100
|
||||
Package Status: Final Version 1.39
|
||||
|
||||
Fri Jun 07 20:50:19 2024
|
||||
Fri Jul 12 16:08:27 2024
|
||||
|
||||
Pinout by Port Name:
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
@ -292,7 +292,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Fri Jun 07 20:50:23 2024
|
||||
Fri Jul 12 16:08:36 2024
|
||||
|
||||
|
||||
|
||||
|
||||
@ -12,11 +12,12 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Fri Jun 07 20:50:10 2024
|
||||
Fri Jul 12 16:08:09 2024
|
||||
|
||||
C:/lscc/diamond/3.11_x64/ispfpga\bin\nt64\par -f RAM2E_LCMXO2_640HC_impl1.p2t
|
||||
RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.dir
|
||||
RAM2E_LCMXO2_640HC_impl1.prf -gui
|
||||
RAM2E_LCMXO2_640HC_impl1.prf -gui -msgset
|
||||
//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml
|
||||
|
||||
|
||||
Preference file: RAM2E_LCMXO2_640HC_impl1.prf.
|
||||
@ -25,22 +26,22 @@ Preference file: RAM2E_LCMXO2_640HC_impl1.prf.
|
||||
Level/ Number Worst Timing Worst Timing Run NCD
|
||||
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
|
||||
---------- -------- ----- ------ ----------- ----------- ---- ------
|
||||
5_1 * 0 55.718 0 0.379 0 16 Completed
|
||||
5_1 * 0 57.398 0 0.379 0 35 Completed
|
||||
* : Design saved.
|
||||
|
||||
Total (real) run time for 1-seed: 16 secs
|
||||
Total (real) run time for 1-seed: 38 secs
|
||||
|
||||
par done!
|
||||
|
||||
Note: user must run 'Trace' for timing closure signoff.
|
||||
|
||||
Lattice Place and Route Report for Design "RAM2E_LCMXO2_640HC_impl1_map.ncd"
|
||||
Fri Jun 07 20:50:10 2024
|
||||
Fri Jul 12 16:08:10 2024
|
||||
|
||||
|
||||
<A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
|
||||
PAR: Place And Route Diamond (64-bit) 3.11.3.469.
|
||||
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2E_LCMXO2_640HC_impl1.prf
|
||||
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2E_LCMXO2_640HC_impl1.prf
|
||||
Preference file: RAM2E_LCMXO2_640HC_impl1.prf.
|
||||
Placement level-cost: 5-1.
|
||||
Routing Iterations: 6
|
||||
@ -66,39 +67,39 @@ Ignore Preference Error(s): True
|
||||
70+4(JTAG)/79 94% bonded
|
||||
IOLOGIC 22/80 27% used
|
||||
|
||||
SLICE 148/320 46% used
|
||||
SLICE 145/320 45% used
|
||||
|
||||
EFB 1/1 100% used
|
||||
|
||||
|
||||
Number of Signals: 464
|
||||
Number of Connections: 1330
|
||||
Number of Signals: 446
|
||||
Number of Connections: 1292
|
||||
|
||||
Pin Constraint Summary:
|
||||
70 out of 70 pins locked (100% locked).
|
||||
|
||||
The following 1 signal is selected to use the primary clock routing resources:
|
||||
C14M_c (driver: C14M, clk load #: 85)
|
||||
C14M_c (driver: C14M, clk load #: 84)
|
||||
|
||||
WARNING - par: Signal "C14M_c" is selected to use Primary clock resources. However, its driver comp "C14M" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
|
||||
The following 1 signal is selected to use the secondary clock routing resources:
|
||||
RWBank14 (driver: ram2e_ufm/SLICE_82, clk load #: 0, sr load #: 0, ce load #: 11)
|
||||
RWBank14 (driver: ram2e_ufm/SLICE_89, clk load #: 0, sr load #: 0, ce load #: 10)
|
||||
|
||||
No signal is selected as Global Set/Reset.
|
||||
Starting Placer Phase 0.
|
||||
............
|
||||
Finished Placer Phase 0. REAL time: 0 secs
|
||||
.............
|
||||
Finished Placer Phase 0. REAL time: 3 secs
|
||||
|
||||
Starting Placer Phase 1.
|
||||
....................
|
||||
Placer score = 70995.
|
||||
Finished Placer Phase 1. REAL time: 9 secs
|
||||
Placer score = 68344.
|
||||
Finished Placer Phase 1. REAL time: 13 secs
|
||||
|
||||
Starting Placer Phase 2.
|
||||
.
|
||||
Placer score = 70831
|
||||
Finished Placer Phase 2. REAL time: 9 secs
|
||||
Placer score = 68130
|
||||
Finished Placer Phase 2. REAL time: 14 secs
|
||||
|
||||
|
||||
|
||||
@ -111,8 +112,8 @@ Global Clock Resources:
|
||||
DCC : 0 out of 8 (0%)
|
||||
|
||||
Global Clocks:
|
||||
PRIMARY "C14M_c" from comp "C14M" on PIO site "62 (PR5D)", clk load = 85
|
||||
SECONDARY "RWBank14" from F0 on comp "ram2e_ufm/SLICE_82" on site "R2C9D", clk load = 0, ce load = 11, sr load = 0
|
||||
PRIMARY "C14M_c" from comp "C14M" on PIO site "62 (PR5D)", clk load = 84
|
||||
SECONDARY "RWBank14" from F0 on comp "ram2e_ufm/SLICE_89" on site "R6C8B", clk load = 0, ce load = 10, sr load = 0
|
||||
|
||||
PRIMARY : 1 out of 8 (12%)
|
||||
SECONDARY: 1 out of 8 (12%)
|
||||
@ -136,20 +137,20 @@ I/O Bank Usage Summary:
|
||||
| 3 | 20 / 20 (100%) | 3.3V | - |
|
||||
+----------+----------------+------------+-----------+
|
||||
|
||||
Total placer CPU time: 7 secs
|
||||
Total placer CPU time: 8 secs
|
||||
|
||||
Dumping design to file RAM2E_LCMXO2_640HC_impl1.dir/5_1.ncd.
|
||||
|
||||
0 connections routed; 1330 unrouted.
|
||||
0 connections routed; 1292 unrouted.
|
||||
Starting router resource preassignment
|
||||
WARNING - par: The driver of primary clock net C14M_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
|
||||
|
||||
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
|
||||
Signal=PHI1_c loads=5 clock_loads=3
|
||||
|
||||
Completed router resource preassignment. Real time: 14 secs
|
||||
Completed router resource preassignment. Real time: 26 secs
|
||||
|
||||
Start NBR router at 20:50:24 06/07/24
|
||||
Start NBR router at 16:08:36 07/12/24
|
||||
|
||||
*****************************************************************
|
||||
Info: NBR allows conflicts(one node used by more than one signal)
|
||||
@ -164,35 +165,41 @@ Note: NBR uses a different method to calculate timing slacks. The
|
||||
your design.
|
||||
*****************************************************************
|
||||
|
||||
Start NBR special constraint process at 20:50:24 06/07/24
|
||||
Start NBR special constraint process at 16:08:36 07/12/24
|
||||
|
||||
Start NBR section for initial routing at 20:50:24 06/07/24
|
||||
Start NBR section for initial routing at 16:08:36 07/12/24
|
||||
Level 4, iteration 1
|
||||
15(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 55.730ns/0.000ns; real time: 14 secs
|
||||
19(0.04%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 57.410ns/0.000ns; real time: 33 secs
|
||||
|
||||
Info: Initial congestion level at 75% usage is 0
|
||||
Info: Initial congestion area at 75% usage is 0 (0.00%)
|
||||
|
||||
Start NBR section for normal routing at 20:50:25 06/07/24
|
||||
Start NBR section for normal routing at 16:08:43 07/12/24
|
||||
Level 4, iteration 1
|
||||
5(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 55.718ns/0.000ns; real time: 15 secs
|
||||
11(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 57.410ns/0.000ns; real time: 33 secs
|
||||
Level 4, iteration 2
|
||||
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 55.718ns/0.000ns; real time: 15 secs
|
||||
3(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 57.398ns/0.000ns; real time: 33 secs
|
||||
Level 4, iteration 3
|
||||
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 57.398ns/0.000ns; real time: 33 secs
|
||||
Level 4, iteration 4
|
||||
2(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 57.398ns/0.000ns; real time: 33 secs
|
||||
Level 4, iteration 5
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 55.718ns/0.000ns; real time: 15 secs
|
||||
Estimated worst slack/total negative slack<setup>: 57.398ns/0.000ns; real time: 33 secs
|
||||
|
||||
Start NBR section for setup/hold timing optimization with effort level 3 at 20:50:25 06/07/24
|
||||
Start NBR section for setup/hold timing optimization with effort level 3 at 16:08:43 07/12/24
|
||||
|
||||
Start NBR section for re-routing at 20:50:25 06/07/24
|
||||
Start NBR section for re-routing at 16:08:43 07/12/24
|
||||
Level 4, iteration 1
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 55.718ns/0.000ns; real time: 15 secs
|
||||
Estimated worst slack/total negative slack<setup>: 57.398ns/0.000ns; real time: 33 secs
|
||||
|
||||
Start NBR section for post-routing at 20:50:25 06/07/24
|
||||
Start NBR section for post-routing at 16:08:43 07/12/24
|
||||
|
||||
End NBR router with 0 unrouted connection
|
||||
|
||||
@ -200,7 +207,7 @@ NBR Summary
|
||||
-----------
|
||||
Number of unrouted connections : 0 (0.00%)
|
||||
Number of connections with timing violations : 0 (0.00%)
|
||||
Estimated worst slack<setup> : 55.718ns
|
||||
Estimated worst slack<setup> : 57.398ns
|
||||
Timing score<setup> : 0
|
||||
-----------
|
||||
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
|
||||
@ -211,9 +218,9 @@ WARNING - par: The following clock signals will be routed by using generic routi
|
||||
Signal=PHI1_c loads=5 clock_loads=3
|
||||
|
||||
Total CPU time 13 secs
|
||||
Total REAL time: 16 secs
|
||||
Total REAL time: 34 secs
|
||||
Completely routed.
|
||||
End of route. 1330 routed (100.00%); 0 unrouted.
|
||||
End of route. 1292 routed (100.00%); 0 unrouted.
|
||||
|
||||
Hold time timing score: 0, hold timing errors: 0
|
||||
|
||||
@ -227,14 +234,14 @@ All signals are completely routed.
|
||||
|
||||
PAR_SUMMARY::Run status = Completed
|
||||
PAR_SUMMARY::Number of unrouted conns = 0
|
||||
PAR_SUMMARY::Worst slack<setup/<ns>> = 55.718
|
||||
PAR_SUMMARY::Worst slack<setup/<ns>> = 57.398
|
||||
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
|
||||
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.379
|
||||
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
|
||||
PAR_SUMMARY::Number of errors = 0
|
||||
|
||||
Total CPU time to completion: 13 secs
|
||||
Total REAL time to completion: 16 secs
|
||||
Total REAL time to completion: 37 secs
|
||||
|
||||
par done!
|
||||
|
||||
|
||||
@ -13,7 +13,7 @@ Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
|
||||
# Written on Fri Jun 7 20:50:02 2024
|
||||
# Written on Fri Jul 12 16:07:19 2024
|
||||
|
||||
##### FILES SYNTAX CHECKED ##############################################
|
||||
Constraint File(s): "\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc"
|
||||
@ -33,7 +33,7 @@ Clock Summary
|
||||
Start Requested Requested Clock Clock Clock
|
||||
Level Clock Frequency Period Type Group Load
|
||||
-----------------------------------------------------------------------------------------------
|
||||
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 121
|
||||
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 120
|
||||
|
||||
0 - System 100.0 MHz 10.000 system system_clkgroup 0
|
||||
|
||||
@ -47,7 +47,7 @@ Clock Load Summary
|
||||
Clock Source Clock Pin Non-clock Pin Non-clock Pin
|
||||
Clock Load Pin Seq Example Seq Example Comb Example
|
||||
--------------------------------------------------------------------------------------------
|
||||
C14M 121 C14M(port) RAT.C - un1_C14M.I[0](inv)
|
||||
C14M 120 C14M(port) RAT.C - un1_C14M.I[0](inv)
|
||||
|
||||
System 0 - - - -
|
||||
|
||||
|
||||
@ -62,7 +62,7 @@
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Updated:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2024/06/07 20:50:30</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2024/07/12 16:08:57</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Location:</SPAN></TD>
|
||||
|
||||
@ -12,7 +12,7 @@
|
||||
#OS: Windows 8 6.2
|
||||
#Hostname: ZANEMACWIN11
|
||||
|
||||
# Fri Jun 7 20:50:00 2024
|
||||
# Fri Jul 12 16:07:07 2024
|
||||
|
||||
#Implementation: impl1
|
||||
|
||||
@ -61,6 +61,7 @@ Synopsys Verilog Compiler, Version comp2018q2p1, Build 461R, Built Apr 1 2019 0
|
||||
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\REFB.v" (library work)
|
||||
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\DHGR-ON.v" (library work)
|
||||
Verilog syntax check successful!
|
||||
File \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v changed - recompiling
|
||||
Selecting top level module RAM2E
|
||||
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
|
||||
Running optimization stage 1 on VHI .......
|
||||
@ -86,12 +87,12 @@ Running optimization stage 2 on EFB .......
|
||||
Running optimization stage 2 on VLO .......
|
||||
Running optimization stage 2 on VHI .......
|
||||
|
||||
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)
|
||||
At c_ver Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
Process took 0h:00m:04s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Fri Jun 7 20:50:00 2024
|
||||
# Fri Jul 12 16:07:12 2024
|
||||
|
||||
###########################################################]
|
||||
|
||||
@ -111,13 +112,14 @@ Implementation : impl1
|
||||
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
File \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\synwork\layer0.srs changed - recompiling
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Fri Jun 7 20:50:00 2024
|
||||
# Fri Jul 12 16:07:12 2024
|
||||
|
||||
###########################################################]
|
||||
|
||||
@ -127,12 +129,12 @@ For a summary of runtime and memory usage for all design units, please see file:
|
||||
|
||||
@END
|
||||
|
||||
At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
|
||||
At c_hdl Exit (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
Process took 0h:00m:05s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Fri Jun 7 20:50:00 2024
|
||||
# Fri Jul 12 16:07:12 2024
|
||||
|
||||
###########################################################]
|
||||
|
||||
@ -152,18 +154,17 @@ Database state : \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\synwork\|impl1
|
||||
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
File \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_comp.srs changed - recompiling
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 68MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Fri Jun 7 20:50:02 2024
|
||||
# Fri Jul 12 16:07:15 2024
|
||||
|
||||
###########################################################]
|
||||
Premap Report
|
||||
|
||||
# Fri Jun 7 20:50:02 2024
|
||||
# Fri Jul 12 16:07:17 2024
|
||||
|
||||
|
||||
Copyright (C) 1994-2018 Synopsys, Inc.
|
||||
@ -192,26 +193,26 @@ Printing clock summary report in "\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\im
|
||||
@N: MF248 |Running in 64-bit mode.
|
||||
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
|
||||
|
||||
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
|
||||
Design Input Complete (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
|
||||
|
||||
|
||||
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
|
||||
Mapper Initialization Complete (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
|
||||
|
||||
|
||||
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB)
|
||||
Start loading timing files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB)
|
||||
|
||||
|
||||
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
|
||||
Finished loading timing files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
|
||||
|
||||
@N: MF284 |Setting synthesis effort to medium for the design
|
||||
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
|
||||
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":21:4:21:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
|
||||
@N: MH105 |UMR3 is only supported for HAPS-80.
|
||||
@N: MH105 |UMR3 is only supported for HAPS-80.
|
||||
@N: BN115 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":140:9:140:12|Removing instance dhgr (in view: work.RAM2E(verilog)) of type view:work.DHGR(verilog) because it does not drive other instances.
|
||||
@N: BN115 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":136:9:136:12|Removing instance dhgr (in view: work.RAM2E(verilog)) of type view:work.DHGR(verilog) because it does not drive other instances.
|
||||
syn_allowed_resources : blockrams=2 set on top level netlist RAM2E
|
||||
|
||||
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
|
||||
Finished netlist restructuring (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
|
||||
|
||||
|
||||
|
||||
@ -221,7 +222,7 @@ Clock Summary
|
||||
Start Requested Requested Clock Clock Clock
|
||||
Level Clock Frequency Period Type Group Load
|
||||
-----------------------------------------------------------------------------------------------
|
||||
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 121
|
||||
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 120
|
||||
|
||||
0 - System 100.0 MHz 10.000 system system_clkgroup 0
|
||||
|
||||
@ -236,7 +237,7 @@ Clock Load Summary
|
||||
Clock Source Clock Pin Non-clock Pin Non-clock Pin
|
||||
Clock Load Pin Seq Example Seq Example Comb Example
|
||||
--------------------------------------------------------------------------------------------
|
||||
C14M 121 C14M(port) RAT.C - un1_C14M.I[0](inv)
|
||||
C14M 120 C14M(port) RAT.C - un1_C14M.I[0](inv)
|
||||
|
||||
System 0 - - - -
|
||||
|
||||
@ -256,14 +257,14 @@ Number of ICG latches not removed: 0
|
||||
|
||||
#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
|
||||
|
||||
2 non-gated/non-generated clock tree(s) driving 125 clock pin(s) of sequential element(s)
|
||||
2 non-gated/non-generated clock tree(s) driving 124 clock pin(s) of sequential element(s)
|
||||
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
|
||||
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
|
||||
|
||||
=========================== Non-Gated/Non-Generated Clocks ============================
|
||||
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
|
||||
---------------------------------------------------------------------------------------
|
||||
@KP:ckid0_0 C14M port 121 PHI1r
|
||||
@KP:ckid0_0 C14M port 120 PHI1r
|
||||
@KP:ckid0_1 PHI1 Unconstrained_port 4 RC[2:0]
|
||||
=======================================================================================
|
||||
|
||||
@ -273,27 +274,25 @@ Clock Tree ID Driving Element Drive Element Type Fanout Sample I
|
||||
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
|
||||
Finished Pre Mapping Phase.
|
||||
|
||||
Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
|
||||
Starting constraint checker (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
|
||||
|
||||
|
||||
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
|
||||
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
|
||||
|
||||
None
|
||||
None
|
||||
|
||||
Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
|
||||
Finished constraint checker (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
|
||||
|
||||
Pre-mapping successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 143MB)
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 143MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Fri Jun 7 20:50:03 2024
|
||||
Process took 0h:00m:10s realtime, 0h:00m:01s cputime
|
||||
# Fri Jul 12 16:07:28 2024
|
||||
|
||||
###########################################################]
|
||||
Map & Optimize Report
|
||||
|
||||
# Fri Jun 7 20:50:03 2024
|
||||
# Fri Jul 12 16:07:31 2024
|
||||
|
||||
|
||||
Copyright (C) 1994-2018 Synopsys, Inc.
|
||||
@ -333,7 +332,7 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h
|
||||
@N: MF284 |Setting synthesis effort to medium for the design
|
||||
|
||||
|
||||
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
|
||||
Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
|
||||
|
||||
|
||||
Available hyper_sources - for debug and ip models
|
||||
@ -342,61 +341,61 @@ Available hyper_sources - for debug and ip models
|
||||
@N: FX493 |Applying initial value "00000000" on instance RWBank[7:0].
|
||||
@N: FX493 |Applying initial value "0000" on instance S[3:0].
|
||||
|
||||
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)
|
||||
Finished RTL optimizations (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)
|
||||
|
||||
@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":14:23:14:28|Found counter in view:work.RAM2E(verilog) instance FS[15:0]
|
||||
|
||||
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 142MB)
|
||||
Starting factoring (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 142MB)
|
||||
|
||||
|
||||
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
|
||||
Finished factoring (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
|
||||
|
||||
|
||||
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
|
||||
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
|
||||
|
||||
|
||||
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
|
||||
Starting Early Timing Optimization (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
|
||||
|
||||
|
||||
Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
|
||||
Finished Early Timing Optimization (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
|
||||
|
||||
|
||||
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
|
||||
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
|
||||
|
||||
|
||||
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
|
||||
Finished preparing to map (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 147MB)
|
||||
|
||||
|
||||
Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
|
||||
Finished technology mapping (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
|
||||
|
||||
Pass CPU time Worst Slack Luts / Registers
|
||||
------------------------------------------------------------
|
||||
1 0h:00m:01s 6.90ns 281 / 125
|
||||
1 0h:00m:01s 6.90ns 280 / 124
|
||||
|
||||
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
|
||||
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
|
||||
|
||||
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
|
||||
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":171:4:171:9|Boundary register BA_1_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
||||
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":171:4:171:9|Boundary register BA_0_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
||||
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":168:4:168:9|Boundary register BA_1_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
||||
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":168:4:168:9|Boundary register BA_0_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
|
||||
|
||||
Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 158MB peak: 160MB)
|
||||
Finished restoring hierarchy (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:02s; Memory used current: 158MB peak: 160MB)
|
||||
|
||||
|
||||
Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 122MB peak: 160MB)
|
||||
Start Writing Netlists (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:02s; Memory used current: 122MB peak: 160MB)
|
||||
|
||||
Writing Analyst data base \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_m.srm
|
||||
|
||||
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 158MB peak: 160MB)
|
||||
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:02s; Memory used current: 157MB peak: 160MB)
|
||||
|
||||
Writing EDIF Netlist and constraint files
|
||||
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1.edi
|
||||
N-2018.03L-SP1-1
|
||||
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
|
||||
|
||||
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 162MB peak: 164MB)
|
||||
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 163MB)
|
||||
|
||||
|
||||
Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 164MB)
|
||||
Start final timing analysis (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:03s; Memory used current: 160MB peak: 163MB)
|
||||
|
||||
@W: MT246 :"\\mac\icloud\repos\ram2e\cpld\lcmxo2-640hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
|
||||
@N: MT615 |Found clock C14M with period 69.84ns
|
||||
@ -404,7 +403,7 @@ Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:0
|
||||
|
||||
|
||||
##### START OF TIMING REPORT #####[
|
||||
# Timing Report written on Fri Jun 7 20:50:06 2024
|
||||
# Timing Report written on Fri Jul 12 16:07:45 2024
|
||||
#
|
||||
|
||||
|
||||
@ -429,9 +428,9 @@ Worst slack in design: 6.897
|
||||
Requested Estimated Requested Estimated Clock Clock
|
||||
Starting Clock Frequency Frequency Period Period Slack Type Group
|
||||
----------------------------------------------------------------------------------------------------------------------
|
||||
C14M 14.3 MHz 112.1 MHz 69.841 8.918 31.599 declared default_clkgroup
|
||||
C14M 14.3 MHz 120.3 MHz 69.841 8.314 31.675 declared default_clkgroup
|
||||
RAM2E|PHI1 100.0 MHz 322.2 MHz 10.000 3.103 6.897 inferred Inferred_clkgroup_0
|
||||
System 100.0 MHz NA 10.000 NA 67.088 system system_clkgroup
|
||||
System 100.0 MHz NA 10.000 NA 66.719 system system_clkgroup
|
||||
======================================================================================================================
|
||||
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
|
||||
|
||||
@ -446,9 +445,9 @@ Clocks | rise to rise | fall to fall | rise
|
||||
----------------------------------------------------------------------------------------------------------------
|
||||
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
|
||||
----------------------------------------------------------------------------------------------------------------
|
||||
System C14M | 69.841 67.088 | No paths - | No paths - | No paths -
|
||||
System C14M | 69.841 66.719 | No paths - | No paths - | No paths -
|
||||
C14M System | 69.841 68.797 | No paths - | No paths - | No paths -
|
||||
C14M C14M | 69.841 60.923 | No paths - | 34.920 31.599 | No paths -
|
||||
C14M C14M | 69.841 61.527 | No paths - | 34.920 31.675 | No paths -
|
||||
RAM2E|PHI1 C14M | No paths - | No paths - | No paths - | Diff grp -
|
||||
RAM2E|PHI1 RAM2E|PHI1 | No paths - | 10.000 6.897 | No paths - | No paths -
|
||||
================================================================================================================
|
||||
@ -477,10 +476,10 @@ Starting Points with Worst Slack
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
---------------------------------------------------------------------------
|
||||
S[2] C14M FD1S3AX Q S[2] 1.366 31.599
|
||||
S[3] C14M FD1S3AX Q S[3] 1.345 31.619
|
||||
S[1] C14M FD1S3AX Q S[1] 1.344 31.800
|
||||
S[0] C14M FD1S3AX Q S[0] 1.305 31.838
|
||||
S[2] C14M FD1S3AX Q S[2] 1.353 31.675
|
||||
S[3] C14M FD1S3AX Q S[3] 1.337 31.691
|
||||
S[0] C14M FD1S3AX Q S[0] 1.319 32.182
|
||||
S[1] C14M FD1S3AX Q S[1] 1.344 32.656
|
||||
RA[0] C14M FD1P3AX Q RA[0] 1.108 33.707
|
||||
RA[3] C14M FD1P3AX Q RA[3] 1.108 33.707
|
||||
RA[1] C14M FD1P3AX Q RA[1] 1.044 33.771
|
||||
@ -493,21 +492,21 @@ RA[5] C14M FD1P3AX Q RA[5] 1.044 33.771
|
||||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
-----------------------------------------------------------------------------------
|
||||
VOE_i_0io C14M OFS1P3IX CD N_530 34.118 31.599
|
||||
VOE_i_0io C14M OFS1P3IX D VOE_ic_i 35.009 31.800
|
||||
Vout_0io[0] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[1] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[2] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[3] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[4] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[5] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[6] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
Vout_0io[7] C14M OFS1P3DX SP Vout3 34.449 32.634
|
||||
===================================================================================
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------------
|
||||
VOE_i_0io C14M OFS1P3IX CD N_523_1 34.118 31.675
|
||||
RAT C14M FD1S3IX CD RATc_i 34.118 32.147
|
||||
Vout_0io[0] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[1] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[2] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[3] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[4] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[5] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[6] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
Vout_0io[7] C14M OFS1P3DX SP Vout3 34.449 32.647
|
||||
==================================================================================
|
||||
|
||||
|
||||
|
||||
@ -521,9 +520,9 @@ Path information for path number 1:
|
||||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
= Required time: 34.118
|
||||
|
||||
- Propagation time: 2.519
|
||||
- Propagation time: 2.442
|
||||
- Clock delay at starting point: 0.000 (ideal)
|
||||
= Slack (non-critical) : 31.599
|
||||
= Slack (non-critical) : 31.675
|
||||
|
||||
Number of logic level(s): 1
|
||||
Starting point: S[2] / Q
|
||||
@ -531,16 +530,16 @@ Path information for path number 1:
|
||||
The start point is clocked by C14M [rising] on pin CK
|
||||
The end point is clocked by C14M [falling] on pin SCLK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
------------------------------------------------------------------------------------------------------------
|
||||
S[2] FD1S3AX Q Out 1.366 1.366 -
|
||||
S[2] Net - - - - 58
|
||||
ram2e_ufm.un1_wb_adr_0_sqmuxa_2_0_a2_0[0] ORCALUT4 A In 0.000 1.366 -
|
||||
ram2e_ufm.un1_wb_adr_0_sqmuxa_2_0_a2_0[0] ORCALUT4 Z Out 1.153 2.519 -
|
||||
N_530 Net - - - - 3
|
||||
VOE_i_0io OFS1P3IX CD In 0.000 2.519 -
|
||||
============================================================================================================
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
---------------------------------------------------------------------------------------
|
||||
S[2] FD1S3AX Q Out 1.353 1.353 -
|
||||
S[2] Net - - - - 50
|
||||
ram2e_ufm.VOE_2_0_a2 ORCALUT4 A In 0.000 1.353 -
|
||||
ram2e_ufm.VOE_2_0_a2 ORCALUT4 Z Out 1.089 2.442 -
|
||||
N_523_1 Net - - - - 2
|
||||
VOE_i_0io OFS1P3IX CD In 0.000 2.442 -
|
||||
=======================================================================================
|
||||
|
||||
|
||||
|
||||
@ -629,7 +628,7 @@ Starting Points with Worst Slack
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
---------------------------------------------------------------------------------------------------
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBACKO wb_ack 0.000 67.088
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBACKO wb_ack 0.000 66.719
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO0 wb_dato[0] 0.000 69.313
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000 69.313
|
||||
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO2 wb_dato[2] 0.000 69.313
|
||||
@ -644,21 +643,21 @@ ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO7 wb_dato[7]
|
||||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------------------
|
||||
ram2e_ufm.RWMask[0] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[1] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[2] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[3] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[4] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[5] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[6] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.RWMask[7] System FD1P3AX SP N_104 69.369 67.088
|
||||
ram2e_ufm.LEDEN System FD1P3AX SP N_98 69.369 67.736
|
||||
ram2e_ufm.wb_cyc_stb System FD1P3AX SP N_111 69.369 67.736
|
||||
========================================================================================
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
---------------------------------------------------------------------------------------------------------------
|
||||
ram2e_ufm.wb_cyc_stb System FD1P3AX SP un1_CmdBitbangMXO212_1_i[0] 69.369 66.719
|
||||
ram2e_ufm.LEDEN System FD1P3AX SP un1_LEDEN_0_sqmuxa_1_i_0[0] 69.369 67.736
|
||||
ram2e_ufm.RWMask[0] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[1] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[2] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[3] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[4] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[5] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[6] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
ram2e_ufm.RWMask[7] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0[0] 69.369 68.105
|
||||
===============================================================================================================
|
||||
|
||||
|
||||
|
||||
@ -672,30 +671,33 @@ Path information for path number 1:
|
||||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
= Required time: 69.369
|
||||
|
||||
- Propagation time: 2.282
|
||||
- Propagation time: 2.650
|
||||
- Clock delay at starting point: 0.000 (ideal)
|
||||
- Estimated clock delay at start point: -0.000
|
||||
= Slack (non-critical) : 67.088
|
||||
= Slack (non-critical) : 66.719
|
||||
|
||||
Number of logic level(s): 2
|
||||
Number of logic level(s): 3
|
||||
Starting point: ram2e_ufm.ufmefb.EFBInst_0 / WBACKO
|
||||
Ending point: ram2e_ufm.RWMask[0] / SP
|
||||
Ending point: ram2e_ufm.wb_cyc_stb / SP
|
||||
The start point is clocked by System [rising]
|
||||
The end point is clocked by C14M [rising] on pin CK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
----------------------------------------------------------------------------------------------------------------
|
||||
ram2e_ufm.ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 -
|
||||
wb_ack Net - - - - 5
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] ORCALUT4 B In 0.000 0.000 -
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] ORCALUT4 Z Out 1.017 1.017 -
|
||||
un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] Net - - - - 1
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 D In 0.000 1.017 -
|
||||
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 Z Out 1.265 2.282 -
|
||||
N_104 Net - - - - 8
|
||||
ram2e_ufm.RWMask[0] FD1P3AX SP In 0.000 2.282 -
|
||||
================================================================================================================
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
---------------------------------------------------------------------------------------------------------------
|
||||
ram2e_ufm.ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 -
|
||||
wb_ack Net - - - - 4
|
||||
ram2e_ufm.un1_CmdBitbangMXO212_1_0_0_tz[0] ORCALUT4 B In 0.000 0.000 -
|
||||
ram2e_ufm.un1_CmdBitbangMXO212_1_0_0_tz[0] ORCALUT4 Z Out 1.017 1.017 -
|
||||
un1_CmdBitbangMXO212_1_0_0_tz[0] Net - - - - 1
|
||||
ram2e_ufm.un1_CmdBitbangMXO212_1_0_0_0[0] ORCALUT4 C In 0.000 1.017 -
|
||||
ram2e_ufm.un1_CmdBitbangMXO212_1_0_0_0[0] ORCALUT4 Z Out 1.017 2.034 -
|
||||
un1_CmdBitbangMXO212_1_0_0_0[0] Net - - - - 1
|
||||
ram2e_ufm.wb_cyc_stb_RNO_0 ORCALUT4 A In 0.000 2.034 -
|
||||
ram2e_ufm.wb_cyc_stb_RNO_0 ORCALUT4 Z Out 0.617 2.650 -
|
||||
un1_CmdBitbangMXO212_1_i[0] Net - - - - 1
|
||||
ram2e_ufm.wb_cyc_stb FD1P3AX SP In 0.000 2.650 -
|
||||
===============================================================================================================
|
||||
|
||||
|
||||
|
||||
@ -704,16 +706,16 @@ ram2e_ufm.RWMask[0] FD1P3AX SP In
|
||||
Timing exceptions that could not be applied
|
||||
None
|
||||
|
||||
Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 164MB)
|
||||
Finished final timing analysis (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 163MB)
|
||||
|
||||
|
||||
Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 164MB)
|
||||
Finished timing report (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 163MB)
|
||||
|
||||
---------------------------------------
|
||||
Resource Usage Report
|
||||
Part: lcmxo2_640hc-4
|
||||
|
||||
Register bits: 125 of 640 (20%)
|
||||
Register bits: 124 of 640 (19%)
|
||||
PIC Latch: 0
|
||||
I/O cells: 70
|
||||
|
||||
@ -722,7 +724,7 @@ Details:
|
||||
BB: 8
|
||||
CCU2D: 9
|
||||
EFB: 1
|
||||
FD1P3AX: 58
|
||||
FD1P3AX: 57
|
||||
FD1P3IX: 1
|
||||
FD1S3AX: 31
|
||||
FD1S3AY: 4
|
||||
@ -735,16 +737,17 @@ OB: 41
|
||||
OFS1P3BX: 6
|
||||
OFS1P3DX: 12
|
||||
OFS1P3IX: 3
|
||||
ORCALUT4: 275
|
||||
ORCALUT4: 268
|
||||
PFUMX: 10
|
||||
PUR: 1
|
||||
VHI: 3
|
||||
VLO: 3
|
||||
Mapper successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 33MB peak: 164MB)
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:03s; Memory used current: 33MB peak: 163MB)
|
||||
|
||||
Process took 0h:00m:03s realtime, 0h:00m:03s cputime
|
||||
# Fri Jun 7 20:50:07 2024
|
||||
Process took 0h:00m:15s realtime, 0h:00m:03s cputime
|
||||
# Fri Jul 12 16:07:49 2024
|
||||
|
||||
###########################################################]
|
||||
|
||||
|
||||
@ -2,17 +2,19 @@
|
||||
Starting: parse design source files
|
||||
(VERI-1482) Analyzing Verilog file C:/lscc/diamond/3.11_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v
|
||||
(VERI-1482) Analyzing Verilog file //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v
|
||||
WARNING - //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v(140,9-140,25) (VERI-1362) CmdRWMaskSet is already implicitly declared on line 131
|
||||
WARNING - //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v(141,9-141,22) (VERI-1362) CmdLEDSet is already implicitly declared on line 131
|
||||
(VERI-1482) Analyzing Verilog file //Mac/iCloud/Repos/RAM2E/CPLD/UFM-LCMXO2.v
|
||||
(VERI-1482) Analyzing Verilog file //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/REFB.v
|
||||
(VERI-1482) Analyzing Verilog file //Mac/iCloud/Repos/RAM2E/CPLD/DHGR-ON.v
|
||||
INFO - //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v(1,8-1,13) (VERI-1018) compiling module RAM2E
|
||||
INFO - //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v(1,1-479,10) (VERI-9000) elaborating module 'RAM2E'
|
||||
INFO - //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v(1,1-476,10) (VERI-9000) elaborating module 'RAM2E'
|
||||
INFO - //Mac/iCloud/Repos/RAM2E/CPLD/UFM-LCMXO2.v(1,1-335,10) (VERI-9000) elaborating module 'RAM2E_UFM_uniq_1'
|
||||
INFO - //Mac/iCloud/Repos/RAM2E/CPLD/DHGR-ON.v(1,1-1,68) (VERI-9000) elaborating module 'DHGR_uniq_1'
|
||||
INFO - //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/REFB.v(8,1-113,10) (VERI-9000) elaborating module 'REFB_uniq_1'
|
||||
INFO - C:/lscc/diamond/3.11_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_1'
|
||||
INFO - C:/lscc/diamond/3.11_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_1'
|
||||
INFO - C:/lscc/diamond/3.11_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1800,1-1872,10) (VERI-9000) elaborating module 'EFB_uniq_1'
|
||||
Done: design load finished with (0) errors, and (0) warnings
|
||||
Done: design load finished with (0) errors, and (2) warnings
|
||||
|
||||
</PRE></BODY></HTML>
|
||||
@ -1,3 +1,3 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<userSetting name="//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml" version="Diamond (64-bit) 3.11.3.469" date="Sat Jun 08 04:44:51 2024" vendor="Lattice Semiconductor Corporation" >
|
||||
<userSetting name="//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml" version="Diamond (64-bit) 3.11.3.469" date="Fri Jul 12 16:10:18 2024" vendor="Lattice Semiconductor Corporation" >
|
||||
</userSetting>
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
Assembler report for RAM2E
|
||||
Sat Jun 08 01:44:21 2024
|
||||
Fri Jul 12 16:09:17 2024
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
|
||||
|
||||
@ -39,7 +39,7 @@ https://fpgasoftware.intel.com/eula.
|
||||
+---------------------------------------------------------------+
|
||||
; Assembler Summary ;
|
||||
+-----------------------+---------------------------------------+
|
||||
; Assembler Status ; Successful - Sat Jun 08 01:44:21 2024 ;
|
||||
; Assembler Status ; Successful - Fri Jul 12 16:09:17 2024 ;
|
||||
; Revision Name ; RAM2E ;
|
||||
; Top-level Entity Name ; RAM2E ;
|
||||
; Family ; MAX II ;
|
||||
@ -69,8 +69,8 @@ https://fpgasoftware.intel.com/eula.
|
||||
+----------------+----------------------------------------------------------------+
|
||||
; Option ; Setting ;
|
||||
+----------------+----------------------------------------------------------------+
|
||||
; JTAG usercode ; 0x00164439 ;
|
||||
; Checksum ; 0x00164839 ;
|
||||
; JTAG usercode ; 0x001661D2 ;
|
||||
; Checksum ; 0x00166552 ;
|
||||
+----------------+----------------------------------------------------------------+
|
||||
|
||||
|
||||
@ -89,13 +89,13 @@ https://fpgasoftware.intel.com/eula.
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime Assembler
|
||||
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Info: Processing started: Sat Jun 08 01:44:20 2024
|
||||
Info: Processing started: Fri Jul 12 16:09:16 2024
|
||||
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2E-MAXII -c RAM2E
|
||||
Info (115031): Writing out detailed assembly data for power analysis
|
||||
Info (115030): Assembler is generating device programming files
|
||||
Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings
|
||||
Info: Peak virtual memory: 13099 megabytes
|
||||
Info: Processing ended: Sat Jun 08 01:44:21 2024
|
||||
Info: Peak virtual memory: 13106 megabytes
|
||||
Info: Processing ended: Fri Jul 12 16:09:17 2024
|
||||
Info: Elapsed time: 00:00:01
|
||||
Info: Total CPU time (on all processors): 00:00:01
|
||||
|
||||
|
||||
@ -1 +1 @@
|
||||
Sat Jun 08 01:44:26 2024
|
||||
Fri Jul 12 16:09:22 2024
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
Fitter report for RAM2E
|
||||
Sat Jun 08 01:44:18 2024
|
||||
Fri Jul 12 16:09:14 2024
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
|
||||
|
||||
@ -57,14 +57,14 @@ https://fpgasoftware.intel.com/eula.
|
||||
+---------------------------------------------------------------------+
|
||||
; Fitter Summary ;
|
||||
+-----------------------+---------------------------------------------+
|
||||
; Fitter Status ; Successful - Sat Jun 08 01:44:18 2024 ;
|
||||
; Fitter Status ; Successful - Fri Jul 12 16:09:14 2024 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
||||
; Revision Name ; RAM2E ;
|
||||
; Top-level Entity Name ; RAM2E ;
|
||||
; Family ; MAX II ;
|
||||
; Device ; EPM240T100C5 ;
|
||||
; Timing Models ; Final ;
|
||||
; Total logic elements ; 238 / 240 ( 99 % ) ;
|
||||
; Total logic elements ; 233 / 240 ( 97 % ) ;
|
||||
; Total pins ; 71 / 80 ( 89 % ) ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 1 / 1 ( 100 % ) ;
|
||||
@ -134,8 +134,8 @@ https://fpgasoftware.intel.com/eula.
|
||||
; ; ;
|
||||
; Usage by Processor ; % Time Used ;
|
||||
; Processor 1 ; 100.0% ;
|
||||
; Processor 2 ; 1.0% ;
|
||||
; Processors 3-4 ; 0.9% ;
|
||||
; Processor 2 ; 1.1% ;
|
||||
; Processors 3-4 ; 1.0% ;
|
||||
+----------------------------+-------------+
|
||||
|
||||
|
||||
@ -150,27 +150,27 @@ The pin-out file can be found in /Repos/RAM2E/CPLD/MAXII-NODHGR/output_files/RAM
|
||||
+---------------------------------------------+-----------------------+
|
||||
; Resource ; Usage ;
|
||||
+---------------------------------------------+-----------------------+
|
||||
; Total logic elements ; 238 / 240 ( 99 % ) ;
|
||||
; -- Combinational with no register ; 112 ;
|
||||
; Total logic elements ; 233 / 240 ( 97 % ) ;
|
||||
; -- Combinational with no register ; 108 ;
|
||||
; -- Register only ; 19 ;
|
||||
; -- Combinational with a register ; 107 ;
|
||||
; -- Combinational with a register ; 106 ;
|
||||
; ; ;
|
||||
; Logic element usage by number of LUT inputs ; ;
|
||||
; -- 4 input functions ; 116 ;
|
||||
; -- 3 input functions ; 53 ;
|
||||
; -- 2 input functions ; 46 ;
|
||||
; -- 4 input functions ; 111 ;
|
||||
; -- 3 input functions ; 56 ;
|
||||
; -- 2 input functions ; 43 ;
|
||||
; -- 1 input functions ; 3 ;
|
||||
; -- 0 input functions ; 1 ;
|
||||
; ; ;
|
||||
; Logic elements by mode ; ;
|
||||
; -- normal mode ; 224 ;
|
||||
; -- normal mode ; 219 ;
|
||||
; -- arithmetic mode ; 14 ;
|
||||
; -- qfbk mode ; 14 ;
|
||||
; -- register cascade mode ; 0 ;
|
||||
; -- synchronous clear/load mode ; 26 ;
|
||||
; -- synchronous clear/load mode ; 25 ;
|
||||
; -- asynchronous clear/load mode ; 0 ;
|
||||
; ; ;
|
||||
; Total registers ; 126 / 240 ( 53 % ) ;
|
||||
; Total registers ; 125 / 240 ( 52 % ) ;
|
||||
; Total LABs ; 24 / 24 ( 100 % ) ;
|
||||
; Logic elements in carry chains ; 15 ;
|
||||
; Virtual pins ; 0 ;
|
||||
@ -185,12 +185,12 @@ The pin-out file can be found in /Repos/RAM2E/CPLD/MAXII-NODHGR/output_files/RAM
|
||||
; Global signals ; 2 ;
|
||||
; -- Global clocks ; 2 / 4 ( 50 % ) ;
|
||||
; JTAGs ; 0 / 1 ( 0 % ) ;
|
||||
; Average interconnect usage (total/H/V) ; 30.7% / 34.1% / 27.1% ;
|
||||
; Peak interconnect usage (total/H/V) ; 30.7% / 34.1% / 27.1% ;
|
||||
; Maximum fan-out ; 122 ;
|
||||
; Average interconnect usage (total/H/V) ; 27.3% / 28.5% / 26.1% ;
|
||||
; Peak interconnect usage (total/H/V) ; 27.3% / 28.5% / 26.1% ;
|
||||
; Maximum fan-out ; 121 ;
|
||||
; Highest non-global fan-out ; 34 ;
|
||||
; Total fan-out ; 992 ;
|
||||
; Average fan-out ; 3.20 ;
|
||||
; Total fan-out ; 973 ;
|
||||
; Average fan-out ; 3.19 ;
|
||||
+---------------------------------------------+-----------------------+
|
||||
|
||||
|
||||
@ -207,16 +207,16 @@ The pin-out file can be found in /Repos/RAM2E/CPLD/MAXII-NODHGR/output_files/RAM
|
||||
; Ain[5] ; 34 ; 1 ; 3 ; 0 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Ain[6] ; 39 ; 1 ; 5 ; 0 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Ain[7] ; 53 ; 2 ; 8 ; 1 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; C14M ; 12 ; 1 ; 1 ; 3 ; 3 ; 122 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; C14M ; 12 ; 1 ; 1 ; 3 ; 3 ; 121 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[0] ; 38 ; 1 ; 4 ; 0 ; 0 ; 15 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[1] ; 40 ; 1 ; 5 ; 0 ; 2 ; 11 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[2] ; 42 ; 1 ; 5 ; 0 ; 0 ; 13 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[3] ; 41 ; 1 ; 5 ; 0 ; 1 ; 13 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[4] ; 48 ; 1 ; 6 ; 0 ; 0 ; 10 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[1] ; 40 ; 1 ; 5 ; 0 ; 2 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[2] ; 42 ; 1 ; 5 ; 0 ; 0 ; 11 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[3] ; 41 ; 1 ; 5 ; 0 ; 1 ; 11 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[4] ; 48 ; 1 ; 6 ; 0 ; 0 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[5] ; 49 ; 1 ; 7 ; 0 ; 2 ; 9 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[6] ; 36 ; 1 ; 4 ; 0 ; 2 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[7] ; 35 ; 1 ; 3 ; 0 ; 0 ; 10 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; PHI1 ; 37 ; 1 ; 4 ; 0 ; 1 ; 5 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[6] ; 36 ; 1 ; 4 ; 0 ; 2 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[7] ; 35 ; 1 ; 3 ; 0 ; 0 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; PHI1 ; 37 ; 1 ; 4 ; 0 ; 1 ; 6 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; nC07X ; 52 ; 2 ; 8 ; 1 ; 4 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; nEN80 ; 28 ; 1 ; 2 ; 0 ; 1 ; 10 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; nWE ; 51 ; 1 ; 7 ; 0 ; 0 ; 9 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
@ -233,7 +233,7 @@ The pin-out file can be found in /Repos/RAM2E/CPLD/MAXII-NODHGR/output_files/RAM
|
||||
; BA[1] ; 14 ; 1 ; 1 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; CKEout ; 4 ; 1 ; 1 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; DQMH ; 100 ; 2 ; 2 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; DQML ; 98 ; 2 ; 2 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; DQML ; 98 ; 2 ; 2 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; Dout[0] ; 77 ; 2 ; 7 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; Dout[1] ; 76 ; 2 ; 7 ; 5 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; Dout[2] ; 74 ; 2 ; 8 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
@ -255,15 +255,15 @@ The pin-out file can be found in /Repos/RAM2E/CPLD/MAXII-NODHGR/output_files/RAM
|
||||
; RAout[7] ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; RAout[8] ; 17 ; 1 ; 1 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RAout[9] ; 15 ; 1 ; 1 ; 2 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[0] ; 70 ; 2 ; 8 ; 4 ; 4 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; Vout[0] ; 70 ; 2 ; 8 ; 4 ; 4 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[1] ; 67 ; 2 ; 8 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[2] ; 69 ; 2 ; 8 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; Vout[3] ; 62 ; 2 ; 8 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; Vout[2] ; 69 ; 2 ; 8 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[3] ; 62 ; 2 ; 8 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[4] ; 71 ; 2 ; 8 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[5] ; 68 ; 2 ; 8 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[6] ; 58 ; 2 ; 8 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[7] ; 57 ; 2 ; 8 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; nCASout ; 3 ; 1 ; 1 ; 4 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; nCASout ; 3 ; 1 ; 1 ; 4 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; nCSout ; 8 ; 1 ; 1 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; nDHGROE ; 87 ; 2 ; 5 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; nDOE ; 55 ; 2 ; 8 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
@ -279,7 +279,7 @@ The pin-out file can be found in /Repos/RAM2E/CPLD/MAXII-NODHGR/output_files/RAM
|
||||
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
|
||||
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
|
||||
; RD[0] ; 97 ; 2 ; 3 ; 5 ; 3 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ;
|
||||
; RD[1] ; 90 ; 2 ; 4 ; 5 ; 1 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ;
|
||||
; RD[1] ; 90 ; 2 ; 4 ; 5 ; 1 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; RDOE ; - ;
|
||||
; RD[2] ; 99 ; 2 ; 2 ; 5 ; 1 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ;
|
||||
; RD[3] ; 89 ; 2 ; 4 ; 5 ; 0 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ;
|
||||
; RD[4] ; 91 ; 2 ; 4 ; 5 ; 2 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ;
|
||||
@ -429,7 +429,7 @@ Note: User assignments will override these defaults. The user specified values a
|
||||
+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
|
||||
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
|
||||
+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
|
||||
; |RAM2E ; 238 (182) ; 126 ; 1 ; 71 ; 0 ; 112 (88) ; 19 (16) ; 107 (78) ; 15 (15) ; 14 (9) ; |RAM2E ; RAM2E ; work ;
|
||||
; |RAM2E ; 233 (177) ; 125 ; 1 ; 71 ; 0 ; 108 (84) ; 19 (16) ; 106 (77) ; 15 (15) ; 14 (9) ; |RAM2E ; RAM2E ; work ;
|
||||
; |RAM2E_UFM:ram2e_ufm| ; 56 (56) ; 32 ; 1 ; 0 ; 0 ; 24 (24) ; 3 (3) ; 29 (29) ; 0 (0) ; 5 (5) ; |RAM2E|RAM2E_UFM:ram2e_ufm ; RAM2E_UFM ; work ;
|
||||
; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst ; UFM ; work ;
|
||||
; |UFM_altufm_none_lbr:UFM_altufm_none_lbr_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component ; UFM_altufm_none_lbr ; work ;
|
||||
@ -510,8 +510,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
; Din[5] ; Input ; (0) ;
|
||||
; Din[7] ; Input ; (0) ;
|
||||
; Din[4] ; Input ; (0) ;
|
||||
; Din[2] ; Input ; (0) ;
|
||||
; Din[3] ; Input ; (0) ;
|
||||
; Din[2] ; Input ; (0) ;
|
||||
; nC07X ; Input ; (0) ;
|
||||
+-----------+----------+---------------+
|
||||
|
||||
@ -521,22 +521,22 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
+--------------------------------+-------------+---------+---------------+--------+----------------------+------------------+
|
||||
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
|
||||
+--------------------------------+-------------+---------+---------------+--------+----------------------+------------------+
|
||||
; BA[0]~0 ; LC_X2_Y3_N0 ; 2 ; Clock enable ; no ; -- ; -- ;
|
||||
; BA[0]~1 ; LC_X3_Y3_N0 ; 3 ; Clock enable ; no ; -- ; -- ;
|
||||
; C14M ; PIN_12 ; 122 ; Clock ; yes ; Global Clock ; GCLK0 ;
|
||||
; CS[0]~2 ; LC_X4_Y1_N1 ; 3 ; Clock enable ; no ; -- ; -- ;
|
||||
; DQML~0 ; LC_X2_Y4_N8 ; 2 ; Clock enable ; no ; -- ; -- ;
|
||||
; Equal1~1 ; LC_X2_Y2_N5 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; Equal1~2 ; LC_X5_Y3_N5 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; Mux14~0 ; LC_X5_Y2_N8 ; 2 ; Clock enable ; no ; -- ; -- ;
|
||||
; PHI1 ; PIN_37 ; 5 ; Clock ; yes ; Global Clock ; GCLK3 ;
|
||||
; RAM2E_UFM:ram2e_ufm|RWMask~1 ; LC_X2_Y1_N9 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; RAM2E_UFM:ram2e_ufm|UFMD[15]~1 ; LC_X7_Y4_N8 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; RAM2E_UFM:ram2e_ufm|always2~8 ; LC_X4_Y1_N4 ; 16 ; Clock enable ; no ; -- ; -- ;
|
||||
; RA[1]~2 ; LC_X5_Y3_N0 ; 6 ; Clock enable ; no ; -- ; -- ;
|
||||
; RDOE ; LC_X7_Y3_N9 ; 8 ; Output enable ; no ; -- ; -- ;
|
||||
; S[0] ; LC_X4_Y4_N4 ; 32 ; Sync. clear ; no ; -- ; -- ;
|
||||
; S[3] ; LC_X4_Y4_N7 ; 34 ; Sync. clear ; no ; -- ; -- ;
|
||||
; BA[0]~0 ; LC_X2_Y2_N7 ; 2 ; Clock enable ; no ; -- ; -- ;
|
||||
; BA[0]~1 ; LC_X4_Y2_N1 ; 3 ; Clock enable ; no ; -- ; -- ;
|
||||
; C14M ; PIN_12 ; 121 ; Clock ; yes ; Global Clock ; GCLK0 ;
|
||||
; CS[0]~2 ; LC_X6_Y1_N5 ; 3 ; Clock enable ; no ; -- ; -- ;
|
||||
; DQMH~0 ; LC_X2_Y4_N0 ; 2 ; Clock enable ; no ; -- ; -- ;
|
||||
; Equal1~1 ; LC_X2_Y2_N0 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; Equal1~2 ; LC_X7_Y2_N5 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; Mux14~0 ; LC_X2_Y3_N9 ; 2 ; Clock enable ; no ; -- ; -- ;
|
||||
; PHI1 ; PIN_37 ; 6 ; Clock ; yes ; Global Clock ; GCLK3 ;
|
||||
; RAM2E_UFM:ram2e_ufm|RWMask~1 ; LC_X4_Y1_N9 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; RAM2E_UFM:ram2e_ufm|UFMD[15]~1 ; LC_X2_Y1_N0 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; RAM2E_UFM:ram2e_ufm|always2~8 ; LC_X5_Y1_N3 ; 15 ; Clock enable ; no ; -- ; -- ;
|
||||
; RA[2]~2 ; LC_X2_Y3_N8 ; 6 ; Clock enable ; no ; -- ; -- ;
|
||||
; RDOE ; LC_X3_Y2_N4 ; 8 ; Output enable ; no ; -- ; -- ;
|
||||
; S[0] ; LC_X3_Y4_N8 ; 32 ; Sync. clear ; no ; -- ; -- ;
|
||||
; S[3] ; LC_X3_Y4_N7 ; 34 ; Sync. clear ; no ; -- ; -- ;
|
||||
+--------------------------------+-------------+---------+---------------+--------+----------------------+------------------+
|
||||
|
||||
|
||||
@ -545,8 +545,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
+------+----------+---------+----------------------+------------------+
|
||||
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
|
||||
+------+----------+---------+----------------------+------------------+
|
||||
; C14M ; PIN_12 ; 122 ; Global Clock ; GCLK0 ;
|
||||
; PHI1 ; PIN_37 ; 5 ; Global Clock ; GCLK3 ;
|
||||
; C14M ; PIN_12 ; 121 ; Global Clock ; GCLK0 ;
|
||||
; PHI1 ; PIN_37 ; 6 ; Global Clock ; GCLK3 ;
|
||||
+------+----------+---------+----------------------+------------------+
|
||||
|
||||
|
||||
@ -555,86 +555,85 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
+-----------------------+--------------------+
|
||||
; Routing Resource Type ; Usage ;
|
||||
+-----------------------+--------------------+
|
||||
; C4s ; 169 / 784 ( 22 % ) ;
|
||||
; Direct links ; 50 / 888 ( 6 % ) ;
|
||||
; C4s ; 158 / 784 ( 20 % ) ;
|
||||
; Direct links ; 61 / 888 ( 7 % ) ;
|
||||
; Global clocks ; 2 / 4 ( 50 % ) ;
|
||||
; LAB clocks ; 7 / 32 ( 22 % ) ;
|
||||
; LUT chains ; 11 / 216 ( 5 % ) ;
|
||||
; Local interconnects ; 353 / 888 ( 40 % ) ;
|
||||
; R4s ; 190 / 704 ( 27 % ) ;
|
||||
; LUT chains ; 8 / 216 ( 4 % ) ;
|
||||
; Local interconnects ; 335 / 888 ( 38 % ) ;
|
||||
; R4s ; 157 / 704 ( 22 % ) ;
|
||||
+-----------------------+--------------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------+
|
||||
; LAB Logic Elements ;
|
||||
+--------------------------------------------+------------------------------+
|
||||
; Number of Logic Elements (Average = 9.92) ; Number of LABs (Total = 24) ;
|
||||
; Number of Logic Elements (Average = 9.71) ; Number of LABs (Total = 24) ;
|
||||
+--------------------------------------------+------------------------------+
|
||||
; 1 ; 0 ;
|
||||
; 2 ; 0 ;
|
||||
; 3 ; 0 ;
|
||||
; 4 ; 0 ;
|
||||
; 4 ; 1 ;
|
||||
; 5 ; 0 ;
|
||||
; 6 ; 0 ;
|
||||
; 7 ; 0 ;
|
||||
; 8 ; 1 ;
|
||||
; 9 ; 0 ;
|
||||
; 10 ; 23 ;
|
||||
; 8 ; 0 ;
|
||||
; 9 ; 1 ;
|
||||
; 10 ; 22 ;
|
||||
+--------------------------------------------+------------------------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------+
|
||||
; LAB-wide Signals ;
|
||||
+------------------------------------+------------------------------+
|
||||
; LAB-wide Signals (Average = 1.38) ; Number of LABs (Total = 24) ;
|
||||
; LAB-wide Signals (Average = 1.58) ; Number of LABs (Total = 24) ;
|
||||
+------------------------------------+------------------------------+
|
||||
; 1 Clock ; 22 ;
|
||||
; 1 Clock enable ; 8 ;
|
||||
; 1 Clock ; 24 ;
|
||||
; 1 Clock enable ; 13 ;
|
||||
; 1 Sync. clear ; 1 ;
|
||||
; 2 Clock enables ; 2 ;
|
||||
+------------------------------------+------------------------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------------+
|
||||
; LAB Signals Sourced ;
|
||||
+----------------------------------------------+------------------------------+
|
||||
; Number of Signals Sourced (Average = 10.13) ; Number of LABs (Total = 24) ;
|
||||
+----------------------------------------------+------------------------------+
|
||||
; 0 ; 0 ;
|
||||
; 1 ; 0 ;
|
||||
; 2 ; 0 ;
|
||||
; 3 ; 0 ;
|
||||
; 4 ; 0 ;
|
||||
; 5 ; 0 ;
|
||||
; 6 ; 0 ;
|
||||
; 7 ; 0 ;
|
||||
; 8 ; 1 ;
|
||||
; 9 ; 0 ;
|
||||
; 10 ; 22 ;
|
||||
; 11 ; 0 ;
|
||||
; 12 ; 0 ;
|
||||
; 13 ; 0 ;
|
||||
; 14 ; 0 ;
|
||||
; 15 ; 1 ;
|
||||
+----------------------------------------------+------------------------------+
|
||||
+----------------------------------------------------------------------------+
|
||||
; LAB Signals Sourced ;
|
||||
+---------------------------------------------+------------------------------+
|
||||
; Number of Signals Sourced (Average = 9.96) ; Number of LABs (Total = 24) ;
|
||||
+---------------------------------------------+------------------------------+
|
||||
; 0 ; 0 ;
|
||||
; 1 ; 0 ;
|
||||
; 2 ; 0 ;
|
||||
; 3 ; 0 ;
|
||||
; 4 ; 1 ;
|
||||
; 5 ; 0 ;
|
||||
; 6 ; 0 ;
|
||||
; 7 ; 0 ;
|
||||
; 8 ; 0 ;
|
||||
; 9 ; 1 ;
|
||||
; 10 ; 20 ;
|
||||
; 11 ; 1 ;
|
||||
; 12 ; 0 ;
|
||||
; 13 ; 0 ;
|
||||
; 14 ; 0 ;
|
||||
; 15 ; 1 ;
|
||||
+---------------------------------------------+------------------------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------+
|
||||
; LAB Signals Sourced Out ;
|
||||
+-------------------------------------------------+------------------------------+
|
||||
; Number of Signals Sourced Out (Average = 7.50) ; Number of LABs (Total = 24) ;
|
||||
; Number of Signals Sourced Out (Average = 7.08) ; Number of LABs (Total = 24) ;
|
||||
+-------------------------------------------------+------------------------------+
|
||||
; 0 ; 0 ;
|
||||
; 1 ; 0 ;
|
||||
; 2 ; 1 ;
|
||||
; 2 ; 2 ;
|
||||
; 3 ; 1 ;
|
||||
; 4 ; 1 ;
|
||||
; 5 ; 2 ;
|
||||
; 6 ; 3 ;
|
||||
; 7 ; 2 ;
|
||||
; 8 ; 5 ;
|
||||
; 9 ; 3 ;
|
||||
; 10 ; 5 ;
|
||||
; 6 ; 1 ;
|
||||
; 7 ; 6 ;
|
||||
; 8 ; 3 ;
|
||||
; 9 ; 5 ;
|
||||
; 10 ; 2 ;
|
||||
; 11 ; 0 ;
|
||||
; 12 ; 1 ;
|
||||
+-------------------------------------------------+------------------------------+
|
||||
@ -643,7 +642,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
+-----------------------------------------------------------------------------+
|
||||
; LAB Distinct Inputs ;
|
||||
+----------------------------------------------+------------------------------+
|
||||
; Number of Distinct Inputs (Average = 12.75) ; Number of LABs (Total = 24) ;
|
||||
; Number of Distinct Inputs (Average = 12.25) ; Number of LABs (Total = 24) ;
|
||||
+----------------------------------------------+------------------------------+
|
||||
; 0 ; 0 ;
|
||||
; 1 ; 0 ;
|
||||
@ -651,24 +650,25 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
; 3 ; 0 ;
|
||||
; 4 ; 2 ;
|
||||
; 5 ; 0 ;
|
||||
; 6 ; 0 ;
|
||||
; 6 ; 1 ;
|
||||
; 7 ; 1 ;
|
||||
; 8 ; 0 ;
|
||||
; 9 ; 2 ;
|
||||
; 8 ; 1 ;
|
||||
; 9 ; 3 ;
|
||||
; 10 ; 1 ;
|
||||
; 11 ; 8 ;
|
||||
; 11 ; 1 ;
|
||||
; 12 ; 1 ;
|
||||
; 13 ; 0 ;
|
||||
; 13 ; 5 ;
|
||||
; 14 ; 2 ;
|
||||
; 15 ; 1 ;
|
||||
; 16 ; 0 ;
|
||||
; 17 ; 1 ;
|
||||
; 18 ; 2 ;
|
||||
; 19 ; 0 ;
|
||||
; 15 ; 0 ;
|
||||
; 16 ; 2 ;
|
||||
; 17 ; 0 ;
|
||||
; 18 ; 1 ;
|
||||
; 19 ; 2 ;
|
||||
; 20 ; 0 ;
|
||||
; 21 ; 0 ;
|
||||
; 22 ; 2 ;
|
||||
; 23 ; 1 ;
|
||||
; 22 ; 0 ;
|
||||
; 23 ; 0 ;
|
||||
; 24 ; 1 ;
|
||||
+----------------------------------------------+------------------------------+
|
||||
|
||||
|
||||
@ -716,7 +716,8 @@ Info (186079): Completed User Assigned Global Signals Promotion Operation
|
||||
Info (186215): Automatically promoted signal "C14M" to use Global clock in PIN 12 File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v Line: 8
|
||||
Info (186216): Automatically promoted some destinations of signal "PHI1" to use Global clock File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v Line: 8
|
||||
Info (186217): Destination "PHI1r" may be non-global or may not use global clock File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v Line: 20
|
||||
Info (186217): Destination "S~0" may be non-global or may not use global clock File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v Line: 19
|
||||
Info (186217): Destination "S~2" may be non-global or may not use global clock File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v Line: 19
|
||||
Info (186217): Destination "S[3]~9" may be non-global or may not use global clock File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v Line: 21
|
||||
Info (186228): Pin "PHI1" drives global clock, but is not placed in a dedicated clock pin position File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v Line: 8
|
||||
Info (186079): Completed Auto Global Promotion Operation
|
||||
Info (176234): Starting register packing
|
||||
@ -732,27 +733,27 @@ Warning (186473): Ignored the FAST_OUTPUT_REGISTER assignment made to the follow
|
||||
Warning (186484): Ignored assignment to node "RAout[7]" because node "RAr[7]", which is feeding it, is not a register File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v Line: 85
|
||||
Info (186469): Finished processing fast register assignments
|
||||
Info (176235): Finished register packing
|
||||
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00
|
||||
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
|
||||
Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
|
||||
Info (170189): Fitter placement preparation operations beginning
|
||||
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01
|
||||
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
|
||||
Info (170191): Fitter placement operations beginning
|
||||
Info (170137): Fitter placement was successful
|
||||
Info (170192): Fitter placement operations ending: elapsed time is 00:00:02
|
||||
Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
|
||||
Info (170193): Fitter routing operations beginning
|
||||
Info (170089): 5e+01 ns of routing delay (approximately 3.2% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report.
|
||||
Info (170195): Router estimated average interconnect usage is 27% of the available device resources
|
||||
Info (170196): Router estimated peak interconnect usage is 27% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
|
||||
Info (170089): 6e+01 ns of routing delay (approximately 3.8% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report.
|
||||
Info (170195): Router estimated average interconnect usage is 24% of the available device resources
|
||||
Info (170196): Router estimated peak interconnect usage is 24% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
|
||||
Info (170202): The Fitter performed an Auto Fit compilation. No optimizations were skipped because the design's timing and routability requirements required full optimization.
|
||||
Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
|
||||
Info (11888): Total time spent on timing analysis during the Fitter is 1.33 seconds.
|
||||
Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
|
||||
Info (11888): Total time spent on timing analysis during the Fitter is 0.64 seconds.
|
||||
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
|
||||
Info (144001): Generated suppressed messages file /Repos/RAM2E/CPLD/MAXII-NODHGR/output_files/RAM2E.fit.smsg
|
||||
Info: Quartus Prime Fitter was successful. 0 errors, 11 warnings
|
||||
Info: Peak virtual memory: 13775 megabytes
|
||||
Info: Processing ended: Sat Jun 08 01:44:18 2024
|
||||
Info: Elapsed time: 00:00:07
|
||||
Info: Total CPU time (on all processors): 00:00:05
|
||||
Info: Peak virtual memory: 13773 megabytes
|
||||
Info: Processing ended: Fri Jul 12 16:09:14 2024
|
||||
Info: Elapsed time: 00:00:04
|
||||
Info: Total CPU time (on all processors): 00:00:04
|
||||
|
||||
|
||||
+----------------------------+
|
||||
|
||||
@ -1,11 +1,11 @@
|
||||
Fitter Status : Successful - Sat Jun 08 01:44:18 2024
|
||||
Fitter Status : Successful - Fri Jul 12 16:09:14 2024
|
||||
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Revision Name : RAM2E
|
||||
Top-level Entity Name : RAM2E
|
||||
Family : MAX II
|
||||
Device : EPM240T100C5
|
||||
Timing Models : Final
|
||||
Total logic elements : 238 / 240 ( 99 % )
|
||||
Total logic elements : 233 / 240 ( 97 % )
|
||||
Total pins : 71 / 80 ( 89 % )
|
||||
Total virtual pins : 0
|
||||
UFM blocks : 1 / 1 ( 100 % )
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
Flow report for RAM2E
|
||||
Sat Jun 08 01:44:25 2024
|
||||
Fri Jul 12 16:09:21 2024
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
|
||||
|
||||
@ -41,14 +41,14 @@ https://fpgasoftware.intel.com/eula.
|
||||
+---------------------------------------------------------------------+
|
||||
; Flow Summary ;
|
||||
+-----------------------+---------------------------------------------+
|
||||
; Flow Status ; Successful - Sat Jun 08 01:44:21 2024 ;
|
||||
; Flow Status ; Successful - Fri Jul 12 16:09:17 2024 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
||||
; Revision Name ; RAM2E ;
|
||||
; Top-level Entity Name ; RAM2E ;
|
||||
; Family ; MAX II ;
|
||||
; Device ; EPM240T100C5 ;
|
||||
; Timing Models ; Final ;
|
||||
; Total logic elements ; 238 / 240 ( 99 % ) ;
|
||||
; Total logic elements ; 233 / 240 ( 97 % ) ;
|
||||
; Total pins ; 71 / 80 ( 89 % ) ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 1 / 1 ( 100 % ) ;
|
||||
@ -60,7 +60,7 @@ https://fpgasoftware.intel.com/eula.
|
||||
+-------------------+---------------------+
|
||||
; Option ; Setting ;
|
||||
+-------------------+---------------------+
|
||||
; Start date & time ; 06/08/2024 01:43:24 ;
|
||||
; Start date & time ; 07/12/2024 16:07:46 ;
|
||||
; Main task ; Compilation ;
|
||||
; Revision Name ; RAM2E ;
|
||||
+-------------------+---------------------+
|
||||
@ -71,7 +71,7 @@ https://fpgasoftware.intel.com/eula.
|
||||
+---------------------------------------+------------------------------+---------------+-------------+------------+
|
||||
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
|
||||
+---------------------------------------+------------------------------+---------------+-------------+------------+
|
||||
; COMPILER_SIGNATURE_ID ; 121380219419.171782540305852 ; -- ; -- ; -- ;
|
||||
; COMPILER_SIGNATURE_ID ; 121380219419.172081486509296 ; -- ; -- ; -- ;
|
||||
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
|
||||
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
|
||||
; NUM_PARALLEL_PROCESSORS ; 4 ; -- ; -- ; -- ;
|
||||
@ -86,11 +86,11 @@ https://fpgasoftware.intel.com/eula.
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Analysis & Synthesis ; 00:00:47 ; 1.0 ; 13152 MB ; 00:00:39 ;
|
||||
; Fitter ; 00:00:07 ; 1.0 ; 13775 MB ; 00:00:05 ;
|
||||
; Assembler ; 00:00:01 ; 1.0 ; 13098 MB ; 00:00:01 ;
|
||||
; Timing Analyzer ; 00:00:02 ; 1.0 ; 13094 MB ; 00:00:02 ;
|
||||
; Total ; 00:00:57 ; -- ; -- ; 00:00:47 ;
|
||||
; Analysis & Synthesis ; 00:01:27 ; 1.0 ; 13151 MB ; 00:00:40 ;
|
||||
; Fitter ; 00:00:04 ; 1.0 ; 13773 MB ; 00:00:04 ;
|
||||
; Assembler ; 00:00:01 ; 1.0 ; 13105 MB ; 00:00:01 ;
|
||||
; Timing Analyzer ; 00:00:02 ; 1.0 ; 13093 MB ; 00:00:01 ;
|
||||
; Total ; 00:01:34 ; -- ; -- ; 00:00:46 ;
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
Analysis & Synthesis report for RAM2E
|
||||
Sat Jun 08 01:44:10 2024
|
||||
Fri Jul 12 16:09:09 2024
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
|
||||
|
||||
@ -46,12 +46,12 @@ https://fpgasoftware.intel.com/eula.
|
||||
+---------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Summary ;
|
||||
+-----------------------------+---------------------------------------------+
|
||||
; Analysis & Synthesis Status ; Successful - Sat Jun 08 01:44:10 2024 ;
|
||||
; Analysis & Synthesis Status ; Successful - Fri Jul 12 16:09:09 2024 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
||||
; Revision Name ; RAM2E ;
|
||||
; Top-level Entity Name ; RAM2E ;
|
||||
; Family ; MAX II ;
|
||||
; Total logic elements ; 252 ;
|
||||
; Total logic elements ; 247 ;
|
||||
; Total pins ; 71 ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 1 / 1 ( 100 % ) ;
|
||||
@ -164,34 +164,34 @@ https://fpgasoftware.intel.com/eula.
|
||||
+---------------------------------------------+-------+
|
||||
; Resource ; Usage ;
|
||||
+---------------------------------------------+-------+
|
||||
; Total logic elements ; 252 ;
|
||||
; -- Combinational with no register ; 126 ;
|
||||
; Total logic elements ; 247 ;
|
||||
; -- Combinational with no register ; 122 ;
|
||||
; -- Register only ; 33 ;
|
||||
; -- Combinational with a register ; 93 ;
|
||||
; -- Combinational with a register ; 92 ;
|
||||
; ; ;
|
||||
; Logic element usage by number of LUT inputs ; ;
|
||||
; -- 4 input functions ; 116 ;
|
||||
; -- 3 input functions ; 53 ;
|
||||
; -- 2 input functions ; 46 ;
|
||||
; -- 4 input functions ; 111 ;
|
||||
; -- 3 input functions ; 56 ;
|
||||
; -- 2 input functions ; 43 ;
|
||||
; -- 1 input functions ; 3 ;
|
||||
; -- 0 input functions ; 1 ;
|
||||
; ; ;
|
||||
; Logic elements by mode ; ;
|
||||
; -- normal mode ; 238 ;
|
||||
; -- normal mode ; 233 ;
|
||||
; -- arithmetic mode ; 14 ;
|
||||
; -- qfbk mode ; 0 ;
|
||||
; -- register cascade mode ; 0 ;
|
||||
; -- synchronous clear/load mode ; 3 ;
|
||||
; -- asynchronous clear/load mode ; 0 ;
|
||||
; ; ;
|
||||
; Total registers ; 126 ;
|
||||
; Total registers ; 125 ;
|
||||
; Total logic cells in carry chains ; 15 ;
|
||||
; I/O pins ; 71 ;
|
||||
; UFM blocks ; 1 ;
|
||||
; Maximum fan-out node ; C14M ;
|
||||
; Maximum fan-out ; 122 ;
|
||||
; Total fan-out ; 1001 ;
|
||||
; Average fan-out ; 3.09 ;
|
||||
; Maximum fan-out ; 121 ;
|
||||
; Total fan-out ; 982 ;
|
||||
; Average fan-out ; 3.08 ;
|
||||
+---------------------------------------------+-------+
|
||||
|
||||
|
||||
@ -200,7 +200,7 @@ https://fpgasoftware.intel.com/eula.
|
||||
+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
|
||||
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
|
||||
+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
|
||||
; |RAM2E ; 252 (191) ; 126 ; 1 ; 71 ; 0 ; 126 (97) ; 33 (25) ; 93 (69) ; 15 (15) ; 0 (0) ; |RAM2E ; RAM2E ; work ;
|
||||
; |RAM2E ; 247 (186) ; 125 ; 1 ; 71 ; 0 ; 122 (93) ; 33 (25) ; 92 (68) ; 15 (15) ; 0 (0) ; |RAM2E ; RAM2E ; work ;
|
||||
; |RAM2E_UFM:ram2e_ufm| ; 61 (61) ; 32 ; 1 ; 0 ; 0 ; 29 (29) ; 8 (8) ; 24 (24) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm ; RAM2E_UFM ; work ;
|
||||
; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst ; UFM ; work ;
|
||||
; |UFM_altufm_none_lbr:UFM_altufm_none_lbr_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component ; UFM_altufm_none_lbr ; work ;
|
||||
@ -222,12 +222,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
+----------------------------------------------+-------+
|
||||
; Statistic ; Value ;
|
||||
+----------------------------------------------+-------+
|
||||
; Total registers ; 126 ;
|
||||
; Total registers ; 125 ;
|
||||
; Number of registers using Synchronous Clear ; 3 ;
|
||||
; Number of registers using Synchronous Load ; 0 ;
|
||||
; Number of registers using Asynchronous Clear ; 0 ;
|
||||
; Number of registers using Asynchronous Load ; 0 ;
|
||||
; Number of registers using Clock Enable ; 59 ;
|
||||
; Number of registers using Clock Enable ; 58 ;
|
||||
; Number of registers using Preset ; 0 ;
|
||||
+----------------------------------------------+-------+
|
||||
|
||||
@ -256,13 +256,13 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+
|
||||
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
|
||||
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+
|
||||
; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |RAM2E|S[2] ;
|
||||
; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |RAM2E|S[3] ;
|
||||
; 4:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |RAM2E|CS[1] ;
|
||||
; 4:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |RAM2E|RAM2E_UFM:ram2e_ufm|RWMask[5] ;
|
||||
; 4:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |RAM2E|RAM2E_UFM:ram2e_ufm|RWMask[4] ;
|
||||
; 16:1 ; 2 bits ; 20 LEs ; 2 LEs ; 18 LEs ; Yes ; |RAM2E|BA[0]~reg0 ;
|
||||
; 17:1 ; 4 bits ; 44 LEs ; 8 LEs ; 36 LEs ; Yes ; |RAM2E|RA[6] ;
|
||||
; 19:1 ; 2 bits ; 24 LEs ; 4 LEs ; 20 LEs ; Yes ; |RAM2E|RA[1] ;
|
||||
; 10:1 ; 2 bits ; 12 LEs ; 4 LEs ; 8 LEs ; Yes ; |RAM2E|DQML~reg0 ;
|
||||
; 17:1 ; 4 bits ; 44 LEs ; 8 LEs ; 36 LEs ; Yes ; |RAM2E|RA[7] ;
|
||||
; 19:1 ; 2 bits ; 24 LEs ; 4 LEs ; 20 LEs ; Yes ; |RAM2E|RA[2] ;
|
||||
; 10:1 ; 2 bits ; 12 LEs ; 4 LEs ; 8 LEs ; Yes ; |RAM2E|DQMH~reg0 ;
|
||||
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+
|
||||
|
||||
|
||||
@ -283,7 +283,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime Analysis & Synthesis
|
||||
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Info: Processing started: Sat Jun 08 01:43:23 2024
|
||||
Info: Processing started: Fri Jul 12 16:07:42 2024
|
||||
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E-MAXII -c RAM2E
|
||||
Info (20032): Parallel compilation is enabled and will use up to 4 processors
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file //mac/icloud/repos/ram2e/cpld/ram2e.v
|
||||
@ -296,12 +296,12 @@ Info (12021): Found 2 design units, including 2 entities, in source file ufm.v
|
||||
Info (12023): Found entity 1: UFM_altufm_none_lbr File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXII-NODHGR/UFM.v Line: 47
|
||||
Info (12023): Found entity 2: UFM File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXII-NODHGR/UFM.v Line: 166
|
||||
Info (12127): Elaborating entity "RAM2E" for the top level hierarchy
|
||||
Info (12128): Elaborating entity "RAM2E_UFM" for hierarchy "RAM2E_UFM:ram2e_ufm" File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v Line: 136
|
||||
Info (12128): Elaborating entity "RAM2E_UFM" for hierarchy "RAM2E_UFM:ram2e_ufm" File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v Line: 132
|
||||
Info (12128): Elaborating entity "UFM" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst" File: //Mac/iCloud/Repos/RAM2E/CPLD/UFM-MAX.v Line: 77
|
||||
Info (12128): Elaborating entity "UFM_altufm_none_lbr" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component" File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXII-NODHGR/UFM.v Line: 217
|
||||
Info (12128): Elaborating entity "DHGR" for hierarchy "DHGR:dhgr" File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v Line: 140
|
||||
Info (12128): Elaborating entity "DHGR" for hierarchy "DHGR:dhgr" File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v Line: 136
|
||||
Warning (13024): Output pins are stuck at VCC or GND
|
||||
Warning (13410): Pin "nDHGROE" is stuck at VCC File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v Line: 139
|
||||
Warning (13410): Pin "nDHGROE" is stuck at VCC File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v Line: 135
|
||||
Warning (13410): Pin "nCSout" is stuck at GND File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v Line: 75
|
||||
Warning (14632): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v Line: 50
|
||||
Warning (14632): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v Line: 50
|
||||
@ -313,17 +313,17 @@ Warning (14632): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot
|
||||
Warning (14632): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v Line: 50
|
||||
Warning (21074): Design contains 1 input pin(s) that do not drive logic
|
||||
Warning (15610): No output dependent on input pin "nWE80" File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v Line: 11
|
||||
Info (21057): Implemented 324 device resources after synthesis - the final resource count might be different
|
||||
Info (21057): Implemented 319 device resources after synthesis - the final resource count might be different
|
||||
Info (21058): Implemented 22 input pins
|
||||
Info (21059): Implemented 41 output pins
|
||||
Info (21060): Implemented 8 bidirectional pins
|
||||
Info (21061): Implemented 252 logic cells
|
||||
Info (21061): Implemented 247 logic cells
|
||||
Info (21070): Implemented 1 User Flash Memory blocks
|
||||
Info (144001): Generated suppressed messages file /Repos/RAM2E/CPLD/MAXII-NODHGR/output_files/RAM2E.map.smsg
|
||||
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 13 warnings
|
||||
Info: Peak virtual memory: 13152 megabytes
|
||||
Info: Processing ended: Sat Jun 08 01:44:10 2024
|
||||
Info: Elapsed time: 00:00:47
|
||||
Info: Peak virtual memory: 13151 megabytes
|
||||
Info: Processing ended: Fri Jul 12 16:09:09 2024
|
||||
Info: Elapsed time: 00:01:27
|
||||
Info: Total CPU time (on all processors): 00:00:40
|
||||
|
||||
|
||||
|
||||
@ -1,9 +1,9 @@
|
||||
Analysis & Synthesis Status : Successful - Sat Jun 08 01:44:10 2024
|
||||
Analysis & Synthesis Status : Successful - Fri Jul 12 16:09:09 2024
|
||||
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Revision Name : RAM2E
|
||||
Top-level Entity Name : RAM2E
|
||||
Family : MAX II
|
||||
Total logic elements : 252
|
||||
Total logic elements : 247
|
||||
Total pins : 71
|
||||
Total virtual pins : 0
|
||||
UFM blocks : 1 / 1 ( 100 % )
|
||||
|
||||
Binary file not shown.
@ -1,5 +1,5 @@
|
||||
Timing Analyzer report for RAM2E
|
||||
Sat Jun 08 01:44:25 2024
|
||||
Fri Jul 12 16:09:21 2024
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
|
||||
|
||||
@ -17,11 +17,11 @@ Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
9. Recovery Summary
|
||||
10. Removal Summary
|
||||
11. Minimum Pulse Width Summary
|
||||
12. Setup: 'ram2e_ufm|DRCLK|regout'
|
||||
13. Setup: 'ram2e_ufm|ARCLK|regout'
|
||||
12. Setup: 'ram2e_ufm|ARCLK|regout'
|
||||
13. Setup: 'ram2e_ufm|DRCLK|regout'
|
||||
14. Setup: 'C14M'
|
||||
15. Hold: 'ram2e_ufm|ARCLK|regout'
|
||||
16. Hold: 'ram2e_ufm|DRCLK|regout'
|
||||
15. Hold: 'ram2e_ufm|DRCLK|regout'
|
||||
16. Hold: 'ram2e_ufm|ARCLK|regout'
|
||||
17. Hold: 'C14M'
|
||||
18. Setup Transfers
|
||||
19. Hold Transfers
|
||||
@ -80,10 +80,11 @@ https://fpgasoftware.intel.com/eula.
|
||||
; Maximum allowed ; 4 ;
|
||||
; ; ;
|
||||
; Average used ; 1.00 ;
|
||||
; Maximum used ; 1 ;
|
||||
; Maximum used ; 2 ;
|
||||
; ; ;
|
||||
; Usage by Processor ; % Time Used ;
|
||||
; Processor 1 ; 100.0% ;
|
||||
; Processor 2 ; 0.0% ;
|
||||
+----------------------------+-------------+
|
||||
|
||||
|
||||
@ -92,8 +93,8 @@ https://fpgasoftware.intel.com/eula.
|
||||
+------------------+--------+--------------------------+
|
||||
; SDC File Path ; Status ; Read at ;
|
||||
+------------------+--------+--------------------------+
|
||||
; ../RAM2E.sdc ; OK ; Sat Jun 08 01:44:25 2024 ;
|
||||
; ../RAM2E-MAX.sdc ; OK ; Sat Jun 08 01:44:25 2024 ;
|
||||
; ../RAM2E.sdc ; OK ; Fri Jul 12 16:09:20 2024 ;
|
||||
; ../RAM2E-MAX.sdc ; OK ; Fri Jul 12 16:09:20 2024 ;
|
||||
+------------------+--------+--------------------------+
|
||||
|
||||
|
||||
@ -115,7 +116,7 @@ https://fpgasoftware.intel.com/eula.
|
||||
+-----------+-----------------+------------------------+------+
|
||||
; 10.0 MHz ; 10.0 MHz ; ram2e_ufm|ARCLK|regout ; ;
|
||||
; 10.0 MHz ; 10.0 MHz ; ram2e_ufm|DRCLK|regout ; ;
|
||||
; 52.57 MHz ; 52.57 MHz ; C14M ; ;
|
||||
; 65.96 MHz ; 65.96 MHz ; C14M ; ;
|
||||
+-----------+-----------------+------------------------+------+
|
||||
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
|
||||
|
||||
@ -125,9 +126,9 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
|
||||
+------------------------+---------+---------------+
|
||||
; Clock ; Slack ; End Point TNS ;
|
||||
+------------------------+---------+---------------+
|
||||
; ram2e_ufm|ARCLK|regout ; -23.743 ; -23.743 ;
|
||||
; ram2e_ufm|DRCLK|regout ; -23.723 ; -23.723 ;
|
||||
; ram2e_ufm|ARCLK|regout ; -22.545 ; -22.545 ;
|
||||
; C14M ; -8.511 ; -94.827 ;
|
||||
; C14M ; -8.564 ; -94.357 ;
|
||||
+------------------------+---------+---------------+
|
||||
|
||||
|
||||
@ -136,9 +137,9 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
|
||||
+------------------------+---------+---------------+
|
||||
; Clock ; Slack ; End Point TNS ;
|
||||
+------------------------+---------+---------------+
|
||||
; ram2e_ufm|ARCLK|regout ; -17.454 ; -17.454 ;
|
||||
; ram2e_ufm|DRCLK|regout ; -16.286 ; -16.286 ;
|
||||
; C14M ; 1.400 ; 0.000 ;
|
||||
; ram2e_ufm|DRCLK|regout ; -16.306 ; -16.306 ;
|
||||
; ram2e_ufm|ARCLK|regout ; -16.256 ; -16.256 ;
|
||||
; C14M ; 1.408 ; 0.000 ;
|
||||
+------------------------+---------+---------------+
|
||||
|
||||
|
||||
@ -165,261 +166,261 @@ No paths to report.
|
||||
+------------------------+--------+---------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Setup: 'ram2e_ufm|DRCLK|regout' ;
|
||||
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
||||
; -23.723 ; RAM2E_UFM:ram2e_ufm|DRShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.001 ; -1.629 ; 2.095 ;
|
||||
; -23.713 ; RAM2E_UFM:ram2e_ufm|DRDIn ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.001 ; -1.629 ; 2.085 ;
|
||||
; 100.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; 200.000 ; 0.000 ; 80.000 ;
|
||||
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Setup: 'ram2e_ufm|ARCLK|regout' ;
|
||||
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
||||
; -22.545 ; RAM2E_UFM:ram2e_ufm|ARShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M ; ram2e_ufm|ARCLK|regout ; 0.001 ; -0.997 ; 1.549 ;
|
||||
; -23.743 ; RAM2E_UFM:ram2e_ufm|ARShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M ; ram2e_ufm|ARCLK|regout ; 0.001 ; -2.195 ; 1.549 ;
|
||||
; 100.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 200.000 ; 0.000 ; 80.000 ;
|
||||
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Setup: 'ram2e_ufm|DRCLK|regout' ;
|
||||
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
||||
; -23.723 ; RAM2E_UFM:ram2e_ufm|DRShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.001 ; -2.165 ; 1.559 ;
|
||||
; -23.693 ; RAM2E_UFM:ram2e_ufm|DRDIn ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.001 ; -2.165 ; 1.529 ;
|
||||
; 100.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; 200.000 ; 0.000 ; 80.000 ;
|
||||
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Setup: 'C14M' ;
|
||||
+--------+-----------------------------------------------------------------------------------------------------------------+---------------------------------+------------------------+-------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+--------+-----------------------------------------------------------------------------------------------------------------+---------------------------------+------------------------+-------------+--------------+------------+------------+
|
||||
; -8.511 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.629 ; 9.808 ;
|
||||
; -8.511 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.629 ; 9.808 ;
|
||||
; -8.511 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.629 ; 9.808 ;
|
||||
; -8.297 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|LEDEN ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.629 ; 9.594 ;
|
||||
; -8.073 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.629 ; 9.370 ;
|
||||
; -8.073 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.629 ; 9.370 ;
|
||||
; -8.073 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.629 ; 9.370 ;
|
||||
; -8.073 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.629 ; 9.370 ;
|
||||
; -8.073 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.629 ; 9.370 ;
|
||||
; -7.739 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.629 ; 9.036 ;
|
||||
; -6.971 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.629 ; 8.268 ;
|
||||
; -5.922 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.629 ; 7.219 ;
|
||||
; 25.409 ; S[1] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 9.178 ;
|
||||
; 25.409 ; S[1] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 9.178 ;
|
||||
; 25.426 ; S[1] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 9.161 ;
|
||||
; 25.426 ; S[1] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 9.161 ;
|
||||
; 25.426 ; S[1] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 9.161 ;
|
||||
; 25.574 ; S[0] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 9.013 ;
|
||||
; 25.574 ; S[0] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 9.013 ;
|
||||
; 25.591 ; S[0] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 8.996 ;
|
||||
; 25.591 ; S[0] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 8.996 ;
|
||||
; 25.591 ; S[0] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 8.996 ;
|
||||
; 26.100 ; S[1] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 8.487 ;
|
||||
; 26.100 ; S[1] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 8.487 ;
|
||||
; 26.100 ; S[1] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 8.487 ;
|
||||
; 26.265 ; S[0] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 8.322 ;
|
||||
; 26.265 ; S[0] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 8.322 ;
|
||||
; 26.265 ; S[0] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 8.322 ;
|
||||
; 27.658 ; S[2] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.929 ;
|
||||
; 27.658 ; S[2] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.929 ;
|
||||
; 27.675 ; S[2] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.912 ;
|
||||
; 27.675 ; S[2] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.912 ;
|
||||
; 27.675 ; S[2] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.912 ;
|
||||
; 27.916 ; S[3] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.671 ;
|
||||
; 27.916 ; S[3] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.671 ;
|
||||
; 27.933 ; S[3] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.654 ;
|
||||
; 27.933 ; S[3] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.654 ;
|
||||
; 27.933 ; S[3] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.654 ;
|
||||
; 28.161 ; S[0] ; RAT ; C14M ; C14M ; 34.920 ; 0.000 ; 6.426 ;
|
||||
; 28.349 ; S[2] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.238 ;
|
||||
; 28.349 ; S[2] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.238 ;
|
||||
; 28.349 ; S[2] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.238 ;
|
||||
; 28.607 ; S[3] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.980 ;
|
||||
; 28.607 ; S[3] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.980 ;
|
||||
; 28.607 ; S[3] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.980 ;
|
||||
; 28.892 ; S[1] ; VOE ; C14M ; C14M ; 34.920 ; 0.000 ; 5.695 ;
|
||||
; 30.205 ; S[0] ; VOE ; C14M ; C14M ; 34.920 ; 0.000 ; 4.382 ;
|
||||
; 30.358 ; S[1] ; RAT ; C14M ; C14M ; 34.920 ; 0.000 ; 4.229 ;
|
||||
; 30.475 ; S[2] ; VOE ; C14M ; C14M ; 34.920 ; 0.000 ; 4.112 ;
|
||||
; 30.866 ; S[3] ; VOE ; C14M ; C14M ; 34.920 ; 0.000 ; 3.721 ;
|
||||
; 31.113 ; S[2] ; RAT ; C14M ; C14M ; 34.920 ; 0.000 ; 3.474 ;
|
||||
; 31.289 ; RA[7] ; RAr[7] ; C14M ; C14M ; 34.920 ; 0.000 ; 3.298 ;
|
||||
; 31.450 ; S[3] ; RAT ; C14M ; C14M ; 34.920 ; 0.000 ; 3.137 ;
|
||||
; 31.653 ; RA[10] ; RAr[10] ; C14M ; C14M ; 34.920 ; 0.000 ; 2.934 ;
|
||||
; 31.895 ; RA[3] ; RAr[3] ; C14M ; C14M ; 34.920 ; 0.000 ; 2.692 ;
|
||||
; 31.969 ; RA[9] ; RAr[9] ; C14M ; C14M ; 34.920 ; 0.000 ; 2.618 ;
|
||||
; 32.053 ; nRWE ; nRWEout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 2.534 ;
|
||||
; 32.477 ; RA[11] ; RAr[11] ; C14M ; C14M ; 34.920 ; 0.000 ; 2.110 ;
|
||||
; 32.499 ; nCAS ; nCASout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 2.088 ;
|
||||
; 32.563 ; RA[8] ; RAr[8] ; C14M ; C14M ; 34.920 ; 0.000 ; 2.024 ;
|
||||
; 32.583 ; CKE ; CKEout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 2.004 ;
|
||||
; 32.584 ; RA[6] ; RAr[6] ; C14M ; C14M ; 34.920 ; 0.000 ; 2.003 ;
|
||||
; 32.594 ; nRAS ; nRASout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 1.993 ;
|
||||
; 32.965 ; RA[5] ; RAr[5] ; C14M ; C14M ; 34.920 ; 0.000 ; 1.622 ;
|
||||
; 32.971 ; RA[0] ; RAr[0] ; C14M ; C14M ; 34.920 ; 0.000 ; 1.616 ;
|
||||
; 32.973 ; RA[1] ; RAr[1] ; C14M ; C14M ; 34.920 ; 0.000 ; 1.614 ;
|
||||
; 32.980 ; RA[4] ; RAr[4] ; C14M ; C14M ; 34.920 ; 0.000 ; 1.607 ;
|
||||
; 32.981 ; RA[2] ; RAr[2] ; C14M ; C14M ; 34.920 ; 0.000 ; 1.606 ;
|
||||
; 55.470 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; C14M ; C14M ; 69.841 ; 0.000 ; 14.038 ;
|
||||
; 55.780 ; FS[1] ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; C14M ; C14M ; 69.841 ; 0.000 ; 13.728 ;
|
||||
; 55.931 ; S[1] ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; C14M ; C14M ; 69.841 ; 0.000 ; 13.577 ;
|
||||
; 55.942 ; S[1] ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; C14M ; C14M ; 69.841 ; 0.000 ; 13.566 ;
|
||||
; 56.030 ; FS[4] ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; C14M ; C14M ; 69.841 ; 0.000 ; 13.478 ;
|
||||
; 56.222 ; S[0] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.286 ;
|
||||
; 56.331 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; C14M ; C14M ; 69.841 ; 0.000 ; 13.177 ;
|
||||
; 56.411 ; S[1] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.097 ;
|
||||
; 56.411 ; S[1] ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.097 ;
|
||||
; 56.411 ; S[1] ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.097 ;
|
||||
; 56.609 ; S[0] ; RAM2E_UFM:ram2e_ufm|DRCLK ; C14M ; C14M ; 69.841 ; 0.000 ; 12.899 ;
|
||||
; 56.626 ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; C14M ; C14M ; 69.841 ; 0.000 ; 12.882 ;
|
||||
; 56.641 ; FS[1] ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; C14M ; C14M ; 69.841 ; 0.000 ; 12.867 ;
|
||||
; 56.652 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.856 ;
|
||||
; 56.660 ; FS[3] ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; C14M ; C14M ; 69.841 ; 0.000 ; 12.848 ;
|
||||
; 56.718 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.790 ;
|
||||
; 56.718 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.790 ;
|
||||
; 56.718 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.790 ;
|
||||
; 56.729 ; FS[15] ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; C14M ; C14M ; 69.841 ; 0.000 ; 12.779 ;
|
||||
; 56.748 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.760 ;
|
||||
; 56.777 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.731 ;
|
||||
; 56.836 ; S[0] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.672 ;
|
||||
; 56.836 ; S[0] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.672 ;
|
||||
; 56.836 ; S[0] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.672 ;
|
||||
; 56.836 ; S[0] ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.672 ;
|
||||
; 56.836 ; S[0] ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.672 ;
|
||||
; 56.836 ; S[0] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.672 ;
|
||||
; 56.836 ; S[0] ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.672 ;
|
||||
; 56.849 ; S[1] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.659 ;
|
||||
; 56.849 ; S[1] ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.659 ;
|
||||
; 56.849 ; S[1] ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.659 ;
|
||||
; 56.849 ; S[1] ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.659 ;
|
||||
; -8.564 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 10.397 ;
|
||||
; -8.231 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 10.064 ;
|
||||
; -8.230 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 10.063 ;
|
||||
; -8.085 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 9.918 ;
|
||||
; -8.085 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 9.918 ;
|
||||
; -8.085 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 9.918 ;
|
||||
; -8.085 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 9.918 ;
|
||||
; -8.085 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 9.918 ;
|
||||
; -8.085 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 9.918 ;
|
||||
; -8.085 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 9.918 ;
|
||||
; -7.387 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|LEDEN ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 9.220 ;
|
||||
; -5.350 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 7.183 ;
|
||||
; 27.340 ; S[2] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.247 ;
|
||||
; 27.340 ; S[2] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.247 ;
|
||||
; 27.340 ; S[2] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.247 ;
|
||||
; 27.358 ; S[2] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.229 ;
|
||||
; 27.358 ; S[2] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.229 ;
|
||||
; 27.440 ; S[3] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.147 ;
|
||||
; 27.440 ; S[3] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.147 ;
|
||||
; 27.440 ; S[3] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.147 ;
|
||||
; 27.458 ; S[3] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.129 ;
|
||||
; 27.458 ; S[3] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.129 ;
|
||||
; 27.666 ; S[1] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.921 ;
|
||||
; 27.666 ; S[1] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.921 ;
|
||||
; 27.666 ; S[1] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.921 ;
|
||||
; 27.684 ; S[1] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.903 ;
|
||||
; 27.684 ; S[1] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.903 ;
|
||||
; 28.345 ; S[0] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.242 ;
|
||||
; 28.345 ; S[0] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.242 ;
|
||||
; 28.345 ; S[0] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.242 ;
|
||||
; 28.363 ; S[0] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.224 ;
|
||||
; 28.363 ; S[0] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.224 ;
|
||||
; 28.412 ; S[2] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.175 ;
|
||||
; 28.412 ; S[2] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.175 ;
|
||||
; 28.412 ; S[2] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.175 ;
|
||||
; 28.512 ; S[3] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.075 ;
|
||||
; 28.512 ; S[3] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.075 ;
|
||||
; 28.512 ; S[3] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.075 ;
|
||||
; 28.738 ; S[1] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.849 ;
|
||||
; 28.738 ; S[1] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.849 ;
|
||||
; 28.738 ; S[1] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.849 ;
|
||||
; 29.047 ; S[1] ; RAT ; C14M ; C14M ; 34.920 ; 0.000 ; 5.540 ;
|
||||
; 29.369 ; S[1] ; VOE ; C14M ; C14M ; 34.920 ; 0.000 ; 5.218 ;
|
||||
; 29.417 ; S[0] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.170 ;
|
||||
; 29.417 ; S[0] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.170 ;
|
||||
; 29.417 ; S[0] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.170 ;
|
||||
; 30.326 ; S[3] ; VOE ; C14M ; C14M ; 34.920 ; 0.000 ; 4.261 ;
|
||||
; 30.506 ; S[3] ; RAT ; C14M ; C14M ; 34.920 ; 0.000 ; 4.081 ;
|
||||
; 30.779 ; S[2] ; VOE ; C14M ; C14M ; 34.920 ; 0.000 ; 3.808 ;
|
||||
; 30.863 ; S[2] ; RAT ; C14M ; C14M ; 34.920 ; 0.000 ; 3.724 ;
|
||||
; 31.286 ; S[0] ; VOE ; C14M ; C14M ; 34.920 ; 0.000 ; 3.301 ;
|
||||
; 31.310 ; S[0] ; RAT ; C14M ; C14M ; 34.920 ; 0.000 ; 3.277 ;
|
||||
; 31.398 ; RA[11] ; RAr[11] ; C14M ; C14M ; 34.920 ; 0.000 ; 3.189 ;
|
||||
; 31.898 ; nRWE ; nRWEout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 2.689 ;
|
||||
; 31.906 ; CKE ; CKEout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 2.681 ;
|
||||
; 32.039 ; RA[9] ; RAr[9] ; C14M ; C14M ; 34.920 ; 0.000 ; 2.548 ;
|
||||
; 32.047 ; nRAS ; nRASout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 2.540 ;
|
||||
; 32.481 ; RA[10] ; RAr[10] ; C14M ; C14M ; 34.920 ; 0.000 ; 2.106 ;
|
||||
; 32.530 ; RA[8] ; RAr[8] ; C14M ; C14M ; 34.920 ; 0.000 ; 2.057 ;
|
||||
; 32.548 ; nCAS ; nCASout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 2.039 ;
|
||||
; 32.961 ; RA[3] ; RAr[3] ; C14M ; C14M ; 34.920 ; 0.000 ; 1.626 ;
|
||||
; 32.963 ; RA[2] ; RAr[2] ; C14M ; C14M ; 34.920 ; 0.000 ; 1.624 ;
|
||||
; 32.965 ; RA[4] ; RAr[4] ; C14M ; C14M ; 34.920 ; 0.000 ; 1.622 ;
|
||||
; 32.965 ; RA[7] ; RAr[7] ; C14M ; C14M ; 34.920 ; 0.000 ; 1.622 ;
|
||||
; 32.969 ; RA[6] ; RAr[6] ; C14M ; C14M ; 34.920 ; 0.000 ; 1.618 ;
|
||||
; 32.973 ; RA[0] ; RAr[0] ; C14M ; C14M ; 34.920 ; 0.000 ; 1.614 ;
|
||||
; 32.984 ; RA[1] ; RAr[1] ; C14M ; C14M ; 34.920 ; 0.000 ; 1.603 ;
|
||||
; 32.986 ; RA[5] ; RAr[5] ; C14M ; C14M ; 34.920 ; 0.000 ; 1.601 ;
|
||||
; 55.361 ; S[1] ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; C14M ; C14M ; 69.841 ; 0.000 ; 14.147 ;
|
||||
; 55.363 ; S[1] ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; C14M ; C14M ; 69.841 ; 0.000 ; 14.145 ;
|
||||
; 56.330 ; S[3] ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; C14M ; C14M ; 69.841 ; 0.000 ; 13.178 ;
|
||||
; 56.332 ; S[3] ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; C14M ; C14M ; 69.841 ; 0.000 ; 13.176 ;
|
||||
; 56.744 ; S[2] ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; C14M ; C14M ; 69.841 ; 0.000 ; 12.764 ;
|
||||
; 56.746 ; S[2] ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; C14M ; C14M ; 69.841 ; 0.000 ; 12.762 ;
|
||||
; 57.090 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; C14M ; C14M ; 69.841 ; 0.000 ; 12.418 ;
|
||||
; 57.090 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.418 ;
|
||||
; 57.092 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; C14M ; C14M ; 69.841 ; 0.000 ; 12.416 ;
|
||||
; 57.138 ; FS[3] ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; C14M ; C14M ; 69.841 ; 0.000 ; 12.370 ;
|
||||
; 57.138 ; FS[3] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.370 ;
|
||||
; 57.140 ; FS[3] ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; C14M ; C14M ; 69.841 ; 0.000 ; 12.368 ;
|
||||
; 57.222 ; FS[15] ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; C14M ; C14M ; 69.841 ; 0.000 ; 12.286 ;
|
||||
; 57.222 ; FS[15] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.286 ;
|
||||
; 57.224 ; S[1] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.284 ;
|
||||
; 57.224 ; FS[15] ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; C14M ; C14M ; 69.841 ; 0.000 ; 12.284 ;
|
||||
; 57.359 ; S[0] ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; C14M ; C14M ; 69.841 ; 0.000 ; 12.149 ;
|
||||
; 57.361 ; S[0] ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; C14M ; C14M ; 69.841 ; 0.000 ; 12.147 ;
|
||||
; 57.569 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.939 ;
|
||||
; 57.569 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.939 ;
|
||||
; 57.569 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.939 ;
|
||||
; 57.569 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.939 ;
|
||||
; 57.569 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.939 ;
|
||||
; 57.569 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.939 ;
|
||||
; 57.569 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.939 ;
|
||||
; 57.617 ; FS[3] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.891 ;
|
||||
; 57.617 ; FS[3] ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.891 ;
|
||||
; 57.617 ; FS[3] ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.891 ;
|
||||
; 57.617 ; FS[3] ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.891 ;
|
||||
; 57.617 ; FS[3] ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.891 ;
|
||||
; 57.617 ; FS[3] ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.891 ;
|
||||
; 57.617 ; FS[3] ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.891 ;
|
||||
+--------+-----------------------------------------------------------------------------------------------------------------+---------------------------------+------------------------+-------------+--------------+------------+------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Hold: 'ram2e_ufm|ARCLK|regout' ;
|
||||
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
||||
; -17.454 ; RAM2E_UFM:ram2e_ufm|ARShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M ; ram2e_ufm|ARCLK|regout ; 0.000 ; -0.997 ; 1.549 ;
|
||||
; 60.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 0.000 ; 0.000 ; 80.000 ;
|
||||
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Hold: 'ram2e_ufm|DRCLK|regout' ;
|
||||
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
||||
; -16.286 ; RAM2E_UFM:ram2e_ufm|DRDIn ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.000 ; -1.629 ; 2.085 ;
|
||||
; -16.276 ; RAM2E_UFM:ram2e_ufm|DRShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.000 ; -1.629 ; 2.095 ;
|
||||
; -16.306 ; RAM2E_UFM:ram2e_ufm|DRDIn ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.000 ; -2.165 ; 1.529 ;
|
||||
; -16.276 ; RAM2E_UFM:ram2e_ufm|DRShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.000 ; -2.165 ; 1.559 ;
|
||||
; 60.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; 0.000 ; 0.000 ; 80.000 ;
|
||||
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Hold: 'ram2e_ufm|ARCLK|regout' ;
|
||||
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
||||
; -16.256 ; RAM2E_UFM:ram2e_ufm|ARShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M ; ram2e_ufm|ARCLK|regout ; 0.000 ; -2.195 ; 1.549 ;
|
||||
; 60.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 0.000 ; 0.000 ; 80.000 ;
|
||||
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Hold: 'C14M' ;
|
||||
+-------+-----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+-------+-----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; 1.400 ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.621 ;
|
||||
; 1.409 ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.630 ;
|
||||
; 1.676 ; FS[0] ; FS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.897 ;
|
||||
; 1.685 ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.906 ;
|
||||
; 1.685 ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.906 ;
|
||||
; 1.689 ; Ready ; RDOE ; C14M ; C14M ; 0.000 ; 0.000 ; 1.910 ;
|
||||
; 1.706 ; CS[1] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.927 ;
|
||||
; 1.708 ; CS[1] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.929 ;
|
||||
; 1.708 ; CmdTout[0] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.929 ;
|
||||
; 1.709 ; CmdTout[0] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.930 ;
|
||||
; 1.722 ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; C14M ; C14M ; 0.000 ; 0.000 ; 1.943 ;
|
||||
; 1.759 ; CS[0] ; CS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.980 ;
|
||||
; 1.855 ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.076 ;
|
||||
; 1.898 ; RAM2E_UFM:ram2e_ufm|UFMProgram ; RAM2E_UFM:ram2e_ufm|UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 2.119 ;
|
||||
; 1.906 ; RWBank[1] ; RA[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.127 ;
|
||||
; 1.909 ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; C14M ; C14M ; 0.000 ; 0.000 ; 2.130 ;
|
||||
; 1.955 ; CmdTout[1] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.176 ;
|
||||
; 1.971 ; CS[2] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.192 ;
|
||||
; 1.981 ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 2.202 ;
|
||||
; 1.998 ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 2.219 ;
|
||||
; 2.014 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; C14M ; C14M ; 0.000 ; 0.000 ; 2.235 ;
|
||||
; 2.043 ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.264 ;
|
||||
; 2.087 ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.308 ;
|
||||
; 2.095 ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.316 ;
|
||||
; 2.107 ; PHI1r ; S[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.328 ;
|
||||
; 2.108 ; PHI1r ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.329 ;
|
||||
; 2.109 ; RWBank[7] ; RA[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.330 ;
|
||||
; 2.115 ; PHI1r ; S[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.336 ;
|
||||
; 2.115 ; PHI1r ; S[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.336 ;
|
||||
; 2.116 ; FS[8] ; FS[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.337 ;
|
||||
; 2.117 ; FS[15] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.338 ;
|
||||
; 2.117 ; RAM2E_UFM:ram2e_ufm|DRDIn ; RAM2E_UFM:ram2e_ufm|DRDIn ; C14M ; C14M ; 0.000 ; 0.000 ; 2.338 ;
|
||||
; 2.118 ; RAM2E_UFM:ram2e_ufm|DRCLKPulse ; RAM2E_UFM:ram2e_ufm|DRCLK ; C14M ; C14M ; 0.000 ; 0.000 ; 2.339 ;
|
||||
; 2.127 ; FS[7] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.348 ;
|
||||
; 1.408 ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.629 ;
|
||||
; 1.412 ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.633 ;
|
||||
; 1.428 ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.649 ;
|
||||
; 1.429 ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.650 ;
|
||||
; 1.659 ; Ready ; Ready ; C14M ; C14M ; 0.000 ; 0.000 ; 1.880 ;
|
||||
; 1.677 ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.898 ;
|
||||
; 1.686 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.907 ;
|
||||
; 1.704 ; S[0] ; S[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.925 ;
|
||||
; 1.718 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 1.939 ;
|
||||
; 1.720 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 1.941 ;
|
||||
; 1.723 ; CS[0] ; CS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.944 ;
|
||||
; 1.725 ; CS[0] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.946 ;
|
||||
; 1.732 ; CS[0] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.953 ;
|
||||
; 1.899 ; FS[0] ; FS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.120 ;
|
||||
; 1.909 ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; RWBank[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.130 ;
|
||||
; 1.959 ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 2.180 ;
|
||||
; 1.971 ; CmdTout[0] ; CmdTout[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.192 ;
|
||||
; 1.972 ; CmdTout[0] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.193 ;
|
||||
; 1.980 ; CmdTout[0] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.201 ;
|
||||
; 1.981 ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; C14M ; C14M ; 0.000 ; 0.000 ; 2.202 ;
|
||||
; 2.012 ; CS[1] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.233 ;
|
||||
; 2.036 ; CS[1] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.257 ;
|
||||
; 2.107 ; FS[7] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.328 ;
|
||||
; 2.112 ; RWBank[4] ; RA[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.333 ;
|
||||
; 2.121 ; RAM2E_UFM:ram2e_ufm|DRCLKPulse ; RAM2E_UFM:ram2e_ufm|DRCLK ; C14M ; C14M ; 0.000 ; 0.000 ; 2.342 ;
|
||||
; 2.127 ; FS[15] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.348 ;
|
||||
; 2.134 ; FS[8] ; FS[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.355 ;
|
||||
; 2.144 ; FS[5] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.365 ;
|
||||
; 2.151 ; FS[9] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.372 ;
|
||||
; 2.153 ; FS[10] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.374 ;
|
||||
; 2.159 ; FS[9] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.380 ;
|
||||
; 2.174 ; CmdTout[0] ; CmdTout[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.395 ;
|
||||
; 2.212 ; RAM2E_UFM:ram2e_ufm|LEDEN ; RAM2E_UFM:ram2e_ufm|LEDEN ; C14M ; C14M ; 0.000 ; 0.000 ; 2.433 ;
|
||||
; 2.221 ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; C14M ; C14M ; 0.000 ; 0.000 ; 2.442 ;
|
||||
; 2.221 ; RA[10] ; RA[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.442 ;
|
||||
; 2.225 ; CS[0] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.446 ;
|
||||
; 2.227 ; CS[0] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.448 ;
|
||||
; 2.232 ; FS[6] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.453 ;
|
||||
; 2.154 ; RAM2E_UFM:ram2e_ufm|UFMProgram ; RAM2E_UFM:ram2e_ufm|UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 2.375 ;
|
||||
; 2.212 ; RAM2E_UFM:ram2e_ufm|DRDIn ; RAM2E_UFM:ram2e_ufm|DRDIn ; C14M ; C14M ; 0.000 ; 0.000 ; 2.433 ;
|
||||
; 2.233 ; FS[11] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.454 ;
|
||||
; 2.239 ; FS[13] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.460 ;
|
||||
; 2.239 ; FS[14] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.460 ;
|
||||
; 2.240 ; FS[2] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.461 ;
|
||||
; 2.240 ; FS[4] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.461 ;
|
||||
; 2.242 ; FS[11] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.463 ;
|
||||
; 2.240 ; FS[1] ; FS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.461 ;
|
||||
; 2.242 ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; C14M ; C14M ; 0.000 ; 0.000 ; 2.463 ;
|
||||
; 2.248 ; FS[4] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.469 ;
|
||||
; 2.249 ; FS[2] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.470 ;
|
||||
; 2.249 ; CmdTout[2] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.470 ;
|
||||
; 2.250 ; FS[12] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.471 ;
|
||||
; 2.252 ; FS[3] ; FS[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.473 ;
|
||||
; 2.260 ; CmdTout[2] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.481 ;
|
||||
; 2.261 ; Ready ; Ready ; C14M ; C14M ; 0.000 ; 0.000 ; 2.482 ;
|
||||
; 2.272 ; CmdTout[1] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.493 ;
|
||||
; 2.319 ; RWBank[6] ; BA[1]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 2.540 ;
|
||||
; 2.333 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 2.554 ;
|
||||
; 2.342 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 2.563 ;
|
||||
; 2.352 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.573 ;
|
||||
; 2.380 ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.601 ;
|
||||
; 2.521 ; S[0] ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.742 ;
|
||||
; 2.523 ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.744 ;
|
||||
; 2.603 ; RAM2E_UFM:ram2e_ufm|CmdBitbangMAX ; RAM2E_UFM:ram2e_ufm|DRCLKPulse ; C14M ; C14M ; 0.000 ; 0.000 ; 2.824 ;
|
||||
; 2.604 ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.825 ;
|
||||
; 2.660 ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.881 ;
|
||||
; 2.727 ; RWSel ; RWSel ; C14M ; C14M ; 0.000 ; 0.000 ; 2.948 ;
|
||||
; 2.775 ; FS[11] ; RA[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.996 ;
|
||||
; 2.788 ; S[2] ; CKE ; C14M ; C14M ; 0.000 ; 0.000 ; 3.009 ;
|
||||
; 2.805 ; S[2] ; DOEEN ; C14M ; C14M ; 0.000 ; 0.000 ; 3.026 ;
|
||||
; 2.809 ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.030 ;
|
||||
; 2.889 ; S[3] ; DQML~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.110 ;
|
||||
; 2.890 ; RWBank[5] ; BA[0]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.111 ;
|
||||
; 2.891 ; S[3] ; DQMH~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.112 ;
|
||||
; 2.909 ; FS[13] ; RA[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.130 ;
|
||||
; 2.948 ; FS[8] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.169 ;
|
||||
; 2.969 ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; RAM2E_UFM:ram2e_ufm|UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 3.190 ;
|
||||
; 2.262 ; FS[6] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.483 ;
|
||||
; 2.270 ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 2.491 ;
|
||||
; 2.271 ; CmdTout[1] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.492 ;
|
||||
; 2.273 ; FS[3] ; FS[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.494 ;
|
||||
; 2.275 ; S[0] ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.496 ;
|
||||
; 2.282 ; S[0] ; nCAS ; C14M ; C14M ; 0.000 ; 0.000 ; 2.503 ;
|
||||
; 2.308 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; C14M ; C14M ; 0.000 ; 0.000 ; 2.529 ;
|
||||
; 2.351 ; S[3] ; S[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.572 ;
|
||||
; 2.357 ; CS[2] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.578 ;
|
||||
; 2.478 ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; RWBank[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.699 ;
|
||||
; 2.532 ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; RWBank[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.753 ;
|
||||
; 2.536 ; CmdTout[1] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.757 ;
|
||||
; 2.541 ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.762 ;
|
||||
; 2.547 ; RWBank[6] ; BA[1]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 2.768 ;
|
||||
; 2.564 ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; C14M ; C14M ; 0.000 ; 0.000 ; 2.785 ;
|
||||
; 2.566 ; PHI1r ; S[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.787 ;
|
||||
; 2.573 ; PHI1r ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.794 ;
|
||||
; 2.600 ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; RWBank[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.821 ;
|
||||
; 2.607 ; S[1] ; S[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.828 ;
|
||||
; 2.609 ; PHI1r ; S[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.830 ;
|
||||
; 2.614 ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.835 ;
|
||||
; 2.616 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.837 ;
|
||||
; 2.635 ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.856 ;
|
||||
; 2.651 ; RA[10] ; RA[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.872 ;
|
||||
; 2.663 ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.884 ;
|
||||
; 2.666 ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.887 ;
|
||||
; 2.667 ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.888 ;
|
||||
; 2.673 ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.894 ;
|
||||
; 2.691 ; RAM2E_UFM:ram2e_ufm|CmdBitbangMAX ; RAM2E_UFM:ram2e_ufm|DRCLKPulse ; C14M ; C14M ; 0.000 ; 0.000 ; 2.912 ;
|
||||
; 2.710 ; RWSel ; RWSel ; C14M ; C14M ; 0.000 ; 0.000 ; 2.931 ;
|
||||
; 2.721 ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; RWBank[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.942 ;
|
||||
; 2.764 ; FS[14] ; RA[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.985 ;
|
||||
; 2.774 ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; RWBank[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.995 ;
|
||||
; 2.798 ; RWSel ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.019 ;
|
||||
; 2.804 ; RWSel ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.025 ;
|
||||
; 2.809 ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.030 ;
|
||||
; 2.818 ; FS[4] ; RA[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.039 ;
|
||||
; 2.833 ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.054 ;
|
||||
; 2.899 ; FS[13] ; RA[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.120 ;
|
||||
; 2.966 ; FS[8] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.187 ;
|
||||
; 2.976 ; FS[5] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.197 ;
|
||||
; 2.976 ; FS[11] ; RA[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.197 ;
|
||||
; 2.983 ; FS[9] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.204 ;
|
||||
; 2.985 ; FS[10] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.206 ;
|
||||
; 2.985 ; FS[4] ; RA[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.206 ;
|
||||
; 2.991 ; FS[9] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.212 ;
|
||||
; 3.008 ; RWBank[4] ; RA[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.229 ;
|
||||
; 3.028 ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; RWBank[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.249 ;
|
||||
; 3.049 ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; RWBank[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.270 ;
|
||||
; 3.052 ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.273 ;
|
||||
; 3.059 ; FS[8] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.280 ;
|
||||
; 3.075 ; RWBank[2] ; RA[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.296 ;
|
||||
; 2.991 ; S[3] ; CKE ; C14M ; C14M ; 0.000 ; 0.000 ; 3.212 ;
|
||||
; 3.009 ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; RAM2E_UFM:ram2e_ufm|UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 3.230 ;
|
||||
; 3.013 ; FS[15] ; DQML~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.234 ;
|
||||
; 3.015 ; FS[15] ; DQMH~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.236 ;
|
||||
; 3.017 ; S[1] ; nRWE ; C14M ; C14M ; 0.000 ; 0.000 ; 3.238 ;
|
||||
; 3.020 ; FS[10] ; RA[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.241 ;
|
||||
; 3.060 ; RAM2E_UFM:ram2e_ufm|LEDEN ; RAM2E_UFM:ram2e_ufm|LEDEN ; C14M ; C14M ; 0.000 ; 0.000 ; 3.281 ;
|
||||
; 3.077 ; FS[8] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.298 ;
|
||||
; 3.087 ; FS[5] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.308 ;
|
||||
; 3.094 ; FS[9] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.315 ;
|
||||
; 3.096 ; FS[10] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.317 ;
|
||||
; 3.098 ; S[2] ; nRWE ; C14M ; C14M ; 0.000 ; 0.000 ; 3.319 ;
|
||||
; 3.099 ; RWSel ; RAM2E_UFM:ram2e_ufm|DRCLKPulse ; C14M ; C14M ; 0.000 ; 0.000 ; 3.320 ;
|
||||
; 3.102 ; FS[9] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.323 ;
|
||||
; 3.112 ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; RAM2E_UFM:ram2e_ufm|LEDEN ; C14M ; C14M ; 0.000 ; 0.000 ; 3.333 ;
|
||||
; 3.120 ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.341 ;
|
||||
; 3.145 ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; RWBank[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.366 ;
|
||||
; 3.156 ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; RWBank[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.377 ;
|
||||
; 3.170 ; FS[8] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.391 ;
|
||||
; 3.172 ; FS[6] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.393 ;
|
||||
; 3.179 ; FS[14] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.400 ;
|
||||
; 3.179 ; FS[1] ; FS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.400 ;
|
||||
; 3.179 ; FS[13] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.400 ;
|
||||
; 3.180 ; FS[4] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.401 ;
|
||||
; 3.124 ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.345 ;
|
||||
; 3.136 ; S[0] ; DQML~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.357 ;
|
||||
; 3.142 ; S[0] ; DQMH~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.363 ;
|
||||
; 3.145 ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.366 ;
|
||||
+-------+-----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
|
||||
|
||||
@ -428,7 +429,7 @@ No paths to report.
|
||||
+------------------------+------------------------+----------+----------+----------+----------+
|
||||
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
|
||||
+------------------------+------------------------+----------+----------+----------+----------+
|
||||
; C14M ; C14M ; 1539 ; 0 ; 56 ; 0 ;
|
||||
; C14M ; C14M ; 1532 ; 0 ; 56 ; 0 ;
|
||||
; ram2e_ufm|DRCLK|regout ; C14M ; 13 ; 0 ; 0 ; 0 ;
|
||||
; C14M ; ram2e_ufm|ARCLK|regout ; 1 ; 0 ; 0 ; 0 ;
|
||||
; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 1 ; 0 ; 0 ; 0 ;
|
||||
@ -443,7 +444,7 @@ Entries labeled "false path" only account for clock-to-clock false paths and not
|
||||
+------------------------+------------------------+----------+----------+----------+----------+
|
||||
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
|
||||
+------------------------+------------------------+----------+----------+----------+----------+
|
||||
; C14M ; C14M ; 1539 ; 0 ; 56 ; 0 ;
|
||||
; C14M ; C14M ; 1532 ; 0 ; 56 ; 0 ;
|
||||
; ram2e_ufm|DRCLK|regout ; C14M ; 13 ; 0 ; 0 ; 0 ;
|
||||
; C14M ; ram2e_ufm|ARCLK|regout ; 1 ; 0 ; 0 ; 0 ;
|
||||
; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 1 ; 0 ; 0 ; 0 ;
|
||||
@ -473,7 +474,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
||||
; Illegal Clocks ; 0 ; 0 ;
|
||||
; Unconstrained Clocks ; 1 ; 1 ;
|
||||
; Unconstrained Input Ports ; 28 ; 28 ;
|
||||
; Unconstrained Input Port Paths ; 169 ; 169 ;
|
||||
; Unconstrained Input Port Paths ; 161 ; 161 ;
|
||||
; Unconstrained Output Ports ; 47 ; 47 ;
|
||||
; Unconstrained Output Port Paths ; 83 ; 83 ;
|
||||
+---------------------------------+-------+------+
|
||||
@ -679,7 +680,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime Timing Analyzer
|
||||
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Info: Processing started: Sat Jun 08 01:44:23 2024
|
||||
Info: Processing started: Fri Jul 12 16:09:19 2024
|
||||
Info: Command: quartus_sta RAM2E-MAXII -c RAM2E
|
||||
Info: qsta_default_script.tcl version: #1
|
||||
Info (20032): Parallel compilation is enabled and will use up to 4 processors
|
||||
@ -696,18 +697,18 @@ Info: Can't run Report Timing Closure Recommendations. The current device family
|
||||
Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ram2e_ufm|ARCLK|regout are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
|
||||
Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ram2e_ufm|DRCLK|regout are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
|
||||
Critical Warning (332148): Timing requirements not met
|
||||
Info (332146): Worst-case setup slack is -23.723
|
||||
Info (332146): Worst-case setup slack is -23.743
|
||||
Info (332119): Slack End Point TNS Clock
|
||||
Info (332119): ========= =================== =====================
|
||||
Info (332119): -23.743 -23.743 ram2e_ufm|ARCLK|regout
|
||||
Info (332119): -23.723 -23.723 ram2e_ufm|DRCLK|regout
|
||||
Info (332119): -22.545 -22.545 ram2e_ufm|ARCLK|regout
|
||||
Info (332119): -8.511 -94.827 C14M
|
||||
Info (332146): Worst-case hold slack is -17.454
|
||||
Info (332119): -8.564 -94.357 C14M
|
||||
Info (332146): Worst-case hold slack is -16.306
|
||||
Info (332119): Slack End Point TNS Clock
|
||||
Info (332119): ========= =================== =====================
|
||||
Info (332119): -17.454 -17.454 ram2e_ufm|ARCLK|regout
|
||||
Info (332119): -16.286 -16.286 ram2e_ufm|DRCLK|regout
|
||||
Info (332119): 1.400 0.000 C14M
|
||||
Info (332119): -16.306 -16.306 ram2e_ufm|DRCLK|regout
|
||||
Info (332119): -16.256 -16.256 ram2e_ufm|ARCLK|regout
|
||||
Info (332119): 1.408 0.000 C14M
|
||||
Info (332140): No Recovery paths to report
|
||||
Info (332140): No Removal paths to report
|
||||
Info (332146): Worst-case minimum pulse width slack is 34.654
|
||||
@ -720,9 +721,9 @@ Info (332001): The selected device family is not supported by the report_metasta
|
||||
Info (332102): Design is not fully constrained for setup requirements
|
||||
Info (332102): Design is not fully constrained for hold requirements
|
||||
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 4 warnings
|
||||
Info: Peak virtual memory: 13094 megabytes
|
||||
Info: Processing ended: Sat Jun 08 01:44:25 2024
|
||||
Info: Peak virtual memory: 13093 megabytes
|
||||
Info: Processing ended: Fri Jul 12 16:09:21 2024
|
||||
Info: Elapsed time: 00:00:02
|
||||
Info: Total CPU time (on all processors): 00:00:02
|
||||
Info: Total CPU time (on all processors): 00:00:01
|
||||
|
||||
|
||||
|
||||
@ -2,28 +2,28 @@
|
||||
Timing Analyzer Summary
|
||||
------------------------------------------------------------
|
||||
|
||||
Type : Setup 'ram2e_ufm|ARCLK|regout'
|
||||
Slack : -23.743
|
||||
TNS : -23.743
|
||||
|
||||
Type : Setup 'ram2e_ufm|DRCLK|regout'
|
||||
Slack : -23.723
|
||||
TNS : -23.723
|
||||
|
||||
Type : Setup 'ram2e_ufm|ARCLK|regout'
|
||||
Slack : -22.545
|
||||
TNS : -22.545
|
||||
|
||||
Type : Setup 'C14M'
|
||||
Slack : -8.511
|
||||
TNS : -94.827
|
||||
|
||||
Type : Hold 'ram2e_ufm|ARCLK|regout'
|
||||
Slack : -17.454
|
||||
TNS : -17.454
|
||||
Slack : -8.564
|
||||
TNS : -94.357
|
||||
|
||||
Type : Hold 'ram2e_ufm|DRCLK|regout'
|
||||
Slack : -16.286
|
||||
TNS : -16.286
|
||||
Slack : -16.306
|
||||
TNS : -16.306
|
||||
|
||||
Type : Hold 'ram2e_ufm|ARCLK|regout'
|
||||
Slack : -16.256
|
||||
TNS : -16.256
|
||||
|
||||
Type : Hold 'C14M'
|
||||
Slack : 1.400
|
||||
Slack : 1.408
|
||||
TNS : 0.000
|
||||
|
||||
Type : Minimum Pulse Width 'C14M'
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,5 +1,5 @@
|
||||
Assembler report for RAM2E
|
||||
Sat Jun 08 01:44:21 2024
|
||||
Fri Jul 12 16:08:53 2024
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
|
||||
|
||||
@ -39,7 +39,7 @@ https://fpgasoftware.intel.com/eula.
|
||||
+---------------------------------------------------------------+
|
||||
; Assembler Summary ;
|
||||
+-----------------------+---------------------------------------+
|
||||
; Assembler Status ; Successful - Sat Jun 08 01:44:21 2024 ;
|
||||
; Assembler Status ; Successful - Fri Jul 12 16:08:53 2024 ;
|
||||
; Revision Name ; RAM2E ;
|
||||
; Top-level Entity Name ; RAM2E ;
|
||||
; Family ; MAX II ;
|
||||
@ -69,8 +69,8 @@ https://fpgasoftware.intel.com/eula.
|
||||
+----------------+---------------------------------------------------------+
|
||||
; Option ; Setting ;
|
||||
+----------------+---------------------------------------------------------+
|
||||
; JTAG usercode ; 0x00164419 ;
|
||||
; Checksum ; 0x00164899 ;
|
||||
; JTAG usercode ; 0x001661B2 ;
|
||||
; Checksum ; 0x00166532 ;
|
||||
+----------------+---------------------------------------------------------+
|
||||
|
||||
|
||||
@ -89,14 +89,14 @@ https://fpgasoftware.intel.com/eula.
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime Assembler
|
||||
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Info: Processing started: Sat Jun 08 01:44:20 2024
|
||||
Info: Processing started: Fri Jul 12 16:08:48 2024
|
||||
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2E-MAXII -c RAM2E
|
||||
Info (115031): Writing out detailed assembly data for power analysis
|
||||
Info (115030): Assembler is generating device programming files
|
||||
Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings
|
||||
Info: Peak virtual memory: 13099 megabytes
|
||||
Info: Processing ended: Sat Jun 08 01:44:21 2024
|
||||
Info: Elapsed time: 00:00:01
|
||||
Info: Peak virtual memory: 13098 megabytes
|
||||
Info: Processing ended: Fri Jul 12 16:08:53 2024
|
||||
Info: Elapsed time: 00:00:05
|
||||
Info: Total CPU time (on all processors): 00:00:01
|
||||
|
||||
|
||||
|
||||
@ -1 +1 @@
|
||||
Sat Jun 08 01:44:26 2024
|
||||
Fri Jul 12 16:09:07 2024
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
Fitter report for RAM2E
|
||||
Sat Jun 08 01:44:18 2024
|
||||
Fri Jul 12 16:08:41 2024
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
|
||||
|
||||
@ -57,14 +57,14 @@ https://fpgasoftware.intel.com/eula.
|
||||
+---------------------------------------------------------------------+
|
||||
; Fitter Summary ;
|
||||
+-----------------------+---------------------------------------------+
|
||||
; Fitter Status ; Successful - Sat Jun 08 01:44:18 2024 ;
|
||||
; Fitter Status ; Successful - Fri Jul 12 16:08:41 2024 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
||||
; Revision Name ; RAM2E ;
|
||||
; Top-level Entity Name ; RAM2E ;
|
||||
; Family ; MAX II ;
|
||||
; Device ; EPM240T100C5 ;
|
||||
; Timing Models ; Final ;
|
||||
; Total logic elements ; 238 / 240 ( 99 % ) ;
|
||||
; Total logic elements ; 233 / 240 ( 97 % ) ;
|
||||
; Total pins ; 71 / 80 ( 89 % ) ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 1 / 1 ( 100 % ) ;
|
||||
@ -129,13 +129,12 @@ https://fpgasoftware.intel.com/eula.
|
||||
; Number detected on machine ; 4 ;
|
||||
; Maximum allowed ; 4 ;
|
||||
; ; ;
|
||||
; Average used ; 1.03 ;
|
||||
; Average used ; 1.01 ;
|
||||
; Maximum used ; 4 ;
|
||||
; ; ;
|
||||
; Usage by Processor ; % Time Used ;
|
||||
; Processor 1 ; 100.0% ;
|
||||
; Processor 2 ; 0.9% ;
|
||||
; Processors 3-4 ; 0.9% ;
|
||||
; Processors 2-4 ; 0.3% ;
|
||||
+----------------------------+-------------+
|
||||
|
||||
|
||||
@ -150,27 +149,27 @@ The pin-out file can be found in /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pin.
|
||||
+---------------------------------------------+-----------------------+
|
||||
; Resource ; Usage ;
|
||||
+---------------------------------------------+-----------------------+
|
||||
; Total logic elements ; 238 / 240 ( 99 % ) ;
|
||||
; -- Combinational with no register ; 112 ;
|
||||
; Total logic elements ; 233 / 240 ( 97 % ) ;
|
||||
; -- Combinational with no register ; 108 ;
|
||||
; -- Register only ; 19 ;
|
||||
; -- Combinational with a register ; 107 ;
|
||||
; -- Combinational with a register ; 106 ;
|
||||
; ; ;
|
||||
; Logic element usage by number of LUT inputs ; ;
|
||||
; -- 4 input functions ; 116 ;
|
||||
; -- 3 input functions ; 53 ;
|
||||
; -- 2 input functions ; 46 ;
|
||||
; -- 4 input functions ; 111 ;
|
||||
; -- 3 input functions ; 56 ;
|
||||
; -- 2 input functions ; 43 ;
|
||||
; -- 1 input functions ; 3 ;
|
||||
; -- 0 input functions ; 1 ;
|
||||
; ; ;
|
||||
; Logic elements by mode ; ;
|
||||
; -- normal mode ; 224 ;
|
||||
; -- normal mode ; 219 ;
|
||||
; -- arithmetic mode ; 14 ;
|
||||
; -- qfbk mode ; 14 ;
|
||||
; -- register cascade mode ; 0 ;
|
||||
; -- synchronous clear/load mode ; 26 ;
|
||||
; -- synchronous clear/load mode ; 25 ;
|
||||
; -- asynchronous clear/load mode ; 0 ;
|
||||
; ; ;
|
||||
; Total registers ; 126 / 240 ( 53 % ) ;
|
||||
; Total registers ; 125 / 240 ( 52 % ) ;
|
||||
; Total LABs ; 24 / 24 ( 100 % ) ;
|
||||
; Logic elements in carry chains ; 15 ;
|
||||
; Virtual pins ; 0 ;
|
||||
@ -185,12 +184,12 @@ The pin-out file can be found in /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pin.
|
||||
; Global signals ; 2 ;
|
||||
; -- Global clocks ; 2 / 4 ( 50 % ) ;
|
||||
; JTAGs ; 0 / 1 ( 0 % ) ;
|
||||
; Average interconnect usage (total/H/V) ; 30.7% / 34.1% / 27.1% ;
|
||||
; Peak interconnect usage (total/H/V) ; 30.7% / 34.1% / 27.1% ;
|
||||
; Maximum fan-out ; 122 ;
|
||||
; Average interconnect usage (total/H/V) ; 27.3% / 28.5% / 26.1% ;
|
||||
; Peak interconnect usage (total/H/V) ; 27.3% / 28.5% / 26.1% ;
|
||||
; Maximum fan-out ; 121 ;
|
||||
; Highest non-global fan-out ; 34 ;
|
||||
; Total fan-out ; 992 ;
|
||||
; Average fan-out ; 3.20 ;
|
||||
; Total fan-out ; 973 ;
|
||||
; Average fan-out ; 3.19 ;
|
||||
+---------------------------------------------+-----------------------+
|
||||
|
||||
|
||||
@ -207,16 +206,16 @@ The pin-out file can be found in /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pin.
|
||||
; Ain[5] ; 34 ; 1 ; 3 ; 0 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Ain[6] ; 39 ; 1 ; 5 ; 0 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Ain[7] ; 53 ; 2 ; 8 ; 1 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; C14M ; 12 ; 1 ; 1 ; 3 ; 3 ; 122 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; C14M ; 12 ; 1 ; 1 ; 3 ; 3 ; 121 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[0] ; 38 ; 1 ; 4 ; 0 ; 0 ; 15 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[1] ; 40 ; 1 ; 5 ; 0 ; 2 ; 11 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[2] ; 42 ; 1 ; 5 ; 0 ; 0 ; 13 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[3] ; 41 ; 1 ; 5 ; 0 ; 1 ; 13 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[4] ; 48 ; 1 ; 6 ; 0 ; 0 ; 10 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[1] ; 40 ; 1 ; 5 ; 0 ; 2 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[2] ; 42 ; 1 ; 5 ; 0 ; 0 ; 11 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[3] ; 41 ; 1 ; 5 ; 0 ; 1 ; 11 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[4] ; 48 ; 1 ; 6 ; 0 ; 0 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[5] ; 49 ; 1 ; 7 ; 0 ; 2 ; 9 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[6] ; 36 ; 1 ; 4 ; 0 ; 2 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[7] ; 35 ; 1 ; 3 ; 0 ; 0 ; 10 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; PHI1 ; 37 ; 1 ; 4 ; 0 ; 1 ; 5 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[6] ; 36 ; 1 ; 4 ; 0 ; 2 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[7] ; 35 ; 1 ; 3 ; 0 ; 0 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; PHI1 ; 37 ; 1 ; 4 ; 0 ; 1 ; 6 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; nC07X ; 52 ; 2 ; 8 ; 1 ; 4 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; nEN80 ; 28 ; 1 ; 2 ; 0 ; 1 ; 10 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; nWE ; 51 ; 1 ; 7 ; 0 ; 0 ; 9 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
@ -233,7 +232,7 @@ The pin-out file can be found in /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pin.
|
||||
; BA[1] ; 14 ; 1 ; 1 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; CKEout ; 4 ; 1 ; 1 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; DQMH ; 100 ; 2 ; 2 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; DQML ; 98 ; 2 ; 2 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; DQML ; 98 ; 2 ; 2 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; Dout[0] ; 77 ; 2 ; 7 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; Dout[1] ; 76 ; 2 ; 7 ; 5 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; Dout[2] ; 74 ; 2 ; 8 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
@ -255,15 +254,15 @@ The pin-out file can be found in /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pin.
|
||||
; RAout[7] ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; RAout[8] ; 17 ; 1 ; 1 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RAout[9] ; 15 ; 1 ; 1 ; 2 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[0] ; 70 ; 2 ; 8 ; 4 ; 4 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; Vout[0] ; 70 ; 2 ; 8 ; 4 ; 4 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[1] ; 67 ; 2 ; 8 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[2] ; 69 ; 2 ; 8 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; Vout[3] ; 62 ; 2 ; 8 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; Vout[2] ; 69 ; 2 ; 8 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[3] ; 62 ; 2 ; 8 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[4] ; 71 ; 2 ; 8 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[5] ; 68 ; 2 ; 8 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[6] ; 58 ; 2 ; 8 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[7] ; 57 ; 2 ; 8 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; nCASout ; 3 ; 1 ; 1 ; 4 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; nCASout ; 3 ; 1 ; 1 ; 4 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; nCSout ; 8 ; 1 ; 1 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; nDHGROE ; 87 ; 2 ; 5 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; nDOE ; 55 ; 2 ; 8 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
@ -279,7 +278,7 @@ The pin-out file can be found in /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pin.
|
||||
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
|
||||
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
|
||||
; RD[0] ; 97 ; 2 ; 3 ; 5 ; 3 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ;
|
||||
; RD[1] ; 90 ; 2 ; 4 ; 5 ; 1 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ;
|
||||
; RD[1] ; 90 ; 2 ; 4 ; 5 ; 1 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; RDOE ; - ;
|
||||
; RD[2] ; 99 ; 2 ; 2 ; 5 ; 1 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ;
|
||||
; RD[3] ; 89 ; 2 ; 4 ; 5 ; 0 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ;
|
||||
; RD[4] ; 91 ; 2 ; 4 ; 5 ; 2 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ;
|
||||
@ -429,7 +428,7 @@ Note: User assignments will override these defaults. The user specified values a
|
||||
+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
|
||||
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
|
||||
+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
|
||||
; |RAM2E ; 238 (182) ; 126 ; 1 ; 71 ; 0 ; 112 (88) ; 19 (16) ; 107 (78) ; 15 (15) ; 14 (9) ; |RAM2E ; RAM2E ; work ;
|
||||
; |RAM2E ; 233 (177) ; 125 ; 1 ; 71 ; 0 ; 108 (84) ; 19 (16) ; 106 (77) ; 15 (15) ; 14 (9) ; |RAM2E ; RAM2E ; work ;
|
||||
; |RAM2E_UFM:ram2e_ufm| ; 56 (56) ; 32 ; 1 ; 0 ; 0 ; 24 (24) ; 3 (3) ; 29 (29) ; 0 (0) ; 5 (5) ; |RAM2E|RAM2E_UFM:ram2e_ufm ; RAM2E_UFM ; work ;
|
||||
; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst ; UFM ; work ;
|
||||
; |UFM_altufm_none_lbr:UFM_altufm_none_lbr_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component ; UFM_altufm_none_lbr ; work ;
|
||||
@ -510,8 +509,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
; Din[5] ; Input ; (0) ;
|
||||
; Din[7] ; Input ; (0) ;
|
||||
; Din[4] ; Input ; (0) ;
|
||||
; Din[2] ; Input ; (0) ;
|
||||
; Din[3] ; Input ; (0) ;
|
||||
; Din[2] ; Input ; (0) ;
|
||||
; nC07X ; Input ; (0) ;
|
||||
+-----------+----------+---------------+
|
||||
|
||||
@ -521,22 +520,22 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
+--------------------------------+-------------+---------+---------------+--------+----------------------+------------------+
|
||||
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
|
||||
+--------------------------------+-------------+---------+---------------+--------+----------------------+------------------+
|
||||
; BA[0]~0 ; LC_X2_Y3_N0 ; 2 ; Clock enable ; no ; -- ; -- ;
|
||||
; BA[0]~1 ; LC_X3_Y3_N0 ; 3 ; Clock enable ; no ; -- ; -- ;
|
||||
; C14M ; PIN_12 ; 122 ; Clock ; yes ; Global Clock ; GCLK0 ;
|
||||
; CS[0]~2 ; LC_X4_Y1_N1 ; 3 ; Clock enable ; no ; -- ; -- ;
|
||||
; DQML~0 ; LC_X2_Y4_N8 ; 2 ; Clock enable ; no ; -- ; -- ;
|
||||
; Equal1~1 ; LC_X2_Y2_N5 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; Equal1~2 ; LC_X5_Y3_N5 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; Mux14~0 ; LC_X5_Y2_N8 ; 2 ; Clock enable ; no ; -- ; -- ;
|
||||
; PHI1 ; PIN_37 ; 5 ; Clock ; yes ; Global Clock ; GCLK3 ;
|
||||
; RAM2E_UFM:ram2e_ufm|RWMask~1 ; LC_X2_Y1_N9 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; RAM2E_UFM:ram2e_ufm|UFMD[15]~1 ; LC_X7_Y4_N8 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; RAM2E_UFM:ram2e_ufm|always2~8 ; LC_X4_Y1_N4 ; 16 ; Clock enable ; no ; -- ; -- ;
|
||||
; RA[1]~2 ; LC_X5_Y3_N0 ; 6 ; Clock enable ; no ; -- ; -- ;
|
||||
; RDOE ; LC_X7_Y3_N9 ; 8 ; Output enable ; no ; -- ; -- ;
|
||||
; S[0] ; LC_X4_Y4_N4 ; 32 ; Sync. clear ; no ; -- ; -- ;
|
||||
; S[3] ; LC_X4_Y4_N7 ; 34 ; Sync. clear ; no ; -- ; -- ;
|
||||
; BA[0]~0 ; LC_X2_Y2_N7 ; 2 ; Clock enable ; no ; -- ; -- ;
|
||||
; BA[0]~1 ; LC_X4_Y2_N1 ; 3 ; Clock enable ; no ; -- ; -- ;
|
||||
; C14M ; PIN_12 ; 121 ; Clock ; yes ; Global Clock ; GCLK0 ;
|
||||
; CS[0]~2 ; LC_X6_Y1_N5 ; 3 ; Clock enable ; no ; -- ; -- ;
|
||||
; DQMH~0 ; LC_X2_Y4_N0 ; 2 ; Clock enable ; no ; -- ; -- ;
|
||||
; Equal1~1 ; LC_X2_Y2_N0 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; Equal1~2 ; LC_X7_Y2_N5 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; Mux14~0 ; LC_X2_Y3_N9 ; 2 ; Clock enable ; no ; -- ; -- ;
|
||||
; PHI1 ; PIN_37 ; 6 ; Clock ; yes ; Global Clock ; GCLK3 ;
|
||||
; RAM2E_UFM:ram2e_ufm|RWMask~1 ; LC_X4_Y1_N9 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; RAM2E_UFM:ram2e_ufm|UFMD[15]~1 ; LC_X2_Y1_N0 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; RAM2E_UFM:ram2e_ufm|always2~8 ; LC_X5_Y1_N3 ; 15 ; Clock enable ; no ; -- ; -- ;
|
||||
; RA[2]~2 ; LC_X2_Y3_N8 ; 6 ; Clock enable ; no ; -- ; -- ;
|
||||
; RDOE ; LC_X3_Y2_N4 ; 8 ; Output enable ; no ; -- ; -- ;
|
||||
; S[0] ; LC_X3_Y4_N8 ; 32 ; Sync. clear ; no ; -- ; -- ;
|
||||
; S[3] ; LC_X3_Y4_N7 ; 34 ; Sync. clear ; no ; -- ; -- ;
|
||||
+--------------------------------+-------------+---------+---------------+--------+----------------------+------------------+
|
||||
|
||||
|
||||
@ -545,8 +544,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
+------+----------+---------+----------------------+------------------+
|
||||
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
|
||||
+------+----------+---------+----------------------+------------------+
|
||||
; C14M ; PIN_12 ; 122 ; Global Clock ; GCLK0 ;
|
||||
; PHI1 ; PIN_37 ; 5 ; Global Clock ; GCLK3 ;
|
||||
; C14M ; PIN_12 ; 121 ; Global Clock ; GCLK0 ;
|
||||
; PHI1 ; PIN_37 ; 6 ; Global Clock ; GCLK3 ;
|
||||
+------+----------+---------+----------------------+------------------+
|
||||
|
||||
|
||||
@ -555,86 +554,85 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
+-----------------------+--------------------+
|
||||
; Routing Resource Type ; Usage ;
|
||||
+-----------------------+--------------------+
|
||||
; C4s ; 169 / 784 ( 22 % ) ;
|
||||
; Direct links ; 50 / 888 ( 6 % ) ;
|
||||
; C4s ; 158 / 784 ( 20 % ) ;
|
||||
; Direct links ; 61 / 888 ( 7 % ) ;
|
||||
; Global clocks ; 2 / 4 ( 50 % ) ;
|
||||
; LAB clocks ; 7 / 32 ( 22 % ) ;
|
||||
; LUT chains ; 11 / 216 ( 5 % ) ;
|
||||
; Local interconnects ; 353 / 888 ( 40 % ) ;
|
||||
; R4s ; 190 / 704 ( 27 % ) ;
|
||||
; LUT chains ; 8 / 216 ( 4 % ) ;
|
||||
; Local interconnects ; 335 / 888 ( 38 % ) ;
|
||||
; R4s ; 157 / 704 ( 22 % ) ;
|
||||
+-----------------------+--------------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------+
|
||||
; LAB Logic Elements ;
|
||||
+--------------------------------------------+------------------------------+
|
||||
; Number of Logic Elements (Average = 9.92) ; Number of LABs (Total = 24) ;
|
||||
; Number of Logic Elements (Average = 9.71) ; Number of LABs (Total = 24) ;
|
||||
+--------------------------------------------+------------------------------+
|
||||
; 1 ; 0 ;
|
||||
; 2 ; 0 ;
|
||||
; 3 ; 0 ;
|
||||
; 4 ; 0 ;
|
||||
; 4 ; 1 ;
|
||||
; 5 ; 0 ;
|
||||
; 6 ; 0 ;
|
||||
; 7 ; 0 ;
|
||||
; 8 ; 1 ;
|
||||
; 9 ; 0 ;
|
||||
; 10 ; 23 ;
|
||||
; 8 ; 0 ;
|
||||
; 9 ; 1 ;
|
||||
; 10 ; 22 ;
|
||||
+--------------------------------------------+------------------------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------+
|
||||
; LAB-wide Signals ;
|
||||
+------------------------------------+------------------------------+
|
||||
; LAB-wide Signals (Average = 1.38) ; Number of LABs (Total = 24) ;
|
||||
; LAB-wide Signals (Average = 1.58) ; Number of LABs (Total = 24) ;
|
||||
+------------------------------------+------------------------------+
|
||||
; 1 Clock ; 22 ;
|
||||
; 1 Clock enable ; 8 ;
|
||||
; 1 Clock ; 24 ;
|
||||
; 1 Clock enable ; 13 ;
|
||||
; 1 Sync. clear ; 1 ;
|
||||
; 2 Clock enables ; 2 ;
|
||||
+------------------------------------+------------------------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------------+
|
||||
; LAB Signals Sourced ;
|
||||
+----------------------------------------------+------------------------------+
|
||||
; Number of Signals Sourced (Average = 10.13) ; Number of LABs (Total = 24) ;
|
||||
+----------------------------------------------+------------------------------+
|
||||
; 0 ; 0 ;
|
||||
; 1 ; 0 ;
|
||||
; 2 ; 0 ;
|
||||
; 3 ; 0 ;
|
||||
; 4 ; 0 ;
|
||||
; 5 ; 0 ;
|
||||
; 6 ; 0 ;
|
||||
; 7 ; 0 ;
|
||||
; 8 ; 1 ;
|
||||
; 9 ; 0 ;
|
||||
; 10 ; 22 ;
|
||||
; 11 ; 0 ;
|
||||
; 12 ; 0 ;
|
||||
; 13 ; 0 ;
|
||||
; 14 ; 0 ;
|
||||
; 15 ; 1 ;
|
||||
+----------------------------------------------+------------------------------+
|
||||
+----------------------------------------------------------------------------+
|
||||
; LAB Signals Sourced ;
|
||||
+---------------------------------------------+------------------------------+
|
||||
; Number of Signals Sourced (Average = 9.96) ; Number of LABs (Total = 24) ;
|
||||
+---------------------------------------------+------------------------------+
|
||||
; 0 ; 0 ;
|
||||
; 1 ; 0 ;
|
||||
; 2 ; 0 ;
|
||||
; 3 ; 0 ;
|
||||
; 4 ; 1 ;
|
||||
; 5 ; 0 ;
|
||||
; 6 ; 0 ;
|
||||
; 7 ; 0 ;
|
||||
; 8 ; 0 ;
|
||||
; 9 ; 1 ;
|
||||
; 10 ; 20 ;
|
||||
; 11 ; 1 ;
|
||||
; 12 ; 0 ;
|
||||
; 13 ; 0 ;
|
||||
; 14 ; 0 ;
|
||||
; 15 ; 1 ;
|
||||
+---------------------------------------------+------------------------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------+
|
||||
; LAB Signals Sourced Out ;
|
||||
+-------------------------------------------------+------------------------------+
|
||||
; Number of Signals Sourced Out (Average = 7.50) ; Number of LABs (Total = 24) ;
|
||||
; Number of Signals Sourced Out (Average = 7.08) ; Number of LABs (Total = 24) ;
|
||||
+-------------------------------------------------+------------------------------+
|
||||
; 0 ; 0 ;
|
||||
; 1 ; 0 ;
|
||||
; 2 ; 1 ;
|
||||
; 2 ; 2 ;
|
||||
; 3 ; 1 ;
|
||||
; 4 ; 1 ;
|
||||
; 5 ; 2 ;
|
||||
; 6 ; 3 ;
|
||||
; 7 ; 2 ;
|
||||
; 8 ; 5 ;
|
||||
; 9 ; 3 ;
|
||||
; 10 ; 5 ;
|
||||
; 6 ; 1 ;
|
||||
; 7 ; 6 ;
|
||||
; 8 ; 3 ;
|
||||
; 9 ; 5 ;
|
||||
; 10 ; 2 ;
|
||||
; 11 ; 0 ;
|
||||
; 12 ; 1 ;
|
||||
+-------------------------------------------------+------------------------------+
|
||||
@ -643,7 +641,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
+-----------------------------------------------------------------------------+
|
||||
; LAB Distinct Inputs ;
|
||||
+----------------------------------------------+------------------------------+
|
||||
; Number of Distinct Inputs (Average = 12.75) ; Number of LABs (Total = 24) ;
|
||||
; Number of Distinct Inputs (Average = 12.25) ; Number of LABs (Total = 24) ;
|
||||
+----------------------------------------------+------------------------------+
|
||||
; 0 ; 0 ;
|
||||
; 1 ; 0 ;
|
||||
@ -651,24 +649,25 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
; 3 ; 0 ;
|
||||
; 4 ; 2 ;
|
||||
; 5 ; 0 ;
|
||||
; 6 ; 0 ;
|
||||
; 6 ; 1 ;
|
||||
; 7 ; 1 ;
|
||||
; 8 ; 0 ;
|
||||
; 9 ; 2 ;
|
||||
; 8 ; 1 ;
|
||||
; 9 ; 3 ;
|
||||
; 10 ; 1 ;
|
||||
; 11 ; 8 ;
|
||||
; 11 ; 1 ;
|
||||
; 12 ; 1 ;
|
||||
; 13 ; 0 ;
|
||||
; 13 ; 5 ;
|
||||
; 14 ; 2 ;
|
||||
; 15 ; 1 ;
|
||||
; 16 ; 0 ;
|
||||
; 17 ; 1 ;
|
||||
; 18 ; 2 ;
|
||||
; 19 ; 0 ;
|
||||
; 15 ; 0 ;
|
||||
; 16 ; 2 ;
|
||||
; 17 ; 0 ;
|
||||
; 18 ; 1 ;
|
||||
; 19 ; 2 ;
|
||||
; 20 ; 0 ;
|
||||
; 21 ; 0 ;
|
||||
; 22 ; 2 ;
|
||||
; 23 ; 1 ;
|
||||
; 22 ; 0 ;
|
||||
; 23 ; 0 ;
|
||||
; 24 ; 1 ;
|
||||
+----------------------------------------------+------------------------------+
|
||||
|
||||
|
||||
@ -716,7 +715,8 @@ Info (186079): Completed User Assigned Global Signals Promotion Operation
|
||||
Info (186215): Automatically promoted signal "C14M" to use Global clock in PIN 12 File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v Line: 8
|
||||
Info (186216): Automatically promoted some destinations of signal "PHI1" to use Global clock File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v Line: 8
|
||||
Info (186217): Destination "PHI1r" may be non-global or may not use global clock File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v Line: 20
|
||||
Info (186217): Destination "S~0" may be non-global or may not use global clock File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v Line: 19
|
||||
Info (186217): Destination "S~2" may be non-global or may not use global clock File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v Line: 19
|
||||
Info (186217): Destination "S[3]~9" may be non-global or may not use global clock File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v Line: 21
|
||||
Info (186228): Pin "PHI1" drives global clock, but is not placed in a dedicated clock pin position File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v Line: 8
|
||||
Info (186079): Completed Auto Global Promotion Operation
|
||||
Info (176234): Starting register packing
|
||||
@ -732,26 +732,26 @@ Warning (186473): Ignored the FAST_OUTPUT_REGISTER assignment made to the follow
|
||||
Warning (186484): Ignored assignment to node "RAout[7]" because node "RAr[7]", which is feeding it, is not a register File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v Line: 85
|
||||
Info (186469): Finished processing fast register assignments
|
||||
Info (176235): Finished register packing
|
||||
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00
|
||||
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:04
|
||||
Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
|
||||
Info (170189): Fitter placement preparation operations beginning
|
||||
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
|
||||
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:03
|
||||
Info (170191): Fitter placement operations beginning
|
||||
Info (170137): Fitter placement was successful
|
||||
Info (170192): Fitter placement operations ending: elapsed time is 00:00:02
|
||||
Info (170192): Fitter placement operations ending: elapsed time is 00:00:19
|
||||
Info (170193): Fitter routing operations beginning
|
||||
Info (170089): 5e+01 ns of routing delay (approximately 3.2% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report.
|
||||
Info (170195): Router estimated average interconnect usage is 27% of the available device resources
|
||||
Info (170196): Router estimated peak interconnect usage is 27% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
|
||||
Info (170089): 6e+01 ns of routing delay (approximately 3.8% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report.
|
||||
Info (170195): Router estimated average interconnect usage is 24% of the available device resources
|
||||
Info (170196): Router estimated peak interconnect usage is 24% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
|
||||
Info (170202): The Fitter performed an Auto Fit compilation. No optimizations were skipped because the design's timing and routability requirements required full optimization.
|
||||
Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
|
||||
Info (11888): Total time spent on timing analysis during the Fitter is 1.13 seconds.
|
||||
Info (170194): Fitter routing operations ending: elapsed time is 00:00:02
|
||||
Info (11888): Total time spent on timing analysis during the Fitter is 16.41 seconds.
|
||||
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
|
||||
Info (144001): Generated suppressed messages file /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.fit.smsg
|
||||
Info: Quartus Prime Fitter was successful. 0 errors, 11 warnings
|
||||
Info: Peak virtual memory: 13775 megabytes
|
||||
Info: Processing ended: Sat Jun 08 01:44:18 2024
|
||||
Info: Elapsed time: 00:00:06
|
||||
Info: Peak virtual memory: 13835 megabytes
|
||||
Info: Processing ended: Fri Jul 12 16:08:42 2024
|
||||
Info: Elapsed time: 00:00:40
|
||||
Info: Total CPU time (on all processors): 00:00:04
|
||||
|
||||
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
|
||||
Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
|
||||
Extra Info (176244): Moving registers into LUTs to improve timing and density
|
||||
Extra Info (176245): Finished moving registers into LUTs: elapsed time is 00:00:00
|
||||
Extra Info (176245): Finished moving registers into LUTs: elapsed time is 00:00:01
|
||||
|
||||
@ -1,11 +1,11 @@
|
||||
Fitter Status : Successful - Sat Jun 08 01:44:18 2024
|
||||
Fitter Status : Successful - Fri Jul 12 16:08:41 2024
|
||||
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Revision Name : RAM2E
|
||||
Top-level Entity Name : RAM2E
|
||||
Family : MAX II
|
||||
Device : EPM240T100C5
|
||||
Timing Models : Final
|
||||
Total logic elements : 238 / 240 ( 99 % )
|
||||
Total logic elements : 233 / 240 ( 97 % )
|
||||
Total pins : 71 / 80 ( 89 % )
|
||||
Total virtual pins : 0
|
||||
UFM blocks : 1 / 1 ( 100 % )
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
Flow report for RAM2E
|
||||
Sat Jun 08 01:44:25 2024
|
||||
Fri Jul 12 16:09:04 2024
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
|
||||
|
||||
@ -41,14 +41,14 @@ https://fpgasoftware.intel.com/eula.
|
||||
+---------------------------------------------------------------------+
|
||||
; Flow Summary ;
|
||||
+-----------------------+---------------------------------------------+
|
||||
; Flow Status ; Successful - Sat Jun 08 01:44:21 2024 ;
|
||||
; Flow Status ; Successful - Fri Jul 12 16:08:53 2024 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
||||
; Revision Name ; RAM2E ;
|
||||
; Top-level Entity Name ; RAM2E ;
|
||||
; Family ; MAX II ;
|
||||
; Device ; EPM240T100C5 ;
|
||||
; Timing Models ; Final ;
|
||||
; Total logic elements ; 238 / 240 ( 99 % ) ;
|
||||
; Total logic elements ; 233 / 240 ( 97 % ) ;
|
||||
; Total pins ; 71 / 80 ( 89 % ) ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 1 / 1 ( 100 % ) ;
|
||||
@ -60,7 +60,7 @@ https://fpgasoftware.intel.com/eula.
|
||||
+-------------------+---------------------+
|
||||
; Option ; Setting ;
|
||||
+-------------------+---------------------+
|
||||
; Start date & time ; 06/08/2024 01:43:22 ;
|
||||
; Start date & time ; 07/12/2024 16:06:43 ;
|
||||
; Main task ; Compilation ;
|
||||
; Revision Name ; RAM2E ;
|
||||
+-------------------+---------------------+
|
||||
@ -71,7 +71,7 @@ https://fpgasoftware.intel.com/eula.
|
||||
+---------------------------------------+------------------------------+---------------+-------------+------------+
|
||||
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
|
||||
+---------------------------------------+------------------------------+---------------+-------------+------------+
|
||||
; COMPILER_SIGNATURE_ID ; 121380219419.171782540212708 ; -- ; -- ; -- ;
|
||||
; COMPILER_SIGNATURE_ID ; 121380219419.172081480308696 ; -- ; -- ; -- ;
|
||||
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
|
||||
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
|
||||
; NUM_PARALLEL_PROCESSORS ; 4 ; -- ; -- ; -- ;
|
||||
@ -86,11 +86,11 @@ https://fpgasoftware.intel.com/eula.
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Analysis & Synthesis ; 00:00:49 ; 1.0 ; 13152 MB ; 00:00:40 ;
|
||||
; Fitter ; 00:00:06 ; 1.0 ; 13775 MB ; 00:00:04 ;
|
||||
; Assembler ; 00:00:01 ; 1.0 ; 13098 MB ; 00:00:01 ;
|
||||
; Timing Analyzer ; 00:00:02 ; 1.0 ; 13094 MB ; 00:00:01 ;
|
||||
; Total ; 00:00:58 ; -- ; -- ; 00:00:46 ;
|
||||
; Analysis & Synthesis ; 00:01:17 ; 1.0 ; 13149 MB ; 00:00:47 ;
|
||||
; Fitter ; 00:00:39 ; 1.0 ; 13835 MB ; 00:00:04 ;
|
||||
; Assembler ; 00:00:05 ; 1.0 ; 13097 MB ; 00:00:01 ;
|
||||
; Timing Analyzer ; 00:00:06 ; 1.0 ; 13093 MB ; 00:00:01 ;
|
||||
; Total ; 00:02:07 ; -- ; -- ; 00:00:53 ;
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
Analysis & Synthesis report for RAM2E
|
||||
Sat Jun 08 01:44:10 2024
|
||||
Fri Jul 12 16:07:59 2024
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
|
||||
|
||||
@ -46,12 +46,12 @@ https://fpgasoftware.intel.com/eula.
|
||||
+---------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Summary ;
|
||||
+-----------------------------+---------------------------------------------+
|
||||
; Analysis & Synthesis Status ; Successful - Sat Jun 08 01:44:10 2024 ;
|
||||
; Analysis & Synthesis Status ; Successful - Fri Jul 12 16:07:59 2024 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
||||
; Revision Name ; RAM2E ;
|
||||
; Top-level Entity Name ; RAM2E ;
|
||||
; Family ; MAX II ;
|
||||
; Total logic elements ; 252 ;
|
||||
; Total logic elements ; 247 ;
|
||||
; Total pins ; 71 ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 1 / 1 ( 100 % ) ;
|
||||
@ -164,34 +164,34 @@ https://fpgasoftware.intel.com/eula.
|
||||
+---------------------------------------------+-------+
|
||||
; Resource ; Usage ;
|
||||
+---------------------------------------------+-------+
|
||||
; Total logic elements ; 252 ;
|
||||
; -- Combinational with no register ; 126 ;
|
||||
; Total logic elements ; 247 ;
|
||||
; -- Combinational with no register ; 122 ;
|
||||
; -- Register only ; 33 ;
|
||||
; -- Combinational with a register ; 93 ;
|
||||
; -- Combinational with a register ; 92 ;
|
||||
; ; ;
|
||||
; Logic element usage by number of LUT inputs ; ;
|
||||
; -- 4 input functions ; 116 ;
|
||||
; -- 3 input functions ; 53 ;
|
||||
; -- 2 input functions ; 46 ;
|
||||
; -- 4 input functions ; 111 ;
|
||||
; -- 3 input functions ; 56 ;
|
||||
; -- 2 input functions ; 43 ;
|
||||
; -- 1 input functions ; 3 ;
|
||||
; -- 0 input functions ; 1 ;
|
||||
; ; ;
|
||||
; Logic elements by mode ; ;
|
||||
; -- normal mode ; 238 ;
|
||||
; -- normal mode ; 233 ;
|
||||
; -- arithmetic mode ; 14 ;
|
||||
; -- qfbk mode ; 0 ;
|
||||
; -- register cascade mode ; 0 ;
|
||||
; -- synchronous clear/load mode ; 3 ;
|
||||
; -- asynchronous clear/load mode ; 0 ;
|
||||
; ; ;
|
||||
; Total registers ; 126 ;
|
||||
; Total registers ; 125 ;
|
||||
; Total logic cells in carry chains ; 15 ;
|
||||
; I/O pins ; 71 ;
|
||||
; UFM blocks ; 1 ;
|
||||
; Maximum fan-out node ; C14M ;
|
||||
; Maximum fan-out ; 122 ;
|
||||
; Total fan-out ; 1001 ;
|
||||
; Average fan-out ; 3.09 ;
|
||||
; Maximum fan-out ; 121 ;
|
||||
; Total fan-out ; 982 ;
|
||||
; Average fan-out ; 3.08 ;
|
||||
+---------------------------------------------+-------+
|
||||
|
||||
|
||||
@ -200,7 +200,7 @@ https://fpgasoftware.intel.com/eula.
|
||||
+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
|
||||
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
|
||||
+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
|
||||
; |RAM2E ; 252 (191) ; 126 ; 1 ; 71 ; 0 ; 126 (97) ; 33 (25) ; 93 (69) ; 15 (15) ; 0 (0) ; |RAM2E ; RAM2E ; work ;
|
||||
; |RAM2E ; 247 (186) ; 125 ; 1 ; 71 ; 0 ; 122 (93) ; 33 (25) ; 92 (68) ; 15 (15) ; 0 (0) ; |RAM2E ; RAM2E ; work ;
|
||||
; |RAM2E_UFM:ram2e_ufm| ; 61 (61) ; 32 ; 1 ; 0 ; 0 ; 29 (29) ; 8 (8) ; 24 (24) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm ; RAM2E_UFM ; work ;
|
||||
; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst ; UFM ; work ;
|
||||
; |UFM_altufm_none_lbr:UFM_altufm_none_lbr_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component ; UFM_altufm_none_lbr ; work ;
|
||||
@ -222,12 +222,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
+----------------------------------------------+-------+
|
||||
; Statistic ; Value ;
|
||||
+----------------------------------------------+-------+
|
||||
; Total registers ; 126 ;
|
||||
; Total registers ; 125 ;
|
||||
; Number of registers using Synchronous Clear ; 3 ;
|
||||
; Number of registers using Synchronous Load ; 0 ;
|
||||
; Number of registers using Asynchronous Clear ; 0 ;
|
||||
; Number of registers using Asynchronous Load ; 0 ;
|
||||
; Number of registers using Clock Enable ; 59 ;
|
||||
; Number of registers using Clock Enable ; 58 ;
|
||||
; Number of registers using Preset ; 0 ;
|
||||
+----------------------------------------------+-------+
|
||||
|
||||
@ -256,13 +256,13 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+
|
||||
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
|
||||
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+
|
||||
; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |RAM2E|S[2] ;
|
||||
; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |RAM2E|S[3] ;
|
||||
; 4:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |RAM2E|CS[1] ;
|
||||
; 4:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |RAM2E|RAM2E_UFM:ram2e_ufm|RWMask[5] ;
|
||||
; 4:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |RAM2E|RAM2E_UFM:ram2e_ufm|RWMask[4] ;
|
||||
; 16:1 ; 2 bits ; 20 LEs ; 2 LEs ; 18 LEs ; Yes ; |RAM2E|BA[0]~reg0 ;
|
||||
; 17:1 ; 4 bits ; 44 LEs ; 8 LEs ; 36 LEs ; Yes ; |RAM2E|RA[6] ;
|
||||
; 19:1 ; 2 bits ; 24 LEs ; 4 LEs ; 20 LEs ; Yes ; |RAM2E|RA[1] ;
|
||||
; 10:1 ; 2 bits ; 12 LEs ; 4 LEs ; 8 LEs ; Yes ; |RAM2E|DQML~reg0 ;
|
||||
; 17:1 ; 4 bits ; 44 LEs ; 8 LEs ; 36 LEs ; Yes ; |RAM2E|RA[7] ;
|
||||
; 19:1 ; 2 bits ; 24 LEs ; 4 LEs ; 20 LEs ; Yes ; |RAM2E|RA[2] ;
|
||||
; 10:1 ; 2 bits ; 12 LEs ; 4 LEs ; 8 LEs ; Yes ; |RAM2E|DQMH~reg0 ;
|
||||
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+
|
||||
|
||||
|
||||
@ -283,7 +283,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime Analysis & Synthesis
|
||||
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Info: Processing started: Sat Jun 08 01:43:21 2024
|
||||
Info: Processing started: Fri Jul 12 16:06:42 2024
|
||||
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E-MAXII -c RAM2E
|
||||
Info (20032): Parallel compilation is enabled and will use up to 4 processors
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file //mac/icloud/repos/ram2e/cpld/ram2e.v
|
||||
@ -296,12 +296,12 @@ Info (12021): Found 2 design units, including 2 entities, in source file ufm.v
|
||||
Info (12023): Found entity 1: UFM_altufm_none_lbr File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 47
|
||||
Info (12023): Found entity 2: UFM File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 166
|
||||
Info (12127): Elaborating entity "RAM2E" for the top level hierarchy
|
||||
Info (12128): Elaborating entity "RAM2E_UFM" for hierarchy "RAM2E_UFM:ram2e_ufm" File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v Line: 136
|
||||
Info (12128): Elaborating entity "RAM2E_UFM" for hierarchy "RAM2E_UFM:ram2e_ufm" File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v Line: 132
|
||||
Info (12128): Elaborating entity "UFM" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst" File: //Mac/iCloud/Repos/RAM2E/CPLD/UFM-MAX.v Line: 77
|
||||
Info (12128): Elaborating entity "UFM_altufm_none_lbr" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component" File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 217
|
||||
Info (12128): Elaborating entity "DHGR" for hierarchy "DHGR:dhgr" File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v Line: 140
|
||||
Info (12128): Elaborating entity "DHGR" for hierarchy "DHGR:dhgr" File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v Line: 136
|
||||
Warning (13024): Output pins are stuck at VCC or GND
|
||||
Warning (13410): Pin "nDHGROE" is stuck at GND File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v Line: 139
|
||||
Warning (13410): Pin "nDHGROE" is stuck at GND File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v Line: 135
|
||||
Warning (13410): Pin "nCSout" is stuck at GND File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v Line: 75
|
||||
Warning (14632): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v Line: 50
|
||||
Warning (14632): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v Line: 50
|
||||
@ -313,18 +313,18 @@ Warning (14632): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot
|
||||
Warning (14632): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v Line: 50
|
||||
Warning (21074): Design contains 1 input pin(s) that do not drive logic
|
||||
Warning (15610): No output dependent on input pin "nWE80" File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v Line: 11
|
||||
Info (21057): Implemented 324 device resources after synthesis - the final resource count might be different
|
||||
Info (21057): Implemented 319 device resources after synthesis - the final resource count might be different
|
||||
Info (21058): Implemented 22 input pins
|
||||
Info (21059): Implemented 41 output pins
|
||||
Info (21060): Implemented 8 bidirectional pins
|
||||
Info (21061): Implemented 252 logic cells
|
||||
Info (21061): Implemented 247 logic cells
|
||||
Info (21070): Implemented 1 User Flash Memory blocks
|
||||
Info (144001): Generated suppressed messages file /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.map.smsg
|
||||
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 13 warnings
|
||||
Info: Peak virtual memory: 13152 megabytes
|
||||
Info: Processing ended: Sat Jun 08 01:44:10 2024
|
||||
Info: Elapsed time: 00:00:49
|
||||
Info: Total CPU time (on all processors): 00:00:41
|
||||
Info: Peak virtual memory: 13149 megabytes
|
||||
Info: Processing ended: Fri Jul 12 16:07:59 2024
|
||||
Info: Elapsed time: 00:01:17
|
||||
Info: Total CPU time (on all processors): 00:00:47
|
||||
|
||||
|
||||
+------------------------------------------+
|
||||
|
||||
@ -1,9 +1,9 @@
|
||||
Analysis & Synthesis Status : Successful - Sat Jun 08 01:44:10 2024
|
||||
Analysis & Synthesis Status : Successful - Fri Jul 12 16:07:59 2024
|
||||
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Revision Name : RAM2E
|
||||
Top-level Entity Name : RAM2E
|
||||
Family : MAX II
|
||||
Total logic elements : 252
|
||||
Total logic elements : 247
|
||||
Total pins : 71
|
||||
Total virtual pins : 0
|
||||
UFM blocks : 1 / 1 ( 100 % )
|
||||
|
||||
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Reference in New Issue
Block a user