mirror of
https://github.com/garrettsworkshop/RAM2E.git
synced 2024-12-25 03:30:40 +00:00
Zane Kaminski
parent
51e5d7e984
commit
6706e42efb
1
.gitignore
vendored
1
.gitignore
vendored
@ -39,4 +39,3 @@ CPLD/LCMXO*/impl1/*
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!CPLD/LCMXO*/impl1/*.srr
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!CPLD/LCMXO*/impl1/*.twr
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!CPLD/LCMXO*/impl1/*.tw1
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*.bak
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@ -42,7 +42,7 @@ set_global_assignment -name DEVICE EPM240T100C5
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set_global_assignment -name TOP_LEVEL_ENTITY RAM2E
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 19.1.0
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "07:26:23 AUGUST 20, 2023"
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set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 SP0.02std Lite Edition"
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set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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@ -240,15 +240,9 @@ set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RD
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set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
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set_global_assignment -name VERILOG_FILE "../RAM2E-MAX.v"
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set_global_assignment -name QIP_FILE UFM.qip
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set_global_assignment -name MIF_FILE ../RAM2E-MAX.mif
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set_global_assignment -name MIF_FILE ../RAM2E.mif
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set_global_assignment -name SDC_FILE ../RAM2E.sdc
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set_global_assignment -name SDC_FILE "../RAM2E-MAX.sdc"
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set_location_assignment PIN_88 -to LED
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LED
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set_instance_assignment -name SLOW_SLEW_RATE ON -to LED
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set_location_assignment PIN_81 -to RCLK
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set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RCLK
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set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RCLK
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set_instance_assignment -name SLOW_SLEW_RATE OFF -to RCLK
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set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RCLK
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set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RCLK
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Binary file not shown.
@ -34,7 +34,7 @@
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//https://fpgasoftware.intel.com/eula.
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//altufm_none CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="MAX II" ERASE_TIME=500000000 LPM_FILE="../RAM2E-MAX.mif" OSC_FREQUENCY=180000 PORT_ARCLKENA="PORT_UNUSED" PORT_DRCLKENA="PORT_UNUSED" PROGRAM_TIME=1600000 WIDTH_UFM_ADDRESS=9 arclk ardin arshft busy drclk drdin drdout drshft erase osc oscena program rtpbusy
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//altufm_none CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="MAX II" ERASE_TIME=500000000 LPM_FILE="../RAM2E.mif" OSC_FREQUENCY=180000 PORT_ARCLKENA="PORT_UNUSED" PORT_DRCLKENA="PORT_UNUSED" PROGRAM_TIME=1600000 WIDTH_UFM_ADDRESS=9 arclk ardin arshft busy drclk drdin drdout drshft erase osc oscena program rtpbusy
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//VERSION_BEGIN 19.1 cbx_a_gray2bin 2019:09:22:11:00:27:SJ cbx_a_graycounter 2019:09:22:11:00:27:SJ cbx_altufm_none 2019:09:22:11:00:28:SJ cbx_cycloneii 2019:09:22:11:00:28:SJ cbx_lpm_add_sub 2019:09:22:11:00:28:SJ cbx_lpm_compare 2019:09:22:11:00:28:SJ cbx_lpm_counter 2019:09:22:11:00:28:SJ cbx_lpm_decode 2019:09:22:11:00:28:SJ cbx_lpm_mux 2019:09:22:11:00:28:SJ cbx_maxii 2019:09:22:11:00:28:SJ cbx_mgl 2019:09:22:11:02:15:SJ cbx_nadder 2019:09:22:11:00:28:SJ cbx_stratix 2019:09:22:11:00:28:SJ cbx_stratixii 2019:09:22:11:00:28:SJ cbx_util_mgl 2019:09:22:11:00:28:SJ VERSION_END
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// synthesis VERILOG_INPUT_VERSION VERILOG_2001
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// altera message_off 10463
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@ -118,7 +118,7 @@ module UFM_altufm_none_lbr
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defparam
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maxii_ufm_block1.address_width = 9,
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maxii_ufm_block1.erase_time = 500000000,
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maxii_ufm_block1.init_file = "../RAM2E-MAX.mif",
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maxii_ufm_block1.init_file = "../RAM2E.mif",
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maxii_ufm_block1.mem1 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
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maxii_ufm_block1.mem10 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
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maxii_ufm_block1.mem11 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
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@ -225,7 +225,7 @@ endmodule
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX II"
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// Retrieval info: CONSTANT: ERASE_TIME NUMERIC "500000000"
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// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX II"
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// Retrieval info: CONSTANT: LPM_FILE STRING "../RAM2E-MAX.mif"
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// Retrieval info: CONSTANT: LPM_FILE STRING "../RAM2E.mif"
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// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "altufm_none"
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// Retrieval info: CONSTANT: OSC_FREQUENCY NUMERIC "180000"
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@ -1,6 +1,6 @@
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Assembler report for RAM2E
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Tue Nov 21 06:54:42 2023
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Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
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Thu Sep 21 05:34:41 2023
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Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
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---------------------
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@ -10,7 +10,7 @@ Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Editio
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2. Assembler Summary
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3. Assembler Settings
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4. Assembler Generated Files
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5. Assembler Device Options: Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pof
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5. Assembler Device Options: /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pof
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6. Assembler Messages
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@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula.
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+---------------------------------------------------------------+
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; Assembler Summary ;
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+-----------------------+---------------------------------------+
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; Assembler Status ; Successful - Tue Nov 21 06:54:42 2023 ;
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; Assembler Status ; Successful - Thu Sep 21 05:34:41 2023 ;
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; Revision Name ; RAM2E ;
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; Top-level Entity Name ; RAM2E ;
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; Family ; MAX II ;
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@ -53,23 +53,23 @@ https://fpgasoftware.intel.com/eula.
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+--------+---------+---------------+
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+--------------------------------------------------+
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; Assembler Generated Files ;
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+--------------------------------------------------+
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; File Name ;
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+--------------------------------------------------+
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; Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pof ;
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+--------------------------------------------------+
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+------------------------------------------------+
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; Assembler Generated Files ;
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+------------------------------------------------+
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; File Name ;
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+------------------------------------------------+
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; /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pof ;
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+------------------------------------------------+
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+----------------------------------------------------------------------------+
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; Assembler Device Options: Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pof ;
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+----------------+-----------------------------------------------------------+
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; Option ; Setting ;
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+----------------+-----------------------------------------------------------+
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; JTAG usercode ; 0x0016C0A4 ;
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; Checksum ; 0x0016C524 ;
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+----------------+-----------------------------------------------------------+
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+--------------------------------------------------------------------------+
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; Assembler Device Options: /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pof ;
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+----------------+---------------------------------------------------------+
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; Option ; Setting ;
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+----------------+---------------------------------------------------------+
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; JTAG usercode ; 0x0016D33C ;
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; Checksum ; 0x0016D634 ;
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+----------------+---------------------------------------------------------+
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+--------------------+
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@ -77,15 +77,15 @@ https://fpgasoftware.intel.com/eula.
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+--------------------+
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Info: *******************************************************************
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Info: Running Quartus Prime Assembler
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Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
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Info: Processing started: Tue Nov 21 06:54:41 2023
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Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
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Info: Processing started: Thu Sep 21 05:34:39 2023
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Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2E-MAXII -c RAM2E
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Info (115031): Writing out detailed assembly data for power analysis
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Info (115030): Assembler is generating device programming files
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Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings
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Info: Peak virtual memory: 13068 megabytes
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Info: Processing ended: Tue Nov 21 06:54:42 2023
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Info: Elapsed time: 00:00:01
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Info: Peak virtual memory: 13092 megabytes
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Info: Processing ended: Thu Sep 21 05:34:41 2023
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Info: Elapsed time: 00:00:02
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Info: Total CPU time (on all processors): 00:00:01
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@ -1 +1 @@
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Tue Nov 21 06:54:46 2023
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Thu Sep 21 05:34:46 2023
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@ -1,6 +1,6 @@
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Fitter report for RAM2E
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Tue Nov 21 06:54:39 2023
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Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
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Thu Sep 21 05:34:37 2023
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Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
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---------------------
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@ -54,21 +54,21 @@ https://fpgasoftware.intel.com/eula.
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+-------------------------------------------------------------------------------------+
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; Fitter Summary ;
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+-----------------------+-------------------------------------------------------------+
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; Fitter Status ; Successful - Tue Nov 21 06:54:39 2023 ;
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; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
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; Revision Name ; RAM2E ;
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; Top-level Entity Name ; RAM2E ;
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; Family ; MAX II ;
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; Device ; EPM240T100C5 ;
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; Timing Models ; Final ;
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; Total logic elements ; 209 / 240 ( 87 % ) ;
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; Total pins ; 71 / 80 ( 89 % ) ;
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; Total virtual pins ; 0 ;
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; UFM blocks ; 1 / 1 ( 100 % ) ;
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+-----------------------+-------------------------------------------------------------+
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+---------------------------------------------------------------------+
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; Fitter Summary ;
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+-----------------------+---------------------------------------------+
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; Fitter Status ; Successful - Thu Sep 21 05:34:37 2023 ;
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; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
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; Revision Name ; RAM2E ;
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; Top-level Entity Name ; RAM2E ;
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; Family ; MAX II ;
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; Device ; EPM240T100C5 ;
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; Timing Models ; Final ;
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; Total logic elements ; 197 / 240 ( 82 % ) ;
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; Total pins ; 70 / 80 ( 88 % ) ;
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; Total virtual pins ; 0 ;
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; UFM blocks ; 1 / 1 ( 100 % ) ;
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+-----------------------+---------------------------------------------+
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+--------------------------------------------------------------------------------------------------------------------------------------+
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@ -129,20 +129,20 @@ https://fpgasoftware.intel.com/eula.
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; Number detected on machine ; 4 ;
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; Maximum allowed ; 4 ;
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; ; ;
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; Average used ; 1.02 ;
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; Average used ; 1.03 ;
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; Maximum used ; 4 ;
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; ; ;
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; Usage by Processor ; % Time Used ;
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; Processor 1 ; 100.0% ;
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; Processor 2 ; 0.9% ;
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; Processors 3-4 ; 0.7% ;
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; Processor 2 ; 1.2% ;
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; Processors 3-4 ; 1.1% ;
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+----------------------------+-------------+
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+--------------+
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; Pin-Out File ;
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+--------------+
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The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pin.
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The pin-out file can be found in /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pin.
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+---------------------------------------------------------------------+
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@ -150,31 +150,31 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pi
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+---------------------------------------------+-----------------------+
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; Resource ; Usage ;
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+---------------------------------------------+-----------------------+
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; Total logic elements ; 209 / 240 ( 87 % ) ;
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; -- Combinational with no register ; 95 ;
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; Total logic elements ; 197 / 240 ( 82 % ) ;
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; -- Combinational with no register ; 85 ;
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; -- Register only ; 19 ;
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; -- Combinational with a register ; 95 ;
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; -- Combinational with a register ; 93 ;
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; ; ;
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; Logic element usage by number of LUT inputs ; ;
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; -- 4 input functions ; 99 ;
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; -- 3 input functions ; 33 ;
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; -- 2 input functions ; 53 ;
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; -- 1 input functions ; 4 ;
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; -- 4 input functions ; 103 ;
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; -- 3 input functions ; 29 ;
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; -- 2 input functions ; 42 ;
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; -- 1 input functions ; 3 ;
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; -- 0 input functions ; 1 ;
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; ; ;
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; Logic elements by mode ; ;
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; -- normal mode ; 195 ;
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; -- normal mode ; 183 ;
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; -- arithmetic mode ; 14 ;
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; -- qfbk mode ; 8 ;
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; -- register cascade mode ; 0 ;
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; -- synchronous clear/load mode ; 10 ;
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; -- synchronous clear/load mode ; 12 ;
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; -- asynchronous clear/load mode ; 0 ;
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; ; ;
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; Total registers ; 114 / 240 ( 48 % ) ;
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; Total registers ; 112 / 240 ( 47 % ) ;
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; Total LABs ; 24 / 24 ( 100 % ) ;
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; Logic elements in carry chains ; 15 ;
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; Virtual pins ; 0 ;
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; I/O pins ; 71 / 80 ( 89 % ) ;
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; I/O pins ; 70 / 80 ( 88 % ) ;
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; -- Clock pins ; 3 / 4 ( 75 % ) ;
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; ; ;
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; UFM blocks ; 1 / 1 ( 100 % ) ;
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@ -185,12 +185,12 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pi
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; Global signals ; 1 ;
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; -- Global clocks ; 1 / 4 ( 25 % ) ;
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; JTAGs ; 0 / 1 ( 0 % ) ;
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; Average interconnect usage (total/H/V) ; 22.4% / 22.7% / 22.1% ;
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; Peak interconnect usage (total/H/V) ; 22.4% / 22.7% / 22.1% ;
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; Maximum fan-out ; 114 ;
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; Highest non-global fan-out ; 36 ;
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; Total fan-out ; 872 ;
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; Average fan-out ; 3.10 ;
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; Average interconnect usage (total/H/V) ; 22.5% / 24.3% / 20.7% ;
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; Peak interconnect usage (total/H/V) ; 22.5% / 24.3% / 20.7% ;
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; Maximum fan-out ; 112 ;
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; Highest non-global fan-out ; 31 ;
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; Total fan-out ; 847 ;
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; Average fan-out ; 3.16 ;
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+---------------------------------------------+-----------------------+
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@ -207,16 +207,16 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pi
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; Ain[5] ; 34 ; 1 ; 3 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
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; Ain[6] ; 39 ; 1 ; 5 ; 0 ; 3 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
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; Ain[7] ; 53 ; 2 ; 8 ; 1 ; 3 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
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; C14M ; 12 ; 1 ; 1 ; 3 ; 3 ; 114 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
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; Din[0] ; 38 ; 1 ; 4 ; 0 ; 0 ; 13 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
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; Din[1] ; 40 ; 1 ; 5 ; 0 ; 2 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
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; Din[2] ; 42 ; 1 ; 5 ; 0 ; 0 ; 12 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
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; Din[3] ; 41 ; 1 ; 5 ; 0 ; 1 ; 11 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
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; C14M ; 12 ; 1 ; 1 ; 3 ; 3 ; 112 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
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; Din[0] ; 38 ; 1 ; 4 ; 0 ; 0 ; 14 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
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; Din[1] ; 40 ; 1 ; 5 ; 0 ; 2 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
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; Din[2] ; 42 ; 1 ; 5 ; 0 ; 0 ; 13 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
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; Din[3] ; 41 ; 1 ; 5 ; 0 ; 1 ; 12 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
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; Din[4] ; 48 ; 1 ; 6 ; 0 ; 0 ; 9 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
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; Din[5] ; 49 ; 1 ; 7 ; 0 ; 2 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
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; Din[5] ; 49 ; 1 ; 7 ; 0 ; 2 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
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; Din[6] ; 36 ; 1 ; 4 ; 0 ; 2 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
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; Din[7] ; 35 ; 1 ; 3 ; 0 ; 0 ; 9 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
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; PHI1 ; 37 ; 1 ; 4 ; 0 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
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; Din[7] ; 35 ; 1 ; 3 ; 0 ; 0 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
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; PHI1 ; 37 ; 1 ; 4 ; 0 ; 1 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
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; nC07X ; 52 ; 2 ; 8 ; 1 ; 4 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
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; nEN80 ; 28 ; 1 ; 2 ; 0 ; 1 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
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; nWE ; 51 ; 1 ; 7 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
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@ -231,31 +231,30 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pi
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+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
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; BA[0] ; 6 ; 1 ; 1 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
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; BA[1] ; 14 ; 1 ; 1 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
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; CKE ; 4 ; 1 ; 1 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
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; CKE ; 4 ; 1 ; 1 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; DQMH ; 100 ; 2 ; 2 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; DQML ; 98 ; 2 ; 2 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Dout[0] ; 77 ; 2 ; 7 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Dout[1] ; 76 ; 2 ; 7 ; 5 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Dout[2] ; 74 ; 2 ; 8 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; Dout[1] ; 76 ; 2 ; 7 ; 5 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; Dout[2] ; 74 ; 2 ; 8 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Dout[3] ; 75 ; 2 ; 7 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Dout[4] ; 73 ; 2 ; 8 ; 4 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; Dout[5] ; 72 ; 2 ; 8 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Dout[6] ; 84 ; 2 ; 6 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Dout[7] ; 85 ; 2 ; 5 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; LED ; 88 ; 2 ; 5 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; LED ; 88 ; 2 ; 5 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; RA[0] ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; RA[10] ; 16 ; 1 ; 1 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RA[11] ; 7 ; 1 ; 1 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RA[1] ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RA[2] ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RA[3] ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RA[3] ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; RA[4] ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RA[5] ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RA[6] ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RA[7] ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RA[8] ; 17 ; 1 ; 1 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RA[9] ; 15 ; 1 ; 1 ; 2 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RCLK ; 81 ; 2 ; 6 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; Vout[0] ; 70 ; 2 ; 8 ; 4 ; 4 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[1] ; 67 ; 2 ; 8 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[2] ; 69 ; 2 ; 8 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
@ -265,8 +264,8 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pi
|
||||
; Vout[6] ; 58 ; 2 ; 8 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[7] ; 57 ; 2 ; 8 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; nCAS ; 3 ; 1 ; 1 ; 4 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; nCS ; 8 ; 1 ; 1 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; nDOE ; 55 ; 2 ; 8 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; nCS ; 8 ; 1 ; 1 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; nDOE ; 55 ; 2 ; 8 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; nRAS ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; nRWE ; 2 ; 1 ; 1 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; nVOE ; 50 ; 1 ; 7 ; 0 ; 1 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
@ -295,7 +294,7 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pi
|
||||
; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
|
||||
+----------+-------------------+---------------+--------------+
|
||||
; 1 ; 38 / 38 ( 100 % ) ; 3.3V ; -- ;
|
||||
; 2 ; 33 / 42 ( 79 % ) ; 3.3V ; -- ;
|
||||
; 2 ; 32 / 42 ( 76 % ) ; 3.3V ; -- ;
|
||||
+----------+-------------------+---------------+--------------+
|
||||
|
||||
|
||||
@ -384,7 +383,7 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pi
|
||||
; 78 ; 64 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
|
||||
; 79 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; 80 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
|
||||
; 81 ; 65 ; 2 ; RCLK ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
|
||||
; 81 ; 65 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
|
||||
; 82 ; 66 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
|
||||
; 83 ; 67 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
|
||||
; 84 ; 68 ; 2 ; Dout[6] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
|
||||
@ -429,7 +428,7 @@ Note: User assignments will override these defaults. The user specified values a
|
||||
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+
|
||||
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
|
||||
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+
|
||||
; |RAM2E ; 209 (209) ; 114 ; 1 ; 71 ; 0 ; 95 (95) ; 19 (19) ; 95 (95) ; 15 (15) ; 8 (8) ; |RAM2E ; RAM2E ; work ;
|
||||
; |RAM2E ; 197 (197) ; 112 ; 1 ; 70 ; 0 ; 85 (85) ; 19 (19) ; 93 (93) ; 15 (15) ; 8 (8) ; |RAM2E ; RAM2E ; work ;
|
||||
; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|UFM:UFM_inst ; UFM ; work ;
|
||||
; |UFM_altufm_none_lbr:UFM_altufm_none_lbr_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component ; UFM_altufm_none_lbr ; work ;
|
||||
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+
|
||||
@ -441,7 +440,6 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
+---------+----------+---------------+
|
||||
; Name ; Pin Type ; Pad to Core 0 ;
|
||||
+---------+----------+---------------+
|
||||
; RCLK ; Output ; -- ;
|
||||
; LED ; Output ; -- ;
|
||||
; Dout[0] ; Output ; -- ;
|
||||
; Dout[1] ; Output ; -- ;
|
||||
@ -493,8 +491,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
; nEN80 ; Input ; (0) ;
|
||||
; nWE ; Input ; (0) ;
|
||||
; PHI1 ; Input ; (1) ;
|
||||
; C14M ; Input ; (0) ;
|
||||
; Din[0] ; Input ; (0) ;
|
||||
; C14M ; Input ; (0) ;
|
||||
; nWE80 ; Input ; (0) ;
|
||||
; Ain[0] ; Input ; (0) ;
|
||||
; Ain[1] ; Input ; (0) ;
|
||||
@ -515,23 +513,22 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
+---------+----------+---------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------+
|
||||
; Control Signals ;
|
||||
+--------------+-------------+---------+---------------+--------+----------------------+------------------+
|
||||
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
|
||||
+--------------+-------------+---------+---------------+--------+----------------------+------------------+
|
||||
; C14M ; PIN_12 ; 114 ; Clock ; yes ; Global Clock ; GCLK0 ;
|
||||
; CS[0]~2 ; LC_X6_Y2_N5 ; 3 ; Clock enable ; no ; -- ; -- ;
|
||||
; Equal17~1 ; LC_X7_Y2_N8 ; 16 ; Clock enable ; no ; -- ; -- ;
|
||||
; Equal17~2 ; LC_X7_Y2_N5 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; RA[0]~15 ; LC_X2_Y2_N5 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; RDOE ; LC_X3_Y4_N4 ; 8 ; Output enable ; no ; -- ; -- ;
|
||||
; RWMask~1 ; LC_X4_Y2_N6 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; S[2] ; LC_X5_Y1_N4 ; 22 ; Sync. clear ; no ; -- ; -- ;
|
||||
; UFMD[7]~0 ; LC_X3_Y2_N0 ; 9 ; Clock enable ; no ; -- ; -- ;
|
||||
; UFMProgram~3 ; LC_X3_Y3_N1 ; 2 ; Clock enable ; no ; -- ; -- ;
|
||||
; always4~10 ; LC_X5_Y2_N5 ; 16 ; Clock enable ; no ; -- ; -- ;
|
||||
+--------------+-------------+---------+---------------+--------+----------------------+------------------+
|
||||
+-------------------------------------------------------------------------------------------------------+
|
||||
; Control Signals ;
|
||||
+------------+-------------+---------+---------------+--------+----------------------+------------------+
|
||||
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
|
||||
+------------+-------------+---------+---------------+--------+----------------------+------------------+
|
||||
; C14M ; PIN_12 ; 112 ; Clock ; yes ; Global Clock ; GCLK0 ;
|
||||
; CS[0]~2 ; LC_X3_Y2_N8 ; 3 ; Clock enable ; no ; -- ; -- ;
|
||||
; Equal9~1 ; LC_X3_Y3_N0 ; 16 ; Clock enable ; no ; -- ; -- ;
|
||||
; Equal9~2 ; LC_X7_Y2_N5 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; RA[0]~15 ; LC_X2_Y2_N0 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; RDOE ; LC_X3_Y3_N5 ; 8 ; Output enable ; no ; -- ; -- ;
|
||||
; RWMask~1 ; LC_X4_Y1_N4 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; S[2] ; LC_X6_Y3_N6 ; 22 ; Sync. clear ; no ; -- ; -- ;
|
||||
; UFMD[15]~0 ; LC_X6_Y1_N2 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; always2~8 ; LC_X3_Y3_N7 ; 16 ; Clock enable ; no ; -- ; -- ;
|
||||
+------------+-------------+---------+---------------+--------+----------------------+------------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------+
|
||||
@ -539,7 +536,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
+------+----------+---------+----------------------+------------------+
|
||||
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
|
||||
+------+----------+---------+----------------------+------------------+
|
||||
; C14M ; PIN_12 ; 114 ; Global Clock ; GCLK0 ;
|
||||
; C14M ; PIN_12 ; 112 ; Global Clock ; GCLK0 ;
|
||||
+------+----------+---------+----------------------+------------------+
|
||||
|
||||
|
||||
@ -548,115 +545,120 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
+-----------------------+--------------------+
|
||||
; Routing Resource Type ; Usage ;
|
||||
+-----------------------+--------------------+
|
||||
; C4s ; 138 / 784 ( 18 % ) ;
|
||||
; Direct links ; 37 / 888 ( 4 % ) ;
|
||||
; C4s ; 139 / 784 ( 18 % ) ;
|
||||
; Direct links ; 38 / 888 ( 4 % ) ;
|
||||
; Global clocks ; 1 / 4 ( 25 % ) ;
|
||||
; LAB clocks ; 6 / 32 ( 19 % ) ;
|
||||
; LUT chains ; 5 / 216 ( 2 % ) ;
|
||||
; Local interconnects ; 268 / 888 ( 30 % ) ;
|
||||
; R4s ; 126 / 704 ( 18 % ) ;
|
||||
; LUT chains ; 4 / 216 ( 2 % ) ;
|
||||
; Local interconnects ; 282 / 888 ( 32 % ) ;
|
||||
; R4s ; 134 / 704 ( 19 % ) ;
|
||||
+-----------------------+--------------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------+
|
||||
; LAB Logic Elements ;
|
||||
+--------------------------------------------+------------------------------+
|
||||
; Number of Logic Elements (Average = 8.71) ; Number of LABs (Total = 24) ;
|
||||
; Number of Logic Elements (Average = 8.21) ; Number of LABs (Total = 24) ;
|
||||
+--------------------------------------------+------------------------------+
|
||||
; 1 ; 0 ;
|
||||
; 1 ; 2 ;
|
||||
; 2 ; 0 ;
|
||||
; 3 ; 2 ;
|
||||
; 4 ; 1 ;
|
||||
; 5 ; 0 ;
|
||||
; 6 ; 2 ;
|
||||
; 3 ; 1 ;
|
||||
; 4 ; 0 ;
|
||||
; 5 ; 1 ;
|
||||
; 6 ; 1 ;
|
||||
; 7 ; 0 ;
|
||||
; 8 ; 1 ;
|
||||
; 9 ; 1 ;
|
||||
; 10 ; 17 ;
|
||||
; 8 ; 3 ;
|
||||
; 9 ; 3 ;
|
||||
; 10 ; 13 ;
|
||||
+--------------------------------------------+------------------------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------+
|
||||
; LAB-wide Signals ;
|
||||
+------------------------------------+------------------------------+
|
||||
; LAB-wide Signals (Average = 1.33) ; Number of LABs (Total = 24) ;
|
||||
; LAB-wide Signals (Average = 1.38) ; Number of LABs (Total = 24) ;
|
||||
+------------------------------------+------------------------------+
|
||||
; 1 Clock ; 22 ;
|
||||
; 1 Clock enable ; 7 ;
|
||||
; 2 Clock enables ; 3 ;
|
||||
; 1 Clock ; 23 ;
|
||||
; 1 Clock enable ; 9 ;
|
||||
; 2 Clock enables ; 1 ;
|
||||
+------------------------------------+------------------------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------+
|
||||
; LAB Signals Sourced ;
|
||||
+---------------------------------------------+------------------------------+
|
||||
; Number of Signals Sourced (Average = 8.96) ; Number of LABs (Total = 24) ;
|
||||
; Number of Signals Sourced (Average = 8.54) ; Number of LABs (Total = 24) ;
|
||||
+---------------------------------------------+------------------------------+
|
||||
; 0 ; 0 ;
|
||||
; 1 ; 0 ;
|
||||
; 1 ; 2 ;
|
||||
; 2 ; 0 ;
|
||||
; 3 ; 2 ;
|
||||
; 4 ; 1 ;
|
||||
; 5 ; 0 ;
|
||||
; 6 ; 2 ;
|
||||
; 3 ; 1 ;
|
||||
; 4 ; 0 ;
|
||||
; 5 ; 1 ;
|
||||
; 6 ; 1 ;
|
||||
; 7 ; 0 ;
|
||||
; 8 ; 1 ;
|
||||
; 9 ; 1 ;
|
||||
; 10 ; 16 ;
|
||||
; 11 ; 0 ;
|
||||
; 12 ; 0 ;
|
||||
; 8 ; 3 ;
|
||||
; 9 ; 2 ;
|
||||
; 10 ; 11 ;
|
||||
; 11 ; 1 ;
|
||||
; 12 ; 1 ;
|
||||
; 13 ; 0 ;
|
||||
; 14 ; 0 ;
|
||||
; 15 ; 0 ;
|
||||
; 16 ; 1 ;
|
||||
; 14 ; 1 ;
|
||||
+---------------------------------------------+------------------------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------+
|
||||
; LAB Signals Sourced Out ;
|
||||
+-------------------------------------------------+------------------------------+
|
||||
; Number of Signals Sourced Out (Average = 6.04) ; Number of LABs (Total = 24) ;
|
||||
; Number of Signals Sourced Out (Average = 6.33) ; Number of LABs (Total = 24) ;
|
||||
+-------------------------------------------------+------------------------------+
|
||||
; 0 ; 0 ;
|
||||
; 1 ; 0 ;
|
||||
; 2 ; 1 ;
|
||||
; 3 ; 4 ;
|
||||
; 1 ; 2 ;
|
||||
; 2 ; 0 ;
|
||||
; 3 ; 2 ;
|
||||
; 4 ; 2 ;
|
||||
; 5 ; 1 ;
|
||||
; 6 ; 6 ;
|
||||
; 7 ; 4 ;
|
||||
; 8 ; 3 ;
|
||||
; 9 ; 1 ;
|
||||
; 10 ; 1 ;
|
||||
; 11 ; 1 ;
|
||||
; 5 ; 3 ;
|
||||
; 6 ; 4 ;
|
||||
; 7 ; 3 ;
|
||||
; 8 ; 2 ;
|
||||
; 9 ; 2 ;
|
||||
; 10 ; 3 ;
|
||||
; 11 ; 0 ;
|
||||
; 12 ; 1 ;
|
||||
+-------------------------------------------------+------------------------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------------+
|
||||
; LAB Distinct Inputs ;
|
||||
+----------------------------------------------+------------------------------+
|
||||
; Number of Distinct Inputs (Average = 10.25) ; Number of LABs (Total = 24) ;
|
||||
; Number of Distinct Inputs (Average = 10.42) ; Number of LABs (Total = 24) ;
|
||||
+----------------------------------------------+------------------------------+
|
||||
; 0 ; 0 ;
|
||||
; 1 ; 0 ;
|
||||
; 2 ; 0 ;
|
||||
; 3 ; 1 ;
|
||||
; 4 ; 2 ;
|
||||
; 3 ; 3 ;
|
||||
; 4 ; 0 ;
|
||||
; 5 ; 2 ;
|
||||
; 6 ; 1 ;
|
||||
; 7 ; 0 ;
|
||||
; 6 ; 2 ;
|
||||
; 7 ; 1 ;
|
||||
; 8 ; 3 ;
|
||||
; 9 ; 3 ;
|
||||
; 10 ; 1 ;
|
||||
; 9 ; 1 ;
|
||||
; 10 ; 0 ;
|
||||
; 11 ; 2 ;
|
||||
; 12 ; 2 ;
|
||||
; 13 ; 1 ;
|
||||
; 14 ; 0 ;
|
||||
; 15 ; 2 ;
|
||||
; 14 ; 2 ;
|
||||
; 15 ; 1 ;
|
||||
; 16 ; 1 ;
|
||||
; 17 ; 2 ;
|
||||
; 17 ; 1 ;
|
||||
; 18 ; 0 ;
|
||||
; 19 ; 1 ;
|
||||
; 20 ; 0 ;
|
||||
; 21 ; 0 ;
|
||||
; 22 ; 0 ;
|
||||
; 23 ; 0 ;
|
||||
; 24 ; 0 ;
|
||||
; 25 ; 1 ;
|
||||
+----------------------------------------------+------------------------------+
|
||||
|
||||
|
||||
@ -699,12 +701,10 @@ Info (332111): Found 3 clocks
|
||||
Info (332111): 69.841 C14M
|
||||
Info (332111): 200.000 DRCLK
|
||||
Info (186079): Completed User Assigned Global Signals Promotion Operation
|
||||
Info (186215): Automatically promoted signal "C14M" to use Global clock in PIN 12 File: Y:/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 8
|
||||
Info (186215): Automatically promoted signal "C14M" to use Global clock in PIN 12 File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 8
|
||||
Info (186079): Completed Auto Global Promotion Operation
|
||||
Info (176234): Starting register packing
|
||||
Info (186468): Started processing fast register assignments
|
||||
Warning (186473): Ignored the FAST_OUTPUT_REGISTER assignment made to the following nodes
|
||||
Warning (186483): Ignored assignment to node "nCS" because the DATAIN port is unconnected File: Y:/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 43
|
||||
Info (186469): Finished processing fast register assignments
|
||||
Info (176235): Finished register packing
|
||||
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
|
||||
@ -715,25 +715,25 @@ Info (170191): Fitter placement operations beginning
|
||||
Info (170137): Fitter placement was successful
|
||||
Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
|
||||
Info (170193): Fitter routing operations beginning
|
||||
Info (170089): 4e+01 ns of routing delay (approximately 2.5% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report.
|
||||
Info (170195): Router estimated average interconnect usage is 21% of the available device resources
|
||||
Info (170196): Router estimated peak interconnect usage is 21% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
|
||||
Info (170089): 5e+01 ns of routing delay (approximately 3.1% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report.
|
||||
Info (170195): Router estimated average interconnect usage is 20% of the available device resources
|
||||
Info (170196): Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
|
||||
Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
|
||||
Info (170201): Optimizations that may affect the design's routability were skipped
|
||||
Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
|
||||
Info (11888): Total time spent on timing analysis during the Fitter is 0.45 seconds.
|
||||
Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
|
||||
Info (11888): Total time spent on timing analysis during the Fitter is 0.83 seconds.
|
||||
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
|
||||
Info (144001): Generated suppressed messages file Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.fit.smsg
|
||||
Info: Quartus Prime Fitter was successful. 0 errors, 3 warnings
|
||||
Info: Peak virtual memory: 13750 megabytes
|
||||
Info: Processing ended: Tue Nov 21 06:54:39 2023
|
||||
Info: Elapsed time: 00:00:06
|
||||
Info (144001): Generated suppressed messages file /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.fit.smsg
|
||||
Info: Quartus Prime Fitter was successful. 0 errors, 1 warning
|
||||
Info: Peak virtual memory: 13770 megabytes
|
||||
Info: Processing ended: Thu Sep 21 05:34:37 2023
|
||||
Info: Elapsed time: 00:00:04
|
||||
Info: Total CPU time (on all processors): 00:00:04
|
||||
|
||||
|
||||
+----------------------------+
|
||||
; Fitter Suppressed Messages ;
|
||||
+----------------------------+
|
||||
The suppressed messages can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.fit.smsg.
|
||||
The suppressed messages can be found in /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.fit.smsg.
|
||||
|
||||
|
||||
|
||||
@ -1,11 +1,11 @@
|
||||
Fitter Status : Successful - Tue Nov 21 06:54:39 2023
|
||||
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
Fitter Status : Successful - Thu Sep 21 05:34:37 2023
|
||||
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Revision Name : RAM2E
|
||||
Top-level Entity Name : RAM2E
|
||||
Family : MAX II
|
||||
Device : EPM240T100C5
|
||||
Timing Models : Final
|
||||
Total logic elements : 209 / 240 ( 87 % )
|
||||
Total pins : 71 / 80 ( 89 % )
|
||||
Total logic elements : 197 / 240 ( 82 % )
|
||||
Total pins : 70 / 80 ( 88 % )
|
||||
Total virtual pins : 0
|
||||
UFM blocks : 1 / 1 ( 100 % )
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
Flow report for RAM2E
|
||||
Tue Nov 21 06:54:45 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
Thu Sep 21 05:34:45 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
|
||||
|
||||
---------------------
|
||||
@ -38,21 +38,21 @@ https://fpgasoftware.intel.com/eula.
|
||||
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------------+
|
||||
; Flow Summary ;
|
||||
+-----------------------+-------------------------------------------------------------+
|
||||
; Flow Status ; Successful - Tue Nov 21 06:54:42 2023 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
|
||||
; Revision Name ; RAM2E ;
|
||||
; Top-level Entity Name ; RAM2E ;
|
||||
; Family ; MAX II ;
|
||||
; Device ; EPM240T100C5 ;
|
||||
; Timing Models ; Final ;
|
||||
; Total logic elements ; 209 / 240 ( 87 % ) ;
|
||||
; Total pins ; 71 / 80 ( 89 % ) ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 1 / 1 ( 100 % ) ;
|
||||
+-----------------------+-------------------------------------------------------------+
|
||||
+---------------------------------------------------------------------+
|
||||
; Flow Summary ;
|
||||
+-----------------------+---------------------------------------------+
|
||||
; Flow Status ; Successful - Thu Sep 21 05:34:41 2023 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
||||
; Revision Name ; RAM2E ;
|
||||
; Top-level Entity Name ; RAM2E ;
|
||||
; Family ; MAX II ;
|
||||
; Device ; EPM240T100C5 ;
|
||||
; Timing Models ; Final ;
|
||||
; Total logic elements ; 197 / 240 ( 82 % ) ;
|
||||
; Total pins ; 70 / 80 ( 88 % ) ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 1 / 1 ( 100 % ) ;
|
||||
+-----------------------+---------------------------------------------+
|
||||
|
||||
|
||||
+-----------------------------------------+
|
||||
@ -60,7 +60,7 @@ https://fpgasoftware.intel.com/eula.
|
||||
+-------------------+---------------------+
|
||||
; Option ; Setting ;
|
||||
+-------------------+---------------------+
|
||||
; Start date & time ; 11/21/2023 06:54:05 ;
|
||||
; Start date & time ; 09/21/2023 05:33:57 ;
|
||||
; Main task ; Compilation ;
|
||||
; Revision Name ; RAM2E ;
|
||||
+-------------------+---------------------+
|
||||
@ -71,7 +71,7 @@ https://fpgasoftware.intel.com/eula.
|
||||
+---------------------------------------+------------------------------+---------------+-------------+------------+
|
||||
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
|
||||
+---------------------------------------+------------------------------+---------------+-------------+------------+
|
||||
; COMPILER_SIGNATURE_ID ; 121381084694.170056764503816 ; -- ; -- ; -- ;
|
||||
; COMPILER_SIGNATURE_ID ; 121381084694.169528883703908 ; -- ; -- ; -- ;
|
||||
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
|
||||
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
|
||||
; NUM_PARALLEL_PROCESSORS ; 4 ; -- ; -- ; -- ;
|
||||
@ -86,11 +86,11 @@ https://fpgasoftware.intel.com/eula.
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Analysis & Synthesis ; 00:00:28 ; 1.0 ; 13107 MB ; 00:00:45 ;
|
||||
; Fitter ; 00:00:06 ; 1.0 ; 13750 MB ; 00:00:04 ;
|
||||
; Assembler ; 00:00:01 ; 1.0 ; 13068 MB ; 00:00:01 ;
|
||||
; Timing Analyzer ; 00:00:02 ; 1.0 ; 13066 MB ; 00:00:01 ;
|
||||
; Total ; 00:00:37 ; -- ; -- ; 00:00:51 ;
|
||||
; Analysis & Synthesis ; 00:00:35 ; 1.0 ; 13144 MB ; 00:00:49 ;
|
||||
; Fitter ; 00:00:04 ; 1.0 ; 13770 MB ; 00:00:04 ;
|
||||
; Assembler ; 00:00:02 ; 1.0 ; 13091 MB ; 00:00:01 ;
|
||||
; Timing Analyzer ; 00:00:02 ; 1.0 ; 13089 MB ; 00:00:02 ;
|
||||
; Total ; 00:00:43 ; -- ; -- ; 00:00:56 ;
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
|
||||
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
<sld_project_info>
|
||||
<project>
|
||||
<hash md5_digest_80b="f1177731eb35f907c990"/>
|
||||
<hash md5_digest_80b="c40857e37f967e83d8af"/>
|
||||
</project>
|
||||
<file_info>
|
||||
<file device="EPM240T100C5" path="RAM2E.sof" usercode="0xFFFFFFFF"/>
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
Analysis & Synthesis report for RAM2E
|
||||
Tue Nov 21 06:54:32 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
Thu Sep 21 05:34:32 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
|
||||
|
||||
---------------------
|
||||
@ -43,19 +43,19 @@ https://fpgasoftware.intel.com/eula.
|
||||
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Summary ;
|
||||
+-----------------------------+-------------------------------------------------------------+
|
||||
; Analysis & Synthesis Status ; Successful - Tue Nov 21 06:54:32 2023 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
|
||||
; Revision Name ; RAM2E ;
|
||||
; Top-level Entity Name ; RAM2E ;
|
||||
; Family ; MAX II ;
|
||||
; Total logic elements ; 217 ;
|
||||
; Total pins ; 71 ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 1 / 1 ( 100 % ) ;
|
||||
+-----------------------------+-------------------------------------------------------------+
|
||||
+---------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Summary ;
|
||||
+-----------------------------+---------------------------------------------+
|
||||
; Analysis & Synthesis Status ; Successful - Thu Sep 21 05:34:32 2023 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
||||
; Revision Name ; RAM2E ;
|
||||
; Top-level Entity Name ; RAM2E ;
|
||||
; Family ; MAX II ;
|
||||
; Total logic elements ; 205 ;
|
||||
; Total pins ; 70 ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 1 / 1 ( 100 % ) ;
|
||||
+-----------------------------+---------------------------------------------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------------------------------------------------+
|
||||
@ -146,15 +146,15 @@ https://fpgasoftware.intel.com/eula.
|
||||
+----------------------------+-------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Source Files Read ;
|
||||
+----------------------------------+-----------------+----------------------------------+-----------------------------------+---------+
|
||||
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
|
||||
+----------------------------------+-----------------+----------------------------------+-----------------------------------+---------+
|
||||
; ../RAM2E-MAX.v ; yes ; User Verilog HDL File ; Y:/Repos/RAM2E/CPLD/RAM2E-MAX.v ; ;
|
||||
; UFM.v ; yes ; User Wizard-Generated File ; Y:/Repos/RAM2E/CPLD/MAXII/UFM.v ; ;
|
||||
; ../RAM2E-MAX.mif ; yes ; User Memory Initialization File ; Y:/Repos/RAM2E/CPLD/RAM2E-MAX.mif ; ;
|
||||
+----------------------------------+-----------------+----------------------------------+-----------------------------------+---------+
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Source Files Read ;
|
||||
+----------------------------------+-----------------+----------------------------------+-------------------------------------------+---------+
|
||||
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
|
||||
+----------------------------------+-----------------+----------------------------------+-------------------------------------------+---------+
|
||||
; ../RAM2E-MAX.v ; yes ; User Verilog HDL File ; //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-MAX.v ; ;
|
||||
; UFM.v ; yes ; User Wizard-Generated File ; //Mac/iCloud/Repos/RAM2E/CPLD/MAXII/UFM.v ; ;
|
||||
; ../RAM2E.mif ; yes ; User Memory Initialization File ; //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.mif ; ;
|
||||
+----------------------------------+-----------------+----------------------------------+-------------------------------------------+---------+
|
||||
|
||||
|
||||
+-----------------------------------------------------+
|
||||
@ -162,34 +162,34 @@ https://fpgasoftware.intel.com/eula.
|
||||
+---------------------------------------------+-------+
|
||||
; Resource ; Usage ;
|
||||
+---------------------------------------------+-------+
|
||||
; Total logic elements ; 217 ;
|
||||
; -- Combinational with no register ; 103 ;
|
||||
; Total logic elements ; 205 ;
|
||||
; -- Combinational with no register ; 93 ;
|
||||
; -- Register only ; 27 ;
|
||||
; -- Combinational with a register ; 87 ;
|
||||
; -- Combinational with a register ; 85 ;
|
||||
; ; ;
|
||||
; Logic element usage by number of LUT inputs ; ;
|
||||
; -- 4 input functions ; 99 ;
|
||||
; -- 3 input functions ; 33 ;
|
||||
; -- 2 input functions ; 53 ;
|
||||
; -- 1 input functions ; 4 ;
|
||||
; -- 4 input functions ; 103 ;
|
||||
; -- 3 input functions ; 29 ;
|
||||
; -- 2 input functions ; 42 ;
|
||||
; -- 1 input functions ; 3 ;
|
||||
; -- 0 input functions ; 1 ;
|
||||
; ; ;
|
||||
; Logic elements by mode ; ;
|
||||
; -- normal mode ; 203 ;
|
||||
; -- normal mode ; 191 ;
|
||||
; -- arithmetic mode ; 14 ;
|
||||
; -- qfbk mode ; 0 ;
|
||||
; -- register cascade mode ; 0 ;
|
||||
; -- synchronous clear/load mode ; 1 ;
|
||||
; -- asynchronous clear/load mode ; 0 ;
|
||||
; ; ;
|
||||
; Total registers ; 114 ;
|
||||
; Total registers ; 112 ;
|
||||
; Total logic cells in carry chains ; 15 ;
|
||||
; I/O pins ; 71 ;
|
||||
; I/O pins ; 70 ;
|
||||
; UFM blocks ; 1 ;
|
||||
; Maximum fan-out node ; C14M ;
|
||||
; Maximum fan-out ; 114 ;
|
||||
; Total fan-out ; 873 ;
|
||||
; Average fan-out ; 3.02 ;
|
||||
; Maximum fan-out ; 112 ;
|
||||
; Total fan-out ; 850 ;
|
||||
; Average fan-out ; 3.08 ;
|
||||
+---------------------------------------------+-------+
|
||||
|
||||
|
||||
@ -198,7 +198,7 @@ https://fpgasoftware.intel.com/eula.
|
||||
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+
|
||||
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
|
||||
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+
|
||||
; |RAM2E ; 217 (217) ; 114 ; 1 ; 71 ; 0 ; 103 (103) ; 27 (27) ; 87 (87) ; 15 (15) ; 0 (0) ; |RAM2E ; RAM2E ; work ;
|
||||
; |RAM2E ; 205 (205) ; 112 ; 1 ; 70 ; 0 ; 93 (93) ; 27 (27) ; 85 (85) ; 15 (15) ; 0 (0) ; |RAM2E ; RAM2E ; work ;
|
||||
; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|UFM:UFM_inst ; UFM ; work ;
|
||||
; |UFM_altufm_none_lbr:UFM_altufm_none_lbr_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component ; UFM_altufm_none_lbr ; work ;
|
||||
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+
|
||||
@ -219,12 +219,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
+----------------------------------------------+-------+
|
||||
; Statistic ; Value ;
|
||||
+----------------------------------------------+-------+
|
||||
; Total registers ; 114 ;
|
||||
; Total registers ; 112 ;
|
||||
; Number of registers using Synchronous Clear ; 1 ;
|
||||
; Number of registers using Synchronous Load ; 0 ;
|
||||
; Number of registers using Asynchronous Clear ; 0 ;
|
||||
; Number of registers using Asynchronous Load ; 0 ;
|
||||
; Number of registers using Clock Enable ; 63 ;
|
||||
; Number of registers using Clock Enable ; 60 ;
|
||||
; Number of registers using Preset ; 0 ;
|
||||
+----------------------------------------------+-------+
|
||||
|
||||
@ -234,12 +234,13 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
+----------------------------------------+---------+
|
||||
; Inverted Register ; Fan out ;
|
||||
+----------------------------------------+---------+
|
||||
; nCS~reg0 ; 1 ;
|
||||
; nRAS~reg0 ; 1 ;
|
||||
; nCAS~reg0 ; 1 ;
|
||||
; nRWE~reg0 ; 1 ;
|
||||
; DQML~reg0 ; 1 ;
|
||||
; DQMH~reg0 ; 1 ;
|
||||
; Total number of inverted registers = 5 ; ;
|
||||
; Total number of inverted registers = 6 ; ;
|
||||
+----------------------------------------+---------+
|
||||
|
||||
|
||||
@ -249,7 +250,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
|
||||
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
|
||||
; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |RAM2E|RA[0]~reg0 ;
|
||||
; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |RAM2E|S[1] ;
|
||||
; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |RAM2E|S[2] ;
|
||||
; 4:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |RAM2E|CS[0] ;
|
||||
; 4:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |RAM2E|RWMask[4] ;
|
||||
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
|
||||
@ -271,37 +272,35 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
+-------------------------------+
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime Analysis & Synthesis
|
||||
Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
Info: Processing started: Tue Nov 21 06:54:04 2023
|
||||
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Info: Processing started: Thu Sep 21 05:33:57 2023
|
||||
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E-MAXII -c RAM2E
|
||||
Info (20032): Parallel compilation is enabled and will use up to 4 processors
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file /repos/ram2e/cpld/ram2e-max.v
|
||||
Info (12023): Found entity 1: RAM2E File: Y:/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 1
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file //mac/icloud/repos/ram2e/cpld/ram2e-max.v
|
||||
Info (12023): Found entity 1: RAM2E File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 1
|
||||
Info (12021): Found 2 design units, including 2 entities, in source file ufm.v
|
||||
Info (12023): Found entity 1: UFM_altufm_none_lbr File: Y:/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 47
|
||||
Info (12023): Found entity 2: UFM File: Y:/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 166
|
||||
Info (12023): Found entity 1: UFM_altufm_none_lbr File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 47
|
||||
Info (12023): Found entity 2: UFM File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 166
|
||||
Info (12127): Elaborating entity "RAM2E" for the top level hierarchy
|
||||
Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst" File: Y:/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 98
|
||||
Info (12128): Elaborating entity "UFM_altufm_none_lbr" for hierarchy "UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component" File: Y:/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 217
|
||||
Warning (13024): Output pins are stuck at VCC or GND
|
||||
Warning (13410): Pin "nCS" is stuck at GND File: Y:/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 43
|
||||
Info (21057): Implemented 289 device resources after synthesis - the final resource count might be different
|
||||
Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst" File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 93
|
||||
Info (12128): Elaborating entity "UFM_altufm_none_lbr" for hierarchy "UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component" File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 217
|
||||
Info (21057): Implemented 276 device resources after synthesis - the final resource count might be different
|
||||
Info (21058): Implemented 22 input pins
|
||||
Info (21059): Implemented 41 output pins
|
||||
Info (21059): Implemented 40 output pins
|
||||
Info (21060): Implemented 8 bidirectional pins
|
||||
Info (21061): Implemented 217 logic cells
|
||||
Info (21061): Implemented 205 logic cells
|
||||
Info (21070): Implemented 1 User Flash Memory blocks
|
||||
Info (144001): Generated suppressed messages file Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.map.smsg
|
||||
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 2 warnings
|
||||
Info: Peak virtual memory: 13107 megabytes
|
||||
Info: Processing ended: Tue Nov 21 06:54:32 2023
|
||||
Info: Elapsed time: 00:00:28
|
||||
Info: Total CPU time (on all processors): 00:00:45
|
||||
Info (144001): Generated suppressed messages file /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.map.smsg
|
||||
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 0 warnings
|
||||
Info: Peak virtual memory: 13144 megabytes
|
||||
Info: Processing ended: Thu Sep 21 05:34:32 2023
|
||||
Info: Elapsed time: 00:00:35
|
||||
Info: Total CPU time (on all processors): 00:00:49
|
||||
|
||||
|
||||
+------------------------------------------+
|
||||
; Analysis & Synthesis Suppressed Messages ;
|
||||
+------------------------------------------+
|
||||
The suppressed messages can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.map.smsg.
|
||||
The suppressed messages can be found in /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.map.smsg.
|
||||
|
||||
|
||||
|
||||
@ -1,3 +1,3 @@
|
||||
Warning (10273): Verilog HDL warning at RAM2E-MAX.v(51): extended using "x" or "z" File: Y:/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 51
|
||||
Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: Y:/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 73
|
||||
Warning (10463): Verilog HDL Declaration warning at UFM.v(189): "program" is SystemVerilog-2005 keyword File: Y:/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 189
|
||||
Warning (10273): Verilog HDL warning at RAM2E-MAX.v(46): extended using "x" or "z" File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 46
|
||||
Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 73
|
||||
Warning (10463): Verilog HDL Declaration warning at UFM.v(189): "program" is SystemVerilog-2005 keyword File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 189
|
||||
|
||||
@ -1,9 +1,9 @@
|
||||
Analysis & Synthesis Status : Successful - Tue Nov 21 06:54:32 2023
|
||||
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
Analysis & Synthesis Status : Successful - Thu Sep 21 05:34:32 2023
|
||||
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Revision Name : RAM2E
|
||||
Top-level Entity Name : RAM2E
|
||||
Family : MAX II
|
||||
Total logic elements : 217
|
||||
Total pins : 71
|
||||
Total logic elements : 205
|
||||
Total pins : 70
|
||||
Total virtual pins : 0
|
||||
UFM blocks : 1 / 1 ( 100 % )
|
||||
|
||||
@ -58,7 +58,7 @@
|
||||
-- Pin directions (input, output or bidir) are based on device operating in user mode.
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
CHIP "RAM2E" ASSIGNED TO AN: EPM240T100C5
|
||||
|
||||
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
|
||||
@ -143,7 +143,7 @@ Dout[0] : 77 : output : 3.3-V LVCMOS :
|
||||
GND* : 78 : : : : 2 :
|
||||
GNDIO : 79 : gnd : : : :
|
||||
VCCIO2 : 80 : power : : 3.3V : 2 :
|
||||
RCLK : 81 : output : 3.3-V LVCMOS : : 2 : Y
|
||||
GND* : 81 : : : : 2 :
|
||||
GND* : 82 : : : : 2 :
|
||||
GND* : 83 : : : : 2 :
|
||||
Dout[6] : 84 : output : 3.3-V LVCMOS : : 2 : Y
|
||||
|
||||
Binary file not shown.
@ -1,6 +1,6 @@
|
||||
Timing Analyzer report for RAM2E
|
||||
Tue Nov 21 06:54:45 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
Thu Sep 21 05:34:45 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
|
||||
|
||||
---------------------
|
||||
@ -20,8 +20,8 @@ Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Editio
|
||||
12. Setup: 'DRCLK'
|
||||
13. Setup: 'ARCLK'
|
||||
14. Setup: 'C14M'
|
||||
15. Hold: 'DRCLK'
|
||||
16. Hold: 'ARCLK'
|
||||
15. Hold: 'ARCLK'
|
||||
16. Hold: 'DRCLK'
|
||||
17. Hold: 'C14M'
|
||||
18. Setup Transfers
|
||||
19. Hold Transfers
|
||||
@ -57,18 +57,18 @@ https://fpgasoftware.intel.com/eula.
|
||||
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------+
|
||||
; Timing Analyzer Summary ;
|
||||
+-----------------------+---------------------------------------------------------------------+
|
||||
; Quartus Prime Version ; Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
|
||||
; Timing Analyzer ; Legacy Timing Analyzer ;
|
||||
; Revision Name ; RAM2E ;
|
||||
; Device Family ; MAX II ;
|
||||
; Device Name ; EPM240T100C5 ;
|
||||
; Timing Models ; Final ;
|
||||
; Delay Model ; Slow Model ;
|
||||
; Rise/Fall Delays ; Unavailable ;
|
||||
+-----------------------+---------------------------------------------------------------------+
|
||||
+-----------------------------------------------------------------------------+
|
||||
; Timing Analyzer Summary ;
|
||||
+-----------------------+-----------------------------------------------------+
|
||||
; Quartus Prime Version ; Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
||||
; Timing Analyzer ; Legacy Timing Analyzer ;
|
||||
; Revision Name ; RAM2E ;
|
||||
; Device Family ; MAX II ;
|
||||
; Device Name ; EPM240T100C5 ;
|
||||
; Timing Models ; Final ;
|
||||
; Delay Model ; Slow Model ;
|
||||
; Rise/Fall Delays ; Unavailable ;
|
||||
+-----------------------+-----------------------------------------------------+
|
||||
|
||||
|
||||
+------------------------------------------+
|
||||
@ -84,7 +84,7 @@ https://fpgasoftware.intel.com/eula.
|
||||
; ; ;
|
||||
; Usage by Processor ; % Time Used ;
|
||||
; Processor 1 ; 100.0% ;
|
||||
; Processor 2 ; 0.0% ;
|
||||
; Processor 2 ; 0.2% ;
|
||||
+----------------------------+-------------+
|
||||
|
||||
|
||||
@ -93,8 +93,8 @@ https://fpgasoftware.intel.com/eula.
|
||||
+------------------+--------+--------------------------+
|
||||
; SDC File Path ; Status ; Read at ;
|
||||
+------------------+--------+--------------------------+
|
||||
; ../RAM2E.sdc ; OK ; Tue Nov 21 06:54:45 2023 ;
|
||||
; ../RAM2E-MAX.sdc ; OK ; Tue Nov 21 06:54:45 2023 ;
|
||||
; ../RAM2E.sdc ; OK ; Thu Sep 21 05:34:44 2023 ;
|
||||
; ../RAM2E-MAX.sdc ; OK ; Thu Sep 21 05:34:44 2023 ;
|
||||
+------------------+--------+--------------------------+
|
||||
|
||||
|
||||
@ -116,7 +116,7 @@ https://fpgasoftware.intel.com/eula.
|
||||
+-----------+-----------------+------------+------+
|
||||
; 10.0 MHz ; 10.0 MHz ; ARCLK ; ;
|
||||
; 10.0 MHz ; 10.0 MHz ; DRCLK ; ;
|
||||
; 61.24 MHz ; 61.24 MHz ; C14M ; ;
|
||||
; 61.13 MHz ; 61.13 MHz ; C14M ; ;
|
||||
+-----------+-----------------+------------+------+
|
||||
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
|
||||
|
||||
@ -126,9 +126,9 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
|
||||
+-------+---------+---------------+
|
||||
; Clock ; Slack ; End Point TNS ;
|
||||
+-------+---------+---------------+
|
||||
; DRCLK ; -23.270 ; -23.270 ;
|
||||
; ARCLK ; -23.257 ; -23.257 ;
|
||||
; C14M ; -5.695 ; -5.695 ;
|
||||
; DRCLK ; -23.265 ; -23.265 ;
|
||||
; ARCLK ; -23.125 ; -23.125 ;
|
||||
; C14M ; -8.026 ; -92.836 ;
|
||||
+-------+---------+---------------+
|
||||
|
||||
|
||||
@ -137,9 +137,9 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
|
||||
+-------+---------+---------------+
|
||||
; Clock ; Slack ; End Point TNS ;
|
||||
+-------+---------+---------------+
|
||||
; DRCLK ; -16.759 ; -16.759 ;
|
||||
; ARCLK ; -16.742 ; -16.742 ;
|
||||
; C14M ; 1.400 ; 0.000 ;
|
||||
; ARCLK ; -16.874 ; -16.874 ;
|
||||
; DRCLK ; -16.746 ; -16.746 ;
|
||||
; C14M ; 1.415 ; 0.000 ;
|
||||
+-------+---------+---------------+
|
||||
|
||||
|
||||
@ -171,8 +171,8 @@ No paths to report.
|
||||
+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; -23.270 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; DRCLK ; 0.001 ; -1.712 ; 1.559 ;
|
||||
; -23.240 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; DRCLK ; 0.001 ; -1.712 ; 1.529 ;
|
||||
; -23.265 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; DRCLK ; 0.001 ; -1.725 ; 1.541 ;
|
||||
; -23.253 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; DRCLK ; 0.001 ; -1.725 ; 1.529 ;
|
||||
; 100.000 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 200.000 ; 0.000 ; 80.000 ;
|
||||
+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
|
||||
@ -182,7 +182,7 @@ No paths to report.
|
||||
+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; -23.257 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M ; ARCLK ; 0.001 ; -1.729 ; 1.529 ;
|
||||
; -23.125 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M ; ARCLK ; 0.001 ; -1.597 ; 1.529 ;
|
||||
; 100.000 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 200.000 ; 0.000 ; 80.000 ;
|
||||
+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
|
||||
@ -192,236 +192,236 @@ No paths to report.
|
||||
+--------+---------------------------------------------------------------------------------------------+--------------+--------------+-------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+--------+---------------------------------------------------------------------------------------------+--------------+--------------+-------------+--------------+------------+------------+
|
||||
; -5.695 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; UFMD[7] ; DRCLK ; C14M ; 0.001 ; 1.712 ; 7.075 ;
|
||||
; 26.860 ; S[2] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.727 ;
|
||||
; 26.949 ; S[1] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.638 ;
|
||||
; 27.207 ; S[3] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.380 ;
|
||||
; 27.276 ; S[0] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.311 ;
|
||||
; 27.440 ; S[2] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.147 ;
|
||||
; 27.529 ; S[1] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.058 ;
|
||||
; 27.530 ; S[2] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.057 ;
|
||||
; 27.530 ; S[2] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.057 ;
|
||||
; 27.530 ; S[2] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.057 ;
|
||||
; 27.530 ; S[2] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.057 ;
|
||||
; 27.530 ; S[2] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.057 ;
|
||||
; 27.530 ; S[2] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.057 ;
|
||||
; 27.549 ; S[2] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.038 ;
|
||||
; 27.549 ; S[2] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.038 ;
|
||||
; 27.601 ; S[2] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.986 ;
|
||||
; 27.601 ; S[2] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.986 ;
|
||||
; 27.601 ; S[2] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.986 ;
|
||||
; 27.619 ; S[1] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.968 ;
|
||||
; 27.619 ; S[1] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.968 ;
|
||||
; 27.619 ; S[1] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.968 ;
|
||||
; 27.619 ; S[1] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.968 ;
|
||||
; 27.619 ; S[1] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.968 ;
|
||||
; 27.619 ; S[1] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.968 ;
|
||||
; 27.642 ; S[1] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.945 ;
|
||||
; 27.642 ; S[1] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.945 ;
|
||||
; 27.694 ; S[1] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.893 ;
|
||||
; 27.694 ; S[1] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.893 ;
|
||||
; 27.694 ; S[1] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.893 ;
|
||||
; 27.787 ; S[3] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.800 ;
|
||||
; 27.856 ; S[0] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.731 ;
|
||||
; 27.877 ; S[3] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.710 ;
|
||||
; 27.877 ; S[3] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.710 ;
|
||||
; 27.877 ; S[3] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.710 ;
|
||||
; 27.877 ; S[3] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.710 ;
|
||||
; 27.877 ; S[3] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.710 ;
|
||||
; 27.877 ; S[3] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.710 ;
|
||||
; 27.896 ; S[3] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.691 ;
|
||||
; 27.896 ; S[3] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.691 ;
|
||||
; 27.946 ; S[0] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.641 ;
|
||||
; 27.946 ; S[0] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.641 ;
|
||||
; 27.946 ; S[0] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.641 ;
|
||||
; 27.946 ; S[0] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.641 ;
|
||||
; 27.946 ; S[0] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.641 ;
|
||||
; 27.946 ; S[0] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.641 ;
|
||||
; 27.948 ; S[3] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.639 ;
|
||||
; 27.948 ; S[3] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.639 ;
|
||||
; 27.948 ; S[3] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.639 ;
|
||||
; 27.964 ; S[0] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.623 ;
|
||||
; 27.964 ; S[0] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.623 ;
|
||||
; 28.016 ; S[0] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.571 ;
|
||||
; 28.016 ; S[0] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.571 ;
|
||||
; 28.016 ; S[0] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.571 ;
|
||||
; 28.637 ; S[2] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.950 ;
|
||||
; 28.637 ; S[2] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.950 ;
|
||||
; 28.637 ; S[2] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.950 ;
|
||||
; 28.730 ; S[1] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.857 ;
|
||||
; 28.730 ; S[1] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.857 ;
|
||||
; 28.730 ; S[1] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.857 ;
|
||||
; 28.984 ; S[3] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.603 ;
|
||||
; 28.984 ; S[3] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.603 ;
|
||||
; 28.984 ; S[3] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.603 ;
|
||||
; 29.052 ; S[0] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.535 ;
|
||||
; 29.052 ; S[0] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.535 ;
|
||||
; 29.052 ; S[0] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.535 ;
|
||||
; 32.948 ; RCLKx1 ; RCLKx0 ; C14M ; C14M ; 34.921 ; 0.000 ; 1.640 ;
|
||||
; 53.511 ; FS[14] ; RA[10]~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 15.997 ;
|
||||
; 53.852 ; FS[15] ; RA[10]~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 15.656 ;
|
||||
; 54.656 ; FS[14] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 14.852 ;
|
||||
; 54.843 ; FS[14] ; nCAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 14.665 ;
|
||||
; 54.997 ; FS[15] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 14.511 ;
|
||||
; 55.184 ; FS[15] ; nCAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 14.324 ;
|
||||
; 55.303 ; S[2] ; UFMD[9] ; C14M ; C14M ; 69.841 ; 0.000 ; 14.205 ;
|
||||
; 55.303 ; S[2] ; UFMD[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 14.205 ;
|
||||
; 55.303 ; S[2] ; UFMD[8] ; C14M ; C14M ; 69.841 ; 0.000 ; 14.205 ;
|
||||
; 55.303 ; S[2] ; UFMD[13] ; C14M ; C14M ; 69.841 ; 0.000 ; 14.205 ;
|
||||
; 55.303 ; S[2] ; UFMD[14] ; C14M ; C14M ; 69.841 ; 0.000 ; 14.205 ;
|
||||
; 55.303 ; S[2] ; UFMD[12] ; C14M ; C14M ; 69.841 ; 0.000 ; 14.205 ;
|
||||
; 55.303 ; S[2] ; UFMD[10] ; C14M ; C14M ; 69.841 ; 0.000 ; 14.205 ;
|
||||
; 55.303 ; S[2] ; UFMD[11] ; C14M ; C14M ; 69.841 ; 0.000 ; 14.205 ;
|
||||
; 55.303 ; S[2] ; UFMD[15] ; C14M ; C14M ; 69.841 ; 0.000 ; 14.205 ;
|
||||
; 56.090 ; FS[14] ; nRWE~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 13.418 ;
|
||||
; 56.246 ; S[2] ; DRCLK ; C14M ; C14M ; 69.841 ; 0.000 ; 13.262 ;
|
||||
; 56.300 ; S[0] ; UFMD[9] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.208 ;
|
||||
; 56.300 ; S[0] ; UFMD[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.208 ;
|
||||
; 56.300 ; S[0] ; UFMD[8] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.208 ;
|
||||
; 56.300 ; S[0] ; UFMD[13] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.208 ;
|
||||
; 56.300 ; S[0] ; UFMD[14] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.208 ;
|
||||
; 56.300 ; S[0] ; UFMD[12] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.208 ;
|
||||
; 56.300 ; S[0] ; UFMD[10] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.208 ;
|
||||
; 56.300 ; S[0] ; UFMD[11] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.208 ;
|
||||
; 56.300 ; S[0] ; UFMD[15] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.208 ;
|
||||
; 56.431 ; FS[15] ; nRWE~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 13.077 ;
|
||||
; 56.445 ; S[2] ; RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.063 ;
|
||||
; 56.445 ; S[2] ; RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.063 ;
|
||||
; 56.445 ; S[2] ; RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.063 ;
|
||||
; 56.605 ; FS[11] ; RA[10]~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 12.903 ;
|
||||
; 56.743 ; FS[9] ; RA[10]~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 12.765 ;
|
||||
; 56.768 ; S[3] ; UFMD[9] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.740 ;
|
||||
; 56.768 ; S[3] ; UFMD[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.740 ;
|
||||
; -8.026 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RWMask[4] ; DRCLK ; C14M ; 0.001 ; 1.725 ; 9.419 ;
|
||||
; -8.026 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RWMask[5] ; DRCLK ; C14M ; 0.001 ; 1.725 ; 9.419 ;
|
||||
; -8.026 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RWMask[7] ; DRCLK ; C14M ; 0.001 ; 1.725 ; 9.419 ;
|
||||
; -8.026 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RWMask[0] ; DRCLK ; C14M ; 0.001 ; 1.725 ; 9.419 ;
|
||||
; -8.026 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RWMask[1] ; DRCLK ; C14M ; 0.001 ; 1.725 ; 9.419 ;
|
||||
; -8.026 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RWMask[2] ; DRCLK ; C14M ; 0.001 ; 1.725 ; 9.419 ;
|
||||
; -8.026 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RWMask[3] ; DRCLK ; C14M ; 0.001 ; 1.725 ; 9.419 ;
|
||||
; -8.026 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RWMask[6] ; DRCLK ; C14M ; 0.001 ; 1.725 ; 9.419 ;
|
||||
; -7.612 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; LEDEN ; DRCLK ; C14M ; 0.001 ; 1.725 ; 9.005 ;
|
||||
; -7.370 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; UFMInitDone ; DRCLK ; C14M ; 0.001 ; 1.725 ; 8.763 ;
|
||||
; -7.319 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; UFMReqErase ; DRCLK ; C14M ; 0.001 ; 1.725 ; 8.712 ;
|
||||
; -6.327 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; UFMD[8] ; DRCLK ; C14M ; 0.001 ; 1.725 ; 7.720 ;
|
||||
; 27.280 ; S[1] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.307 ;
|
||||
; 27.280 ; S[1] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.307 ;
|
||||
; 27.332 ; S[1] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.255 ;
|
||||
; 27.332 ; S[1] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.255 ;
|
||||
; 27.332 ; S[1] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.255 ;
|
||||
; 27.583 ; S[2] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.004 ;
|
||||
; 27.583 ; S[2] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.004 ;
|
||||
; 27.583 ; S[2] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.004 ;
|
||||
; 27.583 ; S[2] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.004 ;
|
||||
; 27.583 ; S[2] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.004 ;
|
||||
; 27.583 ; S[2] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.004 ;
|
||||
; 27.585 ; S[2] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.002 ;
|
||||
; 27.590 ; S[2] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.997 ;
|
||||
; 27.761 ; S[1] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.826 ;
|
||||
; 27.761 ; S[1] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.826 ;
|
||||
; 27.761 ; S[1] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.826 ;
|
||||
; 27.761 ; S[1] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.826 ;
|
||||
; 27.761 ; S[1] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.826 ;
|
||||
; 27.761 ; S[1] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.826 ;
|
||||
; 27.763 ; S[1] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.824 ;
|
||||
; 27.768 ; S[1] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.819 ;
|
||||
; 27.779 ; S[0] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.808 ;
|
||||
; 27.779 ; S[0] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.808 ;
|
||||
; 27.779 ; S[0] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.808 ;
|
||||
; 27.779 ; S[0] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.808 ;
|
||||
; 27.779 ; S[0] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.808 ;
|
||||
; 27.779 ; S[0] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.808 ;
|
||||
; 27.781 ; S[0] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.806 ;
|
||||
; 27.786 ; S[0] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.801 ;
|
||||
; 27.878 ; S[2] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.709 ;
|
||||
; 27.878 ; S[2] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.709 ;
|
||||
; 27.930 ; S[2] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.657 ;
|
||||
; 27.930 ; S[2] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.657 ;
|
||||
; 27.930 ; S[2] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.657 ;
|
||||
; 28.203 ; S[3] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.384 ;
|
||||
; 28.203 ; S[3] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.384 ;
|
||||
; 28.203 ; S[3] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.384 ;
|
||||
; 28.203 ; S[3] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.384 ;
|
||||
; 28.203 ; S[3] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.384 ;
|
||||
; 28.203 ; S[3] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.384 ;
|
||||
; 28.205 ; S[3] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.382 ;
|
||||
; 28.210 ; S[3] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.377 ;
|
||||
; 28.368 ; S[1] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.219 ;
|
||||
; 28.368 ; S[1] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.219 ;
|
||||
; 28.368 ; S[1] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.219 ;
|
||||
; 28.431 ; S[3] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.156 ;
|
||||
; 28.431 ; S[3] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.156 ;
|
||||
; 28.483 ; S[3] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.104 ;
|
||||
; 28.483 ; S[3] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.104 ;
|
||||
; 28.483 ; S[3] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.104 ;
|
||||
; 28.546 ; S[0] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.041 ;
|
||||
; 28.546 ; S[0] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.041 ;
|
||||
; 28.598 ; S[0] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.989 ;
|
||||
; 28.598 ; S[0] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.989 ;
|
||||
; 28.598 ; S[0] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.989 ;
|
||||
; 28.966 ; S[2] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.621 ;
|
||||
; 28.966 ; S[2] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.621 ;
|
||||
; 28.966 ; S[2] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.621 ;
|
||||
; 29.519 ; S[3] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.068 ;
|
||||
; 29.519 ; S[3] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.068 ;
|
||||
; 29.519 ; S[3] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.068 ;
|
||||
; 29.634 ; S[0] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.953 ;
|
||||
; 29.634 ; S[0] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.953 ;
|
||||
; 29.634 ; S[0] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.953 ;
|
||||
; 53.482 ; FS[15] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 16.026 ;
|
||||
; 53.855 ; FS[14] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 15.653 ;
|
||||
; 54.606 ; FS[15] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 14.902 ;
|
||||
; 54.773 ; FS[15] ; RA[10]~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 14.735 ;
|
||||
; 54.979 ; FS[14] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 14.529 ;
|
||||
; 55.110 ; FS[15] ; nCAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 14.398 ;
|
||||
; 55.146 ; FS[14] ; RA[10]~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 14.362 ;
|
||||
; 55.483 ; FS[14] ; nCAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 14.025 ;
|
||||
; 55.674 ; FS[11] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 13.834 ;
|
||||
; 55.804 ; FS[10] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 13.704 ;
|
||||
; 56.000 ; FS[8] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 13.508 ;
|
||||
; 56.341 ; FS[9] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 13.167 ;
|
||||
; 56.591 ; FS[12] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 12.917 ;
|
||||
; 56.798 ; FS[11] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 12.710 ;
|
||||
; 56.928 ; FS[10] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 12.580 ;
|
||||
; 56.931 ; FS[13] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 12.577 ;
|
||||
; 56.965 ; FS[11] ; RA[10]~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 12.543 ;
|
||||
; 56.994 ; S[2] ; RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.514 ;
|
||||
; 56.994 ; S[2] ; RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.514 ;
|
||||
; 56.994 ; S[2] ; RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.514 ;
|
||||
; 56.994 ; S[2] ; RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.514 ;
|
||||
; 56.994 ; S[2] ; RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.514 ;
|
||||
; 56.994 ; S[2] ; RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.514 ;
|
||||
; 56.994 ; S[2] ; RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.514 ;
|
||||
+--------+---------------------------------------------------------------------------------------------+--------------+--------------+-------------+--------------+------------+------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Hold: 'DRCLK' ;
|
||||
+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; -16.759 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; DRCLK ; 0.000 ; -1.712 ; 1.529 ;
|
||||
; -16.729 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; DRCLK ; 0.000 ; -1.712 ; 1.559 ;
|
||||
; 60.000 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 0.000 ; 0.000 ; 80.000 ;
|
||||
+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Hold: 'ARCLK' ;
|
||||
+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; -16.742 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M ; ARCLK ; 0.000 ; -1.729 ; 1.529 ;
|
||||
; -16.874 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M ; ARCLK ; 0.000 ; -1.597 ; 1.529 ;
|
||||
; 60.000 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 0.000 ; 0.000 ; 80.000 ;
|
||||
+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------------------------------------------------+
|
||||
; Hold: 'C14M' ;
|
||||
+-------+---------------+-------------------+--------------+-------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+-------+---------------+-------------------+--------------+-------------+--------------+------------+------------+
|
||||
; 1.400 ; UFMD[11] ; UFMD[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.621 ;
|
||||
; 1.425 ; UFMD[7] ; UFMD[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.646 ;
|
||||
; 1.678 ; CmdPrgmMAX ; CmdPrgmMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 1.899 ;
|
||||
; 1.680 ; CmdPrgmMAX ; CmdEraseMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 1.901 ;
|
||||
; 1.693 ; UFMReqErase ; UFMReqErase ; C14M ; C14M ; 0.000 ; 0.000 ; 1.914 ;
|
||||
; 1.695 ; CS[1] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.916 ;
|
||||
; 1.702 ; CS[1] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.923 ;
|
||||
; 1.710 ; FS[0] ; FS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.931 ;
|
||||
; 1.738 ; CS[0] ; CS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.959 ;
|
||||
; 1.739 ; CmdTout[0] ; CmdTout[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.960 ;
|
||||
; 1.741 ; CmdTout[0] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.962 ;
|
||||
; 1.898 ; DRDIn ; DRDIn ; C14M ; C14M ; 0.000 ; 0.000 ; 2.119 ;
|
||||
; 1.899 ; UFMD[9] ; UFMD[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.120 ;
|
||||
; 1.915 ; RWMask[2] ; RWBank[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.136 ;
|
||||
; 1.916 ; RWMask[5] ; RWBank[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.137 ;
|
||||
; 1.916 ; RWMask[3] ; RWBank[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.137 ;
|
||||
; 1.920 ; RWMask[4] ; RWBank[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.141 ;
|
||||
; 1.920 ; RWMask[1] ; RWBank[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.141 ;
|
||||
; 1.922 ; UFMD[14] ; UFMD[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.143 ;
|
||||
; 1.924 ; CmdTout[2] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.145 ;
|
||||
; 1.938 ; RCLKx1 ; RCLKx1 ; C14M ; C14M ; 0.000 ; 0.000 ; 2.159 ;
|
||||
; 1.951 ; LEDEN ; LEDEN ; C14M ; C14M ; 0.000 ; 0.000 ; 2.172 ;
|
||||
; 1.969 ; S[0] ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.190 ;
|
||||
; 2.085 ; CmdBitbangMAX ; DRCLKPulse ; C14M ; C14M ; 0.000 ; 0.000 ; 2.306 ;
|
||||
; 2.114 ; RWBank[5] ; BA[1]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 2.335 ;
|
||||
; 2.117 ; FS[5] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.338 ;
|
||||
; 2.126 ; FS[7] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.347 ;
|
||||
; 2.127 ; FS[15] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.348 ;
|
||||
; 2.134 ; FS[8] ; FS[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.355 ;
|
||||
; 2.143 ; FS[9] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.364 ;
|
||||
; 2.144 ; Ready ; Ready ; C14M ; C14M ; 0.000 ; 0.000 ; 2.365 ;
|
||||
; 2.144 ; UFMInitDone ; UFMInitDone ; C14M ; C14M ; 0.000 ; 0.000 ; 2.365 ;
|
||||
; 2.145 ; FS[10] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.366 ;
|
||||
; 2.157 ; PHI1reg ; S[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.378 ;
|
||||
; 2.160 ; UFMProgStart ; UFMProgStart ; C14M ; C14M ; 0.000 ; 0.000 ; 2.381 ;
|
||||
; 2.161 ; PHI1reg ; S[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.382 ;
|
||||
; 2.163 ; PHI1reg ; S[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.384 ;
|
||||
; 2.163 ; UFMProgStart ; UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 2.384 ;
|
||||
; 2.168 ; UFMD[8] ; UFMD[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.389 ;
|
||||
; 2.169 ; UFMProgStart ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 2.390 ;
|
||||
; 2.204 ; CS[0] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.425 ;
|
||||
; 2.213 ; CS[0] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.434 ;
|
||||
; 2.215 ; CmdTout[0] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.436 ;
|
||||
; 2.231 ; RWMask[0] ; RWBank[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.452 ;
|
||||
; 2.233 ; FS[11] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.454 ;
|
||||
; 2.234 ; RWMask[6] ; RWBank[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.455 ;
|
||||
; 2.236 ; UFMErase ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 2.457 ;
|
||||
; 2.248 ; FS[6] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.469 ;
|
||||
; 2.248 ; FS[14] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.469 ;
|
||||
; 2.248 ; FS[4] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.469 ;
|
||||
; 2.250 ; FS[1] ; FS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.471 ;
|
||||
; 2.259 ; FS[3] ; FS[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.480 ;
|
||||
; 2.260 ; CS[2] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.481 ;
|
||||
; 2.261 ; FS[13] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.482 ;
|
||||
; 2.261 ; FS[12] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.482 ;
|
||||
; 2.262 ; FS[2] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.483 ;
|
||||
; 2.290 ; CmdTout[1] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.511 ;
|
||||
; 2.295 ; RWSel ; RWSel ; C14M ; C14M ; 0.000 ; 0.000 ; 2.516 ;
|
||||
; 2.299 ; RWSel ; DRCLKPulse ; C14M ; C14M ; 0.000 ; 0.000 ; 2.520 ;
|
||||
; 2.305 ; CmdTout[1] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.526 ;
|
||||
; 2.325 ; RWMask[7] ; RWBank[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.546 ;
|
||||
; 2.523 ; UFMD[10] ; UFMD[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.744 ;
|
||||
; 2.529 ; RWBank[7] ; RA[8]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 2.750 ;
|
||||
; 2.687 ; RWBank[0] ; RA[8]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 2.908 ;
|
||||
; 2.706 ; S[3] ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.927 ;
|
||||
; 2.706 ; CmdEraseMAX ; CmdEraseMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 2.927 ;
|
||||
; 2.707 ; CmdEraseMAX ; CmdPrgmMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 2.928 ;
|
||||
; 2.731 ; CS[2] ; CmdSetRWBankFFMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 2.952 ;
|
||||
; 2.735 ; PHI1reg ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.956 ;
|
||||
; 2.868 ; UFMD[8] ; RWMask[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.089 ;
|
||||
; 2.913 ; UFMD[14] ; RWMask[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.134 ;
|
||||
; 2.919 ; UFMD[13] ; UFMD[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.140 ;
|
||||
; 2.924 ; RWSel ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.145 ;
|
||||
; 2.949 ; FS[5] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.170 ;
|
||||
; 2.966 ; FS[8] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.187 ;
|
||||
; 2.975 ; FS[9] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.196 ;
|
||||
; 2.977 ; FS[10] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.198 ;
|
||||
; 3.057 ; CS[0] ; CmdRWMaskSet ; C14M ; C14M ; 0.000 ; 0.000 ; 3.278 ;
|
||||
; 3.060 ; FS[5] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.281 ;
|
||||
; 3.063 ; CS[0] ; CmdSetRWBankFFMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 3.284 ;
|
||||
; 3.066 ; CS[0] ; CmdSetRWBankFFLED ; C14M ; C14M ; 0.000 ; 0.000 ; 3.287 ;
|
||||
; 3.077 ; FS[8] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.298 ;
|
||||
; 3.086 ; FS[9] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.307 ;
|
||||
; 3.088 ; FS[10] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.309 ;
|
||||
; 3.095 ; S[3] ; S[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.316 ;
|
||||
; 3.101 ; RWBank[1] ; RA[9]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.322 ;
|
||||
; 3.173 ; FS[11] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.394 ;
|
||||
; 3.188 ; FS[14] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.409 ;
|
||||
; 3.188 ; FS[4] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.409 ;
|
||||
; 3.188 ; FS[6] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.409 ;
|
||||
; 3.188 ; FS[8] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.409 ;
|
||||
; 3.190 ; FS[1] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.411 ;
|
||||
; 3.196 ; RWBank[3] ; RA[11]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.417 ;
|
||||
; 3.197 ; FS[9] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.418 ;
|
||||
; 3.199 ; FS[3] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.420 ;
|
||||
; 3.201 ; FS[13] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.422 ;
|
||||
; 3.234 ; UFMD[15] ; RWMask[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.455 ;
|
||||
; 3.237 ; FS[0] ; ARCLK ; C14M ; C14M ; 0.000 ; 0.000 ; 3.458 ;
|
||||
; 3.241 ; FS[0] ; Ready ; C14M ; C14M ; 0.000 ; 0.000 ; 3.462 ;
|
||||
; 3.242 ; RWSel ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.463 ;
|
||||
+-------+---------------+-------------------+--------------+-------------+--------------+------------+------------+
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Hold: 'DRCLK' ;
|
||||
+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; -16.746 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; DRCLK ; 0.000 ; -1.725 ; 1.529 ;
|
||||
; -16.734 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; DRCLK ; 0.000 ; -1.725 ; 1.541 ;
|
||||
; 60.000 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 0.000 ; 0.000 ; 80.000 ;
|
||||
+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------------+
|
||||
; Hold: 'C14M' ;
|
||||
+-------+-------------------+-------------+--------------+-------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+-------+-------------------+-------------+--------------+-------------+--------------+------------+------------+
|
||||
; 1.415 ; UFMD[12] ; UFMD[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.636 ;
|
||||
; 1.421 ; UFMD[11] ; UFMD[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.642 ;
|
||||
; 1.639 ; DRDIn ; DRDIn ; C14M ; C14M ; 0.000 ; 0.000 ; 1.860 ;
|
||||
; 1.639 ; FS[0] ; FS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.860 ;
|
||||
; 1.660 ; CmdTout[2] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.881 ;
|
||||
; 1.669 ; UFMD[10] ; UFMD[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.890 ;
|
||||
; 1.701 ; S[3] ; S[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.922 ;
|
||||
; 1.701 ; CS[2] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.922 ;
|
||||
; 1.730 ; S[0] ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.951 ;
|
||||
; 1.732 ; S[0] ; S[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.953 ;
|
||||
; 1.822 ; UFMD[8] ; UFMD[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.043 ;
|
||||
; 1.844 ; UFMD[9] ; UFMD[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.065 ;
|
||||
; 1.953 ; UFMInitDone ; UFMInitDone ; C14M ; C14M ; 0.000 ; 0.000 ; 2.174 ;
|
||||
; 1.981 ; CmdTout[1] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.202 ;
|
||||
; 1.991 ; CmdTout[0] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.212 ;
|
||||
; 2.107 ; LEDEN ; LEDEN ; C14M ; C14M ; 0.000 ; 0.000 ; 2.328 ;
|
||||
; 2.107 ; FS[7] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.328 ;
|
||||
; 2.107 ; CmdBitbangMAX ; DRCLKPulse ; C14M ; C14M ; 0.000 ; 0.000 ; 2.328 ;
|
||||
; 2.118 ; Ready ; Ready ; C14M ; C14M ; 0.000 ; 0.000 ; 2.339 ;
|
||||
; 2.126 ; FS[15] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.347 ;
|
||||
; 2.126 ; FS[5] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.347 ;
|
||||
; 2.134 ; FS[8] ; FS[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.355 ;
|
||||
; 2.138 ; CmdPrgmMAX ; CmdPrgmMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 2.359 ;
|
||||
; 2.143 ; CmdPrgmMAX ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 2.364 ;
|
||||
; 2.144 ; UFMErase ; UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 2.365 ;
|
||||
; 2.146 ; UFMProgram ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 2.367 ;
|
||||
; 2.152 ; FS[9] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.373 ;
|
||||
; 2.152 ; FS[10] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.373 ;
|
||||
; 2.162 ; S[2] ; S[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.383 ;
|
||||
; 2.165 ; CmdEraseMAX ; CmdEraseMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 2.386 ;
|
||||
; 2.199 ; CS[0] ; CS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.420 ;
|
||||
; 2.207 ; CS[0] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.428 ;
|
||||
; 2.218 ; CS[0] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.439 ;
|
||||
; 2.233 ; FS[11] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.454 ;
|
||||
; 2.247 ; FS[6] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.468 ;
|
||||
; 2.249 ; FS[14] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.470 ;
|
||||
; 2.260 ; FS[13] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.481 ;
|
||||
; 2.262 ; FS[12] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.483 ;
|
||||
; 2.268 ; FS[4] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.489 ;
|
||||
; 2.273 ; FS[1] ; FS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.494 ;
|
||||
; 2.290 ; FS[3] ; FS[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.511 ;
|
||||
; 2.291 ; CmdTout[1] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.512 ;
|
||||
; 2.295 ; FS[2] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.516 ;
|
||||
; 2.308 ; CmdTout[0] ; CmdTout[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.529 ;
|
||||
; 2.309 ; CmdTout[0] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.530 ;
|
||||
; 2.382 ; UFMReqErase ; UFMReqErase ; C14M ; C14M ; 0.000 ; 0.000 ; 2.603 ;
|
||||
; 2.390 ; S[1] ; S[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.611 ;
|
||||
; 2.448 ; UFMD[14] ; UFMD[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.669 ;
|
||||
; 2.455 ; CS[1] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.676 ;
|
||||
; 2.461 ; CS[1] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.682 ;
|
||||
; 2.622 ; RTPBusyReg ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 2.843 ;
|
||||
; 2.624 ; UFMBusyReg ; UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 2.845 ;
|
||||
; 2.626 ; RWBank[3] ; RA[11]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 2.847 ;
|
||||
; 2.645 ; UFMD[13] ; UFMD[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.866 ;
|
||||
; 2.655 ; PHI1reg ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.876 ;
|
||||
; 2.720 ; RWSel ; RWSel ; C14M ; C14M ; 0.000 ; 0.000 ; 2.941 ;
|
||||
; 2.732 ; UFMD[15] ; RWMask[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.953 ;
|
||||
; 2.766 ; RWSel ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.987 ;
|
||||
; 2.823 ; RWMask[3] ; RWBank[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.044 ;
|
||||
; 2.844 ; UFMD[9] ; RWMask[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.065 ;
|
||||
; 2.851 ; RWBank[5] ; BA[1]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.072 ;
|
||||
; 2.911 ; S[3] ; nCS~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.132 ;
|
||||
; 2.913 ; S[3] ; BA[0]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.134 ;
|
||||
; 2.952 ; RTPBusyReg ; UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 3.173 ;
|
||||
; 2.958 ; FS[5] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.179 ;
|
||||
; 2.966 ; FS[8] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.187 ;
|
||||
; 2.984 ; FS[9] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.205 ;
|
||||
; 2.984 ; FS[10] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.205 ;
|
||||
; 2.992 ; RWMask[2] ; RWBank[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.213 ;
|
||||
; 3.041 ; RWBank[0] ; RA[8]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.262 ;
|
||||
; 3.063 ; RWMask[0] ; RWBank[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.284 ;
|
||||
; 3.069 ; FS[5] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.290 ;
|
||||
; 3.077 ; FS[8] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.298 ;
|
||||
; 3.095 ; FS[10] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.316 ;
|
||||
; 3.095 ; FS[9] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.316 ;
|
||||
; 3.096 ; RWSel ; DRCLKPulse ; C14M ; C14M ; 0.000 ; 0.000 ; 3.317 ;
|
||||
; 3.098 ; RWSel ; CmdTout[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.319 ;
|
||||
; 3.118 ; S[0] ; DOEEN ; C14M ; C14M ; 0.000 ; 0.000 ; 3.339 ;
|
||||
; 3.134 ; RWBank[1] ; RA[9]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.355 ;
|
||||
; 3.163 ; UFMD[11] ; RWMask[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.384 ;
|
||||
; 3.168 ; DRCLKPulse ; DRCLK ; C14M ; C14M ; 0.000 ; 0.000 ; 3.389 ;
|
||||
; 3.170 ; RWBank[7] ; RA[8]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.391 ;
|
||||
; 3.173 ; FS[11] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.394 ;
|
||||
; 3.187 ; FS[6] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.408 ;
|
||||
; 3.188 ; FS[8] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.409 ;
|
||||
; 3.189 ; FS[14] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.410 ;
|
||||
; 3.189 ; RWMask[4] ; RWBank[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.410 ;
|
||||
; 3.200 ; FS[13] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.421 ;
|
||||
; 3.203 ; RWMask[1] ; RWBank[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.424 ;
|
||||
; 3.206 ; FS[9] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.427 ;
|
||||
; 3.208 ; FS[4] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.429 ;
|
||||
; 3.213 ; FS[1] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.434 ;
|
||||
; 3.218 ; CmdSetRWBankFFLED ; RWBank[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.439 ;
|
||||
; 3.222 ; CmdSetRWBankFFLED ; RWBank[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.443 ;
|
||||
; 3.230 ; FS[3] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.451 ;
|
||||
; 3.230 ; RWSel ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.451 ;
|
||||
; 3.236 ; S[0] ; nCS~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.457 ;
|
||||
; 3.241 ; UFMD[12] ; RWMask[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.462 ;
|
||||
; 3.274 ; UFMD[14] ; RWMask[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.495 ;
|
||||
; 3.299 ; FS[8] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.520 ;
|
||||
+-------+-------------------+-------------+--------------+-------------+--------------+------------+------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------+
|
||||
@ -431,8 +431,8 @@ No paths to report.
|
||||
+------------+----------+----------+----------+----------+----------+
|
||||
; ARCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ;
|
||||
; C14M ; ARCLK ; 1 ; 0 ; 0 ; 0 ;
|
||||
; C14M ; C14M ; 1715 ; 1 ; 64 ; 1 ;
|
||||
; DRCLK ; C14M ; 1 ; 0 ; 0 ; 0 ;
|
||||
; C14M ; C14M ; 1607 ; 0 ; 64 ; 0 ;
|
||||
; DRCLK ; C14M ; 13 ; 0 ; 0 ; 0 ;
|
||||
; C14M ; DRCLK ; 2 ; 0 ; 0 ; 0 ;
|
||||
; DRCLK ; DRCLK ; 1 ; 0 ; 0 ; 0 ;
|
||||
+------------+----------+----------+----------+----------+----------+
|
||||
@ -446,8 +446,8 @@ Entries labeled "false path" only account for clock-to-clock false paths and not
|
||||
+------------+----------+----------+----------+----------+----------+
|
||||
; ARCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ;
|
||||
; C14M ; ARCLK ; 1 ; 0 ; 0 ; 0 ;
|
||||
; C14M ; C14M ; 1715 ; 1 ; 64 ; 1 ;
|
||||
; DRCLK ; C14M ; 1 ; 0 ; 0 ; 0 ;
|
||||
; C14M ; C14M ; 1607 ; 0 ; 64 ; 0 ;
|
||||
; DRCLK ; C14M ; 13 ; 0 ; 0 ; 0 ;
|
||||
; C14M ; DRCLK ; 2 ; 0 ; 0 ; 0 ;
|
||||
; DRCLK ; DRCLK ; 1 ; 0 ; 0 ; 0 ;
|
||||
+------------+----------+----------+----------+----------+----------+
|
||||
@ -476,7 +476,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
||||
; Unconstrained Input Ports ; 29 ; 29 ;
|
||||
; Unconstrained Input Port Paths ; 169 ; 169 ;
|
||||
; Unconstrained Output Ports ; 48 ; 48 ;
|
||||
; Unconstrained Output Port Paths ; 69 ; 69 ;
|
||||
; Unconstrained Output Port Paths ; 67 ; 67 ;
|
||||
+---------------------------------+-------+------+
|
||||
|
||||
|
||||
@ -559,7 +559,6 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
||||
; RA[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RCLK ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RD[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RD[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RD[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
@ -577,6 +576,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
||||
; Vout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; Vout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nCAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nCS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nDOE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nRAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nRWE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
@ -652,7 +652,6 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
||||
; RA[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RCLK ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RD[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RD[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RD[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
@ -670,6 +669,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
||||
; Vout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; Vout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nCAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nCS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nDOE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nRAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nRWE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
@ -682,8 +682,8 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
||||
+--------------------------+
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime Timing Analyzer
|
||||
Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
Info: Processing started: Tue Nov 21 06:54:43 2023
|
||||
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Info: Processing started: Thu Sep 21 05:34:43 2023
|
||||
Info: Command: quartus_sta RAM2E-MAXII -c RAM2E
|
||||
Info: qsta_default_script.tcl version: #1
|
||||
Info (20032): Parallel compilation is enabled and will use up to 4 processors
|
||||
@ -698,18 +698,18 @@ Info: Can't run Report Timing Closure Recommendations. The current device family
|
||||
Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ARCLK are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
|
||||
Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: DRCLK are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
|
||||
Critical Warning (332148): Timing requirements not met
|
||||
Info (332146): Worst-case setup slack is -23.270
|
||||
Info (332146): Worst-case setup slack is -23.265
|
||||
Info (332119): Slack End Point TNS Clock
|
||||
Info (332119): ========= =================== =====================
|
||||
Info (332119): -23.270 -23.270 DRCLK
|
||||
Info (332119): -23.257 -23.257 ARCLK
|
||||
Info (332119): -5.695 -5.695 C14M
|
||||
Info (332146): Worst-case hold slack is -16.759
|
||||
Info (332119): -23.265 -23.265 DRCLK
|
||||
Info (332119): -23.125 -23.125 ARCLK
|
||||
Info (332119): -8.026 -92.836 C14M
|
||||
Info (332146): Worst-case hold slack is -16.874
|
||||
Info (332119): Slack End Point TNS Clock
|
||||
Info (332119): ========= =================== =====================
|
||||
Info (332119): -16.759 -16.759 DRCLK
|
||||
Info (332119): -16.742 -16.742 ARCLK
|
||||
Info (332119): 1.400 0.000 C14M
|
||||
Info (332119): -16.874 -16.874 ARCLK
|
||||
Info (332119): -16.746 -16.746 DRCLK
|
||||
Info (332119): 1.415 0.000 C14M
|
||||
Info (332140): No Recovery paths to report
|
||||
Info (332140): No Removal paths to report
|
||||
Info (332146): Worst-case minimum pulse width slack is 34.654
|
||||
@ -724,9 +724,9 @@ Warning (332009): The launch and latch times for the relationship between source
|
||||
Info (332102): Design is not fully constrained for setup requirements
|
||||
Info (332102): Design is not fully constrained for hold requirements
|
||||
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings
|
||||
Info: Peak virtual memory: 13066 megabytes
|
||||
Info: Processing ended: Tue Nov 21 06:54:45 2023
|
||||
Info: Peak virtual memory: 13089 megabytes
|
||||
Info: Processing ended: Thu Sep 21 05:34:45 2023
|
||||
Info: Elapsed time: 00:00:02
|
||||
Info: Total CPU time (on all processors): 00:00:01
|
||||
Info: Total CPU time (on all processors): 00:00:02
|
||||
|
||||
|
||||
|
||||
@ -3,27 +3,27 @@ Timing Analyzer Summary
|
||||
------------------------------------------------------------
|
||||
|
||||
Type : Setup 'DRCLK'
|
||||
Slack : -23.270
|
||||
TNS : -23.270
|
||||
Slack : -23.265
|
||||
TNS : -23.265
|
||||
|
||||
Type : Setup 'ARCLK'
|
||||
Slack : -23.257
|
||||
TNS : -23.257
|
||||
Slack : -23.125
|
||||
TNS : -23.125
|
||||
|
||||
Type : Setup 'C14M'
|
||||
Slack : -5.695
|
||||
TNS : -5.695
|
||||
|
||||
Type : Hold 'DRCLK'
|
||||
Slack : -16.759
|
||||
TNS : -16.759
|
||||
Slack : -8.026
|
||||
TNS : -92.836
|
||||
|
||||
Type : Hold 'ARCLK'
|
||||
Slack : -16.742
|
||||
TNS : -16.742
|
||||
Slack : -16.874
|
||||
TNS : -16.874
|
||||
|
||||
Type : Hold 'DRCLK'
|
||||
Slack : -16.746
|
||||
TNS : -16.746
|
||||
|
||||
Type : Hold 'C14M'
|
||||
Slack : 1.400
|
||||
Slack : 1.415
|
||||
TNS : 0.000
|
||||
|
||||
Type : Minimum Pulse Width 'C14M'
|
||||
|
||||
@ -42,7 +42,7 @@ set_global_assignment -name DEVICE 5M240ZT100C5
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY RAM2E
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 19.1.0
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "07:27:32 AUGUST 20, 2023"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 SP0.02std Lite Edition"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
@ -239,15 +239,9 @@ set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RD
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
|
||||
set_global_assignment -name VERILOG_FILE "../RAM2E-MAX.v"
|
||||
set_global_assignment -name QIP_FILE UFM.qip
|
||||
set_global_assignment -name MIF_FILE ../RAM2E-MAX.mif
|
||||
set_global_assignment -name MIF_FILE ../RAM2E.mif
|
||||
set_global_assignment -name SDC_FILE ../RAM2E.sdc
|
||||
set_global_assignment -name SDC_FILE "../RAM2E-MAX.sdc"
|
||||
set_location_assignment PIN_88 -to LED
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LED
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to LED
|
||||
set_location_assignment PIN_81 -to RCLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RCLK
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RCLK
|
||||
set_instance_assignment -name SLOW_SLEW_RATE OFF -to RCLK
|
||||
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RCLK
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RCLK
|
||||
Binary file not shown.
@ -34,7 +34,7 @@
|
||||
//https://fpgasoftware.intel.com/eula.
|
||||
|
||||
|
||||
//altufm_none CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="MAX V" ERASE_TIME=500000000 LPM_FILE="../RAM2E-MAX.mif" OSC_FREQUENCY=180000 PORT_ARCLKENA="PORT_UNUSED" PORT_DRCLKENA="PORT_UNUSED" PROGRAM_TIME=1600000 WIDTH_UFM_ADDRESS=9 arclk ardin arshft busy drclk drdin drdout drshft erase osc oscena program rtpbusy
|
||||
//altufm_none CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="MAX V" ERASE_TIME=500000000 LPM_FILE="../RAM2E.mif" OSC_FREQUENCY=180000 PORT_ARCLKENA="PORT_UNUSED" PORT_DRCLKENA="PORT_UNUSED" PROGRAM_TIME=1600000 WIDTH_UFM_ADDRESS=9 arclk ardin arshft busy drclk drdin drdout drshft erase osc oscena program rtpbusy
|
||||
//VERSION_BEGIN 19.1 cbx_a_gray2bin 2019:09:22:11:00:27:SJ cbx_a_graycounter 2019:09:22:11:00:27:SJ cbx_altufm_none 2019:09:22:11:00:28:SJ cbx_cycloneii 2019:09:22:11:00:28:SJ cbx_lpm_add_sub 2019:09:22:11:00:28:SJ cbx_lpm_compare 2019:09:22:11:00:28:SJ cbx_lpm_counter 2019:09:22:11:00:28:SJ cbx_lpm_decode 2019:09:22:11:00:28:SJ cbx_lpm_mux 2019:09:22:11:00:28:SJ cbx_maxii 2019:09:22:11:00:28:SJ cbx_mgl 2019:09:22:11:02:15:SJ cbx_nadder 2019:09:22:11:00:28:SJ cbx_stratix 2019:09:22:11:00:28:SJ cbx_stratixii 2019:09:22:11:00:28:SJ cbx_util_mgl 2019:09:22:11:00:28:SJ VERSION_END
|
||||
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
|
||||
// altera message_off 10463
|
||||
@ -118,7 +118,7 @@ module UFM_altufm_none_p8r
|
||||
defparam
|
||||
maxii_ufm_block1.address_width = 9,
|
||||
maxii_ufm_block1.erase_time = 500000000,
|
||||
maxii_ufm_block1.init_file = "../RAM2E-MAX.mif",
|
||||
maxii_ufm_block1.init_file = "../RAM2E.mif",
|
||||
maxii_ufm_block1.mem1 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
|
||||
maxii_ufm_block1.mem10 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
|
||||
maxii_ufm_block1.mem11 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
|
||||
@ -225,7 +225,7 @@ endmodule
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX V"
|
||||
// Retrieval info: CONSTANT: ERASE_TIME NUMERIC "500000000"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX V"
|
||||
// Retrieval info: CONSTANT: LPM_FILE STRING "../RAM2E-MAX.mif"
|
||||
// Retrieval info: CONSTANT: LPM_FILE STRING "../RAM2E.mif"
|
||||
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altufm_none"
|
||||
// Retrieval info: CONSTANT: OSC_FREQUENCY NUMERIC "180000"
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
Assembler report for RAM2E
|
||||
Tue Nov 21 06:54:42 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
Thu Sep 21 05:34:42 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
|
||||
|
||||
---------------------
|
||||
@ -10,7 +10,7 @@ Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Editio
|
||||
2. Assembler Summary
|
||||
3. Assembler Settings
|
||||
4. Assembler Generated Files
|
||||
5. Assembler Device Options: Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pof
|
||||
5. Assembler Device Options: /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pof
|
||||
6. Assembler Messages
|
||||
|
||||
|
||||
@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula.
|
||||
+---------------------------------------------------------------+
|
||||
; Assembler Summary ;
|
||||
+-----------------------+---------------------------------------+
|
||||
; Assembler Status ; Successful - Tue Nov 21 06:54:42 2023 ;
|
||||
; Assembler Status ; Successful - Thu Sep 21 05:34:42 2023 ;
|
||||
; Revision Name ; RAM2E ;
|
||||
; Top-level Entity Name ; RAM2E ;
|
||||
; Family ; MAX V ;
|
||||
@ -53,23 +53,23 @@ https://fpgasoftware.intel.com/eula.
|
||||
+--------+---------+---------------+
|
||||
|
||||
|
||||
+-------------------------------------------------+
|
||||
; Assembler Generated Files ;
|
||||
+-------------------------------------------------+
|
||||
; File Name ;
|
||||
+-------------------------------------------------+
|
||||
; Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pof ;
|
||||
+-------------------------------------------------+
|
||||
+-----------------------------------------------+
|
||||
; Assembler Generated Files ;
|
||||
+-----------------------------------------------+
|
||||
; File Name ;
|
||||
+-----------------------------------------------+
|
||||
; /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pof ;
|
||||
+-----------------------------------------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------+
|
||||
; Assembler Device Options: Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pof ;
|
||||
+----------------+----------------------------------------------------------+
|
||||
; Option ; Setting ;
|
||||
+----------------+----------------------------------------------------------+
|
||||
; JTAG usercode ; 0x0016BE3C ;
|
||||
; Checksum ; 0x0016C1A4 ;
|
||||
+----------------+----------------------------------------------------------+
|
||||
+-------------------------------------------------------------------------+
|
||||
; Assembler Device Options: /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pof ;
|
||||
+----------------+--------------------------------------------------------+
|
||||
; Option ; Setting ;
|
||||
+----------------+--------------------------------------------------------+
|
||||
; JTAG usercode ; 0x0016B5DB ;
|
||||
; Checksum ; 0x0016B84B ;
|
||||
+----------------+--------------------------------------------------------+
|
||||
|
||||
|
||||
+--------------------+
|
||||
@ -77,14 +77,14 @@ https://fpgasoftware.intel.com/eula.
|
||||
+--------------------+
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime Assembler
|
||||
Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
Info: Processing started: Tue Nov 21 06:54:41 2023
|
||||
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Info: Processing started: Thu Sep 21 05:34:41 2023
|
||||
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2E-MAXV -c RAM2E
|
||||
Info (115031): Writing out detailed assembly data for power analysis
|
||||
Info (115030): Assembler is generating device programming files
|
||||
Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings
|
||||
Info: Peak virtual memory: 13070 megabytes
|
||||
Info: Processing ended: Tue Nov 21 06:54:42 2023
|
||||
Info: Peak virtual memory: 13092 megabytes
|
||||
Info: Processing ended: Thu Sep 21 05:34:42 2023
|
||||
Info: Elapsed time: 00:00:01
|
||||
Info: Total CPU time (on all processors): 00:00:01
|
||||
|
||||
|
||||
@ -1 +1 @@
|
||||
Tue Nov 21 06:54:46 2023
|
||||
Thu Sep 21 05:34:47 2023
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
Fitter report for RAM2E
|
||||
Tue Nov 21 06:54:39 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
Thu Sep 21 05:34:38 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
|
||||
|
||||
---------------------
|
||||
@ -54,21 +54,21 @@ https://fpgasoftware.intel.com/eula.
|
||||
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------------+
|
||||
; Fitter Summary ;
|
||||
+-----------------------+-------------------------------------------------------------+
|
||||
; Fitter Status ; Successful - Tue Nov 21 06:54:39 2023 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
|
||||
; Revision Name ; RAM2E ;
|
||||
; Top-level Entity Name ; RAM2E ;
|
||||
; Family ; MAX V ;
|
||||
; Device ; 5M240ZT100C5 ;
|
||||
; Timing Models ; Final ;
|
||||
; Total logic elements ; 209 / 240 ( 87 % ) ;
|
||||
; Total pins ; 71 / 79 ( 90 % ) ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 1 / 1 ( 100 % ) ;
|
||||
+-----------------------+-------------------------------------------------------------+
|
||||
+---------------------------------------------------------------------+
|
||||
; Fitter Summary ;
|
||||
+-----------------------+---------------------------------------------+
|
||||
; Fitter Status ; Successful - Thu Sep 21 05:34:38 2023 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
||||
; Revision Name ; RAM2E ;
|
||||
; Top-level Entity Name ; RAM2E ;
|
||||
; Family ; MAX V ;
|
||||
; Device ; 5M240ZT100C5 ;
|
||||
; Timing Models ; Final ;
|
||||
; Total logic elements ; 197 / 240 ( 82 % ) ;
|
||||
; Total pins ; 70 / 79 ( 89 % ) ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 1 / 1 ( 100 % ) ;
|
||||
+-----------------------+---------------------------------------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------------------------------------------------------------+
|
||||
@ -135,14 +135,14 @@ https://fpgasoftware.intel.com/eula.
|
||||
; Usage by Processor ; % Time Used ;
|
||||
; Processor 1 ; 100.0% ;
|
||||
; Processor 2 ; 1.2% ;
|
||||
; Processors 3-4 ; 1.0% ;
|
||||
; Processors 3-4 ; 1.1% ;
|
||||
+----------------------------+-------------+
|
||||
|
||||
|
||||
+--------------+
|
||||
; Pin-Out File ;
|
||||
+--------------+
|
||||
The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pin.
|
||||
The pin-out file can be found in /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pin.
|
||||
|
||||
|
||||
+---------------------------------------------------------------------+
|
||||
@ -150,31 +150,31 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pin
|
||||
+---------------------------------------------+-----------------------+
|
||||
; Resource ; Usage ;
|
||||
+---------------------------------------------+-----------------------+
|
||||
; Total logic elements ; 209 / 240 ( 87 % ) ;
|
||||
; -- Combinational with no register ; 95 ;
|
||||
; Total logic elements ; 197 / 240 ( 82 % ) ;
|
||||
; -- Combinational with no register ; 85 ;
|
||||
; -- Register only ; 19 ;
|
||||
; -- Combinational with a register ; 95 ;
|
||||
; -- Combinational with a register ; 93 ;
|
||||
; ; ;
|
||||
; Logic element usage by number of LUT inputs ; ;
|
||||
; -- 4 input functions ; 99 ;
|
||||
; -- 3 input functions ; 33 ;
|
||||
; -- 2 input functions ; 53 ;
|
||||
; -- 1 input functions ; 4 ;
|
||||
; -- 4 input functions ; 103 ;
|
||||
; -- 3 input functions ; 29 ;
|
||||
; -- 2 input functions ; 42 ;
|
||||
; -- 1 input functions ; 3 ;
|
||||
; -- 0 input functions ; 1 ;
|
||||
; ; ;
|
||||
; Logic elements by mode ; ;
|
||||
; -- normal mode ; 195 ;
|
||||
; -- normal mode ; 183 ;
|
||||
; -- arithmetic mode ; 14 ;
|
||||
; -- qfbk mode ; 8 ;
|
||||
; -- register cascade mode ; 0 ;
|
||||
; -- synchronous clear/load mode ; 13 ;
|
||||
; -- synchronous clear/load mode ; 16 ;
|
||||
; -- asynchronous clear/load mode ; 0 ;
|
||||
; ; ;
|
||||
; Total registers ; 114 / 240 ( 48 % ) ;
|
||||
; Total registers ; 112 / 240 ( 47 % ) ;
|
||||
; Total LABs ; 24 / 24 ( 100 % ) ;
|
||||
; Logic elements in carry chains ; 15 ;
|
||||
; Virtual pins ; 0 ;
|
||||
; I/O pins ; 71 / 79 ( 90 % ) ;
|
||||
; I/O pins ; 70 / 79 ( 89 % ) ;
|
||||
; -- Clock pins ; 3 / 4 ( 75 % ) ;
|
||||
; ; ;
|
||||
; UFM blocks ; 1 / 1 ( 100 % ) ;
|
||||
@ -185,12 +185,12 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pin
|
||||
; Global signals ; 1 ;
|
||||
; -- Global clocks ; 1 / 4 ( 25 % ) ;
|
||||
; JTAGs ; 0 / 1 ( 0 % ) ;
|
||||
; Average interconnect usage (total/H/V) ; 23.1% / 23.3% / 22.8% ;
|
||||
; Peak interconnect usage (total/H/V) ; 23.1% / 23.3% / 22.8% ;
|
||||
; Maximum fan-out ; 114 ;
|
||||
; Highest non-global fan-out ; 36 ;
|
||||
; Total fan-out ; 872 ;
|
||||
; Average fan-out ; 3.10 ;
|
||||
; Average interconnect usage (total/H/V) ; 24.3% / 25.4% / 23.2% ;
|
||||
; Peak interconnect usage (total/H/V) ; 24.3% / 25.4% / 23.2% ;
|
||||
; Maximum fan-out ; 112 ;
|
||||
; Highest non-global fan-out ; 31 ;
|
||||
; Total fan-out ; 847 ;
|
||||
; Average fan-out ; 3.16 ;
|
||||
+---------------------------------------------+-----------------------+
|
||||
|
||||
|
||||
@ -207,16 +207,16 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pin
|
||||
; Ain[5] ; 34 ; 1 ; 3 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Ain[6] ; 39 ; 1 ; 5 ; 0 ; 3 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Ain[7] ; 53 ; 2 ; 8 ; 1 ; 3 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; C14M ; 12 ; 1 ; 1 ; 3 ; 3 ; 114 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[0] ; 38 ; 1 ; 4 ; 0 ; 0 ; 13 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[1] ; 40 ; 1 ; 5 ; 0 ; 2 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[2] ; 42 ; 1 ; 5 ; 0 ; 0 ; 12 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[3] ; 41 ; 1 ; 5 ; 0 ; 1 ; 11 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; C14M ; 12 ; 1 ; 1 ; 3 ; 3 ; 112 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[0] ; 38 ; 1 ; 4 ; 0 ; 0 ; 14 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[1] ; 40 ; 1 ; 5 ; 0 ; 2 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[2] ; 42 ; 1 ; 5 ; 0 ; 0 ; 13 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[3] ; 41 ; 1 ; 5 ; 0 ; 1 ; 12 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[4] ; 48 ; 1 ; 6 ; 0 ; 0 ; 9 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[5] ; 49 ; 1 ; 7 ; 0 ; 2 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[5] ; 49 ; 1 ; 7 ; 0 ; 2 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[6] ; 36 ; 1 ; 4 ; 0 ; 2 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[7] ; 35 ; 1 ; 3 ; 0 ; 0 ; 9 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; PHI1 ; 37 ; 1 ; 4 ; 0 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[7] ; 35 ; 1 ; 3 ; 0 ; 0 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; PHI1 ; 37 ; 1 ; 4 ; 0 ; 1 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; nC07X ; 52 ; 2 ; 8 ; 1 ; 4 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; nEN80 ; 28 ; 1 ; 2 ; 0 ; 1 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; nWE ; 51 ; 1 ; 7 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
@ -231,31 +231,30 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pin
|
||||
+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
|
||||
; BA[0] ; 6 ; 1 ; 1 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; BA[1] ; 14 ; 1 ; 1 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; CKE ; 4 ; 1 ; 1 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; CKE ; 4 ; 1 ; 1 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; DQMH ; 100 ; 2 ; 2 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; DQML ; 98 ; 2 ; 2 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Dout[0] ; 77 ; 2 ; 7 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Dout[1] ; 76 ; 2 ; 7 ; 5 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Dout[2] ; 74 ; 2 ; 8 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; Dout[1] ; 76 ; 2 ; 7 ; 5 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; Dout[2] ; 74 ; 2 ; 8 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Dout[3] ; 75 ; 2 ; 7 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Dout[4] ; 73 ; 2 ; 8 ; 4 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; Dout[5] ; 72 ; 2 ; 8 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Dout[6] ; 84 ; 2 ; 6 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Dout[7] ; 85 ; 2 ; 5 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; LED ; 88 ; 2 ; 5 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; RA[0] ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; RA[0] ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RA[10] ; 16 ; 1 ; 1 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RA[11] ; 7 ; 1 ; 1 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RA[1] ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RA[2] ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RA[3] ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RA[3] ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; RA[4] ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RA[5] ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RA[6] ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RA[7] ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RA[8] ; 17 ; 1 ; 1 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RA[9] ; 15 ; 1 ; 1 ; 2 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RCLK ; 81 ; 2 ; 6 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; RA[9] ; 15 ; 1 ; 1 ; 2 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; Vout[0] ; 70 ; 2 ; 8 ; 4 ; 4 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[1] ; 67 ; 2 ; 8 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[2] ; 69 ; 2 ; 8 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
@ -265,7 +264,7 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pin
|
||||
; Vout[6] ; 58 ; 2 ; 8 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; Vout[7] ; 57 ; 2 ; 8 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; nCAS ; 3 ; 1 ; 1 ; 4 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; nCS ; 8 ; 1 ; 1 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; nCS ; 8 ; 1 ; 1 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; nDOE ; 55 ; 2 ; 8 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; nRAS ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; nRWE ; 2 ; 1 ; 1 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
@ -295,7 +294,7 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pin
|
||||
; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
|
||||
+----------+-------------------+---------------+--------------+
|
||||
; 1 ; 38 / 38 ( 100 % ) ; 3.3V ; -- ;
|
||||
; 2 ; 33 / 41 ( 80 % ) ; 3.3V ; -- ;
|
||||
; 2 ; 32 / 41 ( 78 % ) ; 3.3V ; -- ;
|
||||
+----------+-------------------+---------------+--------------+
|
||||
|
||||
|
||||
@ -384,7 +383,7 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pin
|
||||
; 78 ; 64 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
|
||||
; 79 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
||||
; 80 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
|
||||
; 81 ; 65 ; 2 ; RCLK ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
|
||||
; 81 ; 65 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
|
||||
; 82 ; 66 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
|
||||
; 83 ; 67 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
|
||||
; 84 ; 68 ; 2 ; Dout[6] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
|
||||
@ -432,7 +431,7 @@ Note: User assignments will override these defaults. The user specified values a
|
||||
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+
|
||||
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
|
||||
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+
|
||||
; |RAM2E ; 209 (209) ; 114 ; 1 ; 71 ; 0 ; 95 (95) ; 19 (19) ; 95 (95) ; 15 (15) ; 8 (8) ; |RAM2E ; RAM2E ; work ;
|
||||
; |RAM2E ; 197 (197) ; 112 ; 1 ; 70 ; 0 ; 85 (85) ; 19 (19) ; 93 (93) ; 15 (15) ; 8 (8) ; |RAM2E ; RAM2E ; work ;
|
||||
; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|UFM:UFM_inst ; UFM ; work ;
|
||||
; |UFM_altufm_none_p8r:UFM_altufm_none_p8r_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component ; UFM_altufm_none_p8r ; work ;
|
||||
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+
|
||||
@ -444,7 +443,6 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
+---------+----------+---------------+
|
||||
; Name ; Pin Type ; Pad to Core 0 ;
|
||||
+---------+----------+---------------+
|
||||
; RCLK ; Output ; -- ;
|
||||
; LED ; Output ; -- ;
|
||||
; Dout[0] ; Output ; -- ;
|
||||
; Dout[1] ; Output ; -- ;
|
||||
@ -496,8 +494,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
; nEN80 ; Input ; (0) ;
|
||||
; nWE ; Input ; (0) ;
|
||||
; PHI1 ; Input ; (1) ;
|
||||
; C14M ; Input ; (0) ;
|
||||
; Din[0] ; Input ; (0) ;
|
||||
; C14M ; Input ; (0) ;
|
||||
; nWE80 ; Input ; (0) ;
|
||||
; Ain[0] ; Input ; (0) ;
|
||||
; Ain[1] ; Input ; (0) ;
|
||||
@ -518,23 +516,22 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
+---------+----------+---------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------+
|
||||
; Control Signals ;
|
||||
+--------------+-------------+---------+---------------+--------+----------------------+------------------+
|
||||
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
|
||||
+--------------+-------------+---------+---------------+--------+----------------------+------------------+
|
||||
; C14M ; PIN_12 ; 114 ; Clock ; yes ; Global Clock ; GCLK0 ;
|
||||
; CS[0]~2 ; LC_X6_Y3_N4 ; 3 ; Clock enable ; no ; -- ; -- ;
|
||||
; Equal17~1 ; LC_X4_Y3_N0 ; 16 ; Clock enable ; no ; -- ; -- ;
|
||||
; Equal17~2 ; LC_X7_Y2_N5 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; RA[0]~15 ; LC_X3_Y2_N3 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; RDOE ; LC_X3_Y3_N5 ; 8 ; Output enable ; no ; -- ; -- ;
|
||||
; RWMask~1 ; LC_X5_Y2_N1 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; S[2] ; LC_X6_Y2_N8 ; 22 ; Sync. clear ; no ; -- ; -- ;
|
||||
; UFMD[7]~0 ; LC_X4_Y1_N6 ; 9 ; Clock enable ; no ; -- ; -- ;
|
||||
; UFMProgram~3 ; LC_X3_Y2_N8 ; 2 ; Clock enable ; no ; -- ; -- ;
|
||||
; always4~10 ; LC_X6_Y4_N7 ; 16 ; Clock enable ; no ; -- ; -- ;
|
||||
+--------------+-------------+---------+---------------+--------+----------------------+------------------+
|
||||
+-------------------------------------------------------------------------------------------------------+
|
||||
; Control Signals ;
|
||||
+------------+-------------+---------+---------------+--------+----------------------+------------------+
|
||||
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
|
||||
+------------+-------------+---------+---------------+--------+----------------------+------------------+
|
||||
; C14M ; PIN_12 ; 112 ; Clock ; yes ; Global Clock ; GCLK0 ;
|
||||
; CS[0]~2 ; LC_X6_Y1_N1 ; 3 ; Clock enable ; no ; -- ; -- ;
|
||||
; Equal9~1 ; LC_X5_Y3_N0 ; 16 ; Clock enable ; no ; -- ; -- ;
|
||||
; Equal9~2 ; LC_X7_Y2_N5 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; RA[0]~15 ; LC_X2_Y2_N0 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; RDOE ; LC_X2_Y4_N6 ; 8 ; Output enable ; no ; -- ; -- ;
|
||||
; RWMask~1 ; LC_X4_Y1_N7 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; S[2] ; LC_X7_Y2_N1 ; 22 ; Sync. clear ; no ; -- ; -- ;
|
||||
; UFMD[15]~0 ; LC_X5_Y1_N1 ; 8 ; Clock enable ; no ; -- ; -- ;
|
||||
; always2~8 ; LC_X6_Y1_N2 ; 16 ; Clock enable ; no ; -- ; -- ;
|
||||
+------------+-------------+---------+---------------+--------+----------------------+------------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------+
|
||||
@ -542,7 +539,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
+------+----------+---------+----------------------+------------------+
|
||||
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
|
||||
+------+----------+---------+----------------------+------------------+
|
||||
; C14M ; PIN_12 ; 114 ; Global Clock ; GCLK0 ;
|
||||
; C14M ; PIN_12 ; 112 ; Global Clock ; GCLK0 ;
|
||||
+------+----------+---------+----------------------+------------------+
|
||||
|
||||
|
||||
@ -551,31 +548,31 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
+-----------------------+--------------------+
|
||||
; Routing Resource Type ; Usage ;
|
||||
+-----------------------+--------------------+
|
||||
; C4s ; 139 / 784 ( 18 % ) ;
|
||||
; Direct links ; 36 / 888 ( 4 % ) ;
|
||||
; C4s ; 146 / 784 ( 19 % ) ;
|
||||
; Direct links ; 31 / 888 ( 3 % ) ;
|
||||
; Global clocks ; 1 / 4 ( 25 % ) ;
|
||||
; LAB clocks ; 6 / 32 ( 19 % ) ;
|
||||
; LUT chains ; 4 / 216 ( 2 % ) ;
|
||||
; Local interconnects ; 283 / 888 ( 32 % ) ;
|
||||
; R4s ; 134 / 704 ( 19 % ) ;
|
||||
; Local interconnects ; 279 / 888 ( 31 % ) ;
|
||||
; R4s ; 144 / 704 ( 20 % ) ;
|
||||
+-----------------------+--------------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------+
|
||||
; LAB Logic Elements ;
|
||||
+--------------------------------------------+------------------------------+
|
||||
; Number of Logic Elements (Average = 8.71) ; Number of LABs (Total = 24) ;
|
||||
; Number of Logic Elements (Average = 8.21) ; Number of LABs (Total = 24) ;
|
||||
+--------------------------------------------+------------------------------+
|
||||
; 1 ; 0 ;
|
||||
; 2 ; 1 ;
|
||||
; 1 ; 2 ;
|
||||
; 2 ; 0 ;
|
||||
; 3 ; 1 ;
|
||||
; 4 ; 0 ;
|
||||
; 5 ; 0 ;
|
||||
; 5 ; 1 ;
|
||||
; 6 ; 1 ;
|
||||
; 7 ; 2 ;
|
||||
; 7 ; 1 ;
|
||||
; 8 ; 2 ;
|
||||
; 9 ; 2 ;
|
||||
; 10 ; 15 ;
|
||||
; 10 ; 14 ;
|
||||
+--------------------------------------------+------------------------------+
|
||||
|
||||
|
||||
@ -585,83 +582,84 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
; LAB-wide Signals (Average = 1.38) ; Number of LABs (Total = 24) ;
|
||||
+------------------------------------+------------------------------+
|
||||
; 1 Clock ; 22 ;
|
||||
; 1 Clock enable ; 8 ;
|
||||
; 2 Clock enables ; 3 ;
|
||||
; 1 Clock enable ; 10 ;
|
||||
; 2 Clock enables ; 1 ;
|
||||
+------------------------------------+------------------------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------+
|
||||
; LAB Signals Sourced ;
|
||||
+---------------------------------------------+------------------------------+
|
||||
; Number of Signals Sourced (Average = 8.96) ; Number of LABs (Total = 24) ;
|
||||
; Number of Signals Sourced (Average = 8.54) ; Number of LABs (Total = 24) ;
|
||||
+---------------------------------------------+------------------------------+
|
||||
; 0 ; 0 ;
|
||||
; 1 ; 0 ;
|
||||
; 2 ; 1 ;
|
||||
; 1 ; 2 ;
|
||||
; 2 ; 0 ;
|
||||
; 3 ; 1 ;
|
||||
; 4 ; 0 ;
|
||||
; 5 ; 0 ;
|
||||
; 5 ; 1 ;
|
||||
; 6 ; 1 ;
|
||||
; 7 ; 2 ;
|
||||
; 7 ; 0 ;
|
||||
; 8 ; 2 ;
|
||||
; 9 ; 2 ;
|
||||
; 10 ; 13 ;
|
||||
; 11 ; 0 ;
|
||||
; 12 ; 1 ;
|
||||
; 13 ; 0 ;
|
||||
; 14 ; 1 ;
|
||||
; 13 ; 1 ;
|
||||
+---------------------------------------------+------------------------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------+
|
||||
; LAB Signals Sourced Out ;
|
||||
+-------------------------------------------------+------------------------------+
|
||||
; Number of Signals Sourced Out (Average = 6.29) ; Number of LABs (Total = 24) ;
|
||||
; Number of Signals Sourced Out (Average = 6.25) ; Number of LABs (Total = 24) ;
|
||||
+-------------------------------------------------+------------------------------+
|
||||
; 0 ; 0 ;
|
||||
; 1 ; 1 ;
|
||||
; 1 ; 2 ;
|
||||
; 2 ; 0 ;
|
||||
; 3 ; 3 ;
|
||||
; 4 ; 1 ;
|
||||
; 5 ; 1 ;
|
||||
; 6 ; 8 ;
|
||||
; 7 ; 4 ;
|
||||
; 8 ; 4 ;
|
||||
; 9 ; 0 ;
|
||||
; 10 ; 0 ;
|
||||
; 11 ; 0 ;
|
||||
; 12 ; 2 ;
|
||||
; 3 ; 1 ;
|
||||
; 4 ; 2 ;
|
||||
; 5 ; 5 ;
|
||||
; 6 ; 2 ;
|
||||
; 7 ; 3 ;
|
||||
; 8 ; 5 ;
|
||||
; 9 ; 2 ;
|
||||
; 10 ; 1 ;
|
||||
; 11 ; 1 ;
|
||||
+-------------------------------------------------+------------------------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------------+
|
||||
; LAB Distinct Inputs ;
|
||||
+----------------------------------------------+------------------------------+
|
||||
; Number of Distinct Inputs (Average = 10.88) ; Number of LABs (Total = 24) ;
|
||||
; Number of Distinct Inputs (Average = 10.46) ; Number of LABs (Total = 24) ;
|
||||
+----------------------------------------------+------------------------------+
|
||||
; 0 ; 0 ;
|
||||
; 1 ; 1 ;
|
||||
; 1 ; 0 ;
|
||||
; 2 ; 0 ;
|
||||
; 3 ; 1 ;
|
||||
; 4 ; 1 ;
|
||||
; 3 ; 4 ;
|
||||
; 4 ; 0 ;
|
||||
; 5 ; 2 ;
|
||||
; 6 ; 1 ;
|
||||
; 7 ; 0 ;
|
||||
; 8 ; 0 ;
|
||||
; 6 ; 0 ;
|
||||
; 7 ; 1 ;
|
||||
; 8 ; 2 ;
|
||||
; 9 ; 2 ;
|
||||
; 10 ; 3 ;
|
||||
; 11 ; 3 ;
|
||||
; 12 ; 1 ;
|
||||
; 13 ; 2 ;
|
||||
; 12 ; 0 ;
|
||||
; 13 ; 1 ;
|
||||
; 14 ; 1 ;
|
||||
; 15 ; 1 ;
|
||||
; 16 ; 2 ;
|
||||
; 17 ; 1 ;
|
||||
; 18 ; 1 ;
|
||||
; 16 ; 1 ;
|
||||
; 17 ; 0 ;
|
||||
; 18 ; 0 ;
|
||||
; 19 ; 0 ;
|
||||
; 20 ; 0 ;
|
||||
; 21 ; 0 ;
|
||||
; 22 ; 1 ;
|
||||
; 21 ; 2 ;
|
||||
; 22 ; 0 ;
|
||||
; 23 ; 0 ;
|
||||
; 24 ; 0 ;
|
||||
; 25 ; 1 ;
|
||||
+----------------------------------------------+------------------------------+
|
||||
|
||||
|
||||
@ -706,15 +704,13 @@ Info (332111): Found 3 clocks
|
||||
Info (332111): 69.841 C14M
|
||||
Info (332111): 200.000 DRCLK
|
||||
Info (186079): Completed User Assigned Global Signals Promotion Operation
|
||||
Info (186215): Automatically promoted signal "C14M" to use Global clock in PIN 12 File: Y:/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 8
|
||||
Info (186215): Automatically promoted signal "C14M" to use Global clock in PIN 12 File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 8
|
||||
Info (186079): Completed Auto Global Promotion Operation
|
||||
Info (176234): Starting register packing
|
||||
Info (186468): Started processing fast register assignments
|
||||
Warning (186473): Ignored the FAST_OUTPUT_REGISTER assignment made to the following nodes
|
||||
Warning (186483): Ignored assignment to node "nCS" because the DATAIN port is unconnected File: Y:/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 43
|
||||
Info (186469): Finished processing fast register assignments
|
||||
Info (176235): Finished register packing
|
||||
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
|
||||
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00
|
||||
Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
|
||||
Info (170189): Fitter placement preparation operations beginning
|
||||
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
|
||||
@ -722,24 +718,25 @@ Info (170191): Fitter placement operations beginning
|
||||
Info (170137): Fitter placement was successful
|
||||
Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
|
||||
Info (170193): Fitter routing operations beginning
|
||||
Info (170195): Router estimated average interconnect usage is 20% of the available device resources
|
||||
Info (170196): Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
|
||||
Info (170089): 2e+01 ns of routing delay (approximately 1.0% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report.
|
||||
Info (170195): Router estimated average interconnect usage is 21% of the available device resources
|
||||
Info (170196): Router estimated peak interconnect usage is 21% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
|
||||
Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
|
||||
Info (170201): Optimizations that may affect the design's routability were skipped
|
||||
Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
|
||||
Info (11888): Total time spent on timing analysis during the Fitter is 0.46 seconds.
|
||||
Info (11888): Total time spent on timing analysis during the Fitter is 0.58 seconds.
|
||||
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
|
||||
Info (144001): Generated suppressed messages file Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.fit.smsg
|
||||
Info: Quartus Prime Fitter was successful. 0 errors, 3 warnings
|
||||
Info: Peak virtual memory: 13746 megabytes
|
||||
Info: Processing ended: Tue Nov 21 06:54:39 2023
|
||||
Info: Elapsed time: 00:00:06
|
||||
Info: Total CPU time (on all processors): 00:00:04
|
||||
Info (144001): Generated suppressed messages file /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.fit.smsg
|
||||
Info: Quartus Prime Fitter was successful. 0 errors, 1 warning
|
||||
Info: Peak virtual memory: 13770 megabytes
|
||||
Info: Processing ended: Thu Sep 21 05:34:39 2023
|
||||
Info: Elapsed time: 00:00:05
|
||||
Info: Total CPU time (on all processors): 00:00:03
|
||||
|
||||
|
||||
+----------------------------+
|
||||
; Fitter Suppressed Messages ;
|
||||
+----------------------------+
|
||||
The suppressed messages can be found in Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.fit.smsg.
|
||||
The suppressed messages can be found in /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.fit.smsg.
|
||||
|
||||
|
||||
|
||||
@ -1,11 +1,11 @@
|
||||
Fitter Status : Successful - Tue Nov 21 06:54:39 2023
|
||||
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
Fitter Status : Successful - Thu Sep 21 05:34:38 2023
|
||||
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Revision Name : RAM2E
|
||||
Top-level Entity Name : RAM2E
|
||||
Family : MAX V
|
||||
Device : 5M240ZT100C5
|
||||
Timing Models : Final
|
||||
Total logic elements : 209 / 240 ( 87 % )
|
||||
Total pins : 71 / 79 ( 90 % )
|
||||
Total logic elements : 197 / 240 ( 82 % )
|
||||
Total pins : 70 / 79 ( 89 % )
|
||||
Total virtual pins : 0
|
||||
UFM blocks : 1 / 1 ( 100 % )
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
Flow report for RAM2E
|
||||
Tue Nov 21 06:54:45 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
Thu Sep 21 05:34:46 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
|
||||
|
||||
---------------------
|
||||
@ -38,21 +38,21 @@ https://fpgasoftware.intel.com/eula.
|
||||
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------------+
|
||||
; Flow Summary ;
|
||||
+-----------------------+-------------------------------------------------------------+
|
||||
; Flow Status ; Successful - Tue Nov 21 06:54:42 2023 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
|
||||
; Revision Name ; RAM2E ;
|
||||
; Top-level Entity Name ; RAM2E ;
|
||||
; Family ; MAX V ;
|
||||
; Device ; 5M240ZT100C5 ;
|
||||
; Timing Models ; Final ;
|
||||
; Total logic elements ; 209 / 240 ( 87 % ) ;
|
||||
; Total pins ; 71 / 79 ( 90 % ) ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 1 / 1 ( 100 % ) ;
|
||||
+-----------------------+-------------------------------------------------------------+
|
||||
+---------------------------------------------------------------------+
|
||||
; Flow Summary ;
|
||||
+-----------------------+---------------------------------------------+
|
||||
; Flow Status ; Successful - Thu Sep 21 05:34:42 2023 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
||||
; Revision Name ; RAM2E ;
|
||||
; Top-level Entity Name ; RAM2E ;
|
||||
; Family ; MAX V ;
|
||||
; Device ; 5M240ZT100C5 ;
|
||||
; Timing Models ; Final ;
|
||||
; Total logic elements ; 197 / 240 ( 82 % ) ;
|
||||
; Total pins ; 70 / 79 ( 89 % ) ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 1 / 1 ( 100 % ) ;
|
||||
+-----------------------+---------------------------------------------+
|
||||
|
||||
|
||||
+-----------------------------------------+
|
||||
@ -60,7 +60,7 @@ https://fpgasoftware.intel.com/eula.
|
||||
+-------------------+---------------------+
|
||||
; Option ; Setting ;
|
||||
+-------------------+---------------------+
|
||||
; Start date & time ; 11/21/2023 06:54:06 ;
|
||||
; Start date & time ; 09/21/2023 05:34:00 ;
|
||||
; Main task ; Compilation ;
|
||||
; Revision Name ; RAM2E ;
|
||||
+-------------------+---------------------+
|
||||
@ -71,7 +71,7 @@ https://fpgasoftware.intel.com/eula.
|
||||
+-------------------------------+------------------------------+---------------+-------------+------------+
|
||||
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
|
||||
+-------------------------------+------------------------------+---------------+-------------+------------+
|
||||
; COMPILER_SIGNATURE_ID ; 121381084694.170056764601716 ; -- ; -- ; -- ;
|
||||
; COMPILER_SIGNATURE_ID ; 121381084694.169528883915840 ; -- ; -- ; -- ;
|
||||
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
|
||||
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
|
||||
; NUM_PARALLEL_PROCESSORS ; 4 ; -- ; -- ; -- ;
|
||||
@ -85,11 +85,11 @@ https://fpgasoftware.intel.com/eula.
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Analysis & Synthesis ; 00:00:27 ; 1.0 ; 13111 MB ; 00:00:43 ;
|
||||
; Fitter ; 00:00:06 ; 1.0 ; 13746 MB ; 00:00:04 ;
|
||||
; Assembler ; 00:00:01 ; 1.0 ; 13066 MB ; 00:00:01 ;
|
||||
; Timing Analyzer ; 00:00:02 ; 1.0 ; 13066 MB ; 00:00:02 ;
|
||||
; Total ; 00:00:36 ; -- ; -- ; 00:00:50 ;
|
||||
; Analysis & Synthesis ; 00:00:35 ; 1.0 ; 13144 MB ; 00:00:50 ;
|
||||
; Fitter ; 00:00:04 ; 1.0 ; 13770 MB ; 00:00:03 ;
|
||||
; Assembler ; 00:00:01 ; 1.0 ; 13091 MB ; 00:00:01 ;
|
||||
; Timing Analyzer ; 00:00:03 ; 1.0 ; 13092 MB ; 00:00:02 ;
|
||||
; Total ; 00:00:43 ; -- ; -- ; 00:00:56 ;
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
|
||||
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
<sld_project_info>
|
||||
<project>
|
||||
<hash md5_digest_80b="a200c32949da45b33c7d"/>
|
||||
<hash md5_digest_80b="ec04ae5d795b1a9f31d1"/>
|
||||
</project>
|
||||
<file_info>
|
||||
<file device="5M240ZT100C5" path="RAM2E.sof" usercode="0xFFFFFFFF"/>
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
Analysis & Synthesis report for RAM2E
|
||||
Tue Nov 21 06:54:32 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
Thu Sep 21 05:34:33 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
|
||||
|
||||
---------------------
|
||||
@ -43,19 +43,19 @@ https://fpgasoftware.intel.com/eula.
|
||||
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Summary ;
|
||||
+-----------------------------+-------------------------------------------------------------+
|
||||
; Analysis & Synthesis Status ; Successful - Tue Nov 21 06:54:32 2023 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
|
||||
; Revision Name ; RAM2E ;
|
||||
; Top-level Entity Name ; RAM2E ;
|
||||
; Family ; MAX V ;
|
||||
; Total logic elements ; 217 ;
|
||||
; Total pins ; 71 ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 1 / 1 ( 100 % ) ;
|
||||
+-----------------------------+-------------------------------------------------------------+
|
||||
+---------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Summary ;
|
||||
+-----------------------------+---------------------------------------------+
|
||||
; Analysis & Synthesis Status ; Successful - Thu Sep 21 05:34:33 2023 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
||||
; Revision Name ; RAM2E ;
|
||||
; Top-level Entity Name ; RAM2E ;
|
||||
; Family ; MAX V ;
|
||||
; Total logic elements ; 205 ;
|
||||
; Total pins ; 70 ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 1 / 1 ( 100 % ) ;
|
||||
+-----------------------------+---------------------------------------------+
|
||||
|
||||
|
||||
+------------------------------------------------------------------------------------------------------------+
|
||||
@ -146,15 +146,15 @@ https://fpgasoftware.intel.com/eula.
|
||||
+----------------------------+-------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Source Files Read ;
|
||||
+----------------------------------+-----------------+----------------------------------+-----------------------------------+---------+
|
||||
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
|
||||
+----------------------------------+-----------------+----------------------------------+-----------------------------------+---------+
|
||||
; ../RAM2E-MAX.v ; yes ; User Verilog HDL File ; Y:/Repos/RAM2E/CPLD/RAM2E-MAX.v ; ;
|
||||
; UFM.v ; yes ; User Wizard-Generated File ; Y:/Repos/RAM2E/CPLD/MAXV/UFM.v ; ;
|
||||
; ../RAM2E-MAX.mif ; yes ; User Memory Initialization File ; Y:/Repos/RAM2E/CPLD/RAM2E-MAX.mif ; ;
|
||||
+----------------------------------+-----------------+----------------------------------+-----------------------------------+---------+
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Source Files Read ;
|
||||
+----------------------------------+-----------------+----------------------------------+-------------------------------------------+---------+
|
||||
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
|
||||
+----------------------------------+-----------------+----------------------------------+-------------------------------------------+---------+
|
||||
; ../RAM2E-MAX.v ; yes ; User Verilog HDL File ; //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-MAX.v ; ;
|
||||
; UFM.v ; yes ; User Wizard-Generated File ; //Mac/iCloud/Repos/RAM2E/CPLD/MAXV/UFM.v ; ;
|
||||
; ../RAM2E.mif ; yes ; User Memory Initialization File ; //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.mif ; ;
|
||||
+----------------------------------+-----------------+----------------------------------+-------------------------------------------+---------+
|
||||
|
||||
|
||||
+-----------------------------------------------------+
|
||||
@ -162,34 +162,34 @@ https://fpgasoftware.intel.com/eula.
|
||||
+---------------------------------------------+-------+
|
||||
; Resource ; Usage ;
|
||||
+---------------------------------------------+-------+
|
||||
; Total logic elements ; 217 ;
|
||||
; -- Combinational with no register ; 103 ;
|
||||
; Total logic elements ; 205 ;
|
||||
; -- Combinational with no register ; 93 ;
|
||||
; -- Register only ; 27 ;
|
||||
; -- Combinational with a register ; 87 ;
|
||||
; -- Combinational with a register ; 85 ;
|
||||
; ; ;
|
||||
; Logic element usage by number of LUT inputs ; ;
|
||||
; -- 4 input functions ; 99 ;
|
||||
; -- 3 input functions ; 33 ;
|
||||
; -- 2 input functions ; 53 ;
|
||||
; -- 1 input functions ; 4 ;
|
||||
; -- 4 input functions ; 103 ;
|
||||
; -- 3 input functions ; 29 ;
|
||||
; -- 2 input functions ; 42 ;
|
||||
; -- 1 input functions ; 3 ;
|
||||
; -- 0 input functions ; 1 ;
|
||||
; ; ;
|
||||
; Logic elements by mode ; ;
|
||||
; -- normal mode ; 203 ;
|
||||
; -- normal mode ; 191 ;
|
||||
; -- arithmetic mode ; 14 ;
|
||||
; -- qfbk mode ; 0 ;
|
||||
; -- register cascade mode ; 0 ;
|
||||
; -- synchronous clear/load mode ; 1 ;
|
||||
; -- asynchronous clear/load mode ; 0 ;
|
||||
; ; ;
|
||||
; Total registers ; 114 ;
|
||||
; Total registers ; 112 ;
|
||||
; Total logic cells in carry chains ; 15 ;
|
||||
; I/O pins ; 71 ;
|
||||
; I/O pins ; 70 ;
|
||||
; UFM blocks ; 1 ;
|
||||
; Maximum fan-out node ; C14M ;
|
||||
; Maximum fan-out ; 114 ;
|
||||
; Total fan-out ; 873 ;
|
||||
; Average fan-out ; 3.02 ;
|
||||
; Maximum fan-out ; 112 ;
|
||||
; Total fan-out ; 850 ;
|
||||
; Average fan-out ; 3.08 ;
|
||||
+---------------------------------------------+-------+
|
||||
|
||||
|
||||
@ -198,7 +198,7 @@ https://fpgasoftware.intel.com/eula.
|
||||
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+
|
||||
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
|
||||
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+
|
||||
; |RAM2E ; 217 (217) ; 114 ; 1 ; 71 ; 0 ; 103 (103) ; 27 (27) ; 87 (87) ; 15 (15) ; 0 (0) ; |RAM2E ; RAM2E ; work ;
|
||||
; |RAM2E ; 205 (205) ; 112 ; 1 ; 70 ; 0 ; 93 (93) ; 27 (27) ; 85 (85) ; 15 (15) ; 0 (0) ; |RAM2E ; RAM2E ; work ;
|
||||
; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|UFM:UFM_inst ; UFM ; work ;
|
||||
; |UFM_altufm_none_p8r:UFM_altufm_none_p8r_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component ; UFM_altufm_none_p8r ; work ;
|
||||
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+
|
||||
@ -219,12 +219,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
+----------------------------------------------+-------+
|
||||
; Statistic ; Value ;
|
||||
+----------------------------------------------+-------+
|
||||
; Total registers ; 114 ;
|
||||
; Total registers ; 112 ;
|
||||
; Number of registers using Synchronous Clear ; 1 ;
|
||||
; Number of registers using Synchronous Load ; 0 ;
|
||||
; Number of registers using Asynchronous Clear ; 0 ;
|
||||
; Number of registers using Asynchronous Load ; 0 ;
|
||||
; Number of registers using Clock Enable ; 63 ;
|
||||
; Number of registers using Clock Enable ; 60 ;
|
||||
; Number of registers using Preset ; 0 ;
|
||||
+----------------------------------------------+-------+
|
||||
|
||||
@ -234,12 +234,13 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
+----------------------------------------+---------+
|
||||
; Inverted Register ; Fan out ;
|
||||
+----------------------------------------+---------+
|
||||
; nCS~reg0 ; 1 ;
|
||||
; nRAS~reg0 ; 1 ;
|
||||
; nCAS~reg0 ; 1 ;
|
||||
; nRWE~reg0 ; 1 ;
|
||||
; DQML~reg0 ; 1 ;
|
||||
; DQMH~reg0 ; 1 ;
|
||||
; Total number of inverted registers = 5 ; ;
|
||||
; Total number of inverted registers = 6 ; ;
|
||||
+----------------------------------------+---------+
|
||||
|
||||
|
||||
@ -249,7 +250,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
|
||||
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
|
||||
; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |RAM2E|RA[0]~reg0 ;
|
||||
; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |RAM2E|S[1] ;
|
||||
; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |RAM2E|S[2] ;
|
||||
; 4:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |RAM2E|CS[0] ;
|
||||
; 4:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |RAM2E|RWMask[4] ;
|
||||
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
|
||||
@ -271,37 +272,35 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
||||
+-------------------------------+
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime Analysis & Synthesis
|
||||
Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
Info: Processing started: Tue Nov 21 06:54:05 2023
|
||||
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Info: Processing started: Thu Sep 21 05:33:58 2023
|
||||
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E-MAXV -c RAM2E
|
||||
Info (20032): Parallel compilation is enabled and will use up to 4 processors
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file /repos/ram2e/cpld/ram2e-max.v
|
||||
Info (12023): Found entity 1: RAM2E File: Y:/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 1
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file //mac/icloud/repos/ram2e/cpld/ram2e-max.v
|
||||
Info (12023): Found entity 1: RAM2E File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 1
|
||||
Info (12021): Found 2 design units, including 2 entities, in source file ufm.v
|
||||
Info (12023): Found entity 1: UFM_altufm_none_p8r File: Y:/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 47
|
||||
Info (12023): Found entity 2: UFM File: Y:/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 166
|
||||
Info (12023): Found entity 1: UFM_altufm_none_p8r File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 47
|
||||
Info (12023): Found entity 2: UFM File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 166
|
||||
Info (12127): Elaborating entity "RAM2E" for the top level hierarchy
|
||||
Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst" File: Y:/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 98
|
||||
Info (12128): Elaborating entity "UFM_altufm_none_p8r" for hierarchy "UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component" File: Y:/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 217
|
||||
Warning (13024): Output pins are stuck at VCC or GND
|
||||
Warning (13410): Pin "nCS" is stuck at GND File: Y:/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 43
|
||||
Info (21057): Implemented 289 device resources after synthesis - the final resource count might be different
|
||||
Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst" File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 93
|
||||
Info (12128): Elaborating entity "UFM_altufm_none_p8r" for hierarchy "UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component" File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 217
|
||||
Info (21057): Implemented 276 device resources after synthesis - the final resource count might be different
|
||||
Info (21058): Implemented 22 input pins
|
||||
Info (21059): Implemented 41 output pins
|
||||
Info (21059): Implemented 40 output pins
|
||||
Info (21060): Implemented 8 bidirectional pins
|
||||
Info (21061): Implemented 217 logic cells
|
||||
Info (21061): Implemented 205 logic cells
|
||||
Info (21070): Implemented 1 User Flash Memory blocks
|
||||
Info (144001): Generated suppressed messages file Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.map.smsg
|
||||
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 2 warnings
|
||||
Info: Peak virtual memory: 13111 megabytes
|
||||
Info: Processing ended: Tue Nov 21 06:54:32 2023
|
||||
Info: Elapsed time: 00:00:27
|
||||
Info: Total CPU time (on all processors): 00:00:43
|
||||
Info (144001): Generated suppressed messages file /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.map.smsg
|
||||
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 0 warnings
|
||||
Info: Peak virtual memory: 13144 megabytes
|
||||
Info: Processing ended: Thu Sep 21 05:34:33 2023
|
||||
Info: Elapsed time: 00:00:35
|
||||
Info: Total CPU time (on all processors): 00:00:50
|
||||
|
||||
|
||||
+------------------------------------------+
|
||||
; Analysis & Synthesis Suppressed Messages ;
|
||||
+------------------------------------------+
|
||||
The suppressed messages can be found in Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.map.smsg.
|
||||
The suppressed messages can be found in /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.map.smsg.
|
||||
|
||||
|
||||
|
||||
@ -1,3 +1,3 @@
|
||||
Warning (10273): Verilog HDL warning at RAM2E-MAX.v(51): extended using "x" or "z" File: Y:/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 51
|
||||
Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: Y:/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 73
|
||||
Warning (10463): Verilog HDL Declaration warning at UFM.v(189): "program" is SystemVerilog-2005 keyword File: Y:/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 189
|
||||
Warning (10273): Verilog HDL warning at RAM2E-MAX.v(46): extended using "x" or "z" File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 46
|
||||
Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 73
|
||||
Warning (10463): Verilog HDL Declaration warning at UFM.v(189): "program" is SystemVerilog-2005 keyword File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 189
|
||||
|
||||
@ -1,9 +1,9 @@
|
||||
Analysis & Synthesis Status : Successful - Tue Nov 21 06:54:32 2023
|
||||
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
Analysis & Synthesis Status : Successful - Thu Sep 21 05:34:33 2023
|
||||
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Revision Name : RAM2E
|
||||
Top-level Entity Name : RAM2E
|
||||
Family : MAX V
|
||||
Total logic elements : 217
|
||||
Total pins : 71
|
||||
Total logic elements : 205
|
||||
Total pins : 70
|
||||
Total virtual pins : 0
|
||||
UFM blocks : 1 / 1 ( 100 % )
|
||||
|
||||
@ -58,7 +58,7 @@
|
||||
-- Pin directions (input, output or bidir) are based on device operating in user mode.
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
CHIP "RAM2E" ASSIGNED TO AN: 5M240ZT100C5
|
||||
|
||||
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
|
||||
@ -143,7 +143,7 @@ Dout[0] : 77 : output : 3.3-V LVCMOS :
|
||||
GND* : 78 : : : : 2 :
|
||||
GND : 79 : gnd : : : :
|
||||
VCCIO2 : 80 : power : : 3.3V : 2 :
|
||||
RCLK : 81 : output : 3.3-V LVCMOS : : 2 : Y
|
||||
GND* : 81 : : : : 2 :
|
||||
GND* : 82 : : : : 2 :
|
||||
GND* : 83 : : : : 2 :
|
||||
Dout[6] : 84 : output : 3.3-V LVCMOS : : 2 : Y
|
||||
|
||||
Binary file not shown.
@ -1,6 +1,6 @@
|
||||
Timing Analyzer report for RAM2E
|
||||
Tue Nov 21 06:54:45 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
Thu Sep 21 05:34:46 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
|
||||
|
||||
---------------------
|
||||
@ -57,18 +57,18 @@ https://fpgasoftware.intel.com/eula.
|
||||
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------------------------+
|
||||
; Timing Analyzer Summary ;
|
||||
+-----------------------+---------------------------------------------------------------------+
|
||||
; Quartus Prime Version ; Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
|
||||
; Timing Analyzer ; Legacy Timing Analyzer ;
|
||||
; Revision Name ; RAM2E ;
|
||||
; Device Family ; MAX V ;
|
||||
; Device Name ; 5M240ZT100C5 ;
|
||||
; Timing Models ; Final ;
|
||||
; Delay Model ; Slow Model ;
|
||||
; Rise/Fall Delays ; Unavailable ;
|
||||
+-----------------------+---------------------------------------------------------------------+
|
||||
+-----------------------------------------------------------------------------+
|
||||
; Timing Analyzer Summary ;
|
||||
+-----------------------+-----------------------------------------------------+
|
||||
; Quartus Prime Version ; Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
||||
; Timing Analyzer ; Legacy Timing Analyzer ;
|
||||
; Revision Name ; RAM2E ;
|
||||
; Device Family ; MAX V ;
|
||||
; Device Name ; 5M240ZT100C5 ;
|
||||
; Timing Models ; Final ;
|
||||
; Delay Model ; Slow Model ;
|
||||
; Rise/Fall Delays ; Unavailable ;
|
||||
+-----------------------+-----------------------------------------------------+
|
||||
|
||||
|
||||
+------------------------------------------+
|
||||
@ -84,7 +84,7 @@ https://fpgasoftware.intel.com/eula.
|
||||
; ; ;
|
||||
; Usage by Processor ; % Time Used ;
|
||||
; Processor 1 ; 100.0% ;
|
||||
; Processor 2 ; 0.1% ;
|
||||
; Processor 2 ; 0.0% ;
|
||||
+----------------------------+-------------+
|
||||
|
||||
|
||||
@ -93,8 +93,8 @@ https://fpgasoftware.intel.com/eula.
|
||||
+------------------+--------+--------------------------+
|
||||
; SDC File Path ; Status ; Read at ;
|
||||
+------------------+--------+--------------------------+
|
||||
; ../RAM2E.sdc ; OK ; Tue Nov 21 06:54:45 2023 ;
|
||||
; ../RAM2E-MAX.sdc ; OK ; Tue Nov 21 06:54:45 2023 ;
|
||||
; ../RAM2E.sdc ; OK ; Thu Sep 21 05:34:45 2023 ;
|
||||
; ../RAM2E-MAX.sdc ; OK ; Thu Sep 21 05:34:45 2023 ;
|
||||
+------------------+--------+--------------------------+
|
||||
|
||||
|
||||
@ -116,7 +116,7 @@ https://fpgasoftware.intel.com/eula.
|
||||
+-----------+-----------------+------------+------+
|
||||
; 10.0 MHz ; 10.0 MHz ; ARCLK ; ;
|
||||
; 10.0 MHz ; 10.0 MHz ; DRCLK ; ;
|
||||
; 26.52 MHz ; 26.52 MHz ; C14M ; ;
|
||||
; 25.52 MHz ; 25.52 MHz ; C14M ; ;
|
||||
+-----------+-----------------+------------+------+
|
||||
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
|
||||
|
||||
@ -126,9 +126,9 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
|
||||
+-------+---------+---------------+
|
||||
; Clock ; Slack ; End Point TNS ;
|
||||
+-------+---------+---------------+
|
||||
; DRCLK ; -25.523 ; -25.523 ;
|
||||
; ARCLK ; -25.433 ; -25.433 ;
|
||||
; C14M ; -10.080 ; -10.080 ;
|
||||
; DRCLK ; -24.019 ; -24.019 ;
|
||||
; ARCLK ; -23.863 ; -23.863 ;
|
||||
; C14M ; -15.767 ; -176.992 ;
|
||||
+-------+---------+---------------+
|
||||
|
||||
|
||||
@ -137,9 +137,9 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
|
||||
+-------+---------+---------------+
|
||||
; Clock ; Slack ; End Point TNS ;
|
||||
+-------+---------+---------------+
|
||||
; ARCLK ; -14.566 ; -14.566 ;
|
||||
; DRCLK ; -14.550 ; -14.550 ;
|
||||
; C14M ; 3.107 ; 0.000 ;
|
||||
; ARCLK ; -16.136 ; -16.136 ;
|
||||
; DRCLK ; -15.980 ; -15.980 ;
|
||||
; C14M ; 2.440 ; 0.000 ;
|
||||
+-------+---------+---------------+
|
||||
|
||||
|
||||
@ -171,8 +171,8 @@ No paths to report.
|
||||
+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; -25.523 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M ; DRCLK ; 0.001 ; -1.050 ; 4.474 ;
|
||||
; -25.449 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M ; DRCLK ; 0.001 ; -1.050 ; 4.400 ;
|
||||
; -24.019 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M ; DRCLK ; 0.001 ; -1.057 ; 2.963 ;
|
||||
; -24.019 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M ; DRCLK ; 0.001 ; -1.057 ; 2.963 ;
|
||||
; 100.000 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 200.000 ; 0.000 ; 80.000 ;
|
||||
+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
|
||||
@ -182,7 +182,7 @@ No paths to report.
|
||||
+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; -25.433 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M ; ARCLK ; 0.001 ; -1.042 ; 4.392 ;
|
||||
; -23.863 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M ; ARCLK ; 0.001 ; -0.901 ; 2.963 ;
|
||||
; 100.000 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 200.000 ; 0.000 ; 80.000 ;
|
||||
+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
|
||||
@ -192,106 +192,106 @@ No paths to report.
|
||||
+---------+---------------------------------------------------------------------------------------------+--------------+--------------+-------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+---------+---------------------------------------------------------------------------------------------+--------------+--------------+-------------+--------------+------------+------------+
|
||||
; -10.080 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; UFMD[7] ; DRCLK ; C14M ; 0.001 ; 1.050 ; 10.810 ;
|
||||
; 16.312 ; S[3] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 18.287 ;
|
||||
; 16.390 ; S[3] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 18.209 ;
|
||||
; 16.452 ; S[3] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 18.147 ;
|
||||
; 16.452 ; S[3] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 18.147 ;
|
||||
; 16.452 ; S[3] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 18.147 ;
|
||||
; 16.452 ; S[3] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 18.147 ;
|
||||
; 16.452 ; S[3] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 18.147 ;
|
||||
; 16.452 ; S[3] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 18.147 ;
|
||||
; 16.979 ; S[2] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.620 ;
|
||||
; 17.057 ; S[2] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.542 ;
|
||||
; 17.119 ; S[2] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.480 ;
|
||||
; 17.119 ; S[2] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.480 ;
|
||||
; 17.119 ; S[2] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.480 ;
|
||||
; 17.119 ; S[2] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.480 ;
|
||||
; 17.119 ; S[2] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.480 ;
|
||||
; 17.119 ; S[2] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.480 ;
|
||||
; 17.747 ; S[0] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.852 ;
|
||||
; 17.825 ; S[0] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.774 ;
|
||||
; 17.887 ; S[0] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.712 ;
|
||||
; 17.887 ; S[0] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.712 ;
|
||||
; 17.887 ; S[0] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.712 ;
|
||||
; 17.887 ; S[0] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.712 ;
|
||||
; 17.887 ; S[0] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.712 ;
|
||||
; 17.887 ; S[0] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.712 ;
|
||||
; 17.922 ; S[1] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.677 ;
|
||||
; 18.000 ; S[1] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.599 ;
|
||||
; 18.062 ; S[1] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.537 ;
|
||||
; 18.062 ; S[1] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.537 ;
|
||||
; 18.062 ; S[1] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.537 ;
|
||||
; 18.062 ; S[1] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.537 ;
|
||||
; 18.062 ; S[1] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.537 ;
|
||||
; 18.062 ; S[1] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.537 ;
|
||||
; 19.364 ; S[0] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.235 ;
|
||||
; 19.364 ; S[0] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.235 ;
|
||||
; 19.411 ; S[0] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.188 ;
|
||||
; 19.411 ; S[0] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.188 ;
|
||||
; 19.411 ; S[0] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.188 ;
|
||||
; 20.431 ; S[2] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 14.168 ;
|
||||
; 20.431 ; S[2] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 14.168 ;
|
||||
; 20.478 ; S[2] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 14.121 ;
|
||||
; 20.478 ; S[2] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 14.121 ;
|
||||
; 20.478 ; S[2] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 14.121 ;
|
||||
; 21.781 ; S[1] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.818 ;
|
||||
; 21.781 ; S[1] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.818 ;
|
||||
; 21.828 ; S[1] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.771 ;
|
||||
; 21.828 ; S[1] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.771 ;
|
||||
; 21.828 ; S[1] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.771 ;
|
||||
; 22.329 ; S[0] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.270 ;
|
||||
; 22.329 ; S[0] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.270 ;
|
||||
; 22.329 ; S[0] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.270 ;
|
||||
; 23.278 ; S[3] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.321 ;
|
||||
; 23.278 ; S[3] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.321 ;
|
||||
; 23.325 ; S[3] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.274 ;
|
||||
; 23.325 ; S[3] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.274 ;
|
||||
; 23.325 ; S[3] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.274 ;
|
||||
; 23.396 ; S[2] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.203 ;
|
||||
; 23.396 ; S[2] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.203 ;
|
||||
; 23.396 ; S[2] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.203 ;
|
||||
; 24.746 ; S[1] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 9.853 ;
|
||||
; 24.746 ; S[1] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 9.853 ;
|
||||
; 24.746 ; S[1] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 9.853 ;
|
||||
; 26.243 ; S[3] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 8.356 ;
|
||||
; 26.243 ; S[3] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 8.356 ;
|
||||
; 26.243 ; S[3] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 8.356 ;
|
||||
; 31.403 ; RCLKx1 ; RCLKx0 ; C14M ; C14M ; 34.921 ; 0.000 ; 3.197 ;
|
||||
; 32.128 ; FS[14] ; RA[10]~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 37.392 ;
|
||||
; 32.516 ; FS[14] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 37.004 ;
|
||||
; 32.522 ; FS[14] ; nCAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 36.998 ;
|
||||
; 33.737 ; FS[15] ; RA[10]~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 35.783 ;
|
||||
; 34.125 ; FS[15] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 35.395 ;
|
||||
; 34.131 ; FS[15] ; nCAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 35.389 ;
|
||||
; 34.931 ; FS[14] ; nRWE~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 34.589 ;
|
||||
; 35.247 ; UFMD[10] ; RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 34.273 ;
|
||||
; 35.247 ; UFMD[10] ; RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 34.273 ;
|
||||
; 35.247 ; UFMD[10] ; RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 34.273 ;
|
||||
; 35.247 ; UFMD[10] ; RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 34.273 ;
|
||||
; 35.247 ; UFMD[10] ; RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 34.273 ;
|
||||
; 35.247 ; UFMD[10] ; RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 34.273 ;
|
||||
; 35.247 ; UFMD[10] ; RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 34.273 ;
|
||||
; 35.247 ; UFMD[10] ; RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 34.273 ;
|
||||
; 35.722 ; S[3] ; RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 33.798 ;
|
||||
; 35.722 ; S[3] ; RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 33.798 ;
|
||||
; 35.722 ; S[3] ; RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 33.798 ;
|
||||
; 35.722 ; S[3] ; RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 33.798 ;
|
||||
; 35.722 ; S[3] ; RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 33.798 ;
|
||||
; 35.722 ; S[3] ; RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 33.798 ;
|
||||
; 35.722 ; S[3] ; RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 33.798 ;
|
||||
; 35.722 ; S[3] ; RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 33.798 ;
|
||||
; 36.008 ; UFMD[10] ; ARCLK ; C14M ; C14M ; 69.841 ; 0.000 ; 33.512 ;
|
||||
; 36.389 ; S[2] ; RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 33.131 ;
|
||||
; 36.389 ; S[2] ; RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 33.131 ;
|
||||
; 36.389 ; S[2] ; RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 33.131 ;
|
||||
; 36.389 ; S[2] ; RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 33.131 ;
|
||||
; 36.389 ; S[2] ; RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 33.131 ;
|
||||
; 36.389 ; S[2] ; RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 33.131 ;
|
||||
; 36.389 ; S[2] ; RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 33.131 ;
|
||||
; 36.389 ; S[2] ; RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 33.131 ;
|
||||
; 36.540 ; FS[15] ; nRWE~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 32.980 ;
|
||||
; 36.850 ; S[1] ; RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 32.670 ;
|
||||
; -15.767 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; UFMReqErase ; DRCLK ; C14M ; 0.001 ; 1.057 ; 16.504 ;
|
||||
; -15.215 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RWMask[4] ; DRCLK ; C14M ; 0.001 ; 1.057 ; 15.952 ;
|
||||
; -15.215 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RWMask[5] ; DRCLK ; C14M ; 0.001 ; 1.057 ; 15.952 ;
|
||||
; -15.215 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RWMask[7] ; DRCLK ; C14M ; 0.001 ; 1.057 ; 15.952 ;
|
||||
; -15.215 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RWMask[0] ; DRCLK ; C14M ; 0.001 ; 1.057 ; 15.952 ;
|
||||
; -15.215 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RWMask[1] ; DRCLK ; C14M ; 0.001 ; 1.057 ; 15.952 ;
|
||||
; -15.215 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RWMask[2] ; DRCLK ; C14M ; 0.001 ; 1.057 ; 15.952 ;
|
||||
; -15.215 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RWMask[3] ; DRCLK ; C14M ; 0.001 ; 1.057 ; 15.952 ;
|
||||
; -15.215 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RWMask[6] ; DRCLK ; C14M ; 0.001 ; 1.057 ; 15.952 ;
|
||||
; -14.411 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; LEDEN ; DRCLK ; C14M ; 0.001 ; 1.057 ; 15.148 ;
|
||||
; -13.177 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; UFMInitDone ; DRCLK ; C14M ; 0.001 ; 1.057 ; 13.914 ;
|
||||
; -11.917 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; UFMD[8] ; DRCLK ; C14M ; 0.001 ; 1.057 ; 12.654 ;
|
||||
; 16.803 ; S[1] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.796 ;
|
||||
; 16.803 ; S[1] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.796 ;
|
||||
; 16.803 ; S[1] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.796 ;
|
||||
; 16.803 ; S[1] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.796 ;
|
||||
; 16.803 ; S[1] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.796 ;
|
||||
; 16.803 ; S[1] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.796 ;
|
||||
; 16.806 ; S[1] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.793 ;
|
||||
; 16.809 ; S[1] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.790 ;
|
||||
; 18.727 ; S[2] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.872 ;
|
||||
; 18.727 ; S[2] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.872 ;
|
||||
; 18.727 ; S[2] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.872 ;
|
||||
; 18.727 ; S[2] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.872 ;
|
||||
; 18.727 ; S[2] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.872 ;
|
||||
; 18.727 ; S[2] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.872 ;
|
||||
; 18.730 ; S[2] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.869 ;
|
||||
; 18.733 ; S[2] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.866 ;
|
||||
; 19.149 ; S[3] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.450 ;
|
||||
; 19.149 ; S[3] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.450 ;
|
||||
; 19.196 ; S[3] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.403 ;
|
||||
; 19.196 ; S[3] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.403 ;
|
||||
; 19.196 ; S[3] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.403 ;
|
||||
; 19.260 ; S[0] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.339 ;
|
||||
; 19.260 ; S[0] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.339 ;
|
||||
; 19.307 ; S[0] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.292 ;
|
||||
; 19.307 ; S[0] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.292 ;
|
||||
; 19.307 ; S[0] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.292 ;
|
||||
; 20.893 ; S[0] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.706 ;
|
||||
; 20.893 ; S[0] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.706 ;
|
||||
; 20.893 ; S[0] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.706 ;
|
||||
; 20.893 ; S[0] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.706 ;
|
||||
; 20.893 ; S[0] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.706 ;
|
||||
; 20.893 ; S[0] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.706 ;
|
||||
; 20.896 ; S[0] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.703 ;
|
||||
; 20.899 ; S[0] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.700 ;
|
||||
; 22.101 ; S[3] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.498 ;
|
||||
; 22.101 ; S[3] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.498 ;
|
||||
; 22.101 ; S[3] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.498 ;
|
||||
; 22.212 ; S[0] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.387 ;
|
||||
; 22.212 ; S[0] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.387 ;
|
||||
; 22.212 ; S[0] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.387 ;
|
||||
; 23.092 ; S[3] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.507 ;
|
||||
; 23.092 ; S[3] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.507 ;
|
||||
; 23.092 ; S[3] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.507 ;
|
||||
; 23.092 ; S[3] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.507 ;
|
||||
; 23.092 ; S[3] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.507 ;
|
||||
; 23.092 ; S[3] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.507 ;
|
||||
; 23.095 ; S[3] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.504 ;
|
||||
; 23.098 ; S[3] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.501 ;
|
||||
; 23.710 ; S[1] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.889 ;
|
||||
; 23.710 ; S[1] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.889 ;
|
||||
; 23.757 ; S[1] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.842 ;
|
||||
; 23.757 ; S[1] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.842 ;
|
||||
; 23.757 ; S[1] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.842 ;
|
||||
; 24.349 ; S[2] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.250 ;
|
||||
; 24.349 ; S[2] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.250 ;
|
||||
; 24.396 ; S[2] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.203 ;
|
||||
; 24.396 ; S[2] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.203 ;
|
||||
; 24.396 ; S[2] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.203 ;
|
||||
; 26.662 ; S[1] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.937 ;
|
||||
; 26.662 ; S[1] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.937 ;
|
||||
; 26.662 ; S[1] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.937 ;
|
||||
; 27.301 ; S[2] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.298 ;
|
||||
; 27.301 ; S[2] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.298 ;
|
||||
; 27.301 ; S[2] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.298 ;
|
||||
; 30.659 ; FS[15] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 38.861 ;
|
||||
; 31.593 ; FS[14] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 37.927 ;
|
||||
; 32.392 ; FS[15] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 37.128 ;
|
||||
; 32.513 ; FS[2] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 37.007 ;
|
||||
; 33.326 ; FS[14] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 36.194 ;
|
||||
; 33.452 ; FS[15] ; nCAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 36.068 ;
|
||||
; 33.715 ; S[1] ; CmdEraseMAX ; C14M ; C14M ; 69.841 ; 0.000 ; 35.805 ;
|
||||
; 34.111 ; FS[1] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 35.409 ;
|
||||
; 34.246 ; FS[2] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 35.274 ;
|
||||
; 34.386 ; FS[14] ; nCAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 35.134 ;
|
||||
; 35.112 ; FS[11] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 34.408 ;
|
||||
; 35.288 ; FS[10] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 34.232 ;
|
||||
; 35.392 ; S[1] ; CmdPrgmMAX ; C14M ; C14M ; 69.841 ; 0.000 ; 34.128 ;
|
||||
; 35.639 ; S[2] ; CmdEraseMAX ; C14M ; C14M ; 69.841 ; 0.000 ; 33.881 ;
|
||||
; 35.844 ; FS[1] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 33.676 ;
|
||||
; 36.147 ; FS[8] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 33.373 ;
|
||||
; 36.765 ; FS[9] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 32.755 ;
|
||||
; 36.845 ; FS[11] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 32.675 ;
|
||||
; 37.021 ; FS[10] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 32.499 ;
|
||||
; 37.152 ; FS[4] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 32.368 ;
|
||||
; 37.316 ; S[2] ; CmdPrgmMAX ; C14M ; C14M ; 69.841 ; 0.000 ; 32.204 ;
|
||||
; 37.805 ; S[0] ; CmdEraseMAX ; C14M ; C14M ; 69.841 ; 0.000 ; 31.715 ;
|
||||
; 37.880 ; FS[8] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 31.640 ;
|
||||
; 37.905 ; FS[11] ; nCAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 31.615 ;
|
||||
+---------+---------------------------------------------------------------------------------------------+--------------+--------------+-------------+--------------+------------+------------+
|
||||
|
||||
|
||||
@ -300,7 +300,7 @@ No paths to report.
|
||||
+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; -14.566 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M ; ARCLK ; 0.000 ; -1.042 ; 4.392 ;
|
||||
; -16.136 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M ; ARCLK ; 0.000 ; -0.901 ; 2.963 ;
|
||||
; 60.000 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 0.000 ; 0.000 ; 80.000 ;
|
||||
+---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
|
||||
@ -310,8 +310,8 @@ No paths to report.
|
||||
+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
; -14.550 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M ; DRCLK ; 0.000 ; -1.050 ; 4.400 ;
|
||||
; -14.476 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M ; DRCLK ; 0.000 ; -1.050 ; 4.474 ;
|
||||
; -15.980 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M ; DRCLK ; 0.000 ; -1.057 ; 2.963 ;
|
||||
; -15.980 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M ; DRCLK ; 0.000 ; -1.057 ; 2.963 ;
|
||||
; 60.000 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 0.000 ; 0.000 ; 80.000 ;
|
||||
+---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
||||
|
||||
@ -321,106 +321,106 @@ No paths to report.
|
||||
+-------+---------------+-------------------+--------------+-------------+--------------+------------+------------+
|
||||
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
||||
+-------+---------------+-------------------+--------------+-------------+--------------+------------+------------+
|
||||
; 3.107 ; UFMD[7] ; UFMD[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.146 ;
|
||||
; 3.119 ; UFMD[10] ; UFMD[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.158 ;
|
||||
; 3.155 ; UFMD[11] ; UFMD[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.194 ;
|
||||
; 3.364 ; Ready ; Ready ; C14M ; C14M ; 0.000 ; 0.000 ; 3.403 ;
|
||||
; 3.382 ; UFMD[8] ; UFMD[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.421 ;
|
||||
; 3.402 ; CmdPrgmMAX ; CmdPrgmMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 3.441 ;
|
||||
; 3.412 ; CmdBitbangMAX ; DRCLKPulse ; C14M ; C14M ; 0.000 ; 0.000 ; 3.451 ;
|
||||
; 3.414 ; UFMD[13] ; UFMD[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.453 ;
|
||||
; 3.443 ; CS[0] ; CS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.482 ;
|
||||
; 3.500 ; CmdTout[0] ; CmdTout[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.539 ;
|
||||
; 3.500 ; CmdTout[0] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.539 ;
|
||||
; 3.510 ; CmdTout[0] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.549 ;
|
||||
; 3.740 ; FS[0] ; FS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.779 ;
|
||||
; 3.754 ; RWMask[4] ; RWBank[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.793 ;
|
||||
; 3.756 ; RWMask[1] ; RWBank[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.795 ;
|
||||
; 3.779 ; RWBank[5] ; BA[1]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.818 ;
|
||||
; 3.791 ; RCLKx1 ; RCLKx1 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.830 ;
|
||||
; 3.801 ; CS[1] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.840 ;
|
||||
; 3.803 ; CS[1] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.842 ;
|
||||
; 3.835 ; UFMProgStart ; UFMProgStart ; C14M ; C14M ; 0.000 ; 0.000 ; 3.874 ;
|
||||
; 3.842 ; UFMProgStart ; UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 3.881 ;
|
||||
; 3.843 ; UFMProgStart ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 3.882 ;
|
||||
; 4.088 ; PHI1reg ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.127 ;
|
||||
; 4.524 ; S[3] ; DOEEN ; C14M ; C14M ; 0.000 ; 0.000 ; 4.563 ;
|
||||
; 4.997 ; CmdEraseMAX ; CmdEraseMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 5.036 ;
|
||||
; 5.217 ; CS[2] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.256 ;
|
||||
; 5.229 ; FS[5] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.268 ;
|
||||
; 5.242 ; FS[15] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.281 ;
|
||||
; 5.248 ; FS[7] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.287 ;
|
||||
; 2.440 ; UFMBusyReg ; UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 2.479 ;
|
||||
; 3.130 ; UFMD[12] ; UFMD[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.169 ;
|
||||
; 3.153 ; UFMD[9] ; UFMD[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.192 ;
|
||||
; 3.166 ; UFMD[14] ; UFMD[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.205 ;
|
||||
; 3.170 ; UFMD[13] ; UFMD[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.209 ;
|
||||
; 3.385 ; UFMD[10] ; UFMD[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.424 ;
|
||||
; 3.414 ; FS[0] ; FS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.453 ;
|
||||
; 3.442 ; CmdEraseMAX ; CmdEraseMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 3.481 ;
|
||||
; 3.443 ; S[2] ; S[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.482 ;
|
||||
; 3.451 ; S[2] ; DOEEN ; C14M ; C14M ; 0.000 ; 0.000 ; 3.490 ;
|
||||
; 3.451 ; CmdTout[0] ; CmdTout[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.490 ;
|
||||
; 3.453 ; CmdTout[0] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.492 ;
|
||||
; 3.454 ; CmdTout[0] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.493 ;
|
||||
; 3.528 ; CS[0] ; CS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.567 ;
|
||||
; 3.538 ; CS[0] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.577 ;
|
||||
; 3.740 ; S[0] ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.779 ;
|
||||
; 3.740 ; DRDIn ; DRDIn ; C14M ; C14M ; 0.000 ; 0.000 ; 3.779 ;
|
||||
; 3.741 ; RTPBusyReg ; UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 3.780 ;
|
||||
; 3.779 ; RWSel ; RWSel ; C14M ; C14M ; 0.000 ; 0.000 ; 3.818 ;
|
||||
; 3.810 ; S[1] ; S[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.849 ;
|
||||
; 3.827 ; CmdPrgmMAX ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 3.866 ;
|
||||
; 3.831 ; S[1] ; DOEEN ; C14M ; C14M ; 0.000 ; 0.000 ; 3.870 ;
|
||||
; 3.833 ; CmdTout[1] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.872 ;
|
||||
; 3.839 ; CmdTout[1] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.878 ;
|
||||
; 3.843 ; CS[2] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.882 ;
|
||||
; 4.011 ; PHI1reg ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.050 ;
|
||||
; 4.210 ; UFMD[8] ; UFMD[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.249 ;
|
||||
; 4.278 ; CmdEraseMAX ; UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 4.317 ;
|
||||
; 4.279 ; UFMD[11] ; UFMD[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.318 ;
|
||||
; 5.056 ; RTPBusyReg ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 5.095 ;
|
||||
; 5.228 ; LEDEN ; LEDEN ; C14M ; C14M ; 0.000 ; 0.000 ; 5.267 ;
|
||||
; 5.241 ; FS[15] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.280 ;
|
||||
; 5.243 ; FS[5] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.282 ;
|
||||
; 5.252 ; FS[8] ; FS[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.291 ;
|
||||
; 5.254 ; RWBank[7] ; RA[8]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 5.293 ;
|
||||
; 5.267 ; FS[10] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.306 ;
|
||||
; 5.270 ; FS[9] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.309 ;
|
||||
; 5.288 ; UFMErase ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 5.327 ;
|
||||
; 5.337 ; CmdTout[1] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.376 ;
|
||||
; 5.351 ; CmdTout[1] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.390 ;
|
||||
; 5.416 ; DRDIn ; DRDIn ; C14M ; C14M ; 0.000 ; 0.000 ; 5.455 ;
|
||||
; 5.420 ; RWBank[0] ; RA[8]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 5.459 ;
|
||||
; 5.453 ; UFMInitDone ; UFMInitDone ; C14M ; C14M ; 0.000 ; 0.000 ; 5.492 ;
|
||||
; 5.455 ; FS[11] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.494 ;
|
||||
; 5.268 ; Ready ; Ready ; C14M ; C14M ; 0.000 ; 0.000 ; 5.307 ;
|
||||
; 5.272 ; FS[7] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.311 ;
|
||||
; 5.278 ; FS[10] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.317 ;
|
||||
; 5.281 ; FS[9] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.320 ;
|
||||
; 5.286 ; CmdPrgmMAX ; CmdPrgmMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 5.325 ;
|
||||
; 5.360 ; CS[1] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.399 ;
|
||||
; 5.361 ; CS[1] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.400 ;
|
||||
; 5.440 ; FS[3] ; FS[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.479 ;
|
||||
; 5.441 ; FS[4] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.480 ;
|
||||
; 5.441 ; FS[2] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.480 ;
|
||||
; 5.442 ; FS[11] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.481 ;
|
||||
; 5.452 ; FS[1] ; FS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.491 ;
|
||||
; 5.464 ; FS[14] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.503 ;
|
||||
; 5.464 ; FS[4] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.503 ;
|
||||
; 5.466 ; FS[6] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.505 ;
|
||||
; 5.472 ; FS[1] ; FS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.511 ;
|
||||
; 5.474 ; FS[3] ; FS[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.513 ;
|
||||
; 5.473 ; UFMErase ; UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 5.512 ;
|
||||
; 5.474 ; UFMProgram ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 5.513 ;
|
||||
; 5.475 ; FS[13] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.514 ;
|
||||
; 5.476 ; FS[12] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.515 ;
|
||||
; 5.477 ; FS[2] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.516 ;
|
||||
; 5.477 ; CmdPrgmMAX ; CmdEraseMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 5.516 ;
|
||||
; 5.477 ; CmdTout[2] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.516 ;
|
||||
; 5.525 ; CS[0] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.564 ;
|
||||
; 5.526 ; CS[0] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.565 ;
|
||||
; 5.949 ; PHI1reg ; S[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.988 ;
|
||||
; 5.954 ; PHI1reg ; S[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.993 ;
|
||||
; 5.958 ; PHI1reg ; S[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.997 ;
|
||||
; 5.964 ; FS[5] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.003 ;
|
||||
; 5.476 ; FS[6] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.515 ;
|
||||
; 5.478 ; UFMInitDone ; UFMInitDone ; C14M ; C14M ; 0.000 ; 0.000 ; 5.517 ;
|
||||
; 5.486 ; CmdTout[2] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.525 ;
|
||||
; 5.541 ; S[3] ; S[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.580 ;
|
||||
; 5.613 ; CS[0] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.652 ;
|
||||
; 5.664 ; RWBank[2] ; RA[10]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 5.703 ;
|
||||
; 5.753 ; CmdPrgmMAX ; UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 5.792 ;
|
||||
; 5.978 ; FS[5] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.017 ;
|
||||
; 5.987 ; FS[8] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.026 ;
|
||||
; 6.002 ; FS[10] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.041 ;
|
||||
; 6.005 ; FS[9] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.044 ;
|
||||
; 6.035 ; S[1] ; S[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.074 ;
|
||||
; 6.086 ; UFMD[14] ; UFMD[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.125 ;
|
||||
; 6.108 ; FS[5] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.147 ;
|
||||
; 6.013 ; FS[10] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.052 ;
|
||||
; 6.016 ; FS[9] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.055 ;
|
||||
; 6.122 ; FS[5] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.161 ;
|
||||
; 6.131 ; FS[8] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.170 ;
|
||||
; 6.146 ; FS[10] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.185 ;
|
||||
; 6.149 ; FS[9] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.188 ;
|
||||
; 6.251 ; CS[1] ; CmdSetRWBankFFMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 6.290 ;
|
||||
; 6.157 ; FS[10] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.196 ;
|
||||
; 6.160 ; FS[9] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.199 ;
|
||||
; 6.229 ; DRCLKPulse ; DRCLK ; C14M ; C14M ; 0.000 ; 0.000 ; 6.268 ;
|
||||
; 6.275 ; FS[8] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.314 ;
|
||||
; 6.293 ; FS[9] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.332 ;
|
||||
; 6.386 ; CmdLEDGet ; RWBank[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.425 ;
|
||||
; 6.390 ; LEDEN ; LEDEN ; C14M ; C14M ; 0.000 ; 0.000 ; 6.429 ;
|
||||
; 6.401 ; S[1] ; DOEEN ; C14M ; C14M ; 0.000 ; 0.000 ; 6.440 ;
|
||||
; 6.304 ; FS[9] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.343 ;
|
||||
; 6.419 ; FS[8] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.458 ;
|
||||
; 6.457 ; FS[11] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.496 ;
|
||||
; 6.442 ; FS[3] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.481 ;
|
||||
; 6.443 ; FS[4] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.482 ;
|
||||
; 6.444 ; FS[11] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.483 ;
|
||||
; 6.454 ; FS[1] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.493 ;
|
||||
; 6.466 ; FS[14] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.505 ;
|
||||
; 6.466 ; FS[4] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.505 ;
|
||||
; 6.468 ; FS[6] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.507 ;
|
||||
; 6.474 ; FS[1] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.513 ;
|
||||
; 6.476 ; FS[3] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.515 ;
|
||||
; 6.477 ; FS[13] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.516 ;
|
||||
; 6.586 ; RWMask[7] ; RWBank[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.625 ;
|
||||
; 6.587 ; S[2] ; BA[1]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 6.626 ;
|
||||
; 6.588 ; UFMReqErase ; UFMReqErase ; C14M ; C14M ; 0.000 ; 0.000 ; 6.627 ;
|
||||
; 6.590 ; UFMD[9] ; UFMD[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.629 ;
|
||||
; 6.610 ; FS[4] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.649 ;
|
||||
; 6.620 ; FS[3] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.659 ;
|
||||
; 6.478 ; FS[6] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.517 ;
|
||||
; 6.507 ; RWBank[5] ; BA[1]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 6.546 ;
|
||||
; 6.533 ; CmdBitbangMAX ; DRCLKPulse ; C14M ; C14M ; 0.000 ; 0.000 ; 6.572 ;
|
||||
; 6.586 ; FS[3] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.625 ;
|
||||
; 6.587 ; FS[4] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.626 ;
|
||||
; 6.621 ; FS[13] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.660 ;
|
||||
; 6.627 ; RWMask[5] ; RWBank[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.666 ;
|
||||
; 6.634 ; S[0] ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.673 ;
|
||||
; 6.663 ; RWMask[3] ; RWBank[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.702 ;
|
||||
; 6.676 ; CmdEraseMAX ; CmdPrgmMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 6.715 ;
|
||||
; 6.724 ; UFMD[12] ; RWMask[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.763 ;
|
||||
; 6.754 ; FS[4] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.793 ;
|
||||
; 6.764 ; FS[3] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.803 ;
|
||||
; 6.782 ; FS[10] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.821 ;
|
||||
; 6.782 ; FS[10] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.821 ;
|
||||
; 6.782 ; FS[10] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.821 ;
|
||||
; 6.908 ; FS[3] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.947 ;
|
||||
; 6.929 ; FS[9] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.968 ;
|
||||
; 6.929 ; FS[9] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.968 ;
|
||||
; 6.929 ; FS[9] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.968 ;
|
||||
; 6.651 ; UFMD[11] ; RWMask[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.690 ;
|
||||
; 6.724 ; RWMask[4] ; RWBank[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.763 ;
|
||||
; 6.730 ; FS[3] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.769 ;
|
||||
; 6.731 ; FS[4] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.770 ;
|
||||
; 6.774 ; RWMask[3] ; RWBank[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.813 ;
|
||||
; 6.793 ; FS[10] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.832 ;
|
||||
; 6.793 ; FS[10] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.832 ;
|
||||
; 6.793 ; FS[10] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.832 ;
|
||||
; 6.816 ; UFMD[15] ; RWMask[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.855 ;
|
||||
; 6.836 ; CS[0] ; CmdRWMaskSet ; C14M ; C14M ; 0.000 ; 0.000 ; 6.875 ;
|
||||
; 6.843 ; CS[0] ; CmdSetRWBankFFLED ; C14M ; C14M ; 0.000 ; 0.000 ; 6.882 ;
|
||||
; 6.874 ; FS[3] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.913 ;
|
||||
; 6.895 ; CmdEraseMAX ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 6.934 ;
|
||||
; 6.940 ; FS[9] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.979 ;
|
||||
; 6.940 ; FS[9] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.979 ;
|
||||
; 6.940 ; FS[9] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.979 ;
|
||||
; 6.998 ; FS[2] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 7.037 ;
|
||||
; 6.998 ; FS[2] ; FS[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 7.037 ;
|
||||
+-------+---------------+-------------------+--------------+-------------+--------------+------------+------------+
|
||||
|
||||
|
||||
@ -431,8 +431,8 @@ No paths to report.
|
||||
+------------+----------+----------+----------+----------+----------+
|
||||
; ARCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ;
|
||||
; C14M ; ARCLK ; 1 ; 0 ; 0 ; 0 ;
|
||||
; C14M ; C14M ; 1715 ; 1 ; 64 ; 1 ;
|
||||
; DRCLK ; C14M ; 1 ; 0 ; 0 ; 0 ;
|
||||
; C14M ; C14M ; 1607 ; 0 ; 64 ; 0 ;
|
||||
; DRCLK ; C14M ; 13 ; 0 ; 0 ; 0 ;
|
||||
; C14M ; DRCLK ; 2 ; 0 ; 0 ; 0 ;
|
||||
; DRCLK ; DRCLK ; 1 ; 0 ; 0 ; 0 ;
|
||||
+------------+----------+----------+----------+----------+----------+
|
||||
@ -446,8 +446,8 @@ Entries labeled "false path" only account for clock-to-clock false paths and not
|
||||
+------------+----------+----------+----------+----------+----------+
|
||||
; ARCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ;
|
||||
; C14M ; ARCLK ; 1 ; 0 ; 0 ; 0 ;
|
||||
; C14M ; C14M ; 1715 ; 1 ; 64 ; 1 ;
|
||||
; DRCLK ; C14M ; 1 ; 0 ; 0 ; 0 ;
|
||||
; C14M ; C14M ; 1607 ; 0 ; 64 ; 0 ;
|
||||
; DRCLK ; C14M ; 13 ; 0 ; 0 ; 0 ;
|
||||
; C14M ; DRCLK ; 2 ; 0 ; 0 ; 0 ;
|
||||
; DRCLK ; DRCLK ; 1 ; 0 ; 0 ; 0 ;
|
||||
+------------+----------+----------+----------+----------+----------+
|
||||
@ -476,7 +476,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
||||
; Unconstrained Input Ports ; 29 ; 29 ;
|
||||
; Unconstrained Input Port Paths ; 169 ; 169 ;
|
||||
; Unconstrained Output Ports ; 48 ; 48 ;
|
||||
; Unconstrained Output Port Paths ; 69 ; 69 ;
|
||||
; Unconstrained Output Port Paths ; 67 ; 67 ;
|
||||
+---------------------------------+-------+------+
|
||||
|
||||
|
||||
@ -559,7 +559,6 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
||||
; RA[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RCLK ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RD[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RD[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RD[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
@ -577,6 +576,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
||||
; Vout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; Vout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nCAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nCS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nDOE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nRAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nRWE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
@ -652,7 +652,6 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
||||
; RA[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RA[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RCLK ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RD[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RD[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; RD[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
@ -670,6 +669,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
||||
; Vout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; Vout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nCAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nCS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nDOE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nRAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
; nRWE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
||||
@ -682,8 +682,8 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
|
||||
+--------------------------+
|
||||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime Timing Analyzer
|
||||
Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
|
||||
Info: Processing started: Tue Nov 21 06:54:43 2023
|
||||
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Info: Processing started: Thu Sep 21 05:34:43 2023
|
||||
Info: Command: quartus_sta RAM2E-MAXV -c RAM2E
|
||||
Info: qsta_default_script.tcl version: #1
|
||||
Info (20032): Parallel compilation is enabled and will use up to 4 processors
|
||||
@ -698,18 +698,18 @@ Info: Can't run Report Timing Closure Recommendations. The current device family
|
||||
Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ARCLK are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
|
||||
Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: DRCLK are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
|
||||
Critical Warning (332148): Timing requirements not met
|
||||
Info (332146): Worst-case setup slack is -25.523
|
||||
Info (332146): Worst-case setup slack is -24.019
|
||||
Info (332119): Slack End Point TNS Clock
|
||||
Info (332119): ========= =================== =====================
|
||||
Info (332119): -25.523 -25.523 DRCLK
|
||||
Info (332119): -25.433 -25.433 ARCLK
|
||||
Info (332119): -10.080 -10.080 C14M
|
||||
Info (332146): Worst-case hold slack is -14.566
|
||||
Info (332119): -24.019 -24.019 DRCLK
|
||||
Info (332119): -23.863 -23.863 ARCLK
|
||||
Info (332119): -15.767 -176.992 C14M
|
||||
Info (332146): Worst-case hold slack is -16.136
|
||||
Info (332119): Slack End Point TNS Clock
|
||||
Info (332119): ========= =================== =====================
|
||||
Info (332119): -14.566 -14.566 ARCLK
|
||||
Info (332119): -14.550 -14.550 DRCLK
|
||||
Info (332119): 3.107 0.000 C14M
|
||||
Info (332119): -16.136 -16.136 ARCLK
|
||||
Info (332119): -15.980 -15.980 DRCLK
|
||||
Info (332119): 2.440 0.000 C14M
|
||||
Info (332140): No Recovery paths to report
|
||||
Info (332140): No Removal paths to report
|
||||
Info (332146): Worst-case minimum pulse width slack is 34.581
|
||||
@ -724,9 +724,9 @@ Warning (332009): The launch and latch times for the relationship between source
|
||||
Info (332102): Design is not fully constrained for setup requirements
|
||||
Info (332102): Design is not fully constrained for hold requirements
|
||||
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings
|
||||
Info: Peak virtual memory: 13066 megabytes
|
||||
Info: Processing ended: Tue Nov 21 06:54:45 2023
|
||||
Info: Elapsed time: 00:00:02
|
||||
Info: Peak virtual memory: 13092 megabytes
|
||||
Info: Processing ended: Thu Sep 21 05:34:46 2023
|
||||
Info: Elapsed time: 00:00:03
|
||||
Info: Total CPU time (on all processors): 00:00:02
|
||||
|
||||
|
||||
|
||||
@ -3,27 +3,27 @@ Timing Analyzer Summary
|
||||
------------------------------------------------------------
|
||||
|
||||
Type : Setup 'DRCLK'
|
||||
Slack : -25.523
|
||||
TNS : -25.523
|
||||
Slack : -24.019
|
||||
TNS : -24.019
|
||||
|
||||
Type : Setup 'ARCLK'
|
||||
Slack : -25.433
|
||||
TNS : -25.433
|
||||
Slack : -23.863
|
||||
TNS : -23.863
|
||||
|
||||
Type : Setup 'C14M'
|
||||
Slack : -10.080
|
||||
TNS : -10.080
|
||||
Slack : -15.767
|
||||
TNS : -176.992
|
||||
|
||||
Type : Hold 'ARCLK'
|
||||
Slack : -14.566
|
||||
TNS : -14.566
|
||||
Slack : -16.136
|
||||
TNS : -16.136
|
||||
|
||||
Type : Hold 'DRCLK'
|
||||
Slack : -14.550
|
||||
TNS : -14.550
|
||||
Slack : -15.980
|
||||
TNS : -15.980
|
||||
|
||||
Type : Hold 'C14M'
|
||||
Slack : 3.107
|
||||
Slack : 2.440
|
||||
TNS : 0.000
|
||||
|
||||
Type : Minimum Pulse Width 'C14M'
|
||||
|
||||
@ -7,18 +7,18 @@ module RAM2E(C14M, PHI1, LED,
|
||||
/* Clocks */
|
||||
input C14M, PHI1;
|
||||
|
||||
/* SDRAM clock output */
|
||||
output RCLK;
|
||||
ODDRXE rclk_oddr(.D0(1'b0), .D1(1'b1),
|
||||
.SCLK(C14M), .RST(1'b0), .Q(RCLK));
|
||||
|
||||
/* Control inputs */
|
||||
input nWE, nWE80, nEN80, nC07X;
|
||||
|
||||
/* Delay for EN80 signal */
|
||||
//output DelayOut = 1'b0;
|
||||
//input DelayIn;
|
||||
wire EN80 = !nEN80;
|
||||
|
||||
/* Activity LED */
|
||||
reg LEDEN = 0;
|
||||
output LED;
|
||||
assign LED = !(!nEN80 && LEDEN && Ready);
|
||||
assign LED = !(!nEN80 && LEDEN);
|
||||
|
||||
/* Address Bus */
|
||||
input [7:0] Ain; // Multiplexed DRAM address input
|
||||
@ -27,7 +27,7 @@ module RAM2E(C14M, PHI1, LED,
|
||||
input [7:0] Din; // 6502 data bus inputs
|
||||
reg DOEEN = 0; // 6502 data bus output enable from state machine
|
||||
output nDOE;
|
||||
assign nDOE = !(!nEN80 && nWE && DOEEN); // 6502 data bus output enable
|
||||
assign nDOE = !(EN80 && nWE && DOEEN); // 6502 data bus output enable
|
||||
output reg [7:0] Dout; // 6502 data Bus output
|
||||
|
||||
/* Video Data Bus */
|
||||
@ -37,13 +37,11 @@ module RAM2E(C14M, PHI1, LED,
|
||||
|
||||
/* SDRAM */
|
||||
output reg CKE = 0;
|
||||
output nCS;
|
||||
assign nCS = 0;
|
||||
output reg nRAS = 1, nCAS = 1, nRWE = 1;
|
||||
output reg nCS = 1, nRAS = 1, nCAS = 1, nRWE = 1;
|
||||
output reg [1:0] BA;
|
||||
output reg [11:0] RA;
|
||||
output reg DQML = 1, DQMH = 1;
|
||||
wire RDOE = !nEN80 && !nWE80;
|
||||
wire RDOE = EN80 && !nWE80;
|
||||
inout [7:0] RD;
|
||||
assign RD[7:0] = RDOE ? Din[7:0] : 8'bZ;
|
||||
|
||||
@ -594,7 +592,7 @@ module RAM2E(C14M, PHI1, LED,
|
||||
DOEEN <= 1'b0;
|
||||
end else if (S==4'h8) begin
|
||||
// Enable clock if '245 output enabled
|
||||
CKE <= !nEN80;
|
||||
CKE <= EN80;
|
||||
|
||||
// Activate if '245 output enabled
|
||||
nCS <= nEN80;
|
||||
@ -615,7 +613,7 @@ module RAM2E(C14M, PHI1, LED,
|
||||
DOEEN <= 1'b0;
|
||||
end else if (S==4'h9) begin
|
||||
// Enable clock if '245 output enabled
|
||||
CKE <= !nEN80;
|
||||
CKE <= EN80;
|
||||
|
||||
// Read/Write if '245 output enabled
|
||||
nCS <= nEN80;
|
||||
@ -643,7 +641,7 @@ module RAM2E(C14M, PHI1, LED,
|
||||
DOEEN <= 1'b0;
|
||||
end else if (S==4'hA) begin
|
||||
// Enable clock if '245 output enabled
|
||||
CKE <= !nEN80;
|
||||
CKE <= EN80;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
|
||||
@ -1,28 +0,0 @@
|
||||
-- Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||
-- Your use of Intel Corporation's design tools, logic functions
|
||||
-- and other software and tools, and any partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Intel Program License
|
||||
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
-- the Intel FPGA IP License Agreement, or other applicable license
|
||||
-- agreement, including, without limitation, that your use is for
|
||||
-- the sole purpose of programming logic devices manufactured by
|
||||
-- Intel and sold by Intel or its authorized distributors. Please
|
||||
-- refer to the applicable agreement for further details, at
|
||||
-- https://fpgasoftware.intel.com/eula.
|
||||
|
||||
-- Quartus Prime generated Memory Initialization File (.mif)
|
||||
|
||||
WIDTH=16;
|
||||
DEPTH=512;
|
||||
|
||||
ADDRESS_RADIX=HEX;
|
||||
DATA_RADIX=HEX;
|
||||
|
||||
CONTENT BEGIN
|
||||
[000..0FD] : 0000;
|
||||
0FE : 7F7F;
|
||||
[0FF..1FF] : FFFF;
|
||||
END;
|
||||
148
CPLD/RAM2E-MAX.v
148
CPLD/RAM2E-MAX.v
@ -1,4 +1,4 @@
|
||||
module RAM2E(C14M, RCLK, PHI1, LED,
|
||||
module RAM2E(C14M, PHI1, LED,
|
||||
nWE, nWE80, nEN80, nC07X,
|
||||
Ain, Din, Dout, nDOE, Vout, nVOE,
|
||||
CKE, nCS, nRAS, nCAS, nRWE,
|
||||
@ -7,21 +7,18 @@ module RAM2E(C14M, RCLK, PHI1, LED,
|
||||
/* Clocks */
|
||||
input C14M, PHI1;
|
||||
|
||||
/* SDRAM clock output */
|
||||
output RCLK;
|
||||
reg RCLKx0;
|
||||
reg RCLKx1;
|
||||
always @(negedge C14M) RCLKx1 <= !RCLKx1;
|
||||
always @(posedge C14M) RCLKx0 <= RCLKx1;
|
||||
assign RCLK = RCLKx0 ^ RCLKx1;
|
||||
|
||||
/* Control inputs */
|
||||
input nWE, nWE80, nEN80, nC07X;
|
||||
|
||||
/* Delay for EN80 signal */
|
||||
//output DelayOut = 1'b0;
|
||||
//input DelayIn;
|
||||
wire EN80 = !nEN80;
|
||||
|
||||
/* Activity LED */
|
||||
reg LEDEN = 0;
|
||||
output LED;
|
||||
assign LED = !(!nEN80 && LEDEN && Ready);
|
||||
assign LED = !(!nEN80 && LEDEN);
|
||||
|
||||
/* Address Bus */
|
||||
input [7:0] Ain; // Multiplexed DRAM address input
|
||||
@ -30,7 +27,7 @@ module RAM2E(C14M, RCLK, PHI1, LED,
|
||||
input [7:0] Din; // 6502 data bus inputs
|
||||
reg DOEEN = 0; // 6502 data bus output enable from state machine
|
||||
output nDOE;
|
||||
assign nDOE = !(!nEN80 && nWE && DOEEN); // 6502 data bus output enable
|
||||
assign nDOE = !(EN80 && nWE && DOEEN); // 6502 data bus output enable
|
||||
output reg [7:0] Dout; // 6502 data Bus output
|
||||
|
||||
/* Video Data Bus */
|
||||
@ -40,13 +37,11 @@ module RAM2E(C14M, RCLK, PHI1, LED,
|
||||
|
||||
/* SDRAM */
|
||||
output reg CKE = 0;
|
||||
output nCS;
|
||||
assign nCS = 0;
|
||||
output reg nRAS = 1, nCAS = 1, nRWE = 1;
|
||||
output reg nCS = 1, nRAS = 1, nCAS = 1, nRWE = 1;
|
||||
output reg [1:0] BA;
|
||||
output reg [11:0] RA;
|
||||
output reg DQML = 1, DQMH = 1;
|
||||
wire RDOE = !nEN80 && !nWE80;
|
||||
wire RDOE = EN80 && !nWE80;
|
||||
inout [7:0] RD;
|
||||
assign RD[7:0] = RDOE ? Din[7:0] : 8'bZ;
|
||||
|
||||
@ -68,7 +63,7 @@ module RAM2E(C14M, RCLK, PHI1, LED,
|
||||
reg [2:0] CmdTout = 0; // Command sequence timeout
|
||||
|
||||
/* UFM Interface */
|
||||
reg [15:7] UFMD = 0; // *Parallel* UFM data register
|
||||
reg [15:8] UFMD = 0; // *Parallel* UFM data register
|
||||
reg ARCLK = 0; // UFM address register clock
|
||||
// UFM address register data input tied to 0
|
||||
reg ARShift = 0; // 1 to Shift UFM address in, 0 to increment
|
||||
@ -97,7 +92,7 @@ module RAM2E(C14M, RCLK, PHI1, LED,
|
||||
.osc (UFMOsc),
|
||||
.rtpbusy (RTPBusy));
|
||||
reg UFMRTPBusy = 0;
|
||||
always @(posedge C14M) UFMRTPBusy <= UFMBusy || RTPBusy;
|
||||
always @(posedge C14M) begin UFMRTPBusy <= UFMBusy || RTPBusy;
|
||||
|
||||
/* UFM State and User Command Triggers */
|
||||
reg UFMInitDone = 0; // 1 if UFM initialization finished
|
||||
@ -147,42 +142,37 @@ module RAM2E(C14M, RCLK, PHI1, LED,
|
||||
ARShift <= 1'b0; // Don't care ARShift
|
||||
DRDIn <= 1'b0; // Don't care DRDIn
|
||||
DRShift <= 1'b0; // Don't care DRShift
|
||||
end else if (!UFMInitDone && FS[15:13]==3'b110 && (FS[4:1]==4'h6 || FS[4:1]==4'h7 || FS[4:1]==4'h8 || FS[4:1]==4'h9 || FS[4:1]==4'hA || FS[4:1]==4'hB || FS[4:1]==4'hC || FS[4:1]==4'hD || FS[4:1]==4'hE)) begin
|
||||
// In states CXXX-DXXX (substeps 6-E)
|
||||
// Shift out UFMD[15:7] (repeat 256x 9x)
|
||||
ARCLK <= 1'b0; // Don't clock address register
|
||||
end else if (!UFMInitDone && FS[15:13]==3'b110 && (FS[4:1]==4'h7 || FS[4]==1'b1)) begin
|
||||
// In states CXXX-DXXX (substeps 8-F)
|
||||
// Save UFM D15-8, shift out D14-7 (repeat 256x 8x)
|
||||
DRCLK <= FS[0]; // Clock data register
|
||||
ARShift <= 1'b0; // ARShift is 0 because we want to increment
|
||||
DRDIn <= 1'b0; // Don't care what to shift into data register
|
||||
DRShift <= 1'b1; // Shift data register
|
||||
// Shift into UFMD
|
||||
if (FS[0]) UFMD[15:7] <= {UFMD[14:7], DRDOut};
|
||||
end else if (!UFMInitDone && FS[15:13]==3'b110 && FS[4:1]==4'hF) begin
|
||||
// In states CXXX-DXXX (substep F)
|
||||
// Check and save mask, compute and save LEDEN
|
||||
DRCLK <= 1'b0; // Don't clock data register
|
||||
ARShift <= 1'b0; // ARShift is 0 because we want to increment
|
||||
DRDIn <= 1'b0; // Don't care what to shift into data register
|
||||
DRShift <= 1'b1; // Shift data register
|
||||
// Set settings
|
||||
// If byte is erased (0xFF, i.e. all 1's, is erased)...
|
||||
if (UFMD[15:8]==8'hFF && UFMD[7]==1'b1) begin
|
||||
// Current UFM address is where we want to store
|
||||
UFMInitDone <= 1'b1; // Quit iterating
|
||||
ARCLK <= 1'b0; // Don't increment address register
|
||||
// Otherwise byte is valid setting (i.e. some bit is 0)...
|
||||
end else begin
|
||||
// Set RWMask, but if saved mask is 0x80, set for FF
|
||||
if (UFMD[15:8]==8'b10000000) RWMask[7:0] <= {1'b1, 7'h00};
|
||||
else RWMask[7:0] <= {UFMD[15], ~UFMD[14:8]};
|
||||
// Set LED setting
|
||||
LEDEN <= UFMD[15] ^ UFMD[7];
|
||||
// If last byte in sector...
|
||||
if (FS[12:5]==8'hFF) begin
|
||||
UFMReqErase <= 1'b1; // Need to erase
|
||||
ARCLK <= 1'b0; // Don't increment address register
|
||||
end else ARCLK <= FS[0]; // Increment if not last byte
|
||||
end
|
||||
if (FS[0]) UFMD[15:8] <= {UFMD[14:8], DRDOut};
|
||||
|
||||
// Compare and store mask
|
||||
if (FS[4:1]==4'hF) begin
|
||||
ARCLK <= FS[0]; // Clock address register to increment
|
||||
// If byte is erased (0xFF, i.e. all 1's, is erased)...
|
||||
if (UFMD[15:8]==8'hFF && DRDOut==1'b1) begin
|
||||
// Current UFM address is where we want to store
|
||||
UFMInitDone <= 1'b1; // Quit iterating
|
||||
// Otherwise byte is valid setting (i.e. some bit is 0)...
|
||||
end else begin
|
||||
// Set RWMask, but if saved mask is 0x80, store ~0xFF
|
||||
if (UFMD[15:8]==8'b10000000) begin
|
||||
RWMask[7:0] <= {1'b1, ~7'h7F};
|
||||
end else RWMask[7:0] <= {UFMD[15], ~UFMD[14:8]};
|
||||
// Set LED setting
|
||||
LEDEN <= DRDOut ^ UFMD[15];
|
||||
// If last byte in sector...
|
||||
if (FS[12:5]==8'hFF) begin
|
||||
UFMReqErase <= 1'b1; // Mark need to erase
|
||||
end
|
||||
end
|
||||
end else ARCLK <= 1'b0; // Don't clock address register
|
||||
end else begin
|
||||
ARCLK <= 1'b0;
|
||||
DRCLK <= 1'b0;
|
||||
@ -223,21 +213,15 @@ module RAM2E(C14M, RCLK, PHI1, LED,
|
||||
end
|
||||
|
||||
// UFM programming sequence
|
||||
if (S==4'h1 && !UFMRTPBusy) begin
|
||||
if (!UFMProgStart) begin
|
||||
if (S==4'h1) begin
|
||||
if (!UFMProgStart && !UFMRTPBusy) begin
|
||||
if (CmdPrgmMAX) begin
|
||||
UFMErase <= UFMReqErase;
|
||||
UFMProgram <= 0;
|
||||
UFMProgStart <= 1;
|
||||
end else if (CmdEraseMAX) begin
|
||||
UFMErase <= 1;
|
||||
UFMProgram <= 0;
|
||||
UFMProgStart <= 1;
|
||||
end
|
||||
end else begin
|
||||
end else if (CmdEraseMAX) UFMErase <= 1;
|
||||
end else if (UFMProgStart && !UFMRTPBusy) begin
|
||||
UFMErase <= 0;
|
||||
UFMProgram <= !UFMErase;
|
||||
UFMProgStart <= 1;
|
||||
if (!UFMErase) UFMProgram <= 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
@ -249,30 +233,35 @@ module RAM2E(C14M, RCLK, PHI1, LED,
|
||||
// SDRAM initialization
|
||||
if (FS[15:0]==16'hFFC0) begin
|
||||
// Precharge All
|
||||
nCS <= 1'b0;
|
||||
nRAS <= 1'b0;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b0;
|
||||
RA[10] <= 1'b1; // "all"
|
||||
end else if (FS[15:4]==16'hFFD && FS[0]==1'b0) begin // Repeat 8x
|
||||
// Auto-refresh
|
||||
nCS <= 1'b0;
|
||||
nRAS <= 1'b0;
|
||||
nCAS <= 1'b0;
|
||||
nRWE <= 1'b1;
|
||||
RA[10] <= 1'b0;
|
||||
end else if (FS[15:0]==16'hFFE8) begin
|
||||
// Set Mode Register
|
||||
nCS <= 1'b0;
|
||||
nRAS <= 1'b0;
|
||||
nCAS <= 1'b0;
|
||||
nRWE <= 1'b0;
|
||||
RA[10] <= 1'b0; // Reserved in mode register
|
||||
end else if (FS[15:4]==12'hFFF && FS[0]==1'b0) begin // Repeat 8x
|
||||
// Auto-refresh
|
||||
nCS <= 1'b0;
|
||||
nRAS <= 1'b0;
|
||||
nCAS <= 1'b0;
|
||||
nRWE <= 1'b1;
|
||||
RA[10] <= 1'b0;
|
||||
end else begin // Otherwise send no-op
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
@ -306,6 +295,7 @@ module RAM2E(C14M, RCLK, PHI1, LED,
|
||||
CKE <= 1'b1;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
@ -325,6 +315,7 @@ module RAM2E(C14M, RCLK, PHI1, LED,
|
||||
CKE <= 1'b1;
|
||||
|
||||
// Activate
|
||||
nCS <= 1'b0;
|
||||
nRAS <= 1'b0;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
@ -345,6 +336,7 @@ module RAM2E(C14M, RCLK, PHI1, LED,
|
||||
CKE <= 1'b1;
|
||||
|
||||
// Read
|
||||
nCS <= 1'b0;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b0;
|
||||
nRWE <= 1'b1;
|
||||
@ -369,6 +361,7 @@ module RAM2E(C14M, RCLK, PHI1, LED,
|
||||
CKE <= 1'b1;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
@ -388,6 +381,7 @@ module RAM2E(C14M, RCLK, PHI1, LED,
|
||||
CKE <= 1'b1;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
@ -408,11 +402,13 @@ module RAM2E(C14M, RCLK, PHI1, LED,
|
||||
|
||||
if (FS[5:4]==0) begin
|
||||
// Auto-refresh
|
||||
nCS <= 1'b0;
|
||||
nRAS <= 1'b0;
|
||||
nCAS <= 1'b0;
|
||||
nRWE <= 1'b1;
|
||||
end else begin
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
@ -433,6 +429,7 @@ module RAM2E(C14M, RCLK, PHI1, LED,
|
||||
CKE <= 1'b1;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
@ -451,10 +448,11 @@ module RAM2E(C14M, RCLK, PHI1, LED,
|
||||
DOEEN <= 1'b0;
|
||||
end else if (S==4'h8) begin
|
||||
// Enable clock if '245 output enabled
|
||||
CKE <= !nEN80;
|
||||
CKE <= EN80;
|
||||
|
||||
// Activate if '245 output enabled
|
||||
nRAS <= nEN80;
|
||||
nCS <= nEN80;
|
||||
nRAS <= 1'b0;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
@ -470,21 +468,14 @@ module RAM2E(C14M, RCLK, PHI1, LED,
|
||||
// Inhibit data bus output
|
||||
DOEEN <= 1'b0;
|
||||
end else if (S==4'h9) begin
|
||||
// Keep CKE same as last clock
|
||||
// Enable clock if '245 output enabled
|
||||
CKE <= EN80;
|
||||
|
||||
// Read/Write if '245 output enabled
|
||||
|
||||
if (CKE) begin
|
||||
// Read/Write if CKE ('245 output enabled)
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b0;
|
||||
nRWE <= nWE80;
|
||||
end else begin
|
||||
// NOP
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
end
|
||||
nCS <= nEN80;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b0;
|
||||
nRWE <= nWE80;
|
||||
|
||||
// SDRAM bank still determined by RamWorks, RA[11,9:8] don't care
|
||||
BA[1:0] <= RWBank[5:4];
|
||||
@ -505,9 +496,11 @@ module RAM2E(C14M, RCLK, PHI1, LED,
|
||||
// Inhibit data bus output
|
||||
DOEEN <= 1'b0;
|
||||
end else if (S==4'hA) begin
|
||||
// Keep CKE same as last clock
|
||||
// Enable clock if '245 output enabled
|
||||
CKE <= EN80;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
@ -527,6 +520,7 @@ module RAM2E(C14M, RCLK, PHI1, LED,
|
||||
CKE <= 1'b0;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
@ -546,6 +540,7 @@ module RAM2E(C14M, RCLK, PHI1, LED,
|
||||
CKE <= 1'b0;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
@ -625,6 +620,7 @@ module RAM2E(C14M, RCLK, PHI1, LED,
|
||||
CKE <= 1'b0;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
@ -644,6 +640,7 @@ module RAM2E(C14M, RCLK, PHI1, LED,
|
||||
CKE <= 1'b0;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
@ -665,6 +662,7 @@ module RAM2E(C14M, RCLK, PHI1, LED,
|
||||
CKE <= 1'b0;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
25
CPLD/RAM2E.mif
Normal file
25
CPLD/RAM2E.mif
Normal file
@ -0,0 +1,25 @@
|
||||
-- Copyright (C) 1991-2013 Altera Corporation
|
||||
-- Your use of Altera Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Altera Program License
|
||||
-- Subscription Agreement, Altera MegaCore Function License
|
||||
-- Agreement, or other applicable license agreement, including,
|
||||
-- without limitation, that your use is for the sole purpose of
|
||||
-- programming logic devices manufactured by Altera and sold by
|
||||
-- Altera or its authorized distributors. Please refer to the
|
||||
-- applicable agreement for further details.
|
||||
|
||||
-- Quartus II generated Memory Initialization File (.mif)
|
||||
|
||||
WIDTH=16;
|
||||
DEPTH=512;
|
||||
|
||||
ADDRESS_RADIX=HEX;
|
||||
DATA_RADIX=HEX;
|
||||
|
||||
CONTENT BEGIN
|
||||
[000..1FF] : FFFF;
|
||||
END;
|
||||
File diff suppressed because it is too large
Load Diff
BIN
Hardware/LCMXO2/Documentation/RAM2E.4203B.LCMXO2-Placement 2.pdf
Normal file
BIN
Hardware/LCMXO2/Documentation/RAM2E.4203B.LCMXO2-Placement 2.pdf
Normal file
Binary file not shown.
BIN
Hardware/LCMXO2/Documentation/RAM2E.4203B.LCMXO2-Schematic 2.pdf
Normal file
BIN
Hardware/LCMXO2/Documentation/RAM2E.4203B.LCMXO2-Schematic 2.pdf
Normal file
Binary file not shown.
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user