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63 Commits 5 Branches 6 Tags
8de75a6921897d6b30e90d16ccbc4c7b11d11829
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63 Commits

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Author SHA1 Message Date
Zane Kaminski
8de75a6921 Documentation update 2023-12-18 06:28:46 -05:00
Zane Kaminski
4249ebe983 As sent to testers 2023-11-21 06:55:24 -05:00
Zane Kaminski
51ac7661ef Update .gitignore 2023-11-11 02:18:24 -05:00
Zane Kaminski
9bcec41028 Fixed LED and current-limiting resistor values in BOM 2023-11-10 22:35:04 -05:00
Zane Kaminski
7c0a611f16 Update Makefile 2023-11-07 15:35:42 -05:00
Zane Kaminski
175084877b 2.1? 2023-11-03 04:35:53 -04:00
Zane Kaminski
7f7ab90c67 Fixed MachXO board wrong JTAG pinout 2023-09-21 07:26:21 -04:00
Zane Kaminski
961bdb88d1 Merge branch 'dev-GW4203B-2.0' into dev-GW4203B 2023-09-21 05:50:11 -04:00
Zane Kaminski
101662b4e1 RC 2023-09-21 05:45:21 -04:00
Zane Kaminski
d18e1ceee4 Remove old files 2023-09-21 05:33:45 -04:00
Zane Kaminski
5223b26572 Documentation update 2021-09-04 23:56:58 -04:00
Zane Kaminski
4b4150124b Documentation update 2021-08-06 02:37:57 -04:00
Zane Kaminski
60673b3708 Documentation update 2021-08-06 02:37:29 -04:00
Zane Kaminski
7b7efec4bc Fabbed 2021-07-02 03:26:28 -04:00
Zane Kaminski
60280796a6 Zip everything 2021-06-01 05:30:29 -04:00
Zane Kaminski
9e0f509256 BOM finished 2021-06-01 05:30:16 -04:00
Zane Kaminski
e74f3aa66d DNP 3d models and add FrontIsom render pics of all board variants 2021-06-01 05:15:30 -04:00
Zane Kaminski
664faaa27c Fixed DRC violations on LCMXO2 and iCE40 boards 2021-06-01 04:25:55 -04:00
Zane Kaminski
e06b80e201 Generated gerbers and documentation 2021-06-01 04:01:07 -04:00
Zane Kaminski
6ab27bdce3 idk 2021-05-23 00:44:33 -04:00
Zane Kaminski
9b02e8fec1 still workin 2021-05-22 17:35:02 -04:00
Zane Kaminski
b071be04a9 started 2021-05-08 02:48:29 -04:00
Zane Kaminski
42417bfdd3 Documentation update 2021-04-13 03:41:45 -04:00
Zane Kaminski
0dc721a455 Add dev note 2021-04-03 00:43:41 -04:00
Zane Kaminski
f8ac2a4736 Removed old MAX II stuff from MAX V directory 2021-03-10 21:14:36 -05:00
Zane Kaminski
17c9ca9b88 Added MAX V CPLD firmware 2021-03-10 21:14:12 -05:00
Zane Kaminski
00477998dd Rename /cpld directory to /cpld_maxii 2021-03-10 20:47:44 -05:00
Zane Kaminski
a9938292b4 Add MAX V BOM and placement table 2021-02-16 14:44:27 -05:00
Zane Kaminski
0a675f1349 Documentation update 2021-01-31 15:56:55 -05:00
Zane Kaminski
b92da86ce7 Merge branch 'dev-GW4203B-1.3' into dev-GW4203B B.1.3 2021-01-28 20:39:34 -05:00
Zane Kaminski
a889b312d0 Gitignore Quartus CDFs (chain definition files) 2021-01-28 14:43:03 -05:00
Zane Kaminski
6d468781b2 Refresh rate increase compiled in Quartus 2021-01-28 14:42:44 -05:00
Zane Kaminski
884eb76df7 Merge branch 'dev-GW4203B-1.3' into dev-GW4203B 2021-01-24 08:47:56 -05:00
Zane Kaminski
2167c8e816 Merge branch 'dev-GW4203B-1.2' into dev-GW4203B B.1.2 2021-01-24 08:35:41 -05:00
Zane Kaminski
91a4ce7db0 Increased refresh frequency 2020-12-26 14:15:17 -05:00
Zane Kaminski
4e92d04692 Fabbed 2020-12-25 13:02:24 -05:00
Zane Kaminski
ed7e3c6c2f Added C14M buffering and header 2020-12-16 14:43:41 -05:00
Zane Kaminski
3065cc6dd0 Actually fabbed 10/6/2020 2020-10-09 13:02:03 -04:00
Zane Kaminski
29f76fe8fc Fabbed 9/29/2020 2020-09-29 14:59:55 -04:00
Zane Kaminski
680bbf3af6 Update timing diagram in schematic 
Now reflects longer MAX V propagation delays
 2020-09-25 13:05:58 -04:00
Zane Kaminski
2cc7729a5e Update GW4203BManual B.1.1 2020-09-18 00:47:18 -04:00
Zane Kaminski
01fd38efbf Update GW4203BManual 2020-09-18 00:45:40 -04:00
Zane Kaminski
124d7c676e Merge branch 'dev-GW4203B-1.2' of https://github.com/garrettsworkshop/RAM2E into dev-GW4203B-1.2 2020-09-17 23:32:03 -04:00
Zane Kaminski
f8c44667e8 Merge branch 'dev-GW4203B-1.2' of https://github.com/garrettsworkshop/RAM2E into dev-GW4203B-1.2 2020-09-17 23:32:01 -04:00
Zane Kaminski
e3222664b6 Fix snow on screen 
Previous commit had "snow" in 80-col mode when updating display. Put back command timing to fix problem. Kept PHI0 read gating depending on EN80 and data output gating
 2020-09-16 20:20:16 -04:00
Zane Kaminski
8104efd4a3 Improve power consumption 
Gated RAM access during PHI0, squeezed video access and MPU access together, gated data bus output buffer OE to only output at end of PHI0
 2020-09-16 19:49:18 -04:00
Zane Kaminski
2790f0b58a Updated schematic with 1V8 regulator and MAX V 2020-09-10 10:44:47 -04:00
Zane Kaminski
70fe798ca0 Working on MAX V 2020-09-09 16:35:14 -04:00
Zane Kaminski
73b9e3ede2 As submitted to JLCPCB August 21 2020 2020-08-20 22:32:17 -04:00
Zane Kaminski
9e252e3df1 Documentation update 2020-08-20 22:27:49 -04:00