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19 Commits
1bbca43cfd ... 2adbbb1517

Author SHA1 Message Date
Zane Kaminski 2adbbb1517 Just formatting changes, MAX II/V POF files identical 2024-02-15 13:46:36 -05:00
Zane Kaminski 48d821e7b4 Create Timing.png 2024-02-15 13:46:08 -05:00
Zane Kaminski 73d958c1f8 RC 2024-02-12 17:13:24 -05:00
Zane Kaminski 1937ad85e2 Firmware RC 2024-02-07 21:12:43 -05:00
Zane Kaminski 21a04dedb5 Small board revision, still v2.0 2024-02-07 20:48:53 -05:00
Zane Kaminski 5e32b9cbe9 change nVOE to be solely falling-edge register output 2024-01-31 09:44:04 -05:00
Zane Kaminski 4450161b76 Update Makefile 2024-01-31 09:40:11 -05:00
Zane Kaminski 82c12e351f Change BOM to separate U4 from U3 and U5 2024-01-30 21:02:30 -05:00
Zane Kaminski 1ec43a5a39 Delete duplicate files 2024-01-30 21:02:16 -05:00
Zane Kaminski ab6dd7bbb1 Update Makefile 2024-01-30 21:01:53 -05:00
Zane Kaminski 0bc28d5c8a nVOE change 2024-01-27 17:27:22 -05:00
Zane Kaminski 4d22a0dae6 Create Timing.json 2024-01-27 17:27:15 -05:00
Zane Kaminski 9faa06b94f Add back qws files 2024-01-19 09:33:20 -05:00
Zane Kaminski f021148c5d Fix comments 2024-01-19 09:33:12 -05:00
Zane Kaminski 5335a6ed3c fix comment 2024-01-19 06:30:04 -05:00
Zane Kaminski 4abb0873bf RC 2024-01-16 14:31:03 -05:00
Zane Kaminski 520e7edbdf MAX II/V 2.1 RC1 2024-01-11 09:34:47 -05:00
Zane Kaminski 1c1dcf9ba0 Create RAM2E-old.v 2024-01-11 09:06:31 -05:00
Zane Kaminski c72df9e5e0 idk 2024-01-08 09:20:28 -05:00
93 changed files with 193168 additions and 111695 deletions
Show Stats Expand all files Collapse all files

9
CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC_tcl.html
View File

@ -76,6 +76,15 @@ prj_run Export -impl impl1
<A name="pn231228232404"></A><B><U><big>pn231228232404</big></U></B>
#Start recording tcl command: 12/28/2023 23:23:13
#Project Location: //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC; Project name: RAM2E_LCMXO2_1200HC
prj_project open "//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC.ldf"
prj_run Export -impl impl1
#Stop recording: 12/28/2023 23:24:04
<BR>
<BR>
<BR>

18
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_bgn.html
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@ -12,10 +12,10 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Thu Dec 28 23:23:53 2023
Thu Dec 28 23:23:57 2023
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC -w -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1.ncd RAM2E_LCMXO2_1200HC_impl1.prf
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC -w -jedec -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1.ncd RAM2E_LCMXO2_1200HC_impl1.prf
Loading design for application Bitgen from file RAM2E_LCMXO2_1200HC_impl1.ncd.
Design name: RAM2E
@ -80,9 +80,19 @@ Creating bit map...
Bitstream Status: Final Version 1.95.
Saving bit stream in "RAM2E_LCMXO2_1200HC_impl1.bit".
Saving bit stream in "RAM2E_LCMXO2_1200HC_impl1.jed".
===========
UFM Summary.
===========
UFM Size: 511 Pages (128*511 Bits).
UFM Utilization: General Purpose Flash Memory.
Available General Purpose Flash Memory: 511 Pages (Page 0 to Page 510).
Initialized UFM Pages: 321 Pages (Page 190 to Page 510).
Total CPU Time: 3 secs
Total REAL Time: 4 secs
Total REAL Time: 3 secs
Peak Memory Usage: 275 MB

6
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_summary.html
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@ -24,9 +24,9 @@
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Last Process:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">JEDEC File</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000"></SPAN></TD>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">State:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">Passed</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000"></SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Target Device:</SPAN></TD>
@ -62,7 +62,7 @@
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Updated:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2023/12/28 23:24:01</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2024/01/05 05:57:03</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Location:</SPAN></TD>

2
CPLD/LCMXO2-1200HC/promote.xml
View File

@ -1,3 +1,3 @@
<?xml version="1.0" encoding="UTF-8"?>
<userSetting name="//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml" version="Diamond (64-bit) 3.12.1.454" date="Thu Dec 28 23:24:04 2023" vendor="Lattice Semiconductor Corporation" >
<userSetting name="//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml" version="Diamond (64-bit) 3.12.1.454" date="Fri Jan 05 05:58:46 2024" vendor="Lattice Semiconductor Corporation" >
</userSetting>

9
CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC_tcl.html
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@ -42,6 +42,15 @@ prj_src remove "//Mac/iCloud/Repos/ram2e/CPLD/RAM2E-LCMXO2.v"
<A name="pn231228232403"></A><B><U><big>pn231228232403</big></U></B>
#Start recording tcl command: 12/28/2023 23:23:13
#Project Location: //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC; Project name: RAM2E_LCMXO2_640HC
prj_project open "//Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC.ldf"
prj_run Export -impl impl1
#Stop recording: 12/28/2023 23:24:03
<BR>
<BR>
<BR>

18
CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_bgn.html
View File

@ -12,10 +12,10 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Thu Dec 28 23:23:51 2023
Thu Dec 28 23:23:55 2023
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC -w -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC -w -jedec -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf
Loading design for application Bitgen from file RAM2E_LCMXO2_640HC_impl1.ncd.
Design name: RAM2E
@ -80,9 +80,19 @@ Creating bit map...
Bitstream Status: Final Version 1.95.
Saving bit stream in "RAM2E_LCMXO2_640HC_impl1.bit".
Saving bit stream in "RAM2E_LCMXO2_640HC_impl1.jed".
===========
UFM Summary.
===========
UFM Size: 191 Pages (128*191 Bits).
UFM Utilization: General Purpose Flash Memory.
Available General Purpose Flash Memory: 191 Pages (Page 0 to Page 190).
Initialized UFM Pages: 1 Page (Page 190).
Total CPU Time: 3 secs
Total REAL Time: 4 secs
Total REAL Time: 3 secs
Peak Memory Usage: 267 MB

6
CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_summary.html
View File

@ -24,9 +24,9 @@
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Last Process:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">JEDEC File</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000"></SPAN></TD>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">State:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">Passed</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000"></SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Target Device:</SPAN></TD>
@ -62,7 +62,7 @@
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Updated:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2023/12/28 23:23:58</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2024/01/05 06:01:02</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Location:</SPAN></TD>

2
CPLD/LCMXO2-640HC/promote.xml
View File

@ -1,3 +1,3 @@
<?xml version="1.0" encoding="UTF-8"?>
<userSetting name="//Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml" version="Diamond (64-bit) 3.12.1.454" date="Thu Dec 28 23:24:03 2023" vendor="Lattice Semiconductor Corporation" >
<userSetting name="//Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml" version="Diamond (64-bit) 3.12.1.454" date="Fri Jan 05 06:01:06 2024" vendor="Lattice Semiconductor Corporation" >
</userSetting>

13
CPLD/MAXII/RAM2E.qsf
View File

@ -42,7 +42,7 @@ set_global_assignment -name DEVICE EPM240T100C5
set_global_assignment -name TOP_LEVEL_ENTITY RAM2E
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 19.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "07:26:23 AUGUST 20, 2023"
set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 SP0.02std Lite Edition"
set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
@ -50,9 +50,10 @@ set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V
set_global_assignment -name NUM_PARALLEL_PROCESSORS 4
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS OUTPUT DRIVING GROUND"
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V
set_location_assignment PIN_12 -to C14M
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to C14M
@ -110,7 +111,7 @@ set_location_assignment PIN_55 -to nDOE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nDOE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nDOE
set_instance_assignment -name SLOW_SLEW_RATE ON -to nDOE
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nDOE
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nDOE
set_location_assignment PIN_77 -to Dout[0]
set_location_assignment PIN_76 -to Dout[1]
@ -128,8 +129,8 @@ set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Dout
set_location_assignment PIN_50 -to nVOE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nVOE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nVOE
set_instance_assignment -name SLOW_SLEW_RATE ON -to nVOE
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nVOE
set_instance_assignment -name SLOW_SLEW_RATE OFF -to nVOE
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nVOE
set_location_assignment PIN_70 -to Vout[0]
set_location_assignment PIN_67 -to Vout[1]
@ -234,10 +235,10 @@ set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to RD
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to RD
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RD
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_location_assignment PIN_88 -to LED
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LED
set_instance_assignment -name SLOW_SLEW_RATE ON -to LED
set_global_assignment -name VERILOG_FILE ../RAM2E.v
set_global_assignment -name VERILOG_FILE "../UFM-MAX.v"
set_global_assignment -name QIP_FILE UFM.qip

BIN
CPLD/MAXII/RAM2E.qws
View File

Binary file not shown.

48
CPLD/MAXII/output_files/RAM2E.asm.rpt
View File

@ -1,6 +1,6 @@
Assembler report for RAM2E
Thu Dec 28 23:09:46 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Thu Feb 15 04:16:27 2024
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
---------------------
@ -10,7 +10,7 @@ Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Editio
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pof
5. Assembler Device Options: /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pof
6. Assembler Messages
@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Thu Dec 28 23:09:46 2023 ;
; Assembler Status ; Successful - Thu Feb 15 04:16:27 2024 ;
; Revision Name ; RAM2E ;
; Top-level Entity Name ; RAM2E ;
; Family ; MAX II ;
@ -53,23 +53,23 @@ https://fpgasoftware.intel.com/eula.
+--------+---------+---------------+
+--------------------------------------------------+
; Assembler Generated Files ;
+--------------------------------------------------+
; File Name ;
+--------------------------------------------------+
; Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pof ;
+--------------------------------------------------+
+------------------------------------------------+
; Assembler Generated Files ;
+------------------------------------------------+
; File Name ;
+------------------------------------------------+
; /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pof ;
+------------------------------------------------+
+----------------------------------------------------------------------------+
; Assembler Device Options: Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pof ;
+----------------+-----------------------------------------------------------+
; Option ; Setting ;
+----------------+-----------------------------------------------------------+
; JTAG usercode ; 0x00165DEE ;
; Checksum ; 0x0016605E ;
+----------------+-----------------------------------------------------------+
+--------------------------------------------------------------------------+
; Assembler Device Options: /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pof ;
+----------------+---------------------------------------------------------+
; Option ; Setting ;
+----------------+---------------------------------------------------------+
; JTAG usercode ; 0x00164C21 ;
; Checksum ; 0x00165119 ;
+----------------+---------------------------------------------------------+
+--------------------+
@ -77,15 +77,15 @@ https://fpgasoftware.intel.com/eula.
+--------------------+
Info: *******************************************************************
Info: Running Quartus Prime Assembler
Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Info: Processing started: Thu Dec 28 23:09:46 2023
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Info: Processing started: Thu Feb 15 04:16:25 2024
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2E-MAXII -c RAM2E
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 13071 megabytes
Info: Processing ended: Thu Dec 28 23:09:47 2023
Info: Elapsed time: 00:00:01
Info: Peak virtual memory: 13103 megabytes
Info: Processing ended: Thu Feb 15 04:16:27 2024
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:01

2
CPLD/MAXII/output_files/RAM2E.done
View File

@ -1 +1 @@
Thu Dec 28 23:09:51 2023
Thu Feb 15 04:16:32 2024

309
CPLD/MAXII/output_files/RAM2E.fit.rpt
View File

@ -1,6 +1,6 @@
Fitter report for RAM2E
Thu Dec 28 23:09:44 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Thu Feb 15 04:16:23 2024
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
---------------------
@ -54,21 +54,21 @@ https://fpgasoftware.intel.com/eula.
+-------------------------------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+-------------------------------------------------------------+
; Fitter Status ; Successful - Thu Dec 28 23:09:44 2023 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
; Revision Name ; RAM2E ;
; Top-level Entity Name ; RAM2E ;
; Family ; MAX II ;
; Device ; EPM240T100C5 ;
; Timing Models ; Final ;
; Total logic elements ; 238 / 240 ( 99 % ) ;
; Total pins ; 70 / 80 ( 88 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
+-----------------------+-------------------------------------------------------------+
+---------------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+---------------------------------------------+
; Fitter Status ; Successful - Thu Feb 15 04:16:23 2024 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
; Revision Name ; RAM2E ;
; Top-level Entity Name ; RAM2E ;
; Family ; MAX II ;
; Device ; EPM240T100C5 ;
; Timing Models ; Final ;
; Total logic elements ; 238 / 240 ( 99 % ) ;
; Total pins ; 70 / 80 ( 88 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
+-----------------------+---------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------+
@ -134,7 +134,7 @@ https://fpgasoftware.intel.com/eula.
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processor 2 ; 1.1% ;
; Processor 2 ; 1.2% ;
; Processors 3-4 ; 1.0% ;
+----------------------------+-------------+
@ -142,7 +142,7 @@ https://fpgasoftware.intel.com/eula.
+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pin.
The pin-out file can be found in /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pin.
+---------------------------------------------------------------------+
@ -151,26 +151,26 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pi
; Resource ; Usage ;
+---------------------------------------------+-----------------------+
; Total logic elements ; 238 / 240 ( 99 % ) ;
; -- Combinational with no register ; 115 ;
; -- Register only ; 26 ;
; -- Combinational with a register ; 97 ;
; -- Combinational with no register ; 112 ;
; -- Register only ; 19 ;
; -- Combinational with a register ; 107 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 118 ;
; -- 3 input functions ; 41 ;
; -- 2 input functions ; 48 ;
; -- 1 input functions ; 4 ;
; -- 4 input functions ; 116 ;
; -- 3 input functions ; 53 ;
; -- 2 input functions ; 46 ;
; -- 1 input functions ; 3 ;
; -- 0 input functions ; 1 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 224 ;
; -- arithmetic mode ; 14 ;
; -- qfbk mode ; 6 ;
; -- qfbk mode ; 14 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 24 ;
; -- synchronous clear/load mode ; 26 ;
; -- asynchronous clear/load mode ; 0 ;
; ; ;
; Total registers ; 123 / 240 ( 51 % ) ;
; Total registers ; 126 / 240 ( 53 % ) ;
; Total LABs ; 24 / 24 ( 100 % ) ;
; Logic elements in carry chains ; 15 ;
; Virtual pins ; 0 ;
@ -182,15 +182,15 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pi
; -- Total Fixed Point DSP Blocks ; 0 ;
; -- Total Floating Point DSP Blocks ; 0 ;
; ; ;
; Global signals ; 1 ;
; -- Global clocks ; 1 / 4 ( 25 % ) ;
; Global signals ; 2 ;
; -- Global clocks ; 2 / 4 ( 50 % ) ;
; JTAGs ; 0 / 1 ( 0 % ) ;
; Average interconnect usage (total/H/V) ; 26.0% / 25.7% / 26.3% ;
; Peak interconnect usage (total/H/V) ; 26.0% / 25.7% / 26.3% ;
; Maximum fan-out ; 123 ;
; Highest non-global fan-out ; 35 ;
; Total fan-out ; 976 ;
; Average fan-out ; 3.16 ;
; Average interconnect usage (total/H/V) ; 29.9% / 32.0% / 27.7% ;
; Peak interconnect usage (total/H/V) ; 29.9% / 32.0% / 27.7% ;
; Maximum fan-out ; 122 ;
; Highest non-global fan-out ; 34 ;
; Total fan-out ; 992 ;
; Average fan-out ; 3.21 ;
+---------------------------------------------+-----------------------+
@ -199,15 +199,15 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pi
+--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+----------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Location assigned by ; Slow Slew Rate ;
+--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+----------------+
; Ain[0] ; 56 ; 2 ; 8 ; 1 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Ain[1] ; 54 ; 2 ; 8 ; 1 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Ain[2] ; 43 ; 1 ; 6 ; 0 ; 3 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Ain[3] ; 47 ; 1 ; 6 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Ain[4] ; 44 ; 1 ; 6 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Ain[5] ; 34 ; 1 ; 3 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Ain[6] ; 39 ; 1 ; 5 ; 0 ; 3 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Ain[7] ; 53 ; 2 ; 8 ; 1 ; 3 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; C14M ; 12 ; 1 ; 1 ; 3 ; 3 ; 123 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Ain[0] ; 56 ; 2 ; 8 ; 1 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Ain[1] ; 54 ; 2 ; 8 ; 1 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Ain[2] ; 43 ; 1 ; 6 ; 0 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Ain[3] ; 47 ; 1 ; 6 ; 0 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Ain[4] ; 44 ; 1 ; 6 ; 0 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Ain[5] ; 34 ; 1 ; 3 ; 0 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Ain[6] ; 39 ; 1 ; 5 ; 0 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Ain[7] ; 53 ; 2 ; 8 ; 1 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; C14M ; 12 ; 1 ; 1 ; 3 ; 3 ; 122 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[0] ; 38 ; 1 ; 4 ; 0 ; 0 ; 15 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[1] ; 40 ; 1 ; 5 ; 0 ; 2 ; 11 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[2] ; 42 ; 1 ; 5 ; 0 ; 0 ; 13 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
@ -215,11 +215,11 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pi
; Din[4] ; 48 ; 1 ; 6 ; 0 ; 0 ; 10 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[5] ; 49 ; 1 ; 7 ; 0 ; 2 ; 9 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[6] ; 36 ; 1 ; 4 ; 0 ; 2 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[7] ; 35 ; 1 ; 3 ; 0 ; 0 ; 9 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; PHI1 ; 37 ; 1 ; 4 ; 0 ; 1 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[7] ; 35 ; 1 ; 3 ; 0 ; 0 ; 10 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; PHI1 ; 37 ; 1 ; 4 ; 0 ; 1 ; 5 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; nC07X ; 52 ; 2 ; 8 ; 1 ; 4 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; nEN80 ; 28 ; 1 ; 2 ; 0 ; 1 ; 10 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; nWE ; 51 ; 1 ; 7 ; 0 ; 0 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; nWE ; 51 ; 1 ; 7 ; 0 ; 0 ; 9 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; nWE80 ; 33 ; 1 ; 3 ; 0 ; 2 ; 0 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
+--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+----------------+
@ -242,33 +242,33 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pi
; Dout[5] ; 72 ; 2 ; 8 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; Dout[6] ; 84 ; 2 ; 6 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; Dout[7] ; 85 ; 2 ; 5 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; LED ; 88 ; 2 ; 5 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; RAout[0] ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; LED ; 88 ; 2 ; 5 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; - ; - ;
; RAout[0] ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RAout[10] ; 16 ; 1 ; 1 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; RAout[11] ; 7 ; 1 ; 1 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; RAout[1] ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; RAout[2] ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; RAout[3] ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; RAout[4] ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; RAout[5] ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; RAout[6] ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; RAout[7] ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; RAout[1] ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RAout[2] ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RAout[3] ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RAout[4] ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RAout[5] ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RAout[6] ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RAout[7] ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RAout[8] ; 17 ; 1 ; 1 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; RAout[9] ; 15 ; 1 ; 1 ; 2 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[0] ; 70 ; 2 ; 8 ; 4 ; 4 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; Vout[1] ; 67 ; 2 ; 8 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[2] ; 69 ; 2 ; 8 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[3] ; 62 ; 2 ; 8 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; Vout[2] ; 69 ; 2 ; 8 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; Vout[3] ; 62 ; 2 ; 8 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[4] ; 71 ; 2 ; 8 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[5] ; 68 ; 2 ; 8 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[6] ; 58 ; 2 ; 8 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[7] ; 57 ; 2 ; 8 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; nCASout ; 3 ; 1 ; 1 ; 4 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; nCSout ; 8 ; 1 ; 1 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; nDOE ; 55 ; 2 ; 8 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; nRASout ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; nDOE ; 55 ; 2 ; 8 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; nRASout ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; nRWEout ; 2 ; 1 ; 1 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; nVOE ; 50 ; 1 ; 7 ; 0 ; 1 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; nVOE ; 50 ; 1 ; 7 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
+-----------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
@ -352,12 +352,12 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pi
; 47 ; 37 ; 1 ; Ain[3] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 48 ; 38 ; 1 ; Din[4] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 49 ; 39 ; 1 ; Din[5] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 50 ; 40 ; 1 ; nVOE ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; On ;
; 50 ; 40 ; 1 ; nVOE ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 51 ; 41 ; 1 ; nWE ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 52 ; 42 ; 2 ; nC07X ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 53 ; 43 ; 2 ; Ain[7] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 54 ; 44 ; 2 ; Ain[1] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 55 ; 45 ; 2 ; nDOE ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; On ;
; 55 ; 45 ; 2 ; nDOE ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 56 ; 46 ; 2 ; Ain[0] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 57 ; 47 ; 2 ; Vout[7] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 58 ; 48 ; 2 ; Vout[6] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
@ -428,8 +428,8 @@ Note: User assignments will override these defaults. The user specified values a
+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
; |RAM2E ; 238 (180) ; 123 ; 1 ; 70 ; 0 ; 115 (90) ; 26 (23) ; 97 (67) ; 15 (15) ; 6 (1) ; |RAM2E ; RAM2E ; work ;
; |RAM2E_UFM:ram2e_ufm| ; 58 (58) ; 33 ; 1 ; 0 ; 0 ; 25 (25) ; 3 (3) ; 30 (30) ; 0 (0) ; 5 (5) ; |RAM2E|RAM2E_UFM:ram2e_ufm ; RAM2E_UFM ; work ;
; |RAM2E ; 238 (182) ; 126 ; 1 ; 70 ; 0 ; 112 (88) ; 19 (16) ; 107 (78) ; 15 (15) ; 14 (9) ; |RAM2E ; RAM2E ; work ;
; |RAM2E_UFM:ram2e_ufm| ; 56 (56) ; 32 ; 1 ; 0 ; 0 ; 24 (24) ; 3 (3) ; 29 (29) ; 0 (0) ; 5 (5) ; |RAM2E|RAM2E_UFM:ram2e_ufm ; RAM2E_UFM ; work ;
; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst ; UFM ; work ;
; |UFM_altufm_none_lbr:UFM_altufm_none_lbr_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component ; UFM_altufm_none_lbr ; work ;
+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
@ -492,17 +492,6 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; RD[7] ; Bidir ; (0) ;
; nEN80 ; Input ; (0) ;
; nWE ; Input ; (0) ;
; PHI1 ; Input ; (1) ;
; C14M ; Input ; (0) ;
; Din[0] ; Input ; (0) ;
; Din[6] ; Input ; (0) ;
; Din[1] ; Input ; (0) ;
; Din[5] ; Input ; (0) ;
; Din[7] ; Input ; (0) ;
; Din[4] ; Input ; (0) ;
; Din[2] ; Input ; (0) ;
; Din[3] ; Input ; (0) ;
; nC07X ; Input ; (0) ;
; Ain[0] ; Input ; (0) ;
; Ain[1] ; Input ; (0) ;
; Ain[2] ; Input ; (0) ;
@ -511,6 +500,17 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Ain[5] ; Input ; (0) ;
; Ain[6] ; Input ; (0) ;
; Ain[7] ; Input ; (0) ;
; C14M ; Input ; (0) ;
; Din[0] ; Input ; (0) ;
; Din[6] ; Input ; (0) ;
; PHI1 ; Input ; (1) ;
; Din[1] ; Input ; (0) ;
; Din[5] ; Input ; (0) ;
; Din[7] ; Input ; (0) ;
; Din[4] ; Input ; (0) ;
; Din[2] ; Input ; (0) ;
; Din[3] ; Input ; (0) ;
; nC07X ; Input ; (0) ;
+-----------+----------+---------------+
@ -519,22 +519,22 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+--------------------------------+-------------+---------+---------------+--------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
+--------------------------------+-------------+---------+---------------+--------+----------------------+------------------+
; BA[1]~0 ; LC_X2_Y2_N7 ; 2 ; Clock enable ; no ; -- ; -- ;
; C14M ; PIN_12 ; 123 ; Clock ; yes ; Global Clock ; GCLK0 ;
; CS[0]~2 ; LC_X6_Y4_N2 ; 3 ; Clock enable ; no ; -- ; -- ;
; DQML~0 ; LC_X2_Y4_N0 ; 2 ; Clock enable ; no ; -- ; -- ;
; Equal1~1 ; LC_X7_Y4_N1 ; 8 ; Clock enable ; no ; -- ; -- ;
; Equal1~2 ; LC_X7_Y4_N2 ; 8 ; Clock enable ; no ; -- ; -- ;
; Equal1~4 ; LC_X5_Y4_N7 ; 4 ; Clock enable ; no ; -- ; -- ;
; Equal1~5 ; LC_X4_Y4_N9 ; 3 ; Clock enable ; no ; -- ; -- ;
; Mux14~0 ; LC_X2_Y2_N0 ; 2 ; Clock enable ; no ; -- ; -- ;
; RAM2E_UFM:ram2e_ufm|RWMask~1 ; LC_X6_Y1_N3 ; 8 ; Clock enable ; no ; -- ; -- ;
; RAM2E_UFM:ram2e_ufm|UFMD[15]~1 ; LC_X4_Y1_N1 ; 8 ; Clock enable ; no ; -- ; -- ;
; RAM2E_UFM:ram2e_ufm|always2~8 ; LC_X7_Y4_N3 ; 16 ; Clock enable ; no ; -- ; -- ;
; RA[2]~0 ; LC_X2_Y2_N5 ; 6 ; Clock enable ; no ; -- ; -- ;
; RDOE ; LC_X7_Y2_N7 ; 8 ; Output enable ; no ; -- ; -- ;
; S[0] ; LC_X7_Y3_N8 ; 35 ; Sync. clear ; no ; -- ; -- ;
; S[3] ; LC_X5_Y4_N6 ; 32 ; Sync. clear ; no ; -- ; -- ;
; BA[0]~0 ; LC_X2_Y3_N8 ; 2 ; Clock enable ; no ; -- ; -- ;
; BA[0]~1 ; LC_X4_Y3_N9 ; 3 ; Clock enable ; no ; -- ; -- ;
; C14M ; PIN_12 ; 122 ; Clock ; yes ; Global Clock ; GCLK0 ;
; CS[0]~2 ; LC_X4_Y2_N7 ; 3 ; Clock enable ; no ; -- ; -- ;
; DQML~0 ; LC_X2_Y4_N7 ; 2 ; Clock enable ; no ; -- ; -- ;
; Equal1~1 ; LC_X4_Y2_N1 ; 8 ; Clock enable ; no ; -- ; -- ;
; Equal1~2 ; LC_X6_Y3_N7 ; 8 ; Clock enable ; no ; -- ; -- ;
; Mux14~0 ; LC_X2_Y3_N5 ; 2 ; Clock enable ; no ; -- ; -- ;
; PHI1 ; PIN_37 ; 5 ; Clock ; yes ; Global Clock ; GCLK3 ;
; RAM2E_UFM:ram2e_ufm|RWMask~1 ; LC_X6_Y2_N1 ; 8 ; Clock enable ; no ; -- ; -- ;
; RAM2E_UFM:ram2e_ufm|UFMD[15]~1 ; LC_X3_Y1_N0 ; 8 ; Clock enable ; no ; -- ; -- ;
; RAM2E_UFM:ram2e_ufm|always2~8 ; LC_X4_Y2_N0 ; 16 ; Clock enable ; no ; -- ; -- ;
; RA[1]~2 ; LC_X2_Y3_N1 ; 6 ; Clock enable ; no ; -- ; -- ;
; RDOE ; LC_X5_Y4_N7 ; 8 ; Output enable ; no ; -- ; -- ;
; S[0] ; LC_X6_Y4_N8 ; 32 ; Sync. clear ; no ; -- ; -- ;
; S[3] ; LC_X6_Y4_N1 ; 34 ; Sync. clear ; no ; -- ; -- ;
+--------------------------------+-------------+---------+---------------+--------+----------------------+------------------+
@ -543,7 +543,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+------+----------+---------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
+------+----------+---------+----------------------+------------------+
; C14M ; PIN_12 ; 123 ; Global Clock ; GCLK0 ;
; C14M ; PIN_12 ; 122 ; Global Clock ; GCLK0 ;
; PHI1 ; PIN_37 ; 5 ; Global Clock ; GCLK3 ;
+------+----------+---------+----------------------+------------------+
@ -552,13 +553,13 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+-----------------------+--------------------+
; Routing Resource Type ; Usage ;
+-----------------------+--------------------+
; C4s ; 163 / 784 ( 21 % ) ;
; Direct links ; 46 / 888 ( 5 % ) ;
; Global clocks ; 1 / 4 ( 25 % ) ;
; LAB clocks ; 6 / 32 ( 19 % ) ;
; LUT chains ; 9 / 216 ( 4 % ) ;
; Local interconnects ; 324 / 888 ( 36 % ) ;
; R4s ; 142 / 704 ( 20 % ) ;
; C4s ; 173 / 784 ( 22 % ) ;
; Direct links ; 43 / 888 ( 5 % ) ;
; Global clocks ; 2 / 4 ( 50 % ) ;
; LAB clocks ; 7 / 32 ( 22 % ) ;
; LUT chains ; 7 / 216 ( 3 % ) ;
; Local interconnects ; 340 / 888 ( 38 % ) ;
; R4s ; 174 / 704 ( 25 % ) ;
+-----------------------+--------------------+
@ -583,19 +584,19 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+-------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+------------------------------+
; LAB-wide Signals (Average = 1.54) ; Number of LABs (Total = 24) ;
; LAB-wide Signals (Average = 1.50) ; Number of LABs (Total = 24) ;
+------------------------------------+------------------------------+
; 1 Clock ; 23 ;
; 1 Clock enable ; 10 ;
; 1 Clock ; 22 ;
; 1 Clock enable ; 9 ;
; 1 Sync. clear ; 2 ;
; 2 Clock enables ; 2 ;
; 2 Clock enables ; 3 ;
+------------------------------------+------------------------------+
+-----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+----------------------------------------------+------------------------------+
; Number of Signals Sourced (Average = 10.17) ; Number of LABs (Total = 24) ;
; Number of Signals Sourced (Average = 10.13) ; Number of LABs (Total = 24) ;
+----------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
@ -607,8 +608,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; 7 ; 0 ;
; 8 ; 1 ;
; 9 ; 0 ;
; 10 ; 21 ;
; 11 ; 1 ;
; 10 ; 22 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 0 ;
@ -622,52 +623,49 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Number of Signals Sourced Out (Average = 7.08) ; Number of LABs (Total = 24) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 1 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 2 ;
; 4 ; 1 ;
; 5 ; 3 ;
; 6 ; 2 ;
; 7 ; 3 ;
; 8 ; 4 ;
; 9 ; 4 ;
; 10 ; 3 ;
; 6 ; 3 ;
; 7 ; 4 ;
; 8 ; 5 ;
; 9 ; 3 ;
; 10 ; 2 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 1 ;
; 12 ; 1 ;
+-------------------------------------------------+------------------------------+
+-----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+----------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 12.17) ; Number of LABs (Total = 24) ;
; Number of Distinct Inputs (Average = 12.50) ; Number of LABs (Total = 24) ;
+----------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 2 ; 1 ;
; 3 ; 0 ;
; 4 ; 1 ;
; 4 ; 2 ;
; 5 ; 0 ;
; 6 ; 1 ;
; 7 ; 2 ;
; 8 ; 2 ;
; 9 ; 1 ;
; 10 ; 2 ;
; 11 ; 1 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 1 ;
; 9 ; 2 ;
; 10 ; 1 ;
; 11 ; 4 ;
; 12 ; 3 ;
; 13 ; 3 ;
; 14 ; 1 ;
; 15 ; 1 ;
; 13 ; 1 ;
; 14 ; 2 ;
; 15 ; 0 ;
; 16 ; 2 ;
; 17 ; 2 ;
; 17 ; 0 ;
; 18 ; 1 ;
; 19 ; 0 ;
; 19 ; 1 ;
; 20 ; 0 ;
; 21 ; 0 ;
; 22 ; 0 ;
; 23 ; 0 ;
; 24 ; 1 ;
; 21 ; 2 ;
; 22 ; 1 ;
+----------------------------------------------+------------------------------+
@ -702,6 +700,8 @@ Info (176444): Device migration not selected. If you intend to use device migrat
Info (176445): Device EPM570T100A5 is compatible
Info (332104): Reading SDC File: '../RAM2E.sdc'
Info (332104): Reading SDC File: '../RAM2E-MAX.sdc'
Warning (332060): Node: PHI1 was determined to be a clock but was found without an associated clock assignment.
Info (13166): Register RefReq is being clocked by PHI1
Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
Info (332111): Found 3 clocks
Info (332111): Period Clock Name
@ -710,38 +710,51 @@ Info (332111): Found 3 clocks
Info (332111): 200.000 ram2e_ufm|ARCLK|regout
Info (332111): 200.000 ram2e_ufm|DRCLK|regout
Info (186079): Completed User Assigned Global Signals Promotion Operation
Info (186215): Automatically promoted signal "C14M" to use Global clock in PIN 12 File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 8
Info (186215): Automatically promoted signal "C14M" to use Global clock in PIN 12 File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 8
Info (186216): Automatically promoted some destinations of signal "PHI1" to use Global clock File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 8
Info (186217): Destination "PHI1r" may be non-global or may not use global clock File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 20
Info (186217): Destination "S~0" may be non-global or may not use global clock File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 19
Info (186228): Pin "PHI1" drives global clock, but is not placed in a dedicated clock pin position File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 8
Info (186079): Completed Auto Global Promotion Operation
Info (176234): Starting register packing
Info (186468): Started processing fast register assignments
Warning (186473): Ignored the FAST_OUTPUT_REGISTER assignment made to the following nodes
Warning (186484): Ignored assignment to node "RAout[0]" because node "RAr[0]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85
Warning (186484): Ignored assignment to node "RAout[1]" because node "RAr[1]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85
Warning (186484): Ignored assignment to node "RAout[2]" because node "RAr[2]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85
Warning (186484): Ignored assignment to node "RAout[3]" because node "RAr[3]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85
Warning (186484): Ignored assignment to node "RAout[4]" because node "RAr[4]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85
Warning (186484): Ignored assignment to node "RAout[5]" because node "RAr[5]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85
Warning (186484): Ignored assignment to node "RAout[6]" because node "RAr[6]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85
Warning (186484): Ignored assignment to node "RAout[7]" because node "RAr[7]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85
Info (186469): Finished processing fast register assignments
Info (176235): Finished register packing
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00
Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
Info (170189): Fitter placement preparation operations beginning
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01
Info (170191): Fitter placement operations beginning
Info (170137): Fitter placement was successful
Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
Info (170192): Fitter placement operations ending: elapsed time is 00:00:02
Info (170193): Fitter routing operations beginning
Info (170089): 5e+01 ns of routing delay (approximately 3.0% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report.
Info (170195): Router estimated average interconnect usage is 24% of the available device resources
Info (170196): Router estimated peak interconnect usage is 24% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
Info (170089): 5e+01 ns of routing delay (approximately 3.3% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report.
Info (170195): Router estimated average interconnect usage is 26% of the available device resources
Info (170196): Router estimated peak interconnect usage is 26% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
Info (170202): The Fitter performed an Auto Fit compilation. No optimizations were skipped because the design's timing and routability requirements required full optimization.
Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
Info (11888): Total time spent on timing analysis during the Fitter is 0.84 seconds.
Info (11888): Total time spent on timing analysis during the Fitter is 0.97 seconds.
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
Info (144001): Generated suppressed messages file Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.fit.smsg
Info: Quartus Prime Fitter was successful. 0 errors, 1 warning
Info: Peak virtual memory: 13747 megabytes
Info: Processing ended: Thu Dec 28 23:09:44 2023
Info: Elapsed time: 00:00:04
Info (144001): Generated suppressed messages file /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.fit.smsg
Info: Quartus Prime Fitter was successful. 0 errors, 11 warnings
Info: Peak virtual memory: 13770 megabytes
Info: Processing ended: Thu Feb 15 04:16:23 2024
Info: Elapsed time: 00:00:08
Info: Total CPU time (on all processors): 00:00:04
+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.fit.smsg.
The suppressed messages can be found in /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.fit.smsg.

4
CPLD/MAXII/output_files/RAM2E.fit.summary
View File

@ -1,5 +1,5 @@
Fitter Status : Successful - Thu Dec 28 23:09:44 2023
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Fitter Status : Successful - Thu Feb 15 04:16:23 2024
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Revision Name : RAM2E
Top-level Entity Name : RAM2E
Family : MAX II

48
CPLD/MAXII/output_files/RAM2E.flow.rpt
View File

@ -1,6 +1,6 @@
Flow report for RAM2E
Thu Dec 28 23:09:50 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Thu Feb 15 04:16:31 2024
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
---------------------
@ -38,21 +38,21 @@ https://fpgasoftware.intel.com/eula.
+-------------------------------------------------------------------------------------+
; Flow Summary ;
+-----------------------+-------------------------------------------------------------+
; Flow Status ; Successful - Thu Dec 28 23:09:46 2023 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
; Revision Name ; RAM2E ;
; Top-level Entity Name ; RAM2E ;
; Family ; MAX II ;
; Device ; EPM240T100C5 ;
; Timing Models ; Final ;
; Total logic elements ; 238 / 240 ( 99 % ) ;
; Total pins ; 70 / 80 ( 88 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
+-----------------------+-------------------------------------------------------------+
+---------------------------------------------------------------------+
; Flow Summary ;
+-----------------------+---------------------------------------------+
; Flow Status ; Successful - Thu Feb 15 04:16:27 2024 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
; Revision Name ; RAM2E ;
; Top-level Entity Name ; RAM2E ;
; Family ; MAX II ;
; Device ; EPM240T100C5 ;
; Timing Models ; Final ;
; Total logic elements ; 238 / 240 ( 99 % ) ;
; Total pins ; 70 / 80 ( 88 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
+-----------------------+---------------------------------------------+
+-----------------------------------------+
@ -60,7 +60,7 @@ https://fpgasoftware.intel.com/eula.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 12/28/2023 23:09:12 ;
; Start date & time ; 02/15/2024 04:15:27 ;
; Main task ; Compilation ;
; Revision Name ; RAM2E ;
+-------------------+---------------------+
@ -71,7 +71,7 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------+------------------------------+---------------+-------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+---------------------------------------+------------------------------+---------------+-------------+------------+
; COMPILER_SIGNATURE_ID ; 121381084694.170382295203604 ; -- ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 121380219419.170798852707820 ; -- ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; NUM_PARALLEL_PROCESSORS ; 4 ; -- ; -- ; -- ;
@ -86,11 +86,11 @@ https://fpgasoftware.intel.com/eula.
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:28 ; 1.0 ; 13113 MB ; 00:00:42 ;
; Fitter ; 00:00:04 ; 1.0 ; 13747 MB ; 00:00:04 ;
; Assembler ; 00:00:00 ; 1.0 ; 13067 MB ; 00:00:01 ;
; Timing Analyzer ; 00:00:02 ; 1.0 ; 13064 MB ; 00:00:02 ;
; Total ; 00:00:34 ; -- ; -- ; 00:00:49 ;
; Analysis & Synthesis ; 00:00:47 ; 1.0 ; 13146 MB ; 00:00:47 ;
; Fitter ; 00:00:08 ; 1.0 ; 13770 MB ; 00:00:04 ;
; Assembler ; 00:00:02 ; 1.0 ; 13099 MB ; 00:00:01 ;
; Timing Analyzer ; 00:00:02 ; 1.0 ; 13089 MB ; 00:00:02 ;
; Total ; 00:00:59 ; -- ; -- ; 00:00:54 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+

2
CPLD/MAXII/output_files/RAM2E.jdi
View File

@ -1,6 +1,6 @@
<sld_project_info>
<project>
<hash md5_digest_80b="f1177731eb35f907c990"/>
<hash md5_digest_80b="c40857e37f967e83d8af"/>
</project>
<file_info>
<file device="EPM240T100C5" path="RAM2E.sof" usercode="0xFFFFFFFF"/>

183
CPLD/MAXII/output_files/RAM2E.map.rpt
View File

@ -1,6 +1,6 @@
Analysis & Synthesis report for RAM2E
Thu Dec 28 23:09:39 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Thu Feb 15 04:16:13 2024
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
---------------------
@ -43,19 +43,19 @@ https://fpgasoftware.intel.com/eula.
+-------------------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+-------------------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Dec 28 23:09:39 2023 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
; Revision Name ; RAM2E ;
; Top-level Entity Name ; RAM2E ;
; Family ; MAX II ;
; Total logic elements ; 244 ;
; Total pins ; 70 ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
+-----------------------------+-------------------------------------------------------------+
+---------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+---------------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Feb 15 04:16:13 2024 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
; Revision Name ; RAM2E ;
; Top-level Entity Name ; RAM2E ;
; Family ; MAX II ;
; Total logic elements ; 252 ;
; Total pins ; 70 ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
+-----------------------------+---------------------------------------------+
+------------------------------------------------------------------------------------------------------------+
@ -146,16 +146,16 @@ https://fpgasoftware.intel.com/eula.
+----------------------------+-------------+
+-----------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+----------------------------------+---------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+----------------------------------+---------------------------------+---------+
; ../RAM2E.v ; yes ; User Verilog HDL File ; Y:/Repos/RAM2E/CPLD/RAM2E.v ; ;
; ../UFM-MAX.v ; yes ; User Verilog HDL File ; Y:/Repos/RAM2E/CPLD/UFM-MAX.v ; ;
; UFM.v ; yes ; User Wizard-Generated File ; Y:/Repos/RAM2E/CPLD/MAXII/UFM.v ; ;
; ../RAM2E.mif ; yes ; User Memory Initialization File ; Y:/Repos/RAM2E/CPLD/RAM2E.mif ; ;
+----------------------------------+-----------------+----------------------------------+---------------------------------+---------+
+-------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+----------------------------------+-----------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+----------------------------------+-----------------------------------------+---------+
; ../RAM2E.v ; yes ; User Verilog HDL File ; //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v ; ;
; ../UFM-MAX.v ; yes ; User Verilog HDL File ; //Mac/Home/Repos/RAM2E/CPLD/UFM-MAX.v ; ;
; UFM.v ; yes ; User Wizard-Generated File ; //Mac/Home/Repos/RAM2E/CPLD/MAXII/UFM.v ; ;
; ../RAM2E.mif ; yes ; User Memory Initialization File ; //Mac/Home/Repos/RAM2E/CPLD/RAM2E.mif ; ;
+----------------------------------+-----------------+----------------------------------+-----------------------------------------+---------+
+-----------------------------------------------------+
@ -163,33 +163,33 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------+-------+
; Resource ; Usage ;
+---------------------------------------------+-------+
; Total logic elements ; 244 ;
; -- Combinational with no register ; 121 ;
; -- Register only ; 32 ;
; -- Combinational with a register ; 91 ;
; Total logic elements ; 252 ;
; -- Combinational with no register ; 126 ;
; -- Register only ; 33 ;
; -- Combinational with a register ; 93 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 118 ;
; -- 3 input functions ; 41 ;
; -- 2 input functions ; 48 ;
; -- 1 input functions ; 4 ;
; -- 4 input functions ; 116 ;
; -- 3 input functions ; 53 ;
; -- 2 input functions ; 46 ;
; -- 1 input functions ; 3 ;
; -- 0 input functions ; 1 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 230 ;
; -- normal mode ; 238 ;
; -- arithmetic mode ; 14 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 3 ;
; -- asynchronous clear/load mode ; 0 ;
; ; ;
; Total registers ; 123 ;
; Total registers ; 126 ;
; Total logic cells in carry chains ; 15 ;
; I/O pins ; 70 ;
; UFM blocks ; 1 ;
; Maximum fan-out node ; C14M ;
; Maximum fan-out ; 123 ;
; Total fan-out ; 977 ;
; Maximum fan-out ; 122 ;
; Total fan-out ; 1001 ;
; Average fan-out ; 3.10 ;
+---------------------------------------------+-------+
@ -199,8 +199,8 @@ https://fpgasoftware.intel.com/eula.
+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
; |RAM2E ; 244 (181) ; 123 ; 1 ; 70 ; 0 ; 121 (91) ; 32 (24) ; 91 (66) ; 15 (15) ; 0 (0) ; |RAM2E ; RAM2E ; work ;
; |RAM2E_UFM:ram2e_ufm| ; 63 (63) ; 33 ; 1 ; 0 ; 0 ; 30 (30) ; 8 (8) ; 25 (25) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm ; RAM2E_UFM ; work ;
; |RAM2E ; 252 (191) ; 126 ; 1 ; 70 ; 0 ; 126 (97) ; 33 (25) ; 93 (69) ; 15 (15) ; 0 (0) ; |RAM2E ; RAM2E ; work ;
; |RAM2E_UFM:ram2e_ufm| ; 61 (61) ; 32 ; 1 ; 0 ; 0 ; 29 (29) ; 8 (8) ; 24 (24) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm ; RAM2E_UFM ; work ;
; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst ; UFM ; work ;
; |UFM_altufm_none_lbr:UFM_altufm_none_lbr_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component ; UFM_altufm_none_lbr ; work ;
+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
@ -221,32 +221,33 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 123 ;
; Total registers ; 126 ;
; Number of registers using Synchronous Clear ; 3 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 62 ;
; Number of registers using Clock Enable ; 59 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------+
; Inverted Register Statistics ;
+----------------------------------------+---------+
; Inverted Register ; Fan out ;
+----------------------------------------+---------+
; nRASout~reg0 ; 1 ;
; nCASout~reg0 ; 1 ;
; nRWEout~reg0 ; 1 ;
; DQML~reg0 ; 1 ;
; DQMH~reg0 ; 1 ;
; CKE ; 1 ;
; nRAS ; 1 ;
; nCAS ; 1 ;
; nRWE ; 1 ;
; Total number of inverted registers = 9 ; ;
+----------------------------------------+---------+
+---------------------------------------------------+
; Inverted Register Statistics ;
+-----------------------------------------+---------+
; Inverted Register ; Fan out ;
+-----------------------------------------+---------+
; CKEout~reg0 ; 1 ;
; nRASout~reg0 ; 1 ;
; nCASout~reg0 ; 1 ;
; nRWEout~reg0 ; 1 ;
; DQML~reg0 ; 1 ;
; DQMH~reg0 ; 1 ;
; CKE ; 1 ;
; nRAS ; 1 ;
; nCAS ; 1 ;
; nRWE ; 1 ;
; Total number of inverted registers = 10 ; ;
+-----------------------------------------+---------+
+----------------------------------------------------------------------------------------------------------------------------------------------------+
@ -254,12 +255,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+
; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |RAM2E|S[0] ;
; 4:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |RAM2E|CS[0] ;
; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |RAM2E|S[2] ;
; 4:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |RAM2E|CS[1] ;
; 4:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |RAM2E|RAM2E_UFM:ram2e_ufm|RWMask[5] ;
; 16:1 ; 2 bits ; 20 LEs ; 2 LEs ; 18 LEs ; Yes ; |RAM2E|BA[1]~reg0 ;
; 17:1 ; 4 bits ; 44 LEs ; 8 LEs ; 36 LEs ; Yes ; |RAM2E|RA[4] ;
; 19:1 ; 2 bits ; 24 LEs ; 4 LEs ; 20 LEs ; Yes ; |RAM2E|RA[2] ;
; 16:1 ; 2 bits ; 20 LEs ; 2 LEs ; 18 LEs ; Yes ; |RAM2E|BA[0]~reg0 ;
; 17:1 ; 4 bits ; 44 LEs ; 8 LEs ; 36 LEs ; Yes ; |RAM2E|RA[6] ;
; 19:1 ; 2 bits ; 24 LEs ; 4 LEs ; 20 LEs ; Yes ; |RAM2E|RA[1] ;
; 10:1 ; 2 bits ; 12 LEs ; 4 LEs ; 8 LEs ; Yes ; |RAM2E|DQML~reg0 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+
@ -280,50 +281,50 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Info: Processing started: Thu Dec 28 23:09:11 2023
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Info: Processing started: Thu Feb 15 04:15:26 2024
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E-MAXII -c RAM2E
Info (20032): Parallel compilation is enabled and will use up to 4 processors
Info (12021): Found 1 design units, including 1 entities, in source file /repos/ram2e/cpld/ram2e.v
Info (12023): Found entity 1: RAM2E File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file /repos/ram2e/cpld/ufm-max.v
Info (12023): Found entity 1: RAM2E_UFM File: Y:/Repos/RAM2E/CPLD/UFM-MAX.v Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file //mac/home/repos/ram2e/cpld/ram2e.v
Info (12023): Found entity 1: RAM2E File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file //mac/home/repos/ram2e/cpld/ufm-max.v
Info (12023): Found entity 1: RAM2E_UFM File: //Mac/Home/Repos/RAM2E/CPLD/UFM-MAX.v Line: 1
Info (12021): Found 2 design units, including 2 entities, in source file ufm.v
Info (12023): Found entity 1: UFM_altufm_none_lbr File: Y:/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 47
Info (12023): Found entity 2: UFM File: Y:/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 166
Info (12023): Found entity 1: UFM_altufm_none_lbr File: //Mac/Home/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 47
Info (12023): Found entity 2: UFM File: //Mac/Home/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 166
Info (12127): Elaborating entity "RAM2E" for the top level hierarchy
Info (12128): Elaborating entity "RAM2E_UFM" for hierarchy "RAM2E_UFM:ram2e_ufm" File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 112
Info (12128): Elaborating entity "UFM" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst" File: Y:/Repos/RAM2E/CPLD/UFM-MAX.v Line: 79
Info (12128): Elaborating entity "UFM_altufm_none_lbr" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component" File: Y:/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 217
Info (12128): Elaborating entity "RAM2E_UFM" for hierarchy "RAM2E_UFM:ram2e_ufm" File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 136
Info (12128): Elaborating entity "UFM" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst" File: //Mac/Home/Repos/RAM2E/CPLD/UFM-MAX.v Line: 77
Info (12128): Elaborating entity "UFM_altufm_none_lbr" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component" File: //Mac/Home/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 217
Warning (13024): Output pins are stuck at VCC or GND
Warning (13410): Pin "nCSout" is stuck at GND File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 78
Warning (14632): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
Warning (14632): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
Warning (14632): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
Warning (14632): Output pin "Dout[3]" driven by bidirectional pin "RD[3]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
Warning (14632): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
Warning (14632): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
Warning (14632): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
Warning (14632): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
Warning (13410): Pin "nCSout" is stuck at GND File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 75
Warning (14632): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (14632): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (14632): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (14632): Output pin "Dout[3]" driven by bidirectional pin "RD[3]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (14632): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (14632): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (14632): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (14632): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (21074): Design contains 1 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "nWE80" File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 11
Info (21057): Implemented 315 device resources after synthesis - the final resource count might be different
Warning (15610): No output dependent on input pin "nWE80" File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 11
Info (21057): Implemented 323 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 22 input pins
Info (21059): Implemented 40 output pins
Info (21060): Implemented 8 bidirectional pins
Info (21061): Implemented 244 logic cells
Info (21061): Implemented 252 logic cells
Info (21070): Implemented 1 User Flash Memory blocks
Info (144001): Generated suppressed messages file Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.map.smsg
Info (144001): Generated suppressed messages file /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.map.smsg
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings
Info: Peak virtual memory: 13113 megabytes
Info: Processing ended: Thu Dec 28 23:09:39 2023
Info: Elapsed time: 00:00:28
Info: Total CPU time (on all processors): 00:00:42
Info: Peak virtual memory: 13146 megabytes
Info: Processing ended: Thu Feb 15 04:16:13 2024
Info: Elapsed time: 00:00:47
Info: Total CPU time (on all processors): 00:00:47
+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.map.smsg.
The suppressed messages can be found in /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.map.smsg.

6
CPLD/MAXII/output_files/RAM2E.map.smsg
View File

@ -1,3 +1,3 @@
Warning (10273): Verilog HDL warning at RAM2E.v(74): extended using "x" or "z" File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 74
Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: Y:/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 73
Warning (10463): Verilog HDL Declaration warning at UFM.v(189): "program" is SystemVerilog-2005 keyword File: Y:/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 189
Warning (10273): Verilog HDL warning at RAM2E.v(72): extended using "x" or "z" File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 72
Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: //Mac/Home/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 73
Warning (10463): Verilog HDL Declaration warning at UFM.v(189): "program" is SystemVerilog-2005 keyword File: //Mac/Home/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 189

6
CPLD/MAXII/output_files/RAM2E.map.summary
View File

@ -1,9 +1,9 @@
Analysis & Synthesis Status : Successful - Thu Dec 28 23:09:39 2023
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Analysis & Synthesis Status : Successful - Thu Feb 15 04:16:13 2024
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Revision Name : RAM2E
Top-level Entity Name : RAM2E
Family : MAX II
Total logic elements : 244
Total logic elements : 252
Total pins : 70
Total virtual pins : 0
UFM blocks : 1 / 1 ( 100 % )

2
CPLD/MAXII/output_files/RAM2E.pin
View File

@ -58,7 +58,7 @@
-- Pin directions (input, output or bidir) are based on device operating in user mode.
---------------------------------------------------------------------------------
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
CHIP "RAM2E" ASSIGNED TO AN: EPM240T100C5
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment

BIN
CPLD/MAXII/output_files/RAM2E.pof
View File

Binary file not shown.

546
CPLD/MAXII/output_files/RAM2E.sta.rpt
View File

@ -1,6 +1,6 @@
Timing Analyzer report for RAM2E
Thu Dec 28 23:09:50 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Thu Feb 15 04:16:31 2024
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
---------------------
@ -17,8 +17,8 @@ Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Editio
9. Recovery Summary
10. Removal Summary
11. Minimum Pulse Width Summary
12. Setup: 'ram2e_ufm|DRCLK|regout'
13. Setup: 'ram2e_ufm|ARCLK|regout'
12. Setup: 'ram2e_ufm|ARCLK|regout'
13. Setup: 'ram2e_ufm|DRCLK|regout'
14. Setup: 'C14M'
15. Hold: 'ram2e_ufm|DRCLK|regout'
16. Hold: 'ram2e_ufm|ARCLK|regout'
@ -57,18 +57,18 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+-----------------------+---------------------------------------------------------------------+
; Quartus Prime Version ; Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
; Timing Analyzer ; Legacy Timing Analyzer ;
; Revision Name ; RAM2E ;
; Device Family ; MAX II ;
; Device Name ; EPM240T100C5 ;
; Timing Models ; Final ;
; Delay Model ; Slow Model ;
; Rise/Fall Delays ; Unavailable ;
+-----------------------+---------------------------------------------------------------------+
+-----------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+-----------------------+-----------------------------------------------------+
; Quartus Prime Version ; Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
; Timing Analyzer ; Legacy Timing Analyzer ;
; Revision Name ; RAM2E ;
; Device Family ; MAX II ;
; Device Name ; EPM240T100C5 ;
; Timing Models ; Final ;
; Delay Model ; Slow Model ;
; Rise/Fall Delays ; Unavailable ;
+-----------------------+-----------------------------------------------------+
+------------------------------------------+
@ -80,10 +80,11 @@ https://fpgasoftware.intel.com/eula.
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 1 ;
; Maximum used ; 2 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processor 2 ; 0.0% ;
+----------------------------+-------------+
@ -92,8 +93,8 @@ https://fpgasoftware.intel.com/eula.
+------------------+--------+--------------------------+
; SDC File Path ; Status ; Read at ;
+------------------+--------+--------------------------+
; ../RAM2E.sdc ; OK ; Thu Dec 28 23:09:50 2023 ;
; ../RAM2E-MAX.sdc ; OK ; Thu Dec 28 23:09:50 2023 ;
; ../RAM2E.sdc ; OK ; Thu Feb 15 04:16:31 2024 ;
; ../RAM2E-MAX.sdc ; OK ; Thu Feb 15 04:16:31 2024 ;
+------------------+--------+--------------------------+
@ -115,7 +116,7 @@ https://fpgasoftware.intel.com/eula.
+-----------+-----------------+------------------------+------+
; 10.0 MHz ; 10.0 MHz ; ram2e_ufm|ARCLK|regout ; ;
; 10.0 MHz ; 10.0 MHz ; ram2e_ufm|DRCLK|regout ; ;
; 70.81 MHz ; 70.81 MHz ; C14M ; ;
; 68.17 MHz ; 68.17 MHz ; C14M ; ;
+-----------+-----------------+------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
@ -125,9 +126,9 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+------------------------+---------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------+---------+---------------+
; ram2e_ufm|DRCLK|regout ; -23.738 ; -23.738 ;
; ram2e_ufm|ARCLK|regout ; -23.720 ; -23.720 ;
; C14M ; -9.644 ; -106.641 ;
; ram2e_ufm|ARCLK|regout ; -23.723 ; -23.723 ;
; ram2e_ufm|DRCLK|regout ; -23.713 ; -23.713 ;
; C14M ; -10.120 ; -109.885 ;
+------------------------+---------+---------------+
@ -136,9 +137,9 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+------------------------+---------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------+---------+---------------+
; ram2e_ufm|DRCLK|regout ; -16.287 ; -16.287 ;
; ram2e_ufm|ARCLK|regout ; -16.279 ; -16.279 ;
; C14M ; 1.421 ; 0.000 ;
; ram2e_ufm|DRCLK|regout ; -16.306 ; -16.306 ;
; ram2e_ufm|ARCLK|regout ; -16.276 ; -16.276 ;
; C14M ; 1.415 ; 0.000 ;
+------------------------+---------+---------------+
@ -165,133 +166,133 @@ No paths to report.
+------------------------+--------+---------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup: 'ram2e_ufm|DRCLK|regout' ;
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
; -23.738 ; RAM2E_UFM:ram2e_ufm|DRDIn ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.001 ; -1.671 ; 2.068 ;
; -23.712 ; RAM2E_UFM:ram2e_ufm|DRShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.001 ; -1.671 ; 2.042 ;
; 100.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; 200.000 ; 0.000 ; 80.000 ;
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup: 'ram2e_ufm|ARCLK|regout' ;
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
; -23.720 ; RAM2E_UFM:ram2e_ufm|ARShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M ; ram2e_ufm|ARCLK|regout ; 0.001 ; -1.663 ; 2.058 ;
; -23.723 ; RAM2E_UFM:ram2e_ufm|ARShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M ; ram2e_ufm|ARCLK|regout ; 0.001 ; -2.195 ; 1.529 ;
; 100.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 200.000 ; 0.000 ; 80.000 ;
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup: 'C14M' ;
+--------+-----------------------------------------------------------------------------------------------------------------+---------------------------------+------------------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------------------+---------------------------------+------------------------+-------------+--------------+------------+------------+
; -9.644 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.671 ; 10.983 ;
; -9.644 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.671 ; 10.983 ;
; -9.157 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.671 ; 10.496 ;
; -9.157 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.671 ; 10.496 ;
; -9.157 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.671 ; 10.496 ;
; -9.157 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.671 ; 10.496 ;
; -9.157 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.671 ; 10.496 ;
; -9.157 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.671 ; 10.496 ;
; -8.710 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.671 ; 10.049 ;
; -8.708 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.671 ; 10.047 ;
; -8.612 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|LEDEN ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.671 ; 9.951 ;
; -6.381 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 1.671 ; 7.720 ;
; 31.279 ; RA[8] ; RAout[8]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 3.308 ;
; 31.326 ; RA[11] ; RAout[11]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 3.261 ;
; 31.442 ; RA[9] ; RAout[9]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 3.145 ;
; 31.464 ; RA[0] ; RAout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 3.123 ;
; 31.631 ; RA[10] ; RAout[10]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 2.956 ;
; 31.767 ; CKE ; CKEout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 2.820 ;
; 31.783 ; RA[5] ; RAout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 2.804 ;
; 31.887 ; RA[3] ; RAout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 2.700 ;
; 32.525 ; nCAS ; nCASout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 2.062 ;
; 32.582 ; nRWE ; nRWEout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 2.005 ;
; 32.583 ; RA[1] ; RAout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 2.004 ;
; 32.593 ; nRAS ; nRASout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 1.994 ;
; 32.721 ; RA[4] ; RAout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 1.866 ;
; 32.969 ; RA[2] ; RAout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 1.618 ;
; 32.978 ; RA[7] ; RAout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 1.609 ;
; 32.989 ; RA[6] ; RAout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 1.598 ;
; 55.719 ; FS[4] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.789 ;
; 55.719 ; FS[4] ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.789 ;
; 56.206 ; FS[4] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.302 ;
; 56.206 ; FS[4] ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.302 ;
; 56.206 ; FS[4] ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.302 ;
; 56.206 ; FS[4] ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.302 ;
; 56.206 ; FS[4] ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.302 ;
; 56.206 ; FS[4] ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.302 ;
; 56.603 ; FS[4] ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; C14M ; C14M ; 69.841 ; 0.000 ; 12.905 ;
; 56.844 ; FS[4] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.664 ;
; 56.844 ; FS[4] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.664 ;
; 56.844 ; FS[4] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.664 ;
; 56.844 ; FS[4] ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.664 ;
; 56.844 ; FS[4] ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.664 ;
; 56.844 ; FS[4] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.664 ;
; 56.844 ; FS[4] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.664 ;
; 56.844 ; FS[4] ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.664 ;
; 56.915 ; FS[4] ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; C14M ; C14M ; 69.841 ; 0.000 ; 12.593 ;
; 57.079 ; FS[1] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.429 ;
; 57.079 ; FS[1] ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.429 ;
; 57.323 ; FS[4] ; RAM2E_UFM:ram2e_ufm|LEDEN ; C14M ; C14M ; 69.841 ; 0.000 ; 12.185 ;
; 57.476 ; S[0] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.032 ;
; 57.476 ; S[0] ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.032 ;
; 57.566 ; FS[1] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.942 ;
; 57.566 ; FS[1] ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.942 ;
; 57.566 ; FS[1] ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.942 ;
; 57.566 ; FS[1] ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.942 ;
; 57.566 ; FS[1] ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.942 ;
; 57.566 ; FS[1] ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.942 ;
; 57.651 ; S[0] ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; C14M ; C14M ; 69.841 ; 0.000 ; 11.857 ;
; 57.772 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.736 ;
; 57.772 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.736 ;
; 57.960 ; FS[4] ; nCAS ; C14M ; C14M ; 69.841 ; 0.000 ; 11.548 ;
; 57.963 ; S[0] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.545 ;
; 57.963 ; S[0] ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.545 ;
; 57.963 ; S[0] ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.545 ;
; 57.963 ; S[0] ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.545 ;
; 57.963 ; S[0] ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.545 ;
; 57.963 ; S[0] ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.545 ;
; 57.963 ; FS[1] ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; C14M ; C14M ; 69.841 ; 0.000 ; 11.545 ;
; 57.963 ; S[0] ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; C14M ; C14M ; 69.841 ; 0.000 ; 11.545 ;
; 58.006 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.502 ;
; 58.006 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.502 ;
; 58.006 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.502 ;
; 58.006 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.502 ;
; 58.006 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.502 ;
; 58.006 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.502 ;
; 58.006 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.502 ;
; 58.006 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.502 ;
; 58.030 ; FS[3] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.478 ;
; 58.030 ; FS[3] ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.478 ;
; 58.039 ; CS[1] ; CS[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.469 ;
; 58.040 ; CS[1] ; CS[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.468 ;
; 58.040 ; CS[1] ; CS[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.468 ;
; 58.068 ; FS[4] ; nRWE ; C14M ; C14M ; 69.841 ; 0.000 ; 11.440 ;
; 58.143 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.365 ;
; 58.143 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.365 ;
; 58.143 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.365 ;
; 58.143 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.365 ;
; 58.143 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.365 ;
; 58.143 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.365 ;
; 58.143 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.365 ;
; 58.143 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.365 ;
; 58.204 ; FS[1] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.304 ;
; 58.204 ; FS[1] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.304 ;
; 58.204 ; FS[1] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.304 ;
; 58.204 ; FS[1] ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.304 ;
; 58.204 ; FS[1] ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.304 ;
; 58.204 ; FS[1] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.304 ;
; 58.204 ; FS[1] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.304 ;
; 58.204 ; FS[1] ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.304 ;
; 58.230 ; S[0] ; S[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 11.278 ;
+--------+-----------------------------------------------------------------------------------------------------------------+---------------------------------+------------------------+-------------+--------------+------------+------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup: 'ram2e_ufm|DRCLK|regout' ;
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
; -23.713 ; RAM2E_UFM:ram2e_ufm|DRDIn ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.001 ; -2.165 ; 1.549 ;
; -23.693 ; RAM2E_UFM:ram2e_ufm|DRShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.001 ; -2.165 ; 1.529 ;
; 100.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; 200.000 ; 0.000 ; 80.000 ;
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup: 'C14M' ;
+---------+-----------------------------------------------------------------------------------------------------------------+---------------------------------+------------------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+-----------------------------------------------------------------------------------------------------------------+---------------------------------+------------------------+-------------+--------------+------------+------------+
; -10.120 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 11.953 ;
; -10.120 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 11.953 ;
; -9.711 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 11.544 ;
; -9.711 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 11.544 ;
; -9.711 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 11.544 ;
; -9.711 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 11.544 ;
; -9.711 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 11.544 ;
; -9.711 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 11.544 ;
; -9.027 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|LEDEN ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 10.860 ;
; -7.930 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 9.763 ;
; -7.925 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 9.758 ;
; -6.497 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 8.330 ;
; 27.586 ; S[1] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.001 ;
; 27.586 ; S[1] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.001 ;
; 27.729 ; S[2] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.858 ;
; 27.729 ; S[2] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.858 ;
; 27.800 ; S[0] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.787 ;
; 27.800 ; S[0] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.787 ;
; 28.220 ; S[3] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.367 ;
; 28.220 ; S[3] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.367 ;
; 28.226 ; S[1] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.361 ;
; 28.226 ; S[1] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.361 ;
; 28.226 ; S[1] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.361 ;
; 28.369 ; S[2] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.218 ;
; 28.369 ; S[2] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.218 ;
; 28.369 ; S[2] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.218 ;
; 28.440 ; S[0] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.147 ;
; 28.440 ; S[0] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.147 ;
; 28.440 ; S[0] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.147 ;
; 28.860 ; S[3] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.727 ;
; 28.860 ; S[3] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.727 ;
; 28.860 ; S[3] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.727 ;
; 28.910 ; S[1] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.677 ;
; 28.910 ; S[1] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.677 ;
; 28.910 ; S[1] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.677 ;
; 29.053 ; S[2] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.534 ;
; 29.053 ; S[2] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.534 ;
; 29.053 ; S[2] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.534 ;
; 29.124 ; S[0] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.463 ;
; 29.124 ; S[0] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.463 ;
; 29.124 ; S[0] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.463 ;
; 29.544 ; S[3] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.043 ;
; 29.544 ; S[3] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.043 ;
; 29.544 ; S[3] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.043 ;
; 29.726 ; S[1] ; RAT ; C14M ; C14M ; 34.920 ; 0.000 ; 4.861 ;
; 30.004 ; S[3] ; RAT ; C14M ; C14M ; 34.920 ; 0.000 ; 4.583 ;
; 30.351 ; S[2] ; RAT ; C14M ; C14M ; 34.920 ; 0.000 ; 4.236 ;
; 30.681 ; S[0] ; RAT ; C14M ; C14M ; 34.920 ; 0.000 ; 3.906 ;
; 31.064 ; nRWE ; nRWEout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 3.523 ;
; 31.134 ; RA[10] ; RAr[10] ; C14M ; C14M ; 34.920 ; 0.000 ; 3.453 ;
; 31.373 ; RA[9] ; RAr[9] ; C14M ; C14M ; 34.920 ; 0.000 ; 3.214 ;
; 31.459 ; RA[8] ; RAr[8] ; C14M ; C14M ; 34.920 ; 0.000 ; 3.128 ;
; 31.701 ; CKE ; CKEout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 2.886 ;
; 31.732 ; S[3] ; VOE ; C14M ; C14M ; 34.920 ; 0.000 ; 2.855 ;
; 31.854 ; RA[11] ; RAr[11] ; C14M ; C14M ; 34.920 ; 0.000 ; 2.733 ;
; 31.909 ; S[2] ; VOE ; C14M ; C14M ; 34.920 ; 0.000 ; 2.678 ;
; 31.932 ; nCAS ; nCASout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 2.655 ;
; 31.945 ; nRAS ; nRASout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 2.642 ;
; 32.013 ; S[0] ; VOE ; C14M ; C14M ; 34.920 ; 0.000 ; 2.574 ;
; 32.533 ; RA[3] ; RAr[3] ; C14M ; C14M ; 34.920 ; 0.000 ; 2.054 ;
; 32.562 ; RA[6] ; RAr[6] ; C14M ; C14M ; 34.920 ; 0.000 ; 2.025 ;
; 32.597 ; S[1] ; VOE ; C14M ; C14M ; 34.920 ; 0.000 ; 1.990 ;
; 32.955 ; RA[0] ; RAr[0] ; C14M ; C14M ; 34.920 ; 0.000 ; 1.632 ;
; 32.974 ; RA[4] ; RAr[4] ; C14M ; C14M ; 34.920 ; 0.000 ; 1.613 ;
; 32.977 ; RA[7] ; RAr[7] ; C14M ; C14M ; 34.920 ; 0.000 ; 1.610 ;
; 32.979 ; RA[5] ; RAr[5] ; C14M ; C14M ; 34.920 ; 0.000 ; 1.608 ;
; 32.980 ; RA[1] ; RAr[1] ; C14M ; C14M ; 34.920 ; 0.000 ; 1.607 ;
; 32.981 ; RA[2] ; RAr[2] ; C14M ; C14M ; 34.920 ; 0.000 ; 1.606 ;
; 55.823 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.685 ;
; 55.823 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.685 ;
; 56.232 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.276 ;
; 56.232 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.276 ;
; 56.232 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.276 ;
; 56.232 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.276 ;
; 56.232 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.276 ;
; 56.232 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.276 ;
; 56.355 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; C14M ; C14M ; 69.841 ; 0.000 ; 13.153 ;
; 56.360 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; C14M ; C14M ; 69.841 ; 0.000 ; 13.148 ;
; 56.403 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.105 ;
; 56.403 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.105 ;
; 56.476 ; FS[15] ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; C14M ; C14M ; 69.841 ; 0.000 ; 13.032 ;
; 56.481 ; FS[15] ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; C14M ; C14M ; 69.841 ; 0.000 ; 13.027 ;
; 56.524 ; FS[15] ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.984 ;
; 56.524 ; FS[15] ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.984 ;
; 56.812 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.696 ;
; 56.812 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.696 ;
; 56.812 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.696 ;
; 56.812 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.696 ;
; 56.812 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.696 ;
; 56.812 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.696 ;
; 56.866 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.642 ;
; 56.866 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.642 ;
; 56.866 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.642 ;
; 56.866 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.642 ;
; 56.866 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.642 ;
; 56.866 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.642 ;
; 56.916 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|LEDEN ; C14M ; C14M ; 69.841 ; 0.000 ; 12.592 ;
; 56.933 ; FS[15] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.575 ;
; 56.933 ; FS[15] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.575 ;
; 56.933 ; FS[15] ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.575 ;
+---------+-----------------------------------------------------------------------------------------------------------------+---------------------------------+------------------------+-------------+--------------+------------+------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
@ -299,8 +300,8 @@ No paths to report.
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
; -16.287 ; RAM2E_UFM:ram2e_ufm|DRShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.000 ; -1.671 ; 2.042 ;
; -16.261 ; RAM2E_UFM:ram2e_ufm|DRDIn ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.000 ; -1.671 ; 2.068 ;
; -16.306 ; RAM2E_UFM:ram2e_ufm|DRShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.000 ; -2.165 ; 1.529 ;
; -16.286 ; RAM2E_UFM:ram2e_ufm|DRDIn ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.000 ; -2.165 ; 1.549 ;
; 60.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; 0.000 ; 0.000 ; 80.000 ;
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
@ -310,7 +311,7 @@ No paths to report.
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
; -16.279 ; RAM2E_UFM:ram2e_ufm|ARShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M ; ram2e_ufm|ARCLK|regout ; 0.000 ; -1.663 ; 2.058 ;
; -16.276 ; RAM2E_UFM:ram2e_ufm|ARShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M ; ram2e_ufm|ARCLK|regout ; 0.000 ; -2.195 ; 1.529 ;
; 60.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 0.000 ; 0.000 ; 80.000 ;
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
@ -320,106 +321,106 @@ No paths to report.
+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
; 1.421 ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.642 ;
; 1.421 ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.642 ;
; 1.445 ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.666 ;
; 1.451 ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.672 ;
; 1.461 ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.682 ;
; 1.639 ; RWSel ; RWSel ; C14M ; C14M ; 0.000 ; 0.000 ; 1.860 ;
; 1.684 ; FS[0] ; FS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.905 ;
; 1.687 ; CS[1] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.908 ;
; 1.688 ; CS[1] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.909 ;
; 1.696 ; CmdTout[0] ; CmdTout[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.917 ;
; 1.702 ; CmdTout[0] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.923 ;
; 1.706 ; CmdTout[0] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.927 ;
; 1.716 ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; C14M ; C14M ; 0.000 ; 0.000 ; 1.937 ;
; 1.818 ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.039 ;
; 1.905 ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; RWBank[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.126 ;
; 1.928 ; RWBank[1] ; RA[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.149 ;
; 1.935 ; CS[2] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.156 ;
; 1.954 ; RC[0] ; RC[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.175 ;
; 1.961 ; RC[0] ; RC[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.182 ;
; 1.968 ; RC[0] ; RC[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.189 ;
; 1.971 ; S[3] ; S[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.192 ;
; 1.972 ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 2.193 ;
; 1.984 ; CS[0] ; CS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.205 ;
; 1.993 ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 2.214 ;
; 1.995 ; CS[0] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.216 ;
; 2.107 ; RAM2E_UFM:ram2e_ufm|LEDEN ; RAM2E_UFM:ram2e_ufm|LEDEN ; C14M ; C14M ; 0.000 ; 0.000 ; 2.328 ;
; 2.109 ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; RWBank[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.330 ;
; 2.116 ; FS[8] ; FS[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.337 ;
; 2.117 ; FS[15] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.338 ;
; 2.117 ; FS[5] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.338 ;
; 2.125 ; FS[9] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.346 ;
; 2.126 ; RAM2E_UFM:ram2e_ufm|DRDIn ; RAM2E_UFM:ram2e_ufm|DRDIn ; C14M ; C14M ; 0.000 ; 0.000 ; 2.347 ;
; 2.126 ; FS[7] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.347 ;
; 2.128 ; RWBank[7] ; RA[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.349 ;
; 2.133 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.354 ;
; 2.136 ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; C14M ; C14M ; 0.000 ; 0.000 ; 2.357 ;
; 2.143 ; CmdTout[2] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.364 ;
; 2.150 ; Ready ; Ready ; C14M ; C14M ; 0.000 ; 0.000 ; 2.371 ;
; 2.163 ; RC[1] ; RC[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.384 ;
; 2.181 ; RC[1] ; RC[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.402 ;
; 2.182 ; S[1] ; S[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.403 ;
; 2.184 ; RC[1] ; RC[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.405 ;
; 2.212 ; RA[10] ; RA[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.433 ;
; 2.230 ; FS[6] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.451 ;
; 2.232 ; FS[11] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.453 ;
; 1.415 ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.636 ;
; 1.644 ; RWSel ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.865 ;
; 1.650 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.871 ;
; 1.665 ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; RWBank[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.886 ;
; 1.684 ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; C14M ; C14M ; 0.000 ; 0.000 ; 1.905 ;
; 1.701 ; CS[1] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.922 ;
; 1.715 ; CS[1] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.936 ;
; 1.914 ; RWBank[4] ; RA[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.135 ;
; 1.916 ; RWBank[2] ; RA[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.137 ;
; 1.968 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 2.189 ;
; 1.971 ; CmdTout[0] ; CmdTout[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.192 ;
; 1.973 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 2.194 ;
; 1.973 ; CmdTout[0] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.194 ;
; 1.979 ; CmdTout[0] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.200 ;
; 2.026 ; CS[2] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.247 ;
; 2.107 ; Ready ; Ready ; C14M ; C14M ; 0.000 ; 0.000 ; 2.328 ;
; 2.107 ; FS[7] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.328 ;
; 2.125 ; RA[10] ; RA[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.346 ;
; 2.127 ; FS[15] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.348 ;
; 2.134 ; FS[8] ; FS[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.355 ;
; 2.144 ; FS[5] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.365 ;
; 2.151 ; FS[9] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.372 ;
; 2.153 ; FS[10] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.374 ;
; 2.170 ; RAM2E_UFM:ram2e_ufm|UFMProgram ; RAM2E_UFM:ram2e_ufm|UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 2.391 ;
; 2.174 ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 2.395 ;
; 2.175 ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 2.396 ;
; 2.189 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; C14M ; C14M ; 0.000 ; 0.000 ; 2.410 ;
; 2.190 ; CmdTout[1] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.411 ;
; 2.207 ; CmdTout[1] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.428 ;
; 2.214 ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; RWBank[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.435 ;
; 2.222 ; RAM2E_UFM:ram2e_ufm|LEDEN ; RAM2E_UFM:ram2e_ufm|LEDEN ; C14M ; C14M ; 0.000 ; 0.000 ; 2.443 ;
; 2.222 ; RAM2E_UFM:ram2e_ufm|DRDIn ; RAM2E_UFM:ram2e_ufm|DRDIn ; C14M ; C14M ; 0.000 ; 0.000 ; 2.443 ;
; 2.228 ; CS[0] ; CS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.449 ;
; 2.233 ; FS[11] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.454 ;
; 2.239 ; FS[13] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.460 ;
; 2.239 ; FS[14] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.460 ;
; 2.241 ; FS[1] ; FS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.462 ;
; 2.240 ; FS[1] ; FS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.461 ;
; 2.240 ; CS[0] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.461 ;
; 2.248 ; FS[4] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.469 ;
; 2.249 ; FS[2] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.470 ;
; 2.250 ; FS[12] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.471 ;
; 2.259 ; FS[3] ; FS[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.480 ;
; 2.261 ; FS[4] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.482 ;
; 2.272 ; RAM2E_UFM:ram2e_ufm|UFMProgram ; RAM2E_UFM:ram2e_ufm|UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 2.493 ;
; 2.277 ; RC[2] ; RC[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.498 ;
; 2.279 ; RC[2] ; RC[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.500 ;
; 2.282 ; RC[2] ; RC[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.503 ;
; 2.302 ; CmdTout[1] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.523 ;
; 2.305 ; S[3] ; RA[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.526 ;
; 2.310 ; CmdTout[1] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.531 ;
; 2.313 ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; RWBank[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.534 ;
; 2.316 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 2.537 ;
; 2.319 ; CS[0] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.540 ;
; 2.323 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; C14M ; C14M ; 0.000 ; 0.000 ; 2.544 ;
; 2.332 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 2.553 ;
; 2.347 ; PHI1r ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.568 ;
; 2.372 ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; C14M ; C14M ; 0.000 ; 0.000 ; 2.593 ;
; 2.446 ; RWSel ; CmdTout[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.667 ;
; 2.455 ; RWSel ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.676 ;
; 2.457 ; S[3] ; CKE ; C14M ; C14M ; 0.000 ; 0.000 ; 2.678 ;
; 2.459 ; RWSel ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.680 ;
; 2.531 ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.752 ;
; 2.542 ; S[2] ; S[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.763 ;
; 2.544 ; S[2] ; DOEEN ; C14M ; C14M ; 0.000 ; 0.000 ; 2.765 ;
; 2.563 ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.784 ;
; 2.606 ; RAM2E_UFM:ram2e_ufm|UFMErase ; RAM2E_UFM:ram2e_ufm|UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 2.827 ;
; 2.610 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 2.831 ;
; 2.653 ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.874 ;
; 2.655 ; S[0] ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.876 ;
; 2.656 ; FS[10] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.877 ;
; 2.657 ; S[0] ; VOEEN ; C14M ; C14M ; 0.000 ; 0.000 ; 2.878 ;
; 2.660 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.881 ;
; 2.678 ; S[1] ; DOEEN ; C14M ; C14M ; 0.000 ; 0.000 ; 2.899 ;
; 2.719 ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.940 ;
; 2.750 ; S[0] ; RA[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.971 ;
; 2.764 ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; RAM2E_UFM:ram2e_ufm|UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 2.985 ;
; 2.773 ; S[1] ; S[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.994 ;
; 2.785 ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; RWBank[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.006 ;
; 2.794 ; S[0] ; RA[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.015 ;
; 2.815 ; FS[4] ; RA[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.036 ;
; 2.830 ; S[3] ; RA[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.051 ;
; 2.850 ; FS[1] ; RA[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.071 ;
; 2.851 ; RWBank[5] ; BA[0]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.072 ;
; 2.902 ; S[2] ; nRWE ; C14M ; C14M ; 0.000 ; 0.000 ; 3.123 ;
; 2.911 ; S[2] ; nCAS ; C14M ; C14M ; 0.000 ; 0.000 ; 3.132 ;
; 2.929 ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; RWBank[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.150 ;
; 2.933 ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; RAM2E_UFM:ram2e_ufm|UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 3.154 ;
; 2.935 ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; RWBank[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.156 ;
; 2.948 ; FS[8] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.169 ;
; 2.949 ; FS[5] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.170 ;
; 2.957 ; FS[9] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.178 ;
; 2.255 ; CS[0] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.476 ;
; 2.259 ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; C14M ; C14M ; 0.000 ; 0.000 ; 2.480 ;
; 2.262 ; FS[6] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.483 ;
; 2.271 ; CmdTout[2] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.492 ;
; 2.273 ; FS[3] ; FS[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.494 ;
; 2.286 ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; C14M ; C14M ; 0.000 ; 0.000 ; 2.507 ;
; 2.345 ; S[0] ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.566 ;
; 2.346 ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.567 ;
; 2.362 ; S[1] ; RDOE ; C14M ; C14M ; 0.000 ; 0.000 ; 2.583 ;
; 2.417 ; FS[0] ; FS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.638 ;
; 2.455 ; RWBank[1] ; RA[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.676 ;
; 2.486 ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.707 ;
; 2.528 ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.749 ;
; 2.544 ; RWSel ; RAM2E_UFM:ram2e_ufm|DRCLKPulse ; C14M ; C14M ; 0.000 ; 0.000 ; 2.765 ;
; 2.551 ; PHI1r ; S[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.772 ;
; 2.552 ; PHI1r ; S[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.773 ;
; 2.553 ; PHI1r ; S[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.774 ;
; 2.555 ; PHI1r ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.776 ;
; 2.621 ; RAM2E_UFM:ram2e_ufm|UFMErase ; RAM2E_UFM:ram2e_ufm|UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 2.842 ;
; 2.633 ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.854 ;
; 2.722 ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; RWBank[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.943 ;
; 2.838 ; RWSel ; RWSel ; C14M ; C14M ; 0.000 ; 0.000 ; 3.059 ;
; 2.839 ; RWSel ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.060 ;
; 2.842 ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.063 ;
; 2.843 ; RWSel ; CmdTout[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.064 ;
; 2.855 ; RWBank[6] ; BA[1]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.076 ;
; 2.860 ; RWBank[5] ; BA[0]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.081 ;
; 2.921 ; RAM2E_UFM:ram2e_ufm|UFMErase ; RAM2E_UFM:ram2e_ufm|UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 3.142 ;
; 2.938 ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; RWBank[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.159 ;
; 2.957 ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; RWBank[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.178 ;
; 2.966 ; FS[8] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.187 ;
; 2.976 ; FS[5] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.197 ;
; 2.983 ; FS[9] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.204 ;
; 2.985 ; FS[10] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.206 ;
; 2.994 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 3.215 ;
; 3.005 ; S[1] ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.226 ;
; 3.014 ; S[1] ; S[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.235 ;
; 3.015 ; S[1] ; S[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.236 ;
; 3.016 ; S[1] ; S[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.237 ;
; 3.077 ; FS[8] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.298 ;
; 3.087 ; FS[5] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.308 ;
; 3.094 ; FS[9] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.315 ;
; 3.096 ; FS[10] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.317 ;
; 3.096 ; FS[11] ; RA[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.317 ;
; 3.128 ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.349 ;
; 3.129 ; S[3] ; DQMH~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.350 ;
; 3.132 ; FS[0] ; FS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.353 ;
; 3.134 ; S[3] ; DQML~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.355 ;
; 3.155 ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; RWBank[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.376 ;
; 3.172 ; RWBank[0] ; DQML~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.393 ;
; 3.173 ; FS[11] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.394 ;
; 3.174 ; RWBank[0] ; DQMH~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.395 ;
; 3.179 ; FS[14] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.400 ;
; 3.179 ; FS[13] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.400 ;
; 3.180 ; FS[1] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.401 ;
; 3.188 ; FS[4] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.409 ;
; 3.188 ; FS[8] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.409 ;
; 3.202 ; FS[6] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.423 ;
; 3.205 ; FS[9] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.426 ;
+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
@ -428,7 +429,7 @@ No paths to report.
+------------------------+------------------------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------------------+------------------------+----------+----------+----------+----------+
; C14M ; C14M ; 1625 ; 0 ; 16 ; 0 ;
; C14M ; C14M ; 1539 ; 0 ; 56 ; 0 ;
; ram2e_ufm|DRCLK|regout ; C14M ; 13 ; 0 ; 0 ; 0 ;
; C14M ; ram2e_ufm|ARCLK|regout ; 1 ; 0 ; 0 ; 0 ;
; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 1 ; 0 ; 0 ; 0 ;
@ -443,7 +444,7 @@ Entries labeled "false path" only account for clock-to-clock false paths and not
+------------------------+------------------------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------------------+------------------------+----------+----------+----------+----------+
; C14M ; C14M ; 1625 ; 0 ; 16 ; 0 ;
; C14M ; C14M ; 1539 ; 0 ; 56 ; 0 ;
; ram2e_ufm|DRCLK|regout ; C14M ; 13 ; 0 ; 0 ; 0 ;
; C14M ; ram2e_ufm|ARCLK|regout ; 1 ; 0 ; 0 ; 0 ;
; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 1 ; 0 ; 0 ; 0 ;
@ -471,23 +472,24 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
; Property ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 1 ; 1 ;
; Unconstrained Input Ports ; 28 ; 28 ;
; Unconstrained Input Port Paths ; 176 ; 176 ;
; Unconstrained Input Port Paths ; 169 ; 169 ;
; Unconstrained Output Ports ; 47 ; 47 ;
; Unconstrained Output Port Paths ; 76 ; 76 ;
; Unconstrained Output Port Paths ; 83 ; 83 ;
+---------------------------------+-------+------+
+----------------------------------------------------------------------+
; Clock Status Summary ;
+------------------------+------------------------+------+-------------+
; Target ; Clock ; Type ; Status ;
+------------------------+------------------------+------+-------------+
; C14M ; C14M ; Base ; Constrained ;
; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; Base ; Constrained ;
; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; Base ; Constrained ;
+------------------------+------------------------+------+-------------+
+------------------------------------------------------------------------+
; Clock Status Summary ;
+------------------------+------------------------+------+---------------+
; Target ; Clock ; Type ; Status ;
+------------------------+------------------------+------+---------------+
; C14M ; C14M ; Base ; Constrained ;
; PHI1 ; ; Base ; Unconstrained ;
; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; Base ; Constrained ;
; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; Base ; Constrained ;
+------------------------+------------------------+------+---------------+
+---------------------------------------------------------------------------------------------------+
@ -677,8 +679,8 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
+--------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Timing Analyzer
Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Info: Processing started: Thu Dec 28 23:09:48 2023
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Info: Processing started: Thu Feb 15 04:16:29 2024
Info: Command: quartus_sta RAM2E-MAXII -c RAM2E
Info: qsta_default_script.tcl version: #1
Info (20032): Parallel compilation is enabled and will use up to 4 processors
@ -688,23 +690,25 @@ Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332104): Reading SDC File: '../RAM2E.sdc'
Info (332104): Reading SDC File: '../RAM2E-MAX.sdc'
Warning (332060): Node: PHI1 was determined to be a clock but was found without an associated clock assignment.
Info (13166): Register RefReq is being clocked by PHI1
Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Can't run Report Timing Closure Recommendations. The current device family is not supported.
Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ram2e_ufm|ARCLK|regout are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ram2e_ufm|DRCLK|regout are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
Critical Warning (332148): Timing requirements not met
Info (332146): Worst-case setup slack is -23.738
Info (332146): Worst-case setup slack is -23.723
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -23.738 -23.738 ram2e_ufm|DRCLK|regout
Info (332119): -23.720 -23.720 ram2e_ufm|ARCLK|regout
Info (332119): -9.644 -106.641 C14M
Info (332146): Worst-case hold slack is -16.287
Info (332119): -23.723 -23.723 ram2e_ufm|ARCLK|regout
Info (332119): -23.713 -23.713 ram2e_ufm|DRCLK|regout
Info (332119): -10.120 -109.885 C14M
Info (332146): Worst-case hold slack is -16.306
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -16.287 -16.287 ram2e_ufm|DRCLK|regout
Info (332119): -16.279 -16.279 ram2e_ufm|ARCLK|regout
Info (332119): 1.421 0.000 C14M
Info (332119): -16.306 -16.306 ram2e_ufm|DRCLK|regout
Info (332119): -16.276 -16.276 ram2e_ufm|ARCLK|regout
Info (332119): 1.415 0.000 C14M
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is 34.654
@ -714,13 +718,11 @@ Info (332146): Worst-case minimum pulse width slack is 34.654
Info (332119): 70.000 0.000 ram2e_ufm|ARCLK|regout
Info (332119): 70.000 0.000 ram2e_ufm|DRCLK|regout
Info (332001): The selected device family is not supported by the report_metastability command.
Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ram2e_ufm|ARCLK|regout are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ram2e_ufm|DRCLK|regout are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings
Info: Peak virtual memory: 13064 megabytes
Info: Processing ended: Thu Dec 28 23:09:50 2023
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 4 warnings
Info: Peak virtual memory: 13089 megabytes
Info: Processing ended: Thu Feb 15 04:16:31 2024
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:02

26
CPLD/MAXII/output_files/RAM2E.sta.summary
View File

@ -2,28 +2,28 @@
Timing Analyzer Summary
------------------------------------------------------------
Type : Setup 'ram2e_ufm|DRCLK|regout'
Slack : -23.738
TNS : -23.738
Type : Setup 'ram2e_ufm|ARCLK|regout'
Slack : -23.720
TNS : -23.720
Slack : -23.723
TNS : -23.723
Type : Setup 'ram2e_ufm|DRCLK|regout'
Slack : -23.713
TNS : -23.713
Type : Setup 'C14M'
Slack : -9.644
TNS : -106.641
Slack : -10.120
TNS : -109.885
Type : Hold 'ram2e_ufm|DRCLK|regout'
Slack : -16.287
TNS : -16.287
Slack : -16.306
TNS : -16.306
Type : Hold 'ram2e_ufm|ARCLK|regout'
Slack : -16.279
TNS : -16.279
Slack : -16.276
TNS : -16.276
Type : Hold 'C14M'
Slack : 1.421
Slack : 1.415
TNS : 0.000
Type : Minimum Pulse Width 'C14M'

25
CPLD/MAXV/RAM2E.qsf
View File

@ -42,7 +42,7 @@ set_global_assignment -name DEVICE 5M240ZT100C5
set_global_assignment -name TOP_LEVEL_ENTITY RAM2E
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 19.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "07:27:32 AUGUST 20, 2023"
set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 SP0.02std Lite Edition"
set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
@ -52,6 +52,8 @@ set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name NUM_PARALLEL_PROCESSORS 4
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS OUTPUT DRIVING GROUND"
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_location_assignment PIN_12 -to C14M
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to C14M
@ -109,7 +111,7 @@ set_location_assignment PIN_55 -to nDOE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nDOE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nDOE
set_instance_assignment -name SLOW_SLEW_RATE ON -to nDOE
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nDOE
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nDOE
set_location_assignment PIN_77 -to Dout[0]
set_location_assignment PIN_76 -to Dout[1]
@ -127,8 +129,8 @@ set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Dout
set_location_assignment PIN_50 -to nVOE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nVOE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nVOE
set_instance_assignment -name SLOW_SLEW_RATE ON -to nVOE
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nVOE
set_instance_assignment -name SLOW_SLEW_RATE OFF -to nVOE
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nVOE
set_location_assignment PIN_70 -to Vout[0]
set_location_assignment PIN_67 -to Vout[1]
@ -200,7 +202,18 @@ set_location_assignment PIN_16 -to RAout[10]
set_location_assignment PIN_7 -to RAout[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RAout
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RAout
set_instance_assignment -name SLOW_SLEW_RATE ON -to RAout
set_instance_assignment -name SLOW_SLEW_RATE OFF -to RAout[0]
set_instance_assignment -name SLOW_SLEW_RATE OFF -to RAout[1]
set_instance_assignment -name SLOW_SLEW_RATE OFF -to RAout[2]
set_instance_assignment -name SLOW_SLEW_RATE OFF -to RAout[3]
set_instance_assignment -name SLOW_SLEW_RATE OFF -to RAout[4]
set_instance_assignment -name SLOW_SLEW_RATE OFF -to RAout[5]
set_instance_assignment -name SLOW_SLEW_RATE OFF -to RAout[6]
set_instance_assignment -name SLOW_SLEW_RATE OFF -to RAout[7]
set_instance_assignment -name SLOW_SLEW_RATE ON -to RAout[8]
set_instance_assignment -name SLOW_SLEW_RATE ON -to RAout[9]
set_instance_assignment -name SLOW_SLEW_RATE ON -to RAout[10]
set_instance_assignment -name SLOW_SLEW_RATE ON -to RAout[11]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to RAout
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RAout
@ -233,10 +246,10 @@ set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to RD
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to RD
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RD
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_location_assignment PIN_88 -to LED
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LED
set_instance_assignment -name SLOW_SLEW_RATE ON -to LED
set_global_assignment -name VERILOG_FILE ../RAM2E.v
set_global_assignment -name VERILOG_FILE "../UFM-MAX.v"
set_global_assignment -name QIP_FILE UFM.qip

BIN
CPLD/MAXV/RAM2E.qws
View File

Binary file not shown.

48
CPLD/MAXV/output_files/RAM2E.asm.rpt
View File

@ -1,6 +1,6 @@
Assembler report for RAM2E
Thu Dec 28 23:09:48 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Thu Feb 15 04:16:27 2024
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
---------------------
@ -10,7 +10,7 @@ Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Editio
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pof
5. Assembler Device Options: /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pof
6. Assembler Messages
@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Thu Dec 28 23:09:48 2023 ;
; Assembler Status ; Successful - Thu Feb 15 04:16:27 2024 ;
; Revision Name ; RAM2E ;
; Top-level Entity Name ; RAM2E ;
; Family ; MAX V ;
@ -53,23 +53,23 @@ https://fpgasoftware.intel.com/eula.
+--------+---------+---------------+
+-------------------------------------------------+
; Assembler Generated Files ;
+-------------------------------------------------+
; File Name ;
+-------------------------------------------------+
; Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pof ;
+-------------------------------------------------+
+-----------------------------------------------+
; Assembler Generated Files ;
+-----------------------------------------------+
; File Name ;
+-----------------------------------------------+
; /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pof ;
+-----------------------------------------------+
+---------------------------------------------------------------------------+
; Assembler Device Options: Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pof ;
+----------------+----------------------------------------------------------+
; Option ; Setting ;
+----------------+----------------------------------------------------------+
; JTAG usercode ; 0x001658EB ;
; Checksum ; 0x00165BE3 ;
+----------------+----------------------------------------------------------+
+-------------------------------------------------------------------------+
; Assembler Device Options: /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pof ;
+----------------+--------------------------------------------------------+
; Option ; Setting ;
+----------------+--------------------------------------------------------+
; JTAG usercode ; 0x001651A7 ;
; Checksum ; 0x001654A7 ;
+----------------+--------------------------------------------------------+
+--------------------+
@ -77,15 +77,15 @@ https://fpgasoftware.intel.com/eula.
+--------------------+
Info: *******************************************************************
Info: Running Quartus Prime Assembler
Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Info: Processing started: Thu Dec 28 23:09:47 2023
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Info: Processing started: Thu Feb 15 04:16:25 2024
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2E-MAXV -c RAM2E
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 13070 megabytes
Info: Processing ended: Thu Dec 28 23:09:48 2023
Info: Elapsed time: 00:00:01
Info: Peak virtual memory: 13095 megabytes
Info: Processing ended: Thu Feb 15 04:16:27 2024
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:01

2
CPLD/MAXV/output_files/RAM2E.done
View File

@ -1 +1 @@
Thu Dec 28 23:09:52 2023
Thu Feb 15 04:16:33 2024

292
CPLD/MAXV/output_files/RAM2E.fit.rpt
View File

@ -1,6 +1,6 @@
Fitter report for RAM2E
Thu Dec 28 23:09:45 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Thu Feb 15 04:16:23 2024
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
---------------------
@ -54,21 +54,21 @@ https://fpgasoftware.intel.com/eula.
+-------------------------------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+-------------------------------------------------------------+
; Fitter Status ; Successful - Thu Dec 28 23:09:45 2023 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
; Revision Name ; RAM2E ;
; Top-level Entity Name ; RAM2E ;
; Family ; MAX V ;
; Device ; 5M240ZT100C5 ;
; Timing Models ; Final ;
; Total logic elements ; 238 / 240 ( 99 % ) ;
; Total pins ; 70 / 79 ( 89 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
+-----------------------+-------------------------------------------------------------+
+---------------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+---------------------------------------------+
; Fitter Status ; Successful - Thu Feb 15 04:16:23 2024 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
; Revision Name ; RAM2E ;
; Top-level Entity Name ; RAM2E ;
; Family ; MAX V ;
; Device ; 5M240ZT100C5 ;
; Timing Models ; Final ;
; Total logic elements ; 238 / 240 ( 99 % ) ;
; Total pins ; 70 / 79 ( 89 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
+-----------------------+---------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------+
@ -134,7 +134,7 @@ https://fpgasoftware.intel.com/eula.
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processor 2 ; 1.0% ;
; Processor 2 ; 1.1% ;
; Processors 3-4 ; 0.9% ;
+----------------------------+-------------+
@ -142,7 +142,7 @@ https://fpgasoftware.intel.com/eula.
+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pin.
The pin-out file can be found in /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pin.
+---------------------------------------------------------------------+
@ -151,26 +151,26 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pin
; Resource ; Usage ;
+---------------------------------------------+-----------------------+
; Total logic elements ; 238 / 240 ( 99 % ) ;
; -- Combinational with no register ; 115 ;
; -- Register only ; 26 ;
; -- Combinational with a register ; 97 ;
; -- Combinational with no register ; 112 ;
; -- Register only ; 19 ;
; -- Combinational with a register ; 107 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 118 ;
; -- 3 input functions ; 41 ;
; -- 2 input functions ; 48 ;
; -- 1 input functions ; 4 ;
; -- 4 input functions ; 116 ;
; -- 3 input functions ; 53 ;
; -- 2 input functions ; 46 ;
; -- 1 input functions ; 3 ;
; -- 0 input functions ; 1 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 224 ;
; -- arithmetic mode ; 14 ;
; -- qfbk mode ; 6 ;
; -- qfbk mode ; 14 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 20 ;
; -- synchronous clear/load mode ; 24 ;
; -- asynchronous clear/load mode ; 0 ;
; ; ;
; Total registers ; 123 / 240 ( 51 % ) ;
; Total registers ; 126 / 240 ( 53 % ) ;
; Total LABs ; 24 / 24 ( 100 % ) ;
; Logic elements in carry chains ; 15 ;
; Virtual pins ; 0 ;
@ -182,15 +182,15 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pin
; -- Total Fixed Point DSP Blocks ; 0 ;
; -- Total Floating Point DSP Blocks ; 0 ;
; ; ;
; Global signals ; 1 ;
; -- Global clocks ; 1 / 4 ( 25 % ) ;
; Global signals ; 2 ;
; -- Global clocks ; 2 / 4 ( 50 % ) ;
; JTAGs ; 0 / 1 ( 0 % ) ;
; Average interconnect usage (total/H/V) ; 26.9% / 27.0% / 26.7% ;
; Peak interconnect usage (total/H/V) ; 26.9% / 27.0% / 26.7% ;
; Maximum fan-out ; 123 ;
; Highest non-global fan-out ; 35 ;
; Total fan-out ; 976 ;
; Average fan-out ; 3.16 ;
; Average interconnect usage (total/H/V) ; 26.9% / 26.8% / 27.1% ;
; Peak interconnect usage (total/H/V) ; 26.9% / 26.8% / 27.1% ;
; Maximum fan-out ; 122 ;
; Highest non-global fan-out ; 34 ;
; Total fan-out ; 992 ;
; Average fan-out ; 3.21 ;
+---------------------------------------------+-----------------------+
@ -199,15 +199,15 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pin
+--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+----------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Location assigned by ; Slow Slew Rate ;
+--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+----------------+
; Ain[0] ; 56 ; 2 ; 8 ; 1 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Ain[1] ; 54 ; 2 ; 8 ; 1 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Ain[2] ; 43 ; 1 ; 6 ; 0 ; 3 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Ain[3] ; 47 ; 1 ; 6 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Ain[4] ; 44 ; 1 ; 6 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Ain[5] ; 34 ; 1 ; 3 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Ain[6] ; 39 ; 1 ; 5 ; 0 ; 3 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Ain[7] ; 53 ; 2 ; 8 ; 1 ; 3 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; C14M ; 12 ; 1 ; 1 ; 3 ; 3 ; 123 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Ain[0] ; 56 ; 2 ; 8 ; 1 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Ain[1] ; 54 ; 2 ; 8 ; 1 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Ain[2] ; 43 ; 1 ; 6 ; 0 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Ain[3] ; 47 ; 1 ; 6 ; 0 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Ain[4] ; 44 ; 1 ; 6 ; 0 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Ain[5] ; 34 ; 1 ; 3 ; 0 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Ain[6] ; 39 ; 1 ; 5 ; 0 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Ain[7] ; 53 ; 2 ; 8 ; 1 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; C14M ; 12 ; 1 ; 1 ; 3 ; 3 ; 122 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[0] ; 38 ; 1 ; 4 ; 0 ; 0 ; 15 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[1] ; 40 ; 1 ; 5 ; 0 ; 2 ; 11 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[2] ; 42 ; 1 ; 5 ; 0 ; 0 ; 13 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
@ -215,11 +215,11 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pin
; Din[4] ; 48 ; 1 ; 6 ; 0 ; 0 ; 10 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[5] ; 49 ; 1 ; 7 ; 0 ; 2 ; 9 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[6] ; 36 ; 1 ; 4 ; 0 ; 2 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[7] ; 35 ; 1 ; 3 ; 0 ; 0 ; 9 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; PHI1 ; 37 ; 1 ; 4 ; 0 ; 1 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[7] ; 35 ; 1 ; 3 ; 0 ; 0 ; 10 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; PHI1 ; 37 ; 1 ; 4 ; 0 ; 1 ; 5 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; nC07X ; 52 ; 2 ; 8 ; 1 ; 4 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; nEN80 ; 28 ; 1 ; 2 ; 0 ; 1 ; 10 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; nWE ; 51 ; 1 ; 7 ; 0 ; 0 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; nWE ; 51 ; 1 ; 7 ; 0 ; 0 ; 9 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; nWE80 ; 33 ; 1 ; 3 ; 0 ; 2 ; 0 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
+--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+----------------+
@ -243,32 +243,32 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pin
; Dout[6] ; 84 ; 2 ; 6 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; Dout[7] ; 85 ; 2 ; 5 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; LED ; 88 ; 2 ; 5 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; RAout[0] ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; RAout[0] ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RAout[10] ; 16 ; 1 ; 1 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; RAout[11] ; 7 ; 1 ; 1 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; RAout[1] ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; RAout[2] ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; RAout[3] ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; RAout[4] ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; RAout[5] ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; RAout[6] ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; RAout[7] ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; RAout[1] ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RAout[2] ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RAout[3] ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RAout[4] ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RAout[5] ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RAout[6] ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RAout[7] ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RAout[8] ; 17 ; 1 ; 1 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; RAout[9] ; 15 ; 1 ; 1 ; 2 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[0] ; 70 ; 2 ; 8 ; 4 ; 4 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[1] ; 67 ; 2 ; 8 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[2] ; 69 ; 2 ; 8 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; Vout[3] ; 62 ; 2 ; 8 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[3] ; 62 ; 2 ; 8 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; Vout[4] ; 71 ; 2 ; 8 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[5] ; 68 ; 2 ; 8 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[6] ; 58 ; 2 ; 8 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[7] ; 57 ; 2 ; 8 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; nCASout ; 3 ; 1 ; 1 ; 4 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; nCSout ; 8 ; 1 ; 1 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; nDOE ; 55 ; 2 ; 8 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; nDOE ; 55 ; 2 ; 8 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; nRASout ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; nRWEout ; 2 ; 1 ; 1 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; nVOE ; 50 ; 1 ; 7 ; 0 ; 1 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; nVOE ; 50 ; 1 ; 7 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
+-----------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
@ -283,7 +283,7 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pin
; RD[3] ; 89 ; 2 ; 4 ; 5 ; 0 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ;
; RD[4] ; 91 ; 2 ; 4 ; 5 ; 2 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ;
; RD[5] ; 92 ; 2 ; 3 ; 5 ; 0 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ;
; RD[6] ; 95 ; 2 ; 3 ; 5 ; 1 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; RDOE ; - ;
; RD[6] ; 95 ; 2 ; 3 ; 5 ; 1 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ;
; RD[7] ; 96 ; 2 ; 3 ; 5 ; 2 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
@ -352,12 +352,12 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pin
; 47 ; 37 ; 1 ; Ain[3] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 48 ; 38 ; 1 ; Din[4] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 49 ; 39 ; 1 ; Din[5] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 50 ; 40 ; 1 ; nVOE ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; On ;
; 50 ; 40 ; 1 ; nVOE ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 51 ; 41 ; 1 ; nWE ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 52 ; 42 ; 2 ; nC07X ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 53 ; 43 ; 2 ; Ain[7] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 54 ; 44 ; 2 ; Ain[1] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 55 ; 45 ; 2 ; nDOE ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; On ;
; 55 ; 45 ; 2 ; nDOE ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 56 ; 46 ; 2 ; Ain[0] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 57 ; 47 ; 2 ; Vout[7] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 58 ; 48 ; 2 ; Vout[6] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
@ -431,8 +431,8 @@ Note: User assignments will override these defaults. The user specified values a
+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
; |RAM2E ; 238 (180) ; 123 ; 1 ; 70 ; 0 ; 115 (90) ; 26 (23) ; 97 (67) ; 15 (15) ; 6 (1) ; |RAM2E ; RAM2E ; work ;
; |RAM2E_UFM:ram2e_ufm| ; 58 (58) ; 33 ; 1 ; 0 ; 0 ; 25 (25) ; 3 (3) ; 30 (30) ; 0 (0) ; 5 (5) ; |RAM2E|RAM2E_UFM:ram2e_ufm ; RAM2E_UFM ; work ;
; |RAM2E ; 238 (182) ; 126 ; 1 ; 70 ; 0 ; 112 (88) ; 19 (16) ; 107 (78) ; 15 (15) ; 14 (9) ; |RAM2E ; RAM2E ; work ;
; |RAM2E_UFM:ram2e_ufm| ; 56 (56) ; 32 ; 1 ; 0 ; 0 ; 24 (24) ; 3 (3) ; 29 (29) ; 0 (0) ; 5 (5) ; |RAM2E|RAM2E_UFM:ram2e_ufm ; RAM2E_UFM ; work ;
; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst ; UFM ; work ;
; |UFM_altufm_none_p8r:UFM_altufm_none_p8r_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component ; UFM_altufm_none_p8r ; work ;
+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
@ -495,17 +495,6 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; RD[7] ; Bidir ; (0) ;
; nEN80 ; Input ; (0) ;
; nWE ; Input ; (0) ;
; PHI1 ; Input ; (1) ;
; C14M ; Input ; (0) ;
; Din[0] ; Input ; (0) ;
; Din[6] ; Input ; (0) ;
; Din[1] ; Input ; (0) ;
; Din[5] ; Input ; (0) ;
; Din[7] ; Input ; (0) ;
; Din[4] ; Input ; (0) ;
; Din[2] ; Input ; (0) ;
; Din[3] ; Input ; (0) ;
; nC07X ; Input ; (0) ;
; Ain[0] ; Input ; (0) ;
; Ain[1] ; Input ; (0) ;
; Ain[2] ; Input ; (0) ;
@ -514,6 +503,17 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Ain[5] ; Input ; (0) ;
; Ain[6] ; Input ; (0) ;
; Ain[7] ; Input ; (0) ;
; C14M ; Input ; (0) ;
; Din[0] ; Input ; (0) ;
; Din[6] ; Input ; (0) ;
; PHI1 ; Input ; (1) ;
; Din[1] ; Input ; (0) ;
; Din[5] ; Input ; (0) ;
; Din[7] ; Input ; (0) ;
; Din[4] ; Input ; (0) ;
; Din[2] ; Input ; (0) ;
; Din[3] ; Input ; (0) ;
; nC07X ; Input ; (0) ;
+-----------+----------+---------------+
@ -522,22 +522,22 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+--------------------------------+-------------+---------+---------------+--------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
+--------------------------------+-------------+---------+---------------+--------+----------------------+------------------+
; BA[1]~0 ; LC_X2_Y2_N7 ; 2 ; Clock enable ; no ; -- ; -- ;
; C14M ; PIN_12 ; 123 ; Clock ; yes ; Global Clock ; GCLK0 ;
; CS[0]~2 ; LC_X4_Y3_N0 ; 3 ; Clock enable ; no ; -- ; -- ;
; BA[0]~0 ; LC_X2_Y3_N5 ; 2 ; Clock enable ; no ; -- ; -- ;
; BA[0]~1 ; LC_X5_Y2_N3 ; 3 ; Clock enable ; no ; -- ; -- ;
; C14M ; PIN_12 ; 122 ; Clock ; yes ; Global Clock ; GCLK0 ;
; CS[0]~2 ; LC_X3_Y1_N8 ; 3 ; Clock enable ; no ; -- ; -- ;
; DQML~0 ; LC_X2_Y4_N5 ; 2 ; Clock enable ; no ; -- ; -- ;
; Equal1~1 ; LC_X6_Y3_N2 ; 8 ; Clock enable ; no ; -- ; -- ;
; Equal1~2 ; LC_X6_Y4_N0 ; 8 ; Clock enable ; no ; -- ; -- ;
; Equal1~4 ; LC_X6_Y3_N1 ; 4 ; Clock enable ; no ; -- ; -- ;
; Equal1~5 ; LC_X5_Y4_N8 ; 3 ; Clock enable ; no ; -- ; -- ;
; Mux14~0 ; LC_X5_Y4_N3 ; 2 ; Clock enable ; no ; -- ; -- ;
; RAM2E_UFM:ram2e_ufm|RWMask~1 ; LC_X6_Y1_N9 ; 8 ; Clock enable ; no ; -- ; -- ;
; RAM2E_UFM:ram2e_ufm|UFMD[15]~1 ; LC_X4_Y1_N6 ; 8 ; Clock enable ; no ; -- ; -- ;
; RAM2E_UFM:ram2e_ufm|always2~8 ; LC_X6_Y3_N9 ; 16 ; Clock enable ; no ; -- ; -- ;
; RA[2]~0 ; LC_X2_Y2_N5 ; 6 ; Clock enable ; no ; -- ; -- ;
; RDOE ; LC_X3_Y4_N0 ; 8 ; Output enable ; no ; -- ; -- ;
; S[0] ; LC_X7_Y3_N2 ; 35 ; Sync. clear ; no ; -- ; -- ;
; S[3] ; LC_X6_Y4_N9 ; 32 ; Sync. clear ; no ; -- ; -- ;
; Equal1~1 ; LC_X2_Y2_N1 ; 8 ; Clock enable ; no ; -- ; -- ;
; Equal1~2 ; LC_X7_Y4_N7 ; 8 ; Clock enable ; no ; -- ; -- ;
; Mux14~0 ; LC_X2_Y3_N8 ; 2 ; Clock enable ; no ; -- ; -- ;
; PHI1 ; PIN_37 ; 5 ; Clock ; yes ; Global Clock ; GCLK3 ;
; RAM2E_UFM:ram2e_ufm|RWMask~1 ; LC_X7_Y1_N7 ; 8 ; Clock enable ; no ; -- ; -- ;
; RAM2E_UFM:ram2e_ufm|UFMD[15]~1 ; LC_X3_Y1_N3 ; 8 ; Clock enable ; no ; -- ; -- ;
; RAM2E_UFM:ram2e_ufm|always2~8 ; LC_X4_Y2_N1 ; 16 ; Clock enable ; no ; -- ; -- ;
; RA[1]~2 ; LC_X2_Y3_N9 ; 6 ; Clock enable ; no ; -- ; -- ;
; RDOE ; LC_X3_Y3_N4 ; 8 ; Output enable ; no ; -- ; -- ;
; S[0] ; LC_X3_Y3_N3 ; 32 ; Sync. clear ; no ; -- ; -- ;
; S[3] ; LC_X3_Y3_N6 ; 34 ; Sync. clear ; no ; -- ; -- ;
+--------------------------------+-------------+---------+---------------+--------+----------------------+------------------+
@ -546,7 +546,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+------+----------+---------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
+------+----------+---------+----------------------+------------------+
; C14M ; PIN_12 ; 123 ; Global Clock ; GCLK0 ;
; C14M ; PIN_12 ; 122 ; Global Clock ; GCLK0 ;
; PHI1 ; PIN_37 ; 5 ; Global Clock ; GCLK3 ;
+------+----------+---------+----------------------+------------------+
@ -555,12 +556,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+-----------------------+--------------------+
; Routing Resource Type ; Usage ;
+-----------------------+--------------------+
; C4s ; 171 / 784 ( 22 % ) ;
; Direct links ; 55 / 888 ( 6 % ) ;
; Global clocks ; 1 / 4 ( 25 % ) ;
; LAB clocks ; 6 / 32 ( 19 % ) ;
; LUT chains ; 6 / 216 ( 3 % ) ;
; Local interconnects ; 343 / 888 ( 39 % ) ;
; C4s ; 163 / 784 ( 21 % ) ;
; Direct links ; 57 / 888 ( 6 % ) ;
; Global clocks ; 2 / 4 ( 50 % ) ;
; LAB clocks ; 7 / 32 ( 22 % ) ;
; LUT chains ; 5 / 216 ( 2 % ) ;
; Local interconnects ; 340 / 888 ( 38 % ) ;
; R4s ; 150 / 704 ( 21 % ) ;
+-----------------------+--------------------+
@ -586,19 +587,20 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+-------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+------------------------------+
; LAB-wide Signals (Average = 1.58) ; Number of LABs (Total = 24) ;
; LAB-wide Signals (Average = 1.42) ; Number of LABs (Total = 24) ;
+------------------------------------+------------------------------+
; 1 Clock ; 24 ;
; 1 Clock ; 21 ;
; 1 Clock enable ; 9 ;
; 1 Sync. clear ; 2 ;
; 2 Clock enables ; 3 ;
; 2 Clock enables ; 1 ;
; 2 Clocks ; 1 ;
+------------------------------------+------------------------------+
+-----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+----------------------------------------------+------------------------------+
; Number of Signals Sourced (Average = 10.17) ; Number of LABs (Total = 24) ;
; Number of Signals Sourced (Average = 10.13) ; Number of LABs (Total = 24) ;
+----------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
@ -610,8 +612,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; 7 ; 0 ;
; 8 ; 1 ;
; 9 ; 0 ;
; 10 ; 21 ;
; 11 ; 1 ;
; 10 ; 22 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 0 ;
@ -622,18 +624,18 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out (Average = 7.50) ; Number of LABs (Total = 24) ;
; Number of Signals Sourced Out (Average = 7.21) ; Number of LABs (Total = 24) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 1 ; 1 ;
; 2 ; 0 ;
; 3 ; 1 ;
; 4 ; 2 ;
; 5 ; 3 ;
; 6 ; 2 ;
; 7 ; 2 ;
; 3 ; 2 ;
; 4 ; 0 ;
; 5 ; 1 ;
; 6 ; 3 ;
; 7 ; 6 ;
; 8 ; 4 ;
; 9 ; 6 ;
; 9 ; 3 ;
; 10 ; 3 ;
; 11 ; 0 ;
; 12 ; 1 ;
@ -643,29 +645,29 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+-----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+----------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 12.88) ; Number of LABs (Total = 24) ;
; Number of Distinct Inputs (Average = 12.54) ; Number of LABs (Total = 24) ;
+----------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 2 ;
; 5 ; 1 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 2 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 2 ;
; 11 ; 1 ;
; 12 ; 1 ;
; 13 ; 3 ;
; 14 ; 3 ;
; 15 ; 2 ;
; 8 ; 1 ;
; 9 ; 2 ;
; 10 ; 1 ;
; 11 ; 3 ;
; 12 ; 2 ;
; 13 ; 1 ;
; 14 ; 2 ;
; 15 ; 1 ;
; 16 ; 2 ;
; 17 ; 1 ;
; 18 ; 2 ;
; 18 ; 1 ;
; 19 ; 1 ;
; 20 ; 0 ;
; 20 ; 1 ;
; 21 ; 0 ;
; 22 ; 0 ;
; 23 ; 0 ;
@ -706,6 +708,8 @@ Info (176444): Device migration not selected. If you intend to use device migrat
Info (176445): Device 5M570ZT100I5 is compatible
Info (332104): Reading SDC File: '../RAM2E.sdc'
Info (332104): Reading SDC File: '../RAM2E-MAX.sdc'
Warning (332060): Node: PHI1 was determined to be a clock but was found without an associated clock assignment.
Info (13166): Register RefReq is being clocked by PHI1
Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
Info (332111): Found 3 clocks
Info (332111): Period Clock Name
@ -714,10 +718,23 @@ Info (332111): Found 3 clocks
Info (332111): 200.000 ram2e_ufm|ARCLK|regout
Info (332111): 200.000 ram2e_ufm|DRCLK|regout
Info (186079): Completed User Assigned Global Signals Promotion Operation
Info (186215): Automatically promoted signal "C14M" to use Global clock in PIN 12 File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 8
Info (186215): Automatically promoted signal "C14M" to use Global clock in PIN 12 File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 8
Info (186216): Automatically promoted some destinations of signal "PHI1" to use Global clock File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 8
Info (186217): Destination "PHI1r" may be non-global or may not use global clock File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 20
Info (186217): Destination "S~0" may be non-global or may not use global clock File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 19
Info (186228): Pin "PHI1" drives global clock, but is not placed in a dedicated clock pin position File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 8
Info (186079): Completed Auto Global Promotion Operation
Info (176234): Starting register packing
Info (186468): Started processing fast register assignments
Warning (186473): Ignored the FAST_OUTPUT_REGISTER assignment made to the following nodes
Warning (186484): Ignored assignment to node "RAout[0]" because node "RAr[0]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85
Warning (186484): Ignored assignment to node "RAout[1]" because node "RAr[1]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85
Warning (186484): Ignored assignment to node "RAout[2]" because node "RAr[2]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85
Warning (186484): Ignored assignment to node "RAout[3]" because node "RAr[3]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85
Warning (186484): Ignored assignment to node "RAout[4]" because node "RAr[4]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85
Warning (186484): Ignored assignment to node "RAout[5]" because node "RAr[5]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85
Warning (186484): Ignored assignment to node "RAout[6]" because node "RAr[6]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85
Warning (186484): Ignored assignment to node "RAout[7]" because node "RAr[7]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85
Info (186469): Finished processing fast register assignments
Info (176235): Finished register packing
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00
@ -726,25 +743,26 @@ Info (170189): Fitter placement preparation operations beginning
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
Info (170191): Fitter placement operations beginning
Info (170137): Fitter placement was successful
Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
Info (170192): Fitter placement operations ending: elapsed time is 00:00:02
Info (170193): Fitter routing operations beginning
Info (170195): Router estimated average interconnect usage is 23% of the available device resources
Info (170196): Router estimated peak interconnect usage is 23% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
Info (170089): 2e+01 ns of routing delay (approximately 1.1% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report.
Info (170195): Router estimated average interconnect usage is 25% of the available device resources
Info (170196): Router estimated peak interconnect usage is 25% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
Info (170202): The Fitter performed an Auto Fit compilation. No optimizations were skipped because the design's timing and routability requirements required full optimization.
Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
Info (11888): Total time spent on timing analysis during the Fitter is 0.67 seconds.
Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
Info (11888): Total time spent on timing analysis during the Fitter is 0.84 seconds.
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
Info (144001): Generated suppressed messages file Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.fit.smsg
Info: Quartus Prime Fitter was successful. 0 errors, 1 warning
Info: Peak virtual memory: 13748 megabytes
Info: Processing ended: Thu Dec 28 23:09:45 2023
Info: Elapsed time: 00:00:04
Info: Total CPU time (on all processors): 00:00:04
Info (144001): Generated suppressed messages file /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.fit.smsg
Info: Quartus Prime Fitter was successful. 0 errors, 11 warnings
Info: Peak virtual memory: 13771 megabytes
Info: Processing ended: Thu Feb 15 04:16:23 2024
Info: Elapsed time: 00:00:08
Info: Total CPU time (on all processors): 00:00:05
+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.fit.smsg.
The suppressed messages can be found in /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.fit.smsg.

4
CPLD/MAXV/output_files/RAM2E.fit.summary
View File

@ -1,5 +1,5 @@
Fitter Status : Successful - Thu Dec 28 23:09:45 2023
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Fitter Status : Successful - Thu Feb 15 04:16:23 2024
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Revision Name : RAM2E
Top-level Entity Name : RAM2E
Family : MAX V

48
CPLD/MAXV/output_files/RAM2E.flow.rpt
View File

@ -1,6 +1,6 @@
Flow report for RAM2E
Thu Dec 28 23:09:52 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Thu Feb 15 04:16:32 2024
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
---------------------
@ -38,21 +38,21 @@ https://fpgasoftware.intel.com/eula.
+-------------------------------------------------------------------------------------+
; Flow Summary ;
+-----------------------+-------------------------------------------------------------+
; Flow Status ; Successful - Thu Dec 28 23:09:48 2023 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
; Revision Name ; RAM2E ;
; Top-level Entity Name ; RAM2E ;
; Family ; MAX V ;
; Device ; 5M240ZT100C5 ;
; Timing Models ; Final ;
; Total logic elements ; 238 / 240 ( 99 % ) ;
; Total pins ; 70 / 79 ( 89 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
+-----------------------+-------------------------------------------------------------+
+---------------------------------------------------------------------+
; Flow Summary ;
+-----------------------+---------------------------------------------+
; Flow Status ; Successful - Thu Feb 15 04:16:27 2024 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
; Revision Name ; RAM2E ;
; Top-level Entity Name ; RAM2E ;
; Family ; MAX V ;
; Device ; 5M240ZT100C5 ;
; Timing Models ; Final ;
; Total logic elements ; 238 / 240 ( 99 % ) ;
; Total pins ; 70 / 79 ( 89 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
+-----------------------+---------------------------------------------+
+-----------------------------------------+
@ -60,7 +60,7 @@ https://fpgasoftware.intel.com/eula.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 12/28/2023 23:09:13 ;
; Start date & time ; 02/15/2024 04:15:29 ;
; Main task ; Compilation ;
; Revision Name ; RAM2E ;
+-------------------+---------------------+
@ -71,7 +71,7 @@ https://fpgasoftware.intel.com/eula.
+-------------------------------+------------------------------+---------------+-------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------+------------------------------+---------------+-------------+------------+
; COMPILER_SIGNATURE_ID ; 121381084694.170382295304664 ; -- ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 121380219419.170798852904876 ; -- ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; NUM_PARALLEL_PROCESSORS ; 4 ; -- ; -- ; -- ;
@ -85,11 +85,11 @@ https://fpgasoftware.intel.com/eula.
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:28 ; 1.0 ; 13113 MB ; 00:00:41 ;
; Fitter ; 00:00:04 ; 1.0 ; 13748 MB ; 00:00:04 ;
; Assembler ; 00:00:01 ; 1.0 ; 13069 MB ; 00:00:01 ;
; Timing Analyzer ; 00:00:03 ; 1.0 ; 13067 MB ; 00:00:02 ;
; Total ; 00:00:36 ; -- ; -- ; 00:00:48 ;
; Analysis & Synthesis ; 00:00:45 ; 1.0 ; 13146 MB ; 00:00:47 ;
; Fitter ; 00:00:08 ; 1.0 ; 13771 MB ; 00:00:05 ;
; Assembler ; 00:00:02 ; 1.0 ; 13091 MB ; 00:00:01 ;
; Timing Analyzer ; 00:00:03 ; 1.0 ; 13093 MB ; 00:00:02 ;
; Total ; 00:00:58 ; -- ; -- ; 00:00:55 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+

2
CPLD/MAXV/output_files/RAM2E.jdi
View File

@ -1,6 +1,6 @@
<sld_project_info>
<project>
<hash md5_digest_80b="a200c32949da45b33c7d"/>
<hash md5_digest_80b="ec04ae5d795b1a9f31d1"/>
</project>
<file_info>
<file device="5M240ZT100C5" path="RAM2E.sof" usercode="0xFFFFFFFF"/>

183
CPLD/MAXV/output_files/RAM2E.map.rpt
View File

@ -1,6 +1,6 @@
Analysis & Synthesis report for RAM2E
Thu Dec 28 23:09:40 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Thu Feb 15 04:16:13 2024
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
---------------------
@ -43,19 +43,19 @@ https://fpgasoftware.intel.com/eula.
+-------------------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+-------------------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Dec 28 23:09:40 2023 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
; Revision Name ; RAM2E ;
; Top-level Entity Name ; RAM2E ;
; Family ; MAX V ;
; Total logic elements ; 244 ;
; Total pins ; 70 ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
+-----------------------------+-------------------------------------------------------------+
+---------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+---------------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Feb 15 04:16:13 2024 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
; Revision Name ; RAM2E ;
; Top-level Entity Name ; RAM2E ;
; Family ; MAX V ;
; Total logic elements ; 252 ;
; Total pins ; 70 ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
+-----------------------------+---------------------------------------------+
+------------------------------------------------------------------------------------------------------------+
@ -146,16 +146,16 @@ https://fpgasoftware.intel.com/eula.
+----------------------------+-------------+
+----------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+----------------------------------+--------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+----------------------------------+--------------------------------+---------+
; ../RAM2E.v ; yes ; User Verilog HDL File ; Y:/Repos/RAM2E/CPLD/RAM2E.v ; ;
; ../UFM-MAX.v ; yes ; User Verilog HDL File ; Y:/Repos/RAM2E/CPLD/UFM-MAX.v ; ;
; UFM.v ; yes ; User Wizard-Generated File ; Y:/Repos/RAM2E/CPLD/MAXV/UFM.v ; ;
; ../RAM2E.mif ; yes ; User Memory Initialization File ; Y:/Repos/RAM2E/CPLD/RAM2E.mif ; ;
+----------------------------------+-----------------+----------------------------------+--------------------------------+---------+
+------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+----------------------------------+----------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+----------------------------------+----------------------------------------+---------+
; ../RAM2E.v ; yes ; User Verilog HDL File ; //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v ; ;
; ../UFM-MAX.v ; yes ; User Verilog HDL File ; //Mac/Home/Repos/RAM2E/CPLD/UFM-MAX.v ; ;
; UFM.v ; yes ; User Wizard-Generated File ; //Mac/Home/Repos/RAM2E/CPLD/MAXV/UFM.v ; ;
; ../RAM2E.mif ; yes ; User Memory Initialization File ; //Mac/Home/Repos/RAM2E/CPLD/RAM2E.mif ; ;
+----------------------------------+-----------------+----------------------------------+----------------------------------------+---------+
+-----------------------------------------------------+
@ -163,33 +163,33 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------+-------+
; Resource ; Usage ;
+---------------------------------------------+-------+
; Total logic elements ; 244 ;
; -- Combinational with no register ; 121 ;
; -- Register only ; 32 ;
; -- Combinational with a register ; 91 ;
; Total logic elements ; 252 ;
; -- Combinational with no register ; 126 ;
; -- Register only ; 33 ;
; -- Combinational with a register ; 93 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 118 ;
; -- 3 input functions ; 41 ;
; -- 2 input functions ; 48 ;
; -- 1 input functions ; 4 ;
; -- 4 input functions ; 116 ;
; -- 3 input functions ; 53 ;
; -- 2 input functions ; 46 ;
; -- 1 input functions ; 3 ;
; -- 0 input functions ; 1 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 230 ;
; -- normal mode ; 238 ;
; -- arithmetic mode ; 14 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 3 ;
; -- asynchronous clear/load mode ; 0 ;
; ; ;
; Total registers ; 123 ;
; Total registers ; 126 ;
; Total logic cells in carry chains ; 15 ;
; I/O pins ; 70 ;
; UFM blocks ; 1 ;
; Maximum fan-out node ; C14M ;
; Maximum fan-out ; 123 ;
; Total fan-out ; 977 ;
; Maximum fan-out ; 122 ;
; Total fan-out ; 1001 ;
; Average fan-out ; 3.10 ;
+---------------------------------------------+-------+
@ -199,8 +199,8 @@ https://fpgasoftware.intel.com/eula.
+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
; |RAM2E ; 244 (181) ; 123 ; 1 ; 70 ; 0 ; 121 (91) ; 32 (24) ; 91 (66) ; 15 (15) ; 0 (0) ; |RAM2E ; RAM2E ; work ;
; |RAM2E_UFM:ram2e_ufm| ; 63 (63) ; 33 ; 1 ; 0 ; 0 ; 30 (30) ; 8 (8) ; 25 (25) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm ; RAM2E_UFM ; work ;
; |RAM2E ; 252 (191) ; 126 ; 1 ; 70 ; 0 ; 126 (97) ; 33 (25) ; 93 (69) ; 15 (15) ; 0 (0) ; |RAM2E ; RAM2E ; work ;
; |RAM2E_UFM:ram2e_ufm| ; 61 (61) ; 32 ; 1 ; 0 ; 0 ; 29 (29) ; 8 (8) ; 24 (24) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm ; RAM2E_UFM ; work ;
; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst ; UFM ; work ;
; |UFM_altufm_none_p8r:UFM_altufm_none_p8r_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component ; UFM_altufm_none_p8r ; work ;
+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+
@ -221,32 +221,33 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 123 ;
; Total registers ; 126 ;
; Number of registers using Synchronous Clear ; 3 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 62 ;
; Number of registers using Clock Enable ; 59 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------+
; Inverted Register Statistics ;
+----------------------------------------+---------+
; Inverted Register ; Fan out ;
+----------------------------------------+---------+
; nRASout~reg0 ; 1 ;
; nCASout~reg0 ; 1 ;
; nRWEout~reg0 ; 1 ;
; DQML~reg0 ; 1 ;
; DQMH~reg0 ; 1 ;
; CKE ; 1 ;
; nRAS ; 1 ;
; nCAS ; 1 ;
; nRWE ; 1 ;
; Total number of inverted registers = 9 ; ;
+----------------------------------------+---------+
+---------------------------------------------------+
; Inverted Register Statistics ;
+-----------------------------------------+---------+
; Inverted Register ; Fan out ;
+-----------------------------------------+---------+
; CKEout~reg0 ; 1 ;
; nRASout~reg0 ; 1 ;
; nCASout~reg0 ; 1 ;
; nRWEout~reg0 ; 1 ;
; DQML~reg0 ; 1 ;
; DQMH~reg0 ; 1 ;
; CKE ; 1 ;
; nRAS ; 1 ;
; nCAS ; 1 ;
; nRWE ; 1 ;
; Total number of inverted registers = 10 ; ;
+-----------------------------------------+---------+
+----------------------------------------------------------------------------------------------------------------------------------------------------+
@ -254,12 +255,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+
; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |RAM2E|S[0] ;
; 4:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |RAM2E|CS[0] ;
; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |RAM2E|S[2] ;
; 4:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |RAM2E|CS[1] ;
; 4:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |RAM2E|RAM2E_UFM:ram2e_ufm|RWMask[5] ;
; 16:1 ; 2 bits ; 20 LEs ; 2 LEs ; 18 LEs ; Yes ; |RAM2E|BA[1]~reg0 ;
; 17:1 ; 4 bits ; 44 LEs ; 8 LEs ; 36 LEs ; Yes ; |RAM2E|RA[4] ;
; 19:1 ; 2 bits ; 24 LEs ; 4 LEs ; 20 LEs ; Yes ; |RAM2E|RA[2] ;
; 16:1 ; 2 bits ; 20 LEs ; 2 LEs ; 18 LEs ; Yes ; |RAM2E|BA[0]~reg0 ;
; 17:1 ; 4 bits ; 44 LEs ; 8 LEs ; 36 LEs ; Yes ; |RAM2E|RA[6] ;
; 19:1 ; 2 bits ; 24 LEs ; 4 LEs ; 20 LEs ; Yes ; |RAM2E|RA[1] ;
; 10:1 ; 2 bits ; 12 LEs ; 4 LEs ; 8 LEs ; Yes ; |RAM2E|DQML~reg0 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+
@ -280,50 +281,50 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Info: Processing started: Thu Dec 28 23:09:12 2023
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Info: Processing started: Thu Feb 15 04:15:28 2024
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E-MAXV -c RAM2E
Info (20032): Parallel compilation is enabled and will use up to 4 processors
Info (12021): Found 1 design units, including 1 entities, in source file /repos/ram2e/cpld/ram2e.v
Info (12023): Found entity 1: RAM2E File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file /repos/ram2e/cpld/ufm-max.v
Info (12023): Found entity 1: RAM2E_UFM File: Y:/Repos/RAM2E/CPLD/UFM-MAX.v Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file //mac/home/repos/ram2e/cpld/ram2e.v
Info (12023): Found entity 1: RAM2E File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file //mac/home/repos/ram2e/cpld/ufm-max.v
Info (12023): Found entity 1: RAM2E_UFM File: //Mac/Home/Repos/RAM2E/CPLD/UFM-MAX.v Line: 1
Info (12021): Found 2 design units, including 2 entities, in source file ufm.v
Info (12023): Found entity 1: UFM_altufm_none_p8r File: Y:/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 47
Info (12023): Found entity 2: UFM File: Y:/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 166
Info (12023): Found entity 1: UFM_altufm_none_p8r File: //Mac/Home/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 47
Info (12023): Found entity 2: UFM File: //Mac/Home/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 166
Info (12127): Elaborating entity "RAM2E" for the top level hierarchy
Info (12128): Elaborating entity "RAM2E_UFM" for hierarchy "RAM2E_UFM:ram2e_ufm" File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 112
Info (12128): Elaborating entity "UFM" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst" File: Y:/Repos/RAM2E/CPLD/UFM-MAX.v Line: 79
Info (12128): Elaborating entity "UFM_altufm_none_p8r" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component" File: Y:/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 217
Info (12128): Elaborating entity "RAM2E_UFM" for hierarchy "RAM2E_UFM:ram2e_ufm" File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 136
Info (12128): Elaborating entity "UFM" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst" File: //Mac/Home/Repos/RAM2E/CPLD/UFM-MAX.v Line: 77
Info (12128): Elaborating entity "UFM_altufm_none_p8r" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component" File: //Mac/Home/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 217
Warning (13024): Output pins are stuck at VCC or GND
Warning (13410): Pin "nCSout" is stuck at GND File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 78
Warning (14632): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
Warning (14632): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
Warning (14632): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
Warning (14632): Output pin "Dout[3]" driven by bidirectional pin "RD[3]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
Warning (14632): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
Warning (14632): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
Warning (14632): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
Warning (14632): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 52
Warning (13410): Pin "nCSout" is stuck at GND File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 75
Warning (14632): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (14632): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (14632): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (14632): Output pin "Dout[3]" driven by bidirectional pin "RD[3]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (14632): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (14632): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (14632): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (14632): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50
Warning (21074): Design contains 1 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "nWE80" File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 11
Info (21057): Implemented 315 device resources after synthesis - the final resource count might be different
Warning (15610): No output dependent on input pin "nWE80" File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 11
Info (21057): Implemented 323 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 22 input pins
Info (21059): Implemented 40 output pins
Info (21060): Implemented 8 bidirectional pins
Info (21061): Implemented 244 logic cells
Info (21061): Implemented 252 logic cells
Info (21070): Implemented 1 User Flash Memory blocks
Info (144001): Generated suppressed messages file Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.map.smsg
Info (144001): Generated suppressed messages file /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.map.smsg
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings
Info: Peak virtual memory: 13113 megabytes
Info: Processing ended: Thu Dec 28 23:09:40 2023
Info: Elapsed time: 00:00:28
Info: Total CPU time (on all processors): 00:00:41
Info: Peak virtual memory: 13146 megabytes
Info: Processing ended: Thu Feb 15 04:16:13 2024
Info: Elapsed time: 00:00:45
Info: Total CPU time (on all processors): 00:00:47
+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in Y:/Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.map.smsg.
The suppressed messages can be found in /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.map.smsg.

6
CPLD/MAXV/output_files/RAM2E.map.smsg
View File

@ -1,3 +1,3 @@
Warning (10273): Verilog HDL warning at RAM2E.v(74): extended using "x" or "z" File: Y:/Repos/RAM2E/CPLD/RAM2E.v Line: 74
Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: Y:/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 73
Warning (10463): Verilog HDL Declaration warning at UFM.v(189): "program" is SystemVerilog-2005 keyword File: Y:/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 189
Warning (10273): Verilog HDL warning at RAM2E.v(72): extended using "x" or "z" File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 72
Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: //Mac/Home/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 73
Warning (10463): Verilog HDL Declaration warning at UFM.v(189): "program" is SystemVerilog-2005 keyword File: //Mac/Home/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 189

6
CPLD/MAXV/output_files/RAM2E.map.summary
View File

@ -1,9 +1,9 @@
Analysis & Synthesis Status : Successful - Thu Dec 28 23:09:40 2023
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Analysis & Synthesis Status : Successful - Thu Feb 15 04:16:13 2024
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Revision Name : RAM2E
Top-level Entity Name : RAM2E
Family : MAX V
Total logic elements : 244
Total logic elements : 252
Total pins : 70
Total virtual pins : 0
UFM blocks : 1 / 1 ( 100 % )

2
CPLD/MAXV/output_files/RAM2E.pin
View File

@ -58,7 +58,7 @@
-- Pin directions (input, output or bidir) are based on device operating in user mode.
---------------------------------------------------------------------------------
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
CHIP "RAM2E" ASSIGNED TO AN: 5M240ZT100C5
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment

BIN
CPLD/MAXV/output_files/RAM2E.pof
View File

Binary file not shown.

527
CPLD/MAXV/output_files/RAM2E.sta.rpt
View File

@ -1,6 +1,6 @@
Timing Analyzer report for RAM2E
Thu Dec 28 23:09:52 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Thu Feb 15 04:16:32 2024
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
---------------------
@ -20,8 +20,8 @@ Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Editio
12. Setup: 'ram2e_ufm|DRCLK|regout'
13. Setup: 'ram2e_ufm|ARCLK|regout'
14. Setup: 'C14M'
15. Hold: 'ram2e_ufm|DRCLK|regout'
16. Hold: 'ram2e_ufm|ARCLK|regout'
15. Hold: 'ram2e_ufm|ARCLK|regout'
16. Hold: 'ram2e_ufm|DRCLK|regout'
17. Hold: 'C14M'
18. Setup Transfers
19. Hold Transfers
@ -57,18 +57,18 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+-----------------------+---------------------------------------------------------------------+
; Quartus Prime Version ; Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
; Timing Analyzer ; Legacy Timing Analyzer ;
; Revision Name ; RAM2E ;
; Device Family ; MAX V ;
; Device Name ; 5M240ZT100C5 ;
; Timing Models ; Final ;
; Delay Model ; Slow Model ;
; Rise/Fall Delays ; Unavailable ;
+-----------------------+---------------------------------------------------------------------+
+-----------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+-----------------------+-----------------------------------------------------+
; Quartus Prime Version ; Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
; Timing Analyzer ; Legacy Timing Analyzer ;
; Revision Name ; RAM2E ;
; Device Family ; MAX V ;
; Device Name ; 5M240ZT100C5 ;
; Timing Models ; Final ;
; Delay Model ; Slow Model ;
; Rise/Fall Delays ; Unavailable ;
+-----------------------+-----------------------------------------------------+
+------------------------------------------+
@ -93,8 +93,8 @@ https://fpgasoftware.intel.com/eula.
+------------------+--------+--------------------------+
; SDC File Path ; Status ; Read at ;
+------------------+--------+--------------------------+
; ../RAM2E.sdc ; OK ; Thu Dec 28 23:09:51 2023 ;
; ../RAM2E-MAX.sdc ; OK ; Thu Dec 28 23:09:51 2023 ;
; ../RAM2E.sdc ; OK ; Thu Feb 15 04:16:31 2024 ;
; ../RAM2E-MAX.sdc ; OK ; Thu Feb 15 04:16:31 2024 ;
+------------------+--------+--------------------------+
@ -116,7 +116,7 @@ https://fpgasoftware.intel.com/eula.
+-----------+-----------------+------------------------+------+
; 10.0 MHz ; 10.0 MHz ; ram2e_ufm|ARCLK|regout ; ;
; 10.0 MHz ; 10.0 MHz ; ram2e_ufm|DRCLK|regout ; ;
; 27.71 MHz ; 27.71 MHz ; C14M ; ;
; 27.75 MHz ; 27.75 MHz ; C14M ; ;
+-----------+-----------------+------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
@ -126,9 +126,9 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+------------------------+---------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------+---------+---------------+
; ram2e_ufm|DRCLK|regout ; -25.451 ; -25.451 ;
; ram2e_ufm|ARCLK|regout ; -25.441 ; -25.441 ;
; C14M ; -20.081 ; -208.886 ;
; ram2e_ufm|DRCLK|regout ; -25.469 ; -25.469 ;
; ram2e_ufm|ARCLK|regout ; -25.439 ; -25.439 ;
; C14M ; -18.223 ; -201.658 ;
+------------------------+---------+---------------+
@ -137,9 +137,9 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+------------------------+---------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------+---------+---------------+
; ram2e_ufm|DRCLK|regout ; -14.567 ; -14.567 ;
; ram2e_ufm|ARCLK|regout ; -14.558 ; -14.558 ;
; C14M ; 3.133 ; 0.000 ;
; ram2e_ufm|ARCLK|regout ; -14.560 ; -14.560 ;
; ram2e_ufm|DRCLK|regout ; -14.560 ; -14.560 ;
; C14M ; 3.156 ; 0.000 ;
+------------------------+---------+---------------+
@ -171,8 +171,8 @@ No paths to report.
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
; -25.451 ; RAM2E_UFM:ram2e_ufm|DRShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.001 ; -0.970 ; 4.482 ;
; -25.432 ; RAM2E_UFM:ram2e_ufm|DRDIn ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.001 ; -0.970 ; 4.463 ;
; -25.469 ; RAM2E_UFM:ram2e_ufm|DRShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.001 ; -2.477 ; 2.993 ;
; -25.439 ; RAM2E_UFM:ram2e_ufm|DRDIn ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.001 ; -2.477 ; 2.963 ;
; 100.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; 200.000 ; 0.000 ; 80.000 ;
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
@ -182,128 +182,117 @@ No paths to report.
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
; -25.441 ; RAM2E_UFM:ram2e_ufm|ARShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M ; ram2e_ufm|ARCLK|regout ; 0.001 ; -0.977 ; 4.465 ;
; -25.439 ; RAM2E_UFM:ram2e_ufm|ARShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M ; ram2e_ufm|ARCLK|regout ; 0.001 ; -2.477 ; 2.963 ;
; 100.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 200.000 ; 0.000 ; 80.000 ;
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup: 'C14M' ;
+---------+-----------------------------------------------------------------------------------------------------------------+----------------------------------+------------------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+-----------------------------------------------------------------------------------------------------------------+----------------------------------+------------------------+-------------+--------------+------------+------------+
; -20.081 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.970 ; 20.731 ;
; -18.769 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.970 ; 19.419 ;
; -18.109 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.970 ; 18.759 ;
; -17.584 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.970 ; 18.234 ;
; -17.584 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.970 ; 18.234 ;
; -17.584 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.970 ; 18.234 ;
; -17.584 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.970 ; 18.234 ;
; -17.584 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.970 ; 18.234 ;
; -17.584 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.970 ; 18.234 ;
; -17.584 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.970 ; 18.234 ;
; -16.915 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|LEDEN ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.970 ; 17.565 ;
; -11.924 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 0.970 ; 12.574 ;
; 25.780 ; RA[5] ; RAout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 8.819 ;
; 26.401 ; RA[0] ; RAout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 8.198 ;
; 27.872 ; RA[10] ; RAout[10]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.727 ;
; 28.323 ; CKE ; CKEout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.276 ;
; 28.531 ; RA[8] ; RAout[8]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.068 ;
; 28.539 ; RA[11] ; RAout[11]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.060 ;
; 28.589 ; RA[9] ; RAout[9]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.010 ;
; 30.107 ; RA[7] ; RAout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.492 ;
; 30.133 ; nRWE ; nRWEout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.466 ;
; 30.360 ; nRAS ; nRASout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.239 ;
; 30.365 ; nCAS ; nCASout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.234 ;
; 30.369 ; RA[1] ; RAout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.230 ;
; 30.392 ; RA[6] ; RAout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.207 ;
; 31.173 ; RA[3] ; RAout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 3.426 ;
; 31.207 ; RA[2] ; RAout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 3.392 ;
; 31.456 ; RA[4] ; RAout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 3.143 ;
; 33.754 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.766 ;
; 33.754 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.766 ;
; 33.754 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.766 ;
; 33.754 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.766 ;
; 33.754 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.766 ;
; 33.754 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.766 ;
; 33.754 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.766 ;
; 33.754 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.766 ;
; 34.170 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.350 ;
; 34.170 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.350 ;
; 34.170 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.350 ;
; 34.170 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.350 ;
; 34.170 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.350 ;
; 34.170 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.350 ;
; 34.170 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.350 ;
; 34.170 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.350 ;
; 35.281 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 69.841 ; 0.000 ; 34.239 ;
; 35.281 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 69.841 ; 0.000 ; 34.239 ;
; 35.281 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 69.841 ; 0.000 ; 34.239 ;
; 35.281 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; C14M ; C14M ; 69.841 ; 0.000 ; 34.239 ;
; 35.281 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; C14M ; C14M ; 69.841 ; 0.000 ; 34.239 ;
; 35.281 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 69.841 ; 0.000 ; 34.239 ;
; 35.281 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 69.841 ; 0.000 ; 34.239 ;
; 35.281 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; C14M ; C14M ; 69.841 ; 0.000 ; 34.239 ;
; 37.521 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMErase ; C14M ; C14M ; 69.841 ; 0.000 ; 31.999 ;
; 37.937 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMErase ; C14M ; C14M ; 69.841 ; 0.000 ; 31.583 ;
; 39.048 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMErase ; C14M ; C14M ; 69.841 ; 0.000 ; 30.472 ;
; 40.235 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMProgram ; C14M ; C14M ; 69.841 ; 0.000 ; 29.285 ;
; 40.239 ; S[1] ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; C14M ; C14M ; 69.841 ; 0.000 ; 29.281 ;
; 40.355 ; S[1] ; RAM2E_UFM:ram2e_ufm|DRCLK ; C14M ; C14M ; 69.841 ; 0.000 ; 29.165 ;
; 40.651 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMProgram ; C14M ; C14M ; 69.841 ; 0.000 ; 28.869 ;
; 40.655 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; C14M ; C14M ; 69.841 ; 0.000 ; 28.865 ;
; 40.771 ; S[2] ; RAM2E_UFM:ram2e_ufm|DRCLK ; C14M ; C14M ; 69.841 ; 0.000 ; 28.749 ;
; 41.239 ; FS[15] ; nCAS ; C14M ; C14M ; 69.841 ; 0.000 ; 28.281 ;
; 41.532 ; S[3] ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 27.988 ;
; 41.557 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 27.963 ;
; 41.762 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMProgram ; C14M ; C14M ; 69.841 ; 0.000 ; 27.758 ;
; 41.766 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; C14M ; C14M ; 69.841 ; 0.000 ; 27.754 ;
; 41.808 ; FS[15] ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 27.712 ;
; 41.882 ; S[3] ; RAM2E_UFM:ram2e_ufm|DRCLK ; C14M ; C14M ; 69.841 ; 0.000 ; 27.638 ;
; 41.904 ; FS[13] ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 27.616 ;
; 42.244 ; CS[0] ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; C14M ; C14M ; 69.841 ; 0.000 ; 27.276 ;
; 42.246 ; CS[0] ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; C14M ; C14M ; 69.841 ; 0.000 ; 27.274 ;
; 42.482 ; FS[15] ; nRAS ; C14M ; C14M ; 69.841 ; 0.000 ; 27.038 ;
; 42.717 ; S[3] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.803 ;
; 42.717 ; S[3] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.803 ;
; 42.717 ; S[3] ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.803 ;
; 42.717 ; S[3] ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.803 ;
; 42.717 ; S[3] ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.803 ;
; 42.717 ; S[3] ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.803 ;
; 42.717 ; S[3] ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.803 ;
; 42.742 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.778 ;
; 42.742 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.778 ;
; 42.742 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.778 ;
; 42.742 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.778 ;
; 42.742 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.778 ;
; 42.742 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.778 ;
; 42.742 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.778 ;
; 42.780 ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.740 ;
; 42.842 ; S[2] ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.678 ;
; 42.988 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.532 ;
; 42.988 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.532 ;
; 42.988 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.532 ;
; 42.988 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.532 ;
; 42.988 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.532 ;
; 42.988 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.532 ;
; 42.988 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.532 ;
; 42.988 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.532 ;
; 42.991 ; FS[0] ; nCAS ; C14M ; C14M ; 69.841 ; 0.000 ; 26.529 ;
; 42.993 ; FS[15] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.527 ;
; 42.993 ; FS[15] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.527 ;
; 42.993 ; FS[15] ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.527 ;
+---------+-----------------------------------------------------------------------------------------------------------------+----------------------------------+------------------------+-------------+--------------+------------+------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold: 'ram2e_ufm|DRCLK|regout' ;
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
; -14.567 ; RAM2E_UFM:ram2e_ufm|DRDIn ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.000 ; -0.970 ; 4.463 ;
; -14.548 ; RAM2E_UFM:ram2e_ufm|DRShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.000 ; -0.970 ; 4.482 ;
; 60.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; 0.000 ; 0.000 ; 80.000 ;
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup: 'C14M' ;
+---------+-----------------------------------------------------------------------------------------------------------------+---------------------------------+------------------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+-----------------------------------------------------------------------------------------------------------------+---------------------------------+------------------------+-------------+--------------+------------+------------+
; -18.223 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.477 ; 20.380 ;
; -18.223 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.477 ; 20.380 ;
; -18.223 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.477 ; 20.380 ;
; -18.223 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.477 ; 20.380 ;
; -18.223 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.477 ; 20.380 ;
; -18.223 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.477 ; 20.380 ;
; -18.223 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.477 ; 20.380 ;
; -18.223 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.477 ; 20.380 ;
; -17.497 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|LEDEN ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.477 ; 19.654 ;
; -14.015 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.477 ; 16.172 ;
; -14.004 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.477 ; 16.161 ;
; -10.358 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.477 ; 12.515 ;
; 16.903 ; S[3] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.696 ;
; 16.903 ; S[3] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.696 ;
; 16.903 ; S[3] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.696 ;
; 16.993 ; S[3] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.606 ;
; 16.993 ; S[3] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.606 ;
; 16.993 ; S[3] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.606 ;
; 17.034 ; S[1] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.565 ;
; 17.034 ; S[1] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.565 ;
; 17.034 ; S[1] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.565 ;
; 17.124 ; S[1] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.475 ;
; 17.124 ; S[1] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.475 ;
; 17.124 ; S[1] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.475 ;
; 17.625 ; S[2] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.974 ;
; 17.625 ; S[2] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.974 ;
; 17.625 ; S[2] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.974 ;
; 17.715 ; S[2] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.884 ;
; 17.715 ; S[2] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.884 ;
; 17.715 ; S[2] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.884 ;
; 17.828 ; S[0] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.771 ;
; 17.828 ; S[0] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.771 ;
; 17.828 ; S[0] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.771 ;
; 17.918 ; S[0] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.681 ;
; 17.918 ; S[0] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.681 ;
; 17.918 ; S[0] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.681 ;
; 20.070 ; S[3] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 14.529 ;
; 20.070 ; S[3] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 14.529 ;
; 20.201 ; S[1] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 14.398 ;
; 20.201 ; S[1] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 14.398 ;
; 20.792 ; S[2] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.807 ;
; 20.792 ; S[2] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.807 ;
; 20.995 ; S[0] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.604 ;
; 20.995 ; S[0] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.604 ;
; 22.233 ; S[2] ; VOE ; C14M ; C14M ; 34.920 ; 0.000 ; 12.366 ;
; 23.933 ; S[3] ; VOE ; C14M ; C14M ; 34.920 ; 0.000 ; 10.666 ;
; 24.168 ; S[0] ; VOE ; C14M ; C14M ; 34.920 ; 0.000 ; 10.431 ;
; 25.342 ; S[1] ; VOE ; C14M ; C14M ; 34.920 ; 0.000 ; 9.257 ;
; 25.631 ; S[2] ; RAT ; C14M ; C14M ; 34.920 ; 0.000 ; 8.968 ;
; 27.763 ; S[3] ; RAT ; C14M ; C14M ; 34.920 ; 0.000 ; 6.836 ;
; 28.027 ; RA[8] ; RAr[8] ; C14M ; C14M ; 34.920 ; 0.000 ; 6.572 ;
; 28.362 ; RA[11] ; RAr[11] ; C14M ; C14M ; 34.920 ; 0.000 ; 6.237 ;
; 28.707 ; nCAS ; nCASout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.892 ;
; 29.373 ; S[0] ; RAT ; C14M ; C14M ; 34.920 ; 0.000 ; 5.226 ;
; 29.587 ; S[1] ; RAT ; C14M ; C14M ; 34.920 ; 0.000 ; 5.012 ;
; 30.153 ; nRWE ; nRWEout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.446 ;
; 30.163 ; nRAS ; nRASout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.436 ;
; 30.336 ; RA[6] ; RAr[6] ; C14M ; C14M ; 34.920 ; 0.000 ; 4.263 ;
; 30.364 ; RA[2] ; RAr[2] ; C14M ; C14M ; 34.920 ; 0.000 ; 4.235 ;
; 30.410 ; RA[9] ; RAr[9] ; C14M ; C14M ; 34.920 ; 0.000 ; 4.189 ;
; 30.411 ; CKE ; CKEout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.188 ;
; 30.417 ; RA[10] ; RAr[10] ; C14M ; C14M ; 34.920 ; 0.000 ; 4.182 ;
; 31.443 ; RA[0] ; RAr[0] ; C14M ; C14M ; 34.920 ; 0.000 ; 3.156 ;
; 31.443 ; RA[3] ; RAr[3] ; C14M ; C14M ; 34.920 ; 0.000 ; 3.156 ;
; 31.443 ; RA[4] ; RAr[4] ; C14M ; C14M ; 34.920 ; 0.000 ; 3.156 ;
; 31.444 ; RA[1] ; RAr[1] ; C14M ; C14M ; 34.920 ; 0.000 ; 3.155 ;
; 31.444 ; RA[7] ; RAr[7] ; C14M ; C14M ; 34.920 ; 0.000 ; 3.155 ;
; 31.452 ; RA[5] ; RAr[5] ; C14M ; C14M ; 34.920 ; 0.000 ; 3.147 ;
; 33.825 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.695 ;
; 33.825 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.695 ;
; 33.825 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.695 ;
; 33.825 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.695 ;
; 33.825 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.695 ;
; 33.825 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.695 ;
; 33.825 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.695 ;
; 33.825 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.695 ;
; 35.938 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 69.841 ; 0.000 ; 33.582 ;
; 35.938 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 69.841 ; 0.000 ; 33.582 ;
; 35.938 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 69.841 ; 0.000 ; 33.582 ;
; 35.938 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; C14M ; C14M ; 69.841 ; 0.000 ; 33.582 ;
; 35.938 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; C14M ; C14M ; 69.841 ; 0.000 ; 33.582 ;
; 35.938 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 69.841 ; 0.000 ; 33.582 ;
; 35.938 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 69.841 ; 0.000 ; 33.582 ;
; 35.938 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; C14M ; C14M ; 69.841 ; 0.000 ; 33.582 ;
; 36.829 ; S[2] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 32.691 ;
; 36.829 ; S[2] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 32.691 ;
; 36.829 ; S[2] ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 32.691 ;
; 36.829 ; S[2] ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 32.691 ;
; 36.829 ; S[2] ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 32.691 ;
; 36.829 ; S[2] ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 32.691 ;
; 36.829 ; S[2] ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 32.691 ;
; 36.829 ; S[2] ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 32.691 ;
; 36.851 ; S[2] ; RAM2E_UFM:ram2e_ufm|DRCLK ; C14M ; C14M ; 69.841 ; 0.000 ; 32.669 ;
; 36.947 ; S[0] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 69.841 ; 0.000 ; 32.573 ;
; 36.947 ; S[0] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 69.841 ; 0.000 ; 32.573 ;
; 36.947 ; S[0] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 69.841 ; 0.000 ; 32.573 ;
; 36.947 ; S[0] ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; C14M ; C14M ; 69.841 ; 0.000 ; 32.573 ;
; 36.947 ; S[0] ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; C14M ; C14M ; 69.841 ; 0.000 ; 32.573 ;
; 36.947 ; S[0] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 69.841 ; 0.000 ; 32.573 ;
; 36.947 ; S[0] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 69.841 ; 0.000 ; 32.573 ;
+---------+-----------------------------------------------------------------------------------------------------------------+---------------------------------+------------------------+-------------+--------------+------------+------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
@ -311,116 +300,127 @@ No paths to report.
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
; -14.558 ; RAM2E_UFM:ram2e_ufm|ARShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M ; ram2e_ufm|ARCLK|regout ; 0.000 ; -0.977 ; 4.465 ;
; -14.560 ; RAM2E_UFM:ram2e_ufm|ARShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M ; ram2e_ufm|ARCLK|regout ; 0.000 ; -2.477 ; 2.963 ;
; 60.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 0.000 ; 0.000 ; 80.000 ;
+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold: 'ram2e_ufm|DRCLK|regout' ;
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
; -14.560 ; RAM2E_UFM:ram2e_ufm|DRDIn ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.000 ; -2.477 ; 2.963 ;
; -14.530 ; RAM2E_UFM:ram2e_ufm|DRShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.000 ; -2.477 ; 2.993 ;
; 60.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; 0.000 ; 0.000 ; 80.000 ;
+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold: 'C14M' ;
+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
; 3.133 ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.172 ;
; 3.136 ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.175 ;
; 3.429 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.468 ;
; 3.436 ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.475 ;
; 3.453 ; CmdTout[0] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.492 ;
; 3.483 ; CS[0] ; CS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.522 ;
; 3.527 ; CS[1] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.566 ;
; 3.753 ; RWBank[7] ; RA[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.792 ;
; 3.765 ; Ready ; Ready ; C14M ; C14M ; 0.000 ; 0.000 ; 3.804 ;
; 3.767 ; FS[0] ; FS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.806 ;
; 3.803 ; CmdTout[1] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.842 ;
; 3.833 ; CS[2] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.872 ;
; 3.879 ; RC[2] ; RC[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.918 ;
; 3.883 ; RC[2] ; RC[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.922 ;
; 3.885 ; RC[2] ; RC[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.924 ;
; 4.002 ; PHI1r ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.041 ;
; 4.318 ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.357 ;
; 4.629 ; RWSel ; RWSel ; C14M ; C14M ; 0.000 ; 0.000 ; 4.668 ;
; 4.854 ; S[0] ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.893 ;
; 4.855 ; S[1] ; S[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.894 ;
; 4.859 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.898 ;
; 4.879 ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.918 ;
; 5.050 ; RWSel ; CmdTout[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.089 ;
; 5.054 ; RWSel ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.093 ;
; 5.156 ; S[2] ; DOEEN ; C14M ; C14M ; 0.000 ; 0.000 ; 5.195 ;
; 5.163 ; S[2] ; VOEEN ; C14M ; C14M ; 0.000 ; 0.000 ; 5.202 ;
; 3.156 ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.195 ;
; 3.164 ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.203 ;
; 3.170 ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.209 ;
; 3.364 ; FS[0] ; FS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.403 ;
; 3.394 ; Ready ; Ready ; C14M ; C14M ; 0.000 ; 0.000 ; 3.433 ;
; 3.418 ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.457 ;
; 3.450 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.489 ;
; 3.543 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 3.582 ;
; 3.547 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 3.586 ;
; 3.741 ; RAM2E_UFM:ram2e_ufm|DRDIn ; RAM2E_UFM:ram2e_ufm|DRDIn ; C14M ; C14M ; 0.000 ; 0.000 ; 3.780 ;
; 3.752 ; RAM2E_UFM:ram2e_ufm|UFMProgram ; RAM2E_UFM:ram2e_ufm|UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 3.791 ;
; 3.752 ; RWSel ; RWSel ; C14M ; C14M ; 0.000 ; 0.000 ; 3.791 ;
; 3.776 ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; C14M ; C14M ; 0.000 ; 0.000 ; 3.815 ;
; 3.814 ; CmdTout[0] ; CmdTout[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.853 ;
; 3.817 ; CmdTout[0] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.856 ;
; 3.829 ; CmdTout[0] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.868 ;
; 3.865 ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; C14M ; C14M ; 0.000 ; 0.000 ; 3.904 ;
; 3.935 ; CS[0] ; CS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.974 ;
; 3.938 ; CS[0] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.977 ;
; 3.951 ; CS[0] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.990 ;
; 4.101 ; PHI1r ; S[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.140 ;
; 4.102 ; PHI1r ; S[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.141 ;
; 4.106 ; PHI1r ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.145 ;
; 4.224 ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.263 ;
; 4.479 ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.518 ;
; 4.839 ; CmdSetRWBankFFChip ; RWBank[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.878 ;
; 4.849 ; RAM2E_UFM:ram2e_ufm|DRCLKPulse ; RAM2E_UFM:ram2e_ufm|DRCLK ; C14M ; C14M ; 0.000 ; 0.000 ; 4.888 ;
; 5.135 ; S[3] ; BA[0]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 5.174 ;
; 5.217 ; FS[15] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.256 ;
; 5.217 ; FS[7] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.256 ;
; 5.228 ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; C14M ; C14M ; 0.000 ; 0.000 ; 5.267 ;
; 5.229 ; RAM2E_UFM:ram2e_ufm|DRDIn ; RAM2E_UFM:ram2e_ufm|DRDIn ; C14M ; C14M ; 0.000 ; 0.000 ; 5.268 ;
; 5.233 ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; RWBank[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.272 ;
; 5.253 ; FS[9] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.292 ;
; 5.218 ; RWBank[7] ; RA[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.257 ;
; 5.231 ; RA[10] ; RA[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.270 ;
; 5.266 ; FS[5] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.305 ;
; 5.272 ; RWBank[1] ; RA[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.311 ;
; 5.281 ; CmdTout[1] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.320 ;
; 5.290 ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 5.329 ;
; 5.301 ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 5.340 ;
; 5.312 ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; C14M ; C14M ; 0.000 ; 0.000 ; 5.351 ;
; 5.313 ; RC[0] ; RC[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.352 ;
; 5.315 ; RC[0] ; RC[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.354 ;
; 5.316 ; RC[0] ; RC[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.355 ;
; 5.320 ; CmdTout[0] ; CmdTout[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.359 ;
; 5.329 ; CmdTout[0] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.368 ;
; 5.351 ; S[3] ; S[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.390 ;
; 5.354 ; S[3] ; VOEEN ; C14M ; C14M ; 0.000 ; 0.000 ; 5.393 ;
; 5.355 ; S[3] ; DOEEN ; C14M ; C14M ; 0.000 ; 0.000 ; 5.394 ;
; 5.429 ; RAM2E_UFM:ram2e_ufm|UFMProgram ; RAM2E_UFM:ram2e_ufm|UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 5.468 ;
; 5.429 ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; C14M ; C14M ; 0.000 ; 0.000 ; 5.468 ;
; 5.443 ; FS[1] ; FS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.482 ;
; 5.267 ; FS[9] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.306 ;
; 5.271 ; FS[10] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.310 ;
; 5.284 ; CmdTout[1] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.323 ;
; 5.287 ; CmdTout[1] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.326 ;
; 5.420 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; C14M ; C14M ; 0.000 ; 0.000 ; 5.459 ;
; 5.443 ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; C14M ; C14M ; 0.000 ; 0.000 ; 5.482 ;
; 5.443 ; CmdTout[2] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.482 ;
; 5.449 ; FS[11] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.488 ;
; 5.452 ; FS[4] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.491 ;
; 5.452 ; FS[13] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.491 ;
; 5.453 ; FS[2] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.492 ;
; 5.453 ; FS[14] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.492 ;
; 5.460 ; FS[6] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.499 ;
; 5.464 ; FS[3] ; FS[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.503 ;
; 5.455 ; FS[1] ; FS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.494 ;
; 5.457 ; S[1] ; RDOE ; C14M ; C14M ; 0.000 ; 0.000 ; 5.496 ;
; 5.464 ; FS[4] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.503 ;
; 5.465 ; FS[2] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.504 ;
; 5.466 ; FS[12] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.505 ;
; 5.552 ; RC[1] ; RC[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.591 ;
; 5.559 ; RC[1] ; RC[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.598 ;
; 5.561 ; CS[0] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.600 ;
; 5.563 ; RC[1] ; RC[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.602 ;
; 5.564 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 5.603 ;
; 5.565 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; C14M ; C14M ; 0.000 ; 0.000 ; 5.604 ;
; 5.565 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 5.604 ;
; 5.570 ; S[1] ; DOEEN ; C14M ; C14M ; 0.000 ; 0.000 ; 5.609 ;
; 5.579 ; S[1] ; VOEEN ; C14M ; C14M ; 0.000 ; 0.000 ; 5.618 ;
; 5.613 ; CS[1] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.652 ;
; 5.884 ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.923 ;
; 5.988 ; FS[9] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.027 ;
; 5.482 ; FS[6] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.521 ;
; 5.486 ; FS[3] ; FS[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.525 ;
; 5.514 ; S[0] ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.553 ;
; 5.515 ; S[0] ; nCAS ; C14M ; C14M ; 0.000 ; 0.000 ; 5.554 ;
; 5.530 ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 5.569 ;
; 5.534 ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 5.573 ;
; 5.564 ; CS[1] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.603 ;
; 5.574 ; CS[1] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.613 ;
; 5.704 ; CmdLEDGet ; RWBank[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.743 ;
; 5.895 ; CmdSetRWBankFFLED ; RWBank[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.934 ;
; 6.001 ; FS[5] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.040 ;
; 6.016 ; S[0] ; RA[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.055 ;
; 6.132 ; FS[9] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.171 ;
; 6.002 ; FS[9] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.041 ;
; 6.006 ; FS[10] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.045 ;
; 6.064 ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.103 ;
; 6.145 ; FS[5] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.184 ;
; 6.276 ; FS[9] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.315 ;
; 6.315 ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.354 ;
; 6.319 ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; RWBank[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.358 ;
; 6.338 ; CS[0] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.377 ;
; 6.365 ; FS[8] ; FS[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.404 ;
; 6.445 ; FS[1] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.484 ;
; 6.451 ; FS[11] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.490 ;
; 6.454 ; FS[4] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.493 ;
; 6.146 ; FS[9] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.185 ;
; 6.150 ; FS[10] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.189 ;
; 6.174 ; PHI1r ; S[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.213 ;
; 6.290 ; FS[9] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.329 ;
; 6.294 ; RWBank[1] ; RA[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.333 ;
; 6.298 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.337 ;
; 6.310 ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.349 ;
; 6.318 ; RWBank[6] ; BA[1]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 6.357 ;
; 6.321 ; FS[15] ; DQML~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 6.360 ;
; 6.323 ; FS[15] ; DQMH~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 6.362 ;
; 6.348 ; RAM2E_UFM:ram2e_ufm|LEDEN ; RAM2E_UFM:ram2e_ufm|LEDEN ; C14M ; C14M ; 0.000 ; 0.000 ; 6.387 ;
; 6.351 ; RWBank[4] ; RA[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.390 ;
; 6.371 ; FS[8] ; FS[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.410 ;
; 6.389 ; Ready ; RDOE ; C14M ; C14M ; 0.000 ; 0.000 ; 6.428 ;
; 6.393 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 6.432 ;
; 6.425 ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; RWBank[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.464 ;
; 6.452 ; CS[2] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.491 ;
; 6.454 ; FS[13] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.493 ;
; 6.455 ; FS[14] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.494 ;
; 6.462 ; FS[6] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.501 ;
; 6.466 ; FS[3] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.505 ;
; 6.516 ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; RWBank[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.555 ;
; 6.536 ; FS[10] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.575 ;
; 6.567 ; S[3] ; CKE ; C14M ; C14M ; 0.000 ; 0.000 ; 6.606 ;
; 6.598 ; FS[4] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.637 ;
; 6.457 ; FS[1] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.496 ;
; 6.466 ; FS[4] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.505 ;
; 6.484 ; FS[6] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.523 ;
; 6.488 ; FS[3] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.527 ;
; 6.509 ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.548 ;
; 6.537 ; FS[11] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.576 ;
; 6.542 ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.581 ;
; 6.549 ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; RWBank[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.588 ;
; 6.598 ; FS[13] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.637 ;
; 6.610 ; FS[3] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.649 ;
; 6.627 ; S[2] ; S[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.666 ;
; 6.628 ; RA[10] ; RA[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.667 ;
; 6.710 ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.749 ;
; 6.735 ; RWSel ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.774 ;
; 6.742 ; FS[4] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.781 ;
; 6.754 ; FS[3] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.793 ;
; 6.771 ; RWBank[4] ; RA[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.810 ;
; 6.787 ; S[0] ; RA[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.826 ;
; 6.610 ; FS[4] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.649 ;
; 6.613 ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.652 ;
; 6.632 ; FS[3] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.671 ;
; 6.692 ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; RWBank[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.731 ;
; 6.754 ; FS[4] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.793 ;
; 6.774 ; FS[10] ; RA[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.813 ;
; 6.776 ; FS[3] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.815 ;
; 6.786 ; FS[10] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.825 ;
; 6.786 ; FS[10] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.825 ;
; 6.786 ; FS[10] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.825 ;
+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+
@ -429,7 +429,7 @@ No paths to report.
+------------------------+------------------------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------------------+------------------------+----------+----------+----------+----------+
; C14M ; C14M ; 1625 ; 0 ; 16 ; 0 ;
; C14M ; C14M ; 1539 ; 0 ; 56 ; 0 ;
; ram2e_ufm|DRCLK|regout ; C14M ; 13 ; 0 ; 0 ; 0 ;
; C14M ; ram2e_ufm|ARCLK|regout ; 1 ; 0 ; 0 ; 0 ;
; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 1 ; 0 ; 0 ; 0 ;
@ -444,7 +444,7 @@ Entries labeled "false path" only account for clock-to-clock false paths and not
+------------------------+------------------------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------------------+------------------------+----------+----------+----------+----------+
; C14M ; C14M ; 1625 ; 0 ; 16 ; 0 ;
; C14M ; C14M ; 1539 ; 0 ; 56 ; 0 ;
; ram2e_ufm|DRCLK|regout ; C14M ; 13 ; 0 ; 0 ; 0 ;
; C14M ; ram2e_ufm|ARCLK|regout ; 1 ; 0 ; 0 ; 0 ;
; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 1 ; 0 ; 0 ; 0 ;
@ -472,23 +472,24 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
; Property ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 1 ; 1 ;
; Unconstrained Input Ports ; 28 ; 28 ;
; Unconstrained Input Port Paths ; 176 ; 176 ;
; Unconstrained Input Port Paths ; 169 ; 169 ;
; Unconstrained Output Ports ; 47 ; 47 ;
; Unconstrained Output Port Paths ; 76 ; 76 ;
; Unconstrained Output Port Paths ; 83 ; 83 ;
+---------------------------------+-------+------+
+----------------------------------------------------------------------+
; Clock Status Summary ;
+------------------------+------------------------+------+-------------+
; Target ; Clock ; Type ; Status ;
+------------------------+------------------------+------+-------------+
; C14M ; C14M ; Base ; Constrained ;
; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; Base ; Constrained ;
; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; Base ; Constrained ;
+------------------------+------------------------+------+-------------+
+------------------------------------------------------------------------+
; Clock Status Summary ;
+------------------------+------------------------+------+---------------+
; Target ; Clock ; Type ; Status ;
+------------------------+------------------------+------+---------------+
; C14M ; C14M ; Base ; Constrained ;
; PHI1 ; ; Base ; Unconstrained ;
; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; Base ; Constrained ;
; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; Base ; Constrained ;
+------------------------+------------------------+------+---------------+
+---------------------------------------------------------------------------------------------------+
@ -678,8 +679,8 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
+--------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Timing Analyzer
Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Info: Processing started: Thu Dec 28 23:09:49 2023
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Info: Processing started: Thu Feb 15 04:16:29 2024
Info: Command: quartus_sta RAM2E-MAXV -c RAM2E
Info: qsta_default_script.tcl version: #1
Info (20032): Parallel compilation is enabled and will use up to 4 processors
@ -689,23 +690,25 @@ Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332104): Reading SDC File: '../RAM2E.sdc'
Info (332104): Reading SDC File: '../RAM2E-MAX.sdc'
Warning (332060): Node: PHI1 was determined to be a clock but was found without an associated clock assignment.
Info (13166): Register RefReq is being clocked by PHI1
Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Can't run Report Timing Closure Recommendations. The current device family is not supported.
Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ram2e_ufm|ARCLK|regout are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ram2e_ufm|DRCLK|regout are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
Critical Warning (332148): Timing requirements not met
Info (332146): Worst-case setup slack is -25.451
Info (332146): Worst-case setup slack is -25.469
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -25.451 -25.451 ram2e_ufm|DRCLK|regout
Info (332119): -25.441 -25.441 ram2e_ufm|ARCLK|regout
Info (332119): -20.081 -208.886 C14M
Info (332146): Worst-case hold slack is -14.567
Info (332119): -25.469 -25.469 ram2e_ufm|DRCLK|regout
Info (332119): -25.439 -25.439 ram2e_ufm|ARCLK|regout
Info (332119): -18.223 -201.658 C14M
Info (332146): Worst-case hold slack is -14.560
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): -14.567 -14.567 ram2e_ufm|DRCLK|regout
Info (332119): -14.558 -14.558 ram2e_ufm|ARCLK|regout
Info (332119): 3.133 0.000 C14M
Info (332119): -14.560 -14.560 ram2e_ufm|ARCLK|regout
Info (332119): -14.560 -14.560 ram2e_ufm|DRCLK|regout
Info (332119): 3.156 0.000 C14M
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is 34.581
@ -715,13 +718,11 @@ Info (332146): Worst-case minimum pulse width slack is 34.581
Info (332119): 70.000 0.000 ram2e_ufm|ARCLK|regout
Info (332119): 70.000 0.000 ram2e_ufm|DRCLK|regout
Info (332001): The selected device family is not supported by the report_metastability command.
Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ram2e_ufm|ARCLK|regout are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ram2e_ufm|DRCLK|regout are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings
Info: Peak virtual memory: 13067 megabytes
Info: Processing ended: Thu Dec 28 23:09:52 2023
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 4 warnings
Info: Peak virtual memory: 13093 megabytes
Info: Processing ended: Thu Feb 15 04:16:32 2024
Info: Elapsed time: 00:00:03
Info: Total CPU time (on all processors): 00:00:02

26
CPLD/MAXV/output_files/RAM2E.sta.summary
View File

@ -3,27 +3,27 @@ Timing Analyzer Summary
------------------------------------------------------------
Type : Setup 'ram2e_ufm|DRCLK|regout'
Slack : -25.451
TNS : -25.451
Slack : -25.469
TNS : -25.469
Type : Setup 'ram2e_ufm|ARCLK|regout'
Slack : -25.441
TNS : -25.441
Slack : -25.439
TNS : -25.439
Type : Setup 'C14M'
Slack : -20.081
TNS : -208.886
Type : Hold 'ram2e_ufm|DRCLK|regout'
Slack : -14.567
TNS : -14.567
Slack : -18.223
TNS : -201.658
Type : Hold 'ram2e_ufm|ARCLK|regout'
Slack : -14.558
TNS : -14.558
Slack : -14.560
TNS : -14.560
Type : Hold 'ram2e_ufm|DRCLK|regout'
Slack : -14.560
TNS : -14.560
Type : Hold 'C14M'
Slack : 3.133
Slack : 3.156
TNS : 0.000
Type : Minimum Pulse Width 'C14M'

636
CPLD/RAM2E-old.v Normal file
View File

@ -0,0 +1,636 @@
module RAM2E(C14M, PHI1,
nWE, nWE80, nEN80, nC07X,
Ain, Din, Dout, nDOE, Vout, nVOE,
CKE, nCS, nRAS, nCAS, nRWE,
BA, RA, RD, DQML, DQMH);
/* Clocks */
input C14M, PHI1;
/* Control inputs */
input nWE, nWE80, nEN80, nC07X;
/* Delay for EN80 signal */
//output DelayOut = 1'b0;
//input DelayIn;
wire EN80 = ~nEN80;
/* Address Bus */
input [7:0] Ain; // Multiplexed DRAM address input
/* 6502 Data Bus */
input [7:0] Din; // 6502 data bus inputs
reg DOEEN = 0; // 6502 data bus output enable from state machine
output nDOE = ~(EN80 & nWE & DOEEN); // 6502 data bus output enable
output reg [7:0] Dout; // 6502 data Bus output
/* Video Data Bus */
output nVOE = ~(~PHI1); /// Video data bus output enable
output reg [7:0] Vout; // Video data bus
/* SDRAM */
output reg CKE = 0;
output reg nCS = 1, nRAS = 1, nCAS = 1, nRWE = 1;
output reg [1:0] BA;
output reg [11:0] RA;
output reg DQML = 1, DQMH = 1;
wire RDOE = EN80 & ~nWE80;
inout [7:0] RD = RDOE ? Din[7:0] : 8'bZ;
/* RAMWorks Bank Register and Capacity Mask */
reg [7:0] RWBank = 0; // RAMWorks bank register
reg [7:0] RWMask = 0; // RAMWorks bank reg. capacity mask
reg RWSel = 0; // RAMWorks bank register select
reg RWMaskSet = 0; // RAMWorks Mask register set flag
reg SetRWBankFF = 0; // Causes RWBank to be zeroed next RWSel access
/* Command Sequence Detector */
reg [2:0] CS = 0; // Command sequence state
reg [2:0] CmdTout = 0; // Command sequence timeout
/* UFM Interface */
reg [15:8] UFMD = 0; // *Parallel* UFM data register
reg ARCLK = 0; // UFM address register clock
// UFM address register data input tied to 0
reg ARShift = 0; // 1 to Shift UFM address in, 0 to increment
reg DRCLK = 0; // UFM data register clock
reg DRDIn = 0; // UFM data register input
reg DRShift = 0; // 1 to shift UFM out, 0 to load from current address
reg UFMErase = 0; // Rising edge starts erase. UFM+RTP must not be busy
reg UFMProgram = 0; // Rising edge starts program. UFM+RTP must not be busy
wire UFMBusy; // 1 if UFM is doing user operation. Asynchronous
wire RTPBusy; // 1 if real-time programming in progress. Asynchronous
wire DRDOut; // UFM data output
// UFM oscillator always enabled
wire UFMOsc; // UFM oscillator output (3.3-5.5 MHz)
UFM UFM_inst ( // UFM IP block (for Altera MAX II and MAX V)
.arclk (ARCLK),
.ardin (1'b0),
.arshft (ARShift),
.drclk (DRCLK),
.drdin (DRDIn),
.drshft (DRShift),
.erase (UFMErase),
.oscena (1'b1),
.program (UFMProgram),
.busy (UFMBusy),
.drdout (DRDOut),
.osc (UFMOsc),
.rtpbusy (RTPBusy));
reg UFMBusyReg = 0; // UFMBusy registered to sync with C14M
reg RTPBusyReg = 0; // RTPBusy registered to sync with C14M
/* UFM State & User Command Triggers */
reg UFMInitDone = 0; // 1 if UFM initialization finished
reg UFMReqErase = 0; // 1 if UFM requires erase
reg UFMBitbang = 0; // Set by user command. Loads UFM outputs next RWSel
reg UFMPrgmEN = 0; // Set by user command. Programs UFM
reg UFMEraseEN = 0; // Set by user command. Erases UFM
reg DRCLKPulse = 0; // Set by user command. Causes DRCLK pulse next C14M
/* State Counters */
reg PHI1reg = 0; // Saved PHI1 at last rising clock edge
reg Ready = 0; // 1 if done with init sequence (S0) and enter S1-S15
reg [15:0] FS = 0; // Fast state counter
reg [3:0] S = 0; // IIe State counter
/* State Counters */
always @(posedge C14M) begin
// Increment fast state counter
FS <= FS+1;
// Synchronize Apple state counter to S1 when just entering PHI1
PHI1reg <= PHI1; // Save old PHI1
S <= (PHI1 & ~PHI1reg & Ready) ? 4'h1 :
S==4'h0 ? 4'h0 :
S==4'hF ? 4'hF : S+1;
end
/* UFM Control */
always @(posedge C14M) begin
// Synchronize asynchronous UFM signals
UFMBusyReg <= UFMBusy;
RTPBusyReg <= RTPBusy;
if (S==4'h0) begin
if ((FS[15:13]==3'b101) | (FS[15:13]==3'b111 & UFMReqErase)) begin
// In states AXXX-BXXX and also EXXX-FXXX if erase/wrap req'd
// shift in 0's to address register
ARCLK <= FS[0]; // Clock address register
DRCLK <= 1'b0; // Don't clock data register
ARShift <= 1'b1; // Shift address registers
DRDIn <= 1'b0; // Don't care DRDIn
DRShift <= 1'b0; // Don't care DRDShift
end else if (~UFMInitDone & FS[15:13]==3'b110 & FS[4:1]==4'h4) begin
// In states CXXX-DXXX (substep 4)
// Xfer to data reg (repeat 256x 1x)
ARCLK <= 1'b0; // Don't clock address register
DRCLK <= FS[0]; // Clock data register
ARShift <= 1'b0; // Don't care ARShift
DRDIn <= 1'b0; // Don't care DRDIn
DRShift <= 1'b0; // Don't care DRShift
end else if (~UFMInitDone & FS[15:13]==3'b110 & FS[4]==1'b1) begin
// In states CXXX-DXXX (substeps 8-F)
// Save UFM D15-8, shift out D14-7 (repeat 256x 8x)
DRCLK <= FS[0]; // Clock data register
ARShift <= 1'b0; // ARShift is 0 because we want to increment
DRDIn <= 1'b0; // Don't care what to shift into data register
DRShift <= 1'b1; // Shift data register
// Shift into UFMD
if (FS[0]) UFMD[15:8] <= {UFMD[14:8], DRDOut};
// Compare and store mask
if (FS[4:1]==4'hF) begin
ARCLK <= FS[0]; // Clock address register to increment
// If byte is erased (0xFF, i.e. all 1's, is erased)...
if (UFMD[14:8]==7'b1111111 & DRDOut==1'b1) begin
// Current UFM address is where we want to store
UFMInitDone <= 1'b1; // Quit iterating
// Otherwise byte is valid setting (i.e. some bit is 0)...
end else begin
// Set RWMask, but if saved mask is 0x80, store ~0xFF
if (UFMD[14:8]==7'b1000000 & DRDOut==1'b0) begin
RWMask[7:0] <= {1'b1, ~7'h7F};
end else RWMask[7:0] <= {UFMD[14], ~UFMD[13:8], ~DRDOut};
// If last byte in sector...
if (FS[12:5]==8'hFF) begin
UFMReqErase <= 1'b1; // Mark need to erase
end
end
end else ARCLK <= 1'b0; // Don't clock address register
end else begin
ARCLK <= 1'b0;
DRCLK <= 1'b0;
ARShift <= 1'b0;
DRDIn <= 1'b0;
DRShift <= 1'b0;
end
// Don't erase or program UFM during initialization
UFMErase <= 1'b0;
UFMProgram <= 1'b0;
// Keep DRCLK pulse control disabled during init
DRCLKPulse <= 1'b0;
end else begin
// Can only shift UFM data register now
ARCLK <= 1'b0;
ARShift <= 1'b0;
DRShift <= 1'b1;
// UFM bitbang control
if (UFMBitbang & CS==3'h7 & RWSel & S==4'hC) begin
DRDIn <= Din[6];
DRCLKPulse <= Din[7];
DRCLK <= 1'b0;
end else begin
DRCLKPulse <= 1'b0;
DRCLK <= DRCLKPulse;
end
// Set capacity mask
if (RWMaskSet & RWSel & S==4'hC) RWMask[7:0] <= {Din[7], ~Din[6:0]};
// UFM programming sequence
if (UFMPrgmEN | UFMEraseEN) begin
if (~UFMBusyReg & ~RTPBusyReg) begin
if (UFMReqErase | UFMEraseEN) UFMErase <= 1'b1;
else if (UFMPrgmEN) UFMProgram <= 1'b1;
end else if (UFMBusyReg) UFMReqErase <= 1'b0;
end
end
end
/* SDRAM Control */
always @(posedge C14M) begin
if (S==4'h0) begin
// SDRAM initialization
if (FS[15:0]==16'hFFC0) begin
// Precharge All
nCS <= 1'b0;
nRAS <= 1'b0;
nCAS <= 1'b1;
nRWE <= 1'b0;
RA[10] <= 1'b1; // "all"
end else if (FS[15:4]==16'hFFD & FS[0]==1'b0) begin // Repeat 8x
// Auto-refresh
nCS <= 1'b0;
nRAS <= 1'b0;
nCAS <= 1'b0;
nRWE <= 1'b1;
RA[10] <= 1'b0;
end else if (FS[15:0]==16'hFFE8) begin
// Set Mode Register
nCS <= 1'b0;
nRAS <= 1'b0;
nCAS <= 1'b0;
nRWE <= 1'b0;
RA[10] <= 1'b0; // Reserved in mode register
end else if (FS[15:4]==12'hFFF & FS[0]==1'b0) begin // Repeat 8x
// Auto-refresh
nCS <= 1'b0;
nRAS <= 1'b0;
nCAS <= 1'b0;
nRWE <= 1'b1;
RA[10] <= 1'b0;
end else begin // Otherwise send no-op
// NOP
nCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nRWE <= 1'b1;
RA[10] <= 1'b0;
end
// Enable SDRAM clock after 65,280 cycles (~4.56ms)
CKE <= FS[15:8] == 8'hFF;
// Mode register contents
BA[1:0] <= 2'b00; // Reserved
RA[11] <= 1'b0; // Reserved
// RA[10] set above ^
RA[9] <= 1'b1; // "1" for single write mode
RA[8] <= 1'b0; // Reserved
RA[7] <= 1'b0; // "0" for not test mode
RA[6:4] <= 3'b010; // "2" for CAS latency 2
RA[3] <= 1'b0; // "0" for sequential burst (not used)
RA[2:0] <= 3'b000; // "0" for burst length 1 (no burst)
// Mask everything
DQML <= 1'b1;
DQMH <= 1'b1;
// Inhibit data bus output
DOEEN <= 1'b0;
// Begin normal operation after 128k init cycles (~9.15ms)
if (FS == 16'hFFFF) Ready <= 1'b1;
end else if (S==4'h1) begin
// Enable clock
CKE <= 1'b1;
// NOP
nCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nRWE <= 1'b1;
// Don't care bank, RA[11:8]
BA <= 2'b00;
RA[11:8] <= 4'b0000;
// Mask everything
DQML <= 1'b1;
DQMH <= 1'b1;
// Inhibit data bus output
DOEEN <= 1'b0;
end else if (S==4'h2) begin
// Enable clock
CKE <= 1'b1;
// Activate
nCS <= 1'b0;
nRAS <= 1'b0;
nCAS <= 1'b1;
nRWE <= 1'b1;
// SDRAM bank 0, high-order row address is 0
BA <= 2'b00;
RA[11:8] <= 4'b0000;
// Row address is as previously latched
// Mask everything
DQML <= 1'b1;
DQMH <= 1'b1;
// Inhibit data bus output
DOEEN <= 1'b0;
end else if (S==4'h3) begin
// Enable clock
CKE <= 1'b1;
// Read
nCS <= 1'b0;
nRAS <= 1'b1;
nCAS <= 1'b0;
nRWE <= 1'b1;
// SDRAM bank 0, RA[11,9:8] don't care
BA <= 2'b00;
RA[11] <= 1'b0;
RA[10] <= 1'b1; // (A10 set to auto-precharge)
RA[9] <= 1'b0;
RA[8] <= 1'b0;
// Latch column address for read command
RA[7:0] <= Ain[7:0];
// Read low byte (high byte is +4MB in ramworks)
DQML <= 1'b0;
DQMH <= 1'b1;
// Inhibit data bus output
DOEEN <= 1'b0;
end else if (S==4'h4) begin
// Enable clock
CKE <= 1'b1;
// NOP
nCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nRWE <= 1'b1;
// Don't care bank, RA[11:8]
BA <= 2'b00;
RA[11:8] <= 4'b0000;
// Mask everything
DQML <= 1'b1;
DQMH <= 1'b1;
// Inhibit data bus output
DOEEN <= 1'b0;
end else if (S==4'h5) begin
// Enable clock
CKE <= 1'b1;
// NOP
nCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nRWE <= 1'b1;
// Don't care bank, RA[11:8]
BA <= 2'b00;
RA[11:8] <= 4'b0000;
// Mask everything
DQML <= 1'b1;
DQMH <= 1'b1;
// Inhibit data bus output
DOEEN <= 1'b0;
end else if (S==4'h6) begin
// Enable clock
CKE <= 1'b1;
if (FS[5:4]==0) begin
// Auto-refresh
nCS <= 1'b0;
nRAS <= 1'b0;
nCAS <= 1'b0;
nRWE <= 1'b1;
end else begin
// NOP
nCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nRWE <= 1'b1;
end
// Don't care bank, RA[11:8]
BA <= 2'b00;
RA[11:8] <= 4'b0000;
// Mask everything
DQML <= 1'b1;
DQMH <= 1'b1;
// Inhibit data bus output
DOEEN <= 1'b0;
end else if (S==4'h7) begin
// Enable clock
CKE <= 1'b1;
// NOP
nCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nRWE <= 1'b1;
// Don't care bank, RA[11:8]
BA <= 2'b00;
RA[11:8] <= 4'b0000;
// Latch row address for activate command
RA[7:0] <= Ain[7:0];
// Mask everything
DQML <= 1'b1;
DQMH <= 1'b1;
// Inhibit data bus output
DOEEN <= 1'b0;
end else if (S==4'h8) begin
// Enable clock if '245 output enabled
CKE <= EN80;
// Activate if '245 output enabled
nCS <= nEN80;
nRAS <= 1'b0;
nCAS <= 1'b1;
nRWE <= 1'b1;
// SDRAM bank, RA[11:8] determine by RamWorks bank
BA <= RWBank[5:4];
RA[11:8] <= RWBank[3:0];
// Row address is as previously latched
// Mask everything
DQML <= 1'b1;
DQMH <= 1'b1;
// Inhibit data bus output
DOEEN <= 1'b0;
end else if (S==4'h9) begin
// Enable clock if '245 output enabled
CKE <= EN80;
// Read/Write if '245 output enabled
nCS <= nEN80;
nRAS <= 1'b1;
nCAS <= 1'b0;
nRWE <= nWE80;
// SDRAM bank still determined by RamWorks, RA[11,9:8] don't care
BA <= RWBank[5:4];
RA[11] <= 1'b0;
RA[10] <= 1'b1; // (A10 set to auto-precharge)
RA[9] <= 1'b0;
RA[8] <= RWBank[7];
// Latch column address for R/W command
RA[7:0] <= Ain[7:0];
// Latch RAMWorks low nybble write select using old row address
RWSel <= RA[0] & ~RA[3] & ~nWE & ~nC07X;
// Mask according to RAMWorks bank (high byte is +4MB)
DQML <= RWBank[6];
DQMH <= ~RWBank[6];
// Inhibit data bus output
DOEEN <= 1'b0;
end else if (S==4'hA) begin
// Enable clock if '245 output enabled
CKE <= EN80;
// NOP
nCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nRWE <= 1'b1;
// Don't care bank, RA[11:8]
BA <= 2'b00;
RA[11:8] <= 4'b0000;
// Mask everything
DQML <= 1'b1;
DQMH <= 1'b1;
// Inhibit data bus output
DOEEN <= 1'b0;
end else if (S==4'hB) begin
// Disable clock
CKE <= 1'b0;
// NOP
nCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nRWE <= 1'b1;
// Don't care bank, RA[11:8]
BA <= 2'b00;
RA[11:8] <= 4'b0000;
// Mask everything
DQML <= 1'b1;
DQMH <= 1'b1;
// Enable data bus output
DOEEN <= 1'b1;
end else if (S==4'hC) begin
// Disable clock
CKE <= 1'b0;
// NOP
nCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nRWE <= 1'b1;
// Don't care bank, RA[11:8]
BA <= 2'b00;
RA[11:8] <= 4'b0000;
// Mask everything
DQML <= 1'b1;
DQMH <= 1'b1;
// Enable data bus output
DOEEN <= 1'b1;
// RAMWorks Bank Register Select
if (RWSel) begin
// Latch RAMWorks bank if accessed
if (SetRWBankFF) RWBank <= 8'hFF;
else RWBank <= Din[7:0] & {RWMask[7], ~RWMask[6:0]};
// Recognize command sequence and advance CS state
if ((CS==3'h0 & Din[7:0]==8'hFF) |
(CS==3'h1 & Din[7:0]==8'h00) |
(CS==3'h2 & Din[7:0]==8'h55) |
(CS==3'h3 & Din[7:0]==8'hAA) |
(CS==3'h4 & Din[7:0]==8'hC1) |
(CS==3'h5 & Din[7:0]==8'hAD) |
CS==3'h6 | CS==3'h7) CS <= CS+1;
else CS <= 0; // Back to beginning if it's not right
if (CS==3'h6) begin // Recognize and submit command in CS6
SetRWBankFF <= Din[7:0]==8'hFF;
if (Din[7:0]==8'hEF) UFMPrgmEN <= 1'b1;
if (Din[7:0]==8'hEE) UFMEraseEN <= 1'b1;
UFMBitbang <= Din[7:0]==8'hEA;
RWMaskSet <= Din[7:0]==8'hE0;
end else begin // Reset command triggers
SetRWBankFF <= 1'b0;
UFMBitbang <= 1'b0;
RWMaskSet <= 1'b0;
end
CmdTout <= 0; // Reset command timeout if RWSel accessed
end else begin
CmdTout <= CmdTout+1; // Increment command timeout
// If command sequence times out, reset sequence state
if (CmdTout==3'h7) CS <= 0;
end
end else if (S==4'hD) begin
// Disable clock
CKE <= 1'b0;
// NOP
nCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nRWE <= 1'b1;
// Don't care bank, RA[11:8]
BA <= 2'b00;
RA[11:8] <= 4'b0000;
// Mask everything
DQML <= 1'b1;
DQMH <= 1'b1;
// Enable data bus output
DOEEN <= 1'b1;
end else if (S==4'hE) begin
// Disable clock
CKE <= 1'b0;
// NOP
nCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nRWE <= 1'b1;
// Don't care bank, RA[11:8]
BA <= 2'b00;
RA[11:8] <= 4'b0000;
// Latch row address for next video read
RA[7:0] <= Ain[7:0];
// Mask everything
DQML <= 1'b1;
DQMH <= 1'b1;
// Enable data bus output
DOEEN <= 1'b1;
end else if (S==4'hF) begin
// Disable clock
CKE <= 1'b0;
// NOP
nCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nRWE <= 1'b1;
// Don't care bank, RA[11:8]
BA <= 2'b00;
RA[11:8] <= 4'b0000;
// Latch row address for next video read
RA[7:0] <= Ain[7:0];
// Mask everything
DQML <= 1'b1;
DQMH <= 1'b1;
// Enable data bus output
DOEEN <= 1'b1;
end
end
always @(negedge C14M) begin
// Latch video and read data outputs
if (S==4'h6) Vout[7:0] <= RD[7:0];
if (S==4'hC) Dout[7:0] <= RD[7:0];
end
endmodule

110
CPLD/RAM2E.v
View File

@ -19,72 +19,74 @@ module RAM2E(C14M, PHI1, LED,
reg [3:0] S = 0;
reg PHI1r = 0; always @(posedge C14M) PHI1r <= PHI1;
always @(posedge C14M) begin
S <= (PHI1 && !PHI1r && Ready) ? 4'h1 :
S <= (PHI1 && !PHI1r && Ready) ? 4'h1 :
(S==4'h0) ? 4'h0 :
(S==4'hF) ? 4'hF : S+4'h1;
end
/* Refresh counter */
reg [2:0] RC;
wire RefReq = RC==0;
always @(posedge C14M) begin
if (S==4'h1) begin
if (RC[2] && RC[1]) RC <= 0; // RC==6 || RC==7
else RC <= RC+3'h1;
end
reg RefReq;
always @(negedge PHI1) begin
if (RC[2] && RC[1]) RC <= 0; // RC==6 || RC==7
else RC <= RC+3'h1;
RefReq <= RC==0;
end
/* Activity LED */
wire LEDEN;
output LED; assign LED = !(!nEN80 && LEDEN && Ready);
/* Address Bus */
input [7:0] Ain; // Multiplexed DRAM address input
/* DRAM multiplexed address bus input */
input [7:0] Ain;
/* 6502 Data Bus */
input [7:0] Din; // 6502 data bus inputs
/* 6502 data bus input/output */
input [7:0] Din;
reg DOEEN;
always @(posedge C14M) begin
DOEEN <= /*(S==4'h8) || (S==4'h9) || (S==4'hA) ||*/ (S==4'hB) ||
(S==4'hC) || (S==4'hD) || (S==4'hE) || (S==4'hF);
DOEEN <= S==4'hB || S==4'hC || S==4'hD || S==4'hE || S==4'hF;
end
output nDOE; assign nDOE = !(!nEN80 && nWE && DOEEN);
output [7:0] Dout; assign Dout[7:0] = RD[7:0];
/* Video Data Bus */
reg VOEEN;
always @(posedge C14M) begin
VOEEN <= (S==4'h7) ||
(S==4'h8) || (S==4'h9) || (S==4'hA) || (S==4'hB) ||
(S==4'hC) || (S==4'hD) || (S==4'hE) || (S==4'hF);
reg VOE;
always @(negedge C14M) begin
VOE <= S==4'h7 || S==4'h8 || S==4'h9 || S==4'hA || S==4'hB || S==4'hC;
end
output nVOE; assign nVOE = !(!PHI1 && VOEEN);
output nVOE; assign nVOE = !VOE;
output reg [7:0] Vout; // Video data bus
always @(posedge C14M) if (S==4'h6) Vout[7:0] <= RD[7:0];
always @(negedge C14M) if (S==4'h6) Vout[7:0] <= RD[7:0];
/* SDRAM bus */
reg CKE = 1;
reg nRAS = 1, nCAS = 1, nRWE = 1;
reg CKE = 1, nRAS = 1, nCAS = 1, nRWE = 1;
output reg [1:0] BA;
reg [11:0] RA;
output reg DQML = 1, DQMH = 1;
inout [7:0] RD;
wire [7:0] RDout = Ready ? Din[7:0] : 8'h00;
wire RDOE = (!Ready) || (!nEN80 && !nWE);
reg RDOE;
always @(posedge C14M) begin
RDOE <= (!Ready) || (!nEN80 && !nWE && (S==4'hA || S==4'hB));
end
assign RD[7:0] = RDOE ? RDout[7:0] : 8'bZ;
/* SDRAM falling edge outputs */
output reg CKEout;
/* SDRAM falling edge command outputs */
output nCSout; assign nCSout = 0;
output reg nRASout = 1, nCASout = 1, nRWEout = 1;
output reg [11:0] RAout;
output reg CKEout = 1, nRASout = 1, nCASout = 1, nRWEout = 1;
always @(negedge C14M) begin
CKEout <= CKE;
nRASout <= nRAS;
nCASout <= nCAS;
nRWEout <= nRWE;
RAout <= RA;
end
/* SDRAM address outputs */
output [11:0] RAout;
reg [11:0] RAr; always @(negedge C14M) RAr <= RA;
reg RAT; always @(negedge C14M) RAT <= S==4'hA;
assign RAout[11:8] = RAr[11:8];
assign RAout[7:0] = RAT ? Ain[7:0] : RAr[7:0];
/* RAMWorks Bank Register and Capacity Mask */
reg [7:0] RWBank = 0; // RAMWorks bank register
@ -94,7 +96,6 @@ module RAM2E(C14M, PHI1, LED,
if (S==4'h9) RWSel <= RA[0] && !RA[3] && !nWE && !nC07X;
end
reg CmdRWMaskSet = 0; // RAMWorks Mask register set flag
wire CmdSetRWBankFFChip;
reg CmdSetRWBankFFLED = 0;
reg CmdLEDSet = 0;
reg CmdLEDGet = 0;
@ -103,14 +104,6 @@ module RAM2E(C14M, PHI1, LED,
reg [2:0] CS = 0; // Command sequence state
reg [2:0] CmdTout = 0; // Command sequence timeout
/* Chip-specific UFM interface */
RAM2E_UFM ram2e_ufm (
.C14M(C14M), .S(S), .FS(FS), .CS(CS), .Ready(Ready),
.RWSel(RWSel), .D(Din),
.RWMask(RWMask), .LEDEN(LEDEN),
.CmdRWMaskSet(CmdRWMaskSet), .CmdLEDSet(CmdLEDSet),
.CmdSetRWBankFFChip(CmdSetRWBankFFChip));
/* Command sequence control */
always @(posedge C14M) begin
if (S==4'hC) begin
@ -133,7 +126,17 @@ module RAM2E(C14M, PHI1, LED,
end
end
/* Chip-specific UFM interface */
wire [7:0] ChipCmdNum;
RAM2E_UFM ram2e_ufm (
.C14M(C14M), .S(S), .FS(FS), .CS(CS),
.RWSel(RWSel), .D(Din),
.RWMask(RWMask), .LEDEN(LEDEN),
.CmdRWMaskSet(CmdRWMaskSet), .CmdLEDSet(CmdLEDSet),
.ChipCmdNum(ChipCmdNum));
/* RAMWorks register control - bank, LED, etc. */
reg CmdSetRWBankFFChip;
always @(posedge C14M) begin
if (S==4'hC && RWSel) begin
// Latch RAMWorks bank if accessed
@ -142,15 +145,16 @@ module RAM2E(C14M, PHI1, LED,
else RWBank <= Din[7:0] & {RWMask[7], ~RWMask[6:0]};
if (CS==3'h6) begin // Recognize and submit command in CS6
// LED detect command
CmdSetRWBankFFLED <= Din[7:0]==8'hF0;
// Volatile commands
CmdSetRWBankFFLED <= Din[7:0]==8'hF0;
CmdRWMaskSet <= Din[7:0]==8'hE0;
CmdLEDSet <= Din[7:0]==8'hE2;
CmdLEDGet <= Din[7:0]==8'hE3;
// Chip detection command
CmdSetRWBankFFChip <= Din[7:0]==ChipCmdNum[7:0];
// LED exists detect command
CmdSetRWBankFFLED <= Din[7:0]==8'hF0;
// Volatile settings commands
CmdRWMaskSet <= Din[7:0]==8'hE0;
CmdLEDSet <= Din[7:0]==8'hE2;
CmdLEDGet <= Din[7:0]==8'hE3;
end else begin // Reset command triggers
CmdSetRWBankFFChip <= 0;
CmdSetRWBankFFLED <= 0;
CmdRWMaskSet <= 0;
CmdLEDSet <= 0;
@ -212,10 +216,10 @@ module RAM2E(C14M, PHI1, LED,
nRWE <= 1'b0;
end
endcase
BA[1:0] <= 2'b00;
case (FS[4:3])
2'b00, 2'b01: begin
// Mode register contents
BA[1:0] <= 2'b00; // Reserved
RA[11] <= 1'b0; // Reserved
RA[10] <= !FS[1]; // reserved / "all"
RA[9] <= 1'b1; // "1" for single write mode
@ -225,11 +229,9 @@ module RAM2E(C14M, PHI1, LED,
RA[3] <= 1'b0; // "0" for sequential burst (not used)
RA[2:0] <= 3'b000; // "0" for burst length 1 (no burst)
end 2'b10: begin
BA[1:0] <= 2'b00;
RA[11:8] <= 4'h0;
RA[7:0] <= FS[14:7];
end 2'b11: begin
BA[1:0] <= 2'b00;
RA[11:3] <= 9'h000;
RA[2:1] <= FS[6:5];
RA[0] <= FS[1];
@ -282,9 +284,8 @@ module RAM2E(C14M, PHI1, LED,
nRWE <= 1'b0;
end
// Hold BA
// Hold RA[11]
// Hold RA[11,9:0]
RA[10] <= 1'b1; // "all"
// Hold RA[9:0]
// Hold DQMs
end 4'h5: begin
if (RefReq) begin // Refresh request
@ -370,7 +371,7 @@ module RAM2E(C14M, PHI1, LED,
// Hold BA
RA[11:9] <= 3'b000; // no auto-precharge
RA[8] <= RWBank[7];
RA[7:0] <= Ain[7:0];
// RA[7:0] is transparent
DQML <= RWBank[0];
DQMH <= !RWBank[0];
end 4'hA: begin
@ -397,7 +398,8 @@ module RAM2E(C14M, PHI1, LED,
RA[10] <= 1'b0; // no auto-precharge
end
// Hold BA
// Hold RA[11,9:0]
// Hold RA[11,9:8]
RA[7:0] <= Ain[7:0];
// Hold DQMs
end 4'hB: begin
if (nEN80) begin // Idle
@ -429,14 +431,14 @@ module RAM2E(C14M, PHI1, LED,
nRAS <= 1'b1;
nCAS <= 1'b1;
nRWE <= 1'b1;
RA[10] <= 1'b0;
// Hold RA[10]
end else if (nWE) begin // Read
// NOP CKD
CKE <= 1'b0;
nRAS <= 1'b1;
nCAS <= 1'b1;
nRWE <= 1'b1;
RA[10] <= 1'b1;
// Hold RA[10]
end else begin // Write
// PC all CKD
CKE <= 1'b0;

39
CPLD/UFM-LCMXO2.v
View File

@ -1,32 +1,31 @@
module RAM2E_UFM(C14M, S, FS, CS, Ready,
module RAM2E_UFM(C14M, S, FS, CS,
RWSel, D,
RWMask, LEDEN,
CmdRWMaskSet, CmdLEDSet,
CmdSetRWBankFFChip);
ChipCmdNum);
input C14M;
input [3:0] S;
input [15:0] FS;
input [2:0] CS;
input Ready;
input [2:0] CS;
input RWSel;
input [7:0] D;
output reg [7:0] RWMask;
output reg LEDEN;
input CmdRWMaskSet;
input CmdLEDSet;
output reg CmdSetRWBankFFChip;
/* Chip ID */
//output [7:0] ChipCmdNum; assign ChipCmdNum[7:0] = 8'hFF; // MAX
//output [7:0] ChipCmdNum; assign ChipCmdNum[7:0] = 8'hFE; // SPI
output [7:0] ChipCmdNum; assign ChipCmdNum[7:0] = 8'hFD; // MachXO2
/* RAMWorks register control - Lattice MachXO2 */
reg CmdBitbangMXO2 = 0;
reg CmdExecMXO2 = 0;
always @(posedge C14M) begin
if (S==4'hC && RWSel) begin
if (CS==3'h6) begin // Recognize and submit command in CS6
// Chip detection commands
//CmdSetRWBankFFChip <= D[7:0]==8'hFF; // MAX
//CmdSetRWBankFFChip <= D[7:0]==8'hFE; // SPI
CmdSetRWBankFFChip <= D[7:0]==8'hFD; // MachXO2
// Altera MAX II/V commands
//CmdBitbangMAX <= D[7:0]==8'hEA;
//if (!CmdEraseMAX && !CmdPrgmMAX) begin
@ -41,7 +40,6 @@ module RAM2E_UFM(C14M, S, FS, CS, Ready,
CmdBitbangMXO2 <= D[7:0]==8'hEC;
CmdExecMXO2 <= D[7:0]==8'hED;
end else begin // Reset command triggers
CmdSetRWBankFFChip <= 0;
CmdBitbangMXO2 <= 0;
CmdExecMXO2 <= 0;
end
@ -85,22 +83,22 @@ module RAM2E_UFM(C14M, S, FS, CS, Ready,
wb_adr[7:0] <= 8'h70;
wb_dati[7:0] <= 8'h80;
wb_req <= 1;
end 1: begin // Enable configuration interface - command
end 1: begin // Enable config interface - command
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h71;
wb_dati[7:0] <= 8'h74;
wb_req <= 1;
end 2: begin // Enable configuration interface - operand 1/3
end 2: begin // Enable config interface - operand 1/3
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h71;
wb_dati[7:0] <= 8'h08;
wb_req <= 1;
end 3: begin // Enable configuration interface - operand 2/3
end 3: begin // Enable config interface - operand 2/3
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h71;
wb_dati[7:0] <= 8'h00;
wb_req <= 1;
end 4: begin // Enable configuration interface - operand 3/3
end 4: begin // Enable config interface - operand 3/3
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h71;
wb_dati[7:0] <= 8'h00;
@ -254,17 +252,17 @@ module RAM2E_UFM(C14M, S, FS, CS, Ready,
wb_adr[7:0] <= 8'h70;
wb_dati[7:0] <= 8'h80;
wb_req <= 1;
end 49: begin // Disable configuration interface - command
end 49: begin // Disable config interface - command
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h71;
wb_dati[7:0] <= 8'h26;
wb_req <= 1;
end 50: begin // Disable configuration interface - operand 1/2
end 50: begin // Disable config interface - operand 1/2
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h71;
wb_dati[7:0] <= 8'h00;
wb_req <= 1;
end 51: begin // Disable configuration interface - operand 2/2
end 51: begin // Disable config interface - operand 2/2
wb_we <= 1'b1;
wb_adr[7:0] <= 8'h71;
wb_dati[7:0] <= 8'h00;
@ -310,13 +308,16 @@ module RAM2E_UFM(C14M, S, FS, CS, Ready,
wb_rst <= 1'b0;
wb_req <= 1'b0;
// Volatile settings command execution
if (RWSel && S==4'hC) begin
// LED control
if (CmdLEDSet) LEDEN <= D[0];
// Set capacity mask
if (CmdRWMaskSet) RWMask[7:0] <= {D[7], ~D[6:0]};
end
// EFB commands
if (RWSel && S==4'hC) begin
// Set EFB address
if (CmdBitbangMXO2) begin
wb_adr[7:0] <= D[7:0];

27
CPLD/UFM-MAX.v
View File

@ -1,20 +1,23 @@
module RAM2E_UFM(C14M, S, FS, CS, Ready,
module RAM2E_UFM(C14M, S, FS, CS,
RWSel, D,
RWMask, LEDEN,
CmdRWMaskSet, CmdLEDSet,
CmdSetRWBankFFChip);
ChipCmdNum);
input C14M;
input [3:0] S;
input [15:0] FS;
input [2:0] CS;
input Ready;
input RWSel;
input [7:0] D;
output reg [7:0] RWMask;
output reg LEDEN;
input CmdRWMaskSet;
input CmdLEDSet;
output reg CmdSetRWBankFFChip;
/* Chip ID */
output [7:0] ChipCmdNum; assign ChipCmdNum[7:0] = 8'hFF; // MAX
//output [7:0] ChipCmdNum; assign ChipCmdNum[7:0] = 8'hFE; // SPI
//output [7:0] ChipCmdNum; assign ChipCmdNum[7:0] = 8'hFD; // MachXO2
/* RAMWorks register control - Altera MAX */
reg CmdBitbangMAX = 0; // Set by user command. Loads UFM outputs next RWSel
@ -23,11 +26,6 @@ module RAM2E_UFM(C14M, S, FS, CS, Ready,
always @(posedge C14M) begin
if (S==4'hC && RWSel) begin
if (CS==3'h6) begin // Recognize and submit command in CS6
// Chip detection commands
CmdSetRWBankFFChip <= D[7:0]==8'hFF; // MAX
//CmdSetRWBankFFChip <= D[7:0]==8'hFE; // SPI
//CmdSetRWBankFFChip <= D[7:0]==8'hFD; // MachXO2
// Altera MAX II/V commands
CmdBitbangMAX <= D[7:0]==8'hEA;
if (!CmdEraseMAX && !CmdPrgmMAX) begin
@ -42,12 +40,12 @@ module RAM2E_UFM(C14M, S, FS, CS, Ready,
//CmdBitbangMXO2 <= D[7:0]==8'hEC;
//CmdExecMXO2 <= D[7:0]==8'hED;
end else begin // Reset command triggers
CmdSetRWBankFFChip <= 0;
CmdBitbangMAX <= 0;
end
end
end
/* UFM Interface */
reg [15:8] UFMD = 0; // *Parallel* UFM data register
reg ARCLK = 0; // UFM address register clock
@ -87,7 +85,8 @@ module RAM2E_UFM(C14M, S, FS, CS, Ready,
reg UFMProgStart;
always @(posedge C14M) begin
if (S==4'h0) begin
if ((FS[15:13]==3'b101) || (FS[15:13]==3'b111 && UFMReqErase)) begin
if ((FS[15:13]==3'b101) ||
(FS[15:13]==3'b111 && UFMReqErase)) begin
// In states AXXX-BXXX and also EXXX-FXXX if erase/wrap req'd
// shift in 0's to address register
ARCLK <= FS[0]; // Clock address register
@ -95,7 +94,8 @@ module RAM2E_UFM(C14M, S, FS, CS, Ready,
ARShift <= 1'b1; // Shift address registers
DRDIn <= 1'b0; // Don't care DRDIn
DRShift <= 1'b0; // Don't care DRDShift
end else if (!UFMInitDone && FS[15:13]==3'b110 && FS[4:1]==4'h4) begin
end else if (!UFMInitDone &&
FS[15:13]==3'b110 && FS[4:1]==4'h4) begin
// In states CXXX-DXXX (substep 4)
// Xfer to data reg (repeat 256x 1x)
ARCLK <= 1'b0; // Don't clock address register
@ -103,7 +103,8 @@ module RAM2E_UFM(C14M, S, FS, CS, Ready,
ARShift <= 1'b0; // Don't care ARShift
DRDIn <= 1'b0; // Don't care DRDIn
DRShift <= 1'b0; // Don't care DRShift
end else if (!UFMInitDone && FS[15:13]==3'b110 && (FS[4:1]==4'h7 || FS[4]==1'b1)) begin
end else if (!UFMInitDone &&
FS[15:13]==3'b110 && (FS[4:1]==4'h7 || FS[4]==1'b1)) begin
// In states CXXX-DXXX (substeps 8-F)
// Save UFM D15-8, shift out D14-7 (repeat 256x 8x)
DRCLK <= FS[0]; // Clock data register

38
Documentation/Timing.json Normal file
View File

@ -0,0 +1,38 @@
{signal: [
{name: 'C14M', wave: 'p................', phase: 0.00, period: 1},
{name: 'State', wave: '22222222222222222', phase: 0.00, period: 1,
data:['D/F','E/F','1','2','3','4','5','6','7','8','9','A','B','C','D','E','1']},
{name: 'PHI0', wave: '10......1......0.', phase: 0.00, period: 1},
{name: '/RAS', wave: '1.0....1.0....1.0', phase: 0.00, period: 1},
{name: '/CAS', wave: '1...0...1..0...1.', phase: 0.00, period: 1},
{name: '/Q3', wave: '1....0..1...0..1.', phase: 0.00, period: 1},
{name: 'RA[7:0]', wave: '2.x2.xx2...xx2..x2.xx2...xx2..x2.x', phase: 0.00, period: 0.5,
data:['crow','vrow','vcol','vrow','crow','ccol','crow','vrow']},
{},
{name: 'CKE (idle)', wave: '0..1..0..10......', phase: 0.00, period: 1},
{name: 'Cmd (idle)', wave: '22222222222222222', phase: 0.00, period: 1,
data:[ 'NOP','NOP','NOP',
'NOP','ACT','RD','PCa','NOP','NOP','NOP','NOP','NOP','NOP','NOP','NOP','NOP','NOP']},
{name: 'CKE (idle)', wave: '0..1....010......', phase: 0.00, period: 1},
{name: 'Cmd (idle)', wave: '22222222222222222', phase: 0.00, period: 1,
data:[ 'NOP','NOP','NOP',
'NOP','ACT','RD','PCa','REF','NOP','NOP','NOP','NOP','NOP','NOP','NOP','NOP','NOP']},
{},
{name: 'CKE (read)', wave: '0..1..0..1..0....', phase: 0.00, period: 1},
{name: 'Cmd (read)', wave: '22222222222222222', phase: 0.00, period: 1,
data:[ 'NOP','NOP','NOP',
'NOP','ACT','RD','PCa','NOP','NOP','NOP','ACT','RD','PCa','NOP','NOP','NOP','NOP']},
{name: 'CKE (read)', wave: '0..1....01..0....', phase: 0.00, period: 1},
{name: 'Cmd (read)', wave: '22222222222222222', phase: 0.00, period: 1,
data:[ 'NOP','NOP','NOP',
'NOP','ACT','RD','PCa','REF','NOP','NOP','ACT','RD','PCa','NOP','NOP','NOP','NOP']},
{},
{name: 'CKE (write)', wave: '0..1..0..101..0..', phase: 0.00, period: 1},
{name: 'Cmd (write)', wave: '22222222222222222', phase: 0.00, period: 1,
data:[ 'NOP','NOP','NOP',
'NOP','ACT','RD','PCa','NOP','NOP','NOP','ACT','NOP','WR','NOP','PCa','NOP','NOP']},
{name: 'CKE (write)', wave: '0..1....0101..0..', phase: 0.00, period: 1},
{name: 'Cmd (write)', wave: '22222222222222222', phase: 0.00, period: 1,
data:[ 'NOP','NOP','NOP',
'NOP','ACT','RD','PCa','REF','NOP','NOP','ACT','NOP','WR','NOP','PCa','NOP','NOP']},
]}

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5
Hardware/LCMXO2/BOM/RAM2E-BOM.LCMXO2HC.csv
View File

@ -17,7 +17,8 @@ R7 ,1,DNP,stdpads:R_0805,,,,
R5 R8 R9 R11 ,4,10k,stdpads:R_0603,,C25804,Uniroyal 0603WAF1002T5E,Any manufacturer's part is acceptable.
U1 ,1,LCMXO2-TG100,stdpads:TQFP-100_14x14mm_P0.5mm,,C1519051,"Lattice LCMXO2-640HC-4TG100C, Lattice LCMXO2-640HC-5TG100C, Lattice LCMXO2-640HC-6TG100C, Lattice LCMXO2-640HC-4TG100I, Lattice LCMXO2-640HC-5TG100I, Lattice LCMXO2-640HC-6TG100I, Lattice LCMXO2-1200HC-4TG100C, Lattice LCMXO2-1200HC-5TG100C, Lattice LCMXO2-1200HC-6TG100C, Lattice LCMXO2-1200HC-4TG100I, Lattice LCMXO2-1200HC-5TG100I, Lattice LCMXO2-1200HC-6TG100I",
U2 ,1,W9812G6KH-6,stdpads:TSOP-II-54_22.2x10.16mm_P0.8mm,,C62379,"Winbond W9812G6KH-6, Winbond W9812G6KH-6I, Winbond W9825G6KH-6, Winbond W9825G6KH-6I, ISSI IS42S16160J-6TL, ISSI IS42S16160J-6TLI, Micron MT48LC16M16A2P-6A :G, Micron MT48LC16M16A2P-6A IT:G",Most 166 MHz 128/256 Mbit x16 SDRAM is acceptable.
U3 U4 U5 ,3,74LVC245APW,stdpads:TSSOP-20_4.4x6.5mm_P0.65mm,,C6082,"NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI 74AHC245PW",Most 74LVC245 or 74AHC245 in TSSOP-20 package is acceptable.
U4 ,1,74LVC245APW,stdpads:TSSOP-20_4.4x6.5mm_P0.65mm,,C6082,"NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI 74AHC245PW",Most 74LVC245 or 74AHC245 in TSSOP-20 package is acceptable.
U3 U5 ,2,74AHC245PW,stdpads:TSSOP-20_4.4x6.5mm_P0.65mm,,C6082,"NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI 74AHC245PW",Most 74LVC245 or 74AHC245 in TSSOP-20 package is acceptable.
U6 U7 ,2,74AHCT245PW,stdpads:TSSOP-20_4.4x6.5mm_P0.65mm,,C173388,"NXP 74AHCT245PW, NXP 74AHCT245APW, TI SN74AHCT245PW",Most 74AHCT245 in TSSOP-20 package is acceptable.
U8 ,1,XC6206P332MR,stdpads:SOT-23,,C5446,Torex XC6206P332MR,Most 3.3V regulator in SOT-23 package is acceptable.
U9 ,1,DNP,stdpads:SOT-23-5,,,,
U9 ,1,DNP,stdpads:SOT-23-5,,,,

1 Reference Quantity Value Footprint Datasheet LCSC Part Mfg. Part Numbers Notes
17 R5 R8 R9 R11 4 10k stdpads:R_0603 C25804 Uniroyal 0603WAF1002T5E Any manufacturer's part is acceptable.
18 U1 1 LCMXO2-TG100 stdpads:TQFP-100_14x14mm_P0.5mm C1519051 Lattice LCMXO2-640HC-4TG100C, Lattice LCMXO2-640HC-5TG100C, Lattice LCMXO2-640HC-6TG100C, Lattice LCMXO2-640HC-4TG100I, Lattice LCMXO2-640HC-5TG100I, Lattice LCMXO2-640HC-6TG100I, Lattice LCMXO2-1200HC-4TG100C, Lattice LCMXO2-1200HC-5TG100C, Lattice LCMXO2-1200HC-6TG100C, Lattice LCMXO2-1200HC-4TG100I, Lattice LCMXO2-1200HC-5TG100I, Lattice LCMXO2-1200HC-6TG100I
19 U2 1 W9812G6KH-6 stdpads:TSOP-II-54_22.2x10.16mm_P0.8mm C62379 Winbond W9812G6KH-6, Winbond W9812G6KH-6I, Winbond W9825G6KH-6, Winbond W9825G6KH-6I, ISSI IS42S16160J-6TL, ISSI IS42S16160J-6TLI, Micron MT48LC16M16A2P-6A :G, Micron MT48LC16M16A2P-6A IT:G Most 166 MHz 128/256 Mbit x16 SDRAM is acceptable.
20 U3 U4 U5 U4 3 1 74LVC245APW stdpads:TSSOP-20_4.4x6.5mm_P0.65mm C6082 NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI 74AHC245PW Most 74LVC245 or 74AHC245 in TSSOP-20 package is acceptable.
21 U3 U5 2 74AHC245PW stdpads:TSSOP-20_4.4x6.5mm_P0.65mm C6082 NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI 74AHC245PW Most 74LVC245 or 74AHC245 in TSSOP-20 package is acceptable.
22 U6 U7 2 74AHCT245PW stdpads:TSSOP-20_4.4x6.5mm_P0.65mm C173388 NXP 74AHCT245PW, NXP 74AHCT245APW, TI SN74AHCT245PW Most 74AHCT245 in TSSOP-20 package is acceptable.
23 U8 1 XC6206P332MR stdpads:SOT-23 C5446 Torex XC6206P332MR Most 3.3V regulator in SOT-23 package is acceptable.
24 U9 1 DNP stdpads:SOT-23-5

5
Hardware/LCMXO2/BOM/RAM2E-BOM.LCMXO2HE.csv
View File

@ -17,7 +17,8 @@ R7 ,1,DNP,stdpads:R_0805,,,,
R5 R8 R9 R11 ,4,10k,stdpads:R_0603,,C25804,Uniroyal 0603WAF1002T5E,Any manufacturer's part is acceptable.
U1 ,1,LCMXO2-TG100,stdpads:TQFP-100_14x14mm_P0.5mm,,C1519051,"Lattice LCMXO2-640HE-4TG100C, Lattice LCMXO2-640HE-5TG100C, Lattice LCMXO2-640HE-6TG100C, Lattice LCMXO2-640HE-4TG100I, Lattice LCMXO2-640HE-5TG100I, Lattice LCMXO2-640HE-6TG100I, Lattice LCMXO2-1200HE-4TG100C, Lattice LCMXO2-1200HE-5TG100C, Lattice LCMXO2-1200HE-6TG100C, Lattice LCMXO2-1200HE-4TG100I, Lattice LCMXO2-1200HE-5TG100I, Lattice LCMXO2-1200HE-6TG100I",
U2 ,1,W9812G6KH-6,stdpads:TSOP-II-54_22.2x10.16mm_P0.8mm,,C62379,"Winbond W9812G6KH-6, Winbond W9812G6KH-6I, Winbond W9825G6KH-6, Winbond W9825G6KH-6I, ISSI IS42S16160J-6TL, ISSI IS42S16160J-6TLI, Micron MT48LC16M16A2P-6A :G, Micron MT48LC16M16A2P-6A IT:G",Most 166 MHz 128/256 Mbit x16 SDRAM is acceptable.
U3 U4 U5 ,3,74LVC245APW,stdpads:TSSOP-20_4.4x6.5mm_P0.65mm,,C6082,"NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI 74AHC245PW",Most 74LVC245 or 74AHC245 in TSSOP-20 package is acceptable.
U4 ,1,74LVC245APW,stdpads:TSSOP-20_4.4x6.5mm_P0.65mm,,C6082,"NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI 74AHC245PW",Most 74LVC245 or 74AHC245 in TSSOP-20 package is acceptable.
U3 U5 ,2,74AHC245PW,stdpads:TSSOP-20_4.4x6.5mm_P0.65mm,,C6082,"NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI 74AHC245PW",Most 74LVC245 or 74AHC245 in TSSOP-20 package is acceptable.
U6 U7 ,2,74AHCT245PW,stdpads:TSSOP-20_4.4x6.5mm_P0.65mm,,C173388,"NXP 74AHCT245PW, NXP 74AHCT245APW, TI SN74AHCT245PW",Most 74AHCT245 in TSSOP-20 package is acceptable.
U8 ,1,XC6206P332MR,stdpads:SOT-23,,C5446,Torex XC6206P332MR,Most 3.3V regulator in SOT-23 package is acceptable.
U9 ,1,AP2127K-1.2TRG1,stdpads:SOT-23-5,,C151376,"Diodes AP2127K-1.2TRG1, Torex XC6228D122VR",Most 1.2V regulator in SOT-23-5 package is acceptable.
U9 ,1,AP2127K-1.2TRG1,stdpads:SOT-23-5,,C151376,"Diodes AP2127K-1.2TRG1, Torex XC6228D122VR",Most 1.2V regulator in SOT-23-5 package is acceptable.

1 Reference Quantity Value Footprint Datasheet LCSC Part Mfg. Part Numbers Notes
17 R5 R8 R9 R11 4 10k stdpads:R_0603 C25804 Uniroyal 0603WAF1002T5E Any manufacturer's part is acceptable.
18 U1 1 LCMXO2-TG100 stdpads:TQFP-100_14x14mm_P0.5mm C1519051 Lattice LCMXO2-640HE-4TG100C, Lattice LCMXO2-640HE-5TG100C, Lattice LCMXO2-640HE-6TG100C, Lattice LCMXO2-640HE-4TG100I, Lattice LCMXO2-640HE-5TG100I, Lattice LCMXO2-640HE-6TG100I, Lattice LCMXO2-1200HE-4TG100C, Lattice LCMXO2-1200HE-5TG100C, Lattice LCMXO2-1200HE-6TG100C, Lattice LCMXO2-1200HE-4TG100I, Lattice LCMXO2-1200HE-5TG100I, Lattice LCMXO2-1200HE-6TG100I
19 U2 1 W9812G6KH-6 stdpads:TSOP-II-54_22.2x10.16mm_P0.8mm C62379 Winbond W9812G6KH-6, Winbond W9812G6KH-6I, Winbond W9825G6KH-6, Winbond W9825G6KH-6I, ISSI IS42S16160J-6TL, ISSI IS42S16160J-6TLI, Micron MT48LC16M16A2P-6A :G, Micron MT48LC16M16A2P-6A IT:G Most 166 MHz 128/256 Mbit x16 SDRAM is acceptable.
20 U3 U4 U5 U4 3 1 74LVC245APW stdpads:TSSOP-20_4.4x6.5mm_P0.65mm C6082 NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI 74AHC245PW Most 74LVC245 or 74AHC245 in TSSOP-20 package is acceptable.
21 U3 U5 2 74AHC245PW stdpads:TSSOP-20_4.4x6.5mm_P0.65mm C6082 NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI 74AHC245PW Most 74LVC245 or 74AHC245 in TSSOP-20 package is acceptable.
22 U6 U7 2 74AHCT245PW stdpads:TSSOP-20_4.4x6.5mm_P0.65mm C173388 NXP 74AHCT245PW, NXP 74AHCT245APW, TI SN74AHCT245PW Most 74AHCT245 in TSSOP-20 package is acceptable.
23 U8 1 XC6206P332MR stdpads:SOT-23 C5446 Torex XC6206P332MR Most 3.3V regulator in SOT-23 package is acceptable.
24 U9 1 AP2127K-1.2TRG1 stdpads:SOT-23-5 C151376 Diodes AP2127K-1.2TRG1, Torex XC6228D122VR Most 1.2V regulator in SOT-23-5 package is acceptable.

BIN
Hardware/LCMXO2/Documentation/RAM2E.4203B.LCMXO2-Placement 2.pdf
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Hardware/LCMXO2/Documentation/RAM2E.4203B.LCMXO2-Placement.pdf
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Hardware/LCMXO2/Documentation/RAM2E.4203B.LCMXO2-Schematic 2.pdf
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Hardware/LCMXO2/RAM2E.kicad_pcb
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Hardware/LCMXO2/RAM2E.kicad_sch
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@ -5034,7 +5034,7 @@
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(effects (font (size 1.27 1.27)))
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(property "Value" "74LVC245APW" (at 76.2 53.34 0)
(property "Value" "74AHC245PW" (at 76.2 53.34 0)
(effects (font (size 1.27 1.27)))
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(property "Footprint" "stdpads:TSSOP-20_4.4x6.5mm_P0.65mm" (at 76.2 54.61 0)
@ -5043,7 +5043,7 @@
(property "Datasheet" "" (at 76.2 35.56 0)
(effects (font (size 1.524 1.524)) hide)
)
(property "LCSC Part" "C6082" (at 76.2 38.1 0)
(property "LCSC Part" "C5516" (at 76.2 38.1 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Mfg. Part Numbers" "NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI 74AHC245PW" (at 76.2 38.1 0)
@ -5087,7 +5087,7 @@
(property "Reference" "U5" (at 76.2 88.9 0)
(effects (font (size 1.27 1.27)))
)
(property "Value" "74LVC245APW" (at 76.2 119.38 0)
(property "Value" "74AHC245PW" (at 76.2 119.38 0)
(effects (font (size 1.27 1.27)))
)
(property "Footprint" "stdpads:TSSOP-20_4.4x6.5mm_P0.65mm" (at 76.2 120.65 0)
@ -5096,7 +5096,7 @@
(property "Datasheet" "" (at 76.2 101.6 0)
(effects (font (size 1.524 1.524)) hide)
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(property "LCSC Part" "C6082" (at 76.2 104.14 0)
(property "LCSC Part" "C5516" (at 76.2 104.14 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Mfg. Part Numbers" "NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI 74AHC245PW" (at 76.2 104.14 0)

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Hardware/LCMXO2/gerber/RAM2E-B_Cu.gbl
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Hardware/LCMXO2/gerber/RAM2E-B_Mask.gbs
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Hardware/LCMXO2/gerber/RAM2E-Edge_Cuts.gm1
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@ -1,11 +1,11 @@
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G04 #@! TF.CreationDate,2023-10-30T17:31:41-04:00*
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,7.0.10*
G04 #@! TF.CreationDate,2024-02-07T20:48:26-05:00*
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Hardware/LCMXO2/gerber/RAM2E-F_Paste.gtp
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@ -1,12 +1,12 @@
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G04 #@! TF.ProjectId,RAM2E,52414d32-452e-46b6-9963-61645f706362,2.1*
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G04 Created by KiCad (PCBNEW 7.0.10) date 2024-02-07 20:48:26*
%MOMM*%
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@ -29,26 +29,26 @@ G04 Aperture macros list*
20,1,$1+$1,$6,$7,$8,$9,0*
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G04 Aperture macros list end*
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2850
Hardware/LCMXO2/gerber/RAM2E-F_Silkscreen.gto
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Hardware/LCMXO2/gerber/RAM2E-In1_Cu.g2
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Hardware/LCMXO2/gerber/RAM2E-In2_Cu.g3
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Hardware/LCMXO2/gerber/RAM2E-job.gbrjob
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@ -3,9 +3,9 @@
"GenerationSoftware": {
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"Version": "7.0.10"
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},
"GeneralSpecs": {
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4
Hardware/LCMXO2/gerber/RAM2E-top-pos.JUMPER.csv
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@ -49,9 +49,9 @@ Ref,Val,Package,MidX,MidY,Rotation,Side
"R13","47","R_0603",228.000000,-118.550000,-90.000000,top
"U1","LCMXO2-TG100","TQFP-100_14x14mm_P0.5mm",240.050000,-108.350000,90.000000,top
"U2","W9812G6KH-6","TSOP-II-54_22.2x10.16mm_P0.8mm",218.800000,-105.450000,-90.000000,top
"U3","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",220.775000,-124.600000,0.000000,top
"U3","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",220.775000,-124.600000,0.000000,top
"U4","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",229.975000,-124.600000,0.000000,top
"U5","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",239.175000,-124.600000,0.000000,top
"U5","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",239.175000,-124.600000,0.000000,top
"U6","74AHCT245PW","TSSOP-20_4.4x6.5mm_P0.65mm",248.375000,-124.600000,0.000000,top
"U7","74AHCT245PW","TSSOP-20_4.4x6.5mm_P0.65mm",257.575000,-124.600000,0.000000,top
"U8","XC6206P332MR","SOT-23",267.650000,-110.800000,180.000000,top

1 Ref Val Package MidX MidY Rotation Side
49 R13 47 R_0603 228.000000 -118.550000 -90.000000 top
50 U1 LCMXO2-TG100 TQFP-100_14x14mm_P0.5mm 240.050000 -108.350000 90.000000 top
51 U2 W9812G6KH-6 TSOP-II-54_22.2x10.16mm_P0.8mm 218.800000 -105.450000 -90.000000 top
52 U3 74LVC245APW 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 220.775000 -124.600000 0.000000 top
53 U4 74LVC245APW TSSOP-20_4.4x6.5mm_P0.65mm 229.975000 -124.600000 0.000000 top
54 U5 74LVC245APW 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 239.175000 -124.600000 0.000000 top
55 U6 74AHCT245PW TSSOP-20_4.4x6.5mm_P0.65mm 248.375000 -124.600000 0.000000 top
56 U7 74AHCT245PW TSSOP-20_4.4x6.5mm_P0.65mm 257.575000 -124.600000 0.000000 top
57 U8 XC6206P332MR SOT-23 267.650000 -110.800000 180.000000 top

4
Hardware/LCMXO2/gerber/RAM2E-top-pos.VCORE.csv
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@ -48,9 +48,9 @@ Ref,Val,Package,MidX,MidY,Rotation,Side
"R13","47","R_0603",228.000000,-118.550000,-90.000000,top
"U1","LCMXO2-TG100","TQFP-100_14x14mm_P0.5mm",240.050000,-108.350000,90.000000,top
"U2","W9812G6KH-6","TSOP-II-54_22.2x10.16mm_P0.8mm",218.800000,-105.450000,-90.000000,top
"U3","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",220.775000,-124.600000,0.000000,top
"U3","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",220.775000,-124.600000,0.000000,top
"U4","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",229.975000,-124.600000,0.000000,top
"U5","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",239.175000,-124.600000,0.000000,top
"U5","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",239.175000,-124.600000,0.000000,top
"U6","74AHCT245PW","TSSOP-20_4.4x6.5mm_P0.65mm",248.375000,-124.600000,0.000000,top
"U7","74AHCT245PW","TSSOP-20_4.4x6.5mm_P0.65mm",257.575000,-124.600000,0.000000,top
"U8","XC6206P332MR","SOT-23",267.650000,-110.800000,180.000000,top

1 Ref Val Package MidX MidY Rotation Side
48 R13 47 R_0603 228.000000 -118.550000 -90.000000 top
49 U1 LCMXO2-TG100 TQFP-100_14x14mm_P0.5mm 240.050000 -108.350000 90.000000 top
50 U2 W9812G6KH-6 TSOP-II-54_22.2x10.16mm_P0.8mm 218.800000 -105.450000 -90.000000 top
51 U3 74LVC245APW 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 220.775000 -124.600000 0.000000 top
52 U4 74LVC245APW TSSOP-20_4.4x6.5mm_P0.65mm 229.975000 -124.600000 0.000000 top
53 U5 74LVC245APW 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 239.175000 -124.600000 0.000000 top
54 U6 74AHCT245PW TSSOP-20_4.4x6.5mm_P0.65mm 248.375000 -124.600000 0.000000 top
55 U7 74AHCT245PW TSSOP-20_4.4x6.5mm_P0.65mm 257.575000 -124.600000 0.000000 top
56 U8 XC6206P332MR SOT-23 267.650000 -110.800000 180.000000 top

4
Hardware/LCMXO2/gerber/RAM2E-top-pos.csv
View File

@ -49,9 +49,9 @@ Ref,Val,Package,MidX,MidY,Rotation,Side
"R13","47","R_0603",228.000000,-118.550000,-90.000000,top
"U1","LCMXO2-TG100","TQFP-100_14x14mm_P0.5mm",240.050000,-108.350000,90.000000,top
"U2","W9812G6KH-6","TSOP-II-54_22.2x10.16mm_P0.8mm",218.800000,-105.450000,-90.000000,top
"U3","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",220.775000,-124.600000,0.000000,top
"U3","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",220.775000,-124.600000,0.000000,top
"U4","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",229.975000,-124.600000,0.000000,top
"U5","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",239.175000,-124.600000,0.000000,top
"U5","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",239.175000,-124.600000,0.000000,top
"U6","74AHCT245PW","TSSOP-20_4.4x6.5mm_P0.65mm",248.375000,-124.600000,0.000000,top
"U7","74AHCT245PW","TSSOP-20_4.4x6.5mm_P0.65mm",257.575000,-124.600000,0.000000,top
"U8","XC6206P332MR","SOT-23",267.650000,-110.800000,180.000000,top

1 Ref Val Package MidX MidY Rotation Side
49 R13 47 R_0603 228.000000 -118.550000 -90.000000 top
50 U1 LCMXO2-TG100 TQFP-100_14x14mm_P0.5mm 240.050000 -108.350000 90.000000 top
51 U2 W9812G6KH-6 TSOP-II-54_22.2x10.16mm_P0.8mm 218.800000 -105.450000 -90.000000 top
52 U3 74LVC245APW 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 220.775000 -124.600000 0.000000 top
53 U4 74LVC245APW TSSOP-20_4.4x6.5mm_P0.65mm 229.975000 -124.600000 0.000000 top
54 U5 74LVC245APW 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 239.175000 -124.600000 0.000000 top
55 U6 74AHCT245PW TSSOP-20_4.4x6.5mm_P0.65mm 248.375000 -124.600000 0.000000 top
56 U7 74AHCT245PW TSSOP-20_4.4x6.5mm_P0.65mm 257.575000 -124.600000 0.000000 top
57 U8 XC6206P332MR SOT-23 267.650000 -110.800000 180.000000 top

BIN
Hardware/LCMXO2/gerber/RAM2E.4203B.LCMXO2-gerber 2.zip
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Hardware/LCMXO2/gerber/RAM2E.4203B.LCMXO2-gerber.zip
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1033
Hardware/LCMXO2/gerber/RAM2E.drl
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5
Hardware/MAX/BOM/RAM2E-BOM.MAXII.csv
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@ -16,7 +16,8 @@ R8 ,1,220,stdpads:R_0805,,C17557,Uniroyal 0805W8F2200T5E,Any manufacturer's part
R9 R10 ,2,22k,stdpads:R_0805,,C17560,Uniroyal 0805W8F2202T5E,Any manufacturer's part is acceptable.
U1 ,1,EPM240T100,stdpads:TQFP-100_14x14mm_P0.5mm,,C10041,"Altera EPM240T100C5N, Altera EPM240T100C4N, Altera EPM240T100C3N, Altera EPM240T100I5N, Altera EPM240T100I4N, Altera EPM240T100A5N, Altera EPM240T100A4N",
U2 ,1,W9812G6KH-6,stdpads:TSOP-II-54_22.2x10.16mm_P0.8mm,,C62379,"Winbond W9812G6KH-6, Winbond W9812G6KH-6I, Winbond W9825G6KH-6, Winbond W9825G6KH-6I, ISSI IS42S16160J-6TL, ISSI IS42S16160J-6TLI, Micron MT48LC16M16A2P-6A :G, Micron MT48LC16M16A2P-6A IT:G",Most 166 MHz 128/256 Mbit x16 SDRAM is acceptable.
U3 U4 U5 ,3,74LVC245APW,stdpads:TSSOP-20_4.4x6.5mm_P0.65mm,,C6082,"NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI SN74AHC245PW",Most 74LVC245 or 74AHC245 in TSSOP-20 package is acceptable.
U4 ,1,74LVC245APW,stdpads:TSSOP-20_4.4x6.5mm_P0.65mm,,C6082,"NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI SN74AHC245PW",Most 74LVC245 or 74AHC245 in TSSOP-20 package is acceptable.
U3 U5 ,2,74AHC245PW,stdpads:TSSOP-20_4.4x6.5mm_P0.65mm,,C5516,"NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI SN74AHC245PW",Most 74LVC245 or 74AHC245 in TSSOP-20 package is acceptable.
U6 U7 ,2,74AHCT245PW,stdpads:TSSOP-20_4.4x6.5mm_P0.65mm,,C173388,"NXP 74AHCT245PW, NXP 74AHCT245APW, TI SN74AHCT245PW",Most 74AHCT245 in TSSOP-20 package is acceptable.
U8 ,1,XC6206P332MR,stdpads:SOT-23,,C5446,Torex XC6206P332MR,Most 3.3V regulator in SOT-23 package is acceptable.
U9 ,1,AP2127K-1.8TRG1,stdpads:SOT-23-5,,C151375,"Diodes AP2127K-1.8TRG1, Torex XC6228D182VR",Most 1.8V regulator in SOT-23-5 package is acceptable.
U9 ,1,DNP,stdpads:SOT-23-5,,,,

1 Reference Quantity Value Footprint Datasheet LCSC Part Mfg. Part Numbers Notes
16 R9 R10 2 22k stdpads:R_0805 C17560 Uniroyal 0805W8F2202T5E Any manufacturer's part is acceptable.
17 U1 1 EPM240T100 stdpads:TQFP-100_14x14mm_P0.5mm C10041 Altera EPM240T100C5N, Altera EPM240T100C4N, Altera EPM240T100C3N, Altera EPM240T100I5N, Altera EPM240T100I4N, Altera EPM240T100A5N, Altera EPM240T100A4N
18 U2 1 W9812G6KH-6 stdpads:TSOP-II-54_22.2x10.16mm_P0.8mm C62379 Winbond W9812G6KH-6, Winbond W9812G6KH-6I, Winbond W9825G6KH-6, Winbond W9825G6KH-6I, ISSI IS42S16160J-6TL, ISSI IS42S16160J-6TLI, Micron MT48LC16M16A2P-6A :G, Micron MT48LC16M16A2P-6A IT:G Most 166 MHz 128/256 Mbit x16 SDRAM is acceptable.
19 U3 U4 U5 U4 3 1 74LVC245APW stdpads:TSSOP-20_4.4x6.5mm_P0.65mm C6082 NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI SN74AHC245PW Most 74LVC245 or 74AHC245 in TSSOP-20 package is acceptable.
20 U3 U5 2 74AHC245PW stdpads:TSSOP-20_4.4x6.5mm_P0.65mm C5516 NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI SN74AHC245PW Most 74LVC245 or 74AHC245 in TSSOP-20 package is acceptable.
21 U6 U7 2 74AHCT245PW stdpads:TSSOP-20_4.4x6.5mm_P0.65mm C173388 NXP 74AHCT245PW, NXP 74AHCT245APW, TI SN74AHCT245PW Most 74AHCT245 in TSSOP-20 package is acceptable.
22 U8 1 XC6206P332MR stdpads:SOT-23 C5446 Torex XC6206P332MR Most 3.3V regulator in SOT-23 package is acceptable.
23 U9 1 AP2127K-1.8TRG1 DNP stdpads:SOT-23-5 C151375 Diodes AP2127K-1.8TRG1, Torex XC6228D182VR Most 1.8V regulator in SOT-23-5 package is acceptable.

5
Hardware/MAX/BOM/RAM2E-BOM.MAXV.csv
View File

@ -16,7 +16,8 @@ R8 ,1,220,stdpads:R_0805,,C17557,Uniroyal 0805W8F2200T5E,Any manufacturer's part
R9 R10 ,2,22k,stdpads:R_0805,,C17560,Uniroyal 0805W8F2202T5E,Any manufacturer's part is acceptable.
U1 ,1,5M240ZT100,stdpads:TQFP-100_14x14mm_P0.5mm,,C10041,"Altera 5M240ZT100C5N, Altera 5M240ZT100C4N, Altera 5M240ZT100C3N, Altera 5M240ZT100I5N, Altera 5M240ZT100I4N, Altera 5M240ZT100A5N, Altera 5M240ZT100A4N",
U2 ,1,W9812G6KH-6,stdpads:TSOP-II-54_22.2x10.16mm_P0.8mm,,C62379,"Winbond W9812G6KH-6, Winbond W9812G6KH-6I, Winbond W9825G6KH-6, Winbond W9825G6KH-6I, ISSI IS42S16160J-6TL, ISSI IS42S16160J-6TLI, Micron MT48LC16M16A2P-6A :G, Micron MT48LC16M16A2P-6A IT:G",Most 166 MHz 128/256 Mbit x16 SDRAM is acceptable.
U3 U4 U5 ,3,74LVC245APW,stdpads:TSSOP-20_4.4x6.5mm_P0.65mm,,C6082,"NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI SN74AHC245PW",Most 74LVC245 or 74AHC245 in TSSOP-20 package is acceptable.
U4 ,1,74LVC245APW,stdpads:TSSOP-20_4.4x6.5mm_P0.65mm,,C6082,"NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI SN74AHC245PW",Most 74LVC245 or 74AHC245 in TSSOP-20 package is acceptable.
U3 U5 ,2,74AHC245PW,stdpads:TSSOP-20_4.4x6.5mm_P0.65mm,,C5516,"NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI SN74AHC245PW",Most 74LVC245 or 74AHC245 in TSSOP-20 package is acceptable.
U6 U7 ,2,74AHCT245PW,stdpads:TSSOP-20_4.4x6.5mm_P0.65mm,,C173388,"NXP 74AHCT245PW, NXP 74AHCT245APW, TI SN74AHCT245PW",Most 74AHCT245 in TSSOP-20 package is acceptable.
U8 ,1,XC6206P332MR,stdpads:SOT-23,,C5446,Torex XC6206P332MR,Most 3.3V regulator in SOT-23 package is acceptable.
U9 ,1,AP2127K-1.8TRG1,stdpads:SOT-23-5,,C151375,"Diodes AP2127K-1.8TRG1, Torex XC6228D182VR",Most 1.8V regulator in SOT-23-5 package is acceptable.
U9 ,1,AP2127K-1.8TRG1,stdpads:SOT-23-5,,C151375,"Diodes AP2127K-1.8TRG1, Torex XC6228D182VR",Most 1.8V regulator in SOT-23-5 package is acceptable.

1 Reference Quantity Value Footprint Datasheet LCSC Part Mfg. Part Numbers Notes
16 R9 R10 2 22k stdpads:R_0805 C17560 Uniroyal 0805W8F2202T5E Any manufacturer's part is acceptable.
17 U1 1 5M240ZT100 stdpads:TQFP-100_14x14mm_P0.5mm C10041 Altera 5M240ZT100C5N, Altera 5M240ZT100C4N, Altera 5M240ZT100C3N, Altera 5M240ZT100I5N, Altera 5M240ZT100I4N, Altera 5M240ZT100A5N, Altera 5M240ZT100A4N
18 U2 1 W9812G6KH-6 stdpads:TSOP-II-54_22.2x10.16mm_P0.8mm C62379 Winbond W9812G6KH-6, Winbond W9812G6KH-6I, Winbond W9825G6KH-6, Winbond W9825G6KH-6I, ISSI IS42S16160J-6TL, ISSI IS42S16160J-6TLI, Micron MT48LC16M16A2P-6A :G, Micron MT48LC16M16A2P-6A IT:G Most 166 MHz 128/256 Mbit x16 SDRAM is acceptable.
19 U3 U4 U5 U4 3 1 74LVC245APW stdpads:TSSOP-20_4.4x6.5mm_P0.65mm C6082 NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI SN74AHC245PW Most 74LVC245 or 74AHC245 in TSSOP-20 package is acceptable.
20 U3 U5 2 74AHC245PW stdpads:TSSOP-20_4.4x6.5mm_P0.65mm C5516 NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI SN74AHC245PW Most 74LVC245 or 74AHC245 in TSSOP-20 package is acceptable.
21 U6 U7 2 74AHCT245PW stdpads:TSSOP-20_4.4x6.5mm_P0.65mm C173388 NXP 74AHCT245PW, NXP 74AHCT245APW, TI SN74AHCT245PW Most 74AHCT245 in TSSOP-20 package is acceptable.
22 U8 1 XC6206P332MR stdpads:SOT-23 C5446 Torex XC6206P332MR Most 3.3V regulator in SOT-23 package is acceptable.
23 U9 1 AP2127K-1.8TRG1 stdpads:SOT-23-5 C151375 Diodes AP2127K-1.8TRG1, Torex XC6228D182VR Most 1.8V regulator in SOT-23-5 package is acceptable.

BIN
Hardware/MAX/Documentation/RAM2E.4203B.MAX-Placement.pdf
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Hardware/MAX/Documentation/RAM2E.4203B.MAX-Schematic.pdf
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51752
Hardware/MAX/RAM2E.kicad_pcb
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6
Hardware/MAX/RAM2E.kicad_pro
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@ -517,12 +517,8 @@
},
"sheets": [
[
"0dd11af3-0465-4c84-bbb0-f3ae16a77316",
"ca91ccfe-7a99-4124-b7c6-e1f3ffab8bf1",
""
],
[
"00000000-0000-0000-0000-00005e93a857",
"Docs"
]
],
"text_variables": {}

8
Hardware/MAX/RAM2E.kicad_sch
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@ -4969,7 +4969,7 @@
(property "Reference" "U3" (at 76.2 22.86 0)
(effects (font (size 1.27 1.27)))
)
(property "Value" "74LVC245APW" (at 76.2 53.34 0)
(property "Value" "74AHC245PW" (at 76.2 53.34 0)
(effects (font (size 1.27 1.27)))
)
(property "Footprint" "stdpads:TSSOP-20_4.4x6.5mm_P0.65mm" (at 76.2 54.61 0)
@ -4978,7 +4978,7 @@
(property "Datasheet" "" (at 76.2 35.56 0)
(effects (font (size 1.524 1.524)) hide)
)
(property "LCSC Part" "C6082" (at 76.2 38.1 0)
(property "LCSC Part" "C5516" (at 76.2 38.1 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Mfg. Part Numbers" "NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI SN74AHC245PW" (at 76.2 38.1 0)
@ -5022,7 +5022,7 @@
(property "Reference" "U5" (at 76.2 88.9 0)
(effects (font (size 1.27 1.27)))
)
(property "Value" "74LVC245APW" (at 76.2 119.38 0)
(property "Value" "74AHC245PW" (at 76.2 119.38 0)
(effects (font (size 1.27 1.27)))
)
(property "Footprint" "stdpads:TSSOP-20_4.4x6.5mm_P0.65mm" (at 76.2 120.65 0)
@ -5031,7 +5031,7 @@
(property "Datasheet" "" (at 76.2 101.6 0)
(effects (font (size 1.524 1.524)) hide)
)
(property "LCSC Part" "C6082" (at 76.2 104.14 0)
(property "LCSC Part" "C5516" (at 76.2 104.14 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "Mfg. Part Numbers" "NXP 74LVC245APW, TI SN74LVC245APW, NXP 74AHC245PW, NXP 74AHC245APW, TI SN74AHC245PW" (at 76.2 104.14 0)

10596
Hardware/MAX/gerber/RAM2E-B_Cu.gbl
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2158
Hardware/MAX/gerber/RAM2E-B_Mask.gbs
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Hardware/MAX/gerber/RAM2E-B_Silkscreen.gbo
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6
Hardware/MAX/gerber/RAM2E-Edge_Cuts.gm1
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@ -1,11 +1,11 @@
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,7.0.1-0*
G04 #@! TF.CreationDate,2023-10-30T17:31:38-04:00*
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,7.0.10*
G04 #@! TF.CreationDate,2024-02-07T20:48:24-05:00*
G04 #@! TF.ProjectId,RAM2E,52414d32-452e-46b6-9963-61645f706362,2.1*
G04 #@! TF.SameCoordinates,Original*
G04 #@! TF.FileFunction,Profile,NP*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 7.0.1-0) date 2023-10-30 17:31:38*
G04 Created by KiCad (PCBNEW 7.0.10) date 2024-02-07 20:48:24*
%MOMM*%
%LPD*%
G01*

22950
Hardware/MAX/gerber/RAM2E-F_Cu.gtl
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15541
Hardware/MAX/gerber/RAM2E-F_Mask.gts
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44
Hardware/MAX/gerber/RAM2E-F_Paste.gtp
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@ -1,12 +1,12 @@
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,7.0.1-0*
G04 #@! TF.CreationDate,2023-10-30T17:31:38-04:00*
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,7.0.10*
G04 #@! TF.CreationDate,2024-02-07T20:48:24-05:00*
G04 #@! TF.ProjectId,RAM2E,52414d32-452e-46b6-9963-61645f706362,2.1*
G04 #@! TF.SameCoordinates,Original*
G04 #@! TF.FileFunction,Paste,Top*
G04 #@! TF.FilePolarity,Positive*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 7.0.1-0) date 2023-10-30 17:31:38*
G04 Created by KiCad (PCBNEW 7.0.10) date 2024-02-07 20:48:24*
%MOMM*%
%LPD*%
G01*
@ -29,25 +29,25 @@ G04 Aperture macros list*
20,1,$1+$1,$6,$7,$8,$9,0*
20,1,$1+$1,$8,$9,$2,$3,0*%
G04 Aperture macros list end*
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%ADD26RoundRect,0.125000X-0.300000X0.175000X-0.300000X-0.175000X0.300000X-0.175000X0.300000X0.175000X0*%
%ADD27RoundRect,0.125000X-0.175000X-0.300000X0.175000X-0.300000X0.175000X0.300000X-0.175000X0.300000X0*%
%ADD28RoundRect,0.205650X0.243750X0.456250X-0.243750X0.456250X-0.243750X-0.456250X0.243750X-0.456250X0*%
%ADD10RoundRect,0.092500X0.092500X-0.592500X0.092500X0.592500X-0.092500X0.592500X-0.092500X-0.592500X0*%
%ADD11RoundRect,0.192500X-0.242500X0.192500X-0.242500X-0.192500X0.242500X-0.192500X0.242500X0.192500X0*%
%ADD12RoundRect,0.192500X0.242500X-0.192500X0.242500X0.192500X-0.242500X0.192500X-0.242500X-0.192500X0*%
%ADD13RoundRect,0.192500X-0.192500X-0.242500X0.192500X-0.242500X0.192500X0.242500X-0.192500X0.242500X0*%
%ADD14RoundRect,0.099500X-0.625500X-0.099500X0.625500X-0.099500X0.625500X0.099500X-0.625500X0.099500X0*%
%ADD15RoundRect,0.192500X0.192500X0.242500X-0.192500X0.242500X-0.192500X-0.242500X0.192500X-0.242500X0*%
%ADD16RoundRect,0.057500X-0.645000X-0.057500X0.645000X-0.057500X0.645000X0.057500X-0.645000X0.057500X0*%
%ADD17RoundRect,0.057500X-0.057500X-0.645000X0.057500X-0.645000X0.057500X0.645000X-0.057500X0.645000X0*%
%ADD18RoundRect,0.250000X0.250000X0.425000X-0.250000X0.425000X-0.250000X-0.425000X0.250000X-0.425000X0*%
%ADD19RoundRect,0.250000X-0.425000X0.250000X-0.425000X-0.250000X0.425000X-0.250000X0.425000X0.250000X0*%
%ADD20RoundRect,0.200000X-0.200000X-0.475000X0.200000X-0.475000X0.200000X0.475000X-0.200000X0.475000X0*%
%ADD21RoundRect,0.200000X0.200000X0.475000X-0.200000X0.475000X-0.200000X-0.475000X0.200000X-0.475000X0*%
%ADD22RoundRect,0.250000X0.425000X-0.250000X0.425000X0.250000X-0.425000X0.250000X-0.425000X-0.250000X0*%
%ADD23RoundRect,0.175000X-0.450000X-0.175000X0.450000X-0.175000X0.450000X0.175000X-0.450000X0.175000X0*%
%ADD24RoundRect,0.137500X0.487500X0.137500X-0.487500X0.137500X-0.487500X-0.137500X0.487500X-0.137500X0*%
%ADD25RoundRect,0.200000X0.475000X-0.200000X0.475000X0.200000X-0.475000X0.200000X-0.475000X-0.200000X0*%
%ADD26RoundRect,0.150000X-0.275000X0.150000X-0.275000X-0.150000X0.275000X-0.150000X0.275000X0.150000X0*%
%ADD27RoundRect,0.150000X-0.150000X-0.275000X0.150000X-0.275000X0.150000X0.275000X-0.150000X0.275000X0*%
%ADD28RoundRect,0.224700X0.224700X0.437200X-0.224700X0.437200X-0.224700X-0.437200X0.224700X-0.437200X0*%
G04 APERTURE END LIST*
D10*
X236250000Y-127550000D03*

2848
Hardware/MAX/gerber/RAM2E-F_Silkscreen.gto
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6322
Hardware/MAX/gerber/RAM2E-In1_Cu.g2
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11930
Hardware/MAX/gerber/RAM2E-In2_Cu.g3
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4
Hardware/MAX/gerber/RAM2E-job.gbrjob
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@ -3,9 +3,9 @@
"GenerationSoftware": {
"Vendor": "KiCad",
"Application": "Pcbnew",
"Version": "7.0.1-0"
"Version": "7.0.10"
},
"CreationDate": "2023-10-30T17:31:38-04:00"
"CreationDate": "2024-02-07T20:48:24-05:00"
},
"GeneralSpecs": {
"ProjectId": {

4
Hardware/MAX/gerber/RAM2E-top-pos.JUMPER.csv
View File

@ -44,9 +44,9 @@ Ref,Val,Package,MidX,MidY,Rotation,Side
"R10","22k","R_0805",207.264000,-108.077000,180.000000,top
"U1","EPM240T100","TQFP-100_14x14mm_P0.5mm",240.050000,-108.350000,-90.000000,top
"U2","W9812G6KH-6","TSOP-II-54_22.2x10.16mm_P0.8mm",218.800000,-105.450000,-90.000000,top
"U3","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",220.775000,-124.600000,0.000000,top
"U3","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",220.775000,-124.600000,0.000000,top
"U4","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",229.975000,-124.600000,0.000000,top
"U5","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",239.175000,-124.600000,0.000000,top
"U5","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",239.175000,-124.600000,0.000000,top
"U6","74AHCT245PW","TSSOP-20_4.4x6.5mm_P0.65mm",248.375000,-124.600000,0.000000,top
"U7","74AHCT245PW","TSSOP-20_4.4x6.5mm_P0.65mm",257.575000,-124.600000,0.000000,top
"U8","XC6206P332MR","SOT-23",267.650000,-110.800000,180.000000,top

1 Ref Val Package MidX MidY Rotation Side
44 R10 22k R_0805 207.264000 -108.077000 180.000000 top
45 U1 EPM240T100 TQFP-100_14x14mm_P0.5mm 240.050000 -108.350000 -90.000000 top
46 U2 W9812G6KH-6 TSOP-II-54_22.2x10.16mm_P0.8mm 218.800000 -105.450000 -90.000000 top
47 U3 74LVC245APW 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 220.775000 -124.600000 0.000000 top
48 U4 74LVC245APW TSSOP-20_4.4x6.5mm_P0.65mm 229.975000 -124.600000 0.000000 top
49 U5 74LVC245APW 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 239.175000 -124.600000 0.000000 top
50 U6 74AHCT245PW TSSOP-20_4.4x6.5mm_P0.65mm 248.375000 -124.600000 0.000000 top
51 U7 74AHCT245PW TSSOP-20_4.4x6.5mm_P0.65mm 257.575000 -124.600000 0.000000 top
52 U8 XC6206P332MR SOT-23 267.650000 -110.800000 180.000000 top

4
Hardware/MAX/gerber/RAM2E-top-pos.VCORE.csv
View File

@ -43,9 +43,9 @@ Ref,Val,Package,MidX,MidY,Rotation,Side
"R10","22k","R_0805",207.264000,-108.077000,180.000000,top
"U1","EPM240T100","TQFP-100_14x14mm_P0.5mm",240.050000,-108.350000,-90.000000,top
"U2","W9812G6KH-6","TSOP-II-54_22.2x10.16mm_P0.8mm",218.800000,-105.450000,-90.000000,top
"U3","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",220.775000,-124.600000,0.000000,top
"U3","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",220.775000,-124.600000,0.000000,top
"U4","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",229.975000,-124.600000,0.000000,top
"U5","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",239.175000,-124.600000,0.000000,top
"U5","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",239.175000,-124.600000,0.000000,top
"U6","74AHCT245PW","TSSOP-20_4.4x6.5mm_P0.65mm",248.375000,-124.600000,0.000000,top
"U7","74AHCT245PW","TSSOP-20_4.4x6.5mm_P0.65mm",257.575000,-124.600000,0.000000,top
"U8","XC6206P332MR","SOT-23",267.650000,-110.800000,180.000000,top

1 Ref Val Package MidX MidY Rotation Side
43 R10 22k R_0805 207.264000 -108.077000 180.000000 top
44 U1 EPM240T100 TQFP-100_14x14mm_P0.5mm 240.050000 -108.350000 -90.000000 top
45 U2 W9812G6KH-6 TSOP-II-54_22.2x10.16mm_P0.8mm 218.800000 -105.450000 -90.000000 top
46 U3 74LVC245APW 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 220.775000 -124.600000 0.000000 top
47 U4 74LVC245APW TSSOP-20_4.4x6.5mm_P0.65mm 229.975000 -124.600000 0.000000 top
48 U5 74LVC245APW 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 239.175000 -124.600000 0.000000 top
49 U6 74AHCT245PW TSSOP-20_4.4x6.5mm_P0.65mm 248.375000 -124.600000 0.000000 top
50 U7 74AHCT245PW TSSOP-20_4.4x6.5mm_P0.65mm 257.575000 -124.600000 0.000000 top
51 U8 XC6206P332MR SOT-23 267.650000 -110.800000 180.000000 top

4
Hardware/MAX/gerber/RAM2E-top-pos.csv
View File

@ -44,9 +44,9 @@ Ref,Val,Package,MidX,MidY,Rotation,Side
"R10","22k","R_0805",207.264000,-108.077000,180.000000,top
"U1","EPM240T100","TQFP-100_14x14mm_P0.5mm",240.050000,-108.350000,-90.000000,top
"U2","W9812G6KH-6","TSOP-II-54_22.2x10.16mm_P0.8mm",218.800000,-105.450000,-90.000000,top
"U3","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",220.775000,-124.600000,0.000000,top
"U3","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",220.775000,-124.600000,0.000000,top
"U4","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",229.975000,-124.600000,0.000000,top
"U5","74LVC245APW","TSSOP-20_4.4x6.5mm_P0.65mm",239.175000,-124.600000,0.000000,top
"U5","74AHC245PW","TSSOP-20_4.4x6.5mm_P0.65mm",239.175000,-124.600000,0.000000,top
"U6","74AHCT245PW","TSSOP-20_4.4x6.5mm_P0.65mm",248.375000,-124.600000,0.000000,top
"U7","74AHCT245PW","TSSOP-20_4.4x6.5mm_P0.65mm",257.575000,-124.600000,0.000000,top
"U8","XC6206P332MR","SOT-23",267.650000,-110.800000,180.000000,top

1 Ref Val Package MidX MidY Rotation Side
44 R10 22k R_0805 207.264000 -108.077000 180.000000 top
45 U1 EPM240T100 TQFP-100_14x14mm_P0.5mm 240.050000 -108.350000 -90.000000 top
46 U2 W9812G6KH-6 TSOP-II-54_22.2x10.16mm_P0.8mm 218.800000 -105.450000 -90.000000 top
47 U3 74LVC245APW 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 220.775000 -124.600000 0.000000 top
48 U4 74LVC245APW TSSOP-20_4.4x6.5mm_P0.65mm 229.975000 -124.600000 0.000000 top
49 U5 74LVC245APW 74AHC245PW TSSOP-20_4.4x6.5mm_P0.65mm 239.175000 -124.600000 0.000000 top
50 U6 74AHCT245PW TSSOP-20_4.4x6.5mm_P0.65mm 248.375000 -124.600000 0.000000 top
51 U7 74AHCT245PW TSSOP-20_4.4x6.5mm_P0.65mm 257.575000 -124.600000 0.000000 top
52 U8 XC6206P332MR SOT-23 267.650000 -110.800000 180.000000 top

BIN
Hardware/MAX/gerber/RAM2E.4203B.MAX-gerber.zip
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1109
Hardware/MAX/gerber/RAM2E.drl
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1
Makefile
View File

@ -51,6 +51,7 @@ Hardware/MAX/gerber Hardware/LCMXO2/gerber:
cp $(F_POS) $(F_POS_JUMPER)
sed -i '' '/"R1"/d' $(F_POS_VCORE)
sed -i '' '/"U9"/d' $(F_POS_JUMPER)
rm -f $(F_ZIP)
zip -r $(F_ZIP) $@/
Hardware/MAX/Documentation Hardware/LCMXO2/Documentation:
mkdir -p $@