This commit is contained in:
Zane Kaminski 2023-12-28 23:24:48 -05:00
parent e73d7034d8
commit 1bbca43cfd
58 changed files with 329 additions and 300 deletions

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@ -59,6 +59,23 @@ prj_project open "//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200H
<A name="pn231228231137"></A><B><U><big>pn231228231137</big></U></B>
#Start recording tcl command: 12/26/2023 23:38:54
#Project Location: //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC; Project name: RAM2E_LCMXO2_1200HC
prj_project open "//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC.ldf"
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1 -forceAll
prj_run Export -impl impl1 -forceAll
prj_run Export -impl impl1 -forceAll
prj_run Export -impl impl1 -forceAll
prj_run Export -impl impl1 -forceAll
prj_run Export -impl impl1 -forceAll
prj_run Export -impl impl1
#Stop recording: 12/28/2023 23:11:37
<BR>
<BR>
<BR>

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@ -1,6 +1,6 @@
NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
NOTE All Rights Reserved *
NOTE DATE CREATED: Thu Dec 28 23:10:34 2023 *
NOTE DATE CREATED: Thu Dec 28 23:24:00 2023 *
NOTE DESIGN NAME: RAM2E *
NOTE DEVICE NAME: LCMXO2-1200HC-4TQFP100 *
NOTE PIN ASSIGNMENTS *

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@ -4,7 +4,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Thu Dec 28 23:10:30 2023
Thu Dec 28 23:23:57 2023
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC -w -jedec -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1.ncd RAM2E_LCMXO2_1200HC_impl1.prf
@ -82,5 +82,5 @@ Available General Purpose Flash Memory: 511 Pages (Page 0 to Page 510).
Initialized UFM Pages: 321 Pages (Page 190 to Page 510).
Total CPU Time: 3 secs
Total REAL Time: 4 secs
Total REAL Time: 3 secs
Peak Memory Usage: 275 MB

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@ -4,7 +4,7 @@
(keywordMap (keywordLevel 0))
(status
(written
(timeStamp 2023 12 28 23 9 53)
(timeStamp 2023 12 28 23 23 26)
(author "Synopsys, Inc.")
(program "Synplify Pro" (version "R-2021.03L-SP1, mapper map202103lat, Build 070R"))
)

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@ -2,7 +2,7 @@
NOTE Diamond (64-bit) 3.12.1.454 JEDEC Compatible Fuse File.*
NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation.*
NOTE All Rights Reserved.*
NOTE DATE CREATED: Thu Dec 28 23:10:30 2023*
NOTE DATE CREATED: Thu Dec 28 23:23:57 2023*
NOTE DESIGN NAME: RAM2E_LCMXO2_1200HC_impl1.ncd*
NOTE DEVICE NAME: LCMXO2-1200HC-4TQFP100*
NOTE JEDEC FILE STATUS: Final Version 1.95*
@ -2781,4 +2781,4 @@ E0000000000000000000000000000000000000000000000000000000000000000
0000010001100000*
NOTE User Electronic Signature Data*
UH00000000*
C84F
C85C

View File

@ -15,7 +15,7 @@ Target Vendor: LATTICE
Target Device: LCMXO2-1200HCTQFP100
Target Performance: 4
Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454
Mapped on: 12/28/23 23:09:57
Mapped on: 12/28/23 23:23:27
Design Summary
--------------
@ -66,7 +66,7 @@ Design Summary
Design: RAM2E Date: 12/28/23 23:09:57
Design: RAM2E Date: 12/28/23 23:23:27
Design Summary (cont)
---------------------
@ -132,7 +132,7 @@ WARNING - map: IO buffer missing for top level port nWE80...logic will be
Design: RAM2E Date: 12/28/23 23:09:57
Design: RAM2E Date: 12/28/23 23:23:27
IO (PIO) Attributes
@ -198,7 +198,7 @@ IO (PIO) Attributes
Design: RAM2E Date: 12/28/23 23:09:57
Design: RAM2E Date: 12/28/23 23:23:27
IO (PIO) Attributes (cont)
--------------------------
@ -264,7 +264,7 @@ IO (PIO) Attributes (cont)
Design: RAM2E Date: 12/28/23 23:09:57
Design: RAM2E Date: 12/28/23 23:23:27
IO (PIO) Attributes (cont)
--------------------------
@ -330,7 +330,7 @@ Signal ram2e_ufm/ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
Design: RAM2E Date: 12/28/23 23:09:57
Design: RAM2E Date: 12/28/23 23:23:27
Removed logic (cont)
--------------------
@ -396,7 +396,7 @@ Embedded Functional Block Connection Summary
Design: RAM2E Date: 12/28/23 23:09:57
Design: RAM2E Date: 12/28/23 23:23:27
Embedded Functional Block Connection Summary (cont)
---------------------------------------------------
@ -443,7 +443,7 @@ Instance Name: ram2e_ufm/ufmefb/EFBInst_0
Run Time and Memory Usage
-------------------------
Total CPU Time: 1 secs
Total CPU Time: 0 secs
Total REAL Time: 0 secs
Peak Memory Usage: 64 MB

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@ -6,7 +6,7 @@ Performance Grade: 4
PACKAGE: TQFP100
Package Status: Final Version 1.44
Thu Dec 28 23:10:10 2023
Thu Dec 28 23:23:38 2023
Pinout by Port Name:
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
@ -309,5 +309,5 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Thu Dec 28 23:10:13 2023
Thu Dec 28 23:23:42 2023

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@ -1,5 +1,5 @@
SCHEMATIC START ;
# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Thu Dec 28 23:09:58 2023
# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Thu Dec 28 23:23:28 2023
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
LOCATE COMP "RD[0]" SITE "36" ;

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@ -3,7 +3,7 @@
#OS: Windows 8 6.2
#Hostname: ZANEMACWIN11
# Thu Dec 28 23:09:45 2023
# Thu Dec 28 23:23:19 2023
#Implementation: impl1
@ -52,6 +52,8 @@ Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 202
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v" (library work)
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\REFB.v" (library work)
Verilog syntax check successful!
File \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v changed - recompiling
File \\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v changed - recompiling
Selecting top level module RAM2E
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
Running optimization stage 1 on VHI .......
@ -73,7 +75,7 @@ Running optimization stage 1 on RAM2E .......
Finished optimization stage 1 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB)
Running optimization stage 2 on RAM2E .......
@N: CL159 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v":11:15:11:19|Input nWE80 is unused.
Finished optimization stage 2 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
Finished optimization stage 2 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB)
Running optimization stage 2 on RAM2E_UFM .......
@N: CL159 :"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v":10:7:10:11|Input Ready is unused.
Finished optimization stage 2 on RAM2E_UFM (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
@ -91,7 +93,7 @@ At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Dec 28 23:09:45 2023
# Thu Dec 28 23:23:19 2023
###########################################################]
###########################################################[
@ -112,13 +114,14 @@ Implementation : impl1
Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
@N|Running in 64-bit mode
File \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\layer0.srs changed - recompiling
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Dec 28 23:09:46 2023
# Thu Dec 28 23:23:20 2023
###########################################################]
@ -128,12 +131,12 @@ For a summary of runtime and memory usage for all design units, please see file:
@END
At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 30MB peak: 31MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Dec 28 23:09:46 2023
# Thu Dec 28 23:23:20 2023
###########################################################]
###########################################################[
@ -156,15 +159,15 @@ Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug
@N|Running in 64-bit mode
File \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_comp.srs changed - recompiling
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Dec 28 23:09:47 2023
# Thu Dec 28 23:23:21 2023
###########################################################]
# Thu Dec 28 23:09:47 2023
# Thu Dec 28 23:23:21 2023
Copyright (C) 1994-2021 Synopsys, Inc.
@ -183,10 +186,10 @@ Implementation : impl1
Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 140MB)
Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 140MB)
Reading constraint file: \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
@L: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1_scck.rpt
@ -234,17 +237,17 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h
Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
@N: FX1184 |Applying syn_allowed_resources blockrams=7 on top level netlist RAM2E
Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
@ -303,7 +306,7 @@ Finished Pre Mapping Phase.
Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
@ -313,10 +316,10 @@ Pre-mapping successful!
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 99MB peak: 185MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Dec 28 23:09:49 2023
# Thu Dec 28 23:23:23 2023
###########################################################]
# Thu Dec 28 23:09:49 2023
# Thu Dec 28 23:23:23 2023
Copyright (C) 1994-2021 Synopsys, Inc.
@ -335,34 +338,34 @@ Implementation : impl1
Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
@N: MF916 |Option synthesis_strategy=base is enabled.
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 139MB)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 139MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 146MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB)
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 178MB peak: 178MB)
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 179MB peak: 179MB)
Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB)
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB)
@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":14:23:14:28|Found counter in view:work.RAM2E(verilog) instance FS[15:0]
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB)
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB)
Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
@ -378,22 +381,22 @@ Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CP
Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 191MB)
Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 191MB)
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 191MB)
Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 191MB)
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 191MB)
Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 211MB peak: 211MB)
Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 211MB peak: 211MB)
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:02s 33.71ns 284 / 122
1 0h:00m:01s 33.71ns 284 / 122
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 211MB peak: 211MB)
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 211MB peak: 211MB)
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Boundary register BA_1_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
@ -402,30 +405,30 @@ Finished technology timing optimizations and critical path resynthesis (Real Tim
Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 212MB peak: 212MB)
Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 174MB peak: 212MB)
Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 174MB peak: 212MB)
Writing Analyst data base \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_m.srm
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 212MB peak: 212MB)
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 212MB peak: 212MB)
Writing EDIF Netlist and constraint files
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1.edi
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB)
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB)
Finished Writing Netlists (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB)
Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB)
Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 215MB peak: 217MB)
Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 215MB peak: 217MB)
@W: MT246 :"\\mac\icloud\repos\ram2e\cpld\lcmxo2-1200hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@N: MT615 |Found clock C14M with period 69.84ns
##### START OF TIMING REPORT #####[
# Timing report written on Thu Dec 28 23:09:54 2023
# Timing report written on Thu Dec 28 23:23:26 2023
#
@ -647,10 +650,10 @@ ram2e_ufm.RWMask[0] FD1P3AX SP In
Timing exceptions that could not be applied
Finished final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 216MB peak: 217MB)
Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 216MB peak: 217MB)
Finished timing report (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 216MB peak: 217MB)
Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 216MB peak: 217MB)
---------------------------------------
Resource Usage Report
@ -685,9 +688,9 @@ VHI: 3
VLO: 3
Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 79MB peak: 217MB)
At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 80MB peak: 217MB)
Process took 0h:00m:04s realtime, 0h:00m:04s cputime
# Thu Dec 28 23:09:54 2023
Process took 0h:00m:03s realtime, 0h:00m:03s cputime
# Thu Dec 28 23:23:26 2023
###########################################################]

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@ -13,7 +13,7 @@ Setup and Hold Report
--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
Thu Dec 28 23:09:59 2023
Thu Dec 28 23:23:29 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
@ -114,7 +114,7 @@ Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
Thu Dec 28 23:09:59 2023
Thu Dec 28 23:23:29 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.

View File

@ -13,7 +13,7 @@ Setup and Hold Report
--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
Thu Dec 28 23:10:17 2023
Thu Dec 28 23:23:45 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
@ -614,7 +614,7 @@ Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
Thu Dec 28 23:10:17 2023
Thu Dec 28 23:23:45 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.

View File

@ -12,7 +12,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Thu Dec 28 23:10:25 2023
Thu Dec 28 23:23:53 2023
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC -w -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1.ncd RAM2E_LCMXO2_1200HC_impl1.prf
@ -81,7 +81,7 @@ Creating bit map...
Bitstream Status: Final Version 1.95.
Saving bit stream in "RAM2E_LCMXO2_1200HC_impl1.bit".
Total CPU Time: 4 secs
Total CPU Time: 3 secs
Total REAL Time: 4 secs
Peak Memory Usage: 275 MB

View File

@ -13,7 +13,7 @@ Hostname: ZANEMACWIN11
Implementation : impl1
# Written on Thu Dec 28 23:09:49 2023
# Written on Thu Dec 28 23:23:22 2023
##### DESIGN INFO #######################################################

View File

@ -38,7 +38,7 @@ Performance Hardware Data Status: Final Version 34.4.
// Package: TQFP100
// ncd File: ram2e_lcmxo2_1200hc_impl1.ncd
// Version: Diamond (64-bit) 3.12.1.454
// Written on Thu Dec 28 23:10:20 2023
// Written on Thu Dec 28 23:23:48 2023
// M: Minimum Performance Grade
// iotiming RAM2E_LCMXO2_1200HC_impl1.ncd RAM2E_LCMXO2_1200HC_impl1.prf -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml

View File

@ -1,7 +1,7 @@
(DELAYFILE
(SDFVERSION "3.0")
(DESIGN "RAM2E")
(DATE "Thu Dec 28 23:10:01 2023")
(DATE "Thu Dec 28 23:23:31 2023")
(VENDOR "Lattice")
(PROGRAM "ldbanno")
(VERSION "Diamond (64-bit) 3.12.1.454")

View File

@ -2,8 +2,8 @@
// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454
// ldbanno -n Verilog -o RAM2E_LCMXO2_1200HC_impl1_mapvo.vo -w -neg -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1_map.ncd
// Netlist created on Thu Dec 28 23:09:57 2023
// Netlist written on Thu Dec 28 23:10:01 2023
// Netlist created on Thu Dec 28 23:23:27 2023
// Netlist written on Thu Dec 28 23:23:31 2023
// Design is for device LCMXO2-1200HC
// Design is for package TQFP100
// Design is for performance grade 4

View File

@ -23,7 +23,7 @@ Target Vendor: LATTICE
Target Device: LCMXO2-1200HCTQFP100
Target Performance: 4
Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454
Mapped on: 12/28/23 23:09:57
Mapped on: 12/28/23 23:23:27
<A name="mrp_ds"></A><B><U><big>Design Summary</big></U></B>
@ -407,7 +407,7 @@ Instance Name: ram2e_ufm/ufmefb/EFBInst_0
<A name="mrp_runtime"></A><B><U><big>Run Time and Memory Usage</big></U></B>
-------------------------
Total CPU Time: 1 secs
Total CPU Time: 0 secs
Total REAL Time: 0 secs
Peak Memory Usage: 64 MB

View File

@ -14,7 +14,7 @@ Performance Grade: 4
PACKAGE: TQFP100
Package Status: Final Version 1.44
Thu Dec 28 23:10:10 2023
Thu Dec 28 23:23:38 2023
Pinout by Port Name:
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
@ -318,7 +318,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Thu Dec 28 23:10:13 2023
Thu Dec 28 23:23:42 2023

View File

@ -12,7 +12,7 @@ Copyright (c) 1995 AT&amp;T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Thu Dec 28 23:10:01 2023
Thu Dec 28 23:23:31 2023
C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2E_LCMXO2_1200HC_impl1.p2t
RAM2E_LCMXO2_1200HC_impl1_map.ncd RAM2E_LCMXO2_1200HC_impl1.dir
@ -26,17 +26,17 @@ Preference file: RAM2E_LCMXO2_1200HC_impl1.prf.
Level/ Number Worst Timing Worst Timing Run NCD
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
---------- -------- ----- ------ ----------- ----------- ---- ------
5_1 * 0 58.069 0 0.342 0 15 Completed
5_1 * 0 58.069 0 0.342 0 13 Completed
* : Design saved.
Total (real) run time for 1-seed: 15 secs
Total (real) run time for 1-seed: 13 secs
par done!
Note: user must run &apos;Trace&apos; for timing closure signoff.
Lattice Place and Route Report for Design &quot;RAM2E_LCMXO2_1200HC_impl1_map.ncd&quot;
Thu Dec 28 23:10:01 2023
Thu Dec 28 23:23:31 2023
<A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
@ -89,17 +89,17 @@ The following 1 signal is selected to use the secondary clock routing resources:
No signal is selected as Global Set/Reset.
Starting Placer Phase 0.
........
Finished Placer Phase 0. REAL time: 3 secs
Finished Placer Phase 0. REAL time: 2 secs
Starting Placer Phase 1.
....................
Placer score = 82860.
Finished Placer Phase 1. REAL time: 8 secs
Finished Placer Phase 1. REAL time: 7 secs
Starting Placer Phase 2.
.
Placer score = 82610
Finished Placer Phase 2. REAL time: 9 secs
Finished Placer Phase 2. REAL time: 7 secs
@ -141,7 +141,7 @@ I/O Bank Usage Summary:
| 3 | 20 / 20 (100%) | 3.3V | - |
+----------+----------------+------------+-----------+
Total placer CPU time: 7 secs
Total placer CPU time: 6 secs
Dumping design to file RAM2E_LCMXO2_1200HC_impl1.dir/5_1.ncd.
@ -149,9 +149,9 @@ Dumping design to file RAM2E_LCMXO2_1200HC_impl1.dir/5_1.ncd.
Starting router resource preassignment
WARNING - par: The driver of primary clock net C14M_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
Completed router resource preassignment. Real time: 13 secs
Completed router resource preassignment. Real time: 12 secs
Start NBR router at 23:10:14 12/28/23
Start NBR router at 23:23:43 12/28/23
*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
@ -166,32 +166,32 @@ Note: NBR uses a different method to calculate timing slacks. The
your design.
*****************************************************************
Start NBR special constraint process at 23:10:14 12/28/23
Start NBR special constraint process at 23:23:43 12/28/23
Start NBR section for initial routing at 23:10:14 12/28/23
Start NBR section for initial routing at 23:23:43 12/28/23
Level 4, iteration 1
19(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 58.075ns/0.000ns; real time: 14 secs
Estimated worst slack/total negative slack&lt;setup&gt;: 58.075ns/0.000ns; real time: 12 secs
Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area at 75% usage is 0 (0.00%)
Start NBR section for normal routing at 23:10:15 12/28/23
Start NBR section for normal routing at 23:23:43 12/28/23
Level 4, iteration 1
3(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 58.069ns/0.000ns; real time: 14 secs
Estimated worst slack/total negative slack&lt;setup&gt;: 58.069ns/0.000ns; real time: 12 secs
Level 4, iteration 2
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 58.069ns/0.000ns; real time: 14 secs
Estimated worst slack/total negative slack&lt;setup&gt;: 58.069ns/0.000ns; real time: 12 secs
Start NBR section for setup/hold timing optimization with effort level 3 at 23:10:15 12/28/23
Start NBR section for setup/hold timing optimization with effort level 3 at 23:23:43 12/28/23
Start NBR section for re-routing at 23:10:15 12/28/23
Start NBR section for re-routing at 23:23:43 12/28/23
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 58.069ns/0.000ns; real time: 14 secs
Estimated worst slack/total negative slack&lt;setup&gt;: 58.069ns/0.000ns; real time: 12 secs
Start NBR section for post-routing at 23:10:15 12/28/23
Start NBR section for post-routing at 23:23:43 12/28/23
End NBR router with 0 unrouted connection
@ -206,8 +206,8 @@ Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored
Total CPU time 13 secs
Total REAL time: 15 secs
Total CPU time 12 secs
Total REAL time: 13 secs
Completely routed.
End of route. 1330 routed (100.00%); 0 unrouted.
@ -229,8 +229,8 @@ PAR_SUMMARY::Worst slack&lt;hold /&lt;ns&gt;&gt; = 0.342
PAR_SUMMARY::Timing score&lt;hold /&lt;ns&gt;&gt; = 0.000
PAR_SUMMARY::Number of errors = 0
Total CPU time to completion: 14 secs
Total REAL time to completion: 15 secs
Total CPU time to completion: 12 secs
Total REAL time to completion: 13 secs
par done!

View File

@ -13,7 +13,7 @@ Hostname: ZANEMACWIN11
Implementation : impl1
# Written on Thu Dec 28 23:09:48 2023
# Written on Thu Dec 28 23:23:22 2023
##### FILES SYNTAX CHECKED ##############################################
Constraint File(s): "\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc"

View File

@ -62,7 +62,7 @@
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Updated:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2023/12/28 23:10:34</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2023/12/28 23:24:01</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Location:</SPAN></TD>

View File

@ -12,7 +12,7 @@
#OS: Windows 8 6.2
#Hostname: ZANEMACWIN11
# Thu Dec 28 23:09:45 2023
# Thu Dec 28 23:23:19 2023
#Implementation: impl1
@ -61,6 +61,8 @@ Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 202
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v" (library work)
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\REFB.v" (library work)
Verilog syntax check successful!
File \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v changed - recompiling
File \\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v changed - recompiling
Selecting top level module RAM2E
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
Running optimization stage 1 on VHI .......
@ -82,7 +84,7 @@ Running optimization stage 1 on RAM2E .......
Finished optimization stage 1 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB)
Running optimization stage 2 on RAM2E .......
@N: CL159 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v":11:15:11:19|Input nWE80 is unused.
Finished optimization stage 2 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
Finished optimization stage 2 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB)
Running optimization stage 2 on RAM2E_UFM .......
@N: CL159 :"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v":10:7:10:11|Input Ready is unused.
Finished optimization stage 2 on RAM2E_UFM (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
@ -100,7 +102,7 @@ At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Dec 28 23:09:45 2023
# Thu Dec 28 23:23:19 2023
###########################################################]
###########################################################[
@ -121,13 +123,14 @@ Implementation : impl1
Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
@N|Running in 64-bit mode
File \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\layer0.srs changed - recompiling
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Dec 28 23:09:46 2023
# Thu Dec 28 23:23:20 2023
###########################################################]
@ -137,12 +140,12 @@ For a summary of runtime and memory usage for all design units, please see file:
@END
At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 30MB peak: 31MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Dec 28 23:09:46 2023
# Thu Dec 28 23:23:20 2023
###########################################################]
###########################################################[
@ -165,15 +168,15 @@ Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug
@N|Running in 64-bit mode
File \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_comp.srs changed - recompiling
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Dec 28 23:09:47 2023
# Thu Dec 28 23:23:21 2023
###########################################################]
# Thu Dec 28 23:09:47 2023
# Thu Dec 28 23:23:21 2023
Copyright (C) 1994-2021 Synopsys, Inc.
@ -192,10 +195,10 @@ Implementation : impl1
Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 140MB)
Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 140MB)
Reading constraint file: \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
@L: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1_scck.rpt
@ -243,17 +246,17 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h
Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
@N: FX1184 |Applying syn_allowed_resources blockrams=7 on top level netlist RAM2E
Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
@ -312,7 +315,7 @@ Finished Pre Mapping Phase.
Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
@ -322,10 +325,10 @@ Pre-mapping successful!
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 99MB peak: 185MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Dec 28 23:09:49 2023
# Thu Dec 28 23:23:23 2023
###########################################################]
# Thu Dec 28 23:09:49 2023
# Thu Dec 28 23:23:23 2023
Copyright (C) 1994-2021 Synopsys, Inc.
@ -344,34 +347,34 @@ Implementation : impl1
Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
@N: MF916 |Option synthesis_strategy=base is enabled.
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 139MB)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 139MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 146MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB)
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 178MB peak: 178MB)
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 179MB peak: 179MB)
Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB)
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB)
@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":14:23:14:28|Found counter in view:work.RAM2E(verilog) instance FS[15:0]
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB)
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB)
Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
@ -387,22 +390,22 @@ Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CP
Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 191MB)
Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 191MB)
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 191MB)
Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 191MB)
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 191MB)
Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 211MB peak: 211MB)
Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 211MB peak: 211MB)
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:02s 33.71ns 284 / 122
1 0h:00m:01s 33.71ns 284 / 122
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 211MB peak: 211MB)
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 211MB peak: 211MB)
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Boundary register BA_1_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
@ -411,30 +414,30 @@ Finished technology timing optimizations and critical path resynthesis (Real Tim
Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 212MB peak: 212MB)
Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 174MB peak: 212MB)
Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 174MB peak: 212MB)
Writing Analyst data base \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_m.srm
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 212MB peak: 212MB)
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 212MB peak: 212MB)
Writing EDIF Netlist and constraint files
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1.edi
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB)
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB)
Finished Writing Netlists (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB)
Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB)
Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 215MB peak: 217MB)
Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 215MB peak: 217MB)
@W: MT246 :"\\mac\icloud\repos\ram2e\cpld\lcmxo2-1200hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@N: MT615 |Found clock C14M with period 69.84ns
##### START OF TIMING REPORT #####[
# Timing report written on Thu Dec 28 23:09:54 2023
# Timing report written on Thu Dec 28 23:23:26 2023
#
@ -656,10 +659,10 @@ ram2e_ufm.RWMask[0] FD1P3AX SP In
Timing exceptions that could not be applied
Finished final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 216MB peak: 217MB)
Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 216MB peak: 217MB)
Finished timing report (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 216MB peak: 217MB)
Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 216MB peak: 217MB)
---------------------------------------
Resource Usage Report
@ -694,10 +697,10 @@ VHI: 3
VLO: 3
Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 79MB peak: 217MB)
At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 80MB peak: 217MB)
Process took 0h:00m:04s realtime, 0h:00m:04s cputime
# Thu Dec 28 23:09:54 2023
Process took 0h:00m:03s realtime, 0h:00m:03s cputime
# Thu Dec 28 23:23:26 2023
###########################################################]

View File

@ -22,7 +22,7 @@ Setup and Hold Report
--------------------------------------------------------------------------------
<A name="Map_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454</big></U></B>
Thu Dec 28 23:09:59 2023
Thu Dec 28 23:23:29 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
@ -128,7 +128,7 @@ Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)
--------------------------------------------------------------------------------
<A name="Map_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454</big></U></B>
Thu Dec 28 23:09:59 2023
Thu Dec 28 23:23:29 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.

View File

@ -22,7 +22,7 @@ Setup and Hold Report
--------------------------------------------------------------------------------
<A name="Par_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454</big></U></B>
Thu Dec 28 23:10:17 2023
Thu Dec 28 23:23:45 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
@ -628,7 +628,7 @@ Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)
--------------------------------------------------------------------------------
<A name="Par_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454</big></U></B>
Thu Dec 28 23:10:17 2023
Thu Dec 28 23:23:45 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.

View File

@ -1,7 +1,7 @@
(DELAYFILE
(SDFVERSION "3.0")
(DESIGN "RAM2E")
(DATE "Thu Dec 28 23:10:25 2023")
(DATE "Thu Dec 28 23:23:53 2023")
(VENDOR "Lattice")
(PROGRAM "ldbanno")
(VERSION "Diamond (64-bit) 3.12.1.454")

View File

@ -2,8 +2,8 @@
// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454
// ldbanno -n Verilog -o RAM2E_LCMXO2_1200HC_impl1_vo.vo -w -neg -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1.ncd
// Netlist created on Thu Dec 28 23:09:57 2023
// Netlist written on Thu Dec 28 23:10:24 2023
// Netlist created on Thu Dec 28 23:23:27 2023
// Netlist written on Thu Dec 28 23:23:52 2023
// Design is for device LCMXO2-1200HC
// Design is for package TQFP100
// Design is for performance grade 4

View File

@ -5,8 +5,8 @@ Starting: parse design source files
(VERI-1482) Analyzing Verilog file '//Mac/iCloud/Repos/RAM2E/CPLD/UFM-LCMXO2.v'
(VERI-1482) Analyzing Verilog file '//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/REFB.v'
INFO - //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v(1,8-1,13) (VERI-1018) compiling module 'RAM2E'
INFO - //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v(1,1-463,10) (VERI-9000) elaborating module 'RAM2E'
INFO - //Mac/iCloud/Repos/RAM2E/CPLD/UFM-LCMXO2.v(1,1-333,10) (VERI-9000) elaborating module 'RAM2E_UFM_uniq_1'
INFO - //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v(1,1-473,10) (VERI-9000) elaborating module 'RAM2E'
INFO - //Mac/iCloud/Repos/RAM2E/CPLD/UFM-LCMXO2.v(1,1-334,10) (VERI-9000) elaborating module 'RAM2E_UFM_uniq_1'
INFO - //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/REFB.v(8,1-113,10) (VERI-9000) elaborating module 'REFB_uniq_1'
INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_1'
INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_1'

View File

@ -29,7 +29,7 @@ Performance Hardware Data Status: Final Version 34.4.
// Package: TQFP100
// ncd File: ram2e_lcmxo2_1200hc_impl1.ncd
// Version: Diamond (64-bit) 3.12.1.454
// Written on Thu Dec 28 23:10:20 2023
// Written on Thu Dec 28 23:23:48 2023
// M: Minimum Performance Grade
// iotiming RAM2E_LCMXO2_1200HC_impl1.ncd RAM2E_LCMXO2_1200HC_impl1.prf -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml

View File

@ -1,3 +1,3 @@
<?xml version="1.0" encoding="UTF-8"?>
<userSetting name="//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml" version="Diamond (64-bit) 3.12.1.454" date="Thu Dec 28 23:11:37 2023" vendor="Lattice Semiconductor Corporation" >
<userSetting name="//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml" version="Diamond (64-bit) 3.12.1.454" date="Thu Dec 28 23:24:04 2023" vendor="Lattice Semiconductor Corporation" >
</userSetting>

View File

@ -1,6 +1,6 @@
NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
NOTE All Rights Reserved *
NOTE DATE CREATED: Thu Dec 28 23:10:32 2023 *
NOTE DATE CREATED: Thu Dec 28 23:23:58 2023 *
NOTE DESIGN NAME: RAM2E *
NOTE DEVICE NAME: LCMXO2-640HC-4TQFP100 *
NOTE PIN ASSIGNMENTS *

View File

@ -4,7 +4,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Thu Dec 28 23:10:28 2023
Thu Dec 28 23:23:55 2023
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC -w -jedec -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf
@ -82,5 +82,5 @@ Available General Purpose Flash Memory: 191 Pages (Page 0 to Page 190).
Initialized UFM Pages: 1 Page (Page 190).
Total CPU Time: 3 secs
Total REAL Time: 4 secs
Total REAL Time: 3 secs
Peak Memory Usage: 267 MB

View File

@ -4,7 +4,7 @@
(keywordMap (keywordLevel 0))
(status
(written
(timeStamp 2023 12 28 23 9 53)
(timeStamp 2023 12 28 23 23 25)
(author "Synopsys, Inc.")
(program "Synplify Pro" (version "R-2021.03L-SP1, mapper map202103lat, Build 070R"))
)

View File

@ -2,7 +2,7 @@
NOTE Diamond (64-bit) 3.12.1.454 JEDEC Compatible Fuse File.*
NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation.*
NOTE All Rights Reserved.*
NOTE DATE CREATED: Thu Dec 28 23:10:29 2023*
NOTE DATE CREATED: Thu Dec 28 23:23:55 2023*
NOTE DESIGN NAME: RAM2E_LCMXO2_640HC_impl1.ncd*
NOTE DEVICE NAME: LCMXO2-640HC-4TQFP100*
NOTE JEDEC FILE STATUS: Final Version 1.95*
@ -1437,4 +1437,4 @@ E0000000000000000000000000000000000000000000000000000000000000000
0000010001100000*
NOTE User Electronic Signature Data*
UH00000000*
4DD0
4DD3

View File

@ -15,7 +15,7 @@ Target Vendor: LATTICE
Target Device: LCMXO2-640HCTQFP100
Target Performance: 4
Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454
Mapped on: 12/28/23 23:09:57
Mapped on: 12/28/23 23:23:28
Design Summary
--------------
@ -66,7 +66,7 @@ Design Summary
Design: RAM2E Date: 12/28/23 23:09:57
Design: RAM2E Date: 12/28/23 23:23:28
Design Summary (cont)
---------------------
@ -132,7 +132,7 @@ IO (PIO) Attributes
Design: RAM2E Date: 12/28/23 23:09:57
Design: RAM2E Date: 12/28/23 23:23:28
IO (PIO) Attributes (cont)
--------------------------
@ -198,7 +198,7 @@ IO (PIO) Attributes (cont)
Design: RAM2E Date: 12/28/23 23:09:57
Design: RAM2E Date: 12/28/23 23:23:28
IO (PIO) Attributes (cont)
--------------------------
@ -264,7 +264,7 @@ IO (PIO) Attributes (cont)
Design: RAM2E Date: 12/28/23 23:09:57
Design: RAM2E Date: 12/28/23 23:23:28
IO (PIO) Attributes (cont)
--------------------------
@ -330,7 +330,7 @@ Signal ram2e_ufm/ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
Design: RAM2E Date: 12/28/23 23:09:57
Design: RAM2E Date: 12/28/23 23:23:28
Removed logic (cont)
--------------------
@ -396,7 +396,7 @@ Embedded Functional Block Connection Summary
Design: RAM2E Date: 12/28/23 23:09:57
Design: RAM2E Date: 12/28/23 23:23:28
Embedded Functional Block Connection Summary (cont)
---------------------------------------------------