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This commit is contained in:
Zane Kaminski
2023-12-28 23:24:48 -05:00
parent e73d7034d8
commit 1bbca43cfd
58 changed files with 329 additions and 300 deletions
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17
CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC_tcl.html
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@@ -59,6 +59,23 @@ prj_project open "//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200H
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{

2
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.alt
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@@ -1,6 +1,6 @@
NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
NOTE All Rights Reserved *
NOTE DATE CREATED: Thu Dec 28 23:10:34 2023 *
NOTE DATE CREATED: Thu Dec 28 23:24:00 2023 *
NOTE DESIGN NAME: RAM2E *
NOTE DEVICE NAME: LCMXO2-1200HC-4TQFP100 *
NOTE PIN ASSIGNMENTS *

4
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.bgn
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@@ -4,7 +4,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Thu Dec 28 23:10:30 2023
Thu Dec 28 23:23:57 2023
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC -w -jedec -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1.ncd RAM2E_LCMXO2_1200HC_impl1.prf
@@ -82,5 +82,5 @@ Available General Purpose Flash Memory: 511 Pages (Page 0 to Page 510).
Initialized UFM Pages: 321 Pages (Page 190 to Page 510).
Total CPU Time: 3 secs
Total REAL Time: 4 secs
Total REAL Time: 3 secs
Peak Memory Usage: 275 MB

BIN
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.bit
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Binary file not shown.

2
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.edi
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@@ -4,7 +4,7 @@
(keywordMap (keywordLevel 0))
(status
(written
(timeStamp 2023 12 28 23 9 53)
(timeStamp 2023 12 28 23 23 26)
(author "Synopsys, Inc.")
(program "Synplify Pro" (version "R-2021.03L-SP1, mapper map202103lat, Build 070R"))
)

4
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.jed
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@@ -2,7 +2,7 @@
NOTE Diamond (64-bit) 3.12.1.454 JEDEC Compatible Fuse File.*
NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation.*
NOTE All Rights Reserved.*
NOTE DATE CREATED: Thu Dec 28 23:10:30 2023*
NOTE DATE CREATED: Thu Dec 28 23:23:57 2023*
NOTE DESIGN NAME: RAM2E_LCMXO2_1200HC_impl1.ncd*
NOTE DEVICE NAME: LCMXO2-1200HC-4TQFP100*
NOTE JEDEC FILE STATUS: Final Version 1.95*
@@ -2781,4 +2781,4 @@ E0000000000000000000000000000000000000000000000000000000000000000
0000010001100000*
NOTE User Electronic Signature Data*
UH00000000*
C84F
C85C

16
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.mrp
View File

@@ -15,7 +15,7 @@ Target Vendor: LATTICE
Target Device: LCMXO2-1200HCTQFP100
Target Performance: 4
Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454
Mapped on: 12/28/23 23:09:57
Mapped on: 12/28/23 23:23:27
Design Summary
--------------
@@ -66,7 +66,7 @@ Design Summary
Design: RAM2E Date: 12/28/23 23:09:57
Design: RAM2E Date: 12/28/23 23:23:27
Design Summary (cont)
---------------------
@@ -132,7 +132,7 @@ WARNING - map: IO buffer missing for top level port nWE80...logic will be
Design: RAM2E Date: 12/28/23 23:09:57
Design: RAM2E Date: 12/28/23 23:23:27
IO (PIO) Attributes
@@ -198,7 +198,7 @@ IO (PIO) Attributes
Design: RAM2E Date: 12/28/23 23:09:57
Design: RAM2E Date: 12/28/23 23:23:27
IO (PIO) Attributes (cont)
--------------------------
@@ -264,7 +264,7 @@ IO (PIO) Attributes (cont)
Design: RAM2E Date: 12/28/23 23:09:57
Design: RAM2E Date: 12/28/23 23:23:27
IO (PIO) Attributes (cont)
--------------------------
@@ -330,7 +330,7 @@ Signal ram2e_ufm/ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
Design: RAM2E Date: 12/28/23 23:09:57
Design: RAM2E Date: 12/28/23 23:23:27
Removed logic (cont)
--------------------
@@ -396,7 +396,7 @@ Embedded Functional Block Connection Summary
Design: RAM2E Date: 12/28/23 23:09:57
Design: RAM2E Date: 12/28/23 23:23:27
Embedded Functional Block Connection Summary (cont)
---------------------------------------------------
@@ -443,7 +443,7 @@ Instance Name: ram2e_ufm/ufmefb/EFBInst_0
Run Time and Memory Usage
-------------------------
Total CPU Time: 1 secs
Total CPU Time: 0 secs
Total REAL Time: 0 secs
Peak Memory Usage: 64 MB

4
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.pad
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@@ -6,7 +6,7 @@ Performance Grade: 4
PACKAGE: TQFP100
Package Status: Final Version 1.44
Thu Dec 28 23:10:10 2023
Thu Dec 28 23:23:38 2023
Pinout by Port Name:
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
@@ -309,5 +309,5 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Thu Dec 28 23:10:13 2023
Thu Dec 28 23:23:42 2023

2
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.prf
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@@ -1,5 +1,5 @@
SCHEMATIC START ;
# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Thu Dec 28 23:09:58 2023
# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Thu Dec 28 23:23:28 2023
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
LOCATE COMP "RD[0]" SITE "36" ;

87
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.srr
View File

@@ -3,7 +3,7 @@
#OS: Windows 8 6.2
#Hostname: ZANEMACWIN11
# Thu Dec 28 23:09:45 2023
# Thu Dec 28 23:23:19 2023
#Implementation: impl1
@@ -52,6 +52,8 @@ Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 202
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v" (library work)
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\REFB.v" (library work)
Verilog syntax check successful!
File \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v changed - recompiling
File \\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v changed - recompiling
Selecting top level module RAM2E
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
Running optimization stage 1 on VHI .......
@@ -73,7 +75,7 @@ Running optimization stage 1 on RAM2E .......
Finished optimization stage 1 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB)
Running optimization stage 2 on RAM2E .......
@N: CL159 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v":11:15:11:19|Input nWE80 is unused.
Finished optimization stage 2 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
Finished optimization stage 2 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB)
Running optimization stage 2 on RAM2E_UFM .......
@N: CL159 :"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v":10:7:10:11|Input Ready is unused.
Finished optimization stage 2 on RAM2E_UFM (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
@@ -91,7 +93,7 @@ At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Dec 28 23:09:45 2023
# Thu Dec 28 23:23:19 2023
###########################################################]
###########################################################[
@@ -112,13 +114,14 @@ Implementation : impl1
Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
@N|Running in 64-bit mode
File \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\layer0.srs changed - recompiling
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Dec 28 23:09:46 2023
# Thu Dec 28 23:23:20 2023
###########################################################]
@@ -128,12 +131,12 @@ For a summary of runtime and memory usage for all design units, please see file:
@END
At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 30MB peak: 31MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Dec 28 23:09:46 2023
# Thu Dec 28 23:23:20 2023
###########################################################]
###########################################################[
@@ -156,15 +159,15 @@ Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug
@N|Running in 64-bit mode
File \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_comp.srs changed - recompiling
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Dec 28 23:09:47 2023
# Thu Dec 28 23:23:21 2023
###########################################################]
# Thu Dec 28 23:09:47 2023
# Thu Dec 28 23:23:21 2023
Copyright (C) 1994-2021 Synopsys, Inc.
@@ -183,10 +186,10 @@ Implementation : impl1
Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 140MB)
Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 140MB)
Reading constraint file: \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
@L: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1_scck.rpt
@@ -234,17 +237,17 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h
Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
@N: FX1184 |Applying syn_allowed_resources blockrams=7 on top level netlist RAM2E
Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
@@ -303,7 +306,7 @@ Finished Pre Mapping Phase.
Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
@@ -313,10 +316,10 @@ Pre-mapping successful!
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 99MB peak: 185MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Dec 28 23:09:49 2023
# Thu Dec 28 23:23:23 2023
###########################################################]
# Thu Dec 28 23:09:49 2023
# Thu Dec 28 23:23:23 2023
Copyright (C) 1994-2021 Synopsys, Inc.
@@ -335,34 +338,34 @@ Implementation : impl1
Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
@N: MF916 |Option synthesis_strategy=base is enabled.
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 139MB)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 139MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 146MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB)
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 178MB peak: 178MB)
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 179MB peak: 179MB)
Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB)
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB)
@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":14:23:14:28|Found counter in view:work.RAM2E(verilog) instance FS[15:0]
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB)
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB)
Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
@@ -378,22 +381,22 @@ Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CP
Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 191MB)
Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 191MB)
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 191MB)
Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 191MB)
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 191MB)
Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 211MB peak: 211MB)
Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 211MB peak: 211MB)
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:02s 33.71ns 284 / 122
1 0h:00m:01s 33.71ns 284 / 122
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 211MB peak: 211MB)
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 211MB peak: 211MB)
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Boundary register BA_1_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
@@ -402,30 +405,30 @@ Finished technology timing optimizations and critical path resynthesis (Real Tim
Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 212MB peak: 212MB)
Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 174MB peak: 212MB)
Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 174MB peak: 212MB)
Writing Analyst data base \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_m.srm
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 212MB peak: 212MB)
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 212MB peak: 212MB)
Writing EDIF Netlist and constraint files
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1.edi
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB)
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB)
Finished Writing Netlists (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB)
Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB)
Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 215MB peak: 217MB)
Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 215MB peak: 217MB)
@W: MT246 :"\\mac\icloud\repos\ram2e\cpld\lcmxo2-1200hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@N: MT615 |Found clock C14M with period 69.84ns
##### START OF TIMING REPORT #####[
# Timing report written on Thu Dec 28 23:09:54 2023
# Timing report written on Thu Dec 28 23:23:26 2023
#
@@ -647,10 +650,10 @@ ram2e_ufm.RWMask[0] FD1P3AX SP In
Timing exceptions that could not be applied
Finished final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 216MB peak: 217MB)
Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 216MB peak: 217MB)
Finished timing report (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 216MB peak: 217MB)
Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 216MB peak: 217MB)
---------------------------------------
Resource Usage Report
@@ -685,9 +688,9 @@ VHI: 3
VLO: 3
Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 79MB peak: 217MB)
At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 80MB peak: 217MB)
Process took 0h:00m:04s realtime, 0h:00m:04s cputime
# Thu Dec 28 23:09:54 2023
Process took 0h:00m:03s realtime, 0h:00m:03s cputime
# Thu Dec 28 23:23:26 2023
###########################################################]

4
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.tw1
View File

@@ -13,7 +13,7 @@ Setup and Hold Report
--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
Thu Dec 28 23:09:59 2023
Thu Dec 28 23:23:29 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
@@ -114,7 +114,7 @@ Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
Thu Dec 28 23:09:59 2023
Thu Dec 28 23:23:29 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.

4
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.twr
View File

@@ -13,7 +13,7 @@ Setup and Hold Report
--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
Thu Dec 28 23:10:17 2023
Thu Dec 28 23:23:45 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
@@ -614,7 +614,7 @@ Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
Thu Dec 28 23:10:17 2023
Thu Dec 28 23:23:45 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.

4
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_bgn.html
View File

@@ -12,7 +12,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
@@ -81,7 +81,7 @@ Creating bit map...
{
background-color: #ff0000;
}
.comment
.comment
{
font-size: 90%;
font-style: italic;

2
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_cck.rpt
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@@ -13,7 +13,7 @@ Hostname: ZANEMACWIN11
Implementation : impl1
# Written on Thu Dec 28 23:09:49 2023
# Written on Thu Dec 28 23:23:22 2023
##### DESIGN INFO #######################################################

2
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_iotiming.html
View File

@@ -38,7 +38,7 @@ Performance Hardware Data Status: Final Version 34.4.
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}

2
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_mapvo.sdf
View File

@@ -1,7 +1,7 @@
(DELAYFILE
(SDFVERSION "3.0")
(DESIGN "RAM2E")
(DATE "Thu Dec 28 23:10:01 2023")
(DATE "Thu Dec 28 23:23:31 2023")
(VENDOR "Lattice")
(PROGRAM "ldbanno")
(VERSION "Diamond (64-bit) 3.12.1.454")

4
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_mapvo.vo
View File

@@ -2,8 +2,8 @@
// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454
// ldbanno -n Verilog -o RAM2E_LCMXO2_1200HC_impl1_mapvo.vo -w -neg -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1_map.ncd
// Netlist created on Thu Dec 28 23:09:57 2023
// Netlist written on Thu Dec 28 23:10:01 2023
// Netlist created on Thu Dec 28 23:23:27 2023
// Netlist written on Thu Dec 28 23:23:31 2023
// Design is for device LCMXO2-1200HC
// Design is for package TQFP100
// Design is for performance grade 4

4
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_mrp.html
View File

@@ -23,7 +23,7 @@ Target Vendor: LATTICE
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
@@ -407,7 +407,7 @@ Instance Name: ram2e_ufm/ufmefb/EFBInst_0
clipped.
Signal ram2e_ufm/ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C1SDAOEN undriven or does not drive anything -
clipped.
clipped.
Signal ram2e_ufm/ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C1SCLOEN undriven or does not drive anything -
clipped.

4
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_pad.html
View File

@@ -14,7 +14,7 @@ Performance Grade: 4
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
@@ -318,7 +318,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
Dedicated sysCONFIG Pins:
List of All Pins' Locate Preferences Based on Final Placement After PAR
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste):

48
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_par.html
View File

@@ -12,7 +12,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
@@ -26,17 +26,17 @@ Preference file: RAM2E_LCMXO2_1200HC_impl1.prf.
margin-bottom: 5px;
font-size: 0.80em;
}
p {
p {
font-size:78%;
}
P.Table {
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
@@ -89,17 +89,17 @@ The following 1 signal is selected to use the secondary clock routing resources:
-->
</STYLE>
</HEAD>
</HEAD>
<PRE><A name="Par"></A>PAR: Place And Route Diamond (64-bit) 3.12.1.454.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&amp;T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Thu Dec 28 23:23:31 2023
C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2E_LCMXO2_1200HC_impl1.p2t
RAM2E_LCMXO2_1200HC_impl1_map.ncd RAM2E_LCMXO2_1200HC_impl1.dir
RAM2E_LCMXO2_1200HC_impl1_map.ncd RAM2E_LCMXO2_1200HC_impl1.dir
RAM2E_LCMXO2_1200HC_impl1.prf -gui -msgset
//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml
@@ -141,7 +141,7 @@ I/O Bank Usage Summary:
Package Status: Final Version 1.44.
Performance Hardware Data Status: Final Version 34.4.
License checked out.
Ignore Preference Error(s): True
@@ -149,9 +149,9 @@ Dumping design to file RAM2E_LCMXO2_1200HC_impl1.dir/5_1.ncd.
PIO (prelim) 69+4(JTAG)/108 68% used
69+4(JTAG)/80 91% bonded
IOLOGIC 29/108 26% used
IOLOGIC 29/108 26% used
SLICE 148/640 23% used
SLICE 148/640 23% used
EFB 1/1 100% used
@@ -166,32 +166,32 @@ Note: NBR uses a different method to calculate timing slacks. The
C14M_c (driver: C14M, clk load #: 89)
WARNING - par: Signal &quot;C14M_c&quot; is selected to use Primary clock resources. However, its driver comp &quot;C14M&quot; is located at &quot;62&quot;, which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
The following 1 signal is selected to use the secondary clock routing resources:
N_187_i (driver: ram2e_ufm/SLICE_130, clk load #: 0, sr load #: 0, ce load #: 11)
N_187_i (driver: ram2e_ufm/SLICE_130, clk load #: 0, sr load #: 0, ce load #: 11)
No signal is selected as Global Set/Reset.
Starting Placer Phase 0.
Starting Placer Phase 0.
........
Finished Placer Phase 0. REAL time: 2 secs
Starting Placer Phase 1.
....................
....................
Placer score = 82860.
Finished Placer Phase 1. REAL time: 7 secs
Starting Placer Phase 2.
.
Placer score = 82610
Placer score = 82610
Finished Placer Phase 2. REAL time: 7 secs
<A name="par_clk"></A><B><U><big>Clock Report</big></U></B>
Global Clock Resources:
Global Clock Resources:
CLK_PIN : 0 out of 8 (0%)
General PIO: 1 out of 108 (0%)
General PIO: 1 out of 108 (0%)
PLL : 0 out of 1 (0%)
DCM : 0 out of 2 (0%)
DCC : 0 out of 8 (0%)
@@ -206,8 +206,8 @@ Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored
Edge Clocks:
No edge clock selected.
I/O Usage Summary (final):
69 + 4(JTAG) out of 108 (67.6%) PIO sites used.
@@ -229,8 +229,8 @@ PAR_SUMMARY::Worst slack&lt;hold /&lt;ns&gt;&gt; = 0.342
Dumping design to file RAM2E_LCMXO2_1200HC_impl1.dir/5_1.ncd.
0 connections routed; 1330 unrouted.
Starting router resource preassignment
0 connections routed; 1330 unrouted.
Starting router resource preassignment
WARNING - par: The driver of primary clock net C14M_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
Completed router resource preassignment. Real time: 12 secs

2
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_scck.rpt
View File

@@ -13,7 +13,7 @@ Hostname: ZANEMACWIN11
Implementation : impl1
# Written on Thu Dec 28 23:09:48 2023
# Written on Thu Dec 28 23:23:22 2023
##### FILES SYNTAX CHECKED ##############################################
Constraint File(s): "\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc"

2
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_summary.html
View File

@@ -62,7 +62,7 @@
}
a {
color:#013C9A;
text-decoration:none;
text-decoration:none;
}
a:visited {

87
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_synplify.html
View File

@@ -12,7 +12,7 @@
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
@@ -61,6 +61,8 @@ Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 202
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
@@ -82,7 +84,7 @@ Running optimization stage 1 on RAM2E .......
.comment
{
font-size: 90%;
{
font-style: italic;
}
-->
@@ -100,7 +102,7 @@ At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory
Copyright (C) 1994-2021 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
@@ -121,13 +123,14 @@ Implementation : impl1
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: R-2021.03L-SP1
Install: C:\lscc\diamond\3.12\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
OS: Windows 6.2
Implementation : impl1
Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
@@ -137,12 +140,12 @@ For a summary of runtime and memory usage for all design units, please see file:
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v" (library work)
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v" (library work)
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\REFB.v" (library work)
Verilog syntax check successful!
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v" (library work)
File \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v changed - recompiling
File \\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v changed - recompiling
Selecting top level module RAM2E
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
@@ -165,15 +168,15 @@ Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug
Finished optimization stage 1 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB)
Running optimization stage 2 on RAM2E .......
@N: CL159 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v":11:15:11:19|Input nWE80 is unused.
@N: CL159 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v":11:15:11:19|Input nWE80 is unused.
Finished optimization stage 2 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB)
Running optimization stage 2 on RAM2E_UFM .......
@N: CL159 :"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v":10:7:10:11|Input Ready is unused.
Finished optimization stage 2 on RAM2E_UFM (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
Running optimization stage 2 on REFB .......
Running optimization stage 2 on REFB .......
Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
Running optimization stage 2 on EFB .......
Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
Running optimization stage 2 on VLO .......
Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
Running optimization stage 2 on VHI .......
Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
@@ -192,10 +195,10 @@ Implementation : impl1
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: R-2021.03L-SP1
Build: R-2021.03L-SP1
Install: C:\lscc\diamond\3.12\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
@@ -243,17 +246,17 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h
Hostname: ZANEMACWIN11
Implementation : impl1
Implementation : impl1
Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
@N|Running in 64-bit mode
@N|Running in 64-bit mode
File \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_comp.srs changed - recompiling
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
Process completed successfully.
# Thu Dec 28 23:23:21 2023
###########################################################]
@@ -312,7 +315,7 @@ Finished Pre Mapping Phase.
@N: FX493 |Applying initial value "0" on instance CmdSetRWBankFFLED.
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Initial value on register DQMH is non-zero which can prevent the register from being packed into a block RAM or DSP.
@N: FX493 |Applying initial value "1" on instance DQMH.
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Initial value on register DQML is non-zero which can prevent the register from being packed into a block RAM or DSP.
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Initial value on register DQML is non-zero which can prevent the register from being packed into a block RAM or DSP.
@N: FX493 |Applying initial value "1" on instance DQML.
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":21:4:21:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
@N: FX493 |Applying initial value "0000" on instance S[3:0].
@@ -322,10 +325,10 @@ Pre-mapping successful!
@N: FX493 |Applying initial value "1" on instance nCAS.
@N: FX493 |Applying initial value "1" on instance nCASout.
@N: FX493 |Applying initial value "1" on instance nRAS.
@N: FX493 |Applying initial value "1" on instance nRASout.
@N: FX493 |Applying initial value "1" on instance nRASout.
Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
@@ -344,34 +347,34 @@ Implementation : impl1
Clock Summary
******************
Start Requested Requested Clock Clock Clock
Start Requested Requested Clock Clock Clock
Level Clock Frequency Period Type Group Load
----------------------------------------------------------------------------------------
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 122
0 - System 100.0 MHz 10.000 system system_clkgroup 0
========================================================================================
========================================================================================
Clock Load Summary
***********************
Clock Source Clock Pin Non-clock Pin Non-clock Pin
Clock Load Pin Seq Example Seq Example Comb Example
----------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------
C14M 122 C14M(port) DOEEN.C - un1_C14M.I[0](inv)
System 0 - - - -
========================================================================================
========================================================================================
ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches removed: 0
Number of ICG latches not removed: 0
For details review file gcc_ICG_report.rpt
@S |Clock Optimization Summary
@S |Clock Optimization Summary
@@ -387,22 +390,22 @@ Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CP
@KP:ckid0_0 C14M port 122 nRAS
=======================================================================================
##### END OF CLOCK OPTIMIZATION REPORT ######
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
Finished Pre Mapping Phase.
Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
Pre-mapping successful!
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 99MB peak: 185MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
@@ -411,30 +414,30 @@ Finished technology timing optimizations and critical path resynthesis (Real Tim
###########################################################]
# Thu Dec 28 23:23:23 2023
Copyright (C) 1994-2021 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: R-2021.03L-SP1
Install: C:\lscc\diamond\3.12\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Implementation : impl1
Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
@N: MF916 |Option synthesis_strategy=base is enabled.
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 139MB)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
@@ -656,10 +659,10 @@ ram2e_ufm.RWMask[0] FD1P3AX SP In
====================================
Detailed Report for Clock: System
====================================
Starting Points with Worst Slack
Starting Points with Worst Slack
********************************
Starting Arrival
@@ -694,10 +697,10 @@ VHI: 3
ram2e_ufm.RWMask[6] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088
ram2e_ufm.RWMask[7] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088
ram2e_ufm.LEDEN System FD1P3AX SP un1_LEDEN_0_sqmuxa_1_i_0_0[0] 69.369 67.736
ram2e_ufm.wb_cyc_stb System FD1P3AX SP un1_CmdSetRWBankFFChip13_1_i_0_0[0] 69.369 67.736
ram2e_ufm.wb_cyc_stb System FD1P3AX SP un1_CmdSetRWBankFFChip13_1_i_0_0[0] 69.369 67.736
======================================================================================================================
Worst Path Information
***********************

4
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_tw1.html
View File

@@ -22,7 +22,7 @@ Setup and Hold Report
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
@@ -128,7 +128,7 @@ Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)
<LI><A href='#map_twr_pref_0_0' Target='right'>FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)</A></LI> 1611 items scored, 0 timing errors detected.
Report: 90.967MHz is the maximum frequency for this preference.
BLOCK ASYNCPATHS
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------

4
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_twr.html
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@@ -22,7 +22,7 @@ Setup and Hold Report
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
@@ -628,7 +628,7 @@ Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q S[2] (from C14M_c +)
Destination: FF Data in ram2e_ufm/wb_adr[0] (to C14M_c +)
Destination: FF Data in ram2e_ufm/wb_adr[0] (to C14M_c +)
Delay: 10.898ns (31.4% logic, 68.6% route), 7 logic levels.

2
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_vo.sdf
View File

@@ -1,7 +1,7 @@
(DELAYFILE
(SDFVERSION "3.0")
(DESIGN "RAM2E")
(DATE "Thu Dec 28 23:10:25 2023")
(DATE "Thu Dec 28 23:23:53 2023")
(VENDOR "Lattice")
(PROGRAM "ldbanno")
(VERSION "Diamond (64-bit) 3.12.1.454")

4
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_vo.vo
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@@ -2,8 +2,8 @@
// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454
// ldbanno -n Verilog -o RAM2E_LCMXO2_1200HC_impl1_vo.vo -w -neg -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1.ncd
// Netlist created on Thu Dec 28 23:09:57 2023
// Netlist written on Thu Dec 28 23:10:24 2023
// Netlist created on Thu Dec 28 23:23:27 2023
// Netlist written on Thu Dec 28 23:23:52 2023
// Design is for device LCMXO2-1200HC
// Design is for package TQFP100
// Design is for performance grade 4

4
CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html
View File

@@ -5,8 +5,8 @@ Starting: parse design source files
(VERI-1482) Analyzing Verilog file '//Mac/iCloud/Repos/RAM2E/CPLD/UFM-LCMXO2.v'
(VERI-1482) Analyzing Verilog file '//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/REFB.v'
INFO - //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v(1,8-1,13) (VERI-1018) compiling module 'RAM2E'
INFO - //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v(1,1-463,10) (VERI-9000) elaborating module 'RAM2E'
INFO - //Mac/iCloud/Repos/RAM2E/CPLD/UFM-LCMXO2.v(1,1-333,10) (VERI-9000) elaborating module 'RAM2E_UFM_uniq_1'
INFO - //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v(1,1-473,10) (VERI-9000) elaborating module 'RAM2E'
INFO - //Mac/iCloud/Repos/RAM2E/CPLD/UFM-LCMXO2.v(1,1-334,10) (VERI-9000) elaborating module 'RAM2E_UFM_uniq_1'
INFO - //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/REFB.v(8,1-113,10) (VERI-9000) elaborating module 'REFB_uniq_1'
INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_1'
INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_1'

2
CPLD/LCMXO2-1200HC/impl1/ram2e_lcmxo2_1200hc_impl1.ior
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@@ -29,7 +29,7 @@ Performance Hardware Data Status: Final Version 34.4.
// Package: TQFP100
// ncd File: ram2e_lcmxo2_1200hc_impl1.ncd
// Version: Diamond (64-bit) 3.12.1.454
// Written on Thu Dec 28 23:10:20 2023
// Written on Thu Dec 28 23:23:48 2023
// M: Minimum Performance Grade
// iotiming RAM2E_LCMXO2_1200HC_impl1.ncd RAM2E_LCMXO2_1200HC_impl1.prf -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml

2
CPLD/LCMXO2-1200HC/promote.xml
View File

@@ -1,3 +1,3 @@
<?xml version="1.0" encoding="UTF-8"?>
<userSetting name="//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml" version="Diamond (64-bit) 3.12.1.454" date="Thu Dec 28 23:11:37 2023" vendor="Lattice Semiconductor Corporation" >
<userSetting name="//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml" version="Diamond (64-bit) 3.12.1.454" date="Thu Dec 28 23:24:04 2023" vendor="Lattice Semiconductor Corporation" >
</userSetting>

2
CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.alt
View File

@@ -1,6 +1,6 @@
NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
NOTE All Rights Reserved *
NOTE DATE CREATED: Thu Dec 28 23:10:32 2023 *
NOTE DATE CREATED: Thu Dec 28 23:23:58 2023 *
NOTE DESIGN NAME: RAM2E *
NOTE DEVICE NAME: LCMXO2-640HC-4TQFP100 *
NOTE PIN ASSIGNMENTS *

4
CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.bgn
View File

@@ -4,7 +4,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Thu Dec 28 23:10:28 2023
Thu Dec 28 23:23:55 2023
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC -w -jedec -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf
@@ -82,5 +82,5 @@ Available General Purpose Flash Memory: 191 Pages (Page 0 to Page 190).
Initialized UFM Pages: 1 Page (Page 190).
Total CPU Time: 3 secs
Total REAL Time: 4 secs
Total REAL Time: 3 secs
Peak Memory Usage: 267 MB

BIN
CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.bit
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Binary file not shown.

2
CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.edi
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@@ -4,7 +4,7 @@
(keywordMap (keywordLevel 0))
(status
(written
(timeStamp 2023 12 28 23 9 53)
(timeStamp 2023 12 28 23 23 25)
(author "Synopsys, Inc.")
(program "Synplify Pro" (version "R-2021.03L-SP1, mapper map202103lat, Build 070R"))
)

4
CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.jed
View File

@@ -2,7 +2,7 @@
NOTE Diamond (64-bit) 3.12.1.454 JEDEC Compatible Fuse File.*
NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation.*
NOTE All Rights Reserved.*
NOTE DATE CREATED: Thu Dec 28 23:10:29 2023*
NOTE DATE CREATED: Thu Dec 28 23:23:55 2023*
NOTE DESIGN NAME: RAM2E_LCMXO2_640HC_impl1.ncd*
NOTE DEVICE NAME: LCMXO2-640HC-4TQFP100*
NOTE JEDEC FILE STATUS: Final Version 1.95*
@@ -1437,4 +1437,4 @@ E0000000000000000000000000000000000000000000000000000000000000000
0000010001100000*
NOTE User Electronic Signature Data*
UH00000000*
4DD0
4DD3

14
CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.mrp
View File

@@ -15,7 +15,7 @@ Target Vendor: LATTICE
Target Device: LCMXO2-640HCTQFP100
Target Performance: 4
Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454
Mapped on: 12/28/23 23:09:57
Mapped on: 12/28/23 23:23:28
Design Summary
--------------
@@ -66,7 +66,7 @@ Design Summary
Design: RAM2E Date: 12/28/23 23:09:57
Design: RAM2E Date: 12/28/23 23:23:28
Design Summary (cont)
---------------------
@@ -132,7 +132,7 @@ IO (PIO) Attributes
Design: RAM2E Date: 12/28/23 23:09:57
Design: RAM2E Date: 12/28/23 23:23:28
IO (PIO) Attributes (cont)
--------------------------
@@ -198,7 +198,7 @@ IO (PIO) Attributes (cont)
Design: RAM2E Date: 12/28/23 23:09:57
Design: RAM2E Date: 12/28/23 23:23:28
IO (PIO) Attributes (cont)
--------------------------
@@ -264,7 +264,7 @@ IO (PIO) Attributes (cont)
Design: RAM2E Date: 12/28/23 23:09:57
Design: RAM2E Date: 12/28/23 23:23:28
IO (PIO) Attributes (cont)
--------------------------
@@ -330,7 +330,7 @@ Signal ram2e_ufm/ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
Design: RAM2E Date: 12/28/23 23:09:57
Design: RAM2E Date: 12/28/23 23:23:28
Removed logic (cont)
--------------------
@@ -396,7 +396,7 @@ Embedded Functional Block Connection Summary
Design: RAM2E Date: 12/28/23 23:09:57
Design: RAM2E Date: 12/28/23 23:23:28
Embedded Functional Block Connection Summary (cont)
---------------------------------------------------

4
CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.pad
View File

@@ -6,7 +6,7 @@ Performance Grade: 4
PACKAGE: TQFP100
Package Status: Final Version 1.39
Thu Dec 28 23:10:10 2023
Thu Dec 28 23:23:38 2023
Pinout by Port Name:
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
@@ -281,5 +281,5 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Thu Dec 28 23:10:13 2023
Thu Dec 28 23:23:41 2023

2
CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.prf
View File

@@ -1,5 +1,5 @@
SCHEMATIC START ;
# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Thu Dec 28 23:09:58 2023
# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Thu Dec 28 23:23:28 2023
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
LOCATE COMP "RD[0]" SITE "36" ;

85
CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.srr
View File

@@ -3,7 +3,7 @@
#OS: Windows 8 6.2
#Hostname: ZANEMACWIN11
# Thu Dec 28 23:09:44 2023
# Thu Dec 28 23:23:17 2023
#Implementation: impl1
@@ -52,19 +52,21 @@ Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 202
@I::"\\Mac\iCloud\Repos\ram2e\CPLD\UFM-LCMXO2.v" (library work)
@I::"\\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\REFB.v" (library work)
Verilog syntax check successful!
File \\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.v changed - recompiling
File \\Mac\iCloud\Repos\ram2e\CPLD\UFM-LCMXO2.v changed - recompiling
Selecting top level module RAM2E
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
Running optimization stage 1 on VHI .......
Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 98MB)
Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
Running optimization stage 1 on VLO .......
Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 98MB)
Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
Running optimization stage 1 on EFB .......
Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
@N: CG364 :"\\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
Running optimization stage 1 on REFB .......
Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
@N: CG364 :"\\Mac\iCloud\Repos\ram2e\CPLD\UFM-LCMXO2.v":1:7:1:15|Synthesizing module RAM2E_UFM in library work.
Running optimization stage 1 on RAM2E_UFM .......
Finished optimization stage 1 on RAM2E_UFM (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB)
@@ -73,25 +75,25 @@ Running optimization stage 1 on RAM2E .......
Finished optimization stage 1 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB)
Running optimization stage 2 on RAM2E .......
@N: CL159 :"\\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.v":11:15:11:19|Input nWE80 is unused.
Finished optimization stage 2 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB)
Finished optimization stage 2 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
Running optimization stage 2 on RAM2E_UFM .......
@N: CL159 :"\\Mac\iCloud\Repos\ram2e\CPLD\UFM-LCMXO2.v":10:7:10:11|Input Ready is unused.
Finished optimization stage 2 on RAM2E_UFM (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
Finished optimization stage 2 on RAM2E_UFM (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
Running optimization stage 2 on REFB .......
Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
Running optimization stage 2 on EFB .......
Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
Running optimization stage 2 on VLO .......
Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
Running optimization stage 2 on VHI .......
Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
At c_ver Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 102MB)
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 102MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Dec 28 23:09:45 2023
# Thu Dec 28 23:23:18 2023
###########################################################]
###########################################################[
@@ -112,13 +114,14 @@ Implementation : impl1
Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
@N|Running in 64-bit mode
File \\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\impl1\synwork\layer0.srs changed - recompiling
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Dec 28 23:09:45 2023
# Thu Dec 28 23:23:18 2023
###########################################################]
@@ -128,12 +131,12 @@ For a summary of runtime and memory usage for all design units, please see file:
@END
At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 30MB peak: 31MB)
At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 31MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Dec 28 23:09:46 2023
# Thu Dec 28 23:23:18 2023
###########################################################]
###########################################################[
@@ -161,10 +164,10 @@ At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s;
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Dec 28 23:09:47 2023
# Thu Dec 28 23:23:19 2023
###########################################################]
# Thu Dec 28 23:09:47 2023
# Thu Dec 28 23:23:19 2023
Copyright (C) 1994-2021 Synopsys, Inc.
@@ -204,7 +207,7 @@ Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 149MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 152MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 151MB)
@N: FX493 |Applying initial value "0" on instance CmdBitbangMXO2.
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
@@ -231,20 +234,20 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h
@N: FX493 |Applying initial value "1" on instance nRAS.
@N: FX493 |Applying initial value "1" on instance nRASout.
Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
@N: FX1184 |Applying syn_allowed_resources blockrams=2 on top level netlist RAM2E
Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
@@ -300,7 +303,7 @@ Clock Tree ID Driving Element Drive Element Type Fanout Sample I
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
Finished Pre Mapping Phase.
Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
@@ -313,10 +316,10 @@ Pre-mapping successful!
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 99MB peak: 185MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Dec 28 23:09:49 2023
# Thu Dec 28 23:23:21 2023
###########################################################]
# Thu Dec 28 23:09:49 2023
# Thu Dec 28 23:23:21 2023
Copyright (C) 1994-2021 Synopsys, Inc.
@@ -350,19 +353,19 @@ Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 146MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB)
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 178MB peak: 178MB)
Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB)
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB)
@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":14:23:14:28|Found counter in view:work.RAM2E(verilog) instance FS[15:0]
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB)
Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB)
Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
@@ -384,7 +387,7 @@ Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elaps
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 191MB)
Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 191MB)
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 191MB)
Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 211MB peak: 211MB)
@@ -402,30 +405,30 @@ Finished technology timing optimizations and critical path resynthesis (Real Tim
Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 212MB peak: 212MB)
Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 174MB peak: 212MB)
Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 174MB peak: 212MB)
Writing Analyst data base \\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_m.srm
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 212MB peak: 212MB)
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 212MB peak: 212MB)
Writing EDIF Netlist and constraint files
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1.edi
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB)
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB)
Finished Writing Netlists (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB)
Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB)
Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 215MB peak: 217MB)
Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 215MB peak: 217MB)
@W: MT246 :"\\mac\icloud\repos\ram2e\cpld\lcmxo2-640hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@N: MT615 |Found clock C14M with period 69.84ns
##### START OF TIMING REPORT #####[
# Timing report written on Thu Dec 28 23:09:54 2023
# Timing report written on Thu Dec 28 23:23:25 2023
#
@@ -647,10 +650,10 @@ ram2e_ufm.RWMask[0] FD1P3AX SP In
Timing exceptions that could not be applied
Finished final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 216MB peak: 217MB)
Finished final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 216MB peak: 217MB)
Finished timing report (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 216MB peak: 217MB)
Finished timing report (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 216MB peak: 217MB)
---------------------------------------
Resource Usage Report
@@ -685,9 +688,9 @@ VHI: 3
VLO: 3
Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 79MB peak: 217MB)
At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 78MB peak: 217MB)
Process took 0h:00m:04s realtime, 0h:00m:04s cputime
# Thu Dec 28 23:09:54 2023
# Thu Dec 28 23:23:25 2023
###########################################################]

4
CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.tw1
View File

@@ -13,7 +13,7 @@ Setup and Hold Report
--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
Thu Dec 28 23:09:59 2023
Thu Dec 28 23:23:29 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
@@ -114,7 +114,7 @@ Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
Thu Dec 28 23:09:59 2023
Thu Dec 28 23:23:29 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.

4
CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.twr
View File

@@ -13,7 +13,7 @@ Setup and Hold Report
--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
Thu Dec 28 23:10:16 2023
Thu Dec 28 23:23:44 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
@@ -616,7 +616,7 @@ Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
Thu Dec 28 23:10:16 2023
Thu Dec 28 23:23:44 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.

2
CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_bgn.html
View File

@@ -12,7 +12,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;

2
CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_cck.rpt
View File

@@ -13,7 +13,7 @@ Hostname: ZANEMACWIN11
Implementation : impl1
# Written on Thu Dec 28 23:09:49 2023
# Written on Thu Dec 28 23:23:21 2023
##### DESIGN INFO #######################################################

2
CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_iotiming.html
View File

@@ -38,7 +38,7 @@ Performance Hardware Data Status: Final Version 34.4.
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}

2
CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_mapvo.sdf
View File

@@ -1,7 +1,7 @@
(DELAYFILE
(SDFVERSION "3.0")
(DESIGN "RAM2E")
(DATE "Thu Dec 28 23:10:01 2023")
(DATE "Thu Dec 28 23:23:31 2023")
(VENDOR "Lattice")
(PROGRAM "ldbanno")
(VERSION "Diamond (64-bit) 3.12.1.454")

4
CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_mapvo.vo
View File

@@ -2,8 +2,8 @@
// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454
// ldbanno -n Verilog -o RAM2E_LCMXO2_640HC_impl1_mapvo.vo -w -neg -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1_map.ncd
// Netlist created on Thu Dec 28 23:09:57 2023
// Netlist written on Thu Dec 28 23:10:01 2023
// Netlist created on Thu Dec 28 23:23:28 2023
// Netlist written on Thu Dec 28 23:23:31 2023
// Design is for device LCMXO2-640HC
// Design is for package TQFP100
// Design is for performance grade 4

2
CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_mrp.html
View File

@@ -23,7 +23,7 @@ Target Vendor: LATTICE
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {

4
CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_pad.html
View File

@@ -14,7 +14,7 @@ Performance Grade: 4
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
@@ -290,7 +290,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
Dedicated sysCONFIG Pins:
List of All Pins' Locate Preferences Based on Final Placement After PAR
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste):

50
CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_par.html
View File

@@ -12,7 +12,7 @@ Copyright (c) 1995 AT&amp;T Corp. All rights reserved.
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
@@ -26,17 +26,17 @@ Preference file: RAM2E_LCMXO2_640HC_impl1.prf.
margin-bottom: 5px;
font-size: 0.80em;
}
p {
p {
font-size:78%;
}
P.Table {
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
@@ -89,17 +89,17 @@ The following 1 signal is selected to use the secondary clock routing resources:
-->
</STYLE>
</HEAD>
</HEAD>
<PRE><A name="Par"></A>PAR: Place And Route Diamond (64-bit) 3.12.1.454.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&amp;T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Thu Dec 28 23:23:31 2023
C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2E_LCMXO2_640HC_impl1.p2t
RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.dir
RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.dir
RAM2E_LCMXO2_640HC_impl1.prf -gui -msgset
//Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml
@@ -137,7 +137,7 @@ I/O Bank Usage Summary:
Device: LCMXO2-640HC
Package: TQFP100
Performance: 4
Loading device for application par from file &apos;xo2c640.nph&apos; in environment: C:/lscc/diamond/3.12/ispfpga.
Loading device for application par from file &apos;xo2c640.nph&apos; in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.39.
Performance Hardware Data Status: Final Version 34.4.
License checked out.
@@ -145,9 +145,9 @@ Dumping design to file RAM2E_LCMXO2_640HC_impl1.dir/5_1.ncd.
Ignore Preference Error(s): True
<A name="par_dus"></A><B><U><big>Device utilization summary:</big></U></B>
<A name="par_dus"></A><B><U><big>Device utilization summary:</big></U></B>
PIO (prelim) 69+4(JTAG)/80 91% used
PIO (prelim) 69+4(JTAG)/80 91% used
69+4(JTAG)/79 92% bonded
IOLOGIC 29/80 36% used
@@ -162,35 +162,35 @@ Note: NBR uses a different method to calculate timing slacks. The
Pin Constraint Summary:
69 out of 69 pins locked (100% locked).
The following 1 signal is selected to use the primary clock routing resources:
The following 1 signal is selected to use the primary clock routing resources:
C14M_c (driver: C14M, clk load #: 89)
WARNING - par: Signal &quot;C14M_c&quot; is selected to use Primary clock resources. However, its driver comp &quot;C14M&quot; is located at &quot;62&quot;, which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
The following 1 signal is selected to use the secondary clock routing resources:
The following 1 signal is selected to use the secondary clock routing resources:
N_187_i (driver: ram2e_ufm/SLICE_130, clk load #: 0, sr load #: 0, ce load #: 11)
No signal is selected as Global Set/Reset.
Starting Placer Phase 0.
...........
...........
Finished Placer Phase 0. REAL time: 0 secs
Starting Placer Phase 1.
Starting Placer Phase 1.
....................
Placer score = 69810.
Finished Placer Phase 1. REAL time: 9 secs
Finished Placer Phase 1. REAL time: 7 secs
Starting Placer Phase 2.
.
.
Placer score = 69262
Finished Placer Phase 2. REAL time: 9 secs
Finished Placer Phase 2. REAL time: 7 secs
<A name="par_clk"></A><B><U><big>Clock Report</big></U></B>
Global Clock Resources:
CLK_PIN : 0 out of 8 (0%)
CLK_PIN : 0 out of 8 (0%)
General PIO: 1 out of 80 (1%)
DCM : 0 out of 2 (0%)
DCC : 0 out of 8 (0%)
@@ -205,8 +205,8 @@ Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored
I/O Usage Summary (final):
69 + 4(JTAG) out of 80 (91.3%) PIO sites used.
I/O Usage Summary (final):
69 + 4(JTAG) out of 80 (91.3%) PIO sites used.
69 + 4(JTAG) out of 79 (92.4%) bonded PIO sites used.
Number of PIO comps: 69; differential: 0.
Number of Vref pins used: 0.
@@ -228,8 +228,8 @@ PAR_SUMMARY::Worst slack&lt;hold /&lt;ns&gt;&gt; = 0.379
0 connections routed; 1330 unrouted.
Starting router resource preassignment
WARNING - par: The driver of primary clock net C14M_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
Completed router resource preassignment. Real time: 13 secs
Completed router resource preassignment. Real time: 11 secs
Start NBR router at 23:23:42 12/28/23

2
CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_scck.rpt
View File

@@ -13,7 +13,7 @@ Hostname: ZANEMACWIN11
Implementation : impl1
# Written on Thu Dec 28 23:09:48 2023
# Written on Thu Dec 28 23:23:20 2023
##### FILES SYNTAX CHECKED ##############################################
Constraint File(s): "\\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.sdc"

2
CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_summary.html
View File

@@ -62,7 +62,7 @@
}
a {
color:#013C9A;
text-decoration:none;
text-decoration:none;
}
a:visited {

85
CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_synplify.html
View File

@@ -12,7 +12,7 @@
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
@@ -61,19 +61,21 @@ Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 202
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
text-decoration:underline;
}
.pass
{
.pass
background-color: #00ff00;
}
.fail
{
@@ -82,25 +84,25 @@ Running optimization stage 1 on RAM2E .......
.comment
{
font-size: 90%;
{
font-style: italic;
}
}
-->
</STYLE>
-->
</HEAD>
<PRE><A name="Syn"></A><B><U><big>Synthesis Report</big></U></B>
</HEAD>
#Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021
#install: C:\lscc\diamond\3.12\synpbase
#Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021
#OS: Windows 8 6.2
#Hostname: ZANEMACWIN11
#OS: Windows 8 6.2
# Thu Dec 28 23:23:17 2023
#Implementation: impl1
Copyright (C) 1994-2021 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
@@ -121,13 +123,14 @@ Implementation : impl1
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: R-2021.03L-SP1
Install: C:\lscc\diamond\3.12\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
OS: Windows 6.2
Implementation : impl1
Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
@@ -137,12 +140,12 @@ For a summary of runtime and memory usage for all design units, please see file:
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"\\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.v" (library work)
@I::"\\Mac\iCloud\Repos\ram2e\CPLD\UFM-LCMXO2.v" (library work)
@I::"\\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\REFB.v" (library work)
Verilog syntax check successful!
@I::"\\Mac\iCloud\Repos\ram2e\CPLD\UFM-LCMXO2.v" (library work)
File \\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.v changed - recompiling
File \\Mac\iCloud\Repos\ram2e\CPLD\UFM-LCMXO2.v changed - recompiling
Selecting top level module RAM2E
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
@@ -170,10 +173,10 @@ At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s;
@N: CL159 :"\\Mac\iCloud\Repos\ram2e\CPLD\UFM-LCMXO2.v":10:7:10:11|Input Ready is unused.
Finished optimization stage 2 on RAM2E_UFM (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
Running optimization stage 2 on REFB .......
Running optimization stage 2 on REFB .......
Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
Running optimization stage 2 on EFB .......
Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
Running optimization stage 2 on VLO .......
Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
Running optimization stage 2 on VHI .......
Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
@@ -213,7 +216,7 @@ Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0
Process completed successfully.
# Thu Dec 28 23:23:18 2023
###########################################################]
###########################################################]
For a summary of runtime and memory usage for all design units, please see file:
==========================================================
@@ -240,20 +243,20 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h
Build: R-2021.03L-SP1
Install: C:\lscc\diamond\3.12\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Implementation : impl1
Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
@N|Running in 64-bit mode
@N|Running in 64-bit mode
File \\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_comp.srs changed - recompiling
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
Process completed successfully.
# Thu Dec 28 23:23:19 2023
###########################################################]
@@ -309,7 +312,7 @@ Clock Tree ID Driving Element Drive Element Type Fanout Sample I
@N: FX493 |Applying initial value "0" on instance CmdLEDGet.
@N: FX493 |Applying initial value "0" on instance CmdLEDSet.
@N: FX493 |Applying initial value "0" on instance CmdRWMaskSet.
@N: FX493 |Applying initial value "0" on instance CmdSetRWBankFFLED.
@N: FX493 |Applying initial value "0" on instance CmdSetRWBankFFLED.
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Initial value on register DQMH is non-zero which can prevent the register from being packed into a block RAM or DSP.
@N: FX493 |Applying initial value "1" on instance DQMH.
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Initial value on register DQML is non-zero which can prevent the register from being packed into a block RAM or DSP.
@@ -322,10 +325,10 @@ Pre-mapping successful!
@N: FX493 |Applying initial value "1" on instance nCAS.
@N: FX493 |Applying initial value "1" on instance nCASout.
@N: FX493 |Applying initial value "1" on instance nRAS.
@N: FX493 |Applying initial value "1" on instance nRASout.
@N: FX493 |Applying initial value "1" on instance nRASout.
Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
@@ -359,19 +362,19 @@ Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0
Clock Source Clock Pin Non-clock Pin Non-clock Pin
Clock Load Pin Seq Example Seq Example Comb Example
----------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------
C14M 122 C14M(port) DOEEN.C - un1_C14M.I[0](inv)
System 0 - - - -
========================================================================================
ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches removed: 0
Number of ICG latches not removed: 0
For details review file gcc_ICG_report.rpt
@S |Clock Optimization Summary
@S |Clock Optimization Summary
@@ -393,7 +396,7 @@ Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elaps
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
Finished Pre Mapping Phase.
Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
@@ -411,30 +414,30 @@ Finished technology timing optimizations and critical path resynthesis (Real Tim
###########################################################]
# Thu Dec 28 23:23:21 2023
Copyright (C) 1994-2021 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: R-2021.03L-SP1
Install: C:\lscc\diamond\3.12\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Implementation : impl1
Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
@N: MF916 |Option synthesis_strategy=base is enabled.
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 139MB)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 139MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 139MB)
@@ -656,10 +659,10 @@ ram2e_ufm.RWMask[0] FD1P3AX SP In
====================================
Detailed Report for Clock: System
====================================
Starting Points with Worst Slack
Starting Points with Worst Slack
********************************
Starting Arrival
@@ -694,10 +697,10 @@ VHI: 3
ram2e_ufm.RWMask[6] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088
ram2e_ufm.RWMask[7] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088
ram2e_ufm.LEDEN System FD1P3AX SP un1_LEDEN_0_sqmuxa_1_i_0_0[0] 69.369 67.736
ram2e_ufm.wb_cyc_stb System FD1P3AX SP un1_CmdSetRWBankFFChip13_1_i_0_0[0] 69.369 67.736
ram2e_ufm.wb_cyc_stb System FD1P3AX SP un1_CmdSetRWBankFFChip13_1_i_0_0[0] 69.369 67.736
======================================================================================================================
Worst Path Information
***********************

4
CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_tw1.html
View File

@@ -22,7 +22,7 @@ Setup and Hold Report
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
@@ -128,7 +128,7 @@ Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)
<LI><A href='#map_twr_pref_0_0' Target='right'>FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)</A></LI> 1611 items scored, 0 timing errors detected.
Report: 90.967MHz is the maximum frequency for this preference.
BLOCK ASYNCPATHS
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------

4
CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_twr.html
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@@ -22,7 +22,7 @@ Setup and Hold Report
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
@@ -630,7 +630,7 @@ Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q S[3] (from C14M_c +)
Destination: FF Data in ram2e_ufm/wb_adr[0] (to C14M_c +)
Destination: FF Data in ram2e_ufm/wb_adr[0] (to C14M_c +)
Delay: 10.978ns (31.2% logic, 68.8% route), 7 logic levels.

2
CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_vo.sdf
View File

@@ -1,7 +1,7 @@
(DELAYFILE
(SDFVERSION "3.0")
(DESIGN "RAM2E")
(DATE "Thu Dec 28 23:10:23 2023")
(DATE "Thu Dec 28 23:23:51 2023")
(VENDOR "Lattice")
(PROGRAM "ldbanno")
(VERSION "Diamond (64-bit) 3.12.1.454")

4
CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_vo.vo
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@@ -2,8 +2,8 @@
// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454
// ldbanno -n Verilog -o RAM2E_LCMXO2_640HC_impl1_vo.vo -w -neg -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd
// Netlist created on Thu Dec 28 23:09:57 2023
// Netlist written on Thu Dec 28 23:10:23 2023
// Netlist created on Thu Dec 28 23:23:28 2023
// Netlist written on Thu Dec 28 23:23:51 2023
// Design is for device LCMXO2-640HC
// Design is for package TQFP100
// Design is for performance grade 4

2
CPLD/LCMXO2-640HC/impl1/ram2e_lcmxo2_640hc_impl1.ior
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@@ -29,7 +29,7 @@ Performance Hardware Data Status: Final Version 34.4.
// Package: TQFP100
// ncd File: ram2e_lcmxo2_640hc_impl1.ncd
// Version: Diamond (64-bit) 3.12.1.454
// Written on Thu Dec 28 23:10:19 2023
// Written on Thu Dec 28 23:23:47 2023
// M: Minimum Performance Grade
// iotiming RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml

2
CPLD/LCMXO2-640HC/promote.xml
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@@ -1,3 +1,3 @@
<?xml version="1.0" encoding="UTF-8"?>
<userSetting name="//Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml" version="Diamond (64-bit) 3.12.1.454" date="Thu Dec 28 23:11:36 2023" vendor="Lattice Semiconductor Corporation" >
<userSetting name="//Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml" version="Diamond (64-bit) 3.12.1.454" date="Thu Dec 28 23:24:03 2023" vendor="Lattice Semiconductor Corporation" >
</userSetting>