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27 lines
1.0 KiB
Plaintext
27 lines
1.0 KiB
Plaintext
-- Copyright (C) 2019 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions
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-- and other software and tools, and any partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Intel Program License
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-- Subscription Agreement, the Intel Quartus Prime License Agreement,
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-- the Intel FPGA IP License Agreement, or other applicable license
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-- agreement, including, without limitation, that your use is for
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-- the sole purpose of programming logic devices manufactured by
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-- Intel and sold by Intel or its authorized distributors. Please
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-- refer to the applicable agreement for further details, at
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-- https://fpgasoftware.intel.com/eula.
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-- Quartus Prime generated Memory Initialization File (.mif)
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WIDTH=16;
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DEPTH=512;
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ADDRESS_RADIX=HEX;
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DATA_RADIX=HEX;
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CONTENT BEGIN
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[000..1FF] : FFFF;
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END;
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