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This commit is contained in:
Zane Kaminski 2023-12-28 23:12:12 -05:00
parent 1b7e00193a
commit e73d7034d8
104 changed files with 44355 additions and 33233 deletions
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5
CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC.ldf
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@ -3,9 +3,12 @@
<Options/>
<Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
<Options def_top="RAM2E" top="RAM2E"/>
<Source name="../RAM2E-LCMXO2.v" type="Verilog" type_short="Verilog">
<Source name="../RAM2E.v" type="Verilog" type_short="Verilog">
<Options top_module="RAM2E"/>
</Source>
<Source name="../UFM-LCMXO2.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="REFB.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>

51
CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC_tcl.html
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@ -6,13 +6,56 @@
-->
</STYLE>
</HEAD>
<PRE><A name="pn230921045934"></A><B><U><big>pn230921045934</big></U></B>
#Start recording tcl command: 9/21/2023 04:58:28
<PRE><A name="pn231218062259"></A><B><U><big>pn231218062259</big></U></B>
#Start recording tcl command: 12/5/2023 23:09:24
#Project Location: //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC; Project name: RAM2E_LCMXO2_1200HC
prj_project open "//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC.ldf"
prj_run PAR -impl impl1 -task IOTiming
prj_run Export -impl impl1
prj_run Export -impl impl1
#Stop recording: 12/18/2023 06:22:59
<A name="pn231226182753"></A><B><U><big>pn231226182753</big></U></B>
#Start recording tcl command: 12/26/2023 18:26:59
#Project Location: //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC; Project name: RAM2E_LCMXO2_1200HC
prj_project open "//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC.ldf"
#Stop recording: 12/26/2023 18:27:53
<A name="pn231226232448"></A><B><U><big>pn231226232448</big></U></B>
#Start recording tcl command: 12/26/2023 21:40:03
#Project Location: //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC; Project name: RAM2E_LCMXO2_1200HC
prj_project open "//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC.ldf"
prj_run Export -impl impl1
prj_run Export -impl impl1 -forceAll
#Stop recording: 9/21/2023 04:59:34
prj_run Export -impl impl1 -forceAll
prj_run Export -impl impl1 -forceAll
prj_run Export -impl impl1 -forceAll
prj_src exclude "//Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.v"
prj_src remove "//Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.v"
#Stop recording: 12/26/2023 23:24:48
<A name="pn231226233648"></A><B><U><big>pn231226233648</big></U></B>
#Start recording tcl command: 12/26/2023 23:26:30
#Project Location: //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC; Project name: RAM2E_LCMXO2_1200HC
prj_project open "//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC.ldf"
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1
prj_run Export -impl impl1 -forceAll
#Stop recording: 12/26/2023 23:36:48
<A name="pn231226233754"></A><B><U><big>pn231226233754</big></U></B>
#Start recording tcl command: 12/26/2023 23:36:58
#Project Location: //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC; Project name: RAM2E_LCMXO2_1200HC
prj_project open "//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC.ldf"
#Stop recording: 12/26/2023 23:37:54

41
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.alt
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@ -1,14 +1,12 @@
NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
NOTE All Rights Reserved *
NOTE DATE CREATED: Thu Sep 21 05:35:26 2023 *
NOTE DATE CREATED: Thu Dec 28 23:10:34 2023 *
NOTE DESIGN NAME: RAM2E *
NOTE DEVICE NAME: LCMXO2-1200HC-4TQFP100 *
NOTE PIN ASSIGNMENTS *
NOTE PINS RD[0] : 36 : inout *
NOTE PINS LED : 35 : out *
NOTE PINS C14M : 62 : in *
NOTE PINS DQMH : 49 : out *
NOTE PINS DQML : 48 : out *
NOTE PINS RD[7] : 43 : inout *
NOTE PINS RD[6] : 42 : inout *
NOTE PINS RD[5] : 41 : inout *
@ -16,25 +14,27 @@ NOTE PINS RD[4] : 40 : inout *
NOTE PINS RD[3] : 39 : inout *
NOTE PINS RD[2] : 38 : inout *
NOTE PINS RD[1] : 37 : inout *
NOTE PINS RA[11] : 59 : out *
NOTE PINS RA[10] : 64 : out *
NOTE PINS RA[9] : 63 : out *
NOTE PINS RA[8] : 65 : out *
NOTE PINS RA[7] : 67 : out *
NOTE PINS RA[6] : 69 : out *
NOTE PINS RA[5] : 71 : out *
NOTE PINS RA[4] : 75 : out *
NOTE PINS RA[3] : 74 : out *
NOTE PINS RA[2] : 70 : out *
NOTE PINS RA[1] : 68 : out *
NOTE PINS RA[0] : 66 : out *
NOTE PINS DQMH : 49 : out *
NOTE PINS DQML : 48 : out *
NOTE PINS RAout[11] : 59 : out *
NOTE PINS RAout[10] : 64 : out *
NOTE PINS RAout[9] : 63 : out *
NOTE PINS RAout[8] : 65 : out *
NOTE PINS RAout[7] : 67 : out *
NOTE PINS RAout[6] : 69 : out *
NOTE PINS RAout[5] : 71 : out *
NOTE PINS RAout[4] : 75 : out *
NOTE PINS RAout[3] : 74 : out *
NOTE PINS RAout[2] : 70 : out *
NOTE PINS RAout[1] : 68 : out *
NOTE PINS RAout[0] : 66 : out *
NOTE PINS BA[1] : 60 : out *
NOTE PINS BA[0] : 58 : out *
NOTE PINS nRWE : 51 : out *
NOTE PINS nCAS : 52 : out *
NOTE PINS nRAS : 54 : out *
NOTE PINS nCS : 57 : out *
NOTE PINS CKE : 53 : out *
NOTE PINS nRWEout : 51 : out *
NOTE PINS nCASout : 52 : out *
NOTE PINS nRASout : 54 : out *
NOTE PINS nCSout : 57 : out *
NOTE PINS CKEout : 53 : out *
NOTE PINS nVOE : 10 : out *
NOTE PINS Vout[7] : 12 : out *
NOTE PINS Vout[6] : 14 : out *
@ -71,7 +71,6 @@ NOTE PINS Ain[1] : 2 : in *
NOTE PINS Ain[0] : 3 : in *
NOTE PINS nC07X : 34 : in *
NOTE PINS nEN80 : 82 : in *
NOTE PINS nWE80 : 83 : in *
NOTE PINS nWE : 29 : in *
NOTE PINS PHI1 : 85 : in *
NOTE CONFIGURATION MODE: NONE *

52
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.areasrr
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@ -1,41 +1,61 @@
----------------------------------------------------------------------
Report for cell RAM2E.verilog
Register bits: 111 of 1280 (9%)
Register bits: 122 of 1280 (10%)
PIC Latch: 0
I/O cells: 70
I/O cells: 69
Cell usage:
cell count Res Usage(%)
BB 8 100.0
CCU2D 9 100.0
EFB 1 100.0
FD1P3AX 48 100.0
FD1P3AX 61 100.0
FD1P3IX 1 100.0
FD1S3AX 22 100.0
FD1S3IX 4 100.0
FD1S3AX 21 100.0
FD1S3AY 4 100.0
FD1S3IX 6 100.0
GSR 1 100.0
IB 22 100.0
IB 21 100.0
IFS1P3DX 1 100.0
INV 1 100.0
OB 40 100.0
OFS1P3BX 6 100.0
OFS1P3DX 27 100.0
OFS1P3BX 5 100.0
OFS1P3DX 21 100.0
OFS1P3IX 2 100.0
ORCALUT4 221 100.0
ORCALUT4 277 100.0
PFUMX 3 100.0
PUR 1 100.0
VHI 2 100.0
VLO 2 100.0
VHI 3 100.0
VLO 3 100.0
SUB MODULES
RAM2E_UFM 1 100.0
REFB 1 100.0
TOTAL 420
TOTAL 492
----------------------------------------------------------------------
Report for cell REFB.netlist
Instance path: ufmefb
Report for cell RAM2E_UFM.netlist
Instance path: ram2e_ufm
Cell usage:
cell count Res Usage(%)
EFB 1 100.0
VHI 1 50.0
VLO 1 50.0
FD1P3AX 30 49.2
FD1P3IX 1 100.0
FD1S3IX 1 16.7
ORCALUT4 272 98.2
PFUMX 3 100.0
VHI 2 66.7
VLO 2 66.7
SUB MODULES
REFB 1 100.0
TOTAL 313
----------------------------------------------------------------------
Report for cell REFB.netlist
Instance path: ram2e_ufm.ufmefb
Cell usage:
cell count Res Usage(%)
EFB 1 100.0
VHI 1 33.3
VLO 1 33.3
TOTAL 3

6
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.bgn
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@ -4,7 +4,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Thu Sep 21 05:35:21 2023
Thu Dec 28 23:10:30 2023
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC -w -jedec -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1.ncd RAM2E_LCMXO2_1200HC_impl1.prf
@ -81,6 +81,6 @@ UFM Utilization: General Purpose Flash Memory.
Available General Purpose Flash Memory: 511 Pages (Page 0 to Page 510).
Initialized UFM Pages: 321 Pages (Page 190 to Page 510).
Total CPU Time: 4 secs
Total REAL Time: 5 secs
Total CPU Time: 3 secs
Total REAL Time: 4 secs
Peak Memory Usage: 275 MB

BIN
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.bit
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Binary file not shown.

6972
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.edi
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File diff suppressed because it is too large Load Diff

1183
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.jed
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File diff suppressed because it is too large Load Diff

356
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.mrp
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@ -15,24 +15,24 @@ Target Vendor: LATTICE
Target Device: LCMXO2-1200HCTQFP100
Target Performance: 4
Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454
Mapped on: 09/21/23 05:34:46
Mapped on: 12/28/23 23:09:57
Design Summary
--------------
Number of registers: 111 out of 1520 (7%)
PFU registers: 75 out of 1280 (6%)
PIO registers: 36 out of 240 (15%)
Number of SLICEs: 120 out of 640 (19%)
SLICEs as Logic/ROM: 120 out of 640 (19%)
Number of registers: 122 out of 1520 (8%)
PFU registers: 93 out of 1280 (7%)
PIO registers: 29 out of 240 (12%)
Number of SLICEs: 148 out of 640 (23%)
SLICEs as Logic/ROM: 148 out of 640 (23%)
SLICEs as RAM: 0 out of 480 (0%)
SLICEs as Carry: 9 out of 640 (1%)
Number of LUT4s: 239 out of 1280 (19%)
Number used as logic LUTs: 221
Number of LUT4s: 296 out of 1280 (23%)
Number used as logic LUTs: 278
Number used as distributed RAM: 0
Number used as ripple logic: 18
Number used as shift registers: 0
Number of PIO sites used: 70 + 4(JTAG) out of 80 (93%)
Number of PIO sites used: 69 + 4(JTAG) out of 80 (91%)
Number of block RAMs: 0 out of 7 (0%)
Number of GSRs: 0 out of 1 (0%)
EFB used : Yes
@ -58,64 +58,82 @@ Design Summary
2. Number of logic LUT4s does not include count of distributed RAM and
ripple logic.
Number of clocks: 1
Net C14M_c: 84 loads, 68 rising, 16 falling (Driver: PIO C14M )
Number of Clock Enables: 11
Net C14M_c: 89 loads, 73 rising, 16 falling (Driver: PIO C14M )
Number of Clock Enables: 14
Page 1
Design: RAM2E Date: 09/21/23 05:34:46
Design: RAM2E Date: 12/28/23 23:09:57
Design Summary (cont)
---------------------
Net wb_adr_0_sqmuxa_i: 1 loads, 1 LSLICEs
Net N_576_i: 17 loads, 9 LSLICEs
Net LEDEN13: 4 loads, 4 LSLICEs
Net nCS61: 1 loads, 1 LSLICEs
Net N_225_i: 2 loads, 0 LSLICEs
Net N_201_i: 2 loads, 0 LSLICEs
Net N_187_i: 11 loads, 11 LSLICEs
Net ram2e_ufm/wb_adr_0_sqmuxa_1_i: 1 loads, 1 LSLICEs
Net RC12: 2 loads, 2 LSLICEs
Net ram2e_ufm/CmdBitbangMXO2_RNINSM62: 8 loads, 8 LSLICEs
Net ram2e_ufm/wb_we_RNO_0: 1 loads, 1 LSLICEs
Net N_185_i: 2 loads, 2 LSLICEs
Net ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0]: 1 loads, 1 LSLICEs
Net ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0]: 4 loads, 4 LSLICEs
Net ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0]: 1 loads, 1 LSLICEs
Net N_126: 6 loads, 6 LSLICEs
Net un9_VOEEN_0_a2_0_a3_0_a3: 1 loads, 1 LSLICEs
Net Vout3: 8 loads, 0 LSLICEs
Net S_RNII9DO1_1[1]: 7 loads, 1 LSLICEs
Net un1_wb_cyc_stb_0_sqmuxa_1_i[0]: 1 loads, 1 LSLICEs
Net un1_wb_adr_0_sqmuxa_2_i[0]: 8 loads, 8 LSLICEs
Net N_104: 1 loads, 1 LSLICEs
Net N_88: 4 loads, 4 LSLICEs
Net un1_LEDEN_0_sqmuxa_1_i_0[0]: 1 loads, 1 LSLICEs
Number of LSRs: 5
Number of LSRs: 7
Net un1_CS_0_sqmuxa_i: 2 loads, 2 LSLICEs
Net BA_0_sqmuxa: 2 loads, 0 LSLICEs
Net S[2]: 1 loads, 1 LSLICEs
Net N_566_i: 2 loads, 0 LSLICEs
Net wb_rst: 1 loads, 0 LSLICEs
Net S_RNII9DO1[1]: 1 loads, 1 LSLICEs
Net ram2e_ufm/wb_rst: 1 loads, 0 LSLICEs
Net ram2e_ufm/wb_rst16_i: 1 loads, 1 LSLICEs
Net N_1080_0: 1 loads, 1 LSLICEs
Net N_1078_0: 1 loads, 1 LSLICEs
Number of nets driven by tri-state buffers: 0
Top 10 highest fanout non-clock nets:
Net S[2]: 48 loads
Net S[3]: 48 loads
Net S[0]: 30 loads
Net FS[12]: 22 loads
Net FS[9]: 21 loads
Net S[1]: 21 loads
Net FS[10]: 20 loads
Net FS[11]: 19 loads
Net RWSel: 19 loads
Net FS[13]: 17 loads
Net S[2]: 50 loads
Net S[3]: 45 loads
Net S[0]: 37 loads
Net S[1]: 34 loads
Net FS[12]: 24 loads
Net FS[11]: 22 loads
Net FS[10]: 19 loads
Net FS[13]: 19 loads
Net FS[9]: 19 loads
Net FS[8]: 18 loads
Number of warnings: 1
Number of warnings: 3
Number of errors: 0
Design Errors/Warnings
----------------------
WARNING - map: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf(93): Semantic
error in "IOBUF PORT "nWE80" IO_TYPE=LVCMOS33 PULLMODE=NONE ;": Port
"nWE80" does not exist in the design. This preference has been disabled.
WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
temporarily disable certain features of the device including Power
Controller, GSR, Hardened User SPI Port, Hardened Primary User I2C Port.
Functionality is restored after the Flash Memory (UFM/Configuration)
Interface is disabled using Disable Configuration Interface command 0x26
followed by Bypass command 0xFF.
WARNING - map: IO buffer missing for top level port nWE80...logic will be
discarded.
Page 2
Design: RAM2E Date: 12/28/23 23:09:57
IO (PIO) Attributes
-------------------
@ -126,24 +144,10 @@ IO (PIO) Attributes
+---------------------+-----------+-----------+------------+
| RD[0] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
Page 2
Design: RAM2E Date: 09/21/23 05:34:46
IO (PIO) Attributes (cont)
--------------------------
| LED | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| C14M | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| DQMH | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| DQML | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RD[7] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[6] | BIDIR | LVCMOS33 | |
@ -158,39 +162,35 @@ IO (PIO) Attributes (cont)
+---------------------+-----------+-----------+------------+
| RD[1] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RA[11] | OUTPUT | LVCMOS33 | OUT |
| DQMH | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RA[10] | OUTPUT | LVCMOS33 | OUT |
| DQML | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RA[9] | OUTPUT | LVCMOS33 | OUT |
| RAout[11] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RA[8] | OUTPUT | LVCMOS33 | OUT |
| RAout[10] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RA[7] | OUTPUT | LVCMOS33 | OUT |
| RAout[9] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RA[6] | OUTPUT | LVCMOS33 | OUT |
| RAout[8] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RA[5] | OUTPUT | LVCMOS33 | OUT |
| RAout[7] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RA[4] | OUTPUT | LVCMOS33 | OUT |
| RAout[6] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RA[3] | OUTPUT | LVCMOS33 | |
| RAout[5] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RA[2] | OUTPUT | LVCMOS33 | OUT |
| RAout[4] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RA[1] | OUTPUT | LVCMOS33 | OUT |
| RAout[3] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RA[0] | OUTPUT | LVCMOS33 | |
| RAout[2] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RAout[1] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RAout[0] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| BA[1] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| BA[0] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nRWE | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nCAS | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nRAS | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
Page 3
@ -198,13 +198,21 @@ IO (PIO) Attributes (cont)
Design: RAM2E Date: 09/21/23 05:34:46
Design: RAM2E Date: 12/28/23 23:09:57
IO (PIO) Attributes (cont)
--------------------------
| nCS | OUTPUT | LVCMOS33 | OUT |
| BA[0] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| CKE | OUTPUT | LVCMOS33 | OUT |
| nRWEout | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nCASout | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nRASout | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nCSout | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| CKEout | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nVOE | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
@ -226,21 +234,21 @@ IO (PIO) Attributes (cont)
+---------------------+-----------+-----------+------------+
| nDOE | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[7] | OUTPUT | LVCMOS33 | OUT |
| Dout[7] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[6] | OUTPUT | LVCMOS33 | OUT |
| Dout[6] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[5] | OUTPUT | LVCMOS33 | OUT |
| Dout[5] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[4] | OUTPUT | LVCMOS33 | OUT |
| Dout[4] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[3] | OUTPUT | LVCMOS33 | OUT |
| Dout[3] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[2] | OUTPUT | LVCMOS33 | OUT |
| Dout[2] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[1] | OUTPUT | LVCMOS33 | OUT |
| Dout[1] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[0] | OUTPUT | LVCMOS33 | OUT |
| Dout[0] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[7] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
@ -250,6 +258,16 @@ IO (PIO) Attributes (cont)
+---------------------+-----------+-----------+------------+
| Din[4] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
Page 4
Design: RAM2E Date: 12/28/23 23:09:57
IO (PIO) Attributes (cont)
--------------------------
| Din[3] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[2] | INPUT | LVCMOS33 | |
@ -258,16 +276,6 @@ IO (PIO) Attributes (cont)
+---------------------+-----------+-----------+------------+
| Din[0] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
Page 4
Design: RAM2E Date: 09/21/23 05:34:46
IO (PIO) Attributes (cont)
--------------------------
| Ain[7] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[6] | INPUT | LVCMOS33 | |
@ -288,8 +296,6 @@ IO (PIO) Attributes (cont)
+---------------------+-----------+-----------+------------+
| nEN80 | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nWE80 | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nWE | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| PHI1 | INPUT | LVCMOS33 | IN |
@ -299,77 +305,84 @@ Removed logic
-------------
Block GSR_INST undriven or does not drive anything - clipped.
Signal Dout_0_.CN was merged into signal C14M_c
Signal GND undriven or does not drive anything - clipped.
Signal ufmefb/VCC undriven or does not drive anything - clipped.
Signal ufmefb/GND undriven or does not drive anything - clipped.
Block ram2e_ufm/VCC undriven or does not drive anything - clipped.
Block ram2e_ufm/GND undriven or does not drive anything - clipped.
Signal CKEout.CN was merged into signal C14M_c
Signal ram2e_ufm/ufmefb/VCC undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/GND undriven or does not drive anything - clipped.
Signal FS_s_0_S1[15] undriven or does not drive anything - clipped.
Signal FS_s_0_COUT[15] undriven or does not drive anything - clipped.
Signal ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
Signal ufmefb/CFGWAKE undriven or does not drive anything - clipped.
Signal ufmefb/wbc_ufm_irq undriven or does not drive anything - clipped.
Signal ufmefb/TCOC undriven or does not drive anything - clipped.
Signal ufmefb/TCINT undriven or does not drive anything - clipped.
Signal ufmefb/SPIIRQO undriven or does not drive anything - clipped.
Signal ufmefb/SPICSNEN undriven or does not drive anything - clipped.
Signal ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
Signal ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
Signal ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
Signal ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
Signal ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
Signal ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
Signal ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
Signal ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
Signal ufmefb/SPIMOSIEN undriven or does not drive anything - clipped.
Signal ufmefb/SPIMOSIO undriven or does not drive anything - clipped.
Signal ufmefb/SPIMISOEN undriven or does not drive anything - clipped.
Signal ufmefb/SPIMISOO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/CFGWAKE undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/wbc_ufm_irq undriven or does not drive anything -
clipped.
Signal ram2e_ufm/ufmefb/TCOC undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/TCINT undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIIRQO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPICSNEN undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
Page 5
Design: RAM2E Date: 09/21/23 05:34:46
Design: RAM2E Date: 12/28/23 23:09:57
Removed logic (cont)
--------------------
Signal ufmefb/SPISCKEN undriven or does not drive anything - clipped.
Signal ufmefb/SPISCKO undriven or does not drive anything - clipped.
Signal ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
Signal ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
Signal ufmefb/I2C2SDAOEN undriven or does not drive anything - clipped.
Signal ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
Signal ufmefb/I2C2SCLOEN undriven or does not drive anything - clipped.
Signal ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
Signal ufmefb/I2C1SDAOEN undriven or does not drive anything - clipped.
Signal ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
Signal ufmefb/I2C1SCLOEN undriven or does not drive anything - clipped.
Signal ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
Signal ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
Signal ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
Signal ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
Signal ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
Signal ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
Signal ufmefb/PLLADRO4 undriven or does not drive anything - clipped.
Signal ufmefb/PLLWEO undriven or does not drive anything - clipped.
Signal ufmefb/PLL1STBO undriven or does not drive anything - clipped.
Signal ufmefb/PLL0STBO undriven or does not drive anything - clipped.
Signal ufmefb/PLLRSTO undriven or does not drive anything - clipped.
Signal ufmefb/PLLCLKO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMOSIEN undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMOSIO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMISOEN undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMISOO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPISCKEN undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPISCKO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C2SDAOEN undriven or does not drive anything -
clipped.
Signal ram2e_ufm/ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C2SCLOEN undriven or does not drive anything -
clipped.
Signal ram2e_ufm/ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C1SDAOEN undriven or does not drive anything -
clipped.
Signal ram2e_ufm/ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C1SCLOEN undriven or does not drive anything -
clipped.
Signal ram2e_ufm/ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLADRO4 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLWEO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLL1STBO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLL0STBO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLRSTO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLCLKO undriven or does not drive anything - clipped.
Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped.
Signal N_1 undriven or does not drive anything - clipped.
Block Vout_0_.CN was optimized away.
Block GND was optimized away.
Block ufmefb/VCC was optimized away.
Block ufmefb/GND was optimized away.
Block nCASout.CN was optimized away.
Block ram2e_ufm/ufmefb/VCC was optimized away.
Block ram2e_ufm/ufmefb/GND was optimized away.
@ -377,8 +390,18 @@ Embedded Functional Block Connection Summary
--------------------------------------------
Desired WISHBONE clock frequency: 14.4 MHz
Page 6
Design: RAM2E Date: 12/28/23 23:09:57
Embedded Functional Block Connection Summary (cont)
---------------------------------------------------
Clock source: C14M_c
Reset source: wb_rst
Reset source: ram2e_ufm/wb_rst
Functions mode:
I2C #1 (Primary) Function: DISABLED
I2C #2 (Secondary) Function: DISABLED
@ -390,16 +413,6 @@ Embedded Functional Block Connection Summary
PLL1 Connection: DISABLED
I2C Function Summary:
--------------------
Page 6
Design: RAM2E Date: 09/21/23 05:34:46
Embedded Functional Block Connection Summary (cont)
---------------------------------------------------
None
SPI Function Summary:
--------------------
@ -424,7 +437,7 @@ Embedded Functional Block Connection Summary (cont)
ASIC Components
---------------
Instance Name: ufmefb/EFBInst_0
Instance Name: ram2e_ufm/ufmefb/EFBInst_0
Type: EFB
Run Time and Memory Usage
@ -432,23 +445,10 @@ Run Time and Memory Usage
Total CPU Time: 1 secs
Total REAL Time: 0 secs
Peak Memory Usage: 63 MB
Peak Memory Usage: 64 MB

126
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.pad
View File

@ -6,7 +6,7 @@ Performance Grade: 4
PACKAGE: TQFP100
Package Status: Final Version 1.44
Thu Sep 21 05:34:59 2023
Thu Dec 28 23:10:10 2023
Pinout by Port Name:
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
@ -23,7 +23,7 @@ Pinout by Port Name:
| BA[0] | 58/1 | LVCMOS33_OUT | PR9A | | | DRIVE:4mA SLEW:SLOW |
| BA[1] | 60/1 | LVCMOS33_OUT | PR8C | | | DRIVE:4mA SLEW:SLOW |
| C14M | 62/1 | LVCMOS33_IN | PR5D | | | CLAMP:ON HYSTERESIS:SMALL |
| CKE | 53/1 | LVCMOS33_OUT | PR9D | | | DRIVE:4mA SLEW:SLOW |
| CKEout | 53/1 | LVCMOS33_OUT | PR9D | | | DRIVE:4mA SLEW:SLOW |
| DQMH | 49/2 | LVCMOS33_OUT | PB20D | | | DRIVE:4mA SLEW:SLOW |
| DQML | 48/2 | LVCMOS33_OUT | PB20C | | | DRIVE:4mA SLEW:SLOW |
| Din[0] | 96/0 | LVCMOS33_IN | PT10B | | | CLAMP:ON HYSTERESIS:SMALL |
@ -34,28 +34,28 @@ Pinout by Port Name:
| Din[5] | 99/0 | LVCMOS33_IN | PT9A | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[6] | 88/0 | LVCMOS33_IN | PT12A | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[7] | 87/0 | LVCMOS33_IN | PT12B | | | CLAMP:ON HYSTERESIS:SMALL |
| Dout[0] | 30/2 | LVCMOS33_OUT | PB6B | | | DRIVE:4mA SLEW:FAST |
| Dout[1] | 27/2 | LVCMOS33_OUT | PB4C | | | DRIVE:4mA SLEW:FAST |
| Dout[2] | 25/3 | LVCMOS33_OUT | PL10D | | | DRIVE:4mA SLEW:FAST |
| Dout[3] | 28/2 | LVCMOS33_OUT | PB4D | | | DRIVE:4mA SLEW:FAST |
| Dout[4] | 24/3 | LVCMOS33_OUT | PL10C | | | DRIVE:4mA SLEW:FAST |
| Dout[5] | 21/3 | LVCMOS33_OUT | PL9B | | | DRIVE:4mA SLEW:FAST |
| Dout[6] | 31/2 | LVCMOS33_OUT | PB6C | | | DRIVE:4mA SLEW:FAST |
| Dout[7] | 32/2 | LVCMOS33_OUT | PB6D | | | DRIVE:4mA SLEW:FAST |
| Dout[0] | 30/2 | LVCMOS33_OUT | PB6B | | | DRIVE:4mA SLEW:SLOW |
| Dout[1] | 27/2 | LVCMOS33_OUT | PB4C | | | DRIVE:4mA SLEW:SLOW |
| Dout[2] | 25/3 | LVCMOS33_OUT | PL10D | | | DRIVE:4mA SLEW:SLOW |
| Dout[3] | 28/2 | LVCMOS33_OUT | PB4D | | | DRIVE:4mA SLEW:SLOW |
| Dout[4] | 24/3 | LVCMOS33_OUT | PL10C | | | DRIVE:4mA SLEW:SLOW |
| Dout[5] | 21/3 | LVCMOS33_OUT | PL9B | | | DRIVE:4mA SLEW:SLOW |
| Dout[6] | 31/2 | LVCMOS33_OUT | PB6C | | | DRIVE:4mA SLEW:SLOW |
| Dout[7] | 32/2 | LVCMOS33_OUT | PB6D | | | DRIVE:4mA SLEW:SLOW |
| LED | 35/2 | LVCMOS33_OUT | PB9B | | | DRIVE:4mA SLEW:SLOW |
| PHI1 | 85/0 | LVCMOS33_IN | PT12D | | | CLAMP:ON HYSTERESIS:SMALL |
| RA[0] | 66/1 | LVCMOS33_OUT | PR4D | | | DRIVE:4mA SLEW:SLOW |
| RA[10] | 64/1 | LVCMOS33_OUT | PR5B | | | DRIVE:4mA SLEW:SLOW |
| RA[11] | 59/1 | LVCMOS33_OUT | PR8D | | | DRIVE:4mA SLEW:SLOW |
| RA[1] | 68/1 | LVCMOS33_OUT | PR4B | | | DRIVE:4mA SLEW:SLOW |
| RA[2] | 70/1 | LVCMOS33_OUT | PR3B | | | DRIVE:4mA SLEW:SLOW |
| RA[3] | 74/1 | LVCMOS33_OUT | PR2B | | | DRIVE:4mA SLEW:SLOW |
| RA[4] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA SLEW:SLOW |
| RA[5] | 71/1 | LVCMOS33_OUT | PR3A | | | DRIVE:4mA SLEW:SLOW |
| RA[6] | 69/1 | LVCMOS33_OUT | PR4A | | | DRIVE:4mA SLEW:SLOW |
| RA[7] | 67/1 | LVCMOS33_OUT | PR4C | | | DRIVE:4mA SLEW:SLOW |
| RA[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA SLEW:SLOW |
| RA[9] | 63/1 | LVCMOS33_OUT | PR5C | | | DRIVE:4mA SLEW:SLOW |
| RAout[0] | 66/1 | LVCMOS33_OUT | PR4D | | | DRIVE:4mA SLEW:SLOW |
| RAout[10] | 64/1 | LVCMOS33_OUT | PR5B | | | DRIVE:4mA SLEW:SLOW |
| RAout[11] | 59/1 | LVCMOS33_OUT | PR8D | | | DRIVE:4mA SLEW:SLOW |
| RAout[1] | 68/1 | LVCMOS33_OUT | PR4B | | | DRIVE:4mA SLEW:SLOW |
| RAout[2] | 70/1 | LVCMOS33_OUT | PR3B | | | DRIVE:4mA SLEW:SLOW |
| RAout[3] | 74/1 | LVCMOS33_OUT | PR2B | | | DRIVE:4mA SLEW:SLOW |
| RAout[4] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA SLEW:SLOW |
| RAout[5] | 71/1 | LVCMOS33_OUT | PR3A | | | DRIVE:4mA SLEW:SLOW |
| RAout[6] | 69/1 | LVCMOS33_OUT | PR4A | | | DRIVE:4mA SLEW:SLOW |
| RAout[7] | 67/1 | LVCMOS33_OUT | PR4C | | | DRIVE:4mA SLEW:SLOW |
| RAout[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA SLEW:SLOW |
| RAout[9] | 63/1 | LVCMOS33_OUT | PR5C | | | DRIVE:4mA SLEW:SLOW |
| RD[0] | 36/2 | LVCMOS33_BIDI | PB11C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[1] | 37/2 | LVCMOS33_BIDI | PB11D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[2] | 38/2 | LVCMOS33_BIDI | PB11A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
@ -73,15 +73,14 @@ Pinout by Port Name:
| Vout[6] | 14/3 | LVCMOS33_OUT | PL5C | | | DRIVE:4mA SLEW:SLOW |
| Vout[7] | 12/3 | LVCMOS33_OUT | PL5A | | | DRIVE:4mA SLEW:SLOW |
| nC07X | 34/2 | LVCMOS33_IN | PB9A | | | CLAMP:ON HYSTERESIS:SMALL |
| nCAS | 52/1 | LVCMOS33_OUT | PR10C | | | DRIVE:4mA SLEW:SLOW |
| nCS | 57/1 | LVCMOS33_OUT | PR9B | | | DRIVE:4mA SLEW:SLOW |
| nCASout | 52/1 | LVCMOS33_OUT | PR10C | | | DRIVE:4mA SLEW:SLOW |
| nCSout | 57/1 | LVCMOS33_OUT | PR9B | | | DRIVE:4mA SLEW:SLOW |
| nDOE | 20/3 | LVCMOS33_OUT | PL9A | | | DRIVE:4mA SLEW:SLOW |
| nEN80 | 82/0 | LVCMOS33_IN | PT15C | | | CLAMP:ON HYSTERESIS:SMALL |
| nRAS | 54/1 | LVCMOS33_OUT | PR9C | | | DRIVE:4mA SLEW:SLOW |
| nRWE | 51/1 | LVCMOS33_OUT | PR10D | | | DRIVE:4mA SLEW:SLOW |
| nRASout | 54/1 | LVCMOS33_OUT | PR9C | | | DRIVE:4mA SLEW:SLOW |
| nRWEout | 51/1 | LVCMOS33_OUT | PR10D | | | DRIVE:4mA SLEW:SLOW |
| nVOE | 10/3 | LVCMOS33_OUT | PL4B | | | DRIVE:4mA SLEW:SLOW |
| nWE | 29/2 | LVCMOS33_IN | PB6A | | | CLAMP:ON HYSTERESIS:SMALL |
| nWE80 | 83/0 | LVCMOS33_IN | PT15B | | | CLAMP:ON HYSTERESIS:SMALL |
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
Vccio by Bank:
@ -144,33 +143,33 @@ Pinout by Pin Number:
| 47/2 | unused, PULL:DOWN | | | PB18D | | | |
| 48/2 | DQML | LOCATED | LVCMOS33_OUT | PB20C | SN | | |
| 49/2 | DQMH | LOCATED | LVCMOS33_OUT | PB20D | SI/SISPI | | |
| 51/1 | nRWE | LOCATED | LVCMOS33_OUT | PR10D | DQ1 | | |
| 52/1 | nCAS | LOCATED | LVCMOS33_OUT | PR10C | DQ1 | | |
| 53/1 | CKE | LOCATED | LVCMOS33_OUT | PR9D | DQ1 | | |
| 54/1 | nRAS | LOCATED | LVCMOS33_OUT | PR9C | DQ1 | | |
| 57/1 | nCS | LOCATED | LVCMOS33_OUT | PR9B | DQ1 | | |
| 51/1 | nRWEout | LOCATED | LVCMOS33_OUT | PR10D | DQ1 | | |
| 52/1 | nCASout | LOCATED | LVCMOS33_OUT | PR10C | DQ1 | | |
| 53/1 | CKEout | LOCATED | LVCMOS33_OUT | PR9D | DQ1 | | |
| 54/1 | nRASout | LOCATED | LVCMOS33_OUT | PR9C | DQ1 | | |
| 57/1 | nCSout | LOCATED | LVCMOS33_OUT | PR9B | DQ1 | | |
| 58/1 | BA[0] | LOCATED | LVCMOS33_OUT | PR9A | DQ1 | | |
| 59/1 | RA[11] | LOCATED | LVCMOS33_OUT | PR8D | DQ1 | | |
| 59/1 | RAout[11] | LOCATED | LVCMOS33_OUT | PR8D | DQ1 | | |
| 60/1 | BA[1] | LOCATED | LVCMOS33_OUT | PR8C | DQ1 | | |
| 61/1 | unused, PULL:DOWN | | | PR8A | DQS1 | | |
| 62/1 | C14M | LOCATED | LVCMOS33_IN | PR5D | PCLKC1_0/DQ0 | | |
| 63/1 | RA[9] | LOCATED | LVCMOS33_OUT | PR5C | PCLKT1_0/DQ0 | | |
| 64/1 | RA[10] | LOCATED | LVCMOS33_OUT | PR5B | DQS0N | | |
| 65/1 | RA[8] | LOCATED | LVCMOS33_OUT | PR5A | DQS0 | | |
| 66/1 | RA[0] | LOCATED | LVCMOS33_OUT | PR4D | DQ0 | | |
| 67/1 | RA[7] | LOCATED | LVCMOS33_OUT | PR4C | DQ0 | | |
| 68/1 | RA[1] | LOCATED | LVCMOS33_OUT | PR4B | DQ0 | | |
| 69/1 | RA[6] | LOCATED | LVCMOS33_OUT | PR4A | DQ0 | | |
| 70/1 | RA[2] | LOCATED | LVCMOS33_OUT | PR3B | DQ0 | | |
| 71/1 | RA[5] | LOCATED | LVCMOS33_OUT | PR3A | DQ0 | | |
| 74/1 | RA[3] | LOCATED | LVCMOS33_OUT | PR2B | DQ0 | | |
| 75/1 | RA[4] | LOCATED | LVCMOS33_OUT | PR2A | DQ0 | | |
| 63/1 | RAout[9] | LOCATED | LVCMOS33_OUT | PR5C | PCLKT1_0/DQ0 | | |
| 64/1 | RAout[10] | LOCATED | LVCMOS33_OUT | PR5B | DQS0N | | |
| 65/1 | RAout[8] | LOCATED | LVCMOS33_OUT | PR5A | DQS0 | | |
| 66/1 | RAout[0] | LOCATED | LVCMOS33_OUT | PR4D | DQ0 | | |
| 67/1 | RAout[7] | LOCATED | LVCMOS33_OUT | PR4C | DQ0 | | |
| 68/1 | RAout[1] | LOCATED | LVCMOS33_OUT | PR4B | DQ0 | | |
| 69/1 | RAout[6] | LOCATED | LVCMOS33_OUT | PR4A | DQ0 | | |
| 70/1 | RAout[2] | LOCATED | LVCMOS33_OUT | PR3B | DQ0 | | |
| 71/1 | RAout[5] | LOCATED | LVCMOS33_OUT | PR3A | DQ0 | | |
| 74/1 | RAout[3] | LOCATED | LVCMOS33_OUT | PR2B | DQ0 | | |
| 75/1 | RAout[4] | LOCATED | LVCMOS33_OUT | PR2A | DQ0 | | |
| 76/0 | unused, PULL:DOWN | | | PT17D | DONE | | |
| 77/0 | unused, PULL:DOWN | | | PT17C | INITN | | |
| 78/0 | Ain[4] | LOCATED | LVCMOS33_IN | PT16C | | | |
| 81/0 | unused, PULL:DOWN | | | PT15D | PROGRAMN | | |
| 82/0 | nEN80 | LOCATED | LVCMOS33_IN | PT15C | JTAGENB | | |
| 83/0 | nWE80 | LOCATED | LVCMOS33_IN | PT15B | | | |
| 83/0 | unused, PULL:DOWN | | | PT15B | | | |
| 84/0 | Ain[5] | LOCATED | LVCMOS33_IN | PT15A | | | |
| 85/0 | PHI1 | LOCATED | LVCMOS33_IN | PT12D | SDA/PCLKC0_0 | | |
| 86/0 | Ain[6] | LOCATED | LVCMOS33_IN | PT12C | SCL/PCLKT0_0 | | |
@ -241,7 +240,7 @@ LOCATE COMP "Ain[7]" SITE "8";
LOCATE COMP "BA[0]" SITE "58";
LOCATE COMP "BA[1]" SITE "60";
LOCATE COMP "C14M" SITE "62";
LOCATE COMP "CKE" SITE "53";
LOCATE COMP "CKEout" SITE "53";
LOCATE COMP "DQMH" SITE "49";
LOCATE COMP "DQML" SITE "48";
LOCATE COMP "Din[0]" SITE "96";
@ -262,18 +261,18 @@ LOCATE COMP "Dout[6]" SITE "31";
LOCATE COMP "Dout[7]" SITE "32";
LOCATE COMP "LED" SITE "35";
LOCATE COMP "PHI1" SITE "85";
LOCATE COMP "RA[0]" SITE "66";
LOCATE COMP "RA[10]" SITE "64";
LOCATE COMP "RA[11]" SITE "59";
LOCATE COMP "RA[1]" SITE "68";
LOCATE COMP "RA[2]" SITE "70";
LOCATE COMP "RA[3]" SITE "74";
LOCATE COMP "RA[4]" SITE "75";
LOCATE COMP "RA[5]" SITE "71";
LOCATE COMP "RA[6]" SITE "69";
LOCATE COMP "RA[7]" SITE "67";
LOCATE COMP "RA[8]" SITE "65";
LOCATE COMP "RA[9]" SITE "63";
LOCATE COMP "RAout[0]" SITE "66";
LOCATE COMP "RAout[10]" SITE "64";
LOCATE COMP "RAout[11]" SITE "59";
LOCATE COMP "RAout[1]" SITE "68";
LOCATE COMP "RAout[2]" SITE "70";
LOCATE COMP "RAout[3]" SITE "74";
LOCATE COMP "RAout[4]" SITE "75";
LOCATE COMP "RAout[5]" SITE "71";
LOCATE COMP "RAout[6]" SITE "69";
LOCATE COMP "RAout[7]" SITE "67";
LOCATE COMP "RAout[8]" SITE "65";
LOCATE COMP "RAout[9]" SITE "63";
LOCATE COMP "RD[0]" SITE "36";
LOCATE COMP "RD[1]" SITE "37";
LOCATE COMP "RD[2]" SITE "38";
@ -291,15 +290,14 @@ LOCATE COMP "Vout[5]" SITE "16";
LOCATE COMP "Vout[6]" SITE "14";
LOCATE COMP "Vout[7]" SITE "12";
LOCATE COMP "nC07X" SITE "34";
LOCATE COMP "nCAS" SITE "52";
LOCATE COMP "nCS" SITE "57";
LOCATE COMP "nCASout" SITE "52";
LOCATE COMP "nCSout" SITE "57";
LOCATE COMP "nDOE" SITE "20";
LOCATE COMP "nEN80" SITE "82";
LOCATE COMP "nRAS" SITE "54";
LOCATE COMP "nRWE" SITE "51";
LOCATE COMP "nRASout" SITE "54";
LOCATE COMP "nRWEout" SITE "51";
LOCATE COMP "nVOE" SITE "10";
LOCATE COMP "nWE" SITE "29";
LOCATE COMP "nWE80" SITE "83";
@ -311,5 +309,5 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Thu Sep 21 05:35:04 2023
Thu Dec 28 23:10:13 2023

75
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.prf
View File

@ -1,12 +1,10 @@
SCHEMATIC START ;
# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Thu Sep 21 05:34:47 2023
# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Thu Dec 28 23:09:58 2023
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
LOCATE COMP "RD[0]" SITE "36" ;
LOCATE COMP "LED" SITE "35" ;
LOCATE COMP "C14M" SITE "62" ;
LOCATE COMP "DQMH" SITE "49" ;
LOCATE COMP "DQML" SITE "48" ;
LOCATE COMP "RD[7]" SITE "43" ;
LOCATE COMP "RD[6]" SITE "42" ;
LOCATE COMP "RD[5]" SITE "41" ;
@ -14,25 +12,27 @@ LOCATE COMP "RD[4]" SITE "40" ;
LOCATE COMP "RD[3]" SITE "39" ;
LOCATE COMP "RD[2]" SITE "38" ;
LOCATE COMP "RD[1]" SITE "37" ;
LOCATE COMP "RA[11]" SITE "59" ;
LOCATE COMP "RA[10]" SITE "64" ;
LOCATE COMP "RA[9]" SITE "63" ;
LOCATE COMP "RA[8]" SITE "65" ;
LOCATE COMP "RA[7]" SITE "67" ;
LOCATE COMP "RA[6]" SITE "69" ;
LOCATE COMP "RA[5]" SITE "71" ;
LOCATE COMP "RA[4]" SITE "75" ;
LOCATE COMP "RA[3]" SITE "74" ;
LOCATE COMP "RA[2]" SITE "70" ;
LOCATE COMP "RA[1]" SITE "68" ;
LOCATE COMP "RA[0]" SITE "66" ;
LOCATE COMP "DQMH" SITE "49" ;
LOCATE COMP "DQML" SITE "48" ;
LOCATE COMP "RAout[11]" SITE "59" ;
LOCATE COMP "RAout[10]" SITE "64" ;
LOCATE COMP "RAout[9]" SITE "63" ;
LOCATE COMP "RAout[8]" SITE "65" ;
LOCATE COMP "RAout[7]" SITE "67" ;
LOCATE COMP "RAout[6]" SITE "69" ;
LOCATE COMP "RAout[5]" SITE "71" ;
LOCATE COMP "RAout[4]" SITE "75" ;
LOCATE COMP "RAout[3]" SITE "74" ;
LOCATE COMP "RAout[2]" SITE "70" ;
LOCATE COMP "RAout[1]" SITE "68" ;
LOCATE COMP "RAout[0]" SITE "66" ;
LOCATE COMP "BA[1]" SITE "60" ;
LOCATE COMP "BA[0]" SITE "58" ;
LOCATE COMP "nRWE" SITE "51" ;
LOCATE COMP "nCAS" SITE "52" ;
LOCATE COMP "nRAS" SITE "54" ;
LOCATE COMP "nCS" SITE "57" ;
LOCATE COMP "CKE" SITE "53" ;
LOCATE COMP "nRWEout" SITE "51" ;
LOCATE COMP "nCASout" SITE "52" ;
LOCATE COMP "nRASout" SITE "54" ;
LOCATE COMP "nCSout" SITE "57" ;
LOCATE COMP "CKEout" SITE "53" ;
LOCATE COMP "nVOE" SITE "10" ;
LOCATE COMP "Vout[7]" SITE "12" ;
LOCATE COMP "Vout[6]" SITE "14" ;
@ -69,7 +69,6 @@ LOCATE COMP "Ain[1]" SITE "2" ;
LOCATE COMP "Ain[0]" SITE "3" ;
LOCATE COMP "nC07X" SITE "34" ;
LOCATE COMP "nEN80" SITE "82" ;
LOCATE COMP "nWE80" SITE "83" ;
LOCATE COMP "nWE" SITE "29" ;
LOCATE COMP "PHI1" SITE "85" ;
FREQUENCY PORT "C14M" 14.300000 MHz ;
@ -79,7 +78,7 @@ BLOCK ASYNCPATHS ;
OUTPUT PORT "LED" LOAD 100.000000 pF ;
OUTPUT PORT "BA[1]" LOAD 5.000000 pF ;
OUTPUT PORT "BA[0]" LOAD 5.000000 pF ;
OUTPUT PORT "CKE" LOAD 5.000000 pF ;
OUTPUT PORT "CKEout" LOAD 5.000000 pF ;
OUTPUT PORT "DQMH" LOAD 5.000000 pF ;
OUTPUT PORT "DQML" LOAD 5.000000 pF ;
OUTPUT PORT "Dout[0]" LOAD 15.000000 pF ;
@ -90,18 +89,18 @@ OUTPUT PORT "Dout[4]" LOAD 15.000000 pF ;
OUTPUT PORT "Dout[5]" LOAD 15.000000 pF ;
OUTPUT PORT "Dout[6]" LOAD 15.000000 pF ;
OUTPUT PORT "Dout[7]" LOAD 15.000000 pF ;
OUTPUT PORT "RA[0]" LOAD 5.000000 pF ;
OUTPUT PORT "RA[1]" LOAD 5.000000 pF ;
OUTPUT PORT "RA[2]" LOAD 5.000000 pF ;
OUTPUT PORT "RA[3]" LOAD 5.000000 pF ;
OUTPUT PORT "RA[4]" LOAD 5.000000 pF ;
OUTPUT PORT "RA[5]" LOAD 5.000000 pF ;
OUTPUT PORT "RA[6]" LOAD 5.000000 pF ;
OUTPUT PORT "RA[7]" LOAD 5.000000 pF ;
OUTPUT PORT "RA[8]" LOAD 5.000000 pF ;
OUTPUT PORT "RA[9]" LOAD 5.000000 pF ;
OUTPUT PORT "RA[10]" LOAD 5.000000 pF ;
OUTPUT PORT "RA[11]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[0]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[1]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[2]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[3]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[4]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[5]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[6]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[7]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[8]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[9]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[10]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[11]" LOAD 5.000000 pF ;
OUTPUT PORT "Vout[0]" LOAD 15.000000 pF ;
OUTPUT PORT "Vout[1]" LOAD 15.000000 pF ;
OUTPUT PORT "Vout[2]" LOAD 15.000000 pF ;
@ -110,11 +109,11 @@ OUTPUT PORT "Vout[4]" LOAD 15.000000 pF ;
OUTPUT PORT "Vout[5]" LOAD 15.000000 pF ;
OUTPUT PORT "Vout[6]" LOAD 15.000000 pF ;
OUTPUT PORT "Vout[7]" LOAD 15.000000 pF ;
OUTPUT PORT "nCAS" LOAD 5.000000 pF ;
OUTPUT PORT "nCS" LOAD 5.000000 pF ;
OUTPUT PORT "nCASout" LOAD 5.000000 pF ;
OUTPUT PORT "nCSout" LOAD 5.000000 pF ;
OUTPUT PORT "nDOE" LOAD 10.000000 pF ;
OUTPUT PORT "nRAS" LOAD 5.000000 pF ;
OUTPUT PORT "nRWE" LOAD 5.000000 pF ;
OUTPUT PORT "nRASout" LOAD 5.000000 pF ;
OUTPUT PORT "nRWEout" LOAD 5.000000 pF ;
OUTPUT PORT "nVOE" LOAD 10.000000 pF ;
OUTPUT PORT "RD[0]" LOAD 9.000000 pF ;
OUTPUT PORT "RD[1]" LOAD 9.000000 pF ;

377
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.srr
View File

@ -3,7 +3,7 @@
#OS: Windows 8 6.2
#Hostname: ZANEMACWIN11
# Thu Sep 21 05:34:34 2023
# Thu Dec 28 23:09:45 2023
#Implementation: impl1
@ -48,45 +48,50 @@ Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 202
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E-LCMXO2.v" (library work)
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v" (library work)
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v" (library work)
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\REFB.v" (library work)
Verilog syntax check successful!
Compiler output is up to date. No re-compile necessary
Selecting top level module RAM2E
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
Running optimization stage 1 on VHI .......
Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
Running optimization stage 1 on VLO .......
Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
Running optimization stage 1 on EFB .......
Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
Running optimization stage 1 on REFB .......
Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E-LCMXO2.v":1:7:1:11|Synthesizing module RAM2E in library work.
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v":1:7:1:15|Synthesizing module RAM2E_UFM in library work.
Running optimization stage 1 on RAM2E_UFM .......
Finished optimization stage 1 on RAM2E_UFM (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB)
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v":1:7:1:11|Synthesizing module RAM2E in library work.
Running optimization stage 1 on RAM2E .......
Finished optimization stage 1 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB)
Running optimization stage 2 on RAM2E .......
@N: CL159 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v":11:15:11:19|Input nWE80 is unused.
Finished optimization stage 2 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
Running optimization stage 2 on RAM2E_UFM .......
@N: CL159 :"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v":10:7:10:11|Input Ready is unused.
Finished optimization stage 2 on RAM2E_UFM (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
Running optimization stage 2 on REFB .......
Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
Running optimization stage 2 on EFB .......
Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
Running optimization stage 2 on VLO .......
Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
Running optimization stage 2 on VHI .......
Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 97MB peak: 97MB)
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 102MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Sep 21 05:34:34 2023
# Thu Dec 28 23:09:45 2023
###########################################################]
###########################################################[
@ -113,7 +118,7 @@ At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s;
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Sep 21 05:34:34 2023
# Thu Dec 28 23:09:46 2023
###########################################################]
@ -123,12 +128,12 @@ For a summary of runtime and memory usage for all design units, please see file:
@END
At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Sep 21 05:34:34 2023
# Thu Dec 28 23:09:46 2023
###########################################################]
###########################################################[
@ -156,10 +161,10 @@ At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s;
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Thu Sep 21 05:34:36 2023
# Thu Dec 28 23:09:47 2023
###########################################################]
# Thu Sep 21 05:34:36 2023
# Thu Dec 28 23:09:47 2023
Copyright (C) 1994-2021 Synopsys, Inc.
@ -178,10 +183,10 @@ Implementation : impl1
Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 141MB)
Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 140MB)
Reading constraint file: \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
@L: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1_scck.rpt
@ -190,10 +195,10 @@ See clock summary report "\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 141MB)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 140MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 141MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 140MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 149MB)
@ -201,46 +206,45 @@ Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 151MB)
@N: FX493 |Applying initial value "0" on instance PHI1reg.
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
@N: FX493 |Applying initial value "0" on instance DOEEN.
@N: FX493 |Applying initial value "0" on instance RWSel.
@N: FX493 |Applying initial value "00000000" on instance RWBank[7:0].
@N: FX493 |Applying initial value "1" on instance DQMH.
@N: FX493 |Applying initial value "0" on instance Ready.
@N: FX493 |Applying initial value "0" on instance CmdBitbangMXO2.
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
@N: FX493 |Applying initial value "0" on instance CmdExecMXO2.
@N: FX493 |Applying initial value "0" on instance PHI1r.
@N: FX493 |Applying initial value "0" on instance RWSel.
@N: FX493 |Applying initial value "0" on instance Ready.
@N: FX493 |Applying initial value "00000000" on instance RWBank[7:0].
@N: FX493 |Applying initial value "0" on instance CmdLEDGet.
@N: FX493 |Applying initial value "0" on instance CmdLEDSet.
@N: FX493 |Applying initial value "0" on instance CmdRWMaskSet.
@N: FX493 |Applying initial value "0" on instance CmdSetRWBankFFLED.
@N: FX493 |Applying initial value "0" on instance CmdSetRWBankFFMXO2.
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":375:4:375:9|Initial value on register nRWE is non-zero which can prevent the register from being packed into a block RAM or DSP.
@N: FX493 |Applying initial value "1" on instance nRWE.
@N: FX493 |Applying initial value "0" on instance LEDEN.
@N: FX493 |Applying initial value "00000000" on instance RWMask[7:0].
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":102:4:102:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
@N: FX493 |Applying initial value "0000" on instance S[3:0].
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Initial value on register DQMH is non-zero which can prevent the register from being packed into a block RAM or DSP.
@N: FX493 |Applying initial value "1" on instance DQMH.
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Initial value on register DQML is non-zero which can prevent the register from being packed into a block RAM or DSP.
@N: FX493 |Applying initial value "1" on instance DQML.
@N: FX493 |Applying initial value "0" on instance CKE.
@N: FX493 |Applying initial value "1" on instance nCS.
@N: FX493 |Applying initial value "1" on instance nRAS.
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":21:4:21:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
@N: FX493 |Applying initial value "0000" on instance S[3:0].
@N: FX493 |Applying initial value "1" on instance CKE.
@N: FX493 |Applying initial value "1" on instance nRWE.
@N: FX493 |Applying initial value "1" on instance nRWEout.
@N: FX493 |Applying initial value "1" on instance nCAS.
@N: FX493 |Applying initial value "1" on instance nCASout.
@N: FX493 |Applying initial value "1" on instance nRAS.
@N: FX493 |Applying initial value "1" on instance nRASout.
Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
@N: FX1184 |Applying syn_allowed_resources blockrams=7 on top level netlist RAM2E
Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 181MB peak: 182MB)
Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
@ -250,7 +254,7 @@ Clock Summary
Start Requested Requested Clock Clock Clock
Level Clock Frequency Period Type Group Load
----------------------------------------------------------------------------------------
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 111
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 122
0 - System 100.0 MHz 10.000 system system_clkgroup 0
========================================================================================
@ -263,7 +267,7 @@ Clock Load Summary
Clock Source Clock Pin Non-clock Pin Non-clock Pin
Clock Load Pin Seq Example Seq Example Comb Example
----------------------------------------------------------------------------------------
C14M 111 C14M(port) wb_rst.C - un1_C14M.I[0](inv)
C14M 122 C14M(port) DOEEN.C - un1_C14M.I[0](inv)
System 0 - - - -
========================================================================================
@ -280,14 +284,14 @@ For details review file gcc_ICG_report.rpt
#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
1 non-gated/non-generated clock tree(s) driving 111 clock pin(s) of sequential element(s)
1 non-gated/non-generated clock tree(s) driving 122 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
---------------------------------------------------------------------------------------
@KP:ckid0_0 C14M port 111 nCAS
@KP:ckid0_0 C14M port 122 nRAS
=======================================================================================
@ -308,11 +312,11 @@ Pre-mapping successful!
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 99MB peak: 185MB)
Process took 0h:00m:02s realtime, 0h:00m:01s cputime
# Thu Sep 21 05:34:38 2023
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Dec 28 23:09:49 2023
###########################################################]
# Thu Sep 21 05:34:38 2023
# Thu Dec 28 23:09:49 2023
Copyright (C) 1994-2021 Synopsys, Inc.
@ -331,97 +335,97 @@ Implementation : impl1
Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
@N: MF916 |Option synthesis_strategy=base is enabled.
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 139MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 139MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 146MB)
Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 179MB peak: 179MB)
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 178MB peak: 178MB)
@W: FA239 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":376:8:376:9|ROM DOEEN_2 (in view: work.RAM2E(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@N: MO106 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":376:8:376:9|Found ROM DOEEN_2 (in view: work.RAM2E(verilog)) with 16 words by 1 bit.
Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB)
@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":102:4:102:9|Found counter in view:work.RAM2E(verilog) instance FS[15:0]
@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":14:23:14:28|Found counter in view:work.RAM2E(verilog) instance FS[15:0]
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB)
Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
Available hyper_sources - for debug and ip models
None Found
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
Starting Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 191MB)
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 191MB)
Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 191MB)
Finished technology mapping (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 205MB peak: 205MB)
Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 211MB peak: 211MB)
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:02s 29.35ns 222 / 111
1 0h:00m:02s 33.71ns 284 / 122
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 205MB peak: 205MB)
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 211MB peak: 211MB)
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Boundary register BA_1_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Boundary register BA_0_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
Finished restoring hierarchy (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 206MB peak: 206MB)
Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 212MB peak: 212MB)
Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 168MB peak: 206MB)
Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 174MB peak: 212MB)
Writing Analyst data base \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_m.srm
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:02s; Memory used current: 206MB peak: 206MB)
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 212MB peak: 212MB)
Writing EDIF Netlist and constraint files
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1.edi
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:03s; Memory used current: 211MB peak: 211MB)
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB)
Finished Writing Netlists (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:03s; Memory used current: 211MB peak: 211MB)
Finished Writing Netlists (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB)
Start final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 209MB peak: 211MB)
Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 215MB peak: 217MB)
@W: MT246 :"\\mac\icloud\repos\ram2e\cpld\lcmxo2-1200hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@N: MT615 |Found clock C14M with period 69.84ns
##### START OF TIMING REPORT #####[
# Timing report written on Thu Sep 21 05:34:44 2023
# Timing report written on Thu Dec 28 23:09:54 2023
#
@ -441,12 +445,12 @@ Performance Summary
*******************
Worst slack in design: 31.782
Worst slack in design: 33.707
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
-------------------------------------------------------------------------------------------------------------------
C14M 14.3 MHz 131.4 MHz 69.841 7.610 31.782 declared default_clkgroup
C14M 14.3 MHz 128.0 MHz 69.841 7.813 33.707 declared default_clkgroup
System 100.0 MHz NA 10.000 NA 67.088 system system_clkgroup
===================================================================================================================
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
@ -464,7 +468,7 @@ Starting Ending | constraint slack | constraint slack | constraint sl
----------------------------------------------------------------------------------------------------------
System C14M