RAM2E/CPLD/DHGR-ON.v
Zane Kaminski 1dbf14e8a9 RC1
2024-06-09 01:17:38 -04:00

2 lines
68 B
Verilog

module DHGR(nDHGROE); output nDHGROE; assign nDHGROE = 0; endmodule