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This commit is contained in:
Zane Kaminski 2024-06-09 01:17:38 -04:00
parent d5b5926e97
commit 1dbf14e8a9
171 changed files with 106569 additions and 18 deletions
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1
CPLD/DHGR-OFF.v Normal file
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module DHGR(nDHGROE); output nDHGROE; assign nDHGROE = 1; endmodule

1
CPLD/DHGR-ON.v Normal file
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module DHGR(nDHGROE); output nDHGROE; assign nDHGROE = 0; endmodule

3
CPLD/LCMXO2-1200HC-NODHGR/.setting.ini Normal file
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[General]
Export.auto_tasks=Jedecgen
PAR.auto_tasks=@@empty()

29
CPLD/LCMXO2-1200HC-NODHGR/RAM2E_LCMXO2_1200HC.ldf Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<BaliProject version="3.2" title="RAM2E_LCMXO2_1200HC" device="LCMXO2-1200HC-4TG100C" default_implementation="impl1">
<Options/>
<Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
<Options def_top="RAM2E" top="RAM2E"/>
<Source name="../RAM2E.v" type="Verilog" type_short="Verilog">
<Options top_module="RAM2E"/>
</Source>
<Source name="../UFM-LCMXO2.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="REFB.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../DHGR-OFF.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="impl1/impl1.xcf" type="Programming Project File" type_short="Programming">
<Options/>
</Source>
<Source name="../RAM2E-LCMXO2.lpf" type="Logic Preference" type_short="LPF">
<Options/>
</Source>
<Source name="../RAM2E.sdc" type="Synplify Design Constraints File" type_short="SDC">
<Options/>
</Source>
</Implementation>
<Strategy name="Strategy1" file="RAM2E_LCMXO2_1200HC1.sty"/>
</BaliProject>

203
CPLD/LCMXO2-1200HC-NODHGR/RAM2E_LCMXO2_1200HC1.sty Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE strategy>
<Strategy version="1.0" predefined="0" description="" label="Strategy1">
<Property name="PROP_BD_CmdLineArgs" value="" time="0"/>
<Property name="PROP_BD_EdfHardtimer" value="Enable" time="0"/>
<Property name="PROP_BD_EdfInBusNameConv" value="None" time="0"/>
<Property name="PROP_BD_EdfInLibPath" value="" time="0"/>
<Property name="PROP_BD_EdfInRemLoc" value="Off" time="0"/>
<Property name="PROP_BD_EdfMemPath" value="" time="0"/>
<Property name="PROP_BD_ParSearchPath" value="" time="0"/>
<Property name="PROP_BIT_AddressBitGen" value="Increment" time="0"/>
<Property name="PROP_BIT_AllowReadBitGen" value="Disable" time="0"/>
<Property name="PROP_BIT_ByteWideBitMirror" value="Disable" time="0"/>
<Property name="PROP_BIT_CapReadBitGen" value="Disable" time="0"/>
<Property name="PROP_BIT_ConModBitGen" value="Disable" time="0"/>
<Property name="PROP_BIT_CreateBitFile" value="True" time="0"/>
<Property name="PROP_BIT_DisRAMResBitGen" value="True" time="0"/>
<Property name="PROP_BIT_DisableUESBitgen" value="False" time="0"/>
<Property name="PROP_BIT_DonePinBitGen" value="Pullup" time="0"/>
<Property name="PROP_BIT_DoneSigBitGen" value="4" time="0"/>
<Property name="PROP_BIT_EnIOBitGen" value="TriStateDuringReConfig" time="0"/>
<Property name="PROP_BIT_EnIntOscBitGen" value="Disable" time="0"/>
<Property name="PROP_BIT_ExtClockBitGen" value="False" time="0"/>
<Property name="PROP_BIT_GSREnableBitGen" value="True" time="0"/>
<Property name="PROP_BIT_GSRRelOnBitGen" value="DoneIn" time="0"/>
<Property name="PROP_BIT_GranTimBitGen" value="0" time="0"/>
<Property name="PROP_BIT_IOTriRelBitGen" value="Cycle 2" time="0"/>
<Property name="PROP_BIT_JTAGEnableBitGen" value="False" time="0"/>
<Property name="PROP_BIT_LenBitsBitGen" value="24" time="0"/>
<Property name="PROP_BIT_MIFFileBitGen" value="" time="0"/>
<Property name="PROP_BIT_NoHeader" value="False" time="0"/>
<Property name="PROP_BIT_OutFormatBitGen" value="Bit File (Binary)" time="0"/>
<Property name="PROP_BIT_OutFormatBitGen_REF" value="" time="0"/>
<Property name="PROP_BIT_OutFormatPromGen" value="Intel Hex 32-bit" time="0"/>
<Property name="PROP_BIT_ParityCheckBitGen" value="True" time="0"/>
<Property name="PROP_BIT_ReadBackBitGen" value="Flash" time="0"/>
<Property name="PROP_BIT_ReadCaptureBitGen" value="Disable" time="0"/>
<Property name="PROP_BIT_RemZeroFramesBitGen" value="False" time="0"/>
<Property name="PROP_BIT_RunDRCBitGen" value="True" time="0"/>
<Property name="PROP_BIT_SearchPthBitGen" value="" time="0"/>
<Property name="PROP_BIT_StartUpClkBitGen" value="Cclk" time="0"/>
<Property name="PROP_BIT_SynchIOBitGen" value="True" time="0"/>
<Property name="PROP_BIT_SysClockConBitGen" value="Reset" time="0"/>
<Property name="PROP_BIT_SysConBitGen" value="Reset" time="0"/>
<Property name="PROP_BIT_WaitStTimBitGen" value="5" time="0"/>
<Property name="PROP_IOTIMING_AllSpeed" value="False" time="0"/>
<Property name="PROP_LST_AllowDUPMod" value="False" time="0"/>
<Property name="PROP_LST_CarryChain" value="True" time="0"/>
<Property name="PROP_LST_CarryChainLength" value="0" time="0"/>
<Property name="PROP_LST_CmdLineArgs" value="" time="0"/>
<Property name="PROP_LST_DSPStyle" value="DSP" time="0"/>
<Property name="PROP_LST_DSPUtil" value="100" time="0"/>
<Property name="PROP_LST_DecodeUnreachableStates" value="False" time="0"/>
<Property name="PROP_LST_DisableDistRam" value="False" time="0"/>
<Property name="PROP_LST_EBRUtil" value="100" time="0"/>
<Property name="PROP_LST_EdfFrequency" value="200" time="0"/>
<Property name="PROP_LST_EdfHardtimer" value="Enable" time="0"/>
<Property name="PROP_LST_EdfInLibPath" value="" time="0"/>
<Property name="PROP_LST_EdfInRemLoc" value="Off" time="0"/>
<Property name="PROP_LST_EdfMemPath" value="" time="0"/>
<Property name="PROP_LST_FIXGATEDCLKS" value="True" time="0"/>
<Property name="PROP_LST_FSMEncodeStyle" value="Auto" time="0"/>
<Property name="PROP_LST_ForceGSRInfer" value="Auto" time="0"/>
<Property name="PROP_LST_IOInsertion" value="True" time="0"/>
<Property name="PROP_LST_InterFileDump" value="False" time="0"/>
<Property name="PROP_LST_LoopLimit" value="1950" time="0"/>
<Property name="PROP_LST_MaxFanout" value="1000" time="0"/>
<Property name="PROP_LST_MuxStyle" value="Auto" time="0"/>
<Property name="PROP_LST_NumCriticalPaths" value="3" time="0"/>
<Property name="PROP_LST_OptimizeGoal" value="Balanced" time="0"/>
<Property name="PROP_LST_PropagatConst" value="True" time="0"/>
<Property name="PROP_LST_RAMStyle" value="Auto" time="0"/>
<Property name="PROP_LST_ROMStyle" value="Auto" time="0"/>
<Property name="PROP_LST_RemoveDupRegs" value="True" time="0"/>
<Property name="PROP_LST_ResolvedMixedDrivers" value="False" time="0"/>
<Property name="PROP_LST_ResourceShare" value="True" time="0"/>
<Property name="PROP_LST_UseIOReg" value="Auto" time="0"/>
<Property name="PROP_LST_UseLPF" value="True" time="0"/>
<Property name="PROP_LST_VHDL2008" value="False" time="0"/>
<Property name="PROP_MAPSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
<Property name="PROP_MAPSTA_AutoTiming" value="True" time="0"/>
<Property name="PROP_MAPSTA_CheckUnconstrainedConns" value="False" time="0"/>
<Property name="PROP_MAPSTA_CheckUnconstrainedPaths" value="False" time="0"/>
<Property name="PROP_MAPSTA_FullName" value="False" time="0"/>
<Property name="PROP_MAPSTA_NumUnconstrainedPaths" value="0" time="0"/>
<Property name="PROP_MAPSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
<Property name="PROP_MAPSTA_RouteEstAlogtithm" value="0" time="0"/>
<Property name="PROP_MAPSTA_RptAsynTimLoop" value="False" time="0"/>
<Property name="PROP_MAPSTA_WordCasePaths" value="1" time="0"/>
<Property name="PROP_MAP_IgnorePreErr" value="True" time="0"/>
<Property name="PROP_MAP_MAPIORegister" value="Auto" time="0"/>
<Property name="PROP_MAP_MAPInferGSR" value="True" time="0"/>
<Property name="PROP_MAP_MapModArgs" value="" time="0"/>
<Property name="PROP_MAP_OvermapDevice" value="False" time="0"/>
<Property name="PROP_MAP_PackLogMapDes" value="0" time="0"/>
<Property name="PROP_MAP_RegRetiming" value="False" time="0"/>
<Property name="PROP_MAP_SigCrossRef" value="False" time="0"/>
<Property name="PROP_MAP_SymCrossRef" value="False" time="0"/>
<Property name="PROP_MAP_TimingDriven" value="False" time="0"/>
<Property name="PROP_MAP_TimingDrivenNodeRep" value="False" time="0"/>
<Property name="PROP_MAP_TimingDrivenPack" value="False" time="0"/>
<Property name="PROP_PARSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
<Property name="PROP_PARSTA_AutoTiming" value="True" time="0"/>
<Property name="PROP_PARSTA_CheckUnconstrainedConns" value="False" time="0"/>
<Property name="PROP_PARSTA_CheckUnconstrainedPaths" value="False" time="0"/>
<Property name="PROP_PARSTA_FullName" value="False" time="0"/>
<Property name="PROP_PARSTA_NumUnconstrainedPaths" value="0" time="0"/>
<Property name="PROP_PARSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
<Property name="PROP_PARSTA_RptAsynTimLoop" value="False" time="0"/>
<Property name="PROP_PARSTA_SpeedForHoldAnalysis" value="m" time="0"/>
<Property name="PROP_PARSTA_SpeedForSetupAnalysis" value="default" time="0"/>
<Property name="PROP_PARSTA_WordCasePaths" value="10" time="0"/>
<Property name="PROP_PAR_CrDlyStFileParDes" value="False" time="0"/>
<Property name="PROP_PAR_DisableTDParDes" value="False" time="0"/>
<Property name="PROP_PAR_EffortParDes" value="5" time="0"/>
<Property name="PROP_PAR_MultiSeedSortMode" value="Worst Slack" time="0"/>
<Property name="PROP_PAR_NewRouteParDes" value="NBR" time="0"/>
<Property name="PROP_PAR_PARClockSkew" value="Off" time="0"/>
<Property name="PROP_PAR_PARModArgs" value="" time="0"/>
<Property name="PROP_PAR_ParMultiNodeList" value="" time="0"/>
<Property name="PROP_PAR_ParRunPlaceOnly" value="False" time="0"/>
<Property name="PROP_PAR_PlcIterParDes" value="1" time="0"/>
<Property name="PROP_PAR_PlcStCostTblParDes" value="1" time="0"/>
<Property name="PROP_PAR_PrefErrorOut" value="True" time="0"/>
<Property name="PROP_PAR_RemoveDir" value="True" time="0"/>
<Property name="PROP_PAR_RouteDlyRedParDes" value="0" time="0"/>
<Property name="PROP_PAR_RoutePassParDes" value="6" time="0"/>
<Property name="PROP_PAR_RouteResOptParDes" value="0" time="0"/>
<Property name="PROP_PAR_RoutingCDP" value="0" time="0"/>
<Property name="PROP_PAR_RoutingCDR" value="0" time="0"/>
<Property name="PROP_PAR_RunParWithTrce" value="False" time="0"/>
<Property name="PROP_PAR_SaveBestRsltParDes" value="1" time="0"/>
<Property name="PROP_PAR_StopZero" value="False" time="0"/>
<Property name="PROP_PAR_parHold" value="On" time="0"/>
<Property name="PROP_PAR_parPathBased" value="Off" time="0"/>
<Property name="PROP_PRE_CmdLineArgs" value="" time="0"/>
<Property name="PROP_PRE_EdfArrayBoundsCase" value="False" time="0"/>
<Property name="PROP_PRE_EdfAutoResOfRam" value="False" time="0"/>
<Property name="PROP_PRE_EdfClockDomainCross" value="False" time="0"/>
<Property name="PROP_PRE_EdfDSPAcrossHie" value="False" time="0"/>
<Property name="PROP_PRE_EdfFullCase" value="False" time="0"/>
<Property name="PROP_PRE_EdfIgnoreRamRWCol" value="False" time="0"/>
<Property name="PROP_PRE_EdfMissConstraint" value="False" time="0"/>
<Property name="PROP_PRE_EdfNetFanout" value="True" time="0"/>
<Property name="PROP_PRE_EdfParaCase" value="False" time="0"/>
<Property name="PROP_PRE_EdfReencodeFSM" value="True" time="0"/>
<Property name="PROP_PRE_EdfResSharing" value="True" time="0"/>
<Property name="PROP_PRE_EdfTimingViolation" value="True" time="0"/>
<Property name="PROP_PRE_EdfUseSafeFSM" value="False" time="0"/>
<Property name="PROP_PRE_EdfVlog2001" value="True" time="0"/>
<Property name="PROP_PRE_VSynComArea" value="True" time="0"/>
<Property name="PROP_PRE_VSynCritcal" value="3" time="0"/>
<Property name="PROP_PRE_VSynFSM" value="Auto" time="0"/>
<Property name="PROP_PRE_VSynFreq" value="200" time="0"/>
<Property name="PROP_PRE_VSynGSR" value="False" time="0"/>
<Property name="PROP_PRE_VSynGatedClk" value="False" time="0"/>
<Property name="PROP_PRE_VSynIOPad" value="False" time="0"/>
<Property name="PROP_PRE_VSynOutNetForm" value="None" time="0"/>
<Property name="PROP_PRE_VSynOutPref" value="True" time="0"/>
<Property name="PROP_PRE_VSynRepClkFreq" value="True" time="0"/>
<Property name="PROP_PRE_VSynRetime" value="True" time="0"/>
<Property name="PROP_PRE_VSynTimSum" value="10" time="0"/>
<Property name="PROP_PRE_VSynTransform" value="True" time="0"/>
<Property name="PROP_PRE_VSyninpd" value="0" time="0"/>
<Property name="PROP_PRE_VSynoutd" value="0" time="0"/>
<Property name="PROP_SYN_ClockConversion" value="True" time="0"/>
<Property name="PROP_SYN_CmdLineArgs" value="" time="0"/>
<Property name="PROP_SYN_EdfAllowDUPMod" value="False" time="0"/>
<Property name="PROP_SYN_EdfArea" value="False" time="0"/>
<Property name="PROP_SYN_EdfArrangeVHDLFiles" value="True" time="0"/>
<Property name="PROP_SYN_EdfDefEnumEncode" value="Default" time="0"/>
<Property name="PROP_SYN_EdfFanout" value="1000" time="0"/>
<Property name="PROP_SYN_EdfFrequency" value="100" time="0"/>
<Property name="PROP_SYN_EdfGSR" value="False" time="0"/>
<Property name="PROP_SYN_EdfInsertIO" value="False" time="0"/>
<Property name="PROP_SYN_EdfNumCritPath" value="" time="0"/>
<Property name="PROP_SYN_EdfNumStartEnd" value="" time="0"/>
<Property name="PROP_SYN_EdfOutNetForm" value="None" time="0"/>
<Property name="PROP_SYN_EdfPushTirstates" value="True" time="0"/>
<Property name="PROP_SYN_EdfResSharing" value="True" time="0"/>
<Property name="PROP_SYN_EdfRunRetiming" value="Pipelining Only" time="0"/>
<Property name="PROP_SYN_EdfSymFSM" value="True" time="0"/>
<Property name="PROP_SYN_EdfUnconsClk" value="False" time="0"/>
<Property name="PROP_SYN_EdfVerilogInput" value="Verilog 2001" time="0"/>
<Property name="PROP_SYN_ExportSetting" value="No" time="0"/>
<Property name="PROP_SYN_LibPath" value="" time="0"/>
<Property name="PROP_SYN_ResolvedMixedDrivers" value="False" time="0"/>
<Property name="PROP_SYN_UpdateCompilePtTimData" value="False" time="0"/>
<Property name="PROP_SYN_UseLPF" value="True" time="0"/>
<Property name="PROP_SYN_VHDL2008" value="False" time="0"/>
<Property name="PROP_THERMAL_DefaultFreq" value="0" time="0"/>
<Property name="PROP_TIM_MaxDelSimDes" value="" time="0"/>
<Property name="PROP_TIM_MinSpeedGrade" value="False" time="0"/>
<Property name="PROP_TIM_ModPreSimDes" value="" time="0"/>
<Property name="PROP_TIM_NegStupHldTim" value="True" time="0"/>
<Property name="PROP_TIM_TimSimGenPUR" value="True" time="0"/>
<Property name="PROP_TIM_TimSimGenX" value="False" time="0"/>
<Property name="PROP_TIM_TimSimHierSep" value="" time="0"/>
<Property name="PROP_TIM_TransportModeOfPathDelay" value="False" time="0"/>
<Property name="PROP_TIM_TrgtSpeedGrade" value="" time="0"/>
<Property name="PROP_TIM_WriteVerboseNetlist" value="False" time="0"/>
<Property name="PROP_TMCHK_EnableCheck" value="True" time="0"/>
</Strategy>

8
CPLD/LCMXO2-1200HC-NODHGR/REFB.ipx Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<DiamondModule name="REFB" module="EFB" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2023 09 20 04:46:00.352" version="1.2" type="Module" synthesis="synplify" source_format="Verilog">
<Package>
<File name="REFB.lpc" type="lpc" modified="2023 09 20 04:45:58.427"/>
<File name="REFB.v" type="top_level_verilog" modified="2023 09 20 04:45:58.515"/>
<File name="REFB_tmpl.v" type="template_verilog" modified="2023 09 20 04:45:58.515"/>
</Package>
</DiamondModule>

113
CPLD/LCMXO2-1200HC-NODHGR/REFB.v Normal file
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/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 */
/* Module Version: 1.2 */
/* C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 14.4 -ufm -ufm_ebr 190 -mem_size 321 -memfile ../RAM2E-LCMXO2.mem -memformat hex -wb -dev 1200 */
/* Wed Sep 20 04:45:58 2023 */
`timescale 1 ns / 1 ps
module REFB (wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i,
wb_dat_i, wb_dat_o, wb_ack_o, wbc_ufm_irq)/* synthesis NGD_DRC_MASK=1 */;
input wire wb_clk_i;
input wire wb_rst_i;
input wire wb_cyc_i;
input wire wb_stb_i;
input wire wb_we_i;
input wire [7:0] wb_adr_i;
input wire [7:0] wb_dat_i;
output wire [7:0] wb_dat_o;
output wire wb_ack_o;
output wire wbc_ufm_irq;
wire scuba_vhi;
wire scuba_vlo;
VHI scuba_vhi_inst (.Z(scuba_vhi));
VLO scuba_vlo_inst (.Z(scuba_vlo));
defparam EFBInst_0.UFM_INIT_FILE_FORMAT = "HEX" ;
defparam EFBInst_0.UFM_INIT_FILE_NAME = "../RAM2E-LCMXO2.mem" ;
defparam EFBInst_0.UFM_INIT_ALL_ZEROS = "DISABLED" ;
defparam EFBInst_0.UFM_INIT_START_PAGE = 190 ;
defparam EFBInst_0.UFM_INIT_PAGES = 321 ;
defparam EFBInst_0.DEV_DENSITY = "1200L" ;
defparam EFBInst_0.EFB_UFM = "ENABLED" ;
defparam EFBInst_0.TC_ICAPTURE = "DISABLED" ;
defparam EFBInst_0.TC_OVERFLOW = "DISABLED" ;
defparam EFBInst_0.TC_ICR_INT = "OFF" ;
defparam EFBInst_0.TC_OCR_INT = "OFF" ;
defparam EFBInst_0.TC_OV_INT = "OFF" ;
defparam EFBInst_0.TC_TOP_SEL = "OFF" ;
defparam EFBInst_0.TC_RESETN = "ENABLED" ;
defparam EFBInst_0.TC_OC_MODE = "TOGGLE" ;
defparam EFBInst_0.TC_OCR_SET = 32767 ;
defparam EFBInst_0.TC_TOP_SET = 65535 ;
defparam EFBInst_0.GSR = "ENABLED" ;
defparam EFBInst_0.TC_CCLK_SEL = 1 ;
defparam EFBInst_0.TC_MODE = "CTCM" ;
defparam EFBInst_0.TC_SCLK_SEL = "PCLOCK" ;
defparam EFBInst_0.EFB_TC_PORTMODE = "WB" ;
defparam EFBInst_0.EFB_TC = "DISABLED" ;
defparam EFBInst_0.SPI_WAKEUP = "DISABLED" ;
defparam EFBInst_0.SPI_INTR_RXOVR = "DISABLED" ;
defparam EFBInst_0.SPI_INTR_TXOVR = "DISABLED" ;
defparam EFBInst_0.SPI_INTR_RXRDY = "DISABLED" ;
defparam EFBInst_0.SPI_INTR_TXRDY = "DISABLED" ;
defparam EFBInst_0.SPI_SLAVE_HANDSHAKE = "DISABLED" ;
defparam EFBInst_0.SPI_PHASE_ADJ = "DISABLED" ;
defparam EFBInst_0.SPI_CLK_INV = "DISABLED" ;
defparam EFBInst_0.SPI_LSB_FIRST = "DISABLED" ;
defparam EFBInst_0.SPI_CLK_DIVIDER = 1 ;
defparam EFBInst_0.SPI_MODE = "MASTER" ;
defparam EFBInst_0.EFB_SPI = "DISABLED" ;
defparam EFBInst_0.I2C2_WAKEUP = "DISABLED" ;
defparam EFBInst_0.I2C2_GEN_CALL = "DISABLED" ;
defparam EFBInst_0.I2C2_CLK_DIVIDER = 1 ;
defparam EFBInst_0.I2C2_BUS_PERF = "100kHz" ;
defparam EFBInst_0.I2C2_SLAVE_ADDR = "0b1000010" ;
defparam EFBInst_0.I2C2_ADDRESSING = "7BIT" ;
defparam EFBInst_0.EFB_I2C2 = "DISABLED" ;
defparam EFBInst_0.I2C1_WAKEUP = "DISABLED" ;
defparam EFBInst_0.I2C1_GEN_CALL = "DISABLED" ;
defparam EFBInst_0.I2C1_CLK_DIVIDER = 1 ;
defparam EFBInst_0.I2C1_BUS_PERF = "100kHz" ;
defparam EFBInst_0.I2C1_SLAVE_ADDR = "0b1000001" ;
defparam EFBInst_0.I2C1_ADDRESSING = "7BIT" ;
defparam EFBInst_0.EFB_I2C1 = "DISABLED" ;
defparam EFBInst_0.EFB_WB_CLK_FREQ = "14.4" ;
EFB EFBInst_0 (.WBCLKI(wb_clk_i), .WBRSTI(wb_rst_i), .WBCYCI(wb_cyc_i),
.WBSTBI(wb_stb_i), .WBWEI(wb_we_i), .WBADRI7(wb_adr_i[7]), .WBADRI6(wb_adr_i[6]),
.WBADRI5(wb_adr_i[5]), .WBADRI4(wb_adr_i[4]), .WBADRI3(wb_adr_i[3]),
.WBADRI2(wb_adr_i[2]), .WBADRI1(wb_adr_i[1]), .WBADRI0(wb_adr_i[0]),
.WBDATI7(wb_dat_i[7]), .WBDATI6(wb_dat_i[6]), .WBDATI5(wb_dat_i[5]),
.WBDATI4(wb_dat_i[4]), .WBDATI3(wb_dat_i[3]), .WBDATI2(wb_dat_i[2]),
.WBDATI1(wb_dat_i[1]), .WBDATI0(wb_dat_i[0]), .PLL0DATI7(scuba_vlo),
.PLL0DATI6(scuba_vlo), .PLL0DATI5(scuba_vlo), .PLL0DATI4(scuba_vlo),
.PLL0DATI3(scuba_vlo), .PLL0DATI2(scuba_vlo), .PLL0DATI1(scuba_vlo),
.PLL0DATI0(scuba_vlo), .PLL0ACKI(scuba_vlo), .PLL1DATI7(scuba_vlo),
.PLL1DATI6(scuba_vlo), .PLL1DATI5(scuba_vlo), .PLL1DATI4(scuba_vlo),
.PLL1DATI3(scuba_vlo), .PLL1DATI2(scuba_vlo), .PLL1DATI1(scuba_vlo),
.PLL1DATI0(scuba_vlo), .PLL1ACKI(scuba_vlo), .I2C1SCLI(scuba_vlo),
.I2C1SDAI(scuba_vlo), .I2C2SCLI(scuba_vlo), .I2C2SDAI(scuba_vlo),
.SPISCKI(scuba_vlo), .SPIMISOI(scuba_vlo), .SPIMOSII(scuba_vlo),
.SPISCSN(scuba_vlo), .TCCLKI(scuba_vlo), .TCRSTN(scuba_vlo), .TCIC(scuba_vlo),
.UFMSN(scuba_vhi), .WBDATO7(wb_dat_o[7]), .WBDATO6(wb_dat_o[6]),
.WBDATO5(wb_dat_o[5]), .WBDATO4(wb_dat_o[4]), .WBDATO3(wb_dat_o[3]),
.WBDATO2(wb_dat_o[2]), .WBDATO1(wb_dat_o[1]), .WBDATO0(wb_dat_o[0]),
.WBACKO(wb_ack_o), .PLLCLKO(), .PLLRSTO(), .PLL0STBO(), .PLL1STBO(),
.PLLWEO(), .PLLADRO4(), .PLLADRO3(), .PLLADRO2(), .PLLADRO1(), .PLLADRO0(),
.PLLDATO7(), .PLLDATO6(), .PLLDATO5(), .PLLDATO4(), .PLLDATO3(),
.PLLDATO2(), .PLLDATO1(), .PLLDATO0(), .I2C1SCLO(), .I2C1SCLOEN(),
.I2C1SDAO(), .I2C1SDAOEN(), .I2C2SCLO(), .I2C2SCLOEN(), .I2C2SDAO(),
.I2C2SDAOEN(), .I2C1IRQO(), .I2C2IRQO(), .SPISCKO(), .SPISCKEN(),
.SPIMISOO(), .SPIMISOEN(), .SPIMOSIO(), .SPIMOSIEN(), .SPIMCSN7(),
.SPIMCSN6(), .SPIMCSN5(), .SPIMCSN4(), .SPIMCSN3(), .SPIMCSN2(),
.SPIMCSN1(), .SPIMCSN0(), .SPICSNEN(), .SPIIRQO(), .TCINT(), .TCOC(),
.WBCUFMIRQ(wbc_ufm_irq), .CFGWAKE(), .CFGSTDBY());
// exemplar begin
// exemplar end
endmodule

78
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NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
NOTE All Rights Reserved *
NOTE DATE CREATED: Fri Jun 07 20:50:28 2024 *
NOTE DESIGN NAME: RAM2E *
NOTE DEVICE NAME: LCMXO2-1200HC-4TQFP100 *
NOTE PIN ASSIGNMENTS *
NOTE PINS RD[0] : 36 : inout *
NOTE PINS LED : 35 : out *
NOTE PINS C14M : 62 : in *
NOTE PINS RD[7] : 43 : inout *
NOTE PINS RD[6] : 42 : inout *
NOTE PINS RD[5] : 41 : inout *
NOTE PINS RD[4] : 40 : inout *
NOTE PINS RD[3] : 39 : inout *
NOTE PINS RD[2] : 38 : inout *
NOTE PINS RD[1] : 37 : inout *
NOTE PINS DQMH : 49 : out *
NOTE PINS DQML : 48 : out *
NOTE PINS RAout[11] : 59 : out *
NOTE PINS RAout[10] : 64 : out *
NOTE PINS RAout[9] : 63 : out *
NOTE PINS RAout[8] : 65 : out *
NOTE PINS RAout[7] : 67 : out *
NOTE PINS RAout[6] : 69 : out *
NOTE PINS RAout[5] : 71 : out *
NOTE PINS RAout[4] : 75 : out *
NOTE PINS RAout[3] : 74 : out *
NOTE PINS RAout[2] : 70 : out *
NOTE PINS RAout[1] : 68 : out *
NOTE PINS RAout[0] : 66 : out *
NOTE PINS BA[1] : 60 : out *
NOTE PINS BA[0] : 58 : out *
NOTE PINS nRWEout : 51 : out *
NOTE PINS nCASout : 52 : out *
NOTE PINS nRASout : 54 : out *
NOTE PINS nCSout : 57 : out *
NOTE PINS CKEout : 53 : out *
NOTE PINS nVOE : 10 : out *
NOTE PINS Vout[7] : 12 : out *
NOTE PINS Vout[6] : 14 : out *
NOTE PINS Vout[5] : 16 : out *
NOTE PINS Vout[4] : 19 : out *
NOTE PINS Vout[3] : 13 : out *
NOTE PINS Vout[2] : 17 : out *
NOTE PINS Vout[1] : 15 : out *
NOTE PINS Vout[0] : 18 : out *
NOTE PINS nDOE : 20 : out *
NOTE PINS Dout[7] : 32 : out *
NOTE PINS Dout[6] : 31 : out *
NOTE PINS Dout[5] : 21 : out *
NOTE PINS Dout[4] : 24 : out *
NOTE PINS Dout[3] : 28 : out *
NOTE PINS Dout[2] : 25 : out *
NOTE PINS Dout[1] : 27 : out *
NOTE PINS Dout[0] : 30 : out *
NOTE PINS Din[7] : 87 : in *
NOTE PINS Din[6] : 88 : in *
NOTE PINS Din[5] : 99 : in *
NOTE PINS Din[4] : 1 : in *
NOTE PINS Din[3] : 9 : in *
NOTE PINS Din[2] : 98 : in *
NOTE PINS Din[1] : 97 : in *
NOTE PINS Din[0] : 96 : in *
NOTE PINS Ain[7] : 8 : in *
NOTE PINS Ain[6] : 86 : in *
NOTE PINS Ain[5] : 84 : in *
NOTE PINS Ain[4] : 78 : in *
NOTE PINS Ain[3] : 4 : in *
NOTE PINS Ain[2] : 7 : in *
NOTE PINS Ain[1] : 2 : in *
NOTE PINS Ain[0] : 3 : in *
NOTE PINS nC07X : 34 : in *
NOTE PINS nEN80 : 82 : in *
NOTE PINS nWE : 29 : in *
NOTE PINS nDHGROE : 47 : out *
NOTE PINS PHI1 : 85 : in *
NOTE CONFIGURATION MODE: NONE *
NOTE COMPRESSION: on *

59
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----------------------------------------------------------------------
Report for cell RAM2E.verilog
Register bits: 125 of 1280 (10%)
PIC Latch: 0
I/O cells: 70
Cell usage:
cell count Res Usage(%)
BB 8 100.0
CCU2D 9 100.0
EFB 1 100.0
FD1P3AX 58 100.0
FD1P3IX 1 100.0
FD1S3AX 31 100.0
FD1S3AY 4 100.0
FD1S3IX 9 100.0
GSR 1 100.0
IB 21 100.0
IFS1P3DX 1 100.0
INV 4 100.0
OB 41 100.0
OFS1P3BX 6 100.0
OFS1P3DX 12 100.0
OFS1P3IX 3 100.0
ORCALUT4 275 100.0
PUR 1 100.0
VHI 3 100.0
VLO 3 100.0
SUB MODULES
RAM2E_UFM 1 100.0
REFB 1 100.0
TOTAL 494
----------------------------------------------------------------------
Report for cell RAM2E_UFM.netlist
Instance path: ram2e_ufm
Cell usage:
cell count Res Usage(%)
EFB 1 100.0
FD1P3AX 29 50.0
FD1P3IX 1 100.0
FD1S3IX 1 11.1
ORCALUT4 268 97.5
VHI 2 66.7
VLO 2 66.7
SUB MODULES
REFB 1 100.0
TOTAL 305
----------------------------------------------------------------------
Report for cell REFB.netlist
Instance path: ram2e_ufm.ufmefb
Cell usage:
cell count Res Usage(%)
EFB 1 100.0
VHI 1 33.3
VLO 1 33.3
TOTAL 3

86
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BITGEN: Bitstream Generator Diamond (64-bit) 3.11.3.469
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Fri Jun 07 20:50:24 2024
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC-NODHGR -w -jedec -gui RAM2E_LCMXO2_1200HC_impl1.ncd RAM2E_LCMXO2_1200HC_impl1.prf
Loading design for application Bitgen from file RAM2E_LCMXO2_1200HC_impl1.ncd.
Design name: RAM2E
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-1200HC
Package: TQFP100
Performance: 4
Loading device for application Bitgen from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.11_x64/ispfpga.
Package Status: Final Version 1.42.
Performance Hardware Data Status: Final Version 34.4.
Running DRC.
DRC detected 0 errors and 0 warnings.
Reading Preference File from RAM2E_LCMXO2_1200HC_impl1.prf.
Preference Summary:
+---------------------------------+---------------------------------+
| Preference | Current Setting |
+---------------------------------+---------------------------------+
| RamCfg | Reset** |
+---------------------------------+---------------------------------+
| MCCLK_FREQ | 2.08** |
+---------------------------------+---------------------------------+
| CONFIG_SECURE | OFF** |
+---------------------------------+---------------------------------+
| INBUF | ON** |
+---------------------------------+---------------------------------+
| JTAG_PORT | ENABLE** |
+---------------------------------+---------------------------------+
| SDM_PORT | DISABLE** |
+---------------------------------+---------------------------------+
| SLAVE_SPI_PORT | DISABLE** |
+---------------------------------+---------------------------------+
| MASTER_SPI_PORT | DISABLE** |
+---------------------------------+---------------------------------+
| I2C_PORT | DISABLE** |
+---------------------------------+---------------------------------+
| MUX_CONFIGURATION_PORTS | DISABLE** |
+---------------------------------+---------------------------------+
| CONFIGURATION | CFG** |
+---------------------------------+---------------------------------+
| COMPRESS_CONFIG | ON** |
+---------------------------------+---------------------------------+
| MY_ASSP | OFF** |
+---------------------------------+---------------------------------+
| ONE_TIME_PROGRAM | OFF** |
+---------------------------------+---------------------------------+
| ENABLE_TRANSFR | DISABLE** |
+---------------------------------+---------------------------------+
| SHAREDEBRINIT | DISABLE** |
+---------------------------------+---------------------------------+
| BACKGROUND_RECONFIG | OFF** |
+---------------------------------+---------------------------------+
* Default setting.
** The specified setting matches the default setting.
Creating bit map...
Bitstream Status: Final Version 1.95.
Saving bit stream in "RAM2E_LCMXO2_1200HC_impl1.jed".
===========
UFM Summary.
===========
UFM Size: 511 Pages (128*511 Bits).
UFM Utilization: General Purpose Flash Memory.
Available General Purpose Flash Memory: 511 Pages (Page 0 to Page 510).
Initialized UFM Pages: 321 Pages (Page 190 to Page 510).
Total CPU Time: 3 secs
Total REAL Time: 4 secs
Peak Memory Usage: 275 MB

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File diff suppressed because it is too large Load Diff

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File diff suppressed because it is too large Load Diff

468
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Lattice Mapping Report File for Design Module 'RAM2E'
Design Information
------------------
Command line: map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 4 -oc Commercial
RAM2E_LCMXO2_1200HC_impl1.ngd -o RAM2E_LCMXO2_1200HC_impl1_map.ncd -pr
RAM2E_LCMXO2_1200HC_impl1.prf -mp RAM2E_LCMXO2_1200HC_impl1.mrp -lpf //Mac/
iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC-NODHGR/impl1/RAM2E_LCMXO2_1200HC_impl
1_synplify.lpf -lpf //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf -c 0
-gui
Target Vendor: LATTICE
Target Device: LCMXO2-1200HCTQFP100
Target Performance: 4
Mapper: xo2c00, version: Diamond (64-bit) 3.11.3.469
Mapped on: 06/07/24 20:50:05
Design Summary
--------------
Number of registers: 125 out of 1520 (8%)
PFU registers: 103 out of 1280 (8%)
PIO registers: 22 out of 240 (9%)
Number of SLICEs: 148 out of 640 (23%)
SLICEs as Logic/ROM: 148 out of 640 (23%)
SLICEs as RAM: 0 out of 480 (0%)
SLICEs as Carry: 9 out of 640 (1%)
Number of LUT4s: 296 out of 1280 (23%)
Number used as logic LUTs: 278
Number used as distributed RAM: 0
Number used as ripple logic: 18
Number used as shift registers: 0
Number of PIO sites used: 70 + 4(JTAG) out of 80 (93%)
Number of block RAMs: 0 out of 7 (0%)
Number of GSRs: 0 out of 1 (0%)
EFB used : Yes
JTAG used : No
Readback used : No
Oscillator used : No
Startup used : No
POR : On
Bandgap : On
Number of Power Controller: 0 out of 1 (0%)
Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%)
Number of DCCA: 0 out of 8 (0%)
Number of DCMA: 0 out of 2 (0%)
Number of PLLs: 0 out of 1 (0%)
Number of DQSDLLs: 0 out of 2 (0%)
Number of CLKDIVC: 0 out of 4 (0%)
Number of ECLKSYNCA: 0 out of 4 (0%)
Number of ECLKBRIDGECS: 0 out of 2 (0%)
Notes:-
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
distributed RAMs) + 2*(Number of ripple logic)
2. Number of logic LUT4s does not include count of distributed RAM and
ripple logic.
Number of clocks: 2
Net C14M_c: 85 loads, 63 rising, 22 falling (Driver: PIO C14M )
Net PHI1_c: 3 loads, 0 rising, 3 falling (Driver: PIO PHI1 )
Page 1
Design: RAM2E Date: 06/07/24 20:50:05
Design Summary (cont)
---------------------
Number of Clock Enables: 13
Net N_117_i: 2 loads, 0 LSLICEs
Net RWBank14: 11 loads, 11 LSLICEs
Net ram2e_ufm/wb_adr_0_sqmuxa_1_i: 1 loads, 1 LSLICEs
Net un9_VOE_0_a2_0_a2: 1 loads, 1 LSLICEs
Net un6_DOEEN_0_a2_0_a2: 2 loads, 2 LSLICEs
Net ram2e_ufm/un1_wb_adr_0_sqmuxa_2_i[0]: 8 loads, 8 LSLICEs
Net ram2e_ufm/un1_wb_cyc_stb_0_sqmuxa_1_i[0]: 1 loads, 1 LSLICEs
Net ram2e_ufm/N_111: 1 loads, 1 LSLICEs
Net ram2e_ufm/N_104: 4 loads, 4 LSLICEs
Net ram2e_ufm/N_98: 1 loads, 1 LSLICEs
Net un1_CKE48_0_i: 6 loads, 6 LSLICEs
Net N_389_i: 2 loads, 0 LSLICEs
Net Vout3: 8 loads, 0 LSLICEs
Number of LSRs: 8
Net N_148: 2 loads, 2 LSLICEs
Net N_430_i: 2 loads, 0 LSLICEs
Net RC7: 2 loads, 2 LSLICEs
Net S[2]: 2 loads, 2 LSLICEs
Net ram2e_ufm/wb_rst: 1 loads, 0 LSLICEs
Net ram2e_ufm/nRWE_0_i_o3_RNIP8E61: 1 loads, 1 LSLICEs
Net N_530: 1 loads, 0 LSLICEs
Net N_301_i: 1 loads, 1 LSLICEs
Number of nets driven by tri-state buffers: 0
Top 10 highest fanout non-clock nets:
Net S[2]: 60 loads
Net S[3]: 48 loads
Net S[1]: 46 loads
Net S[0]: 31 loads
Net FS[11]: 24 loads
Net FS[10]: 23 loads
Net FS[12]: 23 loads
Net FS[9]: 23 loads
Net FS[13]: 21 loads
Net FS[8]: 18 loads
Number of warnings: 3
Number of errors: 0
Design Errors/Warnings
----------------------
WARNING - map: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf(94): Semantic
error in "IOBUF PORT "nWE80" IO_TYPE=LVCMOS33 PULLMODE=NONE ;": Port
"nWE80" does not exist in the design. This preference has been disabled.
WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
temporarily disable certain features of the device including Power
Controller, GSR, Hardened User SPI Port, Hardened Primary User I2C Port.
Functionality is restored after the Flash Memory (UFM/Configuration)
Interface is disabled using Disable Configuration Interface command 0x26
followed by Bypass command 0xFF.
WARNING - map: IO buffer missing for top level port nWE80...logic will be
Page 2
Design: RAM2E Date: 06/07/24 20:50:05
Design Errors/Warnings (cont)
-----------------------------
discarded.
IO (PIO) Attributes
-------------------
+---------------------+-----------+-----------+------------+
| IO Name | Direction | Levelmode | IO |
| | | IO_TYPE | Register |
+---------------------+-----------+-----------+------------+
| RD[0] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| LED | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| C14M | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[7] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[6] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[5] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[4] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[3] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[2] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[1] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| DQMH | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| DQML | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RAout[11] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RAout[10] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RAout[9] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RAout[8] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RAout[7] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[6] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[5] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[4] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[3] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[2] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[1] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[0] | OUTPUT | LVCMOS33 | |
Page 3
Design: RAM2E Date: 06/07/24 20:50:05
IO (PIO) Attributes (cont)
--------------------------
+---------------------+-----------+-----------+------------+
| BA[1] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| BA[0] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nRWEout | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nCASout | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nRASout | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nCSout | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| CKEout | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nVOE | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[7] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[6] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[5] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[4] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[3] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[2] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[1] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[0] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nDOE | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[7] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[6] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[5] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[4] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[3] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[2] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[1] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[0] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[7] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[6] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[5] | INPUT | LVCMOS33 | |
Page 4
Design: RAM2E Date: 06/07/24 20:50:05
IO (PIO) Attributes (cont)
--------------------------
+---------------------+-----------+-----------+------------+
| Din[4] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[3] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[2] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[1] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[0] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[7] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[6] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[5] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[4] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[3] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[2] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[1] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[0] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nC07X | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nEN80 | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nWE | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nDHGROE | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| PHI1 | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
Removed logic
-------------
Block GSR_INST undriven or does not drive anything - clipped.
Block ram2e_ufm/VCC undriven or does not drive anything - clipped.
Block ram2e_ufm/GND undriven or does not drive anything - clipped.
Signal RC_0_.CN was merged into signal PHI1_c
Signal RDOE_i was merged into signal RDOE
Signal RAT.CN was merged into signal C14M_c
Signal ram2e_ufm/ufmefb/VCC undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/GND undriven or does not drive anything - clipped.
Signal FS_s_0_S1[15] undriven or does not drive anything - clipped.
Signal FS_s_0_COUT[15] undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/CFGWAKE undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/wbc_ufm_irq undriven or does not drive anything -
clipped.
Signal ram2e_ufm/ufmefb/TCOC undriven or does not drive anything - clipped.
Page 5
Design: RAM2E Date: 06/07/24 20:50:05
Removed logic (cont)
--------------------
Signal ram2e_ufm/ufmefb/TCINT undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIIRQO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPICSNEN undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMOSIEN undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMOSIO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMISOEN undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMISOO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPISCKEN undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPISCKO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C2SDAOEN undriven or does not drive anything -
clipped.
Signal ram2e_ufm/ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C2SCLOEN undriven or does not drive anything -
clipped.
Signal ram2e_ufm/ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C1SDAOEN undriven or does not drive anything -
clipped.
Signal ram2e_ufm/ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C1SCLOEN undriven or does not drive anything -
clipped.
Signal ram2e_ufm/ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLADRO4 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLWEO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLL1STBO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLL0STBO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLRSTO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLCLKO undriven or does not drive anything - clipped.
Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped.
Signal N_1 undriven or does not drive anything - clipped.
Block RefReq.CN was optimized away.
Block RDOE_RNIAM8C was optimized away.
Block nCASout.CN was optimized away.
Page 6
Design: RAM2E Date: 06/07/24 20:50:05
Removed logic (cont)
--------------------
Block ram2e_ufm/ufmefb/VCC was optimized away.
Block ram2e_ufm/ufmefb/GND was optimized away.
Embedded Functional Block Connection Summary
--------------------------------------------
Desired WISHBONE clock frequency: 14.4 MHz
Clock source: C14M_c
Reset source: ram2e_ufm/wb_rst
Functions mode:
I2C #1 (Primary) Function: DISABLED
I2C #2 (Secondary) Function: DISABLED
SPI Function: DISABLED
Timer/Counter Function: DISABLED
Timer/Counter Mode: WB
UFM Connection: ENABLED
PLL0 Connection: DISABLED
PLL1 Connection: DISABLED
I2C Function Summary:
--------------------
None
SPI Function Summary:
--------------------
None
Timer/Counter Function Summary:
------------------------------
None
UFM Function Summary:
--------------------
UFM Utilization: General Purpose Flash Memory
Initialized UFM Pages: 321 Pages (321*128 Bits)
Available General
Purpose Flash Memory: 511 Pages (511*128 Bits)
EBR Blocks with Unique
Initialization Data: 0
WID EBR Instance
--- ------------
ASIC Components
---------------
Instance Name: ram2e_ufm/ufmefb/EFBInst_0
Type: EFB
Run Time and Memory Usage
-------------------------
Total CPU Time: 0 secs
Total REAL Time: 2 secs
Peak Memory Usage: 64 MB
Page 7
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights
reserved.

315
CPLD/LCMXO2-1200HC-NODHGR/impl1/RAM2E_LCMXO2_1200HC_impl1.pad Normal file
View File

@ -0,0 +1,315 @@
PAD Specification File
***************************
PART TYPE: LCMXO2-1200HC
Performance Grade: 4
PACKAGE: TQFP100
Package Status: Final Version 1.42
Fri Jun 07 20:50:15 2024
Pinout by Port Name:
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties |
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
| Ain[0] | 3/3 | LVCMOS33_IN | PL3A | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[1] | 2/3 | LVCMOS33_IN | PL2D | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[2] | 7/3 | LVCMOS33_IN | PL3C | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[3] | 4/3 | LVCMOS33_IN | PL3B | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[4] | 78/0 | LVCMOS33_IN | PT16C | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[5] | 84/0 | LVCMOS33_IN | PT15A | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[6] | 86/0 | LVCMOS33_IN | PT12C | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[7] | 8/3 | LVCMOS33_IN | PL3D | | | CLAMP:ON HYSTERESIS:SMALL |
| BA[0] | 58/1 | LVCMOS33_OUT | PR9A | | | DRIVE:4mA SLEW:SLOW |
| BA[1] | 60/1 | LVCMOS33_OUT | PR8C | | | DRIVE:4mA SLEW:SLOW |
| C14M | 62/1 | LVCMOS33_IN | PR5D | | | CLAMP:ON HYSTERESIS:SMALL |
| CKEout | 53/1 | LVCMOS33_OUT | PR9D | | | DRIVE:4mA SLEW:SLOW |
| DQMH | 49/2 | LVCMOS33_OUT | PB20D | | | DRIVE:4mA SLEW:SLOW |
| DQML | 48/2 | LVCMOS33_OUT | PB20C | | | DRIVE:4mA SLEW:SLOW |
| Din[0] | 96/0 | LVCMOS33_IN | PT10B | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[1] | 97/0 | LVCMOS33_IN | PT10A | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[2] | 98/0 | LVCMOS33_IN | PT9B | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[3] | 9/3 | LVCMOS33_IN | PL4A | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[4] | 1/3 | LVCMOS33_IN | PL2C | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[5] | 99/0 | LVCMOS33_IN | PT9A | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[6] | 88/0 | LVCMOS33_IN | PT12A | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[7] | 87/0 | LVCMOS33_IN | PT12B | | | CLAMP:ON HYSTERESIS:SMALL |
| Dout[0] | 30/2 | LVCMOS33_OUT | PB6B | | | DRIVE:4mA SLEW:SLOW |
| Dout[1] | 27/2 | LVCMOS33_OUT | PB4C | | | DRIVE:4mA SLEW:SLOW |
| Dout[2] | 25/3 | LVCMOS33_OUT | PL10D | | | DRIVE:4mA SLEW:SLOW |
| Dout[3] | 28/2 | LVCMOS33_OUT | PB4D | | | DRIVE:4mA SLEW:SLOW |
| Dout[4] | 24/3 | LVCMOS33_OUT | PL10C | | | DRIVE:4mA SLEW:SLOW |
| Dout[5] | 21/3 | LVCMOS33_OUT | PL9B | | | DRIVE:4mA SLEW:SLOW |
| Dout[6] | 31/2 | LVCMOS33_OUT | PB6C | | | DRIVE:4mA SLEW:SLOW |
| Dout[7] | 32/2 | LVCMOS33_OUT | PB6D | | | DRIVE:4mA SLEW:SLOW |
| LED | 35/2 | LVCMOS33_OUT | PB9B | | | DRIVE:4mA SLEW:SLOW |
| PHI1 | 85/0 | LVCMOS33_IN | PT12D | | | CLAMP:ON HYSTERESIS:SMALL |
| RAout[0] | 66/1 | LVCMOS33_OUT | PR4D | | | DRIVE:4mA SLEW:SLOW |
| RAout[10] | 64/1 | LVCMOS33_OUT | PR5B | | | DRIVE:4mA SLEW:SLOW |
| RAout[11] | 59/1 | LVCMOS33_OUT | PR8D | | | DRIVE:4mA SLEW:SLOW |
| RAout[1] | 68/1 | LVCMOS33_OUT | PR4B | | | DRIVE:4mA SLEW:SLOW |
| RAout[2] | 70/1 | LVCMOS33_OUT | PR3B | | | DRIVE:4mA SLEW:SLOW |
| RAout[3] | 74/1 | LVCMOS33_OUT | PR2B | | | DRIVE:4mA SLEW:SLOW |
| RAout[4] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA SLEW:SLOW |
| RAout[5] | 71/1 | LVCMOS33_OUT | PR3A | | | DRIVE:4mA SLEW:SLOW |
| RAout[6] | 69/1 | LVCMOS33_OUT | PR4A | | | DRIVE:4mA SLEW:SLOW |
| RAout[7] | 67/1 | LVCMOS33_OUT | PR4C | | | DRIVE:4mA SLEW:SLOW |
| RAout[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA SLEW:SLOW |
| RAout[9] | 63/1 | LVCMOS33_OUT | PR5C | | | DRIVE:4mA SLEW:SLOW |
| RD[0] | 36/2 | LVCMOS33_BIDI | PB11C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[1] | 37/2 | LVCMOS33_BIDI | PB11D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[2] | 38/2 | LVCMOS33_BIDI | PB11A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[3] | 39/2 | LVCMOS33_BIDI | PB11B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[4] | 40/2 | LVCMOS33_BIDI | PB15A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[5] | 41/2 | LVCMOS33_BIDI | PB15B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[6] | 42/2 | LVCMOS33_BIDI | PB18A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[7] | 43/2 | LVCMOS33_BIDI | PB18B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| Vout[0] | 18/3 | LVCMOS33_OUT | PL8C | | | DRIVE:4mA SLEW:SLOW |
| Vout[1] | 15/3 | LVCMOS33_OUT | PL5D | | | DRIVE:4mA SLEW:SLOW |
| Vout[2] | 17/3 | LVCMOS33_OUT | PL8B | | | DRIVE:4mA SLEW:SLOW |
| Vout[3] | 13/3 | LVCMOS33_OUT | PL5B | | | DRIVE:4mA SLEW:SLOW |
| Vout[4] | 19/3 | LVCMOS33_OUT | PL8D | | | DRIVE:4mA SLEW:SLOW |
| Vout[5] | 16/3 | LVCMOS33_OUT | PL8A | | | DRIVE:4mA SLEW:SLOW |
| Vout[6] | 14/3 | LVCMOS33_OUT | PL5C | | | DRIVE:4mA SLEW:SLOW |
| Vout[7] | 12/3 | LVCMOS33_OUT | PL5A | | | DRIVE:4mA SLEW:SLOW |
| nC07X | 34/2 | LVCMOS33_IN | PB9A | | | CLAMP:ON HYSTERESIS:SMALL |
| nCASout | 52/1 | LVCMOS33_OUT | PR10C | | | DRIVE:4mA SLEW:SLOW |
| nCSout | 57/1 | LVCMOS33_OUT | PR9B | | | DRIVE:4mA SLEW:SLOW |
| nDHGROE | 47/2 | LVCMOS33_OUT | PB18D | | | DRIVE:4mA SLEW:SLOW |
| nDOE | 20/3 | LVCMOS33_OUT | PL9A | | | DRIVE:4mA SLEW:SLOW |
| nEN80 | 82/0 | LVCMOS33_IN | PT15C | | | CLAMP:ON HYSTERESIS:SMALL |
| nRASout | 54/1 | LVCMOS33_OUT | PR9C | | | DRIVE:4mA SLEW:SLOW |
| nRWEout | 51/1 | LVCMOS33_OUT | PR10D | | | DRIVE:4mA SLEW:SLOW |
| nVOE | 10/3 | LVCMOS33_OUT | PL4B | | | DRIVE:4mA SLEW:SLOW |
| nWE | 29/2 | LVCMOS33_IN | PB6A | | | CLAMP:ON HYSTERESIS:SMALL |
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
Vccio by Bank:
+------+-------+
| Bank | Vccio |
+------+-------+
| 0 | 3.3V |
| 1 | 3.3V |
| 2 | 3.3V |
| 3 | 3.3V |
+------+-------+
Vref by Bank:
+------+-----+-----------------+---------+
| Vref | Pin | Bank # / Vref # | Load(s) |
+------+-----+-----------------+---------+
+------+-----+-----------------+---------+
Pinout by Pin Number:
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable |
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
| 1/3 | Din[4] | LOCATED | LVCMOS33_IN | PL2C | L_GPLLT_IN | | |
| 2/3 | Ain[1] | LOCATED | LVCMOS33_IN | PL2D | L_GPLLC_IN | | |
| 3/3 | Ain[0] | LOCATED | LVCMOS33_IN | PL3A | PCLKT3_2 | | |
| 4/3 | Ain[3] | LOCATED | LVCMOS33_IN | PL3B | PCLKC3_2 | | |
| 7/3 | Ain[2] | LOCATED | LVCMOS33_IN | PL3C | | | |
| 8/3 | Ain[7] | LOCATED | LVCMOS33_IN | PL3D | | | |
| 9/3 | Din[3] | LOCATED | LVCMOS33_IN | PL4A | | | |
| 10/3 | nVOE | LOCATED | LVCMOS33_OUT | PL4B | | | |
| 12/3 | Vout[7] | LOCATED | LVCMOS33_OUT | PL5A | PCLKT3_1 | | |
| 13/3 | Vout[3] | LOCATED | LVCMOS33_OUT | PL5B | PCLKC3_1 | | |
| 14/3 | Vout[6] | LOCATED | LVCMOS33_OUT | PL5C | | | |
| 15/3 | Vout[1] | LOCATED | LVCMOS33_OUT | PL5D | | | |
| 16/3 | Vout[5] | LOCATED | LVCMOS33_OUT | PL8A | | | |
| 17/3 | Vout[2] | LOCATED | LVCMOS33_OUT | PL8B | | | |
| 18/3 | Vout[0] | LOCATED | LVCMOS33_OUT | PL8C | | | |
| 19/3 | Vout[4] | LOCATED | LVCMOS33_OUT | PL8D | | | |
| 20/3 | nDOE | LOCATED | LVCMOS33_OUT | PL9A | PCLKT3_0 | | |
| 21/3 | Dout[5] | LOCATED | LVCMOS33_OUT | PL9B | PCLKC3_0 | | |
| 24/3 | Dout[4] | LOCATED | LVCMOS33_OUT | PL10C | | | |
| 25/3 | Dout[2] | LOCATED | LVCMOS33_OUT | PL10D | | | |
| 27/2 | Dout[1] | LOCATED | LVCMOS33_OUT | PB4C | CSSPIN | | |
| 28/2 | Dout[3] | LOCATED | LVCMOS33_OUT | PB4D | | | |
| 29/2 | nWE | LOCATED | LVCMOS33_IN | PB6A | | | |
| 30/2 | Dout[0] | LOCATED | LVCMOS33_OUT | PB6B | | | |
| 31/2 | Dout[6] | LOCATED | LVCMOS33_OUT | PB6C | MCLK/CCLK | | |
| 32/2 | Dout[7] | LOCATED | LVCMOS33_OUT | PB6D | SO/SPISO | | |
| 34/2 | nC07X | LOCATED | LVCMOS33_IN | PB9A | PCLKT2_0 | | |
| 35/2 | LED | LOCATED | LVCMOS33_OUT | PB9B | PCLKC2_0 | | |
| 36/2 | RD[0] | LOCATED | LVCMOS33_BIDI | PB11C | | | |
| 37/2 | RD[1] | LOCATED | LVCMOS33_BIDI | PB11D | | | |
| 38/2 | RD[2] | LOCATED | LVCMOS33_BIDI | PB11A | PCLKT2_1 | | |
| 39/2 | RD[3] | LOCATED | LVCMOS33_BIDI | PB11B | PCLKC2_1 | | |
| 40/2 | RD[4] | LOCATED | LVCMOS33_BIDI | PB15A | | | |
| 41/2 | RD[5] | LOCATED | LVCMOS33_BIDI | PB15B | | | |
| 42/2 | RD[6] | LOCATED | LVCMOS33_BIDI | PB18A | | | |
| 43/2 | RD[7] | LOCATED | LVCMOS33_BIDI | PB18B | | | |
| 45/2 | unused, PULL:DOWN | | | PB18C | | | |
| 47/2 | nDHGROE | LOCATED | LVCMOS33_OUT | PB18D | | | |
| 48/2 | DQML | LOCATED | LVCMOS33_OUT | PB20C | SN | | |
| 49/2 | DQMH | LOCATED | LVCMOS33_OUT | PB20D | SI/SISPI | | |
| 51/1 | nRWEout | LOCATED | LVCMOS33_OUT | PR10D | DQ1 | | |
| 52/1 | nCASout | LOCATED | LVCMOS33_OUT | PR10C | DQ1 | | |
| 53/1 | CKEout | LOCATED | LVCMOS33_OUT | PR9D | DQ1 | | |
| 54/1 | nRASout | LOCATED | LVCMOS33_OUT | PR9C | DQ1 | | |
| 57/1 | nCSout | LOCATED | LVCMOS33_OUT | PR9B | DQ1 | | |
| 58/1 | BA[0] | LOCATED | LVCMOS33_OUT | PR9A | DQ1 | | |
| 59/1 | RAout[11] | LOCATED | LVCMOS33_OUT | PR8D | DQ1 | | |
| 60/1 | BA[1] | LOCATED | LVCMOS33_OUT | PR8C | DQ1 | | |
| 61/1 | unused, PULL:DOWN | | | PR8A | DQS1 | | |
| 62/1 | C14M | LOCATED | LVCMOS33_IN | PR5D | PCLKC1_0/DQ0 | | |
| 63/1 | RAout[9] | LOCATED | LVCMOS33_OUT | PR5C | PCLKT1_0/DQ0 | | |
| 64/1 | RAout[10] | LOCATED | LVCMOS33_OUT | PR5B | DQS0N | | |
| 65/1 | RAout[8] | LOCATED | LVCMOS33_OUT | PR5A | DQS0 | | |
| 66/1 | RAout[0] | LOCATED | LVCMOS33_OUT | PR4D | DQ0 | | |
| 67/1 | RAout[7] | LOCATED | LVCMOS33_OUT | PR4C | DQ0 | | |
| 68/1 | RAout[1] | LOCATED | LVCMOS33_OUT | PR4B | DQ0 | | |
| 69/1 | RAout[6] | LOCATED | LVCMOS33_OUT | PR4A | DQ0 | | |
| 70/1 | RAout[2] | LOCATED | LVCMOS33_OUT | PR3B | DQ0 | | |
| 71/1 | RAout[5] | LOCATED | LVCMOS33_OUT | PR3A | DQ0 | | |
| 74/1 | RAout[3] | LOCATED | LVCMOS33_OUT | PR2B | DQ0 | | |
| 75/1 | RAout[4] | LOCATED | LVCMOS33_OUT | PR2A | DQ0 | | |
| 76/0 | unused, PULL:DOWN | | | PT17D | DONE | | |
| 77/0 | unused, PULL:DOWN | | | PT17C | INITN | | |
| 78/0 | Ain[4] | LOCATED | LVCMOS33_IN | PT16C | | | |
| 81/0 | unused, PULL:DOWN | | | PT15D | PROGRAMN | | |
| 82/0 | nEN80 | LOCATED | LVCMOS33_IN | PT15C | JTAGENB | | |
| 83/0 | unused, PULL:DOWN | | | PT15B | | | |
| 84/0 | Ain[5] | LOCATED | LVCMOS33_IN | PT15A | | | |
| 85/0 | PHI1 | LOCATED | LVCMOS33_IN | PT12D | SDA/PCLKC0_0 | | |
| 86/0 | Ain[6] | LOCATED | LVCMOS33_IN | PT12C | SCL/PCLKT0_0 | | |
| 87/0 | Din[7] | LOCATED | LVCMOS33_IN | PT12B | PCLKC0_1 | | |
| 88/0 | Din[6] | LOCATED | LVCMOS33_IN | PT12A | PCLKT0_1 | | |
| 90/0 | Reserved: sysCONFIG | | | PT11D | TMS | | |
| 91/0 | Reserved: sysCONFIG | | | PT11C | TCK | | |
| 94/0 | Reserved: sysCONFIG | | | PT10D | TDI | | |
| 95/0 | Reserved: sysCONFIG | | | PT10C | TDO | | |
| 96/0 | Din[0] | LOCATED | LVCMOS33_IN | PT10B | | | |
| 97/0 | Din[1] | LOCATED | LVCMOS33_IN | PT10A | | | |
| 98/0 | Din[2] | LOCATED | LVCMOS33_IN | PT9B | | | |
| 99/0 | Din[5] | LOCATED | LVCMOS33_IN | PT9A | | | |
| PB4A/2 | unused, PULL:DOWN | | | PB4A | | | |
| PB4B/2 | unused, PULL:DOWN | | | PB4B | | | |
| PB9C/2 | unused, PULL:DOWN | | | PB9C | | | |
| PB9D/2 | unused, PULL:DOWN | | | PB9D | | | |
| PB15C/2 | unused, PULL:DOWN | | | PB15C | | | |
| PB15D/2 | unused, PULL:DOWN | | | PB15D | | | |
| PB20A/2 | unused, PULL:DOWN | | | PB20A | | | |
| PB20B/2 | unused, PULL:DOWN | | | PB20B | | | |
| PL2A/3 | unused, PULL:DOWN | | | PL2A | L_GPLLT_FB | | |
| PL2B/3 | unused, PULL:DOWN | | | PL2B | L_GPLLC_FB | | |
| PL4C/3 | unused, PULL:DOWN | | | PL4C | | | |
| PL4D/3 | unused, PULL:DOWN | | | PL4D | | | |
| PL10A/3 | unused, PULL:DOWN | | | PL10A | | | |
| PL10B/3 | unused, PULL:DOWN | | | PL10B | | | |
| PR2C/1 | unused, PULL:DOWN | | | PR2C | DQ0 | | |
| PR2D/1 | unused, PULL:DOWN | | | PR2D | DQ0 | | |
| PR8B/1 | unused, PULL:DOWN | | | PR8B | DQS1N | | |
| PR10A/1 | unused, PULL:DOWN | | | PR10A | DQ1 | | |
| PR10B/1 | unused, PULL:DOWN | | | PR10B | DQ1 | | |
| PT9C/0 | unused, PULL:DOWN | | | PT9C | | | |
| PT9D/0 | unused, PULL:DOWN | | | PT9D | | | |
| PT11A/0 | unused, PULL:DOWN | | | PT11A | | | |
| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | |
| PT16A/0 | unused, PULL:DOWN | | | PT16A | | | |
| PT16B/0 | unused, PULL:DOWN | | | PT16B | | | |
| PT16D/0 | unused, PULL:DOWN | | | PT16D | | | |
| PT17A/0 | unused, PULL:DOWN | | | PT17A | | | |
| PT17B/0 | unused, PULL:DOWN | | | PT17B | | | |
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
sysCONFIG Pins:
+----------+--------------------+--------------------+----------+-------------+-------------------+
| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode |
+----------+--------------------+--------------------+----------+-------------+-------------------+
| PT11D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP |
| PT11C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down |
| PT10D | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP |
| PT10C | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP |
+----------+--------------------+--------------------+----------+-------------+-------------------+
Dedicated sysCONFIG Pins:
List of All Pins' Locate Preferences Based on Final Placement After PAR
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste):
LOCATE COMP "Ain[0]" SITE "3";
LOCATE COMP "Ain[1]" SITE "2";
LOCATE COMP "Ain[2]" SITE "7";
LOCATE COMP "Ain[3]" SITE "4";
LOCATE COMP "Ain[4]" SITE "78";
LOCATE COMP "Ain[5]" SITE "84";
LOCATE COMP "Ain[6]" SITE "86";
LOCATE COMP "Ain[7]" SITE "8";
LOCATE COMP "BA[0]" SITE "58";
LOCATE COMP "BA[1]" SITE "60";
LOCATE COMP "C14M" SITE "62";
LOCATE COMP "CKEout" SITE "53";
LOCATE COMP "DQMH" SITE "49";
LOCATE COMP "DQML" SITE "48";
LOCATE COMP "Din[0]" SITE "96";
LOCATE COMP "Din[1]" SITE "97";
LOCATE COMP "Din[2]" SITE "98";
LOCATE COMP "Din[3]" SITE "9";
LOCATE COMP "Din[4]" SITE "1";
LOCATE COMP "Din[5]" SITE "99";
LOCATE COMP "Din[6]" SITE "88";
LOCATE COMP "Din[7]" SITE "87";
LOCATE COMP "Dout[0]" SITE "30";
LOCATE COMP "Dout[1]" SITE "27";
LOCATE COMP "Dout[2]" SITE "25";
LOCATE COMP "Dout[3]" SITE "28";
LOCATE COMP "Dout[4]" SITE "24";
LOCATE COMP "Dout[5]" SITE "21";
LOCATE COMP "Dout[6]" SITE "31";
LOCATE COMP "Dout[7]" SITE "32";
LOCATE COMP "LED" SITE "35";
LOCATE COMP "PHI1" SITE "85";
LOCATE COMP "RAout[0]" SITE "66";
LOCATE COMP "RAout[10]" SITE "64";
LOCATE COMP "RAout[11]" SITE "59";
LOCATE COMP "RAout[1]" SITE "68";
LOCATE COMP "RAout[2]" SITE "70";
LOCATE COMP "RAout[3]" SITE "74";
LOCATE COMP "RAout[4]" SITE "75";
LOCATE COMP "RAout[5]" SITE "71";
LOCATE COMP "RAout[6]" SITE "69";
LOCATE COMP "RAout[7]" SITE "67";
LOCATE COMP "RAout[8]" SITE "65";
LOCATE COMP "RAout[9]" SITE "63";
LOCATE COMP "RD[0]" SITE "36";
LOCATE COMP "RD[1]" SITE "37";
LOCATE COMP "RD[2]" SITE "38";
LOCATE COMP "RD[3]" SITE "39";
LOCATE COMP "RD[4]" SITE "40";
LOCATE COMP "RD[5]" SITE "41";
LOCATE COMP "RD[6]" SITE "42";
LOCATE COMP "RD[7]" SITE "43";
LOCATE COMP "Vout[0]" SITE "18";
LOCATE COMP "Vout[1]" SITE "15";
LOCATE COMP "Vout[2]" SITE "17";
LOCATE COMP "Vout[3]" SITE "13";
LOCATE COMP "Vout[4]" SITE "19";
LOCATE COMP "Vout[5]" SITE "16";
LOCATE COMP "Vout[6]" SITE "14";
LOCATE COMP "Vout[7]" SITE "12";
LOCATE COMP "nC07X" SITE "34";
LOCATE COMP "nCASout" SITE "52";
LOCATE COMP "nCSout" SITE "57";
LOCATE COMP "nDHGROE" SITE "47";
LOCATE COMP "nDOE" SITE "20";
LOCATE COMP "nEN80" SITE "82";
LOCATE COMP "nRASout" SITE "54";
LOCATE COMP "nRWEout" SITE "51";
LOCATE COMP "nVOE" SITE "10";
LOCATE COMP "nWE" SITE "29";
PAR: Place And Route Diamond (64-bit) 3.11.3.469.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Fri Jun 07 20:50:20 2024

128
CPLD/LCMXO2-1200HC-NODHGR/impl1/RAM2E_LCMXO2_1200HC_impl1.prf Normal file
View File

@ -0,0 +1,128 @@
SCHEMATIC START ;
# map: version Diamond (64-bit) 3.11.3.469 -- WARNING: Map write only section -- Fri Jun 07 20:50:06 2024
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
LOCATE COMP "RD[0]" SITE "36" ;
LOCATE COMP "LED" SITE "35" ;
LOCATE COMP "C14M" SITE "62" ;
LOCATE COMP "RD[7]" SITE "43" ;
LOCATE COMP "RD[6]" SITE "42" ;
LOCATE COMP "RD[5]" SITE "41" ;
LOCATE COMP "RD[4]" SITE "40" ;
LOCATE COMP "RD[3]" SITE "39" ;
LOCATE COMP "RD[2]" SITE "38" ;
LOCATE COMP "RD[1]" SITE "37" ;
LOCATE COMP "DQMH" SITE "49" ;
LOCATE COMP "DQML" SITE "48" ;
LOCATE COMP "RAout[11]" SITE "59" ;
LOCATE COMP "RAout[10]" SITE "64" ;
LOCATE COMP "RAout[9]" SITE "63" ;
LOCATE COMP "RAout[8]" SITE "65" ;
LOCATE COMP "RAout[7]" SITE "67" ;
LOCATE COMP "RAout[6]" SITE "69" ;
LOCATE COMP "RAout[5]" SITE "71" ;
LOCATE COMP "RAout[4]" SITE "75" ;
LOCATE COMP "RAout[3]" SITE "74" ;
LOCATE COMP "RAout[2]" SITE "70" ;
LOCATE COMP "RAout[1]" SITE "68" ;
LOCATE COMP "RAout[0]" SITE "66" ;
LOCATE COMP "BA[1]" SITE "60" ;
LOCATE COMP "BA[0]" SITE "58" ;
LOCATE COMP "nRWEout" SITE "51" ;
LOCATE COMP "nCASout" SITE "52" ;
LOCATE COMP "nRASout" SITE "54" ;
LOCATE COMP "nCSout" SITE "57" ;
LOCATE COMP "CKEout" SITE "53" ;
LOCATE COMP "nVOE" SITE "10" ;
LOCATE COMP "Vout[7]" SITE "12" ;
LOCATE COMP "Vout[6]" SITE "14" ;
LOCATE COMP "Vout[5]" SITE "16" ;
LOCATE COMP "Vout[4]" SITE "19" ;
LOCATE COMP "Vout[3]" SITE "13" ;
LOCATE COMP "Vout[2]" SITE "17" ;
LOCATE COMP "Vout[1]" SITE "15" ;
LOCATE COMP "Vout[0]" SITE "18" ;
LOCATE COMP "nDOE" SITE "20" ;
LOCATE COMP "Dout[7]" SITE "32" ;
LOCATE COMP "Dout[6]" SITE "31" ;
LOCATE COMP "Dout[5]" SITE "21" ;
LOCATE COMP "Dout[4]" SITE "24" ;
LOCATE COMP "Dout[3]" SITE "28" ;
LOCATE COMP "Dout[2]" SITE "25" ;
LOCATE COMP "Dout[1]" SITE "27" ;
LOCATE COMP "Dout[0]" SITE "30" ;
LOCATE COMP "Din[7]" SITE "87" ;
LOCATE COMP "Din[6]" SITE "88" ;
LOCATE COMP "Din[5]" SITE "99" ;
LOCATE COMP "Din[4]" SITE "1" ;
LOCATE COMP "Din[3]" SITE "9" ;
LOCATE COMP "Din[2]" SITE "98" ;
LOCATE COMP "Din[1]" SITE "97" ;
LOCATE COMP "Din[0]" SITE "96" ;
LOCATE COMP "Ain[7]" SITE "8" ;
LOCATE COMP "Ain[6]" SITE "86" ;
LOCATE COMP "Ain[5]" SITE "84" ;
LOCATE COMP "Ain[4]" SITE "78" ;
LOCATE COMP "Ain[3]" SITE "4" ;
LOCATE COMP "Ain[2]" SITE "7" ;
LOCATE COMP "Ain[1]" SITE "2" ;
LOCATE COMP "Ain[0]" SITE "3" ;
LOCATE COMP "nC07X" SITE "34" ;
LOCATE COMP "nEN80" SITE "82" ;
LOCATE COMP "nWE" SITE "29" ;
LOCATE COMP "nDHGROE" SITE "47" ;
LOCATE COMP "PHI1" SITE "85" ;
FREQUENCY PORT "C14M" 14.300000 MHz ;
SCHEMATIC END ;
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
OUTPUT PORT "LED" LOAD 100.000000 pF ;
OUTPUT PORT "nDHGROE" LOAD 10.000000 pF ;
OUTPUT PORT "BA[1]" LOAD 5.000000 pF ;
OUTPUT PORT "BA[0]" LOAD 5.000000 pF ;
OUTPUT PORT "CKEout" LOAD 5.000000 pF ;
OUTPUT PORT "DQMH" LOAD 5.000000 pF ;
OUTPUT PORT "DQML" LOAD 5.000000 pF ;
OUTPUT PORT "Dout[0]" LOAD 15.000000 pF ;
OUTPUT PORT "Dout[1]" LOAD 15.000000 pF ;
OUTPUT PORT "Dout[2]" LOAD 15.000000 pF ;
OUTPUT PORT "Dout[3]" LOAD 15.000000 pF ;
OUTPUT PORT "Dout[4]" LOAD 15.000000 pF ;
OUTPUT PORT "Dout[5]" LOAD 15.000000 pF ;
OUTPUT PORT "Dout[6]" LOAD 15.000000 pF ;
OUTPUT PORT "Dout[7]" LOAD 15.000000 pF ;
OUTPUT PORT "RAout[0]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[1]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[2]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[3]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[4]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[5]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[6]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[7]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[8]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[9]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[10]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[11]" LOAD 5.000000 pF ;
OUTPUT PORT "Vout[0]" LOAD 15.000000 pF ;
OUTPUT PORT "Vout[1]" LOAD 15.000000 pF ;
OUTPUT PORT "Vout[2]" LOAD 15.000000 pF ;
OUTPUT PORT "Vout[3]" LOAD 15.000000 pF ;
OUTPUT PORT "Vout[4]" LOAD 15.000000 pF ;
OUTPUT PORT "Vout[5]" LOAD 15.000000 pF ;
OUTPUT PORT "Vout[6]" LOAD 15.000000 pF ;
OUTPUT PORT "Vout[7]" LOAD 15.000000 pF ;
OUTPUT PORT "nCASout" LOAD 5.000000 pF ;
OUTPUT PORT "nCSout" LOAD 5.000000 pF ;
OUTPUT PORT "nDOE" LOAD 10.000000 pF ;
OUTPUT PORT "nRASout" LOAD 5.000000 pF ;
OUTPUT PORT "nRWEout" LOAD 5.000000 pF ;
OUTPUT PORT "nVOE" LOAD 10.000000 pF ;
OUTPUT PORT "RD[0]" LOAD 9.000000 pF ;
OUTPUT PORT "RD[1]" LOAD 9.000000 pF ;
OUTPUT PORT "RD[2]" LOAD 9.000000 pF ;
OUTPUT PORT "RD[3]" LOAD 9.000000 pF ;
OUTPUT PORT "RD[4]" LOAD 9.000000 pF ;
OUTPUT PORT "RD[5]" LOAD 9.000000 pF ;
OUTPUT PORT "RD[6]" LOAD 9.000000 pF ;
OUTPUT PORT "RD[7]" LOAD 9.000000 pF ;
COMMERCIAL ;

740
CPLD/LCMXO2-1200HC-NODHGR/impl1/RAM2E_LCMXO2_1200HC_impl1.srr Normal file
View File

@ -0,0 +1,740 @@
#Build: Synplify Pro (R) N-2018.03L-SP1-1, Build 443R, Apr 1 2019
#install: C:\lscc\diamond\3.11_x64\synpbase
#OS: Windows 8 6.2
#Hostname: ZANEMACWIN11
# Fri Jun 7 20:49:56 2024
#Implementation: impl1
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys HDL Compiler, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Verilog Compiler, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v" (library work)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\pmi_def.v" (library work)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v" (library work)
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v" (library work)
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC-NODHGR\REFB.v" (library work)
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\DHGR-OFF.v" (library work)
Verilog syntax check successful!
Selecting top level module RAM2E
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
Running optimization stage 1 on VHI .......
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
Running optimization stage 1 on VLO .......
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
Running optimization stage 1 on EFB .......
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC-NODHGR\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
Running optimization stage 1 on REFB .......
@W: CL318 :"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC-NODHGR\REFB.v":9:14:9:21|*Output wb_dat_o has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output.
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v":1:7:1:15|Synthesizing module RAM2E_UFM in library work.
Running optimization stage 1 on RAM2E_UFM .......
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\DHGR-OFF.v":1:7:1:10|Synthesizing module DHGR in library work.
Running optimization stage 1 on DHGR .......
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v":1:7:1:11|Synthesizing module RAM2E in library work.
Running optimization stage 1 on RAM2E .......
Running optimization stage 2 on RAM2E .......
@N: CL159 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v":11:15:11:19|Input nWE80 is unused.
Running optimization stage 2 on DHGR .......
Running optimization stage 2 on RAM2E_UFM .......
Running optimization stage 2 on REFB .......
Running optimization stage 2 on EFB .......
Running optimization stage 2 on VLO .......
Running optimization stage 2 on VHI .......
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Fri Jun 7 20:49:57 2024
###########################################################]
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Fri Jun 7 20:49:57 2024
###########################################################]
For a summary of runtime and memory usage for all design units, please see file:
==========================================================
@L: A:\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC-NODHGR\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_comp.rt.csv
@END
At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Fri Jun 7 20:49:57 2024
###########################################################]
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Database state : \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC-NODHGR\impl1\synwork\|impl1
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Fri Jun 7 20:49:58 2024
###########################################################]
Premap Report
# Fri Jun 7 20:49:58 2024
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Lattice Technology Pre-mapping, Version maplat2018q2p1, Build 055R, Built Apr 3 2019 09:51:54
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
Reading constraint file: \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
@N: MF284 |Setting synthesis effort to medium for the design
@L: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC-NODHGR\impl1\RAM2E_LCMXO2_1200HC_impl1_scck.rpt
Printing clock summary report in "\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC-NODHGR\impl1\RAM2E_LCMXO2_1200HC_impl1_scck.rpt" file
@N: MF916 |Option synthesis_strategy=base is enabled.
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB)
@N: MF284 |Setting synthesis effort to medium for the design
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":21:4:21:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
@N: MH105 |UMR3 is only supported for HAPS-80.
@N: MH105 |UMR3 is only supported for HAPS-80.
@N: BN115 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":140:9:140:12|Removing instance dhgr (in view: work.RAM2E(verilog)) of type view:work.DHGR(verilog) because it does not drive other instances.
syn_allowed_resources : blockrams=7 set on top level netlist RAM2E
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
Clock Summary
******************
Start Requested Requested Clock Clock Clock
Level Clock Frequency Period Type Group Load
-----------------------------------------------------------------------------------------------
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 121
0 - System 100.0 MHz 10.000 system system_clkgroup 0
0 - RAM2E|PHI1 100.0 MHz 10.000 inferred Inferred_clkgroup_0 9
===============================================================================================
Clock Load Summary
***********************
Clock Source Clock Pin Non-clock Pin Non-clock Pin
Clock Load Pin Seq Example Seq Example Comb Example
--------------------------------------------------------------------------------------------
C14M 121 C14M(port) RAT.C - un1_C14M.I[0](inv)
System 0 - - - -
RAM2E|PHI1 9 PHI1(port) RefReq.C S[0].D[0] un1_PHI1.I[0](inv)
============================================================================================
@W: MT529 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":20:19:20:24|Found inferred clock RAM2E|PHI1 which controls 9 sequential elements including PHI1r. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed: 0
@S |Clock Optimization Summary
#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
2 non-gated/non-generated clock tree(s) driving 125 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
---------------------------------------------------------------------------------------
@KP:ckid0_0 C14M port 121 PHI1r
@KP:ckid0_1 PHI1 Unconstrained_port 4 RC[2:0]
=======================================================================================
##### END OF CLOCK OPTIMIZATION REPORT ######
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
Finished Pre Mapping Phase.
Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
None
None
Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
Pre-mapping successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Jun 7 20:49:59 2024
###########################################################]
Map & Optimize Report
# Fri Jun 7 20:50:00 2024
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Lattice Technology Mapper, Version maplat2018q2p1, Build 055R, Built Apr 3 2019 09:51:54
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
@N: MF284 |Setting synthesis effort to medium for the design
@N: MF916 |Option synthesis_strategy=base is enabled.
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
@N: MF284 |Setting synthesis effort to medium for the design
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
Available hyper_sources - for debug and ip models
None Found
@N: FX493 |Applying initial value "00000000" on instance RWBank[7:0].
@N: FX493 |Applying initial value "0000" on instance S[3:0].
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)
@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":14:23:14:28|Found counter in view:work.RAM2E(verilog) instance FS[15:0]
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 142MB)
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:01s 6.90ns 281 / 125
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":171:4:171:9|Boundary register BA_1_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":171:4:171:9|Boundary register BA_0_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 158MB peak: 160MB)
Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 122MB peak: 160MB)
Writing Analyst data base \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC-NODHGR\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_m.srm
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 158MB peak: 160MB)
Writing EDIF Netlist and constraint files
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC-NODHGR\impl1\RAM2E_LCMXO2_1200HC_impl1.edi
N-2018.03L-SP1-1
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 162MB peak: 164MB)
Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 164MB)
@W: MT246 :"\\mac\icloud\repos\ram2e\cpld\lcmxo2-1200hc-nodhgr\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@N: MT615 |Found clock C14M with period 69.84ns
@W: MT420 |Found inferred clock RAM2E|PHI1 with period 10.00ns. Please declare a user-defined clock on port PHI1.
##### START OF TIMING REPORT #####[
# Timing Report written on Fri Jun 7 20:50:03 2024
#
Top view: RAM2E
Requested Frequency: 14.3 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s): \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
Performance Summary
*******************
Worst slack in design: 6.897
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
----------------------------------------------------------------------------------------------------------------------
C14M 14.3 MHz 112.1 MHz 69.841 8.918 31.599 declared default_clkgroup
RAM2E|PHI1 100.0 MHz 322.2 MHz 10.000 3.103 6.897 inferred Inferred_clkgroup_0
System 100.0 MHz NA 10.000 NA 67.088 system system_clkgroup
======================================================================================================================
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
----------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
----------------------------------------------------------------------------------------------------------------
System C14M | 69.841 67.088 | No paths - | No paths - | No paths -
C14M System | 69.841 68.797 | No paths - | No paths - | No paths -
C14M C14M | 69.841 60.923 | No paths - | 34.920 31.599 | No paths -
RAM2E|PHI1 C14M | No paths - | No paths - | No paths - | Diff grp -
RAM2E|PHI1 RAM2E|PHI1 | No paths - | 10.000 6.897 | No paths - | No paths -
================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Interface Information
*********************
No IO constraint found
====================================
Detailed Report for Clock: C14M
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------
S[2] C14M FD1S3AX Q S[2] 1.366 31.599
S[3] C14M FD1S3AX Q S[3] 1.345 31.619
S[1] C14M FD1S3AX Q S[1] 1.344 31.800
S[0] C14M FD1S3AX Q S[0] 1.305 31.838
RA[0] C14M FD1P3AX Q RA[0] 1.108 33.707
RA[3] C14M FD1P3AX Q RA[3] 1.108 33.707
RA[1] C14M FD1P3AX Q RA[1] 1.044 33.771
RA[2] C14M FD1P3AX Q RA[2] 1.044 33.771
RA[4] C14M FD1P3AX Q RA[4] 1.044 33.771
RA[5] C14M FD1P3AX Q RA[5] 1.044 33.771
===========================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
-----------------------------------------------------------------------------------
VOE_i_0io C14M OFS1P3IX CD N_530 34.118 31.599
VOE_i_0io C14M OFS1P3IX D VOE_ic_i 35.009 31.800
Vout_0io[0] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[1] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[2] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[3] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[4] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[5] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[6] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[7] C14M OFS1P3DX SP Vout3 34.449 32.634
===================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 34.920
- Setup time: 0.803
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 34.118
- Propagation time: 2.519
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : 31.599
Number of logic level(s): 1
Starting point: S[2] / Q
Ending point: VOE_i_0io / CD
The start point is clocked by C14M [rising] on pin CK
The end point is clocked by C14M [falling] on pin SCLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
------------------------------------------------------------------------------------------------------------
S[2] FD1S3AX Q Out 1.366 1.366 -
S[2] Net - - - - 58
ram2e_ufm.un1_wb_adr_0_sqmuxa_2_0_a2_0[0] ORCALUT4 A In 0.000 1.366 -
ram2e_ufm.un1_wb_adr_0_sqmuxa_2_0_a2_0[0] ORCALUT4 Z Out 1.153 2.519 -
N_530 Net - - - - 3
VOE_i_0io OFS1P3IX CD In 0.000 2.519 -
============================================================================================================
====================================
Detailed Report for Clock: RAM2E|PHI1
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------
RC[1] RAM2E|PHI1 FD1S3IX Q RC[1] 1.148 6.897
RC[2] RAM2E|PHI1 FD1S3IX Q RC[2] 1.108 6.937
RC[0] RAM2E|PHI1 FD1S3IX Q RC[0] 1.148 8.179
===========================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------
RC[0] RAM2E|PHI1 FD1S3IX CD RC7 9.197 6.897
RC[1] RAM2E|PHI1 FD1S3IX CD RC7 9.197 6.897
RC[2] RAM2E|PHI1 FD1S3IX CD RC7 9.197 6.897
RC[0] RAM2E|PHI1 FD1S3IX D RC_i[0] 9.894 8.179
RC[1] RAM2E|PHI1 FD1S3IX D RC_RNO[1] 10.089 8.324
RC[2] RAM2E|PHI1 FD1S3IX D RC_RNO[2] 10.089 8.324
RefReq RAM2E|PHI1 FD1S3AX D RefReq_2 10.089 8.324
================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 10.000
- Setup time: 0.803
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 9.197
- Propagation time: 2.301
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : 6.897
Number of logic level(s): 1
Starting point: RC[1] / Q
Ending point: RC[0] / CD
The start point is clocked by RAM2E|PHI1 [falling] on pin CK
The end point is clocked by RAM2E|PHI1 [falling] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------
RC[1] FD1S3IX Q Out 1.148 1.148 -
RC[1] Net - - - - 4
RC7 ORCALUT4 A In 0.000 1.148 -
RC7 ORCALUT4 Z Out 1.153 2.301 -
RC7 Net - - - - 3
RC[0] FD1S3IX CD In 0.000 2.301 -
=================================================================================
====================================
Detailed Report for Clock: System
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------------------------------
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBACKO wb_ack 0.000 67.088
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO0 wb_dato[0] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO2 wb_dato[2] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO3 wb_dato[3] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO4 wb_dato[4] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO5 wb_dato[5] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO6 wb_dato[6] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO7 wb_dato[7] 0.000 69.313
===================================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
----------------------------------------------------------------------------------------
ram2e_ufm.RWMask[0] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[1] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[2] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[3] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[4] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[5] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[6] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[7] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.LEDEN System FD1P3AX SP N_98 69.369 67.736
ram2e_ufm.wb_cyc_stb System FD1P3AX SP N_111 69.369 67.736
========================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 69.841
- Setup time: 0.472
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 69.369
- Propagation time: 2.282
- Clock delay at starting point: 0.000 (ideal)
- Estimated clock delay at start point: -0.000
= Slack (non-critical) : 67.088
Number of logic level(s): 2
Starting point: ram2e_ufm.ufmefb.EFBInst_0 / WBACKO
Ending point: ram2e_ufm.RWMask[0] / SP
The start point is clocked by System [rising]
The end point is clocked by C14M [rising] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
----------------------------------------------------------------------------------------------------------------
ram2e_ufm.ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 -
wb_ack Net - - - - 5
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] ORCALUT4 B In 0.000 0.000 -
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] ORCALUT4 Z Out 1.017 1.017 -
un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] Net - - - - 1
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 D In 0.000 1.017 -
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 Z Out 1.265 2.282 -
N_104 Net - - - - 8
ram2e_ufm.RWMask[0] FD1P3AX SP In 0.000 2.282 -
================================================================================================================
##### END OF TIMING REPORT #####]
Timing exceptions that could not be applied
None
Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 164MB)
Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 164MB)
---------------------------------------
Resource Usage Report
Part: lcmxo2_1200hc-4
Register bits: 125 of 1280 (10%)
PIC Latch: 0
I/O cells: 70
Details:
BB: 8
CCU2D: 9
EFB: 1
FD1P3AX: 58
FD1P3IX: 1
FD1S3AX: 31
FD1S3AY: 4
FD1S3IX: 9
GSR: 1
IB: 21
IFS1P3DX: 1
INV: 4
OB: 41
OFS1P3BX: 6
OFS1P3DX: 12
OFS1P3IX: 3
ORCALUT4: 275
PUR: 1
VHI: 3
VLO: 3
Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 32MB peak: 164MB)
Process took 0h:00m:03s realtime, 0h:00m:03s cputime
# Fri Jun 7 20:50:03 2024
###########################################################]

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Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
# Written on Fri Jun 7 20:49:59 2024
##### DESIGN INFO #######################################################
Top View: "RAM2E"
Constraint File(s): "\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc"
##### SUMMARY ############################################################
Found 0 issues in 0 out of 1 constraints
##### DETAILS ############################################################
Clock Relationships
*******************
Starting Ending | rise to rise | fall to fall | rise to fall | fall to rise
-----------------------------------------------------------------------------------------------------------------------------------------
System C14M | 69.841 | No paths | No paths | No paths
C14M System | 69.841 | No paths | No paths | No paths
C14M C14M | 69.841 | No paths | 34.920 | No paths
RAM2E|PHI1 C14M | No paths | No paths | No paths | Diff grp
RAM2E|PHI1 RAM2E|PHI1 | No paths | 10.000 | No paths | No paths
=========================================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Unconstrained Start/End Points
******************************
p:Ain[0]
p:Ain[1]
p:Ain[2]
p:Ain[3]
p:Ain[4]
p:Ain[5]
p:Ain[6]
p:Ain[7]
p:BA[0]
p:BA[1]
p:CKEout
p:DQMH
p:DQML
p:Din[0]
p:Din[1]
p:Din[2]
p:Din[3]
p:Din[4]
p:Din[5]
p:Din[6]
p:Din[7]
p:Dout[0]
p:Dout[1]
p:Dout[2]
p:Dout[3]
p:Dout[4]
p:Dout[5]
p:Dout[6]
p:Dout[7]
p:LED
p:RAout[0]
p:RAout[1]
p:RAout[2]
p:RAout[3]
p:RAout[4]
p:RAout[5]
p:RAout[6]
p:RAout[7]
p:RAout[8]
p:RAout[9]
p:RAout[10]
p:RAout[11]
p:RD[0] (bidir end point)
p:RD[0] (bidir start point)
p:RD[1] (bidir end point)
p:RD[1] (bidir start point)
p:RD[2] (bidir end point)
p:RD[2] (bidir start point)
p:RD[3] (bidir end point)
p:RD[3] (bidir start point)
p:RD[4] (bidir end point)
p:RD[4] (bidir start point)
p:RD[5] (bidir end point)
p:RD[5] (bidir start point)
p:RD[6] (bidir end point)
p:RD[6] (bidir start point)
p:RD[7] (bidir end point)
p:RD[7] (bidir start point)
p:Vout[0]
p:Vout[1]
p:Vout[2]
p:Vout[3]
p:Vout[4]
p:Vout[5]
p:Vout[6]
p:Vout[7]
p:nC07X
p:nCASout
p:nCSout
p:nDHGROE
p:nDOE
p:nEN80
p:nRASout
p:nRWEout
p:nVOE
p:nWE
p:nWE80
Inapplicable constraints
************************
(none)
Applicable constraints with issues
**********************************
(none)
Constraints with matching wildcard expressions
**********************************************
(none)
Library Report
**************
# End of Constraint Checker Report

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<HTML>
<HEAD><TITLE>Project Summary</TITLE>
<STYLE TYPE="text/css">
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<PRE><A name="Mrp"></A>
Lattice Mapping Report File for Design Module 'RAM2E'
<A name="mrp_di"></A><B><U><big>Design Information</big></U></B>
Command line: map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 4 -oc Commercial
RAM2E_LCMXO2_1200HC_impl1.ngd -o RAM2E_LCMXO2_1200HC_impl1_map.ncd -pr
RAM2E_LCMXO2_1200HC_impl1.prf -mp RAM2E_LCMXO2_1200HC_impl1.mrp -lpf //Mac/
iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC-NODHGR/impl1/RAM2E_LCMXO2_1200HC_impl
1_synplify.lpf -lpf //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf -c 0
-gui
Target Vendor: LATTICE
Target Device: LCMXO2-1200HCTQFP100
Target Performance: 4
Mapper: xo2c00, version: Diamond (64-bit) 3.11.3.469
Mapped on: 06/07/24 20:50:05
<A name="mrp_ds"></A><B><U><big>Design Summary</big></U></B>
Number of registers: 125 out of 1520 (8%)
PFU registers: 103 out of 1280 (8%)
PIO registers: 22 out of 240 (9%)
Number of SLICEs: 148 out of 640 (23%)
SLICEs as Logic/ROM: 148 out of 640 (23%)
SLICEs as RAM: 0 out of 480 (0%)
SLICEs as Carry: 9 out of 640 (1%)
Number of LUT4s: 296 out of 1280 (23%)
Number used as logic LUTs: 278
Number used as distributed RAM: 0
Number used as ripple logic: 18
Number used as shift registers: 0
Number of PIO sites used: 70 + 4(JTAG) out of 80 (93%)
Number of block RAMs: 0 out of 7 (0%)
Number of GSRs: 0 out of 1 (0%)
EFB used : Yes
JTAG used : No
Readback used : No
Oscillator used : No
Startup used : No
POR : On
Bandgap : On
Number of Power Controller: 0 out of 1 (0%)
Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%)
Number of DCCA: 0 out of 8 (0%)
Number of DCMA: 0 out of 2 (0%)
Number of PLLs: 0 out of 1 (0%)
Number of DQSDLLs: 0 out of 2 (0%)
Number of CLKDIVC: 0 out of 4 (0%)
Number of ECLKSYNCA: 0 out of 4 (0%)
Number of ECLKBRIDGECS: 0 out of 2 (0%)
Notes:-
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
distributed RAMs) + 2*(Number of ripple logic)
2. Number of logic LUT4s does not include count of distributed RAM and
ripple logic.
Number of clocks: 2
Net C14M_c: 85 loads, 63 rising, 22 falling (Driver: PIO C14M )
Net PHI1_c: 3 loads, 0 rising, 3 falling (Driver: PIO PHI1 )
Number of Clock Enables: 13
Net N_117_i: 2 loads, 0 LSLICEs
Net RWBank14: 11 loads, 11 LSLICEs
Net ram2e_ufm/wb_adr_0_sqmuxa_1_i: 1 loads, 1 LSLICEs
Net un9_VOE_0_a2_0_a2: 1 loads, 1 LSLICEs
Net un6_DOEEN_0_a2_0_a2: 2 loads, 2 LSLICEs
Net ram2e_ufm/un1_wb_adr_0_sqmuxa_2_i[0]: 8 loads, 8 LSLICEs
Net ram2e_ufm/un1_wb_cyc_stb_0_sqmuxa_1_i[0]: 1 loads, 1 LSLICEs
Net ram2e_ufm/N_111: 1 loads, 1 LSLICEs
Net ram2e_ufm/N_104: 4 loads, 4 LSLICEs
Net ram2e_ufm/N_98: 1 loads, 1 LSLICEs
Net un1_CKE48_0_i: 6 loads, 6 LSLICEs
Net N_389_i: 2 loads, 0 LSLICEs
Net Vout3: 8 loads, 0 LSLICEs
Number of LSRs: 8
Net N_148: 2 loads, 2 LSLICEs
Net N_430_i: 2 loads, 0 LSLICEs
Net RC7: 2 loads, 2 LSLICEs
Net S[2]: 2 loads, 2 LSLICEs
Net ram2e_ufm/wb_rst: 1 loads, 0 LSLICEs
Net ram2e_ufm/nRWE_0_i_o3_RNIP8E61: 1 loads, 1 LSLICEs
Net N_530: 1 loads, 0 LSLICEs
Net N_301_i: 1 loads, 1 LSLICEs
Number of nets driven by tri-state buffers: 0
Top 10 highest fanout non-clock nets:
Net S[2]: 60 loads
Net S[3]: 48 loads
Net S[1]: 46 loads
Net S[0]: 31 loads
Net FS[11]: 24 loads
Net FS[10]: 23 loads
Net FS[12]: 23 loads
Net FS[9]: 23 loads
Net FS[13]: 21 loads
Net FS[8]: 18 loads
Number of warnings: 3
Number of errors: 0
<A name="mrp_dwe"></A><B><U><big>Design Errors/Warnings</big></U></B>
WARNING - map: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf(94): Semantic
error in "IOBUF PORT "nWE80" IO_TYPE=LVCMOS33 PULLMODE=NONE ;": Port
"nWE80" does not exist in the design. This preference has been disabled.
WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
temporarily disable certain features of the device including Power
Controller, GSR, Hardened User SPI Port, Hardened Primary User I2C Port.
Functionality is restored after the Flash Memory (UFM/Configuration)
Interface is disabled using Disable Configuration Interface command 0x26
followed by Bypass command 0xFF.
WARNING - map: IO buffer missing for top level port nWE80...logic will be
discarded.
<A name="mrp_ioa"></A><B><U><big>IO (PIO) Attributes</big></U></B>
+---------------------+-----------+-----------+------------+
| IO Name | Direction | Levelmode | IO |
| | | IO_TYPE | Register |
+---------------------+-----------+-----------+------------+
| RD[0] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| LED | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| C14M | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[7] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[6] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[5] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[4] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[3] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[2] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[1] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| DQMH | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| DQML | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RAout[11] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RAout[10] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RAout[9] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RAout[8] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RAout[7] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[6] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[5] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[4] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[3] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[2] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[1] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[0] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| BA[1] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| BA[0] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nRWEout | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nCASout | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nRASout | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nCSout | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| CKEout | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nVOE | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[7] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[6] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[5] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[4] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[3] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[2] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[1] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[0] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nDOE | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[7] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[6] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[5] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[4] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[3] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[2] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[1] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[0] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[7] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[6] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[5] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[4] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[3] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[2] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[1] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[0] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[7] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[6] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[5] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[4] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[3] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[2] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[1] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[0] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nC07X | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nEN80 | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nWE | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nDHGROE | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| PHI1 | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
<A name="mrp_rm"></A><B><U><big>Removed logic</big></U></B>
Block GSR_INST undriven or does not drive anything - clipped.
Block ram2e_ufm/VCC undriven or does not drive anything - clipped.
Block ram2e_ufm/GND undriven or does not drive anything - clipped.
Signal RC_0_.CN was merged into signal PHI1_c
Signal RDOE_i was merged into signal RDOE
Signal RAT.CN was merged into signal C14M_c
Signal ram2e_ufm/ufmefb/VCC undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/GND undriven or does not drive anything - clipped.
Signal FS_s_0_S1[15] undriven or does not drive anything - clipped.
Signal FS_s_0_COUT[15] undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/CFGWAKE undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/wbc_ufm_irq undriven or does not drive anything -
clipped.
Signal ram2e_ufm/ufmefb/TCOC undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/TCINT undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIIRQO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPICSNEN undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMOSIEN undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMOSIO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMISOEN undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMISOO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPISCKEN undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPISCKO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C2SDAOEN undriven or does not drive anything -
clipped.
Signal ram2e_ufm/ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C2SCLOEN undriven or does not drive anything -
clipped.
Signal ram2e_ufm/ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C1SDAOEN undriven or does not drive anything -
clipped.
Signal ram2e_ufm/ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C1SCLOEN undriven or does not drive anything -
clipped.
Signal ram2e_ufm/ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLADRO4 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLWEO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLL1STBO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLL0STBO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLRSTO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLCLKO undriven or does not drive anything - clipped.
Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped.
Signal N_1 undriven or does not drive anything - clipped.
Block RefReq.CN was optimized away.
Block RDOE_RNIAM8C was optimized away.
Block nCASout.CN was optimized away.
Block ram2e_ufm/ufmefb/VCC was optimized away.
Block ram2e_ufm/ufmefb/GND was optimized away.
<A name="mrp_efb"></A><B><U><big>Embedded Functional Block Connection Summary</big></U></B>
Desired WISHBONE clock frequency: 14.4 MHz
Clock source: C14M_c
Reset source: ram2e_ufm/wb_rst
Functions mode:
I2C #1 (Primary) Function: DISABLED
I2C #2 (Secondary) Function: DISABLED
SPI Function: DISABLED
Timer/Counter Function: DISABLED
Timer/Counter Mode: WB
UFM Connection: ENABLED
PLL0 Connection: DISABLED
PLL1 Connection: DISABLED
I2C Function Summary:
--------------------
None
SPI Function Summary:
--------------------
None
Timer/Counter Function Summary:
------------------------------
None
UFM Function Summary:
--------------------
UFM Utilization: General Purpose Flash Memory
Initialized UFM Pages: 321 Pages (321*128 Bits)
Available General
Purpose Flash Memory: 511 Pages (511*128 Bits)
EBR Blocks with Unique
Initialization Data: 0
WID EBR Instance
--- ------------
<A name="mrp_asic"></A><B><U><big>ASIC Components</big></U></B>
---------------
Instance Name: ram2e_ufm/ufmefb/EFBInst_0
Type: EFB
<A name="mrp_runtime"></A><B><U><big>Run Time and Memory Usage</big></U></B>
-------------------------
Total CPU Time: 0 secs
Total REAL Time: 2 secs
Peak Memory Usage: 64 MB
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights
reserved.
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<HEAD><TITLE>PAD Specification File</TITLE>
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<PRE><A name="Pad"></A>PAD Specification File
***************************
PART TYPE: LCMXO2-1200HC
Performance Grade: 4
PACKAGE: TQFP100
Package Status: Final Version 1.42
Fri Jun 07 20:50:15 2024
Pinout by Port Name:
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties |
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
| Ain[0] | 3/3 | LVCMOS33_IN | PL3A | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[1] | 2/3 | LVCMOS33_IN | PL2D | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[2] | 7/3 | LVCMOS33_IN | PL3C | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[3] | 4/3 | LVCMOS33_IN | PL3B | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[4] | 78/0 | LVCMOS33_IN | PT16C | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[5] | 84/0 | LVCMOS33_IN | PT15A | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[6] | 86/0 | LVCMOS33_IN | PT12C | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[7] | 8/3 | LVCMOS33_IN | PL3D | | | CLAMP:ON HYSTERESIS:SMALL |
| BA[0] | 58/1 | LVCMOS33_OUT | PR9A | | | DRIVE:4mA SLEW:SLOW |
| BA[1] | 60/1 | LVCMOS33_OUT | PR8C | | | DRIVE:4mA SLEW:SLOW |
| C14M | 62/1 | LVCMOS33_IN | PR5D | | | CLAMP:ON HYSTERESIS:SMALL |
| CKEout | 53/1 | LVCMOS33_OUT | PR9D | | | DRIVE:4mA SLEW:SLOW |
| DQMH | 49/2 | LVCMOS33_OUT | PB20D | | | DRIVE:4mA SLEW:SLOW |
| DQML | 48/2 | LVCMOS33_OUT | PB20C | | | DRIVE:4mA SLEW:SLOW |
| Din[0] | 96/0 | LVCMOS33_IN | PT10B | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[1] | 97/0 | LVCMOS33_IN | PT10A | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[2] | 98/0 | LVCMOS33_IN | PT9B | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[3] | 9/3 | LVCMOS33_IN | PL4A | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[4] | 1/3 | LVCMOS33_IN | PL2C | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[5] | 99/0 | LVCMOS33_IN | PT9A | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[6] | 88/0 | LVCMOS33_IN | PT12A | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[7] | 87/0 | LVCMOS33_IN | PT12B | | | CLAMP:ON HYSTERESIS:SMALL |
| Dout[0] | 30/2 | LVCMOS33_OUT | PB6B | | | DRIVE:4mA SLEW:SLOW |
| Dout[1] | 27/2 | LVCMOS33_OUT | PB4C | | | DRIVE:4mA SLEW:SLOW |
| Dout[2] | 25/3 | LVCMOS33_OUT | PL10D | | | DRIVE:4mA SLEW:SLOW |
| Dout[3] | 28/2 | LVCMOS33_OUT | PB4D | | | DRIVE:4mA SLEW:SLOW |
| Dout[4] | 24/3 | LVCMOS33_OUT | PL10C | | | DRIVE:4mA SLEW:SLOW |
| Dout[5] | 21/3 | LVCMOS33_OUT | PL9B | | | DRIVE:4mA SLEW:SLOW |
| Dout[6] | 31/2 | LVCMOS33_OUT | PB6C | | | DRIVE:4mA SLEW:SLOW |
| Dout[7] | 32/2 | LVCMOS33_OUT | PB6D | | | DRIVE:4mA SLEW:SLOW |
| LED | 35/2 | LVCMOS33_OUT | PB9B | | | DRIVE:4mA SLEW:SLOW |
| PHI1 | 85/0 | LVCMOS33_IN | PT12D | | | CLAMP:ON HYSTERESIS:SMALL |
| RAout[0] | 66/1 | LVCMOS33_OUT | PR4D | | | DRIVE:4mA SLEW:SLOW |
| RAout[10] | 64/1 | LVCMOS33_OUT | PR5B | | | DRIVE:4mA SLEW:SLOW |
| RAout[11] | 59/1 | LVCMOS33_OUT | PR8D | | | DRIVE:4mA SLEW:SLOW |
| RAout[1] | 68/1 | LVCMOS33_OUT | PR4B | | | DRIVE:4mA SLEW:SLOW |
| RAout[2] | 70/1 | LVCMOS33_OUT | PR3B | | | DRIVE:4mA SLEW:SLOW |
| RAout[3] | 74/1 | LVCMOS33_OUT | PR2B | | | DRIVE:4mA SLEW:SLOW |
| RAout[4] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA SLEW:SLOW |
| RAout[5] | 71/1 | LVCMOS33_OUT | PR3A | | | DRIVE:4mA SLEW:SLOW |
| RAout[6] | 69/1 | LVCMOS33_OUT | PR4A | | | DRIVE:4mA SLEW:SLOW |
| RAout[7] | 67/1 | LVCMOS33_OUT | PR4C | | | DRIVE:4mA SLEW:SLOW |
| RAout[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA SLEW:SLOW |
| RAout[9] | 63/1 | LVCMOS33_OUT | PR5C | | | DRIVE:4mA SLEW:SLOW |
| RD[0] | 36/2 | LVCMOS33_BIDI | PB11C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[1] | 37/2 | LVCMOS33_BIDI | PB11D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[2] | 38/2 | LVCMOS33_BIDI | PB11A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[3] | 39/2 | LVCMOS33_BIDI | PB11B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[4] | 40/2 | LVCMOS33_BIDI | PB15A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[5] | 41/2 | LVCMOS33_BIDI | PB15B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[6] | 42/2 | LVCMOS33_BIDI | PB18A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[7] | 43/2 | LVCMOS33_BIDI | PB18B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| Vout[0] | 18/3 | LVCMOS33_OUT | PL8C | | | DRIVE:4mA SLEW:SLOW |
| Vout[1] | 15/3 | LVCMOS33_OUT | PL5D | | | DRIVE:4mA SLEW:SLOW |
| Vout[2] | 17/3 | LVCMOS33_OUT | PL8B | | | DRIVE:4mA SLEW:SLOW |
| Vout[3] | 13/3 | LVCMOS33_OUT | PL5B | | | DRIVE:4mA SLEW:SLOW |
| Vout[4] | 19/3 | LVCMOS33_OUT | PL8D | | | DRIVE:4mA SLEW:SLOW |
| Vout[5] | 16/3 | LVCMOS33_OUT | PL8A | | | DRIVE:4mA SLEW:SLOW |
| Vout[6] | 14/3 | LVCMOS33_OUT | PL5C | | | DRIVE:4mA SLEW:SLOW |
| Vout[7] | 12/3 | LVCMOS33_OUT | PL5A | | | DRIVE:4mA SLEW:SLOW |
| nC07X | 34/2 | LVCMOS33_IN | PB9A | | | CLAMP:ON HYSTERESIS:SMALL |
| nCASout | 52/1 | LVCMOS33_OUT | PR10C | | | DRIVE:4mA SLEW:SLOW |
| nCSout | 57/1 | LVCMOS33_OUT | PR9B | | | DRIVE:4mA SLEW:SLOW |
| nDHGROE | 47/2 | LVCMOS33_OUT | PB18D | | | DRIVE:4mA SLEW:SLOW |
| nDOE | 20/3 | LVCMOS33_OUT | PL9A | | | DRIVE:4mA SLEW:SLOW |
| nEN80 | 82/0 | LVCMOS33_IN | PT15C | | | CLAMP:ON HYSTERESIS:SMALL |
| nRASout | 54/1 | LVCMOS33_OUT | PR9C | | | DRIVE:4mA SLEW:SLOW |
| nRWEout | 51/1 | LVCMOS33_OUT | PR10D | | | DRIVE:4mA SLEW:SLOW |
| nVOE | 10/3 | LVCMOS33_OUT | PL4B | | | DRIVE:4mA SLEW:SLOW |
| nWE | 29/2 | LVCMOS33_IN | PB6A | | | CLAMP:ON HYSTERESIS:SMALL |
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
Vccio by Bank:
+------+-------+
| Bank | Vccio |
+------+-------+
| 0 | 3.3V |
| 1 | 3.3V |
| 2 | 3.3V |
| 3 | 3.3V |
+------+-------+
<A name="pad_vref"></A><B><U><big>Vref by Bank:</big></U></B>
+------+-----+-----------------+---------+
| Vref | Pin | Bank # / Vref # | Load(s) |
+------+-----+-----------------+---------+
+------+-----+-----------------+---------+
<A name="pad_pin"></A><B><U><big>Pinout by Pin Number:</big></U></B>
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable |
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
| 1/3 | Din[4] | LOCATED | LVCMOS33_IN | PL2C | L_GPLLT_IN | | |
| 2/3 | Ain[1] | LOCATED | LVCMOS33_IN | PL2D | L_GPLLC_IN | | |
| 3/3 | Ain[0] | LOCATED | LVCMOS33_IN | PL3A | PCLKT3_2 | | |
| 4/3 | Ain[3] | LOCATED | LVCMOS33_IN | PL3B | PCLKC3_2 | | |
| 7/3 | Ain[2] | LOCATED | LVCMOS33_IN | PL3C | | | |
| 8/3 | Ain[7] | LOCATED | LVCMOS33_IN | PL3D | | | |
| 9/3 | Din[3] | LOCATED | LVCMOS33_IN | PL4A | | | |
| 10/3 | nVOE | LOCATED | LVCMOS33_OUT | PL4B | | | |
| 12/3 | Vout[7] | LOCATED | LVCMOS33_OUT | PL5A | PCLKT3_1 | | |
| 13/3 | Vout[3] | LOCATED | LVCMOS33_OUT | PL5B | PCLKC3_1 | | |
| 14/3 | Vout[6] | LOCATED | LVCMOS33_OUT | PL5C | | | |
| 15/3 | Vout[1] | LOCATED | LVCMOS33_OUT | PL5D | | | |
| 16/3 | Vout[5] | LOCATED | LVCMOS33_OUT | PL8A | | | |
| 17/3 | Vout[2] | LOCATED | LVCMOS33_OUT | PL8B | | | |
| 18/3 | Vout[0] | LOCATED | LVCMOS33_OUT | PL8C | | | |
| 19/3 | Vout[4] | LOCATED | LVCMOS33_OUT | PL8D | | | |
| 20/3 | nDOE | LOCATED | LVCMOS33_OUT | PL9A | PCLKT3_0 | | |
| 21/3 | Dout[5] | LOCATED | LVCMOS33_OUT | PL9B | PCLKC3_0 | | |
| 24/3 | Dout[4] | LOCATED | LVCMOS33_OUT | PL10C | | | |
| 25/3 | Dout[2] | LOCATED | LVCMOS33_OUT | PL10D | | | |
| 27/2 | Dout[1] | LOCATED | LVCMOS33_OUT | PB4C | CSSPIN | | |
| 28/2 | Dout[3] | LOCATED | LVCMOS33_OUT | PB4D | | | |
| 29/2 | nWE | LOCATED | LVCMOS33_IN | PB6A | | | |
| 30/2 | Dout[0] | LOCATED | LVCMOS33_OUT | PB6B | | | |
| 31/2 | Dout[6] | LOCATED | LVCMOS33_OUT | PB6C | MCLK/CCLK | | |
| 32/2 | Dout[7] | LOCATED | LVCMOS33_OUT | PB6D | SO/SPISO | | |
| 34/2 | nC07X | LOCATED | LVCMOS33_IN | PB9A | PCLKT2_0 | | |
| 35/2 | LED | LOCATED | LVCMOS33_OUT | PB9B | PCLKC2_0 | | |
| 36/2 | RD[0] | LOCATED | LVCMOS33_BIDI | PB11C | | | |
| 37/2 | RD[1] | LOCATED | LVCMOS33_BIDI | PB11D | | | |
| 38/2 | RD[2] | LOCATED | LVCMOS33_BIDI | PB11A | PCLKT2_1 | | |
| 39/2 | RD[3] | LOCATED | LVCMOS33_BIDI | PB11B | PCLKC2_1 | | |
| 40/2 | RD[4] | LOCATED | LVCMOS33_BIDI | PB15A | | | |
| 41/2 | RD[5] | LOCATED | LVCMOS33_BIDI | PB15B | | | |
| 42/2 | RD[6] | LOCATED | LVCMOS33_BIDI | PB18A | | | |
| 43/2 | RD[7] | LOCATED | LVCMOS33_BIDI | PB18B | | | |
| 45/2 | unused, PULL:DOWN | | | PB18C | | | |
| 47/2 | nDHGROE | LOCATED | LVCMOS33_OUT | PB18D | | | |
| 48/2 | DQML | LOCATED | LVCMOS33_OUT | PB20C | SN | | |
| 49/2 | DQMH | LOCATED | LVCMOS33_OUT | PB20D | SI/SISPI | | |
| 51/1 | nRWEout | LOCATED | LVCMOS33_OUT | PR10D | DQ1 | | |
| 52/1 | nCASout | LOCATED | LVCMOS33_OUT | PR10C | DQ1 | | |
| 53/1 | CKEout | LOCATED | LVCMOS33_OUT | PR9D | DQ1 | | |
| 54/1 | nRASout | LOCATED | LVCMOS33_OUT | PR9C | DQ1 | | |
| 57/1 | nCSout | LOCATED | LVCMOS33_OUT | PR9B | DQ1 | | |
| 58/1 | BA[0] | LOCATED | LVCMOS33_OUT | PR9A | DQ1 | | |
| 59/1 | RAout[11] | LOCATED | LVCMOS33_OUT | PR8D | DQ1 | | |
| 60/1 | BA[1] | LOCATED | LVCMOS33_OUT | PR8C | DQ1 | | |
| 61/1 | unused, PULL:DOWN | | | PR8A | DQS1 | | |
| 62/1 | C14M | LOCATED | LVCMOS33_IN | PR5D | PCLKC1_0/DQ0 | | |
| 63/1 | RAout[9] | LOCATED | LVCMOS33_OUT | PR5C | PCLKT1_0/DQ0 | | |
| 64/1 | RAout[10] | LOCATED | LVCMOS33_OUT | PR5B | DQS0N | | |
| 65/1 | RAout[8] | LOCATED | LVCMOS33_OUT | PR5A | DQS0 | | |
| 66/1 | RAout[0] | LOCATED | LVCMOS33_OUT | PR4D | DQ0 | | |
| 67/1 | RAout[7] | LOCATED | LVCMOS33_OUT | PR4C | DQ0 | | |
| 68/1 | RAout[1] | LOCATED | LVCMOS33_OUT | PR4B | DQ0 | | |
| 69/1 | RAout[6] | LOCATED | LVCMOS33_OUT | PR4A | DQ0 | | |
| 70/1 | RAout[2] | LOCATED | LVCMOS33_OUT | PR3B | DQ0 | | |
| 71/1 | RAout[5] | LOCATED | LVCMOS33_OUT | PR3A | DQ0 | | |
| 74/1 | RAout[3] | LOCATED | LVCMOS33_OUT | PR2B | DQ0 | | |
| 75/1 | RAout[4] | LOCATED | LVCMOS33_OUT | PR2A | DQ0 | | |
| 76/0 | unused, PULL:DOWN | | | PT17D | DONE | | |
| 77/0 | unused, PULL:DOWN | | | PT17C | INITN | | |
| 78/0 | Ain[4] | LOCATED | LVCMOS33_IN | PT16C | | | |
| 81/0 | unused, PULL:DOWN | | | PT15D | PROGRAMN | | |
| 82/0 | nEN80 | LOCATED | LVCMOS33_IN | PT15C | JTAGENB | | |
| 83/0 | unused, PULL:DOWN | | | PT15B | | | |
| 84/0 | Ain[5] | LOCATED | LVCMOS33_IN | PT15A | | | |
| 85/0 | PHI1 | LOCATED | LVCMOS33_IN | PT12D | SDA/PCLKC0_0 | | |
| 86/0 | Ain[6] | LOCATED | LVCMOS33_IN | PT12C | SCL/PCLKT0_0 | | |
| 87/0 | Din[7] | LOCATED | LVCMOS33_IN | PT12B | PCLKC0_1 | | |
| 88/0 | Din[6] | LOCATED | LVCMOS33_IN | PT12A | PCLKT0_1 | | |
| 90/0 | Reserved: sysCONFIG | | | PT11D | TMS | | |
| 91/0 | Reserved: sysCONFIG | | | PT11C | TCK | | |
| 94/0 | Reserved: sysCONFIG | | | PT10D | TDI | | |
| 95/0 | Reserved: sysCONFIG | | | PT10C | TDO | | |
| 96/0 | Din[0] | LOCATED | LVCMOS33_IN | PT10B | | | |
| 97/0 | Din[1] | LOCATED | LVCMOS33_IN | PT10A | | | |
| 98/0 | Din[2] | LOCATED | LVCMOS33_IN | PT9B | | | |
| 99/0 | Din[5] | LOCATED | LVCMOS33_IN | PT9A | | | |
| PB4A/2 | unused, PULL:DOWN | | | PB4A | | | |
| PB4B/2 | unused, PULL:DOWN | | | PB4B | | | |
| PB9C/2 | unused, PULL:DOWN | | | PB9C | | | |
| PB9D/2 | unused, PULL:DOWN | | | PB9D | | | |
| PB15C/2 | unused, PULL:DOWN | | | PB15C | | | |
| PB15D/2 | unused, PULL:DOWN | | | PB15D | | | |
| PB20A/2 | unused, PULL:DOWN | | | PB20A | | | |
| PB20B/2 | unused, PULL:DOWN | | | PB20B | | | |
| PL2A/3 | unused, PULL:DOWN | | | PL2A | L_GPLLT_FB | | |
| PL2B/3 | unused, PULL:DOWN | | | PL2B | L_GPLLC_FB | | |
| PL4C/3 | unused, PULL:DOWN | | | PL4C | | | |
| PL4D/3 | unused, PULL:DOWN | | | PL4D | | | |
| PL10A/3 | unused, PULL:DOWN | | | PL10A | | | |
| PL10B/3 | unused, PULL:DOWN | | | PL10B | | | |
| PR2C/1 | unused, PULL:DOWN | | | PR2C | DQ0 | | |
| PR2D/1 | unused, PULL:DOWN | | | PR2D | DQ0 | | |
| PR8B/1 | unused, PULL:DOWN | | | PR8B | DQS1N | | |
| PR10A/1 | unused, PULL:DOWN | | | PR10A | DQ1 | | |
| PR10B/1 | unused, PULL:DOWN | | | PR10B | DQ1 | | |
| PT9C/0 | unused, PULL:DOWN | | | PT9C | | | |
| PT9D/0 | unused, PULL:DOWN | | | PT9D | | | |
| PT11A/0 | unused, PULL:DOWN | | | PT11A | | | |
| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | |
| PT16A/0 | unused, PULL:DOWN | | | PT16A | | | |
| PT16B/0 | unused, PULL:DOWN | | | PT16B | | | |
| PT16D/0 | unused, PULL:DOWN | | | PT16D | | | |
| PT17A/0 | unused, PULL:DOWN | | | PT17A | | | |
| PT17B/0 | unused, PULL:DOWN | | | PT17B | | | |
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
sysCONFIG Pins:
+----------+--------------------+--------------------+----------+-------------+-------------------+
| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode |
+----------+--------------------+--------------------+----------+-------------+-------------------+
| PT11D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP |
| PT11C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down |
| PT10D | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP |
| PT10C | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP |
+----------+--------------------+--------------------+----------+-------------+-------------------+
Dedicated sysCONFIG Pins:
List of All Pins' Locate Preferences Based on Final Placement After PAR
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste):
LOCATE COMP "Ain[0]" SITE "3";
LOCATE COMP "Ain[1]" SITE "2";
LOCATE COMP "Ain[2]" SITE "7";
LOCATE COMP "Ain[3]" SITE "4";
LOCATE COMP "Ain[4]" SITE "78";
LOCATE COMP "Ain[5]" SITE "84";
LOCATE COMP "Ain[6]" SITE "86";
LOCATE COMP "Ain[7]" SITE "8";
LOCATE COMP "BA[0]" SITE "58";
LOCATE COMP "BA[1]" SITE "60";
LOCATE COMP "C14M" SITE "62";
LOCATE COMP "CKEout" SITE "53";
LOCATE COMP "DQMH" SITE "49";
LOCATE COMP "DQML" SITE "48";
LOCATE COMP "Din[0]" SITE "96";
LOCATE COMP "Din[1]" SITE "97";
LOCATE COMP "Din[2]" SITE "98";
LOCATE COMP "Din[3]" SITE "9";
LOCATE COMP "Din[4]" SITE "1";
LOCATE COMP "Din[5]" SITE "99";
LOCATE COMP "Din[6]" SITE "88";
LOCATE COMP "Din[7]" SITE "87";
LOCATE COMP "Dout[0]" SITE "30";
LOCATE COMP "Dout[1]" SITE "27";
LOCATE COMP "Dout[2]" SITE "25";
LOCATE COMP "Dout[3]" SITE "28";
LOCATE COMP "Dout[4]" SITE "24";
LOCATE COMP "Dout[5]" SITE "21";
LOCATE COMP "Dout[6]" SITE "31";
LOCATE COMP "Dout[7]" SITE "32";
LOCATE COMP "LED" SITE "35";
LOCATE COMP "PHI1" SITE "85";
LOCATE COMP "RAout[0]" SITE "66";
LOCATE COMP "RAout[10]" SITE "64";
LOCATE COMP "RAout[11]" SITE "59";
LOCATE COMP "RAout[1]" SITE "68";
LOCATE COMP "RAout[2]" SITE "70";
LOCATE COMP "RAout[3]" SITE "74";
LOCATE COMP "RAout[4]" SITE "75";
LOCATE COMP "RAout[5]" SITE "71";
LOCATE COMP "RAout[6]" SITE "69";
LOCATE COMP "RAout[7]" SITE "67";
LOCATE COMP "RAout[8]" SITE "65";
LOCATE COMP "RAout[9]" SITE "63";
LOCATE COMP "RD[0]" SITE "36";
LOCATE COMP "RD[1]" SITE "37";
LOCATE COMP "RD[2]" SITE "38";
LOCATE COMP "RD[3]" SITE "39";
LOCATE COMP "RD[4]" SITE "40";
LOCATE COMP "RD[5]" SITE "41";
LOCATE COMP "RD[6]" SITE "42";
LOCATE COMP "RD[7]" SITE "43";
LOCATE COMP "Vout[0]" SITE "18";
LOCATE COMP "Vout[1]" SITE "15";
LOCATE COMP "Vout[2]" SITE "17";
LOCATE COMP "Vout[3]" SITE "13";
LOCATE COMP "Vout[4]" SITE "19";
LOCATE COMP "Vout[5]" SITE "16";
LOCATE COMP "Vout[6]" SITE "14";
LOCATE COMP "Vout[7]" SITE "12";
LOCATE COMP "nC07X" SITE "34";
LOCATE COMP "nCASout" SITE "52";
LOCATE COMP "nCSout" SITE "57";
LOCATE COMP "nDHGROE" SITE "47";
LOCATE COMP "nDOE" SITE "20";
LOCATE COMP "nEN80" SITE "82";
LOCATE COMP "nRASout" SITE "54";
LOCATE COMP "nRWEout" SITE "51";
LOCATE COMP "nVOE" SITE "10";
LOCATE COMP "nWE" SITE "29";
PAR: Place And Route Diamond (64-bit) 3.11.3.469.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Fri Jun 07 20:50:20 2024
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<PRE><A name="Par"></A>PAR: Place And Route Diamond (64-bit) 3.11.3.469.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&amp;T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Fri Jun 07 20:50:07 2024
C:/lscc/diamond/3.11_x64/ispfpga\bin\nt64\par -f RAM2E_LCMXO2_1200HC_impl1.p2t
RAM2E_LCMXO2_1200HC_impl1_map.ncd RAM2E_LCMXO2_1200HC_impl1.dir
RAM2E_LCMXO2_1200HC_impl1.prf -gui
Preference file: RAM2E_LCMXO2_1200HC_impl1.prf.
<A name="par_cts"></A><B><U><big>Cost Table Summary</big></U></B>
Level/ Number Worst Timing Worst Timing Run NCD
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
---------- -------- ----- ------ ----------- ----------- ---- ------
5_1 * 0 56.210 0 0.326 0 17 Completed
* : Design saved.
Total (real) run time for 1-seed: 17 secs
par done!
Note: user must run &apos;Trace&apos; for timing closure signoff.
Lattice Place and Route Report for Design &quot;RAM2E_LCMXO2_1200HC_impl1_map.ncd&quot;
Fri Jun 07 20:50:07 2024
<A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
PAR: Place And Route Diamond (64-bit) 3.11.3.469.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF RAM2E_LCMXO2_1200HC_impl1_map.ncd RAM2E_LCMXO2_1200HC_impl1.dir/5_1.ncd RAM2E_LCMXO2_1200HC_impl1.prf
Preference file: RAM2E_LCMXO2_1200HC_impl1.prf.
Placement level-cost: 5-1.
Routing Iterations: 6
Loading design for application par from file RAM2E_LCMXO2_1200HC_impl1_map.ncd.
Design name: RAM2E
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-1200HC
Package: TQFP100
Performance: 4
Loading device for application par from file &apos;xo2c1200.nph&apos; in environment: C:/lscc/diamond/3.11_x64/ispfpga.
Package Status: Final Version 1.42.
Performance Hardware Data Status: Final Version 34.4.
License checked out.
Ignore Preference Error(s): True
<A name="par_dus"></A><B><U><big>Device utilization summary:</big></U></B>
PIO (prelim) 70+4(JTAG)/108 69% used
70+4(JTAG)/80 93% bonded
IOLOGIC 22/108 20% used
SLICE 148/640 23% used
EFB 1/1 100% used
Number of Signals: 465
Number of Connections: 1330
Pin Constraint Summary:
70 out of 70 pins locked (100% locked).
The following 1 signal is selected to use the primary clock routing resources:
C14M_c (driver: C14M, clk load #: 85)
WARNING - par: Signal &quot;C14M_c&quot; is selected to use Primary clock resources. However, its driver comp &quot;C14M&quot; is located at &quot;62&quot;, which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
The following 1 signal is selected to use the secondary clock routing resources:
RWBank14 (driver: ram2e_ufm/SLICE_82, clk load #: 0, sr load #: 0, ce load #: 11)
No signal is selected as Global Set/Reset.
Starting Placer Phase 0.
.......
Finished Placer Phase 0. REAL time: 2 secs
Starting Placer Phase 1.
....................
Placer score = 84481.
Finished Placer Phase 1. REAL time: 8 secs
Starting Placer Phase 2.
.
Placer score = 83723
Finished Placer Phase 2. REAL time: 8 secs
<A name="par_clk"></A><B><U><big>Clock Report</big></U></B>
Global Clock Resources:
CLK_PIN : 0 out of 8 (0%)
General PIO: 1 out of 108 (0%)
PLL : 0 out of 1 (0%)
DCM : 0 out of 2 (0%)
DCC : 0 out of 8 (0%)
Global Clocks:
PRIMARY &quot;C14M_c&quot; from comp &quot;C14M&quot; on PIO site &quot;62 (PR5D)&quot;, clk load = 85
SECONDARY &quot;RWBank14&quot; from F0 on comp &quot;ram2e_ufm/SLICE_82&quot; on site &quot;R7C12A&quot;, clk load = 0, ce load = 11, sr load = 0
PRIMARY : 1 out of 8 (12%)
SECONDARY: 1 out of 8 (12%)
Edge Clocks:
No edge clock selected.
I/O Usage Summary (final):
70 + 4(JTAG) out of 108 (68.5%) PIO sites used.
70 + 4(JTAG) out of 80 (92.5%) bonded PIO sites used.
Number of PIO comps: 70; differential: 0.
Number of Vref pins used: 0.
I/O Bank Usage Summary:
+----------+----------------+------------+-----------+
| I/O Bank | Usage | Bank Vccio | Bank Vref |
+----------+----------------+------------+-----------+
| 0 | 11 / 19 ( 57%) | 3.3V | - |
| 1 | 20 / 21 ( 95%) | 3.3V | - |
| 2 | 19 / 20 ( 95%) | 3.3V | - |
| 3 | 20 / 20 (100%) | 3.3V | - |
+----------+----------------+------------+-----------+
Total placer CPU time: 7 secs
Dumping design to file RAM2E_LCMXO2_1200HC_impl1.dir/5_1.ncd.
0 connections routed; 1330 unrouted.
Starting router resource preassignment
WARNING - par: The driver of primary clock net C14M_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
Signal=PHI1_c loads=5 clock_loads=3
Completed router resource preassignment. Real time: 14 secs
Start NBR router at 20:50:21 06/07/24
*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
in the earlier iterations. In each iteration, it tries to
solve the conflicts while keeping the critical connections
routed as short as possible. The routing process is said to
be completed when no conflicts exist and all connections
are routed.
Note: NBR uses a different method to calculate timing slacks. The
worst slack and total negative slack may not be the same as
that in TRCE report. You should always run TRCE to verify
your design.
*****************************************************************
Start NBR special constraint process at 20:50:21 06/07/24
Start NBR section for initial routing at 20:50:21 06/07/24
Level 4, iteration 1
19(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 56.222ns/0.000ns; real time: 15 secs
Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area at 75% usage is 0 (0.00%)
Start NBR section for normal routing at 20:50:22 06/07/24
Level 4, iteration 1
6(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 56.222ns/0.000ns; real time: 15 secs
Level 4, iteration 2
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 56.210ns/0.000ns; real time: 15 secs
Level 4, iteration 3
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 56.210ns/0.000ns; real time: 15 secs
Start NBR section for setup/hold timing optimization with effort level 3 at 20:50:22 06/07/24
Start NBR section for re-routing at 20:50:23 06/07/24
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 56.210ns/0.000ns; real time: 16 secs
Start NBR section for post-routing at 20:50:23 06/07/24
End NBR router with 0 unrouted connection
NBR Summary
-----------
Number of unrouted connections : 0 (0.00%)
Number of connections with timing violations : 0 (0.00%)
Estimated worst slack&lt;setup&gt; : 56.210ns
Timing score&lt;setup&gt; : 0
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
Signal=PHI1_c loads=5 clock_loads=3
Total CPU time 14 secs
Total REAL time: 16 secs
Completely routed.
End of route. 1330 routed (100.00%); 0 unrouted.
Hold time timing score: 0, hold timing errors: 0
Timing score: 0
Dumping design to file RAM2E_LCMXO2_1200HC_impl1.dir/5_1.ncd.
All signals are completely routed.
PAR_SUMMARY::Run status = Completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst slack&lt;setup/&lt;ns&gt;&gt; = 56.210
PAR_SUMMARY::Timing score&lt;setup/&lt;ns&gt;&gt; = 0.000
PAR_SUMMARY::Worst slack&lt;hold /&lt;ns&gt;&gt; = 0.326
PAR_SUMMARY::Timing score&lt;hold /&lt;ns&gt;&gt; = 0.000
PAR_SUMMARY::Number of errors = 0
Total CPU time to completion: 14 secs
Total REAL time to completion: 17 secs
par done!
Note: user must run &apos;Trace&apos; for timing closure signoff.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&amp;T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
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CPLD/LCMXO2-1200HC-NODHGR/impl1/RAM2E_LCMXO2_1200HC_impl1_scck.rpt Normal file
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Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
# Written on Fri Jun 7 20:49:58 2024
##### FILES SYNTAX CHECKED ##############################################
Constraint File(s): "\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc"
#Run constraint checker to find more issues with constraints.
#########################################################################
No issues found in constraint syntax.
Clock Summary
*************
Start Requested Requested Clock Clock Clock
Level Clock Frequency Period Type Group Load
-----------------------------------------------------------------------------------------------
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 121
0 - System 100.0 MHz 10.000 system system_clkgroup 0
0 - RAM2E|PHI1 100.0 MHz 10.000 inferred Inferred_clkgroup_0 9
===============================================================================================
Clock Load Summary
******************
Clock Source Clock Pin Non-clock Pin Non-clock Pin
Clock Load Pin Seq Example Seq Example Comb Example
--------------------------------------------------------------------------------------------
C14M 121 C14M(port) RAT.C - un1_C14M.I[0](inv)
System 0 - - - -
RAM2E|PHI1 9 PHI1(port) RefReq.C S[0].D[0] un1_PHI1.I[0](inv)
============================================================================================

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<PRE><TABLE border=1 width=100% cellspacing=0 cellpadding=2><small>
<TR>
<TD align='center' BGCOLOR='#000099' COLSPAN='4'><SPAN style="COLOR: #FFFFFF"><B>RAM2E_LCMXO2_1200HC project summary</B></SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Module Name:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">RAM2E_LCMXO2_1200HC</SPAN></TD>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Synthesis:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">SynplifyPro</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Name:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">impl1</SPAN></TD>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Strategy Name:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">Strategy1</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Last Process:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">JEDEC File</SPAN></TD>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">State:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">Passed</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Target Device:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">LCMXO2-1200HC-4TG100C</SPAN></TD>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Device Family:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">MachXO2</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Device Type:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">LCMXO2-1200HC</SPAN></TD>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Package Type:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">TQFP100</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Performance grade:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">4</SPAN></TD>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Operating conditions:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">COM</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Logic preference file:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">RAM2E-LCMXO2.lpf</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Physical Preference file:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">impl1/RAM2E_LCMXO2_1200HC_impl1.prf</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Product Version:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">3.11.3.469</SPAN></TD>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Patch Version:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000"></SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Updated:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2024/06/07 20:50:28</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Location:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC-NODHGR/impl1</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Project File:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC-NODHGR/RAM2E_LCMXO2_1200HC.ldf</SPAN></TD>
</TR>
</small></TABLE>
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<BR>
<BR>
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<PRE><A name="Syn"></A><B><U><big>Synthesis Report</big></U></B>
#Build: Synplify Pro (R) N-2018.03L-SP1-1, Build 443R, Apr 1 2019
#install: C:\lscc\diamond\3.11_x64\synpbase
#OS: Windows 8 6.2
#Hostname: ZANEMACWIN11
# Fri Jun 7 20:49:56 2024
#Implementation: impl1
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys HDL Compiler, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Verilog Compiler, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v" (library work)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\pmi_def.v" (library work)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v" (library work)
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v" (library work)
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC-NODHGR\REFB.v" (library work)
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\DHGR-OFF.v" (library work)
Verilog syntax check successful!
Selecting top level module RAM2E
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
Running optimization stage 1 on VHI .......
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
Running optimization stage 1 on VLO .......
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
Running optimization stage 1 on EFB .......
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC-NODHGR\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
Running optimization stage 1 on REFB .......
@W: CL318 :"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC-NODHGR\REFB.v":9:14:9:21|*Output wb_dat_o has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output.
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v":1:7:1:15|Synthesizing module RAM2E_UFM in library work.
Running optimization stage 1 on RAM2E_UFM .......
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\DHGR-OFF.v":1:7:1:10|Synthesizing module DHGR in library work.
Running optimization stage 1 on DHGR .......
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v":1:7:1:11|Synthesizing module RAM2E in library work.
Running optimization stage 1 on RAM2E .......
Running optimization stage 2 on RAM2E .......
@N: CL159 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v":11:15:11:19|Input nWE80 is unused.
Running optimization stage 2 on DHGR .......
Running optimization stage 2 on RAM2E_UFM .......
Running optimization stage 2 on REFB .......
Running optimization stage 2 on EFB .......
Running optimization stage 2 on VLO .......
Running optimization stage 2 on VHI .......
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Fri Jun 7 20:49:57 2024
###########################################################]
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Fri Jun 7 20:49:57 2024
###########################################################]
For a summary of runtime and memory usage for all design units, please see file:
==========================================================
@L: A:\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC-NODHGR\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_comp.rt.csv
@END
At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Fri Jun 7 20:49:57 2024
###########################################################]
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Database state : \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC-NODHGR\impl1\synwork\|impl1
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Fri Jun 7 20:49:58 2024
###########################################################]
Premap Report
# Fri Jun 7 20:49:58 2024
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Lattice Technology Pre-mapping, Version maplat2018q2p1, Build 055R, Built Apr 3 2019 09:51:54
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
Reading constraint file: \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
@N: MF284 |Setting synthesis effort to medium for the design
@L: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC-NODHGR\impl1\RAM2E_LCMXO2_1200HC_impl1_scck.rpt
Printing clock summary report in "\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC-NODHGR\impl1\RAM2E_LCMXO2_1200HC_impl1_scck.rpt" file
@N: MF916 |Option synthesis_strategy=base is enabled.
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB)
@N: MF284 |Setting synthesis effort to medium for the design
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":21:4:21:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
@N: MH105 |UMR3 is only supported for HAPS-80.
@N: MH105 |UMR3 is only supported for HAPS-80.
@N: BN115 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":140:9:140:12|Removing instance dhgr (in view: work.RAM2E(verilog)) of type view:work.DHGR(verilog) because it does not drive other instances.
syn_allowed_resources : blockrams=7 set on top level netlist RAM2E
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
Clock Summary
******************
Start Requested Requested Clock Clock Clock
Level Clock Frequency Period Type Group Load
-----------------------------------------------------------------------------------------------
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 121
0 - System 100.0 MHz 10.000 system system_clkgroup 0
0 - RAM2E|PHI1 100.0 MHz 10.000 inferred Inferred_clkgroup_0 9
===============================================================================================
Clock Load Summary
***********************
Clock Source Clock Pin Non-clock Pin Non-clock Pin
Clock Load Pin Seq Example Seq Example Comb Example
--------------------------------------------------------------------------------------------
C14M 121 C14M(port) RAT.C - un1_C14M.I[0](inv)
System 0 - - - -
RAM2E|PHI1 9 PHI1(port) RefReq.C S[0].D[0] un1_PHI1.I[0](inv)
============================================================================================
@W: MT529 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":20:19:20:24|Found inferred clock RAM2E|PHI1 which controls 9 sequential elements including PHI1r. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed: 0
@S |Clock Optimization Summary
#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
2 non-gated/non-generated clock tree(s) driving 125 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
---------------------------------------------------------------------------------------
@KP:ckid0_0 C14M port 121 PHI1r
@KP:ckid0_1 PHI1 Unconstrained_port 4 RC[2:0]
=======================================================================================
##### END OF CLOCK OPTIMIZATION REPORT ######
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
Finished Pre Mapping Phase.
Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
None
None
Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
Pre-mapping successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Jun 7 20:49:59 2024
###########################################################]
Map & Optimize Report
# Fri Jun 7 20:50:00 2024
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Lattice Technology Mapper, Version maplat2018q2p1, Build 055R, Built Apr 3 2019 09:51:54
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
@N: MF284 |Setting synthesis effort to medium for the design
@N: MF916 |Option synthesis_strategy=base is enabled.
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
@N: MF284 |Setting synthesis effort to medium for the design
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
Available hyper_sources - for debug and ip models
None Found
@N: FX493 |Applying initial value "00000000" on instance RWBank[7:0].
@N: FX493 |Applying initial value "0000" on instance S[3:0].
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)
@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":14:23:14:28|Found counter in view:work.RAM2E(verilog) instance FS[15:0]
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 142MB)
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:01s 6.90ns 281 / 125
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":171:4:171:9|Boundary register BA_1_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":171:4:171:9|Boundary register BA_0_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 158MB peak: 160MB)
Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 122MB peak: 160MB)
Writing Analyst data base \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC-NODHGR\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_m.srm
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 158MB peak: 160MB)
Writing EDIF Netlist and constraint files
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC-NODHGR\impl1\RAM2E_LCMXO2_1200HC_impl1.edi
N-2018.03L-SP1-1
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 162MB peak: 164MB)
Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 164MB)
@W: MT246 :"\\mac\icloud\repos\ram2e\cpld\lcmxo2-1200hc-nodhgr\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@N: MT615 |Found clock C14M with period 69.84ns
@W: MT420 |Found inferred clock RAM2E|PHI1 with period 10.00ns. Please declare a user-defined clock on port PHI1.
##### START OF TIMING REPORT #####[
# Timing Report written on Fri Jun 7 20:50:03 2024
#
Top view: RAM2E
Requested Frequency: 14.3 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s): \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
Performance Summary
*******************
Worst slack in design: 6.897
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
----------------------------------------------------------------------------------------------------------------------
C14M 14.3 MHz 112.1 MHz 69.841 8.918 31.599 declared default_clkgroup
RAM2E|PHI1 100.0 MHz 322.2 MHz 10.000 3.103 6.897 inferred Inferred_clkgroup_0
System 100.0 MHz NA 10.000 NA 67.088 system system_clkgroup
======================================================================================================================
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
----------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
----------------------------------------------------------------------------------------------------------------
System C14M | 69.841 67.088 | No paths - | No paths - | No paths -
C14M System | 69.841 68.797 | No paths - | No paths - | No paths -
C14M C14M | 69.841 60.923 | No paths - | 34.920 31.599 | No paths -
RAM2E|PHI1 C14M | No paths - | No paths - | No paths - | Diff grp -
RAM2E|PHI1 RAM2E|PHI1 | No paths - | 10.000 6.897 | No paths - | No paths -
================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Interface Information
*********************
No IO constraint found
====================================
Detailed Report for Clock: C14M
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------
S[2] C14M FD1S3AX Q S[2] 1.366 31.599
S[3] C14M FD1S3AX Q S[3] 1.345 31.619
S[1] C14M FD1S3AX Q S[1] 1.344 31.800
S[0] C14M FD1S3AX Q S[0] 1.305 31.838
RA[0] C14M FD1P3AX Q RA[0] 1.108 33.707
RA[3] C14M FD1P3AX Q RA[3] 1.108 33.707
RA[1] C14M FD1P3AX Q RA[1] 1.044 33.771
RA[2] C14M FD1P3AX Q RA[2] 1.044 33.771
RA[4] C14M FD1P3AX Q RA[4] 1.044 33.771
RA[5] C14M FD1P3AX Q RA[5] 1.044 33.771
===========================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
-----------------------------------------------------------------------------------
VOE_i_0io C14M OFS1P3IX CD N_530 34.118 31.599
VOE_i_0io C14M OFS1P3IX D VOE_ic_i 35.009 31.800
Vout_0io[0] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[1] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[2] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[3] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[4] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[5] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[6] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[7] C14M OFS1P3DX SP Vout3 34.449 32.634
===================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 34.920
- Setup time: 0.803
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 34.118
- Propagation time: 2.519
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : 31.599
Number of logic level(s): 1
Starting point: S[2] / Q
Ending point: VOE_i_0io / CD
The start point is clocked by C14M [rising] on pin CK
The end point is clocked by C14M [falling] on pin SCLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
------------------------------------------------------------------------------------------------------------
S[2] FD1S3AX Q Out 1.366 1.366 -
S[2] Net - - - - 58
ram2e_ufm.un1_wb_adr_0_sqmuxa_2_0_a2_0[0] ORCALUT4 A In 0.000 1.366 -
ram2e_ufm.un1_wb_adr_0_sqmuxa_2_0_a2_0[0] ORCALUT4 Z Out 1.153 2.519 -
N_530 Net - - - - 3
VOE_i_0io OFS1P3IX CD In 0.000 2.519 -
============================================================================================================
====================================
Detailed Report for Clock: RAM2E|PHI1
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------
RC[1] RAM2E|PHI1 FD1S3IX Q RC[1] 1.148 6.897
RC[2] RAM2E|PHI1 FD1S3IX Q RC[2] 1.108 6.937
RC[0] RAM2E|PHI1 FD1S3IX Q RC[0] 1.148 8.179
===========================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------
RC[0] RAM2E|PHI1 FD1S3IX CD RC7 9.197 6.897
RC[1] RAM2E|PHI1 FD1S3IX CD RC7 9.197 6.897
RC[2] RAM2E|PHI1 FD1S3IX CD RC7 9.197 6.897
RC[0] RAM2E|PHI1 FD1S3IX D RC_i[0] 9.894 8.179
RC[1] RAM2E|PHI1 FD1S3IX D RC_RNO[1] 10.089 8.324
RC[2] RAM2E|PHI1 FD1S3IX D RC_RNO[2] 10.089 8.324
RefReq RAM2E|PHI1 FD1S3AX D RefReq_2 10.089 8.324
================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 10.000
- Setup time: 0.803
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 9.197
- Propagation time: 2.301
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : 6.897
Number of logic level(s): 1
Starting point: RC[1] / Q
Ending point: RC[0] / CD
The start point is clocked by RAM2E|PHI1 [falling] on pin CK
The end point is clocked by RAM2E|PHI1 [falling] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------
RC[1] FD1S3IX Q Out 1.148 1.148 -
RC[1] Net - - - - 4
RC7 ORCALUT4 A In 0.000 1.148 -
RC7 ORCALUT4 Z Out 1.153 2.301 -
RC7 Net - - - - 3
RC[0] FD1S3IX CD In 0.000 2.301 -
=================================================================================
====================================
Detailed Report for Clock: System
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------------------------------
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBACKO wb_ack 0.000 67.088
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO0 wb_dato[0] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO2 wb_dato[2] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO3 wb_dato[3] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO4 wb_dato[4] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO5 wb_dato[5] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO6 wb_dato[6] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO7 wb_dato[7] 0.000 69.313
===================================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
----------------------------------------------------------------------------------------
ram2e_ufm.RWMask[0] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[1] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[2] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[3] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[4] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[5] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[6] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[7] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.LEDEN System FD1P3AX SP N_98 69.369 67.736
ram2e_ufm.wb_cyc_stb System FD1P3AX SP N_111 69.369 67.736
========================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 69.841
- Setup time: 0.472
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 69.369
- Propagation time: 2.282
- Clock delay at starting point: 0.000 (ideal)
- Estimated clock delay at start point: -0.000
= Slack (non-critical) : 67.088
Number of logic level(s): 2
Starting point: ram2e_ufm.ufmefb.EFBInst_0 / WBACKO
Ending point: ram2e_ufm.RWMask[0] / SP
The start point is clocked by System [rising]
The end point is clocked by C14M [rising] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
----------------------------------------------------------------------------------------------------------------
ram2e_ufm.ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 -
wb_ack Net - - - - 5
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] ORCALUT4 B In 0.000 0.000 -
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] ORCALUT4 Z Out 1.017 1.017 -
un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] Net - - - - 1
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 D In 0.000 1.017 -
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 Z Out 1.265 2.282 -
N_104 Net - - - - 8
ram2e_ufm.RWMask[0] FD1P3AX SP In 0.000 2.282 -
================================================================================================================
##### END OF TIMING REPORT #####]
Timing exceptions that could not be applied
None
Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 164MB)
Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 164MB)
---------------------------------------
Resource Usage Report
Part: lcmxo2_1200hc-4
Register bits: 125 of 1280 (10%)
PIC Latch: 0
I/O cells: 70
Details:
BB: 8
CCU2D: 9
EFB: 1
FD1P3AX: 58
FD1P3IX: 1
FD1S3AX: 31
FD1S3AY: 4
FD1S3IX: 9
GSR: 1
IB: 21
IFS1P3DX: 1
INV: 4
OB: 41
OFS1P3BX: 6
OFS1P3DX: 12
OFS1P3IX: 3
ORCALUT4: 275
PUR: 1
VHI: 3
VLO: 3
Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 32MB peak: 164MB)
Process took 0h:00m:03s realtime, 0h:00m:03s cputime
# Fri Jun 7 20:50:03 2024
###########################################################]
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CPLD/LCMXO2-1200HC-NODHGR/promote.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<userSetting name="//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC-NODHGR/promote.xml" version="Diamond (64-bit) 3.11.3.469" date="Sat Jun 08 04:44:52 2024" vendor="Lattice Semiconductor Corporation" >
</userSetting>

10
CPLD/LCMXO2-1200HC-NODHGR/reportview.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE Report>
<ReportView version="2.0">
<Implement name="impl1">
<ToolReport id="tooldec" path="" status="0"/>
<ToolReport id="toolhle_genhierarchy" path="" status="0"/>
<ToolReport id="toolpio" path="" status="0"/>
<ToolReport id="toolsso" path="" status="0"/>
</Implement>
</ReportView>

6
CPLD/LCMXO2-1200HC/.setting.ini
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@ -1,4 +1,4 @@
[General]
Map.auto_tasks=MapTrace, MapVerilogSimFile
PAR.auto_tasks=PARTrace, IOTiming
Export.auto_tasks=IBIS, TimingSimFileVlg, Bitgen, Jedecgen
Map.auto_tasks=@@empty()
PAR.auto_tasks=@@empty()
Export.auto_tasks=Jedecgen

6
CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC.ldf
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@ -12,6 +12,12 @@
<Source name="REFB.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../DHGR-ON.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="impl1/impl1.xcf" type="Programming Project File" type_short="Programming">
<Options/>
</Source>
<Source name="../RAM2E-LCMXO2.lpf" type="Logic Preference" type_short="LPF">
<Options/>
</Source>

2
CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC1.sty
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@ -129,7 +129,6 @@
<Property name="PROP_PAR_RoutingCDP" value="0" time="0"/>
<Property name="PROP_PAR_RoutingCDR" value="0" time="0"/>
<Property name="PROP_PAR_RunParWithTrce" value="False" time="0"/>
<Property name="PROP_PAR_RunTimeReduction" value="True" time="0"/>
<Property name="PROP_PAR_SaveBestRsltParDes" value="1" time="0"/>
<Property name="PROP_PAR_StopZero" value="False" time="0"/>
<Property name="PROP_PAR_parHold" value="On" time="0"/>
@ -166,7 +165,6 @@
<Property name="PROP_PRE_VSynoutd" value="0" time="0"/>
<Property name="PROP_SYN_ClockConversion" value="True" time="0"/>
<Property name="PROP_SYN_CmdLineArgs" value="" time="0"/>
<Property name="PROP_SYN_DisableRegisterRep" value="False" time="0"/>
<Property name="PROP_SYN_EdfAllowDUPMod" value="False" time="0"/>
<Property name="PROP_SYN_EdfArea" value="False" time="0"/>
<Property name="PROP_SYN_EdfArrangeVHDLFiles" value="True" time="0"/>

78
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.alt Normal file
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NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
NOTE All Rights Reserved *
NOTE DATE CREATED: Fri Jun 07 20:50:35 2024 *
NOTE DESIGN NAME: RAM2E *
NOTE DEVICE NAME: LCMXO2-1200HC-4TQFP100 *
NOTE PIN ASSIGNMENTS *
NOTE PINS RD[0] : 36 : inout *
NOTE PINS LED : 35 : out *
NOTE PINS C14M : 62 : in *
NOTE PINS RD[7] : 43 : inout *
NOTE PINS RD[6] : 42 : inout *
NOTE PINS RD[5] : 41 : inout *
NOTE PINS RD[4] : 40 : inout *
NOTE PINS RD[3] : 39 : inout *
NOTE PINS RD[2] : 38 : inout *
NOTE PINS RD[1] : 37 : inout *
NOTE PINS DQMH : 49 : out *
NOTE PINS DQML : 48 : out *
NOTE PINS RAout[11] : 59 : out *
NOTE PINS RAout[10] : 64 : out *
NOTE PINS RAout[9] : 63 : out *
NOTE PINS RAout[8] : 65 : out *
NOTE PINS RAout[7] : 67 : out *
NOTE PINS RAout[6] : 69 : out *
NOTE PINS RAout[5] : 71 : out *
NOTE PINS RAout[4] : 75 : out *
NOTE PINS RAout[3] : 74 : out *
NOTE PINS RAout[2] : 70 : out *
NOTE PINS RAout[1] : 68 : out *
NOTE PINS RAout[0] : 66 : out *
NOTE PINS BA[1] : 60 : out *
NOTE PINS BA[0] : 58 : out *
NOTE PINS nRWEout : 51 : out *
NOTE PINS nCASout : 52 : out *
NOTE PINS nRASout : 54 : out *
NOTE PINS nCSout : 57 : out *
NOTE PINS CKEout : 53 : out *
NOTE PINS nVOE : 10 : out *
NOTE PINS Vout[7] : 12 : out *
NOTE PINS Vout[6] : 14 : out *
NOTE PINS Vout[5] : 16 : out *
NOTE PINS Vout[4] : 19 : out *
NOTE PINS Vout[3] : 13 : out *
NOTE PINS Vout[2] : 17 : out *
NOTE PINS Vout[1] : 15 : out *
NOTE PINS Vout[0] : 18 : out *
NOTE PINS nDOE : 20 : out *
NOTE PINS Dout[7] : 32 : out *
NOTE PINS Dout[6] : 31 : out *
NOTE PINS Dout[5] : 21 : out *
NOTE PINS Dout[4] : 24 : out *
NOTE PINS Dout[3] : 28 : out *
NOTE PINS Dout[2] : 25 : out *
NOTE PINS Dout[1] : 27 : out *
NOTE PINS Dout[0] : 30 : out *
NOTE PINS Din[7] : 87 : in *
NOTE PINS Din[6] : 88 : in *
NOTE PINS Din[5] : 99 : in *
NOTE PINS Din[4] : 1 : in *
NOTE PINS Din[3] : 9 : in *
NOTE PINS Din[2] : 98 : in *
NOTE PINS Din[1] : 97 : in *
NOTE PINS Din[0] : 96 : in *
NOTE PINS Ain[7] : 8 : in *
NOTE PINS Ain[6] : 86 : in *
NOTE PINS Ain[5] : 84 : in *
NOTE PINS Ain[4] : 78 : in *
NOTE PINS Ain[3] : 4 : in *
NOTE PINS Ain[2] : 7 : in *
NOTE PINS Ain[1] : 2 : in *
NOTE PINS Ain[0] : 3 : in *
NOTE PINS nC07X : 34 : in *
NOTE PINS nEN80 : 82 : in *
NOTE PINS nWE : 29 : in *
NOTE PINS nDHGROE : 47 : out *
NOTE PINS PHI1 : 85 : in *
NOTE CONFIGURATION MODE: NONE *
NOTE COMPRESSION: on *

59
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.areasrr Normal file
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----------------------------------------------------------------------
Report for cell RAM2E.verilog
Register bits: 125 of 1280 (10%)
PIC Latch: 0
I/O cells: 70
Cell usage:
cell count Res Usage(%)
BB 8 100.0
CCU2D 9 100.0
EFB 1 100.0
FD1P3AX 58 100.0
FD1P3IX 1 100.0
FD1S3AX 31 100.0
FD1S3AY 4 100.0
FD1S3IX 9 100.0
GSR 1 100.0
IB 21 100.0
IFS1P3DX 1 100.0
INV 4 100.0
OB 41 100.0
OFS1P3BX 6 100.0
OFS1P3DX 12 100.0
OFS1P3IX 3 100.0
ORCALUT4 275 100.0
PUR 1 100.0
VHI 3 100.0
VLO 3 100.0
SUB MODULES
RAM2E_UFM 1 100.0
REFB 1 100.0
TOTAL 494
----------------------------------------------------------------------
Report for cell RAM2E_UFM.netlist
Instance path: ram2e_ufm
Cell usage:
cell count Res Usage(%)
EFB 1 100.0
FD1P3AX 29 50.0
FD1P3IX 1 100.0
FD1S3IX 1 11.1
ORCALUT4 268 97.5
VHI 2 66.7
VLO 2 66.7
SUB MODULES
REFB 1 100.0
TOTAL 305
----------------------------------------------------------------------
Report for cell REFB.netlist
Instance path: ram2e_ufm.ufmefb
Cell usage:
cell count Res Usage(%)
EFB 1 100.0
VHI 1 33.3
VLO 1 33.3
TOTAL 3

86
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.bgn Normal file
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BITGEN: Bitstream Generator Diamond (64-bit) 3.11.3.469
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Fri Jun 07 20:50:31 2024
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC -w -jedec -gui RAM2E_LCMXO2_1200HC_impl1.ncd RAM2E_LCMXO2_1200HC_impl1.prf
Loading design for application Bitgen from file RAM2E_LCMXO2_1200HC_impl1.ncd.
Design name: RAM2E
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-1200HC
Package: TQFP100
Performance: 4
Loading device for application Bitgen from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.11_x64/ispfpga.
Package Status: Final Version 1.42.
Performance Hardware Data Status: Final Version 34.4.
Running DRC.
DRC detected 0 errors and 0 warnings.
Reading Preference File from RAM2E_LCMXO2_1200HC_impl1.prf.
Preference Summary:
+---------------------------------+---------------------------------+
| Preference | Current Setting |
+---------------------------------+---------------------------------+
| RamCfg | Reset** |
+---------------------------------+---------------------------------+
| MCCLK_FREQ | 2.08** |
+---------------------------------+---------------------------------+
| CONFIG_SECURE | OFF** |
+---------------------------------+---------------------------------+
| INBUF | ON** |
+---------------------------------+---------------------------------+
| JTAG_PORT | ENABLE** |
+---------------------------------+---------------------------------+
| SDM_PORT | DISABLE** |
+---------------------------------+---------------------------------+
| SLAVE_SPI_PORT | DISABLE** |
+---------------------------------+---------------------------------+
| MASTER_SPI_PORT | DISABLE** |
+---------------------------------+---------------------------------+
| I2C_PORT | DISABLE** |
+---------------------------------+---------------------------------+
| MUX_CONFIGURATION_PORTS | DISABLE** |
+---------------------------------+---------------------------------+
| CONFIGURATION | CFG** |
+---------------------------------+---------------------------------+
| COMPRESS_CONFIG | ON** |
+---------------------------------+---------------------------------+
| MY_ASSP | OFF** |
+---------------------------------+---------------------------------+
| ONE_TIME_PROGRAM | OFF** |
+---------------------------------+---------------------------------+
| ENABLE_TRANSFR | DISABLE** |
+---------------------------------+---------------------------------+
| SHAREDEBRINIT | DISABLE** |
+---------------------------------+---------------------------------+
| BACKGROUND_RECONFIG | OFF** |
+---------------------------------+---------------------------------+
* Default setting.
** The specified setting matches the default setting.
Creating bit map...
Bitstream Status: Final Version 1.95.
Saving bit stream in "RAM2E_LCMXO2_1200HC_impl1.jed".
===========
UFM Summary.
===========
UFM Size: 511 Pages (128*511 Bits).
UFM Utilization: General Purpose Flash Memory.
Available General Purpose Flash Memory: 511 Pages (Page 0 to Page 510).
Initialized UFM Pages: 321 Pages (Page 190 to Page 510).
Total CPU Time: 3 secs
Total REAL Time: 4 secs
Peak Memory Usage: 275 MB

5967
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.edi Normal file
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CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.mrp Normal file
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Lattice Mapping Report File for Design Module 'RAM2E'
Design Information
------------------
Command line: map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 4 -oc Commercial
RAM2E_LCMXO2_1200HC_impl1.ngd -o RAM2E_LCMXO2_1200HC_impl1_map.ncd -pr
RAM2E_LCMXO2_1200HC_impl1.prf -mp RAM2E_LCMXO2_1200HC_impl1.mrp -lpf //Mac/
iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_synpl
ify.lpf -lpf //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf -c 0 -gui
Target Vendor: LATTICE
Target Device: LCMXO2-1200HCTQFP100
Target Performance: 4
Mapper: xo2c00, version: Diamond (64-bit) 3.11.3.469
Mapped on: 06/07/24 20:50:13
Design Summary
--------------
Number of registers: 125 out of 1520 (8%)
PFU registers: 103 out of 1280 (8%)
PIO registers: 22 out of 240 (9%)
Number of SLICEs: 148 out of 640 (23%)
SLICEs as Logic/ROM: 148 out of 640 (23%)
SLICEs as RAM: 0 out of 480 (0%)
SLICEs as Carry: 9 out of 640 (1%)
Number of LUT4s: 295 out of 1280 (23%)
Number used as logic LUTs: 277
Number used as distributed RAM: 0
Number used as ripple logic: 18
Number used as shift registers: 0
Number of PIO sites used: 70 + 4(JTAG) out of 80 (93%)
Number of block RAMs: 0 out of 7 (0%)
Number of GSRs: 0 out of 1 (0%)
EFB used : Yes
JTAG used : No
Readback used : No
Oscillator used : No
Startup used : No
POR : On
Bandgap : On
Number of Power Controller: 0 out of 1 (0%)
Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%)
Number of DCCA: 0 out of 8 (0%)
Number of DCMA: 0 out of 2 (0%)
Number of PLLs: 0 out of 1 (0%)
Number of DQSDLLs: 0 out of 2 (0%)
Number of CLKDIVC: 0 out of 4 (0%)
Number of ECLKSYNCA: 0 out of 4 (0%)
Number of ECLKBRIDGECS: 0 out of 2 (0%)
Notes:-
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
distributed RAMs) + 2*(Number of ripple logic)
2. Number of logic LUT4s does not include count of distributed RAM and
ripple logic.
Number of clocks: 2
Net C14M_c: 85 loads, 63 rising, 22 falling (Driver: PIO C14M )
Net PHI1_c: 3 loads, 0 rising, 3 falling (Driver: PIO PHI1 )
Number of Clock Enables: 13
Page 1
Design: RAM2E Date: 06/07/24 20:50:13
Design Summary (cont)
---------------------
Net N_117_i: 2 loads, 0 LSLICEs
Net RWBank14: 11 loads, 11 LSLICEs
Net ram2e_ufm/wb_adr_0_sqmuxa_1_i: 1 loads, 1 LSLICEs
Net un9_VOE_0_a2_0_a2: 1 loads, 1 LSLICEs
Net un6_DOEEN_0_a2_0_a2: 2 loads, 2 LSLICEs
Net ram2e_ufm/un1_wb_adr_0_sqmuxa_2_i[0]: 8 loads, 8 LSLICEs
Net ram2e_ufm/un1_wb_cyc_stb_0_sqmuxa_1_i[0]: 1 loads, 1 LSLICEs
Net ram2e_ufm/N_111: 1 loads, 1 LSLICEs
Net ram2e_ufm/N_104: 4 loads, 4 LSLICEs
Net ram2e_ufm/N_98: 1 loads, 1 LSLICEs
Net un1_CKE48_0_i: 6 loads, 6 LSLICEs
Net N_389_i: 2 loads, 0 LSLICEs
Net Vout3: 8 loads, 0 LSLICEs
Number of LSRs: 8
Net N_148: 2 loads, 2 LSLICEs
Net N_430_i: 2 loads, 0 LSLICEs
Net RC7: 2 loads, 2 LSLICEs
Net S[2]: 2 loads, 2 LSLICEs
Net ram2e_ufm/wb_rst: 1 loads, 0 LSLICEs
Net ram2e_ufm/nRWE_0_i_o3_RNIP8E61: 1 loads, 1 LSLICEs
Net N_530: 1 loads, 0 LSLICEs
Net N_301_i: 1 loads, 1 LSLICEs
Number of nets driven by tri-state buffers: 0
Top 10 highest fanout non-clock nets:
Net S[2]: 60 loads
Net S[3]: 48 loads
Net S[1]: 46 loads
Net S[0]: 31 loads
Net FS[11]: 24 loads
Net FS[10]: 23 loads
Net FS[12]: 23 loads
Net FS[9]: 23 loads
Net FS[13]: 21 loads
Net FS[8]: 18 loads
Number of warnings: 3
Number of errors: 0
Design Errors/Warnings
----------------------
WARNING - map: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf(94): Semantic
error in "IOBUF PORT "nWE80" IO_TYPE=LVCMOS33 PULLMODE=NONE ;": Port
"nWE80" does not exist in the design. This preference has been disabled.
WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
temporarily disable certain features of the device including Power
Controller, GSR, Hardened User SPI Port, Hardened Primary User I2C Port.
Functionality is restored after the Flash Memory (UFM/Configuration)
Interface is disabled using Disable Configuration Interface command 0x26
followed by Bypass command 0xFF.
WARNING - map: IO buffer missing for top level port nWE80...logic will be
discarded.
Page 2
Design: RAM2E Date: 06/07/24 20:50:13
IO (PIO) Attributes
-------------------
+---------------------+-----------+-----------+------------+
| IO Name | Direction | Levelmode | IO |
| | | IO_TYPE | Register |
+---------------------+-----------+-----------+------------+
| RD[0] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| LED | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| C14M | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[7] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[6] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[5] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[4] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[3] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[2] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[1] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| DQMH | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| DQML | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RAout[11] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RAout[10] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RAout[9] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RAout[8] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RAout[7] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[6] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[5] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[4] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[3] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[2] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[1] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[0] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| BA[1] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
Page 3
Design: RAM2E Date: 06/07/24 20:50:13
IO (PIO) Attributes (cont)
--------------------------
| BA[0] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nRWEout | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nCASout | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nRASout | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nCSout | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| CKEout | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nVOE | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[7] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[6] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[5] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[4] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[3] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[2] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[1] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[0] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nDOE | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[7] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[6] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[5] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[4] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[3] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[2] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[1] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[0] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[7] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[6] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[5] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[4] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
Page 4
Design: RAM2E Date: 06/07/24 20:50:13
IO (PIO) Attributes (cont)
--------------------------
| Din[3] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[2] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[1] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[0] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[7] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[6] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[5] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[4] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[3] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[2] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[1] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[0] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nC07X | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nEN80 | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nWE | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nDHGROE | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| PHI1 | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
Removed logic
-------------
Block GSR_INST undriven or does not drive anything - clipped.
Block ram2e_ufm/VCC undriven or does not drive anything - clipped.
Block ram2e_ufm/GND undriven or does not drive anything - clipped.
Signal RC_0_.CN was merged into signal PHI1_c
Signal RDOE_i was merged into signal RDOE
Signal RAT.CN was merged into signal C14M_c
Signal ram2e_ufm/ufmefb/VCC undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/GND undriven or does not drive anything - clipped.
Signal FS_s_0_S1[15] undriven or does not drive anything - clipped.
Signal FS_s_0_COUT[15] undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/CFGWAKE undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/wbc_ufm_irq undriven or does not drive anything -
clipped.
Signal ram2e_ufm/ufmefb/TCOC undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/TCINT undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIIRQO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPICSNEN undriven or does not drive anything - clipped.
Page 5
Design: RAM2E Date: 06/07/24 20:50:13
Removed logic (cont)
--------------------
Signal ram2e_ufm/ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMOSIEN undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMOSIO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMISOEN undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMISOO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPISCKEN undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPISCKO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C2SDAOEN undriven or does not drive anything -
clipped.
Signal ram2e_ufm/ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C2SCLOEN undriven or does not drive anything -
clipped.
Signal ram2e_ufm/ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C1SDAOEN undriven or does not drive anything -
clipped.
Signal ram2e_ufm/ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C1SCLOEN undriven or does not drive anything -
clipped.
Signal ram2e_ufm/ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLADRO4 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLWEO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLL1STBO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLL0STBO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLRSTO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLCLKO undriven or does not drive anything - clipped.
Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped.
Signal N_1 undriven or does not drive anything - clipped.
Block RefReq.CN was optimized away.
Block RDOE_RNIAM8C was optimized away.
Block nCASout.CN was optimized away.
Block ram2e_ufm/ufmefb/VCC was optimized away.
Block ram2e_ufm/ufmefb/GND was optimized away.
Page 6
Design: RAM2E Date: 06/07/24 20:50:13
Removed logic (cont)
--------------------
Embedded Functional Block Connection Summary
--------------------------------------------
Desired WISHBONE clock frequency: 14.4 MHz
Clock source: C14M_c
Reset source: ram2e_ufm/wb_rst
Functions mode:
I2C #1 (Primary) Function: DISABLED
I2C #2 (Secondary) Function: DISABLED
SPI Function: DISABLED
Timer/Counter Function: DISABLED
Timer/Counter Mode: WB
UFM Connection: ENABLED
PLL0 Connection: DISABLED
PLL1 Connection: DISABLED
I2C Function Summary:
--------------------
None
SPI Function Summary:
--------------------
None
Timer/Counter Function Summary:
------------------------------
None
UFM Function Summary:
--------------------
UFM Utilization: General Purpose Flash Memory
Initialized UFM Pages: 321 Pages (321*128 Bits)
Available General
Purpose Flash Memory: 511 Pages (511*128 Bits)
EBR Blocks with Unique
Initialization Data: 0
WID EBR Instance
--- ------------
ASIC Components
---------------
Instance Name: ram2e_ufm/ufmefb/EFBInst_0
Type: EFB
Run Time and Memory Usage
-------------------------
Total CPU Time: 0 secs
Total REAL Time: 2 secs
Peak Memory Usage: 64 MB
Page 7
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights
reserved.

315
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.pad Normal file
View File

@ -0,0 +1,315 @@
PAD Specification File
***************************
PART TYPE: LCMXO2-1200HC
Performance Grade: 4
PACKAGE: TQFP100
Package Status: Final Version 1.42
Fri Jun 07 20:50:24 2024
Pinout by Port Name:
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties |
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
| Ain[0] | 3/3 | LVCMOS33_IN | PL3A | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[1] | 2/3 | LVCMOS33_IN | PL2D | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[2] | 7/3 | LVCMOS33_IN | PL3C | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[3] | 4/3 | LVCMOS33_IN | PL3B | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[4] | 78/0 | LVCMOS33_IN | PT16C | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[5] | 84/0 | LVCMOS33_IN | PT15A | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[6] | 86/0 | LVCMOS33_IN | PT12C | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[7] | 8/3 | LVCMOS33_IN | PL3D | | | CLAMP:ON HYSTERESIS:SMALL |
| BA[0] | 58/1 | LVCMOS33_OUT | PR9A | | | DRIVE:4mA SLEW:SLOW |
| BA[1] | 60/1 | LVCMOS33_OUT | PR8C | | | DRIVE:4mA SLEW:SLOW |
| C14M | 62/1 | LVCMOS33_IN | PR5D | | | CLAMP:ON HYSTERESIS:SMALL |
| CKEout | 53/1 | LVCMOS33_OUT | PR9D | | | DRIVE:4mA SLEW:SLOW |
| DQMH | 49/2 | LVCMOS33_OUT | PB20D | | | DRIVE:4mA SLEW:SLOW |
| DQML | 48/2 | LVCMOS33_OUT | PB20C | | | DRIVE:4mA SLEW:SLOW |
| Din[0] | 96/0 | LVCMOS33_IN | PT10B | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[1] | 97/0 | LVCMOS33_IN | PT10A | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[2] | 98/0 | LVCMOS33_IN | PT9B | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[3] | 9/3 | LVCMOS33_IN | PL4A | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[4] | 1/3 | LVCMOS33_IN | PL2C | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[5] | 99/0 | LVCMOS33_IN | PT9A | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[6] | 88/0 | LVCMOS33_IN | PT12A | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[7] | 87/0 | LVCMOS33_IN | PT12B | | | CLAMP:ON HYSTERESIS:SMALL |
| Dout[0] | 30/2 | LVCMOS33_OUT | PB6B | | | DRIVE:4mA SLEW:SLOW |
| Dout[1] | 27/2 | LVCMOS33_OUT | PB4C | | | DRIVE:4mA SLEW:SLOW |
| Dout[2] | 25/3 | LVCMOS33_OUT | PL10D | | | DRIVE:4mA SLEW:SLOW |
| Dout[3] | 28/2 | LVCMOS33_OUT | PB4D | | | DRIVE:4mA SLEW:SLOW |
| Dout[4] | 24/3 | LVCMOS33_OUT | PL10C | | | DRIVE:4mA SLEW:SLOW |
| Dout[5] | 21/3 | LVCMOS33_OUT | PL9B | | | DRIVE:4mA SLEW:SLOW |
| Dout[6] | 31/2 | LVCMOS33_OUT | PB6C | | | DRIVE:4mA SLEW:SLOW |
| Dout[7] | 32/2 | LVCMOS33_OUT | PB6D | | | DRIVE:4mA SLEW:SLOW |
| LED | 35/2 | LVCMOS33_OUT | PB9B | | | DRIVE:4mA SLEW:SLOW |
| PHI1 | 85/0 | LVCMOS33_IN | PT12D | | | CLAMP:ON HYSTERESIS:SMALL |
| RAout[0] | 66/1 | LVCMOS33_OUT | PR4D | | | DRIVE:4mA SLEW:SLOW |
| RAout[10] | 64/1 | LVCMOS33_OUT | PR5B | | | DRIVE:4mA SLEW:SLOW |
| RAout[11] | 59/1 | LVCMOS33_OUT | PR8D | | | DRIVE:4mA SLEW:SLOW |
| RAout[1] | 68/1 | LVCMOS33_OUT | PR4B | | | DRIVE:4mA SLEW:SLOW |
| RAout[2] | 70/1 | LVCMOS33_OUT | PR3B | | | DRIVE:4mA SLEW:SLOW |
| RAout[3] | 74/1 | LVCMOS33_OUT | PR2B | | | DRIVE:4mA SLEW:SLOW |
| RAout[4] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA SLEW:SLOW |
| RAout[5] | 71/1 | LVCMOS33_OUT | PR3A | | | DRIVE:4mA SLEW:SLOW |
| RAout[6] | 69/1 | LVCMOS33_OUT | PR4A | | | DRIVE:4mA SLEW:SLOW |
| RAout[7] | 67/1 | LVCMOS33_OUT | PR4C | | | DRIVE:4mA SLEW:SLOW |
| RAout[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA SLEW:SLOW |
| RAout[9] | 63/1 | LVCMOS33_OUT | PR5C | | | DRIVE:4mA SLEW:SLOW |
| RD[0] | 36/2 | LVCMOS33_BIDI | PB11C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[1] | 37/2 | LVCMOS33_BIDI | PB11D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[2] | 38/2 | LVCMOS33_BIDI | PB11A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[3] | 39/2 | LVCMOS33_BIDI | PB11B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[4] | 40/2 | LVCMOS33_BIDI | PB15A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[5] | 41/2 | LVCMOS33_BIDI | PB15B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[6] | 42/2 | LVCMOS33_BIDI | PB18A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[7] | 43/2 | LVCMOS33_BIDI | PB18B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| Vout[0] | 18/3 | LVCMOS33_OUT | PL8C | | | DRIVE:4mA SLEW:SLOW |
| Vout[1] | 15/3 | LVCMOS33_OUT | PL5D | | | DRIVE:4mA SLEW:SLOW |
| Vout[2] | 17/3 | LVCMOS33_OUT | PL8B | | | DRIVE:4mA SLEW:SLOW |
| Vout[3] | 13/3 | LVCMOS33_OUT | PL5B | | | DRIVE:4mA SLEW:SLOW |
| Vout[4] | 19/3 | LVCMOS33_OUT | PL8D | | | DRIVE:4mA SLEW:SLOW |
| Vout[5] | 16/3 | LVCMOS33_OUT | PL8A | | | DRIVE:4mA SLEW:SLOW |
| Vout[6] | 14/3 | LVCMOS33_OUT | PL5C | | | DRIVE:4mA SLEW:SLOW |
| Vout[7] | 12/3 | LVCMOS33_OUT | PL5A | | | DRIVE:4mA SLEW:SLOW |
| nC07X | 34/2 | LVCMOS33_IN | PB9A | | | CLAMP:ON HYSTERESIS:SMALL |
| nCASout | 52/1 | LVCMOS33_OUT | PR10C | | | DRIVE:4mA SLEW:SLOW |
| nCSout | 57/1 | LVCMOS33_OUT | PR9B | | | DRIVE:4mA SLEW:SLOW |
| nDHGROE | 47/2 | LVCMOS33_OUT | PB18D | | | DRIVE:4mA SLEW:SLOW |
| nDOE | 20/3 | LVCMOS33_OUT | PL9A | | | DRIVE:4mA SLEW:SLOW |
| nEN80 | 82/0 | LVCMOS33_IN | PT15C | | | CLAMP:ON HYSTERESIS:SMALL |
| nRASout | 54/1 | LVCMOS33_OUT | PR9C | | | DRIVE:4mA SLEW:SLOW |
| nRWEout | 51/1 | LVCMOS33_OUT | PR10D | | | DRIVE:4mA SLEW:SLOW |
| nVOE | 10/3 | LVCMOS33_OUT | PL4B | | | DRIVE:4mA SLEW:SLOW |
| nWE | 29/2 | LVCMOS33_IN | PB6A | | | CLAMP:ON HYSTERESIS:SMALL |
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
Vccio by Bank:
+------+-------+
| Bank | Vccio |
+------+-------+
| 0 | 3.3V |
| 1 | 3.3V |
| 2 | 3.3V |
| 3 | 3.3V |
+------+-------+
Vref by Bank:
+------+-----+-----------------+---------+
| Vref | Pin | Bank # / Vref # | Load(s) |
+------+-----+-----------------+---------+
+------+-----+-----------------+---------+
Pinout by Pin Number:
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable |
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
| 1/3 | Din[4] | LOCATED | LVCMOS33_IN | PL2C | L_GPLLT_IN | | |
| 2/3 | Ain[1] | LOCATED | LVCMOS33_IN | PL2D | L_GPLLC_IN | | |
| 3/3 | Ain[0] | LOCATED | LVCMOS33_IN | PL3A | PCLKT3_2 | | |
| 4/3 | Ain[3] | LOCATED | LVCMOS33_IN | PL3B | PCLKC3_2 | | |
| 7/3 | Ain[2] | LOCATED | LVCMOS33_IN | PL3C | | | |
| 8/3 | Ain[7] | LOCATED | LVCMOS33_IN | PL3D | | | |
| 9/3 | Din[3] | LOCATED | LVCMOS33_IN | PL4A | | | |
| 10/3 | nVOE | LOCATED | LVCMOS33_OUT | PL4B | | | |
| 12/3 | Vout[7] | LOCATED | LVCMOS33_OUT | PL5A | PCLKT3_1 | | |
| 13/3 | Vout[3] | LOCATED | LVCMOS33_OUT | PL5B | PCLKC3_1 | | |
| 14/3 | Vout[6] | LOCATED | LVCMOS33_OUT | PL5C | | | |
| 15/3 | Vout[1] | LOCATED | LVCMOS33_OUT | PL5D | | | |
| 16/3 | Vout[5] | LOCATED | LVCMOS33_OUT | PL8A | | | |
| 17/3 | Vout[2] | LOCATED | LVCMOS33_OUT | PL8B | | | |
| 18/3 | Vout[0] | LOCATED | LVCMOS33_OUT | PL8C | | | |
| 19/3 | Vout[4] | LOCATED | LVCMOS33_OUT | PL8D | | | |
| 20/3 | nDOE | LOCATED | LVCMOS33_OUT | PL9A | PCLKT3_0 | | |
| 21/3 | Dout[5] | LOCATED | LVCMOS33_OUT | PL9B | PCLKC3_0 | | |
| 24/3 | Dout[4] | LOCATED | LVCMOS33_OUT | PL10C | | | |
| 25/3 | Dout[2] | LOCATED | LVCMOS33_OUT | PL10D | | | |
| 27/2 | Dout[1] | LOCATED | LVCMOS33_OUT | PB4C | CSSPIN | | |
| 28/2 | Dout[3] | LOCATED | LVCMOS33_OUT | PB4D | | | |
| 29/2 | nWE | LOCATED | LVCMOS33_IN | PB6A | | | |
| 30/2 | Dout[0] | LOCATED | LVCMOS33_OUT | PB6B | | | |
| 31/2 | Dout[6] | LOCATED | LVCMOS33_OUT | PB6C | MCLK/CCLK | | |
| 32/2 | Dout[7] | LOCATED | LVCMOS33_OUT | PB6D | SO/SPISO | | |
| 34/2 | nC07X | LOCATED | LVCMOS33_IN | PB9A | PCLKT2_0 | | |
| 35/2 | LED | LOCATED | LVCMOS33_OUT | PB9B | PCLKC2_0 | | |
| 36/2 | RD[0] | LOCATED | LVCMOS33_BIDI | PB11C | | | |
| 37/2 | RD[1] | LOCATED | LVCMOS33_BIDI | PB11D | | | |
| 38/2 | RD[2] | LOCATED | LVCMOS33_BIDI | PB11A | PCLKT2_1 | | |
| 39/2 | RD[3] | LOCATED | LVCMOS33_BIDI | PB11B | PCLKC2_1 | | |
| 40/2 | RD[4] | LOCATED | LVCMOS33_BIDI | PB15A | | | |
| 41/2 | RD[5] | LOCATED | LVCMOS33_BIDI | PB15B | | | |
| 42/2 | RD[6] | LOCATED | LVCMOS33_BIDI | PB18A | | | |
| 43/2 | RD[7] | LOCATED | LVCMOS33_BIDI | PB18B | | | |
| 45/2 | unused, PULL:DOWN | | | PB18C | | | |
| 47/2 | nDHGROE | LOCATED | LVCMOS33_OUT | PB18D | | | |
| 48/2 | DQML | LOCATED | LVCMOS33_OUT | PB20C | SN | | |
| 49/2 | DQMH | LOCATED | LVCMOS33_OUT | PB20D | SI/SISPI | | |
| 51/1 | nRWEout | LOCATED | LVCMOS33_OUT | PR10D | DQ1 | | |
| 52/1 | nCASout | LOCATED | LVCMOS33_OUT | PR10C | DQ1 | | |
| 53/1 | CKEout | LOCATED | LVCMOS33_OUT | PR9D | DQ1 | | |
| 54/1 | nRASout | LOCATED | LVCMOS33_OUT | PR9C | DQ1 | | |
| 57/1 | nCSout | LOCATED | LVCMOS33_OUT | PR9B | DQ1 | | |
| 58/1 | BA[0] | LOCATED | LVCMOS33_OUT | PR9A | DQ1 | | |
| 59/1 | RAout[11] | LOCATED | LVCMOS33_OUT | PR8D | DQ1 | | |
| 60/1 | BA[1] | LOCATED | LVCMOS33_OUT | PR8C | DQ1 | | |
| 61/1 | unused, PULL:DOWN | | | PR8A | DQS1 | | |
| 62/1 | C14M | LOCATED | LVCMOS33_IN | PR5D | PCLKC1_0/DQ0 | | |
| 63/1 | RAout[9] | LOCATED | LVCMOS33_OUT | PR5C | PCLKT1_0/DQ0 | | |
| 64/1 | RAout[10] | LOCATED | LVCMOS33_OUT | PR5B | DQS0N | | |
| 65/1 | RAout[8] | LOCATED | LVCMOS33_OUT | PR5A | DQS0 | | |
| 66/1 | RAout[0] | LOCATED | LVCMOS33_OUT | PR4D | DQ0 | | |
| 67/1 | RAout[7] | LOCATED | LVCMOS33_OUT | PR4C | DQ0 | | |
| 68/1 | RAout[1] | LOCATED | LVCMOS33_OUT | PR4B | DQ0 | | |
| 69/1 | RAout[6] | LOCATED | LVCMOS33_OUT | PR4A | DQ0 | | |
| 70/1 | RAout[2] | LOCATED | LVCMOS33_OUT | PR3B | DQ0 | | |
| 71/1 | RAout[5] | LOCATED | LVCMOS33_OUT | PR3A | DQ0 | | |
| 74/1 | RAout[3] | LOCATED | LVCMOS33_OUT | PR2B | DQ0 | | |
| 75/1 | RAout[4] | LOCATED | LVCMOS33_OUT | PR2A | DQ0 | | |
| 76/0 | unused, PULL:DOWN | | | PT17D | DONE | | |
| 77/0 | unused, PULL:DOWN | | | PT17C | INITN | | |
| 78/0 | Ain[4] | LOCATED | LVCMOS33_IN | PT16C | | | |
| 81/0 | unused, PULL:DOWN | | | PT15D | PROGRAMN | | |
| 82/0 | nEN80 | LOCATED | LVCMOS33_IN | PT15C | JTAGENB | | |
| 83/0 | unused, PULL:DOWN | | | PT15B | | | |
| 84/0 | Ain[5] | LOCATED | LVCMOS33_IN | PT15A | | | |
| 85/0 | PHI1 | LOCATED | LVCMOS33_IN | PT12D | SDA/PCLKC0_0 | | |
| 86/0 | Ain[6] | LOCATED | LVCMOS33_IN | PT12C | SCL/PCLKT0_0 | | |
| 87/0 | Din[7] | LOCATED | LVCMOS33_IN | PT12B | PCLKC0_1 | | |
| 88/0 | Din[6] | LOCATED | LVCMOS33_IN | PT12A | PCLKT0_1 | | |
| 90/0 | Reserved: sysCONFIG | | | PT11D | TMS | | |
| 91/0 | Reserved: sysCONFIG | | | PT11C | TCK | | |
| 94/0 | Reserved: sysCONFIG | | | PT10D | TDI | | |
| 95/0 | Reserved: sysCONFIG | | | PT10C | TDO | | |
| 96/0 | Din[0] | LOCATED | LVCMOS33_IN | PT10B | | | |
| 97/0 | Din[1] | LOCATED | LVCMOS33_IN | PT10A | | | |
| 98/0 | Din[2] | LOCATED | LVCMOS33_IN | PT9B | | | |
| 99/0 | Din[5] | LOCATED | LVCMOS33_IN | PT9A | | | |
| PB4A/2 | unused, PULL:DOWN | | | PB4A | | | |
| PB4B/2 | unused, PULL:DOWN | | | PB4B | | | |
| PB9C/2 | unused, PULL:DOWN | | | PB9C | | | |
| PB9D/2 | unused, PULL:DOWN | | | PB9D | | | |
| PB15C/2 | unused, PULL:DOWN | | | PB15C | | | |
| PB15D/2 | unused, PULL:DOWN | | | PB15D | | | |
| PB20A/2 | unused, PULL:DOWN | | | PB20A | | | |
| PB20B/2 | unused, PULL:DOWN | | | PB20B | | | |
| PL2A/3 | unused, PULL:DOWN | | | PL2A | L_GPLLT_FB | | |
| PL2B/3 | unused, PULL:DOWN | | | PL2B | L_GPLLC_FB | | |
| PL4C/3 | unused, PULL:DOWN | | | PL4C | | | |
| PL4D/3 | unused, PULL:DOWN | | | PL4D | | | |
| PL10A/3 | unused, PULL:DOWN | | | PL10A | | | |
| PL10B/3 | unused, PULL:DOWN | | | PL10B | | | |
| PR2C/1 | unused, PULL:DOWN | | | PR2C | DQ0 | | |
| PR2D/1 | unused, PULL:DOWN | | | PR2D | DQ0 | | |
| PR8B/1 | unused, PULL:DOWN | | | PR8B | DQS1N | | |
| PR10A/1 | unused, PULL:DOWN | | | PR10A | DQ1 | | |
| PR10B/1 | unused, PULL:DOWN | | | PR10B | DQ1 | | |
| PT9C/0 | unused, PULL:DOWN | | | PT9C | | | |
| PT9D/0 | unused, PULL:DOWN | | | PT9D | | | |
| PT11A/0 | unused, PULL:DOWN | | | PT11A | | | |
| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | |
| PT16A/0 | unused, PULL:DOWN | | | PT16A | | | |
| PT16B/0 | unused, PULL:DOWN | | | PT16B | | | |
| PT16D/0 | unused, PULL:DOWN | | | PT16D | | | |
| PT17A/0 | unused, PULL:DOWN | | | PT17A | | | |
| PT17B/0 | unused, PULL:DOWN | | | PT17B | | | |
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
sysCONFIG Pins:
+----------+--------------------+--------------------+----------+-------------+-------------------+
| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode |
+----------+--------------------+--------------------+----------+-------------+-------------------+
| PT11D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP |
| PT11C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down |
| PT10D | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP |
| PT10C | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP |
+----------+--------------------+--------------------+----------+-------------+-------------------+
Dedicated sysCONFIG Pins:
List of All Pins' Locate Preferences Based on Final Placement After PAR
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste):
LOCATE COMP "Ain[0]" SITE "3";
LOCATE COMP "Ain[1]" SITE "2";
LOCATE COMP "Ain[2]" SITE "7";
LOCATE COMP "Ain[3]" SITE "4";
LOCATE COMP "Ain[4]" SITE "78";
LOCATE COMP "Ain[5]" SITE "84";
LOCATE COMP "Ain[6]" SITE "86";
LOCATE COMP "Ain[7]" SITE "8";
LOCATE COMP "BA[0]" SITE "58";
LOCATE COMP "BA[1]" SITE "60";
LOCATE COMP "C14M" SITE "62";
LOCATE COMP "CKEout" SITE "53";
LOCATE COMP "DQMH" SITE "49";
LOCATE COMP "DQML" SITE "48";
LOCATE COMP "Din[0]" SITE "96";
LOCATE COMP "Din[1]" SITE "97";
LOCATE COMP "Din[2]" SITE "98";
LOCATE COMP "Din[3]" SITE "9";
LOCATE COMP "Din[4]" SITE "1";
LOCATE COMP "Din[5]" SITE "99";
LOCATE COMP "Din[6]" SITE "88";
LOCATE COMP "Din[7]" SITE "87";
LOCATE COMP "Dout[0]" SITE "30";
LOCATE COMP "Dout[1]" SITE "27";
LOCATE COMP "Dout[2]" SITE "25";
LOCATE COMP "Dout[3]" SITE "28";
LOCATE COMP "Dout[4]" SITE "24";
LOCATE COMP "Dout[5]" SITE "21";
LOCATE COMP "Dout[6]" SITE "31";
LOCATE COMP "Dout[7]" SITE "32";
LOCATE COMP "LED" SITE "35";
LOCATE COMP "PHI1" SITE "85";
LOCATE COMP "RAout[0]" SITE "66";
LOCATE COMP "RAout[10]" SITE "64";
LOCATE COMP "RAout[11]" SITE "59";
LOCATE COMP "RAout[1]" SITE "68";
LOCATE COMP "RAout[2]" SITE "70";
LOCATE COMP "RAout[3]" SITE "74";
LOCATE COMP "RAout[4]" SITE "75";
LOCATE COMP "RAout[5]" SITE "71";
LOCATE COMP "RAout[6]" SITE "69";
LOCATE COMP "RAout[7]" SITE "67";
LOCATE COMP "RAout[8]" SITE "65";
LOCATE COMP "RAout[9]" SITE "63";
LOCATE COMP "RD[0]" SITE "36";
LOCATE COMP "RD[1]" SITE "37";
LOCATE COMP "RD[2]" SITE "38";
LOCATE COMP "RD[3]" SITE "39";
LOCATE COMP "RD[4]" SITE "40";
LOCATE COMP "RD[5]" SITE "41";
LOCATE COMP "RD[6]" SITE "42";
LOCATE COMP "RD[7]" SITE "43";
LOCATE COMP "Vout[0]" SITE "18";
LOCATE COMP "Vout[1]" SITE "15";
LOCATE COMP "Vout[2]" SITE "17";
LOCATE COMP "Vout[3]" SITE "13";
LOCATE COMP "Vout[4]" SITE "19";
LOCATE COMP "Vout[5]" SITE "16";
LOCATE COMP "Vout[6]" SITE "14";
LOCATE COMP "Vout[7]" SITE "12";
LOCATE COMP "nC07X" SITE "34";
LOCATE COMP "nCASout" SITE "52";
LOCATE COMP "nCSout" SITE "57";
LOCATE COMP "nDHGROE" SITE "47";
LOCATE COMP "nDOE" SITE "20";
LOCATE COMP "nEN80" SITE "82";
LOCATE COMP "nRASout" SITE "54";
LOCATE COMP "nRWEout" SITE "51";
LOCATE COMP "nVOE" SITE "10";
LOCATE COMP "nWE" SITE "29";
PAR: Place And Route Diamond (64-bit) 3.11.3.469.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Fri Jun 07 20:50:28 2024

128
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.prf Normal file
View File

@ -0,0 +1,128 @@
SCHEMATIC START ;
# map: version Diamond (64-bit) 3.11.3.469 -- WARNING: Map write only section -- Fri Jun 07 20:50:14 2024
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
LOCATE COMP "RD[0]" SITE "36" ;
LOCATE COMP "LED" SITE "35" ;
LOCATE COMP "C14M" SITE "62" ;
LOCATE COMP "RD[7]" SITE "43" ;
LOCATE COMP "RD[6]" SITE "42" ;
LOCATE COMP "RD[5]" SITE "41" ;
LOCATE COMP "RD[4]" SITE "40" ;
LOCATE COMP "RD[3]" SITE "39" ;
LOCATE COMP "RD[2]" SITE "38" ;
LOCATE COMP "RD[1]" SITE "37" ;
LOCATE COMP "DQMH" SITE "49" ;
LOCATE COMP "DQML" SITE "48" ;
LOCATE COMP "RAout[11]" SITE "59" ;
LOCATE COMP "RAout[10]" SITE "64" ;
LOCATE COMP "RAout[9]" SITE "63" ;
LOCATE COMP "RAout[8]" SITE "65" ;
LOCATE COMP "RAout[7]" SITE "67" ;
LOCATE COMP "RAout[6]" SITE "69" ;
LOCATE COMP "RAout[5]" SITE "71" ;
LOCATE COMP "RAout[4]" SITE "75" ;
LOCATE COMP "RAout[3]" SITE "74" ;
LOCATE COMP "RAout[2]" SITE "70" ;
LOCATE COMP "RAout[1]" SITE "68" ;
LOCATE COMP "RAout[0]" SITE "66" ;
LOCATE COMP "BA[1]" SITE "60" ;
LOCATE COMP "BA[0]" SITE "58" ;
LOCATE COMP "nRWEout" SITE "51" ;
LOCATE COMP "nCASout" SITE "52" ;
LOCATE COMP "nRASout" SITE "54" ;
LOCATE COMP "nCSout" SITE "57" ;
LOCATE COMP "CKEout" SITE "53" ;
LOCATE COMP "nVOE" SITE "10" ;
LOCATE COMP "Vout[7]" SITE "12" ;
LOCATE COMP "Vout[6]" SITE "14" ;
LOCATE COMP "Vout[5]" SITE "16" ;
LOCATE COMP "Vout[4]" SITE "19" ;
LOCATE COMP "Vout[3]" SITE "13" ;
LOCATE COMP "Vout[2]" SITE "17" ;
LOCATE COMP "Vout[1]" SITE "15" ;
LOCATE COMP "Vout[0]" SITE "18" ;
LOCATE COMP "nDOE" SITE "20" ;
LOCATE COMP "Dout[7]" SITE "32" ;
LOCATE COMP "Dout[6]" SITE "31" ;
LOCATE COMP "Dout[5]" SITE "21" ;
LOCATE COMP "Dout[4]" SITE "24" ;
LOCATE COMP "Dout[3]" SITE "28" ;
LOCATE COMP "Dout[2]" SITE "25" ;
LOCATE COMP "Dout[1]" SITE "27" ;
LOCATE COMP "Dout[0]" SITE "30" ;
LOCATE COMP "Din[7]" SITE "87" ;
LOCATE COMP "Din[6]" SITE "88" ;
LOCATE COMP "Din[5]" SITE "99" ;
LOCATE COMP "Din[4]" SITE "1" ;
LOCATE COMP "Din[3]" SITE "9" ;
LOCATE COMP "Din[2]" SITE "98" ;
LOCATE COMP "Din[1]" SITE "97" ;
LOCATE COMP "Din[0]" SITE "96" ;
LOCATE COMP "Ain[7]" SITE "8" ;
LOCATE COMP "Ain[6]" SITE "86" ;
LOCATE COMP "Ain[5]" SITE "84" ;
LOCATE COMP "Ain[4]" SITE "78" ;
LOCATE COMP "Ain[3]" SITE "4" ;
LOCATE COMP "Ain[2]" SITE "7" ;
LOCATE COMP "Ain[1]" SITE "2" ;
LOCATE COMP "Ain[0]" SITE "3" ;
LOCATE COMP "nC07X" SITE "34" ;
LOCATE COMP "nEN80" SITE "82" ;
LOCATE COMP "nWE" SITE "29" ;
LOCATE COMP "nDHGROE" SITE "47" ;
LOCATE COMP "PHI1" SITE "85" ;
FREQUENCY PORT "C14M" 14.300000 MHz ;
SCHEMATIC END ;
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
OUTPUT PORT "LED" LOAD 100.000000 pF ;
OUTPUT PORT "nDHGROE" LOAD 10.000000 pF ;
OUTPUT PORT "BA[1]" LOAD 5.000000 pF ;
OUTPUT PORT "BA[0]" LOAD 5.000000 pF ;
OUTPUT PORT "CKEout" LOAD 5.000000 pF ;
OUTPUT PORT "DQMH" LOAD 5.000000 pF ;
OUTPUT PORT "DQML" LOAD 5.000000 pF ;
OUTPUT PORT "Dout[0]" LOAD 15.000000 pF ;
OUTPUT PORT "Dout[1]" LOAD 15.000000 pF ;
OUTPUT PORT "Dout[2]" LOAD 15.000000 pF ;
OUTPUT PORT "Dout[3]" LOAD 15.000000 pF ;
OUTPUT PORT "Dout[4]" LOAD 15.000000 pF ;
OUTPUT PORT "Dout[5]" LOAD 15.000000 pF ;
OUTPUT PORT "Dout[6]" LOAD 15.000000 pF ;
OUTPUT PORT "Dout[7]" LOAD 15.000000 pF ;
OUTPUT PORT "RAout[0]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[1]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[2]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[3]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[4]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[5]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[6]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[7]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[8]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[9]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[10]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[11]" LOAD 5.000000 pF ;
OUTPUT PORT "Vout[0]" LOAD 15.000000 pF ;
OUTPUT PORT "Vout[1]" LOAD 15.000000 pF ;
OUTPUT PORT "Vout[2]" LOAD 15.000000 pF ;
OUTPUT PORT "Vout[3]" LOAD 15.000000 pF ;
OUTPUT PORT "Vout[4]" LOAD 15.000000 pF ;
OUTPUT PORT "Vout[5]" LOAD 15.000000 pF ;
OUTPUT PORT "Vout[6]" LOAD 15.000000 pF ;
OUTPUT PORT "Vout[7]" LOAD 15.000000 pF ;
OUTPUT PORT "nCASout" LOAD 5.000000 pF ;
OUTPUT PORT "nCSout" LOAD 5.000000 pF ;
OUTPUT PORT "nDOE" LOAD 10.000000 pF ;
OUTPUT PORT "nRASout" LOAD 5.000000 pF ;
OUTPUT PORT "nRWEout" LOAD 5.000000 pF ;
OUTPUT PORT "nVOE" LOAD 10.000000 pF ;
OUTPUT PORT "RD[0]" LOAD 9.000000 pF ;
OUTPUT PORT "RD[1]" LOAD 9.000000 pF ;
OUTPUT PORT "RD[2]" LOAD 9.000000 pF ;
OUTPUT PORT "RD[3]" LOAD 9.000000 pF ;
OUTPUT PORT "RD[4]" LOAD 9.000000 pF ;
OUTPUT PORT "RD[5]" LOAD 9.000000 pF ;
OUTPUT PORT "RD[6]" LOAD 9.000000 pF ;
OUTPUT PORT "RD[7]" LOAD 9.000000 pF ;
COMMERCIAL ;

740
CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.srr Normal file
View File

@ -0,0 +1,740 @@
#Build: Synplify Pro (R) N-2018.03L-SP1-1, Build 443R, Apr 1 2019
#install: C:\lscc\diamond\3.11_x64\synpbase
#OS: Windows 8 6.2
#Hostname: ZANEMACWIN11
# Fri Jun 7 20:50:04 2024
#Implementation: impl1
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys HDL Compiler, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Verilog Compiler, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v" (library work)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\pmi_def.v" (library work)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v" (library work)
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v" (library work)
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\REFB.v" (library work)
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\DHGR-ON.v" (library work)
Verilog syntax check successful!
Selecting top level module RAM2E
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
Running optimization stage 1 on VHI .......
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
Running optimization stage 1 on VLO .......
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
Running optimization stage 1 on EFB .......
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
Running optimization stage 1 on REFB .......
@W: CL318 :"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\REFB.v":9:14:9:21|*Output wb_dat_o has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output.
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v":1:7:1:15|Synthesizing module RAM2E_UFM in library work.
Running optimization stage 1 on RAM2E_UFM .......
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\DHGR-ON.v":1:7:1:10|Synthesizing module DHGR in library work.
Running optimization stage 1 on DHGR .......
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v":1:7:1:11|Synthesizing module RAM2E in library work.
Running optimization stage 1 on RAM2E .......
Running optimization stage 2 on RAM2E .......
@N: CL159 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v":11:15:11:19|Input nWE80 is unused.
Running optimization stage 2 on DHGR .......
Running optimization stage 2 on RAM2E_UFM .......
Running optimization stage 2 on REFB .......
Running optimization stage 2 on EFB .......
Running optimization stage 2 on VLO .......
Running optimization stage 2 on VHI .......
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Fri Jun 7 20:50:05 2024
###########################################################]
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Fri Jun 7 20:50:05 2024
###########################################################]
For a summary of runtime and memory usage for all design units, please see file:
==========================================================
@L: A:\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_comp.rt.csv
@END
At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Fri Jun 7 20:50:05 2024
###########################################################]
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Database state : \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\|impl1
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Fri Jun 7 20:50:07 2024
###########################################################]
Premap Report
# Fri Jun 7 20:50:07 2024
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Lattice Technology Pre-mapping, Version maplat2018q2p1, Build 055R, Built Apr 3 2019 09:51:54
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
Reading constraint file: \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
@N: MF284 |Setting synthesis effort to medium for the design
@L: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1_scck.rpt
Printing clock summary report in "\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1_scck.rpt" file
@N: MF916 |Option synthesis_strategy=base is enabled.
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB)
@N: MF284 |Setting synthesis effort to medium for the design
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":21:4:21:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
@N: MH105 |UMR3 is only supported for HAPS-80.
@N: MH105 |UMR3 is only supported for HAPS-80.
@N: BN115 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":140:9:140:12|Removing instance dhgr (in view: work.RAM2E(verilog)) of type view:work.DHGR(verilog) because it does not drive other instances.
syn_allowed_resources : blockrams=7 set on top level netlist RAM2E
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
Clock Summary
******************
Start Requested Requested Clock Clock Clock
Level Clock Frequency Period Type Group Load
-----------------------------------------------------------------------------------------------
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 121
0 - System 100.0 MHz 10.000 system system_clkgroup 0
0 - RAM2E|PHI1 100.0 MHz 10.000 inferred Inferred_clkgroup_0 9
===============================================================================================
Clock Load Summary
***********************
Clock Source Clock Pin Non-clock Pin Non-clock Pin
Clock Load Pin Seq Example Seq Example Comb Example
--------------------------------------------------------------------------------------------
C14M 121 C14M(port) RAT.C - un1_C14M.I[0](inv)
System 0 - - - -
RAM2E|PHI1 9 PHI1(port) RefReq.C S[0].D[0] un1_PHI1.I[0](inv)
============================================================================================
@W: MT529 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":20:19:20:24|Found inferred clock RAM2E|PHI1 which controls 9 sequential elements including PHI1r. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed: 0
@S |Clock Optimization Summary
#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
2 non-gated/non-generated clock tree(s) driving 125 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
---------------------------------------------------------------------------------------
@KP:ckid0_0 C14M port 121 PHI1r
@KP:ckid0_1 PHI1 Unconstrained_port 4 RC[2:0]
=======================================================================================
##### END OF CLOCK OPTIMIZATION REPORT ######
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
Finished Pre Mapping Phase.
Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
None
None
Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
Pre-mapping successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Jun 7 20:50:08 2024
###########################################################]
Map & Optimize Report
# Fri Jun 7 20:50:08 2024
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Lattice Technology Mapper, Version maplat2018q2p1, Build 055R, Built Apr 3 2019 09:51:54
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
@N: MF284 |Setting synthesis effort to medium for the design
@N: MF916 |Option synthesis_strategy=base is enabled.
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
@N: MF284 |Setting synthesis effort to medium for the design
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
Available hyper_sources - for debug and ip models
None Found
@N: FX493 |Applying initial value "00000000" on instance RWBank[7:0].
@N: FX493 |Applying initial value "0000" on instance S[3:0].
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)
@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":14:23:14:28|Found counter in view:work.RAM2E(verilog) instance FS[15:0]
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 142MB)
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:01s 6.90ns 281 / 125
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":171:4:171:9|Boundary register BA_1_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":171:4:171:9|Boundary register BA_0_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 158MB peak: 160MB)
Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 122MB peak: 160MB)
Writing Analyst data base \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_m.srm
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 158MB peak: 160MB)
Writing EDIF Netlist and constraint files
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1.edi
N-2018.03L-SP1-1
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 162MB peak: 164MB)
Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 161MB peak: 164MB)
@W: MT246 :"\\mac\icloud\repos\ram2e\cpld\lcmxo2-1200hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@N: MT615 |Found clock C14M with period 69.84ns
@W: MT420 |Found inferred clock RAM2E|PHI1 with period 10.00ns. Please declare a user-defined clock on port PHI1.
##### START OF TIMING REPORT #####[
# Timing Report written on Fri Jun 7 20:50:12 2024
#
Top view: RAM2E
Requested Frequency: 14.3 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s): \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
Performance Summary
*******************
Worst slack in design: 6.897
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
----------------------------------------------------------------------------------------------------------------------
C14M 14.3 MHz 112.1 MHz 69.841 8.918 31.599 declared default_clkgroup
RAM2E|PHI1 100.0 MHz 322.2 MHz 10.000 3.103 6.897 inferred Inferred_clkgroup_0
System 100.0 MHz NA 10.000 NA 67.088 system system_clkgroup
======================================================================================================================
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
----------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
----------------------------------------------------------------------------------------------------------------
System C14M | 69.841 67.088 | No paths - | No paths - | No paths -
C14M System | 69.841 68.797 | No paths - | No paths - | No paths -
C14M C14M | 69.841 60.923 | No paths - | 34.920 31.599 | No paths -
RAM2E|PHI1 C14M | No paths - | No paths - | No paths - | Diff grp -
RAM2E|PHI1 RAM2E|PHI1 | No paths - | 10.000 6.897 | No paths - | No paths -
================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Interface Information
*********************
No IO constraint found
====================================
Detailed Report for Clock: C14M
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------
S[2] C14M FD1S3AX Q S[2] 1.366 31.599
S[3] C14M FD1S3AX Q S[3] 1.345 31.619
S[1] C14M FD1S3AX Q S[1] 1.344 31.800
S[0] C14M FD1S3AX Q S[0] 1.305 31.838
RA[0] C14M FD1P3AX Q RA[0] 1.108 33.707
RA[3] C14M FD1P3AX Q RA[3] 1.108 33.707
RA[1] C14M FD1P3AX Q RA[1] 1.044 33.771
RA[2] C14M FD1P3AX Q RA[2] 1.044 33.771
RA[4] C14M FD1P3AX Q RA[4] 1.044 33.771
RA[5] C14M FD1P3AX Q RA[5] 1.044 33.771
===========================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
-----------------------------------------------------------------------------------
VOE_i_0io C14M OFS1P3IX CD N_530 34.118 31.599
VOE_i_0io C14M OFS1P3IX D VOE_ic_i 35.009 31.800
Vout_0io[0] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[1] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[2] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[3] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[4] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[5] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[6] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[7] C14M OFS1P3DX SP Vout3 34.449 32.634
===================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 34.920
- Setup time: 0.803
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 34.118
- Propagation time: 2.519
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : 31.599
Number of logic level(s): 1
Starting point: S[2] / Q
Ending point: VOE_i_0io / CD
The start point is clocked by C14M [rising] on pin CK
The end point is clocked by C14M [falling] on pin SCLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
------------------------------------------------------------------------------------------------------------
S[2] FD1S3AX Q Out 1.366 1.366 -
S[2] Net - - - - 58
ram2e_ufm.un1_wb_adr_0_sqmuxa_2_0_a2_0[0] ORCALUT4 A In 0.000 1.366 -
ram2e_ufm.un1_wb_adr_0_sqmuxa_2_0_a2_0[0] ORCALUT4 Z Out 1.153 2.519 -
N_530 Net - - - - 3
VOE_i_0io OFS1P3IX CD In 0.000 2.519 -
============================================================================================================
====================================
Detailed Report for Clock: RAM2E|PHI1
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------
RC[1] RAM2E|PHI1 FD1S3IX Q RC[1] 1.148 6.897
RC[2] RAM2E|PHI1 FD1S3IX Q RC[2] 1.108 6.937
RC[0] RAM2E|PHI1 FD1S3IX Q RC[0] 1.148 8.179
===========================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------
RC[0] RAM2E|PHI1 FD1S3IX CD RC7 9.197 6.897
RC[1] RAM2E|PHI1 FD1S3IX CD RC7 9.197 6.897
RC[2] RAM2E|PHI1 FD1S3IX CD RC7 9.197 6.897
RC[0] RAM2E|PHI1 FD1S3IX D RC_i[0] 9.894 8.179
RC[1] RAM2E|PHI1 FD1S3IX D RC_RNO[1] 10.089 8.324
RC[2] RAM2E|PHI1 FD1S3IX D RC_RNO[2] 10.089 8.324
RefReq RAM2E|PHI1 FD1S3AX D RefReq_2 10.089 8.324
================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 10.000
- Setup time: 0.803
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 9.197
- Propagation time: 2.301
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : 6.897
Number of logic level(s): 1
Starting point: RC[1] / Q
Ending point: RC[0] / CD
The start point is clocked by RAM2E|PHI1 [falling] on pin CK
The end point is clocked by RAM2E|PHI1 [falling] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------
RC[1] FD1S3IX Q Out 1.148 1.148 -
RC[1] Net - - - - 4
RC7 ORCALUT4 A In 0.000 1.148 -
RC7 ORCALUT4 Z Out 1.153 2.301 -
RC7 Net - - - - 3
RC[0] FD1S3IX CD In 0.000 2.301 -
=================================================================================
====================================
Detailed Report for Clock: System
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------------------------------
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBACKO wb_ack 0.000 67.088
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO0 wb_dato[0] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO2 wb_dato[2] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO3 wb_dato[3] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO4 wb_dato[4] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO5 wb_dato[5] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO6 wb_dato[6] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO7 wb_dato[7] 0.000 69.313
===================================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
----------------------------------------------------------------------------------------
ram2e_ufm.RWMask[0] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[1] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[2] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[3] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[4] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[5] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[6] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[7] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.LEDEN System FD1P3AX SP N_98 69.369 67.736
ram2e_ufm.wb_cyc_stb System FD1P3AX SP N_111 69.369 67.736
========================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 69.841
- Setup time: 0.472
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 69.369
- Propagation time: 2.282
- Clock delay at starting point: 0.000 (ideal)
- Estimated clock delay at start point: -0.000
= Slack (non-critical) : 67.088
Number of logic level(s): 2
Starting point: ram2e_ufm.ufmefb.EFBInst_0 / WBACKO
Ending point: ram2e_ufm.RWMask[0] / SP
The start point is clocked by System [rising]
The end point is clocked by C14M [rising] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
----------------------------------------------------------------------------------------------------------------
ram2e_ufm.ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 -
wb_ack Net - - - - 5
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] ORCALUT4 B In 0.000 0.000 -
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] ORCALUT4 Z Out 1.017 1.017 -
un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] Net - - - - 1
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 D In 0.000 1.017 -
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 Z Out 1.265 2.282 -
N_104 Net - - - - 8
ram2e_ufm.RWMask[0] FD1P3AX SP In 0.000 2.282 -
================================================================================================================
##### END OF TIMING REPORT #####]
Timing exceptions that could not be applied
None
Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 161MB peak: 164MB)
Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 161MB peak: 164MB)
---------------------------------------
Resource Usage Report
Part: lcmxo2_1200hc-4
Register bits: 125 of 1280 (10%)
PIC Latch: 0
I/O cells: 70
Details:
BB: 8
CCU2D: 9
EFB: 1
FD1P3AX: 58
FD1P3IX: 1
FD1S3AX: 31
FD1S3AY: 4
FD1S3IX: 9
GSR: 1
IB: 21
IFS1P3DX: 1
INV: 4
OB: 41
OFS1P3BX: 6
OFS1P3DX: 12
OFS1P3IX: 3
ORCALUT4: 275
PUR: 1
VHI: 3
VLO: 3
Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 33MB peak: 164MB)
Process took 0h:00m:03s realtime, 0h:00m:02s cputime
# Fri Jun 7 20:50:12 2024
###########################################################]

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Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
# Written on Fri Jun 7 20:50:08 2024
##### DESIGN INFO #######################################################
Top View: "RAM2E"
Constraint File(s): "\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc"
##### SUMMARY ############################################################
Found 0 issues in 0 out of 1 constraints
##### DETAILS ############################################################
Clock Relationships
*******************
Starting Ending | rise to rise | fall to fall | rise to fall | fall to rise
-----------------------------------------------------------------------------------------------------------------------------------------
System C14M | 69.841 | No paths | No paths | No paths
C14M System | 69.841 | No paths | No paths | No paths
C14M C14M | 69.841 | No paths | 34.920 | No paths
RAM2E|PHI1 C14M | No paths | No paths | No paths | Diff grp
RAM2E|PHI1 RAM2E|PHI1 | No paths | 10.000 | No paths | No paths
=========================================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Unconstrained Start/End Points
******************************
p:Ain[0]
p:Ain[1]
p:Ain[2]
p:Ain[3]
p:Ain[4]
p:Ain[5]
p:Ain[6]
p:Ain[7]
p:BA[0]
p:BA[1]
p:CKEout
p:DQMH
p:DQML
p:Din[0]
p:Din[1]
p:Din[2]
p:Din[3]
p:Din[4]
p:Din[5]
p:Din[6]
p:Din[7]
p:Dout[0]
p:Dout[1]
p:Dout[2]
p:Dout[3]
p:Dout[4]
p:Dout[5]
p:Dout[6]
p:Dout[7]
p:LED
p:RAout[0]
p:RAout[1]
p:RAout[2]
p:RAout[3]
p:RAout[4]
p:RAout[5]
p:RAout[6]
p:RAout[7]
p:RAout[8]
p:RAout[9]
p:RAout[10]
p:RAout[11]
p:RD[0] (bidir end point)
p:RD[0] (bidir start point)
p:RD[1] (bidir end point)
p:RD[1] (bidir start point)
p:RD[2] (bidir end point)
p:RD[2] (bidir start point)
p:RD[3] (bidir end point)
p:RD[3] (bidir start point)
p:RD[4] (bidir end point)
p:RD[4] (bidir start point)
p:RD[5] (bidir end point)
p:RD[5] (bidir start point)
p:RD[6] (bidir end point)
p:RD[6] (bidir start point)
p:RD[7] (bidir end point)
p:RD[7] (bidir start point)
p:Vout[0]
p:Vout[1]
p:Vout[2]
p:Vout[3]
p:Vout[4]
p:Vout[5]
p:Vout[6]
p:Vout[7]
p:nC07X
p:nCASout
p:nCSout
p:nDHGROE
p:nDOE
p:nEN80
p:nRASout
p:nRWEout
p:nVOE
p:nWE
p:nWE80
Inapplicable constraints
************************
(none)
Applicable constraints with issues
**********************************
(none)
Constraints with matching wildcard expressions
**********************************************
(none)
Library Report
**************
# End of Constraint Checker Report

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<HEAD><TITLE>Project Summary</TITLE>
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<PRE><A name="Mrp"></A>
Lattice Mapping Report File for Design Module 'RAM2E'
<A name="mrp_di"></A><B><U><big>Design Information</big></U></B>
Command line: map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 4 -oc Commercial
RAM2E_LCMXO2_1200HC_impl1.ngd -o RAM2E_LCMXO2_1200HC_impl1_map.ncd -pr
RAM2E_LCMXO2_1200HC_impl1.prf -mp RAM2E_LCMXO2_1200HC_impl1.mrp -lpf //Mac/
iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_synpl
ify.lpf -lpf //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf -c 0 -gui
Target Vendor: LATTICE
Target Device: LCMXO2-1200HCTQFP100
Target Performance: 4
Mapper: xo2c00, version: Diamond (64-bit) 3.11.3.469
Mapped on: 06/07/24 20:50:13
<A name="mrp_ds"></A><B><U><big>Design Summary</big></U></B>
Number of registers: 125 out of 1520 (8%)
PFU registers: 103 out of 1280 (8%)
PIO registers: 22 out of 240 (9%)
Number of SLICEs: 148 out of 640 (23%)
SLICEs as Logic/ROM: 148 out of 640 (23%)
SLICEs as RAM: 0 out of 480 (0%)
SLICEs as Carry: 9 out of 640 (1%)
Number of LUT4s: 295 out of 1280 (23%)
Number used as logic LUTs: 277
Number used as distributed RAM: 0
Number used as ripple logic: 18
Number used as shift registers: 0
Number of PIO sites used: 70 + 4(JTAG) out of 80 (93%)
Number of block RAMs: 0 out of 7 (0%)
Number of GSRs: 0 out of 1 (0%)
EFB used : Yes
JTAG used : No
Readback used : No
Oscillator used : No
Startup used : No
POR : On
Bandgap : On
Number of Power Controller: 0 out of 1 (0%)
Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%)
Number of DCCA: 0 out of 8 (0%)
Number of DCMA: 0 out of 2 (0%)
Number of PLLs: 0 out of 1 (0%)
Number of DQSDLLs: 0 out of 2 (0%)
Number of CLKDIVC: 0 out of 4 (0%)
Number of ECLKSYNCA: 0 out of 4 (0%)
Number of ECLKBRIDGECS: 0 out of 2 (0%)
Notes:-
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
distributed RAMs) + 2*(Number of ripple logic)
2. Number of logic LUT4s does not include count of distributed RAM and
ripple logic.
Number of clocks: 2
Net C14M_c: 85 loads, 63 rising, 22 falling (Driver: PIO C14M )
Net PHI1_c: 3 loads, 0 rising, 3 falling (Driver: PIO PHI1 )
Number of Clock Enables: 13
Net N_117_i: 2 loads, 0 LSLICEs
Net RWBank14: 11 loads, 11 LSLICEs
Net ram2e_ufm/wb_adr_0_sqmuxa_1_i: 1 loads, 1 LSLICEs
Net un9_VOE_0_a2_0_a2: 1 loads, 1 LSLICEs
Net un6_DOEEN_0_a2_0_a2: 2 loads, 2 LSLICEs
Net ram2e_ufm/un1_wb_adr_0_sqmuxa_2_i[0]: 8 loads, 8 LSLICEs
Net ram2e_ufm/un1_wb_cyc_stb_0_sqmuxa_1_i[0]: 1 loads, 1 LSLICEs
Net ram2e_ufm/N_111: 1 loads, 1 LSLICEs
Net ram2e_ufm/N_104: 4 loads, 4 LSLICEs
Net ram2e_ufm/N_98: 1 loads, 1 LSLICEs
Net un1_CKE48_0_i: 6 loads, 6 LSLICEs
Net N_389_i: 2 loads, 0 LSLICEs
Net Vout3: 8 loads, 0 LSLICEs
Number of LSRs: 8
Net N_148: 2 loads, 2 LSLICEs
Net N_430_i: 2 loads, 0 LSLICEs
Net RC7: 2 loads, 2 LSLICEs
Net S[2]: 2 loads, 2 LSLICEs
Net ram2e_ufm/wb_rst: 1 loads, 0 LSLICEs
Net ram2e_ufm/nRWE_0_i_o3_RNIP8E61: 1 loads, 1 LSLICEs
Net N_530: 1 loads, 0 LSLICEs
Net N_301_i: 1 loads, 1 LSLICEs
Number of nets driven by tri-state buffers: 0
Top 10 highest fanout non-clock nets:
Net S[2]: 60 loads
Net S[3]: 48 loads
Net S[1]: 46 loads
Net S[0]: 31 loads
Net FS[11]: 24 loads
Net FS[10]: 23 loads
Net FS[12]: 23 loads
Net FS[9]: 23 loads
Net FS[13]: 21 loads
Net FS[8]: 18 loads
Number of warnings: 3
Number of errors: 0
<A name="mrp_dwe"></A><B><U><big>Design Errors/Warnings</big></U></B>
WARNING - map: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf(94): Semantic
error in "IOBUF PORT "nWE80" IO_TYPE=LVCMOS33 PULLMODE=NONE ;": Port
"nWE80" does not exist in the design. This preference has been disabled.
WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
temporarily disable certain features of the device including Power
Controller, GSR, Hardened User SPI Port, Hardened Primary User I2C Port.
Functionality is restored after the Flash Memory (UFM/Configuration)
Interface is disabled using Disable Configuration Interface command 0x26
followed by Bypass command 0xFF.
WARNING - map: IO buffer missing for top level port nWE80...logic will be
discarded.
<A name="mrp_ioa"></A><B><U><big>IO (PIO) Attributes</big></U></B>
+---------------------+-----------+-----------+------------+
| IO Name | Direction | Levelmode | IO |
| | | IO_TYPE | Register |
+---------------------+-----------+-----------+------------+
| RD[0] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| LED | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| C14M | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[7] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[6] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[5] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[4] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[3] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[2] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[1] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| DQMH | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| DQML | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RAout[11] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RAout[10] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RAout[9] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RAout[8] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RAout[7] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[6] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[5] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[4] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[3] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[2] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[1] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[0] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| BA[1] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| BA[0] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nRWEout | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nCASout | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nRASout | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nCSout | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| CKEout | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nVOE | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[7] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[6] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[5] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[4] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[3] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[2] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[1] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[0] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nDOE | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[7] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[6] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[5] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[4] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[3] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[2] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[1] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[0] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[7] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[6] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[5] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[4] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[3] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[2] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[1] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[0] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[7] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[6] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[5] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[4] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[3] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[2] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[1] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[0] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nC07X | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nEN80 | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nWE | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nDHGROE | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| PHI1 | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
<A name="mrp_rm"></A><B><U><big>Removed logic</big></U></B>
Block GSR_INST undriven or does not drive anything - clipped.
Block ram2e_ufm/VCC undriven or does not drive anything - clipped.
Block ram2e_ufm/GND undriven or does not drive anything - clipped.
Signal RC_0_.CN was merged into signal PHI1_c
Signal RDOE_i was merged into signal RDOE
Signal RAT.CN was merged into signal C14M_c
Signal ram2e_ufm/ufmefb/VCC undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/GND undriven or does not drive anything - clipped.
Signal FS_s_0_S1[15] undriven or does not drive anything - clipped.
Signal FS_s_0_COUT[15] undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/CFGWAKE undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/wbc_ufm_irq undriven or does not drive anything -
clipped.
Signal ram2e_ufm/ufmefb/TCOC undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/TCINT undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIIRQO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPICSNEN undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMOSIEN undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMOSIO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMISOEN undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMISOO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPISCKEN undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPISCKO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C2SDAOEN undriven or does not drive anything -
clipped.
Signal ram2e_ufm/ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C2SCLOEN undriven or does not drive anything -
clipped.
Signal ram2e_ufm/ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C1SDAOEN undriven or does not drive anything -
clipped.
Signal ram2e_ufm/ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C1SCLOEN undriven or does not drive anything -
clipped.
Signal ram2e_ufm/ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLADRO4 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLWEO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLL1STBO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLL0STBO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLRSTO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLCLKO undriven or does not drive anything - clipped.
Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped.
Signal N_1 undriven or does not drive anything - clipped.
Block RefReq.CN was optimized away.
Block RDOE_RNIAM8C was optimized away.
Block nCASout.CN was optimized away.
Block ram2e_ufm/ufmefb/VCC was optimized away.
Block ram2e_ufm/ufmefb/GND was optimized away.
<A name="mrp_efb"></A><B><U><big>Embedded Functional Block Connection Summary</big></U></B>
Desired WISHBONE clock frequency: 14.4 MHz
Clock source: C14M_c
Reset source: ram2e_ufm/wb_rst
Functions mode:
I2C #1 (Primary) Function: DISABLED
I2C #2 (Secondary) Function: DISABLED
SPI Function: DISABLED
Timer/Counter Function: DISABLED
Timer/Counter Mode: WB
UFM Connection: ENABLED
PLL0 Connection: DISABLED
PLL1 Connection: DISABLED
I2C Function Summary:
--------------------
None
SPI Function Summary:
--------------------
None
Timer/Counter Function Summary:
------------------------------
None
UFM Function Summary:
--------------------
UFM Utilization: General Purpose Flash Memory
Initialized UFM Pages: 321 Pages (321*128 Bits)
Available General
Purpose Flash Memory: 511 Pages (511*128 Bits)
EBR Blocks with Unique
Initialization Data: 0
WID EBR Instance
--- ------------
<A name="mrp_asic"></A><B><U><big>ASIC Components</big></U></B>
---------------
Instance Name: ram2e_ufm/ufmefb/EFBInst_0
Type: EFB
<A name="mrp_runtime"></A><B><U><big>Run Time and Memory Usage</big></U></B>
-------------------------
Total CPU Time: 0 secs
Total REAL Time: 2 secs
Peak Memory Usage: 64 MB
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights
reserved.
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<HEAD><TITLE>PAD Specification File</TITLE>
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<PRE><A name="Pad"></A>PAD Specification File
***************************
PART TYPE: LCMXO2-1200HC
Performance Grade: 4
PACKAGE: TQFP100
Package Status: Final Version 1.42
Fri Jun 07 20:50:24 2024
Pinout by Port Name:
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties |
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
| Ain[0] | 3/3 | LVCMOS33_IN | PL3A | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[1] | 2/3 | LVCMOS33_IN | PL2D | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[2] | 7/3 | LVCMOS33_IN | PL3C | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[3] | 4/3 | LVCMOS33_IN | PL3B | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[4] | 78/0 | LVCMOS33_IN | PT16C | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[5] | 84/0 | LVCMOS33_IN | PT15A | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[6] | 86/0 | LVCMOS33_IN | PT12C | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[7] | 8/3 | LVCMOS33_IN | PL3D | | | CLAMP:ON HYSTERESIS:SMALL |
| BA[0] | 58/1 | LVCMOS33_OUT | PR9A | | | DRIVE:4mA SLEW:SLOW |
| BA[1] | 60/1 | LVCMOS33_OUT | PR8C | | | DRIVE:4mA SLEW:SLOW |
| C14M | 62/1 | LVCMOS33_IN | PR5D | | | CLAMP:ON HYSTERESIS:SMALL |
| CKEout | 53/1 | LVCMOS33_OUT | PR9D | | | DRIVE:4mA SLEW:SLOW |
| DQMH | 49/2 | LVCMOS33_OUT | PB20D | | | DRIVE:4mA SLEW:SLOW |
| DQML | 48/2 | LVCMOS33_OUT | PB20C | | | DRIVE:4mA SLEW:SLOW |
| Din[0] | 96/0 | LVCMOS33_IN | PT10B | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[1] | 97/0 | LVCMOS33_IN | PT10A | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[2] | 98/0 | LVCMOS33_IN | PT9B | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[3] | 9/3 | LVCMOS33_IN | PL4A | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[4] | 1/3 | LVCMOS33_IN | PL2C | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[5] | 99/0 | LVCMOS33_IN | PT9A | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[6] | 88/0 | LVCMOS33_IN | PT12A | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[7] | 87/0 | LVCMOS33_IN | PT12B | | | CLAMP:ON HYSTERESIS:SMALL |
| Dout[0] | 30/2 | LVCMOS33_OUT | PB6B | | | DRIVE:4mA SLEW:SLOW |
| Dout[1] | 27/2 | LVCMOS33_OUT | PB4C | | | DRIVE:4mA SLEW:SLOW |
| Dout[2] | 25/3 | LVCMOS33_OUT | PL10D | | | DRIVE:4mA SLEW:SLOW |
| Dout[3] | 28/2 | LVCMOS33_OUT | PB4D | | | DRIVE:4mA SLEW:SLOW |
| Dout[4] | 24/3 | LVCMOS33_OUT | PL10C | | | DRIVE:4mA SLEW:SLOW |
| Dout[5] | 21/3 | LVCMOS33_OUT | PL9B | | | DRIVE:4mA SLEW:SLOW |
| Dout[6] | 31/2 | LVCMOS33_OUT | PB6C | | | DRIVE:4mA SLEW:SLOW |
| Dout[7] | 32/2 | LVCMOS33_OUT | PB6D | | | DRIVE:4mA SLEW:SLOW |
| LED | 35/2 | LVCMOS33_OUT | PB9B | | | DRIVE:4mA SLEW:SLOW |
| PHI1 | 85/0 | LVCMOS33_IN | PT12D | | | CLAMP:ON HYSTERESIS:SMALL |
| RAout[0] | 66/1 | LVCMOS33_OUT | PR4D | | | DRIVE:4mA SLEW:SLOW |
| RAout[10] | 64/1 | LVCMOS33_OUT | PR5B | | | DRIVE:4mA SLEW:SLOW |
| RAout[11] | 59/1 | LVCMOS33_OUT | PR8D | | | DRIVE:4mA SLEW:SLOW |
| RAout[1] | 68/1 | LVCMOS33_OUT | PR4B | | | DRIVE:4mA SLEW:SLOW |
| RAout[2] | 70/1 | LVCMOS33_OUT | PR3B | | | DRIVE:4mA SLEW:SLOW |
| RAout[3] | 74/1 | LVCMOS33_OUT | PR2B | | | DRIVE:4mA SLEW:SLOW |
| RAout[4] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA SLEW:SLOW |
| RAout[5] | 71/1 | LVCMOS33_OUT | PR3A | | | DRIVE:4mA SLEW:SLOW |
| RAout[6] | 69/1 | LVCMOS33_OUT | PR4A | | | DRIVE:4mA SLEW:SLOW |
| RAout[7] | 67/1 | LVCMOS33_OUT | PR4C | | | DRIVE:4mA SLEW:SLOW |
| RAout[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA SLEW:SLOW |
| RAout[9] | 63/1 | LVCMOS33_OUT | PR5C | | | DRIVE:4mA SLEW:SLOW |
| RD[0] | 36/2 | LVCMOS33_BIDI | PB11C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[1] | 37/2 | LVCMOS33_BIDI | PB11D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[2] | 38/2 | LVCMOS33_BIDI | PB11A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[3] | 39/2 | LVCMOS33_BIDI | PB11B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[4] | 40/2 | LVCMOS33_BIDI | PB15A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[5] | 41/2 | LVCMOS33_BIDI | PB15B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[6] | 42/2 | LVCMOS33_BIDI | PB18A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[7] | 43/2 | LVCMOS33_BIDI | PB18B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| Vout[0] | 18/3 | LVCMOS33_OUT | PL8C | | | DRIVE:4mA SLEW:SLOW |
| Vout[1] | 15/3 | LVCMOS33_OUT | PL5D | | | DRIVE:4mA SLEW:SLOW |
| Vout[2] | 17/3 | LVCMOS33_OUT | PL8B | | | DRIVE:4mA SLEW:SLOW |
| Vout[3] | 13/3 | LVCMOS33_OUT | PL5B | | | DRIVE:4mA SLEW:SLOW |
| Vout[4] | 19/3 | LVCMOS33_OUT | PL8D | | | DRIVE:4mA SLEW:SLOW |
| Vout[5] | 16/3 | LVCMOS33_OUT | PL8A | | | DRIVE:4mA SLEW:SLOW |
| Vout[6] | 14/3 | LVCMOS33_OUT | PL5C | | | DRIVE:4mA SLEW:SLOW |
| Vout[7] | 12/3 | LVCMOS33_OUT | PL5A | | | DRIVE:4mA SLEW:SLOW |
| nC07X | 34/2 | LVCMOS33_IN | PB9A | | | CLAMP:ON HYSTERESIS:SMALL |
| nCASout | 52/1 | LVCMOS33_OUT | PR10C | | | DRIVE:4mA SLEW:SLOW |
| nCSout | 57/1 | LVCMOS33_OUT | PR9B | | | DRIVE:4mA SLEW:SLOW |
| nDHGROE | 47/2 | LVCMOS33_OUT | PB18D | | | DRIVE:4mA SLEW:SLOW |
| nDOE | 20/3 | LVCMOS33_OUT | PL9A | | | DRIVE:4mA SLEW:SLOW |
| nEN80 | 82/0 | LVCMOS33_IN | PT15C | | | CLAMP:ON HYSTERESIS:SMALL |
| nRASout | 54/1 | LVCMOS33_OUT | PR9C | | | DRIVE:4mA SLEW:SLOW |
| nRWEout | 51/1 | LVCMOS33_OUT | PR10D | | | DRIVE:4mA SLEW:SLOW |
| nVOE | 10/3 | LVCMOS33_OUT | PL4B | | | DRIVE:4mA SLEW:SLOW |
| nWE | 29/2 | LVCMOS33_IN | PB6A | | | CLAMP:ON HYSTERESIS:SMALL |
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
Vccio by Bank:
+------+-------+
| Bank | Vccio |
+------+-------+
| 0 | 3.3V |
| 1 | 3.3V |
| 2 | 3.3V |
| 3 | 3.3V |
+------+-------+
<A name="pad_vref"></A><B><U><big>Vref by Bank:</big></U></B>
+------+-----+-----------------+---------+
| Vref | Pin | Bank # / Vref # | Load(s) |
+------+-----+-----------------+---------+
+------+-----+-----------------+---------+
<A name="pad_pin"></A><B><U><big>Pinout by Pin Number:</big></U></B>
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable |
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
| 1/3 | Din[4] | LOCATED | LVCMOS33_IN | PL2C | L_GPLLT_IN | | |
| 2/3 | Ain[1] | LOCATED | LVCMOS33_IN | PL2D | L_GPLLC_IN | | |
| 3/3 | Ain[0] | LOCATED | LVCMOS33_IN | PL3A | PCLKT3_2 | | |
| 4/3 | Ain[3] | LOCATED | LVCMOS33_IN | PL3B | PCLKC3_2 | | |
| 7/3 | Ain[2] | LOCATED | LVCMOS33_IN | PL3C | | | |
| 8/3 | Ain[7] | LOCATED | LVCMOS33_IN | PL3D | | | |
| 9/3 | Din[3] | LOCATED | LVCMOS33_IN | PL4A | | | |
| 10/3 | nVOE | LOCATED | LVCMOS33_OUT | PL4B | | | |
| 12/3 | Vout[7] | LOCATED | LVCMOS33_OUT | PL5A | PCLKT3_1 | | |
| 13/3 | Vout[3] | LOCATED | LVCMOS33_OUT | PL5B | PCLKC3_1 | | |
| 14/3 | Vout[6] | LOCATED | LVCMOS33_OUT | PL5C | | | |
| 15/3 | Vout[1] | LOCATED | LVCMOS33_OUT | PL5D | | | |
| 16/3 | Vout[5] | LOCATED | LVCMOS33_OUT | PL8A | | | |
| 17/3 | Vout[2] | LOCATED | LVCMOS33_OUT | PL8B | | | |
| 18/3 | Vout[0] | LOCATED | LVCMOS33_OUT | PL8C | | | |
| 19/3 | Vout[4] | LOCATED | LVCMOS33_OUT | PL8D | | | |
| 20/3 | nDOE | LOCATED | LVCMOS33_OUT | PL9A | PCLKT3_0 | | |
| 21/3 | Dout[5] | LOCATED | LVCMOS33_OUT | PL9B | PCLKC3_0 | | |
| 24/3 | Dout[4] | LOCATED | LVCMOS33_OUT | PL10C | | | |
| 25/3 | Dout[2] | LOCATED | LVCMOS33_OUT | PL10D | | | |
| 27/2 | Dout[1] | LOCATED | LVCMOS33_OUT | PB4C | CSSPIN | | |
| 28/2 | Dout[3] | LOCATED | LVCMOS33_OUT | PB4D | | | |
| 29/2 | nWE | LOCATED | LVCMOS33_IN | PB6A | | | |
| 30/2 | Dout[0] | LOCATED | LVCMOS33_OUT | PB6B | | | |
| 31/2 | Dout[6] | LOCATED | LVCMOS33_OUT | PB6C | MCLK/CCLK | | |
| 32/2 | Dout[7] | LOCATED | LVCMOS33_OUT | PB6D | SO/SPISO | | |
| 34/2 | nC07X | LOCATED | LVCMOS33_IN | PB9A | PCLKT2_0 | | |
| 35/2 | LED | LOCATED | LVCMOS33_OUT | PB9B | PCLKC2_0 | | |
| 36/2 | RD[0] | LOCATED | LVCMOS33_BIDI | PB11C | | | |
| 37/2 | RD[1] | LOCATED | LVCMOS33_BIDI | PB11D | | | |
| 38/2 | RD[2] | LOCATED | LVCMOS33_BIDI | PB11A | PCLKT2_1 | | |
| 39/2 | RD[3] | LOCATED | LVCMOS33_BIDI | PB11B | PCLKC2_1 | | |
| 40/2 | RD[4] | LOCATED | LVCMOS33_BIDI | PB15A | | | |
| 41/2 | RD[5] | LOCATED | LVCMOS33_BIDI | PB15B | | | |
| 42/2 | RD[6] | LOCATED | LVCMOS33_BIDI | PB18A | | | |
| 43/2 | RD[7] | LOCATED | LVCMOS33_BIDI | PB18B | | | |
| 45/2 | unused, PULL:DOWN | | | PB18C | | | |
| 47/2 | nDHGROE | LOCATED | LVCMOS33_OUT | PB18D | | | |
| 48/2 | DQML | LOCATED | LVCMOS33_OUT | PB20C | SN | | |
| 49/2 | DQMH | LOCATED | LVCMOS33_OUT | PB20D | SI/SISPI | | |
| 51/1 | nRWEout | LOCATED | LVCMOS33_OUT | PR10D | DQ1 | | |
| 52/1 | nCASout | LOCATED | LVCMOS33_OUT | PR10C | DQ1 | | |
| 53/1 | CKEout | LOCATED | LVCMOS33_OUT | PR9D | DQ1 | | |
| 54/1 | nRASout | LOCATED | LVCMOS33_OUT | PR9C | DQ1 | | |
| 57/1 | nCSout | LOCATED | LVCMOS33_OUT | PR9B | DQ1 | | |
| 58/1 | BA[0] | LOCATED | LVCMOS33_OUT | PR9A | DQ1 | | |
| 59/1 | RAout[11] | LOCATED | LVCMOS33_OUT | PR8D | DQ1 | | |
| 60/1 | BA[1] | LOCATED | LVCMOS33_OUT | PR8C | DQ1 | | |
| 61/1 | unused, PULL:DOWN | | | PR8A | DQS1 | | |
| 62/1 | C14M | LOCATED | LVCMOS33_IN | PR5D | PCLKC1_0/DQ0 | | |
| 63/1 | RAout[9] | LOCATED | LVCMOS33_OUT | PR5C | PCLKT1_0/DQ0 | | |
| 64/1 | RAout[10] | LOCATED | LVCMOS33_OUT | PR5B | DQS0N | | |
| 65/1 | RAout[8] | LOCATED | LVCMOS33_OUT | PR5A | DQS0 | | |
| 66/1 | RAout[0] | LOCATED | LVCMOS33_OUT | PR4D | DQ0 | | |
| 67/1 | RAout[7] | LOCATED | LVCMOS33_OUT | PR4C | DQ0 | | |
| 68/1 | RAout[1] | LOCATED | LVCMOS33_OUT | PR4B | DQ0 | | |
| 69/1 | RAout[6] | LOCATED | LVCMOS33_OUT | PR4A | DQ0 | | |
| 70/1 | RAout[2] | LOCATED | LVCMOS33_OUT | PR3B | DQ0 | | |
| 71/1 | RAout[5] | LOCATED | LVCMOS33_OUT | PR3A | DQ0 | | |
| 74/1 | RAout[3] | LOCATED | LVCMOS33_OUT | PR2B | DQ0 | | |
| 75/1 | RAout[4] | LOCATED | LVCMOS33_OUT | PR2A | DQ0 | | |
| 76/0 | unused, PULL:DOWN | | | PT17D | DONE | | |
| 77/0 | unused, PULL:DOWN | | | PT17C | INITN | | |
| 78/0 | Ain[4] | LOCATED | LVCMOS33_IN | PT16C | | | |
| 81/0 | unused, PULL:DOWN | | | PT15D | PROGRAMN | | |
| 82/0 | nEN80 | LOCATED | LVCMOS33_IN | PT15C | JTAGENB | | |
| 83/0 | unused, PULL:DOWN | | | PT15B | | | |
| 84/0 | Ain[5] | LOCATED | LVCMOS33_IN | PT15A | | | |
| 85/0 | PHI1 | LOCATED | LVCMOS33_IN | PT12D | SDA/PCLKC0_0 | | |
| 86/0 | Ain[6] | LOCATED | LVCMOS33_IN | PT12C | SCL/PCLKT0_0 | | |
| 87/0 | Din[7] | LOCATED | LVCMOS33_IN | PT12B | PCLKC0_1 | | |
| 88/0 | Din[6] | LOCATED | LVCMOS33_IN | PT12A | PCLKT0_1 | | |
| 90/0 | Reserved: sysCONFIG | | | PT11D | TMS | | |
| 91/0 | Reserved: sysCONFIG | | | PT11C | TCK | | |
| 94/0 | Reserved: sysCONFIG | | | PT10D | TDI | | |
| 95/0 | Reserved: sysCONFIG | | | PT10C | TDO | | |
| 96/0 | Din[0] | LOCATED | LVCMOS33_IN | PT10B | | | |
| 97/0 | Din[1] | LOCATED | LVCMOS33_IN | PT10A | | | |
| 98/0 | Din[2] | LOCATED | LVCMOS33_IN | PT9B | | | |
| 99/0 | Din[5] | LOCATED | LVCMOS33_IN | PT9A | | | |
| PB4A/2 | unused, PULL:DOWN | | | PB4A | | | |
| PB4B/2 | unused, PULL:DOWN | | | PB4B | | | |
| PB9C/2 | unused, PULL:DOWN | | | PB9C | | | |
| PB9D/2 | unused, PULL:DOWN | | | PB9D | | | |
| PB15C/2 | unused, PULL:DOWN | | | PB15C | | | |
| PB15D/2 | unused, PULL:DOWN | | | PB15D | | | |
| PB20A/2 | unused, PULL:DOWN | | | PB20A | | | |
| PB20B/2 | unused, PULL:DOWN | | | PB20B | | | |
| PL2A/3 | unused, PULL:DOWN | | | PL2A | L_GPLLT_FB | | |
| PL2B/3 | unused, PULL:DOWN | | | PL2B | L_GPLLC_FB | | |
| PL4C/3 | unused, PULL:DOWN | | | PL4C | | | |
| PL4D/3 | unused, PULL:DOWN | | | PL4D | | | |
| PL10A/3 | unused, PULL:DOWN | | | PL10A | | | |
| PL10B/3 | unused, PULL:DOWN | | | PL10B | | | |
| PR2C/1 | unused, PULL:DOWN | | | PR2C | DQ0 | | |
| PR2D/1 | unused, PULL:DOWN | | | PR2D | DQ0 | | |
| PR8B/1 | unused, PULL:DOWN | | | PR8B | DQS1N | | |
| PR10A/1 | unused, PULL:DOWN | | | PR10A | DQ1 | | |
| PR10B/1 | unused, PULL:DOWN | | | PR10B | DQ1 | | |
| PT9C/0 | unused, PULL:DOWN | | | PT9C | | | |
| PT9D/0 | unused, PULL:DOWN | | | PT9D | | | |
| PT11A/0 | unused, PULL:DOWN | | | PT11A | | | |
| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | |
| PT16A/0 | unused, PULL:DOWN | | | PT16A | | | |
| PT16B/0 | unused, PULL:DOWN | | | PT16B | | | |
| PT16D/0 | unused, PULL:DOWN | | | PT16D | | | |
| PT17A/0 | unused, PULL:DOWN | | | PT17A | | | |
| PT17B/0 | unused, PULL:DOWN | | | PT17B | | | |
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
sysCONFIG Pins:
+----------+--------------------+--------------------+----------+-------------+-------------------+
| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode |
+----------+--------------------+--------------------+----------+-------------+-------------------+
| PT11D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP |
| PT11C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down |
| PT10D | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP |
| PT10C | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP |
+----------+--------------------+--------------------+----------+-------------+-------------------+
Dedicated sysCONFIG Pins:
List of All Pins' Locate Preferences Based on Final Placement After PAR
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste):
LOCATE COMP "Ain[0]" SITE "3";
LOCATE COMP "Ain[1]" SITE "2";
LOCATE COMP "Ain[2]" SITE "7";
LOCATE COMP "Ain[3]" SITE "4";
LOCATE COMP "Ain[4]" SITE "78";
LOCATE COMP "Ain[5]" SITE "84";
LOCATE COMP "Ain[6]" SITE "86";
LOCATE COMP "Ain[7]" SITE "8";
LOCATE COMP "BA[0]" SITE "58";
LOCATE COMP "BA[1]" SITE "60";
LOCATE COMP "C14M" SITE "62";
LOCATE COMP "CKEout" SITE "53";
LOCATE COMP "DQMH" SITE "49";
LOCATE COMP "DQML" SITE "48";
LOCATE COMP "Din[0]" SITE "96";
LOCATE COMP "Din[1]" SITE "97";
LOCATE COMP "Din[2]" SITE "98";
LOCATE COMP "Din[3]" SITE "9";
LOCATE COMP "Din[4]" SITE "1";
LOCATE COMP "Din[5]" SITE "99";
LOCATE COMP "Din[6]" SITE "88";
LOCATE COMP "Din[7]" SITE "87";
LOCATE COMP "Dout[0]" SITE "30";
LOCATE COMP "Dout[1]" SITE "27";
LOCATE COMP "Dout[2]" SITE "25";
LOCATE COMP "Dout[3]" SITE "28";
LOCATE COMP "Dout[4]" SITE "24";
LOCATE COMP "Dout[5]" SITE "21";
LOCATE COMP "Dout[6]" SITE "31";
LOCATE COMP "Dout[7]" SITE "32";
LOCATE COMP "LED" SITE "35";
LOCATE COMP "PHI1" SITE "85";
LOCATE COMP "RAout[0]" SITE "66";
LOCATE COMP "RAout[10]" SITE "64";
LOCATE COMP "RAout[11]" SITE "59";
LOCATE COMP "RAout[1]" SITE "68";
LOCATE COMP "RAout[2]" SITE "70";
LOCATE COMP "RAout[3]" SITE "74";
LOCATE COMP "RAout[4]" SITE "75";
LOCATE COMP "RAout[5]" SITE "71";
LOCATE COMP "RAout[6]" SITE "69";
LOCATE COMP "RAout[7]" SITE "67";
LOCATE COMP "RAout[8]" SITE "65";
LOCATE COMP "RAout[9]" SITE "63";
LOCATE COMP "RD[0]" SITE "36";
LOCATE COMP "RD[1]" SITE "37";
LOCATE COMP "RD[2]" SITE "38";
LOCATE COMP "RD[3]" SITE "39";
LOCATE COMP "RD[4]" SITE "40";
LOCATE COMP "RD[5]" SITE "41";
LOCATE COMP "RD[6]" SITE "42";
LOCATE COMP "RD[7]" SITE "43";
LOCATE COMP "Vout[0]" SITE "18";
LOCATE COMP "Vout[1]" SITE "15";
LOCATE COMP "Vout[2]" SITE "17";
LOCATE COMP "Vout[3]" SITE "13";
LOCATE COMP "Vout[4]" SITE "19";
LOCATE COMP "Vout[5]" SITE "16";
LOCATE COMP "Vout[6]" SITE "14";
LOCATE COMP "Vout[7]" SITE "12";
LOCATE COMP "nC07X" SITE "34";
LOCATE COMP "nCASout" SITE "52";
LOCATE COMP "nCSout" SITE "57";
LOCATE COMP "nDHGROE" SITE "47";
LOCATE COMP "nDOE" SITE "20";
LOCATE COMP "nEN80" SITE "82";
LOCATE COMP "nRASout" SITE "54";
LOCATE COMP "nRWEout" SITE "51";
LOCATE COMP "nVOE" SITE "10";
LOCATE COMP "nWE" SITE "29";
PAR: Place And Route Diamond (64-bit) 3.11.3.469.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Fri Jun 07 20:50:28 2024
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<PRE><A name="Par"></A>PAR: Place And Route Diamond (64-bit) 3.11.3.469.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&amp;T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Fri Jun 07 20:50:15 2024
C:/lscc/diamond/3.11_x64/ispfpga\bin\nt64\par -f RAM2E_LCMXO2_1200HC_impl1.p2t
RAM2E_LCMXO2_1200HC_impl1_map.ncd RAM2E_LCMXO2_1200HC_impl1.dir
RAM2E_LCMXO2_1200HC_impl1.prf -gui
Preference file: RAM2E_LCMXO2_1200HC_impl1.prf.
<A name="par_cts"></A><B><U><big>Cost Table Summary</big></U></B>
Level/ Number Worst Timing Worst Timing Run NCD
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
---------- -------- ----- ------ ----------- ----------- ---- ------
5_1 * 0 54.468 0 0.379 0 16 Completed
* : Design saved.
Total (real) run time for 1-seed: 16 secs
par done!
Note: user must run &apos;Trace&apos; for timing closure signoff.
Lattice Place and Route Report for Design &quot;RAM2E_LCMXO2_1200HC_impl1_map.ncd&quot;
Fri Jun 07 20:50:15 2024
<A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
PAR: Place And Route Diamond (64-bit) 3.11.3.469.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF RAM2E_LCMXO2_1200HC_impl1_map.ncd RAM2E_LCMXO2_1200HC_impl1.dir/5_1.ncd RAM2E_LCMXO2_1200HC_impl1.prf
Preference file: RAM2E_LCMXO2_1200HC_impl1.prf.
Placement level-cost: 5-1.
Routing Iterations: 6
Loading design for application par from file RAM2E_LCMXO2_1200HC_impl1_map.ncd.
Design name: RAM2E
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-1200HC
Package: TQFP100
Performance: 4
Loading device for application par from file &apos;xo2c1200.nph&apos; in environment: C:/lscc/diamond/3.11_x64/ispfpga.
Package Status: Final Version 1.42.
Performance Hardware Data Status: Final Version 34.4.
License checked out.
Ignore Preference Error(s): True
<A name="par_dus"></A><B><U><big>Device utilization summary:</big></U></B>
PIO (prelim) 70+4(JTAG)/108 69% used
70+4(JTAG)/80 93% bonded
IOLOGIC 22/108 20% used
SLICE 148/640 23% used
EFB 1/1 100% used
Number of Signals: 464
Number of Connections: 1330
Pin Constraint Summary:
70 out of 70 pins locked (100% locked).
The following 1 signal is selected to use the primary clock routing resources:
C14M_c (driver: C14M, clk load #: 85)
WARNING - par: Signal &quot;C14M_c&quot; is selected to use Primary clock resources. However, its driver comp &quot;C14M&quot; is located at &quot;62&quot;, which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
The following 1 signal is selected to use the secondary clock routing resources:
RWBank14 (driver: ram2e_ufm/SLICE_82, clk load #: 0, sr load #: 0, ce load #: 11)
No signal is selected as Global Set/Reset.
Starting Placer Phase 0.
........
Finished Placer Phase 0. REAL time: 2 secs
Starting Placer Phase 1.
....................
Placer score = 86293.
Finished Placer Phase 1. REAL time: 9 secs
Starting Placer Phase 2.
.
Placer score = 85792
Finished Placer Phase 2. REAL time: 9 secs
<A name="par_clk"></A><B><U><big>Clock Report</big></U></B>
Global Clock Resources:
CLK_PIN : 0 out of 8 (0%)
General PIO: 1 out of 108 (0%)
PLL : 0 out of 1 (0%)
DCM : 0 out of 2 (0%)
DCC : 0 out of 8 (0%)
Global Clocks:
PRIMARY &quot;C14M_c&quot; from comp &quot;C14M&quot; on PIO site &quot;62 (PR5D)&quot;, clk load = 85
SECONDARY &quot;RWBank14&quot; from F0 on comp &quot;ram2e_ufm/SLICE_82&quot; on site &quot;R7C14A&quot;, clk load = 0, ce load = 11, sr load = 0
PRIMARY : 1 out of 8 (12%)
SECONDARY: 1 out of 8 (12%)
Edge Clocks:
No edge clock selected.
I/O Usage Summary (final):
70 + 4(JTAG) out of 108 (68.5%) PIO sites used.
70 + 4(JTAG) out of 80 (92.5%) bonded PIO sites used.
Number of PIO comps: 70; differential: 0.
Number of Vref pins used: 0.
I/O Bank Usage Summary:
+----------+----------------+------------+-----------+
| I/O Bank | Usage | Bank Vccio | Bank Vref |
+----------+----------------+------------+-----------+
| 0 | 11 / 19 ( 57%) | 3.3V | - |
| 1 | 20 / 21 ( 95%) | 3.3V | - |
| 2 | 19 / 20 ( 95%) | 3.3V | - |
| 3 | 20 / 20 (100%) | 3.3V | - |
+----------+----------------+------------+-----------+
Total placer CPU time: 7 secs
Dumping design to file RAM2E_LCMXO2_1200HC_impl1.dir/5_1.ncd.
0 connections routed; 1330 unrouted.
Starting router resource preassignment
WARNING - par: The driver of primary clock net C14M_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
Signal=PHI1_c loads=5 clock_loads=3
Completed router resource preassignment. Real time: 14 secs
Start NBR router at 20:50:29 06/07/24
*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
in the earlier iterations. In each iteration, it tries to
solve the conflicts while keeping the critical connections
routed as short as possible. The routing process is said to
be completed when no conflicts exist and all connections
are routed.
Note: NBR uses a different method to calculate timing slacks. The
worst slack and total negative slack may not be the same as
that in TRCE report. You should always run TRCE to verify
your design.
*****************************************************************
Start NBR special constraint process at 20:50:29 06/07/24
Start NBR section for initial routing at 20:50:29 06/07/24
Level 4, iteration 1
25(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 54.468ns/0.000ns; real time: 15 secs
Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area at 75% usage is 0 (0.00%)
Start NBR section for normal routing at 20:50:30 06/07/24
Level 4, iteration 1
5(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 54.468ns/0.000ns; real time: 15 secs
Level 4, iteration 2
5(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 54.468ns/0.000ns; real time: 15 secs
Level 4, iteration 3
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 54.468ns/0.000ns; real time: 15 secs
Start NBR section for setup/hold timing optimization with effort level 3 at 20:50:30 06/07/24
Start NBR section for re-routing at 20:50:30 06/07/24
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 54.468ns/0.000ns; real time: 15 secs
Start NBR section for post-routing at 20:50:30 06/07/24
End NBR router with 0 unrouted connection
NBR Summary
-----------
Number of unrouted connections : 0 (0.00%)
Number of connections with timing violations : 0 (0.00%)
Estimated worst slack&lt;setup&gt; : 54.468ns
Timing score&lt;setup&gt; : 0
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
Signal=PHI1_c loads=5 clock_loads=3
Total CPU time 13 secs
Total REAL time: 16 secs
Completely routed.
End of route. 1330 routed (100.00%); 0 unrouted.
Hold time timing score: 0, hold timing errors: 0
Timing score: 0
Dumping design to file RAM2E_LCMXO2_1200HC_impl1.dir/5_1.ncd.
All signals are completely routed.
PAR_SUMMARY::Run status = Completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst slack&lt;setup/&lt;ns&gt;&gt; = 54.468
PAR_SUMMARY::Timing score&lt;setup/&lt;ns&gt;&gt; = 0.000
PAR_SUMMARY::Worst slack&lt;hold /&lt;ns&gt;&gt; = 0.379
PAR_SUMMARY::Timing score&lt;hold /&lt;ns&gt;&gt; = 0.000
PAR_SUMMARY::Number of errors = 0
Total CPU time to completion: 13 secs
Total REAL time to completion: 16 secs
par done!
Note: user must run &apos;Trace&apos; for timing closure signoff.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&amp;T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
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Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
# Written on Fri Jun 7 20:50:07 2024
##### FILES SYNTAX CHECKED ##############################################
Constraint File(s): "\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc"
#Run constraint checker to find more issues with constraints.
#########################################################################
No issues found in constraint syntax.
Clock Summary
*************
Start Requested Requested Clock Clock Clock
Level Clock Frequency Period Type Group Load
-----------------------------------------------------------------------------------------------
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 121
0 - System 100.0 MHz 10.000 system system_clkgroup 0
0 - RAM2E|PHI1 100.0 MHz 10.000 inferred Inferred_clkgroup_0 9
===============================================================================================
Clock Load Summary
******************
Clock Source Clock Pin Non-clock Pin Non-clock Pin
Clock Load Pin Seq Example Seq Example Comb Example
--------------------------------------------------------------------------------------------
C14M 121 C14M(port) RAT.C - un1_C14M.I[0](inv)
System 0 - - - -
RAM2E|PHI1 9 PHI1(port) RefReq.C S[0].D[0] un1_PHI1.I[0](inv)
============================================================================================

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<PRE><TABLE border=1 width=100% cellspacing=0 cellpadding=2><small>
<TR>
<TD align='center' BGCOLOR='#000099' COLSPAN='4'><SPAN style="COLOR: #FFFFFF"><B>RAM2E_LCMXO2_1200HC project summary</B></SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Module Name:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">RAM2E_LCMXO2_1200HC</SPAN></TD>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Synthesis:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">SynplifyPro</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Name:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">impl1</SPAN></TD>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Strategy Name:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">Strategy1</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Last Process:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">JEDEC File</SPAN></TD>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">State:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">Passed</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Target Device:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">LCMXO2-1200HC-4TG100C</SPAN></TD>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Device Family:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">MachXO2</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Device Type:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">LCMXO2-1200HC</SPAN></TD>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Package Type:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">TQFP100</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Performance grade:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">4</SPAN></TD>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Operating conditions:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">COM</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Logic preference file:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">RAM2E-LCMXO2.lpf</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Physical Preference file:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">impl1/RAM2E_LCMXO2_1200HC_impl1.prf</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Product Version:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">3.11.3.469</SPAN></TD>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Patch Version:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000"></SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Updated:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2024/06/07 20:50:35</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Location:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/impl1</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Project File:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC.ldf</SPAN></TD>
</TR>
</small></TABLE>
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<BR>
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<PRE><A name="Syn"></A><B><U><big>Synthesis Report</big></U></B>
#Build: Synplify Pro (R) N-2018.03L-SP1-1, Build 443R, Apr 1 2019
#install: C:\lscc\diamond\3.11_x64\synpbase
#OS: Windows 8 6.2
#Hostname: ZANEMACWIN11
# Fri Jun 7 20:50:04 2024
#Implementation: impl1
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys HDL Compiler, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Verilog Compiler, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v" (library work)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\pmi_def.v" (library work)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v" (library work)
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v" (library work)
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\REFB.v" (library work)
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\DHGR-ON.v" (library work)
Verilog syntax check successful!
Selecting top level module RAM2E
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
Running optimization stage 1 on VHI .......
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
Running optimization stage 1 on VLO .......
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
Running optimization stage 1 on EFB .......
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
Running optimization stage 1 on REFB .......
@W: CL318 :"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\REFB.v":9:14:9:21|*Output wb_dat_o has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output.
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v":1:7:1:15|Synthesizing module RAM2E_UFM in library work.
Running optimization stage 1 on RAM2E_UFM .......
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\DHGR-ON.v":1:7:1:10|Synthesizing module DHGR in library work.
Running optimization stage 1 on DHGR .......
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v":1:7:1:11|Synthesizing module RAM2E in library work.
Running optimization stage 1 on RAM2E .......
Running optimization stage 2 on RAM2E .......
@N: CL159 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v":11:15:11:19|Input nWE80 is unused.
Running optimization stage 2 on DHGR .......
Running optimization stage 2 on RAM2E_UFM .......
Running optimization stage 2 on REFB .......
Running optimization stage 2 on EFB .......
Running optimization stage 2 on VLO .......
Running optimization stage 2 on VHI .......
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Fri Jun 7 20:50:05 2024
###########################################################]
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Fri Jun 7 20:50:05 2024
###########################################################]
For a summary of runtime and memory usage for all design units, please see file:
==========================================================
@L: A:\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_comp.rt.csv
@END
At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Fri Jun 7 20:50:05 2024
###########################################################]
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Database state : \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\|impl1
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Fri Jun 7 20:50:07 2024
###########################################################]
Premap Report
# Fri Jun 7 20:50:07 2024
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Lattice Technology Pre-mapping, Version maplat2018q2p1, Build 055R, Built Apr 3 2019 09:51:54
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
Reading constraint file: \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
@N: MF284 |Setting synthesis effort to medium for the design
@L: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1_scck.rpt
Printing clock summary report in "\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1_scck.rpt" file
@N: MF916 |Option synthesis_strategy=base is enabled.
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB)
@N: MF284 |Setting synthesis effort to medium for the design
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":21:4:21:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
@N: MH105 |UMR3 is only supported for HAPS-80.
@N: MH105 |UMR3 is only supported for HAPS-80.
@N: BN115 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":140:9:140:12|Removing instance dhgr (in view: work.RAM2E(verilog)) of type view:work.DHGR(verilog) because it does not drive other instances.
syn_allowed_resources : blockrams=7 set on top level netlist RAM2E
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
Clock Summary
******************
Start Requested Requested Clock Clock Clock
Level Clock Frequency Period Type Group Load
-----------------------------------------------------------------------------------------------
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 121
0 - System 100.0 MHz 10.000 system system_clkgroup 0
0 - RAM2E|PHI1 100.0 MHz 10.000 inferred Inferred_clkgroup_0 9
===============================================================================================
Clock Load Summary
***********************
Clock Source Clock Pin Non-clock Pin Non-clock Pin
Clock Load Pin Seq Example Seq Example Comb Example
--------------------------------------------------------------------------------------------
C14M 121 C14M(port) RAT.C - un1_C14M.I[0](inv)
System 0 - - - -
RAM2E|PHI1 9 PHI1(port) RefReq.C S[0].D[0] un1_PHI1.I[0](inv)
============================================================================================
@W: MT529 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":20:19:20:24|Found inferred clock RAM2E|PHI1 which controls 9 sequential elements including PHI1r. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed: 0
@S |Clock Optimization Summary
#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
2 non-gated/non-generated clock tree(s) driving 125 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
---------------------------------------------------------------------------------------
@KP:ckid0_0 C14M port 121 PHI1r
@KP:ckid0_1 PHI1 Unconstrained_port 4 RC[2:0]
=======================================================================================
##### END OF CLOCK OPTIMIZATION REPORT ######
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
Finished Pre Mapping Phase.
Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
None
None
Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
Pre-mapping successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Jun 7 20:50:08 2024
###########################################################]
Map & Optimize Report
# Fri Jun 7 20:50:08 2024
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Lattice Technology Mapper, Version maplat2018q2p1, Build 055R, Built Apr 3 2019 09:51:54
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
@N: MF284 |Setting synthesis effort to medium for the design
@N: MF916 |Option synthesis_strategy=base is enabled.
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
@N: MF284 |Setting synthesis effort to medium for the design
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
Available hyper_sources - for debug and ip models
None Found
@N: FX493 |Applying initial value "00000000" on instance RWBank[7:0].
@N: FX493 |Applying initial value "0000" on instance S[3:0].
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)
@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":14:23:14:28|Found counter in view:work.RAM2E(verilog) instance FS[15:0]
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 142MB)
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:01s 6.90ns 281 / 125
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":171:4:171:9|Boundary register BA_1_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":171:4:171:9|Boundary register BA_0_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 158MB peak: 160MB)
Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 122MB peak: 160MB)
Writing Analyst data base \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_m.srm
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 158MB peak: 160MB)
Writing EDIF Netlist and constraint files
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1.edi
N-2018.03L-SP1-1
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 162MB peak: 164MB)
Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 161MB peak: 164MB)
@W: MT246 :"\\mac\icloud\repos\ram2e\cpld\lcmxo2-1200hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@N: MT615 |Found clock C14M with period 69.84ns
@W: MT420 |Found inferred clock RAM2E|PHI1 with period 10.00ns. Please declare a user-defined clock on port PHI1.
##### START OF TIMING REPORT #####[
# Timing Report written on Fri Jun 7 20:50:12 2024
#
Top view: RAM2E
Requested Frequency: 14.3 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s): \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
Performance Summary
*******************
Worst slack in design: 6.897
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
----------------------------------------------------------------------------------------------------------------------
C14M 14.3 MHz 112.1 MHz 69.841 8.918 31.599 declared default_clkgroup
RAM2E|PHI1 100.0 MHz 322.2 MHz 10.000 3.103 6.897 inferred Inferred_clkgroup_0
System 100.0 MHz NA 10.000 NA 67.088 system system_clkgroup
======================================================================================================================
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
----------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
----------------------------------------------------------------------------------------------------------------
System C14M | 69.841 67.088 | No paths - | No paths - | No paths -
C14M System | 69.841 68.797 | No paths - | No paths - | No paths -
C14M C14M | 69.841 60.923 | No paths - | 34.920 31.599 | No paths -
RAM2E|PHI1 C14M | No paths - | No paths - | No paths - | Diff grp -
RAM2E|PHI1 RAM2E|PHI1 | No paths - | 10.000 6.897 | No paths - | No paths -
================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Interface Information
*********************
No IO constraint found
====================================
Detailed Report for Clock: C14M
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------
S[2] C14M FD1S3AX Q S[2] 1.366 31.599
S[3] C14M FD1S3AX Q S[3] 1.345 31.619
S[1] C14M FD1S3AX Q S[1] 1.344 31.800
S[0] C14M FD1S3AX Q S[0] 1.305 31.838
RA[0] C14M FD1P3AX Q RA[0] 1.108 33.707
RA[3] C14M FD1P3AX Q RA[3] 1.108 33.707
RA[1] C14M FD1P3AX Q RA[1] 1.044 33.771
RA[2] C14M FD1P3AX Q RA[2] 1.044 33.771
RA[4] C14M FD1P3AX Q RA[4] 1.044 33.771
RA[5] C14M FD1P3AX Q RA[5] 1.044 33.771
===========================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
-----------------------------------------------------------------------------------
VOE_i_0io C14M OFS1P3IX CD N_530 34.118 31.599
VOE_i_0io C14M OFS1P3IX D VOE_ic_i 35.009 31.800
Vout_0io[0] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[1] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[2] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[3] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[4] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[5] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[6] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[7] C14M OFS1P3DX SP Vout3 34.449 32.634
===================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 34.920
- Setup time: 0.803
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 34.118
- Propagation time: 2.519
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : 31.599
Number of logic level(s): 1
Starting point: S[2] / Q
Ending point: VOE_i_0io / CD
The start point is clocked by C14M [rising] on pin CK
The end point is clocked by C14M [falling] on pin SCLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
------------------------------------------------------------------------------------------------------------
S[2] FD1S3AX Q Out 1.366 1.366 -
S[2] Net - - - - 58
ram2e_ufm.un1_wb_adr_0_sqmuxa_2_0_a2_0[0] ORCALUT4 A In 0.000 1.366 -
ram2e_ufm.un1_wb_adr_0_sqmuxa_2_0_a2_0[0] ORCALUT4 Z Out 1.153 2.519 -
N_530 Net - - - - 3
VOE_i_0io OFS1P3IX CD In 0.000 2.519 -
============================================================================================================
====================================
Detailed Report for Clock: RAM2E|PHI1
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------
RC[1] RAM2E|PHI1 FD1S3IX Q RC[1] 1.148 6.897
RC[2] RAM2E|PHI1 FD1S3IX Q RC[2] 1.108 6.937
RC[0] RAM2E|PHI1 FD1S3IX Q RC[0] 1.148 8.179
===========================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------
RC[0] RAM2E|PHI1 FD1S3IX CD RC7 9.197 6.897
RC[1] RAM2E|PHI1 FD1S3IX CD RC7 9.197 6.897
RC[2] RAM2E|PHI1 FD1S3IX CD RC7 9.197 6.897
RC[0] RAM2E|PHI1 FD1S3IX D RC_i[0] 9.894 8.179
RC[1] RAM2E|PHI1 FD1S3IX D RC_RNO[1] 10.089 8.324
RC[2] RAM2E|PHI1 FD1S3IX D RC_RNO[2] 10.089 8.324
RefReq RAM2E|PHI1 FD1S3AX D RefReq_2 10.089 8.324
================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 10.000
- Setup time: 0.803
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 9.197
- Propagation time: 2.301
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : 6.897
Number of logic level(s): 1
Starting point: RC[1] / Q
Ending point: RC[0] / CD
The start point is clocked by RAM2E|PHI1 [falling] on pin CK
The end point is clocked by RAM2E|PHI1 [falling] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------
RC[1] FD1S3IX Q Out 1.148 1.148 -
RC[1] Net - - - - 4
RC7 ORCALUT4 A In 0.000 1.148 -
RC7 ORCALUT4 Z Out 1.153 2.301 -
RC7 Net - - - - 3
RC[0] FD1S3IX CD In 0.000 2.301 -
=================================================================================
====================================
Detailed Report for Clock: System
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------------------------------
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBACKO wb_ack 0.000 67.088
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO0 wb_dato[0] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO2 wb_dato[2] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO3 wb_dato[3] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO4 wb_dato[4] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO5 wb_dato[5] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO6 wb_dato[6] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO7 wb_dato[7] 0.000 69.313
===================================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
----------------------------------------------------------------------------------------
ram2e_ufm.RWMask[0] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[1] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[2] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[3] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[4] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[5] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[6] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[7] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.LEDEN System FD1P3AX SP N_98 69.369 67.736
ram2e_ufm.wb_cyc_stb System FD1P3AX SP N_111 69.369 67.736
========================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 69.841
- Setup time: 0.472
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 69.369
- Propagation time: 2.282
- Clock delay at starting point: 0.000 (ideal)
- Estimated clock delay at start point: -0.000
= Slack (non-critical) : 67.088
Number of logic level(s): 2
Starting point: ram2e_ufm.ufmefb.EFBInst_0 / WBACKO
Ending point: ram2e_ufm.RWMask[0] / SP
The start point is clocked by System [rising]
The end point is clocked by C14M [rising] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
----------------------------------------------------------------------------------------------------------------
ram2e_ufm.ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 -
wb_ack Net - - - - 5
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] ORCALUT4 B In 0.000 0.000 -
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] ORCALUT4 Z Out 1.017 1.017 -
un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] Net - - - - 1
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 D In 0.000 1.017 -
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 Z Out 1.265 2.282 -
N_104 Net - - - - 8
ram2e_ufm.RWMask[0] FD1P3AX SP In 0.000 2.282 -
================================================================================================================
##### END OF TIMING REPORT #####]
Timing exceptions that could not be applied
None
Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 161MB peak: 164MB)
Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 161MB peak: 164MB)
---------------------------------------
Resource Usage Report
Part: lcmxo2_1200hc-4
Register bits: 125 of 1280 (10%)
PIC Latch: 0
I/O cells: 70
Details:
BB: 8
CCU2D: 9
EFB: 1
FD1P3AX: 58
FD1P3IX: 1
FD1S3AX: 31
FD1S3AY: 4
FD1S3IX: 9
GSR: 1
IB: 21
IFS1P3DX: 1
INV: 4
OB: 41
OFS1P3BX: 6
OFS1P3DX: 12
OFS1P3IX: 3
ORCALUT4: 275
PUR: 1
VHI: 3
VLO: 3
Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 33MB peak: 164MB)
Process took 0h:00m:03s realtime, 0h:00m:02s cputime
# Fri Jun 7 20:50:12 2024
###########################################################]
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<?xml version="1.0" encoding="UTF-8"?>
<userSetting name="//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml" version="Diamond (64-bit) 3.11.3.469" date="Sat Jun 08 04:44:51 2024" vendor="Lattice Semiconductor Corporation" >
</userSetting>

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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE Report>
<ReportView version="2.0">
<Implement name="impl1">
<ToolReport id="tooldec" path="" status="0"/>
<ToolReport id="toolhle_genhierarchy" path="" status="0"/>
<ToolReport id="toolpio" path="" status="0"/>
<ToolReport id="toolsso" path="" status="0"/>
</Implement>
</ReportView>

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CPLD/LCMXO2-640HC-NODHGR/.setting.ini Normal file
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[General]
Export.auto_tasks=Jedecgen
PAR.auto_tasks=@@empty()

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CPLD/LCMXO2-640HC-NODHGR/RAM2E_LCMXO2_640HC.ldf Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<BaliProject version="3.2" title="RAM2E_LCMXO2_640HC" device="LCMXO2-640HC-4TG100C" default_implementation="impl1">
<Options/>
<Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
<Options def_top="RAM2E" top="RAM2E"/>
<Source name="../RAM2E.v" type="Verilog" type_short="Verilog">
<Options top_module="RAM2E"/>
</Source>
<Source name="../UFM-LCMXO2.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="REFB.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../DHGR-OFF.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="impl1/impl1.xcf" type="Programming Project File" type_short="Programming">
<Options/>
</Source>
<Source name="../RAM2E-LCMXO2.lpf" type="Logic Preference" type_short="LPF">
<Options/>
</Source>
<Source name="../RAM2E.sdc" type="Synplify Design Constraints File" type_short="SDC">
<Options/>
</Source>
</Implementation>
<Strategy name="Strategy1" file="RAM2E_LCMXO2_640HC1.sty"/>
</BaliProject>

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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE strategy>
<Strategy version="1.0" predefined="0" description="" label="Strategy1">
<Property name="PROP_BD_CmdLineArgs" value="" time="0"/>
<Property name="PROP_BD_EdfHardtimer" value="Enable" time="0"/>
<Property name="PROP_BD_EdfInBusNameConv" value="None" time="0"/>
<Property name="PROP_BD_EdfInLibPath" value="" time="0"/>
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<Property name="PROP_BD_EdfMemPath" value="" time="0"/>
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<Property name="PROP_BIT_EnIntOscBitGen" value="Disable" time="0"/>
<Property name="PROP_BIT_ExtClockBitGen" value="False" time="0"/>
<Property name="PROP_BIT_GSREnableBitGen" value="True" time="0"/>
<Property name="PROP_BIT_GSRRelOnBitGen" value="DoneIn" time="0"/>
<Property name="PROP_BIT_GranTimBitGen" value="0" time="0"/>
<Property name="PROP_BIT_IOTriRelBitGen" value="Cycle 2" time="0"/>
<Property name="PROP_BIT_JTAGEnableBitGen" value="False" time="0"/>
<Property name="PROP_BIT_LenBitsBitGen" value="24" time="0"/>
<Property name="PROP_BIT_MIFFileBitGen" value="" time="0"/>
<Property name="PROP_BIT_NoHeader" value="False" time="0"/>
<Property name="PROP_BIT_OutFormatBitGen" value="Bit File (Binary)" time="0"/>
<Property name="PROP_BIT_OutFormatBitGen_REF" value="" time="0"/>
<Property name="PROP_BIT_OutFormatPromGen" value="Intel Hex 32-bit" time="0"/>
<Property name="PROP_BIT_ParityCheckBitGen" value="True" time="0"/>
<Property name="PROP_BIT_ReadBackBitGen" value="Flash" time="0"/>
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<Property name="PROP_BIT_RemZeroFramesBitGen" value="False" time="0"/>
<Property name="PROP_BIT_RunDRCBitGen" value="True" time="0"/>
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<Property name="PROP_BIT_StartUpClkBitGen" value="Cclk" time="0"/>
<Property name="PROP_BIT_SynchIOBitGen" value="True" time="0"/>
<Property name="PROP_BIT_SysClockConBitGen" value="Reset" time="0"/>
<Property name="PROP_BIT_SysConBitGen" value="Reset" time="0"/>
<Property name="PROP_BIT_WaitStTimBitGen" value="5" time="0"/>
<Property name="PROP_IOTIMING_AllSpeed" value="False" time="0"/>
<Property name="PROP_LST_AllowDUPMod" value="False" time="0"/>
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<Property name="PROP_LST_CarryChainLength" value="0" time="0"/>
<Property name="PROP_LST_CmdLineArgs" value="" time="0"/>
<Property name="PROP_LST_DSPStyle" value="DSP" time="0"/>
<Property name="PROP_LST_DSPUtil" value="100" time="0"/>
<Property name="PROP_LST_DecodeUnreachableStates" value="False" time="0"/>
<Property name="PROP_LST_DisableDistRam" value="False" time="0"/>
<Property name="PROP_LST_EBRUtil" value="100" time="0"/>
<Property name="PROP_LST_EdfFrequency" value="200" time="0"/>
<Property name="PROP_LST_EdfHardtimer" value="Enable" time="0"/>
<Property name="PROP_LST_EdfInLibPath" value="" time="0"/>
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<Property name="PROP_LST_EdfMemPath" value="" time="0"/>
<Property name="PROP_LST_FIXGATEDCLKS" value="True" time="0"/>
<Property name="PROP_LST_FSMEncodeStyle" value="Auto" time="0"/>
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<Property name="PROP_LST_IOInsertion" value="True" time="0"/>
<Property name="PROP_LST_InterFileDump" value="False" time="0"/>
<Property name="PROP_LST_LoopLimit" value="1950" time="0"/>
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<Property name="PROP_LST_ResolvedMixedDrivers" value="False" time="0"/>
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<Property name="PROP_LST_UseIOReg" value="Auto" time="0"/>
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<Property name="PROP_MAP_SigCrossRef" value="False" time="0"/>
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<Property name="PROP_MAP_TimingDriven" value="False" time="0"/>
<Property name="PROP_MAP_TimingDrivenNodeRep" value="False" time="0"/>
<Property name="PROP_MAP_TimingDrivenPack" value="False" time="0"/>
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<Property name="PROP_PARSTA_FullName" value="False" time="0"/>
<Property name="PROP_PARSTA_NumUnconstrainedPaths" value="0" time="0"/>
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<Property name="PROP_PARSTA_SpeedForSetupAnalysis" value="default" time="0"/>
<Property name="PROP_PARSTA_WordCasePaths" value="10" time="0"/>
<Property name="PROP_PAR_CrDlyStFileParDes" value="False" time="0"/>
<Property name="PROP_PAR_DisableTDParDes" value="False" time="0"/>
<Property name="PROP_PAR_EffortParDes" value="5" time="0"/>
<Property name="PROP_PAR_MultiSeedSortMode" value="Worst Slack" time="0"/>
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<Property name="PROP_PAR_PARClockSkew" value="Off" time="0"/>
<Property name="PROP_PAR_PARModArgs" value="" time="0"/>
<Property name="PROP_PAR_ParMultiNodeList" value="" time="0"/>
<Property name="PROP_PAR_ParRunPlaceOnly" value="False" time="0"/>
<Property name="PROP_PAR_PlcIterParDes" value="1" time="0"/>
<Property name="PROP_PAR_PlcStCostTblParDes" value="1" time="0"/>
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<Property name="PROP_PRE_VSynComArea" value="True" time="0"/>
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<Property name="PROP_PRE_VSynFreq" value="200" time="0"/>
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<Property name="PROP_PRE_VSynIOPad" value="False" time="0"/>
<Property name="PROP_PRE_VSynOutNetForm" value="None" time="0"/>
<Property name="PROP_PRE_VSynOutPref" value="True" time="0"/>
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<Property name="PROP_PRE_VSynRetime" value="True" time="0"/>
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<Property name="PROP_PRE_VSynTransform" value="True" time="0"/>
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<Property name="PROP_PRE_VSynoutd" value="0" time="0"/>
<Property name="PROP_SYN_ClockConversion" value="True" time="0"/>
<Property name="PROP_SYN_CmdLineArgs" value="" time="0"/>
<Property name="PROP_SYN_EdfAllowDUPMod" value="False" time="0"/>
<Property name="PROP_SYN_EdfArea" value="False" time="0"/>
<Property name="PROP_SYN_EdfArrangeVHDLFiles" value="True" time="0"/>
<Property name="PROP_SYN_EdfDefEnumEncode" value="Default" time="0"/>
<Property name="PROP_SYN_EdfFanout" value="1000" time="0"/>
<Property name="PROP_SYN_EdfFrequency" value="100" time="0"/>
<Property name="PROP_SYN_EdfGSR" value="False" time="0"/>
<Property name="PROP_SYN_EdfInsertIO" value="False" time="0"/>
<Property name="PROP_SYN_EdfNumCritPath" value="" time="0"/>
<Property name="PROP_SYN_EdfNumStartEnd" value="" time="0"/>
<Property name="PROP_SYN_EdfOutNetForm" value="None" time="0"/>
<Property name="PROP_SYN_EdfPushTirstates" value="True" time="0"/>
<Property name="PROP_SYN_EdfResSharing" value="True" time="0"/>
<Property name="PROP_SYN_EdfRunRetiming" value="Pipelining Only" time="0"/>
<Property name="PROP_SYN_EdfSymFSM" value="True" time="0"/>
<Property name="PROP_SYN_EdfUnconsClk" value="False" time="0"/>
<Property name="PROP_SYN_EdfVerilogInput" value="Verilog 2001" time="0"/>
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<Property name="PROP_TIM_ModPreSimDes" value="" time="0"/>
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<Property name="PROP_TIM_TimSimGenX" value="False" time="0"/>
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8
CPLD/LCMXO2-640HC-NODHGR/REFB.ipx Normal file
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@ -0,0 +1,8 @@
<?xml version="1.0" encoding="UTF-8"?>
<DiamondModule name="REFB" module="EFB" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2023 09 20 04:17:25.073" version="1.2" type="Module" synthesis="synplify" source_format="Verilog">
<Package>
<File name="REFB.lpc" type="lpc" modified="2023 09 20 04:17:14.513"/>
<File name="REFB.v" type="top_level_verilog" modified="2023 09 20 04:17:14.586"/>
<File name="REFB_tmpl.v" type="template_verilog" modified="2023 09 20 04:17:14.586"/>
</Package>
</DiamondModule>

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CPLD/LCMXO2-640HC-NODHGR/REFB.v Normal file
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/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 */
/* Module Version: 1.2 */
/* C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 14.4 -ufm -ufm_ebr 190 -mem_size 1 -memfile ../RAM2E-LCMXO2.mem -memformat hex -wb -dev 640 */
/* Wed Sep 20 04:17:14 2023 */
`timescale 1 ns / 1 ps
module REFB (wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i,
wb_dat_i, wb_dat_o, wb_ack_o, wbc_ufm_irq)/* synthesis NGD_DRC_MASK=1 */;
input wire wb_clk_i;
input wire wb_rst_i;
input wire wb_cyc_i;
input wire wb_stb_i;
input wire wb_we_i;
input wire [7:0] wb_adr_i;
input wire [7:0] wb_dat_i;
output wire [7:0] wb_dat_o;
output wire wb_ack_o;
output wire wbc_ufm_irq;
wire scuba_vhi;
wire scuba_vlo;
VHI scuba_vhi_inst (.Z(scuba_vhi));
VLO scuba_vlo_inst (.Z(scuba_vlo));
defparam EFBInst_0.UFM_INIT_FILE_FORMAT = "HEX" ;
defparam EFBInst_0.UFM_INIT_FILE_NAME = "../RAM2E-LCMXO2.mem" ;
defparam EFBInst_0.UFM_INIT_ALL_ZEROS = "DISABLED" ;
defparam EFBInst_0.UFM_INIT_START_PAGE = 190 ;
defparam EFBInst_0.UFM_INIT_PAGES = 1 ;
defparam EFBInst_0.DEV_DENSITY = "640L" ;
defparam EFBInst_0.EFB_UFM = "ENABLED" ;
defparam EFBInst_0.TC_ICAPTURE = "DISABLED" ;
defparam EFBInst_0.TC_OVERFLOW = "DISABLED" ;
defparam EFBInst_0.TC_ICR_INT = "OFF" ;
defparam EFBInst_0.TC_OCR_INT = "OFF" ;
defparam EFBInst_0.TC_OV_INT = "OFF" ;
defparam EFBInst_0.TC_TOP_SEL = "OFF" ;
defparam EFBInst_0.TC_RESETN = "ENABLED" ;
defparam EFBInst_0.TC_OC_MODE = "TOGGLE" ;
defparam EFBInst_0.TC_OCR_SET = 32767 ;
defparam EFBInst_0.TC_TOP_SET = 65535 ;
defparam EFBInst_0.GSR = "ENABLED" ;
defparam EFBInst_0.TC_CCLK_SEL = 1 ;
defparam EFBInst_0.TC_MODE = "CTCM" ;
defparam EFBInst_0.TC_SCLK_SEL = "PCLOCK" ;
defparam EFBInst_0.EFB_TC_PORTMODE = "WB" ;
defparam EFBInst_0.EFB_TC = "DISABLED" ;
defparam EFBInst_0.SPI_WAKEUP = "DISABLED" ;
defparam EFBInst_0.SPI_INTR_RXOVR = "DISABLED" ;
defparam EFBInst_0.SPI_INTR_TXOVR = "DISABLED" ;
defparam EFBInst_0.SPI_INTR_RXRDY = "DISABLED" ;
defparam EFBInst_0.SPI_INTR_TXRDY = "DISABLED" ;
defparam EFBInst_0.SPI_SLAVE_HANDSHAKE = "DISABLED" ;
defparam EFBInst_0.SPI_PHASE_ADJ = "DISABLED" ;
defparam EFBInst_0.SPI_CLK_INV = "DISABLED" ;
defparam EFBInst_0.SPI_LSB_FIRST = "DISABLED" ;
defparam EFBInst_0.SPI_CLK_DIVIDER = 1 ;
defparam EFBInst_0.SPI_MODE = "MASTER" ;
defparam EFBInst_0.EFB_SPI = "DISABLED" ;
defparam EFBInst_0.I2C2_WAKEUP = "DISABLED" ;
defparam EFBInst_0.I2C2_GEN_CALL = "DISABLED" ;
defparam EFBInst_0.I2C2_CLK_DIVIDER = 1 ;
defparam EFBInst_0.I2C2_BUS_PERF = "100kHz" ;
defparam EFBInst_0.I2C2_SLAVE_ADDR = "0b1000010" ;
defparam EFBInst_0.I2C2_ADDRESSING = "7BIT" ;
defparam EFBInst_0.EFB_I2C2 = "DISABLED" ;
defparam EFBInst_0.I2C1_WAKEUP = "DISABLED" ;
defparam EFBInst_0.I2C1_GEN_CALL = "DISABLED" ;
defparam EFBInst_0.I2C1_CLK_DIVIDER = 1 ;
defparam EFBInst_0.I2C1_BUS_PERF = "100kHz" ;
defparam EFBInst_0.I2C1_SLAVE_ADDR = "0b1000001" ;
defparam EFBInst_0.I2C1_ADDRESSING = "7BIT" ;
defparam EFBInst_0.EFB_I2C1 = "DISABLED" ;
defparam EFBInst_0.EFB_WB_CLK_FREQ = "14.4" ;
EFB EFBInst_0 (.WBCLKI(wb_clk_i), .WBRSTI(wb_rst_i), .WBCYCI(wb_cyc_i),
.WBSTBI(wb_stb_i), .WBWEI(wb_we_i), .WBADRI7(wb_adr_i[7]), .WBADRI6(wb_adr_i[6]),
.WBADRI5(wb_adr_i[5]), .WBADRI4(wb_adr_i[4]), .WBADRI3(wb_adr_i[3]),
.WBADRI2(wb_adr_i[2]), .WBADRI1(wb_adr_i[1]), .WBADRI0(wb_adr_i[0]),
.WBDATI7(wb_dat_i[7]), .WBDATI6(wb_dat_i[6]), .WBDATI5(wb_dat_i[5]),
.WBDATI4(wb_dat_i[4]), .WBDATI3(wb_dat_i[3]), .WBDATI2(wb_dat_i[2]),
.WBDATI1(wb_dat_i[1]), .WBDATI0(wb_dat_i[0]), .PLL0DATI7(scuba_vlo),
.PLL0DATI6(scuba_vlo), .PLL0DATI5(scuba_vlo), .PLL0DATI4(scuba_vlo),
.PLL0DATI3(scuba_vlo), .PLL0DATI2(scuba_vlo), .PLL0DATI1(scuba_vlo),
.PLL0DATI0(scuba_vlo), .PLL0ACKI(scuba_vlo), .PLL1DATI7(scuba_vlo),
.PLL1DATI6(scuba_vlo), .PLL1DATI5(scuba_vlo), .PLL1DATI4(scuba_vlo),
.PLL1DATI3(scuba_vlo), .PLL1DATI2(scuba_vlo), .PLL1DATI1(scuba_vlo),
.PLL1DATI0(scuba_vlo), .PLL1ACKI(scuba_vlo), .I2C1SCLI(scuba_vlo),
.I2C1SDAI(scuba_vlo), .I2C2SCLI(scuba_vlo), .I2C2SDAI(scuba_vlo),
.SPISCKI(scuba_vlo), .SPIMISOI(scuba_vlo), .SPIMOSII(scuba_vlo),
.SPISCSN(scuba_vlo), .TCCLKI(scuba_vlo), .TCRSTN(scuba_vlo), .TCIC(scuba_vlo),
.UFMSN(scuba_vhi), .WBDATO7(wb_dat_o[7]), .WBDATO6(wb_dat_o[6]),
.WBDATO5(wb_dat_o[5]), .WBDATO4(wb_dat_o[4]), .WBDATO3(wb_dat_o[3]),
.WBDATO2(wb_dat_o[2]), .WBDATO1(wb_dat_o[1]), .WBDATO0(wb_dat_o[0]),
.WBACKO(wb_ack_o), .PLLCLKO(), .PLLRSTO(), .PLL0STBO(), .PLL1STBO(),
.PLLWEO(), .PLLADRO4(), .PLLADRO3(), .PLLADRO2(), .PLLADRO1(), .PLLADRO0(),
.PLLDATO7(), .PLLDATO6(), .PLLDATO5(), .PLLDATO4(), .PLLDATO3(),
.PLLDATO2(), .PLLDATO1(), .PLLDATO0(), .I2C1SCLO(), .I2C1SCLOEN(),
.I2C1SDAO(), .I2C1SDAOEN(), .I2C2SCLO(), .I2C2SCLOEN(), .I2C2SDAO(),
.I2C2SDAOEN(), .I2C1IRQO(), .I2C2IRQO(), .SPISCKO(), .SPISCKEN(),
.SPIMISOO(), .SPIMISOEN(), .SPIMOSIO(), .SPIMOSIEN(), .SPIMCSN7(),
.SPIMCSN6(), .SPIMCSN5(), .SPIMCSN4(), .SPIMCSN3(), .SPIMCSN2(),
.SPIMCSN1(), .SPIMCSN0(), .SPICSNEN(), .SPIIRQO(), .TCINT(), .TCOC(),
.WBCUFMIRQ(wbc_ufm_irq), .CFGWAKE(), .CFGSTDBY());
// exemplar begin
// exemplar end
endmodule

78
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NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
NOTE All Rights Reserved *
NOTE DATE CREATED: Fri Jun 07 20:50:20 2024 *
NOTE DESIGN NAME: RAM2E *
NOTE DEVICE NAME: LCMXO2-640HC-4TQFP100 *
NOTE PIN ASSIGNMENTS *
NOTE PINS RD[0] : 36 : inout *
NOTE PINS LED : 35 : out *
NOTE PINS C14M : 62 : in *
NOTE PINS RD[7] : 43 : inout *
NOTE PINS RD[6] : 42 : inout *
NOTE PINS RD[5] : 41 : inout *
NOTE PINS RD[4] : 40 : inout *
NOTE PINS RD[3] : 39 : inout *
NOTE PINS RD[2] : 38 : inout *
NOTE PINS RD[1] : 37 : inout *
NOTE PINS DQMH : 49 : out *
NOTE PINS DQML : 48 : out *
NOTE PINS RAout[11] : 59 : out *
NOTE PINS RAout[10] : 64 : out *
NOTE PINS RAout[9] : 63 : out *
NOTE PINS RAout[8] : 65 : out *
NOTE PINS RAout[7] : 67 : out *
NOTE PINS RAout[6] : 69 : out *
NOTE PINS RAout[5] : 71 : out *
NOTE PINS RAout[4] : 75 : out *
NOTE PINS RAout[3] : 74 : out *
NOTE PINS RAout[2] : 70 : out *
NOTE PINS RAout[1] : 68 : out *
NOTE PINS RAout[0] : 66 : out *
NOTE PINS BA[1] : 60 : out *
NOTE PINS BA[0] : 58 : out *
NOTE PINS nRWEout : 51 : out *
NOTE PINS nCASout : 52 : out *
NOTE PINS nRASout : 54 : out *
NOTE PINS nCSout : 57 : out *
NOTE PINS CKEout : 53 : out *
NOTE PINS nVOE : 10 : out *
NOTE PINS Vout[7] : 12 : out *
NOTE PINS Vout[6] : 14 : out *
NOTE PINS Vout[5] : 16 : out *
NOTE PINS Vout[4] : 19 : out *
NOTE PINS Vout[3] : 13 : out *
NOTE PINS Vout[2] : 17 : out *
NOTE PINS Vout[1] : 15 : out *
NOTE PINS Vout[0] : 18 : out *
NOTE PINS nDOE : 20 : out *
NOTE PINS Dout[7] : 32 : out *
NOTE PINS Dout[6] : 31 : out *
NOTE PINS Dout[5] : 21 : out *
NOTE PINS Dout[4] : 24 : out *
NOTE PINS Dout[3] : 28 : out *
NOTE PINS Dout[2] : 25 : out *
NOTE PINS Dout[1] : 27 : out *
NOTE PINS Dout[0] : 30 : out *
NOTE PINS Din[7] : 87 : in *
NOTE PINS Din[6] : 88 : in *
NOTE PINS Din[5] : 99 : in *
NOTE PINS Din[4] : 1 : in *
NOTE PINS Din[3] : 9 : in *
NOTE PINS Din[2] : 98 : in *
NOTE PINS Din[1] : 97 : in *
NOTE PINS Din[0] : 96 : in *
NOTE PINS Ain[7] : 8 : in *
NOTE PINS Ain[6] : 86 : in *
NOTE PINS Ain[5] : 84 : in *
NOTE PINS Ain[4] : 78 : in *
NOTE PINS Ain[3] : 4 : in *
NOTE PINS Ain[2] : 7 : in *
NOTE PINS Ain[1] : 2 : in *
NOTE PINS Ain[0] : 3 : in *
NOTE PINS nC07X : 34 : in *
NOTE PINS nEN80 : 82 : in *
NOTE PINS nWE : 29 : in *
NOTE PINS nDHGROE : 47 : out *
NOTE PINS PHI1 : 85 : in *
NOTE CONFIGURATION MODE: NONE *
NOTE COMPRESSION: on *

59
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----------------------------------------------------------------------
Report for cell RAM2E.verilog
Register bits: 125 of 640 (20%)
PIC Latch: 0
I/O cells: 70
Cell usage:
cell count Res Usage(%)
BB 8 100.0
CCU2D 9 100.0
EFB 1 100.0
FD1P3AX 58 100.0
FD1P3IX 1 100.0
FD1S3AX 31 100.0
FD1S3AY 4 100.0
FD1S3IX 9 100.0
GSR 1 100.0
IB 21 100.0
IFS1P3DX 1 100.0
INV 4 100.0
OB 41 100.0
OFS1P3BX 6 100.0
OFS1P3DX 12 100.0
OFS1P3IX 3 100.0
ORCALUT4 275 100.0
PUR 1 100.0
VHI 3 100.0
VLO 3 100.0
SUB MODULES
RAM2E_UFM 1 100.0
REFB 1 100.0
TOTAL 494
----------------------------------------------------------------------
Report for cell RAM2E_UFM.netlist
Instance path: ram2e_ufm
Cell usage:
cell count Res Usage(%)
EFB 1 100.0
FD1P3AX 29 50.0
FD1P3IX 1 100.0
FD1S3IX 1 11.1
ORCALUT4 268 97.5
VHI 2 66.7
VLO 2 66.7
SUB MODULES
REFB 1 100.0
TOTAL 305
----------------------------------------------------------------------
Report for cell REFB.netlist
Instance path: ram2e_ufm.ufmefb
Cell usage:
cell count Res Usage(%)
EFB 1 100.0
VHI 1 33.3
VLO 1 33.3
TOTAL 3

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BITGEN: Bitstream Generator Diamond (64-bit) 3.11.3.469
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Fri Jun 07 20:50:16 2024
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC-NODHGR -w -jedec -gui RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf
Loading design for application Bitgen from file RAM2E_LCMXO2_640HC_impl1.ncd.
Design name: RAM2E
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-640HC
Package: TQFP100
Performance: 4
Loading device for application Bitgen from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.11_x64/ispfpga.
Package Status: Final Version 1.39.
Performance Hardware Data Status: Final Version 34.4.
Running DRC.
DRC detected 0 errors and 0 warnings.
Reading Preference File from RAM2E_LCMXO2_640HC_impl1.prf.
Preference Summary:
+---------------------------------+---------------------------------+
| Preference | Current Setting |
+---------------------------------+---------------------------------+
| RamCfg | Reset** |
+---------------------------------+---------------------------------+
| MCCLK_FREQ | 2.08** |
+---------------------------------+---------------------------------+
| CONFIG_SECURE | OFF** |
+---------------------------------+---------------------------------+
| INBUF | ON** |
+---------------------------------+---------------------------------+
| JTAG_PORT | ENABLE** |
+---------------------------------+---------------------------------+
| SDM_PORT | DISABLE** |
+---------------------------------+---------------------------------+
| SLAVE_SPI_PORT | DISABLE** |
+---------------------------------+---------------------------------+
| MASTER_SPI_PORT | DISABLE** |
+---------------------------------+---------------------------------+
| I2C_PORT | DISABLE** |
+---------------------------------+---------------------------------+
| MUX_CONFIGURATION_PORTS | DISABLE** |
+---------------------------------+---------------------------------+
| CONFIGURATION | CFG** |
+---------------------------------+---------------------------------+
| COMPRESS_CONFIG | ON** |
+---------------------------------+---------------------------------+
| MY_ASSP | OFF** |
+---------------------------------+---------------------------------+
| ONE_TIME_PROGRAM | OFF** |
+---------------------------------+---------------------------------+
| ENABLE_TRANSFR | DISABLE** |
+---------------------------------+---------------------------------+
| SHAREDEBRINIT | DISABLE** |
+---------------------------------+---------------------------------+
| BACKGROUND_RECONFIG | OFF** |
+---------------------------------+---------------------------------+
* Default setting.
** The specified setting matches the default setting.
Creating bit map...
Bitstream Status: Final Version 1.95.
Saving bit stream in "RAM2E_LCMXO2_640HC_impl1.jed".
===========
UFM Summary.
===========
UFM Size: 191 Pages (128*191 Bits).
UFM Utilization: General Purpose Flash Memory.
Available General Purpose Flash Memory: 191 Pages (Page 0 to Page 190).
Initialized UFM Pages: 1 Page (Page 190).
Total CPU Time: 3 secs
Total REAL Time: 4 secs
Peak Memory Usage: 267 MB

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File diff suppressed because it is too large Load Diff

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File diff suppressed because it is too large Load Diff

468
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Lattice Mapping Report File for Design Module 'RAM2E'
Design Information
------------------
Command line: map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial
RAM2E_LCMXO2_640HC_impl1.ngd -o RAM2E_LCMXO2_640HC_impl1_map.ncd -pr
RAM2E_LCMXO2_640HC_impl1.prf -mp RAM2E_LCMXO2_640HC_impl1.mrp -lpf //Mac/iC
loud/Repos/RAM2E/CPLD/LCMXO2-640HC-NODHGR/impl1/RAM2E_LCMXO2_640HC_impl1_sy
nplify.lpf -lpf //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf -c 0 -gui
Target Vendor: LATTICE
Target Device: LCMXO2-640HCTQFP100
Target Performance: 4
Mapper: xo2c00, version: Diamond (64-bit) 3.11.3.469
Mapped on: 06/07/24 20:49:58
Design Summary
--------------
Number of registers: 125 out of 877 (14%)
PFU registers: 103 out of 640 (16%)
PIO registers: 22 out of 237 (9%)
Number of SLICEs: 148 out of 320 (46%)
SLICEs as Logic/ROM: 148 out of 320 (46%)
SLICEs as RAM: 0 out of 240 (0%)
SLICEs as Carry: 9 out of 320 (3%)
Number of LUT4s: 296 out of 640 (46%)
Number used as logic LUTs: 278
Number used as distributed RAM: 0
Number used as ripple logic: 18
Number used as shift registers: 0
Number of PIO sites used: 70 + 4(JTAG) out of 79 (94%)
Number of block RAMs: 0 out of 2 (0%)
Number of GSRs: 0 out of 1 (0%)
EFB used : Yes
JTAG used : No
Readback used : No
Oscillator used : No
Startup used : No
POR : On
Bandgap : On
Number of Power Controller: 0 out of 1 (0%)
Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
Number of DCCA: 0 out of 8 (0%)
Number of DCMA: 0 out of 2 (0%)
Notes:-
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
distributed RAMs) + 2*(Number of ripple logic)
2. Number of logic LUT4s does not include count of distributed RAM and
ripple logic.
Number of clocks: 2
Net C14M_c: 85 loads, 63 rising, 22 falling (Driver: PIO C14M )
Net PHI1_c: 3 loads, 0 rising, 3 falling (Driver: PIO PHI1 )
Number of Clock Enables: 13
Net N_117_i: 2 loads, 0 LSLICEs
Net RWBank14: 11 loads, 11 LSLICEs
Net ram2e_ufm/wb_adr_0_sqmuxa_1_i: 1 loads, 1 LSLICEs
Net un9_VOE_0_a2_0_a2: 1 loads, 1 LSLICEs
Net un6_DOEEN_0_a2_0_a2: 2 loads, 2 LSLICEs
Net ram2e_ufm/un1_wb_adr_0_sqmuxa_2_i[0]: 8 loads, 8 LSLICEs
Page 1
Design: RAM2E Date: 06/07/24 20:49:58
Design Summary (cont)
---------------------
Net ram2e_ufm/un1_wb_cyc_stb_0_sqmuxa_1_i[0]: 1 loads, 1 LSLICEs
Net ram2e_ufm/N_111: 1 loads, 1 LSLICEs
Net ram2e_ufm/N_104: 4 loads, 4 LSLICEs
Net ram2e_ufm/N_98: 1 loads, 1 LSLICEs
Net un1_CKE48_0_i: 6 loads, 6 LSLICEs
Net N_389_i: 2 loads, 0 LSLICEs
Net Vout3: 8 loads, 0 LSLICEs
Number of LSRs: 8
Net N_148: 2 loads, 2 LSLICEs
Net N_430_i: 2 loads, 0 LSLICEs
Net RC7: 2 loads, 2 LSLICEs
Net S[2]: 2 loads, 2 LSLICEs
Net ram2e_ufm/wb_rst: 1 loads, 0 LSLICEs
Net ram2e_ufm/nRWE_0_i_o3_RNIP8E61: 1 loads, 1 LSLICEs
Net N_530: 1 loads, 0 LSLICEs
Net N_301_i: 1 loads, 1 LSLICEs
Number of nets driven by tri-state buffers: 0
Top 10 highest fanout non-clock nets:
Net S[2]: 60 loads
Net S[3]: 48 loads
Net S[1]: 46 loads
Net S[0]: 31 loads
Net FS[11]: 24 loads
Net FS[10]: 23 loads
Net FS[12]: 23 loads
Net FS[9]: 23 loads
Net FS[13]: 21 loads
Net FS[8]: 18 loads
Number of warnings: 3
Number of errors: 0
Design Errors/Warnings
----------------------
WARNING - map: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf(94): Semantic
error in "IOBUF PORT "nWE80" IO_TYPE=LVCMOS33 PULLMODE=NONE ;": Port
"nWE80" does not exist in the design. This preference has been disabled.
WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
temporarily disable certain features of the device including Power
Controller, GSR, Hardened User SPI Port, Hardened Primary User I2C Port.
Functionality is restored after the Flash Memory (UFM/Configuration)
Interface is disabled using Disable Configuration Interface command 0x26
followed by Bypass command 0xFF.
WARNING - map: IO buffer missing for top level port nWE80...logic will be
discarded.
IO (PIO) Attributes
-------------------
+---------------------+-----------+-----------+------------+
| IO Name | Direction | Levelmode | IO |
Page 2
Design: RAM2E Date: 06/07/24 20:49:58
IO (PIO) Attributes (cont)
--------------------------
| | | IO_TYPE | Register |
+---------------------+-----------+-----------+------------+
| RD[0] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| LED | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| C14M | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[7] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[6] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[5] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[4] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[3] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[2] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[1] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| DQMH | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| DQML | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RAout[11] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RAout[10] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RAout[9] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RAout[8] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RAout[7] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[6] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[5] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[4] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[3] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[2] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[1] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[0] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| BA[1] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| BA[0] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nRWEout | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
Page 3
Design: RAM2E Date: 06/07/24 20:49:58
IO (PIO) Attributes (cont)
--------------------------
| nCASout | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nRASout | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nCSout | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| CKEout | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nVOE | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[7] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[6] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[5] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[4] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[3] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[2] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[1] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[0] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nDOE | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[7] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[6] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[5] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[4] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[3] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[2] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[1] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[0] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[7] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[6] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[5] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[4] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[3] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[2] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
Page 4
Design: RAM2E Date: 06/07/24 20:49:58
IO (PIO) Attributes (cont)
--------------------------
| Din[1] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[0] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[7] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[6] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[5] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[4] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[3] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[2] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[1] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[0] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nC07X | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nEN80 | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nWE | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nDHGROE | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| PHI1 | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
Removed logic
-------------
Block GSR_INST undriven or does not drive anything - clipped.
Block ram2e_ufm/VCC undriven or does not drive anything - clipped.
Block ram2e_ufm/GND undriven or does not drive anything - clipped.
Signal RC_0_.CN was merged into signal PHI1_c
Signal RDOE_i was merged into signal RDOE
Signal RAT.CN was merged into signal C14M_c
Signal ram2e_ufm/ufmefb/VCC undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/GND undriven or does not drive anything - clipped.
Signal FS_s_0_S1[15] undriven or does not drive anything - clipped.
Signal FS_s_0_COUT[15] undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/CFGWAKE undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/wbc_ufm_irq undriven or does not drive anything -
clipped.
Signal ram2e_ufm/ufmefb/TCOC undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/TCINT undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIIRQO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPICSNEN undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
Page 5
Design: RAM2E Date: 06/07/24 20:49:58
Removed logic (cont)
--------------------
Signal ram2e_ufm/ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMOSIEN undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMOSIO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMISOEN undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMISOO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPISCKEN undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPISCKO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C2SDAOEN undriven or does not drive anything -
clipped.
Signal ram2e_ufm/ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C2SCLOEN undriven or does not drive anything -
clipped.
Signal ram2e_ufm/ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C1SDAOEN undriven or does not drive anything -
clipped.
Signal ram2e_ufm/ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C1SCLOEN undriven or does not drive anything -
clipped.
Signal ram2e_ufm/ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLADRO4 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLWEO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLL1STBO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLL0STBO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLRSTO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLCLKO undriven or does not drive anything - clipped.
Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped.
Signal N_1 undriven or does not drive anything - clipped.
Block RefReq.CN was optimized away.
Block RDOE_RNIAM8C was optimized away.
Block nCASout.CN was optimized away.
Block ram2e_ufm/ufmefb/VCC was optimized away.
Block ram2e_ufm/ufmefb/GND was optimized away.
Page 6
Design: RAM2E Date: 06/07/24 20:49:58
Embedded Functional Block Connection Summary
--------------------------------------------
Desired WISHBONE clock frequency: 14.4 MHz
Clock source: C14M_c
Reset source: ram2e_ufm/wb_rst
Functions mode:
I2C #1 (Primary) Function: DISABLED
I2C #2 (Secondary) Function: DISABLED
SPI Function: DISABLED
Timer/Counter Function: DISABLED
Timer/Counter Mode: WB
UFM Connection: ENABLED
PLL0 Connection: DISABLED
PLL1 Connection: DISABLED
I2C Function Summary:
--------------------
None
SPI Function Summary:
--------------------
None
Timer/Counter Function Summary:
------------------------------
None
UFM Function Summary:
--------------------
UFM Utilization: General Purpose Flash Memory
Initialized UFM Pages: 1 Pages (1*128 Bits)
Available General
Purpose Flash Memory: 191 Pages (191*128 Bits)
EBR Blocks with Unique
Initialization Data: 0
WID EBR Instance
--- ------------
ASIC Components
---------------
Instance Name: ram2e_ufm/ufmefb/EFBInst_0
Type: EFB
Run Time and Memory Usage
-------------------------
Total CPU Time: 0 secs
Total REAL Time: 0 secs
Peak Memory Usage: 59 MB
Page 7
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights
reserved.

287
CPLD/LCMXO2-640HC-NODHGR/impl1/RAM2E_LCMXO2_640HC_impl1.pad Normal file
View File

@ -0,0 +1,287 @@
PAD Specification File
***************************
PART TYPE: LCMXO2-640HC
Performance Grade: 4
PACKAGE: TQFP100
Package Status: Final Version 1.39
Fri Jun 07 20:50:08 2024
Pinout by Port Name:
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties |
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
| Ain[0] | 3/3 | LVCMOS33_IN | PL2C | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[1] | 2/3 | LVCMOS33_IN | PL2B | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[2] | 7/3 | LVCMOS33_IN | PL3A | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[3] | 4/3 | LVCMOS33_IN | PL2D | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[4] | 78/0 | LVCMOS33_IN | PT11A | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[5] | 84/0 | LVCMOS33_IN | PT10A | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[6] | 86/0 | LVCMOS33_IN | PT9C | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[7] | 8/3 | LVCMOS33_IN | PL3B | | | CLAMP:ON HYSTERESIS:SMALL |
| BA[0] | 58/1 | LVCMOS33_OUT | PR6C | | | DRIVE:4mA SLEW:SLOW |
| BA[1] | 60/1 | LVCMOS33_OUT | PR6A | | | DRIVE:4mA SLEW:SLOW |
| C14M | 62/1 | LVCMOS33_IN | PR5D | | | CLAMP:ON HYSTERESIS:SMALL |
| CKEout | 53/1 | LVCMOS33_OUT | PR7B | | | DRIVE:4mA SLEW:SLOW |
| DQMH | 49/2 | LVCMOS33_OUT | PB14D | | | DRIVE:4mA SLEW:SLOW |
| DQML | 48/2 | LVCMOS33_OUT | PB14C | | | DRIVE:4mA SLEW:SLOW |
| Din[0] | 96/0 | LVCMOS33_IN | PT6D | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[1] | 97/0 | LVCMOS33_IN | PT6C | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[2] | 98/0 | LVCMOS33_IN | PT6B | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[3] | 9/3 | LVCMOS33_IN | PL3C | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[4] | 1/3 | LVCMOS33_IN | PL2A | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[5] | 99/0 | LVCMOS33_IN | PT6A | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[6] | 88/0 | LVCMOS33_IN | PT9A | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[7] | 87/0 | LVCMOS33_IN | PT9B | | | CLAMP:ON HYSTERESIS:SMALL |
| Dout[0] | 30/2 | LVCMOS33_OUT | PB4D | | | DRIVE:4mA SLEW:SLOW |
| Dout[1] | 27/2 | LVCMOS33_OUT | PB4A | | | DRIVE:4mA SLEW:SLOW |
| Dout[2] | 25/3 | LVCMOS33_OUT | PL7D | | | DRIVE:4mA SLEW:SLOW |
| Dout[3] | 28/2 | LVCMOS33_OUT | PB4B | | | DRIVE:4mA SLEW:SLOW |
| Dout[4] | 24/3 | LVCMOS33_OUT | PL7C | | | DRIVE:4mA SLEW:SLOW |
| Dout[5] | 21/3 | LVCMOS33_OUT | PL7B | | | DRIVE:4mA SLEW:SLOW |
| Dout[6] | 31/2 | LVCMOS33_OUT | PB6A | | | DRIVE:4mA SLEW:SLOW |
| Dout[7] | 32/2 | LVCMOS33_OUT | PB6B | | | DRIVE:4mA SLEW:SLOW |
| LED | 35/2 | LVCMOS33_OUT | PB6D | | | DRIVE:4mA SLEW:SLOW |
| PHI1 | 85/0 | LVCMOS33_IN | PT9D | | | CLAMP:ON HYSTERESIS:SMALL |
| RAout[0] | 66/1 | LVCMOS33_OUT | PR3D | | | DRIVE:4mA SLEW:SLOW |
| RAout[10] | 64/1 | LVCMOS33_OUT | PR5B | | | DRIVE:4mA SLEW:SLOW |
| RAout[11] | 59/1 | LVCMOS33_OUT | PR6B | | | DRIVE:4mA SLEW:SLOW |
| RAout[1] | 68/1 | LVCMOS33_OUT | PR3B | | | DRIVE:4mA SLEW:SLOW |
| RAout[2] | 70/1 | LVCMOS33_OUT | PR2D | | | DRIVE:4mA SLEW:SLOW |
| RAout[3] | 74/1 | LVCMOS33_OUT | PR2B | | | DRIVE:4mA SLEW:SLOW |
| RAout[4] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA SLEW:SLOW |
| RAout[5] | 71/1 | LVCMOS33_OUT | PR2C | | | DRIVE:4mA SLEW:SLOW |
| RAout[6] | 69/1 | LVCMOS33_OUT | PR3A | | | DRIVE:4mA SLEW:SLOW |
| RAout[7] | 67/1 | LVCMOS33_OUT | PR3C | | | DRIVE:4mA SLEW:SLOW |
| RAout[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA SLEW:SLOW |
| RAout[9] | 63/1 | LVCMOS33_OUT | PR5C | | | DRIVE:4mA SLEW:SLOW |
| RD[0] | 36/2 | LVCMOS33_BIDI | PB10A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[1] | 37/2 | LVCMOS33_BIDI | PB10B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[2] | 38/2 | LVCMOS33_BIDI | PB10C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[3] | 39/2 | LVCMOS33_BIDI | PB10D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[4] | 40/2 | LVCMOS33_BIDI | PB12A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[5] | 41/2 | LVCMOS33_BIDI | PB12B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[6] | 42/2 | LVCMOS33_BIDI | PB12C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[7] | 43/2 | LVCMOS33_BIDI | PB12D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| Vout[0] | 18/3 | LVCMOS33_OUT | PL6C | | | DRIVE:4mA SLEW:SLOW |
| Vout[1] | 15/3 | LVCMOS33_OUT | PL5D | | | DRIVE:4mA SLEW:SLOW |
| Vout[2] | 17/3 | LVCMOS33_OUT | PL6B | | | DRIVE:4mA SLEW:SLOW |
| Vout[3] | 13/3 | LVCMOS33_OUT | PL5B | | | DRIVE:4mA SLEW:SLOW |
| Vout[4] | 19/3 | LVCMOS33_OUT | PL6D | | | DRIVE:4mA SLEW:SLOW |
| Vout[5] | 16/3 | LVCMOS33_OUT | PL6A | | | DRIVE:4mA SLEW:SLOW |
| Vout[6] | 14/3 | LVCMOS33_OUT | PL5C | | | DRIVE:4mA SLEW:SLOW |
| Vout[7] | 12/3 | LVCMOS33_OUT | PL5A | | | DRIVE:4mA SLEW:SLOW |
| nC07X | 34/2 | LVCMOS33_IN | PB6C | | | CLAMP:ON HYSTERESIS:SMALL |
| nCASout | 52/1 | LVCMOS33_OUT | PR7C | | | DRIVE:4mA SLEW:SLOW |
| nCSout | 57/1 | LVCMOS33_OUT | PR6D | | | DRIVE:4mA SLEW:SLOW |
| nDHGROE | 47/2 | LVCMOS33_OUT | PB14B | | | DRIVE:4mA SLEW:SLOW |
| nDOE | 20/3 | LVCMOS33_OUT | PL7A | | | DRIVE:4mA SLEW:SLOW |
| nEN80 | 82/0 | LVCMOS33_IN | PT10C | | | CLAMP:ON HYSTERESIS:SMALL |
| nRASout | 54/1 | LVCMOS33_OUT | PR7A | | | DRIVE:4mA SLEW:SLOW |
| nRWEout | 51/1 | LVCMOS33_OUT | PR7D | | | DRIVE:4mA SLEW:SLOW |
| nVOE | 10/3 | LVCMOS33_OUT | PL3D | | | DRIVE:4mA SLEW:SLOW |
| nWE | 29/2 | LVCMOS33_IN | PB4C | | | CLAMP:ON HYSTERESIS:SMALL |
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
Vccio by Bank:
+------+-------+
| Bank | Vccio |
+------+-------+
| 0 | 3.3V |
| 1 | 3.3V |
| 2 | 3.3V |
| 3 | 3.3V |
+------+-------+
Vref by Bank:
+------+-----+-----------------+---------+
| Vref | Pin | Bank # / Vref # | Load(s) |
+------+-----+-----------------+---------+
+------+-----+-----------------+---------+
Pinout by Pin Number:
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable |
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
| 1/3 | Din[4] | LOCATED | LVCMOS33_IN | PL2A | | | |
| 2/3 | Ain[1] | LOCATED | LVCMOS33_IN | PL2B | | | |
| 3/3 | Ain[0] | LOCATED | LVCMOS33_IN | PL2C | PCLKT3_2 | | |
| 4/3 | Ain[3] | LOCATED | LVCMOS33_IN | PL2D | PCLKC3_2 | | |
| 7/3 | Ain[2] | LOCATED | LVCMOS33_IN | PL3A | | | |
| 8/3 | Ain[7] | LOCATED | LVCMOS33_IN | PL3B | | | |
| 9/3 | Din[3] | LOCATED | LVCMOS33_IN | PL3C | | | |
| 10/3 | nVOE | LOCATED | LVCMOS33_OUT | PL3D | | | |
| 12/3 | Vout[7] | LOCATED | LVCMOS33_OUT | PL5A | PCLKT3_1 | | |
| 13/3 | Vout[3] | LOCATED | LVCMOS33_OUT | PL5B | PCLKC3_1 | | |
| 14/3 | Vout[6] | LOCATED | LVCMOS33_OUT | PL5C | | | |
| 15/3 | Vout[1] | LOCATED | LVCMOS33_OUT | PL5D | | | |
| 16/3 | Vout[5] | LOCATED | LVCMOS33_OUT | PL6A | | | |
| 17/3 | Vout[2] | LOCATED | LVCMOS33_OUT | PL6B | | | |
| 18/3 | Vout[0] | LOCATED | LVCMOS33_OUT | PL6C | | | |
| 19/3 | Vout[4] | LOCATED | LVCMOS33_OUT | PL6D | | | |
| 20/3 | nDOE | LOCATED | LVCMOS33_OUT | PL7A | PCLKT3_0 | | |
| 21/3 | Dout[5] | LOCATED | LVCMOS33_OUT | PL7B | PCLKC3_0 | | |
| 24/3 | Dout[4] | LOCATED | LVCMOS33_OUT | PL7C | | | |
| 25/3 | Dout[2] | LOCATED | LVCMOS33_OUT | PL7D | | | |
| 27/2 | Dout[1] | LOCATED | LVCMOS33_OUT | PB4A | CSSPIN | | |
| 28/2 | Dout[3] | LOCATED | LVCMOS33_OUT | PB4B | | | |
| 29/2 | nWE | LOCATED | LVCMOS33_IN | PB4C | | | |
| 30/2 | Dout[0] | LOCATED | LVCMOS33_OUT | PB4D | | | |
| 31/2 | Dout[6] | LOCATED | LVCMOS33_OUT | PB6A | MCLK/CCLK | | |
| 32/2 | Dout[7] | LOCATED | LVCMOS33_OUT | PB6B | SO/SPISO | | |
| 34/2 | nC07X | LOCATED | LVCMOS33_IN | PB6C | PCLKT2_0 | | |
| 35/2 | LED | LOCATED | LVCMOS33_OUT | PB6D | PCLKC2_0 | | |
| 36/2 | RD[0] | LOCATED | LVCMOS33_BIDI | PB10A | | | |
| 37/2 | RD[1] | LOCATED | LVCMOS33_BIDI | PB10B | | | |
| 38/2 | RD[2] | LOCATED | LVCMOS33_BIDI | PB10C | PCLKT2_1 | | |
| 39/2 | RD[3] | LOCATED | LVCMOS33_BIDI | PB10D | PCLKC2_1 | | |
| 40/2 | RD[4] | LOCATED | LVCMOS33_BIDI | PB12A | | | |
| 41/2 | RD[5] | LOCATED | LVCMOS33_BIDI | PB12B | | | |
| 42/2 | RD[6] | LOCATED | LVCMOS33_BIDI | PB12C | | | |
| 43/2 | RD[7] | LOCATED | LVCMOS33_BIDI | PB12D | | | |
| 45/2 | unused, PULL:DOWN | | | PB14A | | | |
| 47/2 | nDHGROE | LOCATED | LVCMOS33_OUT | PB14B | | | |
| 48/2 | DQML | LOCATED | LVCMOS33_OUT | PB14C | SN | | |
| 49/2 | DQMH | LOCATED | LVCMOS33_OUT | PB14D | SI/SISPI | | |
| 51/1 | nRWEout | LOCATED | LVCMOS33_OUT | PR7D | | | |
| 52/1 | nCASout | LOCATED | LVCMOS33_OUT | PR7C | | | |
| 53/1 | CKEout | LOCATED | LVCMOS33_OUT | PR7B | | | |
| 54/1 | nRASout | LOCATED | LVCMOS33_OUT | PR7A | | | |
| 57/1 | nCSout | LOCATED | LVCMOS33_OUT | PR6D | | | |
| 58/1 | BA[0] | LOCATED | LVCMOS33_OUT | PR6C | | | |
| 59/1 | RAout[11] | LOCATED | LVCMOS33_OUT | PR6B | | | |
| 60/1 | BA[1] | LOCATED | LVCMOS33_OUT | PR6A | | | |
| 62/1 | C14M | LOCATED | LVCMOS33_IN | PR5D | PCLKC1_0 | | |
| 63/1 | RAout[9] | LOCATED | LVCMOS33_OUT | PR5C | PCLKT1_0 | | |
| 64/1 | RAout[10] | LOCATED | LVCMOS33_OUT | PR5B | | | |
| 65/1 | RAout[8] | LOCATED | LVCMOS33_OUT | PR5A | | | |
| 66/1 | RAout[0] | LOCATED | LVCMOS33_OUT | PR3D | | | |
| 67/1 | RAout[7] | LOCATED | LVCMOS33_OUT | PR3C | | | |
| 68/1 | RAout[1] | LOCATED | LVCMOS33_OUT | PR3B | | | |
| 69/1 | RAout[6] | LOCATED | LVCMOS33_OUT | PR3A | | | |
| 70/1 | RAout[2] | LOCATED | LVCMOS33_OUT | PR2D | | | |
| 71/1 | RAout[5] | LOCATED | LVCMOS33_OUT | PR2C | | | |
| 74/1 | RAout[3] | LOCATED | LVCMOS33_OUT | PR2B | | | |
| 75/1 | RAout[4] | LOCATED | LVCMOS33_OUT | PR2A | | | |
| 76/0 | unused, PULL:DOWN | | | PT11D | DONE | | |
| 77/0 | unused, PULL:DOWN | | | PT11C | INITN | | |
| 78/0 | Ain[4] | LOCATED | LVCMOS33_IN | PT11A | | | |
| 81/0 | unused, PULL:DOWN | | | PT10D | PROGRAMN | | |
| 82/0 | nEN80 | LOCATED | LVCMOS33_IN | PT10C | JTAGENB | | |
| 83/0 | unused, PULL:DOWN | | | PT10B | | | |
| 84/0 | Ain[5] | LOCATED | LVCMOS33_IN | PT10A | | | |
| 85/0 | PHI1 | LOCATED | LVCMOS33_IN | PT9D | SDA/PCLKC0_0 | | |
| 86/0 | Ain[6] | LOCATED | LVCMOS33_IN | PT9C | SCL/PCLKT0_0 | | |
| 87/0 | Din[7] | LOCATED | LVCMOS33_IN | PT9B | PCLKC0_1 | | |
| 88/0 | Din[6] | LOCATED | LVCMOS33_IN | PT9A | PCLKT0_1 | | |
| 90/0 | Reserved: sysCONFIG | | | PT7D | TMS | | |
| 91/0 | Reserved: sysCONFIG | | | PT7C | TCK | | |
| 94/0 | Reserved: sysCONFIG | | | PT7B | TDI | | |
| 95/0 | Reserved: sysCONFIG | | | PT7A | TDO | | |
| 96/0 | Din[0] | LOCATED | LVCMOS33_IN | PT6D | | | |
| 97/0 | Din[1] | LOCATED | LVCMOS33_IN | PT6C | | | |
| 98/0 | Din[2] | LOCATED | LVCMOS33_IN | PT6B | | | |
| 99/0 | Din[5] | LOCATED | LVCMOS33_IN | PT6A | | | |
| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | |
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
sysCONFIG Pins:
+----------+--------------------+--------------------+----------+-------------+-------------------+
| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode |
+----------+--------------------+--------------------+----------+-------------+-------------------+
| PT7D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP |
| PT7C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down |
| PT7B | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP |
| PT7A | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP |
+----------+--------------------+--------------------+----------+-------------+-------------------+
Dedicated sysCONFIG Pins:
List of All Pins' Locate Preferences Based on Final Placement After PAR
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste):
LOCATE COMP "Ain[0]" SITE "3";
LOCATE COMP "Ain[1]" SITE "2";
LOCATE COMP "Ain[2]" SITE "7";
LOCATE COMP "Ain[3]" SITE "4";
LOCATE COMP "Ain[4]" SITE "78";
LOCATE COMP "Ain[5]" SITE "84";
LOCATE COMP "Ain[6]" SITE "86";
LOCATE COMP "Ain[7]" SITE "8";
LOCATE COMP "BA[0]" SITE "58";
LOCATE COMP "BA[1]" SITE "60";
LOCATE COMP "C14M" SITE "62";
LOCATE COMP "CKEout" SITE "53";
LOCATE COMP "DQMH" SITE "49";
LOCATE COMP "DQML" SITE "48";
LOCATE COMP "Din[0]" SITE "96";
LOCATE COMP "Din[1]" SITE "97";
LOCATE COMP "Din[2]" SITE "98";
LOCATE COMP "Din[3]" SITE "9";
LOCATE COMP "Din[4]" SITE "1";
LOCATE COMP "Din[5]" SITE "99";
LOCATE COMP "Din[6]" SITE "88";
LOCATE COMP "Din[7]" SITE "87";
LOCATE COMP "Dout[0]" SITE "30";
LOCATE COMP "Dout[1]" SITE "27";
LOCATE COMP "Dout[2]" SITE "25";
LOCATE COMP "Dout[3]" SITE "28";
LOCATE COMP "Dout[4]" SITE "24";
LOCATE COMP "Dout[5]" SITE "21";
LOCATE COMP "Dout[6]" SITE "31";
LOCATE COMP "Dout[7]" SITE "32";
LOCATE COMP "LED" SITE "35";
LOCATE COMP "PHI1" SITE "85";
LOCATE COMP "RAout[0]" SITE "66";
LOCATE COMP "RAout[10]" SITE "64";
LOCATE COMP "RAout[11]" SITE "59";
LOCATE COMP "RAout[1]" SITE "68";
LOCATE COMP "RAout[2]" SITE "70";
LOCATE COMP "RAout[3]" SITE "74";
LOCATE COMP "RAout[4]" SITE "75";
LOCATE COMP "RAout[5]" SITE "71";
LOCATE COMP "RAout[6]" SITE "69";
LOCATE COMP "RAout[7]" SITE "67";
LOCATE COMP "RAout[8]" SITE "65";
LOCATE COMP "RAout[9]" SITE "63";
LOCATE COMP "RD[0]" SITE "36";
LOCATE COMP "RD[1]" SITE "37";
LOCATE COMP "RD[2]" SITE "38";
LOCATE COMP "RD[3]" SITE "39";
LOCATE COMP "RD[4]" SITE "40";
LOCATE COMP "RD[5]" SITE "41";
LOCATE COMP "RD[6]" SITE "42";
LOCATE COMP "RD[7]" SITE "43";
LOCATE COMP "Vout[0]" SITE "18";
LOCATE COMP "Vout[1]" SITE "15";
LOCATE COMP "Vout[2]" SITE "17";
LOCATE COMP "Vout[3]" SITE "13";
LOCATE COMP "Vout[4]" SITE "19";
LOCATE COMP "Vout[5]" SITE "16";
LOCATE COMP "Vout[6]" SITE "14";
LOCATE COMP "Vout[7]" SITE "12";
LOCATE COMP "nC07X" SITE "34";
LOCATE COMP "nCASout" SITE "52";
LOCATE COMP "nCSout" SITE "57";
LOCATE COMP "nDHGROE" SITE "47";
LOCATE COMP "nDOE" SITE "20";
LOCATE COMP "nEN80" SITE "82";
LOCATE COMP "nRASout" SITE "54";
LOCATE COMP "nRWEout" SITE "51";
LOCATE COMP "nVOE" SITE "10";
LOCATE COMP "nWE" SITE "29";
PAR: Place And Route Diamond (64-bit) 3.11.3.469.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Fri Jun 07 20:50:12 2024

128
CPLD/LCMXO2-640HC-NODHGR/impl1/RAM2E_LCMXO2_640HC_impl1.prf Normal file
View File

@ -0,0 +1,128 @@
SCHEMATIC START ;
# map: version Diamond (64-bit) 3.11.3.469 -- WARNING: Map write only section -- Fri Jun 07 20:49:59 2024
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
LOCATE COMP "RD[0]" SITE "36" ;
LOCATE COMP "LED" SITE "35" ;
LOCATE COMP "C14M" SITE "62" ;
LOCATE COMP "RD[7]" SITE "43" ;
LOCATE COMP "RD[6]" SITE "42" ;
LOCATE COMP "RD[5]" SITE "41" ;
LOCATE COMP "RD[4]" SITE "40" ;
LOCATE COMP "RD[3]" SITE "39" ;
LOCATE COMP "RD[2]" SITE "38" ;
LOCATE COMP "RD[1]" SITE "37" ;
LOCATE COMP "DQMH" SITE "49" ;
LOCATE COMP "DQML" SITE "48" ;
LOCATE COMP "RAout[11]" SITE "59" ;
LOCATE COMP "RAout[10]" SITE "64" ;
LOCATE COMP "RAout[9]" SITE "63" ;
LOCATE COMP "RAout[8]" SITE "65" ;
LOCATE COMP "RAout[7]" SITE "67" ;
LOCATE COMP "RAout[6]" SITE "69" ;
LOCATE COMP "RAout[5]" SITE "71" ;
LOCATE COMP "RAout[4]" SITE "75" ;
LOCATE COMP "RAout[3]" SITE "74" ;
LOCATE COMP "RAout[2]" SITE "70" ;
LOCATE COMP "RAout[1]" SITE "68" ;
LOCATE COMP "RAout[0]" SITE "66" ;
LOCATE COMP "BA[1]" SITE "60" ;
LOCATE COMP "BA[0]" SITE "58" ;
LOCATE COMP "nRWEout" SITE "51" ;
LOCATE COMP "nCASout" SITE "52" ;
LOCATE COMP "nRASout" SITE "54" ;
LOCATE COMP "nCSout" SITE "57" ;
LOCATE COMP "CKEout" SITE "53" ;
LOCATE COMP "nVOE" SITE "10" ;
LOCATE COMP "Vout[7]" SITE "12" ;
LOCATE COMP "Vout[6]" SITE "14" ;
LOCATE COMP "Vout[5]" SITE "16" ;
LOCATE COMP "Vout[4]" SITE "19" ;
LOCATE COMP "Vout[3]" SITE "13" ;
LOCATE COMP "Vout[2]" SITE "17" ;
LOCATE COMP "Vout[1]" SITE "15" ;
LOCATE COMP "Vout[0]" SITE "18" ;
LOCATE COMP "nDOE" SITE "20" ;
LOCATE COMP "Dout[7]" SITE "32" ;
LOCATE COMP "Dout[6]" SITE "31" ;
LOCATE COMP "Dout[5]" SITE "21" ;
LOCATE COMP "Dout[4]" SITE "24" ;
LOCATE COMP "Dout[3]" SITE "28" ;
LOCATE COMP "Dout[2]" SITE "25" ;
LOCATE COMP "Dout[1]" SITE "27" ;
LOCATE COMP "Dout[0]" SITE "30" ;
LOCATE COMP "Din[7]" SITE "87" ;
LOCATE COMP "Din[6]" SITE "88" ;
LOCATE COMP "Din[5]" SITE "99" ;
LOCATE COMP "Din[4]" SITE "1" ;
LOCATE COMP "Din[3]" SITE "9" ;
LOCATE COMP "Din[2]" SITE "98" ;
LOCATE COMP "Din[1]" SITE "97" ;
LOCATE COMP "Din[0]" SITE "96" ;
LOCATE COMP "Ain[7]" SITE "8" ;
LOCATE COMP "Ain[6]" SITE "86" ;
LOCATE COMP "Ain[5]" SITE "84" ;
LOCATE COMP "Ain[4]" SITE "78" ;
LOCATE COMP "Ain[3]" SITE "4" ;
LOCATE COMP "Ain[2]" SITE "7" ;
LOCATE COMP "Ain[1]" SITE "2" ;
LOCATE COMP "Ain[0]" SITE "3" ;
LOCATE COMP "nC07X" SITE "34" ;
LOCATE COMP "nEN80" SITE "82" ;
LOCATE COMP "nWE" SITE "29" ;
LOCATE COMP "nDHGROE" SITE "47" ;
LOCATE COMP "PHI1" SITE "85" ;
FREQUENCY PORT "C14M" 14.300000 MHz ;
SCHEMATIC END ;
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
OUTPUT PORT "LED" LOAD 100.000000 pF ;
OUTPUT PORT "nDHGROE" LOAD 10.000000 pF ;
OUTPUT PORT "BA[1]" LOAD 5.000000 pF ;
OUTPUT PORT "BA[0]" LOAD 5.000000 pF ;
OUTPUT PORT "CKEout" LOAD 5.000000 pF ;
OUTPUT PORT "DQMH" LOAD 5.000000 pF ;
OUTPUT PORT "DQML" LOAD 5.000000 pF ;
OUTPUT PORT "Dout[0]" LOAD 15.000000 pF ;
OUTPUT PORT "Dout[1]" LOAD 15.000000 pF ;
OUTPUT PORT "Dout[2]" LOAD 15.000000 pF ;
OUTPUT PORT "Dout[3]" LOAD 15.000000 pF ;
OUTPUT PORT "Dout[4]" LOAD 15.000000 pF ;
OUTPUT PORT "Dout[5]" LOAD 15.000000 pF ;
OUTPUT PORT "Dout[6]" LOAD 15.000000 pF ;
OUTPUT PORT "Dout[7]" LOAD 15.000000 pF ;
OUTPUT PORT "RAout[0]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[1]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[2]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[3]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[4]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[5]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[6]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[7]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[8]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[9]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[10]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[11]" LOAD 5.000000 pF ;
OUTPUT PORT "Vout[0]" LOAD 15.000000 pF ;
OUTPUT PORT "Vout[1]" LOAD 15.000000 pF ;
OUTPUT PORT "Vout[2]" LOAD 15.000000 pF ;
OUTPUT PORT "Vout[3]" LOAD 15.000000 pF ;
OUTPUT PORT "Vout[4]" LOAD 15.000000 pF ;
OUTPUT PORT "Vout[5]" LOAD 15.000000 pF ;
OUTPUT PORT "Vout[6]" LOAD 15.000000 pF ;
OUTPUT PORT "Vout[7]" LOAD 15.000000 pF ;
OUTPUT PORT "nCASout" LOAD 5.000000 pF ;
OUTPUT PORT "nCSout" LOAD 5.000000 pF ;
OUTPUT PORT "nDOE" LOAD 10.000000 pF ;
OUTPUT PORT "nRASout" LOAD 5.000000 pF ;
OUTPUT PORT "nRWEout" LOAD 5.000000 pF ;
OUTPUT PORT "nVOE" LOAD 10.000000 pF ;
OUTPUT PORT "RD[0]" LOAD 9.000000 pF ;
OUTPUT PORT "RD[1]" LOAD 9.000000 pF ;
OUTPUT PORT "RD[2]" LOAD 9.000000 pF ;
OUTPUT PORT "RD[3]" LOAD 9.000000 pF ;
OUTPUT PORT "RD[4]" LOAD 9.000000 pF ;
OUTPUT PORT "RD[5]" LOAD 9.000000 pF ;
OUTPUT PORT "RD[6]" LOAD 9.000000 pF ;
OUTPUT PORT "RD[7]" LOAD 9.000000 pF ;
COMMERCIAL ;

740
CPLD/LCMXO2-640HC-NODHGR/impl1/RAM2E_LCMXO2_640HC_impl1.srr Normal file
View File

@ -0,0 +1,740 @@
#Build: Synplify Pro (R) N-2018.03L-SP1-1, Build 443R, Apr 1 2019
#install: C:\lscc\diamond\3.11_x64\synpbase
#OS: Windows 8 6.2
#Hostname: ZANEMACWIN11
# Fri Jun 7 20:49:50 2024
#Implementation: impl1
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys HDL Compiler, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Verilog Compiler, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v" (library work)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\pmi_def.v" (library work)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v" (library work)
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v" (library work)
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC-NODHGR\REFB.v" (library work)
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\DHGR-OFF.v" (library work)
Verilog syntax check successful!
Selecting top level module RAM2E
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
Running optimization stage 1 on VHI .......
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
Running optimization stage 1 on VLO .......
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
Running optimization stage 1 on EFB .......
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC-NODHGR\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
Running optimization stage 1 on REFB .......
@W: CL318 :"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC-NODHGR\REFB.v":9:14:9:21|*Output wb_dat_o has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output.
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v":1:7:1:15|Synthesizing module RAM2E_UFM in library work.
Running optimization stage 1 on RAM2E_UFM .......
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\DHGR-OFF.v":1:7:1:10|Synthesizing module DHGR in library work.
Running optimization stage 1 on DHGR .......
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v":1:7:1:11|Synthesizing module RAM2E in library work.
Running optimization stage 1 on RAM2E .......
Running optimization stage 2 on RAM2E .......
@N: CL159 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v":11:15:11:19|Input nWE80 is unused.
Running optimization stage 2 on DHGR .......
Running optimization stage 2 on RAM2E_UFM .......
Running optimization stage 2 on REFB .......
Running optimization stage 2 on EFB .......
Running optimization stage 2 on VLO .......
Running optimization stage 2 on VHI .......
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Fri Jun 7 20:49:51 2024
###########################################################]
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Fri Jun 7 20:49:51 2024
###########################################################]
For a summary of runtime and memory usage for all design units, please see file:
==========================================================
@L: A:\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC-NODHGR\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_comp.rt.csv
@END
At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Fri Jun 7 20:49:51 2024
###########################################################]
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Database state : \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC-NODHGR\impl1\synwork\|impl1
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Fri Jun 7 20:49:52 2024
###########################################################]
Premap Report
# Fri Jun 7 20:49:53 2024
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Lattice Technology Pre-mapping, Version maplat2018q2p1, Build 055R, Built Apr 3 2019 09:51:54
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
Reading constraint file: \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
@N: MF284 |Setting synthesis effort to medium for the design
@L: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC-NODHGR\impl1\RAM2E_LCMXO2_640HC_impl1_scck.rpt
Printing clock summary report in "\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC-NODHGR\impl1\RAM2E_LCMXO2_640HC_impl1_scck.rpt" file
@N: MF916 |Option synthesis_strategy=base is enabled.
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB)
@N: MF284 |Setting synthesis effort to medium for the design
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":21:4:21:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
@N: MH105 |UMR3 is only supported for HAPS-80.
@N: MH105 |UMR3 is only supported for HAPS-80.
@N: BN115 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":140:9:140:12|Removing instance dhgr (in view: work.RAM2E(verilog)) of type view:work.DHGR(verilog) because it does not drive other instances.
syn_allowed_resources : blockrams=2 set on top level netlist RAM2E
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
Clock Summary
******************
Start Requested Requested Clock Clock Clock
Level Clock Frequency Period Type Group Load
-----------------------------------------------------------------------------------------------
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 121
0 - System 100.0 MHz 10.000 system system_clkgroup 0
0 - RAM2E|PHI1 100.0 MHz 10.000 inferred Inferred_clkgroup_0 9
===============================================================================================
Clock Load Summary
***********************
Clock Source Clock Pin Non-clock Pin Non-clock Pin
Clock Load Pin Seq Example Seq Example Comb Example
--------------------------------------------------------------------------------------------
C14M 121 C14M(port) RAT.C - un1_C14M.I[0](inv)
System 0 - - - -
RAM2E|PHI1 9 PHI1(port) RefReq.C S[0].D[0] un1_PHI1.I[0](inv)
============================================================================================
@W: MT529 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":20:19:20:24|Found inferred clock RAM2E|PHI1 which controls 9 sequential elements including PHI1r. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed: 0
@S |Clock Optimization Summary
#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
2 non-gated/non-generated clock tree(s) driving 125 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
---------------------------------------------------------------------------------------
@KP:ckid0_0 C14M port 121 PHI1r
@KP:ckid0_1 PHI1 Unconstrained_port 4 RC[2:0]
=======================================================================================
##### END OF CLOCK OPTIMIZATION REPORT ######
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
Finished Pre Mapping Phase.
Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
None
None
Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
Pre-mapping successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Jun 7 20:49:53 2024
###########################################################]
Map & Optimize Report
# Fri Jun 7 20:49:53 2024
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Lattice Technology Mapper, Version maplat2018q2p1, Build 055R, Built Apr 3 2019 09:51:54
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
@N: MF284 |Setting synthesis effort to medium for the design
@N: MF916 |Option synthesis_strategy=base is enabled.
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
@N: MF284 |Setting synthesis effort to medium for the design
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
Available hyper_sources - for debug and ip models
None Found
@N: FX493 |Applying initial value "00000000" on instance RWBank[7:0].
@N: FX493 |Applying initial value "0000" on instance S[3:0].
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)
@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":14:23:14:28|Found counter in view:work.RAM2E(verilog) instance FS[15:0]
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 142MB)
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:01s 6.90ns 281 / 125
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":171:4:171:9|Boundary register BA_1_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":171:4:171:9|Boundary register BA_0_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 158MB peak: 160MB)
Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 122MB peak: 160MB)
Writing Analyst data base \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC-NODHGR\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_m.srm
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 158MB peak: 160MB)
Writing EDIF Netlist and constraint files
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC-NODHGR\impl1\RAM2E_LCMXO2_640HC_impl1.edi
N-2018.03L-SP1-1
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 162MB peak: 164MB)
Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 161MB peak: 164MB)
@W: MT246 :"\\mac\icloud\repos\ram2e\cpld\lcmxo2-640hc-nodhgr\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@N: MT615 |Found clock C14M with period 69.84ns
@W: MT420 |Found inferred clock RAM2E|PHI1 with period 10.00ns. Please declare a user-defined clock on port PHI1.
##### START OF TIMING REPORT #####[
# Timing Report written on Fri Jun 7 20:49:57 2024
#
Top view: RAM2E
Requested Frequency: 14.3 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s): \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
Performance Summary
*******************
Worst slack in design: 6.897
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
----------------------------------------------------------------------------------------------------------------------
C14M 14.3 MHz 112.1 MHz 69.841 8.918 31.599 declared default_clkgroup
RAM2E|PHI1 100.0 MHz 322.2 MHz 10.000 3.103 6.897 inferred Inferred_clkgroup_0
System 100.0 MHz NA 10.000 NA 67.088 system system_clkgroup
======================================================================================================================
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
----------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
----------------------------------------------------------------------------------------------------------------
System C14M | 69.841 67.088 | No paths - | No paths - | No paths -
C14M System | 69.841 68.797 | No paths - | No paths - | No paths -
C14M C14M | 69.841 60.923 | No paths - | 34.920 31.599 | No paths -
RAM2E|PHI1 C14M | No paths - | No paths - | No paths - | Diff grp -
RAM2E|PHI1 RAM2E|PHI1 | No paths - | 10.000 6.897 | No paths - | No paths -
================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Interface Information
*********************
No IO constraint found
====================================
Detailed Report for Clock: C14M
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------
S[2] C14M FD1S3AX Q S[2] 1.366 31.599
S[3] C14M FD1S3AX Q S[3] 1.345 31.619
S[1] C14M FD1S3AX Q S[1] 1.344 31.800
S[0] C14M FD1S3AX Q S[0] 1.305 31.838
RA[0] C14M FD1P3AX Q RA[0] 1.108 33.707
RA[3] C14M FD1P3AX Q RA[3] 1.108 33.707
RA[1] C14M FD1P3AX Q RA[1] 1.044 33.771
RA[2] C14M FD1P3AX Q RA[2] 1.044 33.771
RA[4] C14M FD1P3AX Q RA[4] 1.044 33.771
RA[5] C14M FD1P3AX Q RA[5] 1.044 33.771
===========================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
-----------------------------------------------------------------------------------
VOE_i_0io C14M OFS1P3IX CD N_530 34.118 31.599
VOE_i_0io C14M OFS1P3IX D VOE_ic_i 35.009 31.800
Vout_0io[0] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[1] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[2] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[3] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[4] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[5] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[6] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[7] C14M OFS1P3DX SP Vout3 34.449 32.634
===================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 34.920
- Setup time: 0.803
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 34.118
- Propagation time: 2.519
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : 31.599
Number of logic level(s): 1
Starting point: S[2] / Q
Ending point: VOE_i_0io / CD
The start point is clocked by C14M [rising] on pin CK
The end point is clocked by C14M [falling] on pin SCLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
------------------------------------------------------------------------------------------------------------
S[2] FD1S3AX Q Out 1.366 1.366 -
S[2] Net - - - - 58
ram2e_ufm.un1_wb_adr_0_sqmuxa_2_0_a2_0[0] ORCALUT4 A In 0.000 1.366 -
ram2e_ufm.un1_wb_adr_0_sqmuxa_2_0_a2_0[0] ORCALUT4 Z Out 1.153 2.519 -
N_530 Net - - - - 3
VOE_i_0io OFS1P3IX CD In 0.000 2.519 -
============================================================================================================
====================================
Detailed Report for Clock: RAM2E|PHI1
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------
RC[1] RAM2E|PHI1 FD1S3IX Q RC[1] 1.148 6.897
RC[2] RAM2E|PHI1 FD1S3IX Q RC[2] 1.108 6.937
RC[0] RAM2E|PHI1 FD1S3IX Q RC[0] 1.148 8.179
===========================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------
RC[0] RAM2E|PHI1 FD1S3IX CD RC7 9.197 6.897
RC[1] RAM2E|PHI1 FD1S3IX CD RC7 9.197 6.897
RC[2] RAM2E|PHI1 FD1S3IX CD RC7 9.197 6.897
RC[0] RAM2E|PHI1 FD1S3IX D RC_i[0] 9.894 8.179
RC[1] RAM2E|PHI1 FD1S3IX D RC_RNO[1] 10.089 8.324
RC[2] RAM2E|PHI1 FD1S3IX D RC_RNO[2] 10.089 8.324
RefReq RAM2E|PHI1 FD1S3AX D RefReq_2 10.089 8.324
================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 10.000
- Setup time: 0.803
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 9.197
- Propagation time: 2.301
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : 6.897
Number of logic level(s): 1
Starting point: RC[1] / Q
Ending point: RC[0] / CD
The start point is clocked by RAM2E|PHI1 [falling] on pin CK
The end point is clocked by RAM2E|PHI1 [falling] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------
RC[1] FD1S3IX Q Out 1.148 1.148 -
RC[1] Net - - - - 4
RC7 ORCALUT4 A In 0.000 1.148 -
RC7 ORCALUT4 Z Out 1.153 2.301 -
RC7 Net - - - - 3
RC[0] FD1S3IX CD In 0.000 2.301 -
=================================================================================
====================================
Detailed Report for Clock: System
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------------------------------
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBACKO wb_ack 0.000 67.088
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO0 wb_dato[0] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO2 wb_dato[2] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO3 wb_dato[3] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO4 wb_dato[4] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO5 wb_dato[5] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO6 wb_dato[6] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO7 wb_dato[7] 0.000 69.313
===================================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
----------------------------------------------------------------------------------------
ram2e_ufm.RWMask[0] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[1] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[2] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[3] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[4] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[5] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[6] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[7] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.LEDEN System FD1P3AX SP N_98 69.369 67.736
ram2e_ufm.wb_cyc_stb System FD1P3AX SP N_111 69.369 67.736
========================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 69.841
- Setup time: 0.472
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 69.369
- Propagation time: 2.282
- Clock delay at starting point: 0.000 (ideal)
- Estimated clock delay at start point: -0.000
= Slack (non-critical) : 67.088
Number of logic level(s): 2
Starting point: ram2e_ufm.ufmefb.EFBInst_0 / WBACKO
Ending point: ram2e_ufm.RWMask[0] / SP
The start point is clocked by System [rising]
The end point is clocked by C14M [rising] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
----------------------------------------------------------------------------------------------------------------
ram2e_ufm.ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 -
wb_ack Net - - - - 5
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] ORCALUT4 B In 0.000 0.000 -
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] ORCALUT4 Z Out 1.017 1.017 -
un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] Net - - - - 1
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 D In 0.000 1.017 -
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 Z Out 1.265 2.282 -
N_104 Net - - - - 8
ram2e_ufm.RWMask[0] FD1P3AX SP In 0.000 2.282 -
================================================================================================================
##### END OF TIMING REPORT #####]
Timing exceptions that could not be applied
None
Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 161MB peak: 164MB)
Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 161MB peak: 164MB)
---------------------------------------
Resource Usage Report
Part: lcmxo2_640hc-4
Register bits: 125 of 640 (20%)
PIC Latch: 0
I/O cells: 70
Details:
BB: 8
CCU2D: 9
EFB: 1
FD1P3AX: 58
FD1P3IX: 1
FD1S3AX: 31
FD1S3AY: 4
FD1S3IX: 9
GSR: 1
IB: 21
IFS1P3DX: 1
INV: 4
OB: 41
OFS1P3BX: 6
OFS1P3DX: 12
OFS1P3IX: 3
ORCALUT4: 275
PUR: 1
VHI: 3
VLO: 3
Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 32MB peak: 164MB)
Process took 0h:00m:03s realtime, 0h:00m:03s cputime
# Fri Jun 7 20:49:57 2024
###########################################################]

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Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
# Written on Fri Jun 7 20:49:53 2024
##### DESIGN INFO #######################################################
Top View: "RAM2E"
Constraint File(s): "\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc"
##### SUMMARY ############################################################
Found 0 issues in 0 out of 1 constraints
##### DETAILS ############################################################
Clock Relationships
*******************
Starting Ending | rise to rise | fall to fall | rise to fall | fall to rise
-----------------------------------------------------------------------------------------------------------------------------------------
System C14M | 69.841 | No paths | No paths | No paths
C14M System | 69.841 | No paths | No paths | No paths
C14M C14M | 69.841 | No paths | 34.920 | No paths
RAM2E|PHI1 C14M | No paths | No paths | No paths | Diff grp
RAM2E|PHI1 RAM2E|PHI1 | No paths | 10.000 | No paths | No paths
=========================================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Unconstrained Start/End Points
******************************
p:Ain[0]
p:Ain[1]
p:Ain[2]
p:Ain[3]
p:Ain[4]
p:Ain[5]
p:Ain[6]
p:Ain[7]
p:BA[0]
p:BA[1]
p:CKEout
p:DQMH
p:DQML
p:Din[0]
p:Din[1]
p:Din[2]
p:Din[3]
p:Din[4]
p:Din[5]
p:Din[6]
p:Din[7]
p:Dout[0]
p:Dout[1]
p:Dout[2]
p:Dout[3]
p:Dout[4]
p:Dout[5]
p:Dout[6]
p:Dout[7]
p:LED
p:RAout[0]
p:RAout[1]
p:RAout[2]
p:RAout[3]
p:RAout[4]
p:RAout[5]
p:RAout[6]
p:RAout[7]
p:RAout[8]
p:RAout[9]
p:RAout[10]
p:RAout[11]
p:RD[0] (bidir end point)
p:RD[0] (bidir start point)
p:RD[1] (bidir end point)
p:RD[1] (bidir start point)
p:RD[2] (bidir end point)
p:RD[2] (bidir start point)
p:RD[3] (bidir end point)
p:RD[3] (bidir start point)
p:RD[4] (bidir end point)
p:RD[4] (bidir start point)
p:RD[5] (bidir end point)
p:RD[5] (bidir start point)
p:RD[6] (bidir end point)
p:RD[6] (bidir start point)
p:RD[7] (bidir end point)
p:RD[7] (bidir start point)
p:Vout[0]
p:Vout[1]
p:Vout[2]
p:Vout[3]
p:Vout[4]
p:Vout[5]
p:Vout[6]
p:Vout[7]
p:nC07X
p:nCASout
p:nCSout
p:nDHGROE
p:nDOE
p:nEN80
p:nRASout
p:nRWEout
p:nVOE
p:nWE
p:nWE80
Inapplicable constraints
************************
(none)
Applicable constraints with issues
**********************************
(none)
Constraints with matching wildcard expressions
**********************************************
(none)
Library Report
**************
# End of Constraint Checker Report

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<HTML>
<HEAD><TITLE>Project Summary</TITLE>
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<PRE><A name="Mrp"></A>
Lattice Mapping Report File for Design Module 'RAM2E'
<A name="mrp_di"></A><B><U><big>Design Information</big></U></B>
Command line: map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial
RAM2E_LCMXO2_640HC_impl1.ngd -o RAM2E_LCMXO2_640HC_impl1_map.ncd -pr
RAM2E_LCMXO2_640HC_impl1.prf -mp RAM2E_LCMXO2_640HC_impl1.mrp -lpf //Mac/iC
loud/Repos/RAM2E/CPLD/LCMXO2-640HC-NODHGR/impl1/RAM2E_LCMXO2_640HC_impl1_sy
nplify.lpf -lpf //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf -c 0 -gui
Target Vendor: LATTICE
Target Device: LCMXO2-640HCTQFP100
Target Performance: 4
Mapper: xo2c00, version: Diamond (64-bit) 3.11.3.469
Mapped on: 06/07/24 20:49:58
<A name="mrp_ds"></A><B><U><big>Design Summary</big></U></B>
Number of registers: 125 out of 877 (14%)
PFU registers: 103 out of 640 (16%)
PIO registers: 22 out of 237 (9%)
Number of SLICEs: 148 out of 320 (46%)
SLICEs as Logic/ROM: 148 out of 320 (46%)
SLICEs as RAM: 0 out of 240 (0%)
SLICEs as Carry: 9 out of 320 (3%)
Number of LUT4s: 296 out of 640 (46%)
Number used as logic LUTs: 278
Number used as distributed RAM: 0
Number used as ripple logic: 18
Number used as shift registers: 0
Number of PIO sites used: 70 + 4(JTAG) out of 79 (94%)
Number of block RAMs: 0 out of 2 (0%)
Number of GSRs: 0 out of 1 (0%)
EFB used : Yes
JTAG used : No
Readback used : No
Oscillator used : No
Startup used : No
POR : On
Bandgap : On
Number of Power Controller: 0 out of 1 (0%)
Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
Number of DCCA: 0 out of 8 (0%)
Number of DCMA: 0 out of 2 (0%)
Notes:-
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
distributed RAMs) + 2*(Number of ripple logic)
2. Number of logic LUT4s does not include count of distributed RAM and
ripple logic.
Number of clocks: 2
Net C14M_c: 85 loads, 63 rising, 22 falling (Driver: PIO C14M )
Net PHI1_c: 3 loads, 0 rising, 3 falling (Driver: PIO PHI1 )
Number of Clock Enables: 13
Net N_117_i: 2 loads, 0 LSLICEs
Net RWBank14: 11 loads, 11 LSLICEs
Net ram2e_ufm/wb_adr_0_sqmuxa_1_i: 1 loads, 1 LSLICEs
Net un9_VOE_0_a2_0_a2: 1 loads, 1 LSLICEs
Net un6_DOEEN_0_a2_0_a2: 2 loads, 2 LSLICEs
Net ram2e_ufm/un1_wb_adr_0_sqmuxa_2_i[0]: 8 loads, 8 LSLICEs
Net ram2e_ufm/un1_wb_cyc_stb_0_sqmuxa_1_i[0]: 1 loads, 1 LSLICEs
Net ram2e_ufm/N_111: 1 loads, 1 LSLICEs
Net ram2e_ufm/N_104: 4 loads, 4 LSLICEs
Net ram2e_ufm/N_98: 1 loads, 1 LSLICEs
Net un1_CKE48_0_i: 6 loads, 6 LSLICEs
Net N_389_i: 2 loads, 0 LSLICEs
Net Vout3: 8 loads, 0 LSLICEs
Number of LSRs: 8
Net N_148: 2 loads, 2 LSLICEs
Net N_430_i: 2 loads, 0 LSLICEs
Net RC7: 2 loads, 2 LSLICEs
Net S[2]: 2 loads, 2 LSLICEs
Net ram2e_ufm/wb_rst: 1 loads, 0 LSLICEs
Net ram2e_ufm/nRWE_0_i_o3_RNIP8E61: 1 loads, 1 LSLICEs
Net N_530: 1 loads, 0 LSLICEs
Net N_301_i: 1 loads, 1 LSLICEs
Number of nets driven by tri-state buffers: 0
Top 10 highest fanout non-clock nets:
Net S[2]: 60 loads
Net S[3]: 48 loads
Net S[1]: 46 loads
Net S[0]: 31 loads
Net FS[11]: 24 loads
Net FS[10]: 23 loads
Net FS[12]: 23 loads
Net FS[9]: 23 loads
Net FS[13]: 21 loads
Net FS[8]: 18 loads
Number of warnings: 3
Number of errors: 0
<A name="mrp_dwe"></A><B><U><big>Design Errors/Warnings</big></U></B>
WARNING - map: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf(94): Semantic
error in "IOBUF PORT "nWE80" IO_TYPE=LVCMOS33 PULLMODE=NONE ;": Port
"nWE80" does not exist in the design. This preference has been disabled.
WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
temporarily disable certain features of the device including Power
Controller, GSR, Hardened User SPI Port, Hardened Primary User I2C Port.
Functionality is restored after the Flash Memory (UFM/Configuration)
Interface is disabled using Disable Configuration Interface command 0x26
followed by Bypass command 0xFF.
WARNING - map: IO buffer missing for top level port nWE80...logic will be
discarded.
<A name="mrp_ioa"></A><B><U><big>IO (PIO) Attributes</big></U></B>
+---------------------+-----------+-----------+------------+
| IO Name | Direction | Levelmode | IO |
| | | IO_TYPE | Register |
+---------------------+-----------+-----------+------------+
| RD[0] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| LED | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| C14M | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[7] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[6] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[5] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[4] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[3] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[2] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[1] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| DQMH | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| DQML | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RAout[11] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RAout[10] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RAout[9] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RAout[8] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RAout[7] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[6] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[5] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[4] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[3] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[2] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[1] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[0] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| BA[1] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| BA[0] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nRWEout | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nCASout | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nRASout | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nCSout | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| CKEout | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nVOE | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[7] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[6] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[5] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[4] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[3] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[2] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[1] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[0] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nDOE | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[7] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[6] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[5] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[4] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[3] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[2] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[1] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[0] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[7] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[6] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[5] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[4] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[3] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[2] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[1] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[0] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[7] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[6] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[5] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[4] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[3] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[2] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[1] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[0] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nC07X | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nEN80 | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nWE | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nDHGROE | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| PHI1 | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
<A name="mrp_rm"></A><B><U><big>Removed logic</big></U></B>
Block GSR_INST undriven or does not drive anything - clipped.
Block ram2e_ufm/VCC undriven or does not drive anything - clipped.
Block ram2e_ufm/GND undriven or does not drive anything - clipped.
Signal RC_0_.CN was merged into signal PHI1_c
Signal RDOE_i was merged into signal RDOE
Signal RAT.CN was merged into signal C14M_c
Signal ram2e_ufm/ufmefb/VCC undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/GND undriven or does not drive anything - clipped.
Signal FS_s_0_S1[15] undriven or does not drive anything - clipped.
Signal FS_s_0_COUT[15] undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/CFGWAKE undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/wbc_ufm_irq undriven or does not drive anything -
clipped.
Signal ram2e_ufm/ufmefb/TCOC undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/TCINT undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIIRQO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPICSNEN undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMOSIEN undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMOSIO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMISOEN undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMISOO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPISCKEN undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPISCKO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C2SDAOEN undriven or does not drive anything -
clipped.
Signal ram2e_ufm/ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C2SCLOEN undriven or does not drive anything -
clipped.
Signal ram2e_ufm/ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C1SDAOEN undriven or does not drive anything -
clipped.
Signal ram2e_ufm/ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C1SCLOEN undriven or does not drive anything -
clipped.
Signal ram2e_ufm/ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLADRO4 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLWEO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLL1STBO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLL0STBO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLRSTO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLCLKO undriven or does not drive anything - clipped.
Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped.
Signal N_1 undriven or does not drive anything - clipped.
Block RefReq.CN was optimized away.
Block RDOE_RNIAM8C was optimized away.
Block nCASout.CN was optimized away.
Block ram2e_ufm/ufmefb/VCC was optimized away.
Block ram2e_ufm/ufmefb/GND was optimized away.
<A name="mrp_efb"></A><B><U><big>Embedded Functional Block Connection Summary</big></U></B>
Desired WISHBONE clock frequency: 14.4 MHz
Clock source: C14M_c
Reset source: ram2e_ufm/wb_rst
Functions mode:
I2C #1 (Primary) Function: DISABLED
I2C #2 (Secondary) Function: DISABLED
SPI Function: DISABLED
Timer/Counter Function: DISABLED
Timer/Counter Mode: WB
UFM Connection: ENABLED
PLL0 Connection: DISABLED
PLL1 Connection: DISABLED
I2C Function Summary:
--------------------
None
SPI Function Summary:
--------------------
None
Timer/Counter Function Summary:
------------------------------
None
UFM Function Summary:
--------------------
UFM Utilization: General Purpose Flash Memory
Initialized UFM Pages: 1 Pages (1*128 Bits)
Available General
Purpose Flash Memory: 191 Pages (191*128 Bits)
EBR Blocks with Unique
Initialization Data: 0
WID EBR Instance
--- ------------
<A name="mrp_asic"></A><B><U><big>ASIC Components</big></U></B>
---------------
Instance Name: ram2e_ufm/ufmefb/EFBInst_0
Type: EFB
<A name="mrp_runtime"></A><B><U><big>Run Time and Memory Usage</big></U></B>
-------------------------
Total CPU Time: 0 secs
Total REAL Time: 0 secs
Peak Memory Usage: 59 MB
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights
reserved.
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<HEAD><TITLE>PAD Specification File</TITLE>
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<PRE><A name="Pad"></A>PAD Specification File
***************************
PART TYPE: LCMXO2-640HC
Performance Grade: 4
PACKAGE: TQFP100
Package Status: Final Version 1.39
Fri Jun 07 20:50:08 2024
Pinout by Port Name:
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties |
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
| Ain[0] | 3/3 | LVCMOS33_IN | PL2C | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[1] | 2/3 | LVCMOS33_IN | PL2B | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[2] | 7/3 | LVCMOS33_IN | PL3A | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[3] | 4/3 | LVCMOS33_IN | PL2D | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[4] | 78/0 | LVCMOS33_IN | PT11A | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[5] | 84/0 | LVCMOS33_IN | PT10A | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[6] | 86/0 | LVCMOS33_IN | PT9C | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[7] | 8/3 | LVCMOS33_IN | PL3B | | | CLAMP:ON HYSTERESIS:SMALL |
| BA[0] | 58/1 | LVCMOS33_OUT | PR6C | | | DRIVE:4mA SLEW:SLOW |
| BA[1] | 60/1 | LVCMOS33_OUT | PR6A | | | DRIVE:4mA SLEW:SLOW |
| C14M | 62/1 | LVCMOS33_IN | PR5D | | | CLAMP:ON HYSTERESIS:SMALL |
| CKEout | 53/1 | LVCMOS33_OUT | PR7B | | | DRIVE:4mA SLEW:SLOW |
| DQMH | 49/2 | LVCMOS33_OUT | PB14D | | | DRIVE:4mA SLEW:SLOW |
| DQML | 48/2 | LVCMOS33_OUT | PB14C | | | DRIVE:4mA SLEW:SLOW |
| Din[0] | 96/0 | LVCMOS33_IN | PT6D | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[1] | 97/0 | LVCMOS33_IN | PT6C | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[2] | 98/0 | LVCMOS33_IN | PT6B | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[3] | 9/3 | LVCMOS33_IN | PL3C | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[4] | 1/3 | LVCMOS33_IN | PL2A | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[5] | 99/0 | LVCMOS33_IN | PT6A | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[6] | 88/0 | LVCMOS33_IN | PT9A | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[7] | 87/0 | LVCMOS33_IN | PT9B | | | CLAMP:ON HYSTERESIS:SMALL |
| Dout[0] | 30/2 | LVCMOS33_OUT | PB4D | | | DRIVE:4mA SLEW:SLOW |
| Dout[1] | 27/2 | LVCMOS33_OUT | PB4A | | | DRIVE:4mA SLEW:SLOW |
| Dout[2] | 25/3 | LVCMOS33_OUT | PL7D | | | DRIVE:4mA SLEW:SLOW |
| Dout[3] | 28/2 | LVCMOS33_OUT | PB4B | | | DRIVE:4mA SLEW:SLOW |
| Dout[4] | 24/3 | LVCMOS33_OUT | PL7C | | | DRIVE:4mA SLEW:SLOW |
| Dout[5] | 21/3 | LVCMOS33_OUT | PL7B | | | DRIVE:4mA SLEW:SLOW |
| Dout[6] | 31/2 | LVCMOS33_OUT | PB6A | | | DRIVE:4mA SLEW:SLOW |
| Dout[7] | 32/2 | LVCMOS33_OUT | PB6B | | | DRIVE:4mA SLEW:SLOW |
| LED | 35/2 | LVCMOS33_OUT | PB6D | | | DRIVE:4mA SLEW:SLOW |
| PHI1 | 85/0 | LVCMOS33_IN | PT9D | | | CLAMP:ON HYSTERESIS:SMALL |
| RAout[0] | 66/1 | LVCMOS33_OUT | PR3D | | | DRIVE:4mA SLEW:SLOW |
| RAout[10] | 64/1 | LVCMOS33_OUT | PR5B | | | DRIVE:4mA SLEW:SLOW |
| RAout[11] | 59/1 | LVCMOS33_OUT | PR6B | | | DRIVE:4mA SLEW:SLOW |
| RAout[1] | 68/1 | LVCMOS33_OUT | PR3B | | | DRIVE:4mA SLEW:SLOW |
| RAout[2] | 70/1 | LVCMOS33_OUT | PR2D | | | DRIVE:4mA SLEW:SLOW |
| RAout[3] | 74/1 | LVCMOS33_OUT | PR2B | | | DRIVE:4mA SLEW:SLOW |
| RAout[4] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA SLEW:SLOW |
| RAout[5] | 71/1 | LVCMOS33_OUT | PR2C | | | DRIVE:4mA SLEW:SLOW |
| RAout[6] | 69/1 | LVCMOS33_OUT | PR3A | | | DRIVE:4mA SLEW:SLOW |
| RAout[7] | 67/1 | LVCMOS33_OUT | PR3C | | | DRIVE:4mA SLEW:SLOW |
| RAout[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA SLEW:SLOW |
| RAout[9] | 63/1 | LVCMOS33_OUT | PR5C | | | DRIVE:4mA SLEW:SLOW |
| RD[0] | 36/2 | LVCMOS33_BIDI | PB10A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[1] | 37/2 | LVCMOS33_BIDI | PB10B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[2] | 38/2 | LVCMOS33_BIDI | PB10C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[3] | 39/2 | LVCMOS33_BIDI | PB10D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[4] | 40/2 | LVCMOS33_BIDI | PB12A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[5] | 41/2 | LVCMOS33_BIDI | PB12B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[6] | 42/2 | LVCMOS33_BIDI | PB12C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[7] | 43/2 | LVCMOS33_BIDI | PB12D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| Vout[0] | 18/3 | LVCMOS33_OUT | PL6C | | | DRIVE:4mA SLEW:SLOW |
| Vout[1] | 15/3 | LVCMOS33_OUT | PL5D | | | DRIVE:4mA SLEW:SLOW |
| Vout[2] | 17/3 | LVCMOS33_OUT | PL6B | | | DRIVE:4mA SLEW:SLOW |
| Vout[3] | 13/3 | LVCMOS33_OUT | PL5B | | | DRIVE:4mA SLEW:SLOW |
| Vout[4] | 19/3 | LVCMOS33_OUT | PL6D | | | DRIVE:4mA SLEW:SLOW |
| Vout[5] | 16/3 | LVCMOS33_OUT | PL6A | | | DRIVE:4mA SLEW:SLOW |
| Vout[6] | 14/3 | LVCMOS33_OUT | PL5C | | | DRIVE:4mA SLEW:SLOW |
| Vout[7] | 12/3 | LVCMOS33_OUT | PL5A | | | DRIVE:4mA SLEW:SLOW |
| nC07X | 34/2 | LVCMOS33_IN | PB6C | | | CLAMP:ON HYSTERESIS:SMALL |
| nCASout | 52/1 | LVCMOS33_OUT | PR7C | | | DRIVE:4mA SLEW:SLOW |
| nCSout | 57/1 | LVCMOS33_OUT | PR6D | | | DRIVE:4mA SLEW:SLOW |
| nDHGROE | 47/2 | LVCMOS33_OUT | PB14B | | | DRIVE:4mA SLEW:SLOW |
| nDOE | 20/3 | LVCMOS33_OUT | PL7A | | | DRIVE:4mA SLEW:SLOW |
| nEN80 | 82/0 | LVCMOS33_IN | PT10C | | | CLAMP:ON HYSTERESIS:SMALL |
| nRASout | 54/1 | LVCMOS33_OUT | PR7A | | | DRIVE:4mA SLEW:SLOW |
| nRWEout | 51/1 | LVCMOS33_OUT | PR7D | | | DRIVE:4mA SLEW:SLOW |
| nVOE | 10/3 | LVCMOS33_OUT | PL3D | | | DRIVE:4mA SLEW:SLOW |
| nWE | 29/2 | LVCMOS33_IN | PB4C | | | CLAMP:ON HYSTERESIS:SMALL |
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
Vccio by Bank:
+------+-------+
| Bank | Vccio |
+------+-------+
| 0 | 3.3V |
| 1 | 3.3V |
| 2 | 3.3V |
| 3 | 3.3V |
+------+-------+
<A name="pad_vref"></A><B><U><big>Vref by Bank:</big></U></B>
+------+-----+-----------------+---------+
| Vref | Pin | Bank # / Vref # | Load(s) |
+------+-----+-----------------+---------+
+------+-----+-----------------+---------+
<A name="pad_pin"></A><B><U><big>Pinout by Pin Number:</big></U></B>
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable |
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
| 1/3 | Din[4] | LOCATED | LVCMOS33_IN | PL2A | | | |
| 2/3 | Ain[1] | LOCATED | LVCMOS33_IN | PL2B | | | |
| 3/3 | Ain[0] | LOCATED | LVCMOS33_IN | PL2C | PCLKT3_2 | | |
| 4/3 | Ain[3] | LOCATED | LVCMOS33_IN | PL2D | PCLKC3_2 | | |
| 7/3 | Ain[2] | LOCATED | LVCMOS33_IN | PL3A | | | |
| 8/3 | Ain[7] | LOCATED | LVCMOS33_IN | PL3B | | | |
| 9/3 | Din[3] | LOCATED | LVCMOS33_IN | PL3C | | | |
| 10/3 | nVOE | LOCATED | LVCMOS33_OUT | PL3D | | | |
| 12/3 | Vout[7] | LOCATED | LVCMOS33_OUT | PL5A | PCLKT3_1 | | |
| 13/3 | Vout[3] | LOCATED | LVCMOS33_OUT | PL5B | PCLKC3_1 | | |
| 14/3 | Vout[6] | LOCATED | LVCMOS33_OUT | PL5C | | | |
| 15/3 | Vout[1] | LOCATED | LVCMOS33_OUT | PL5D | | | |
| 16/3 | Vout[5] | LOCATED | LVCMOS33_OUT | PL6A | | | |
| 17/3 | Vout[2] | LOCATED | LVCMOS33_OUT | PL6B | | | |
| 18/3 | Vout[0] | LOCATED | LVCMOS33_OUT | PL6C | | | |
| 19/3 | Vout[4] | LOCATED | LVCMOS33_OUT | PL6D | | | |
| 20/3 | nDOE | LOCATED | LVCMOS33_OUT | PL7A | PCLKT3_0 | | |
| 21/3 | Dout[5] | LOCATED | LVCMOS33_OUT | PL7B | PCLKC3_0 | | |
| 24/3 | Dout[4] | LOCATED | LVCMOS33_OUT | PL7C | | | |
| 25/3 | Dout[2] | LOCATED | LVCMOS33_OUT | PL7D | | | |
| 27/2 | Dout[1] | LOCATED | LVCMOS33_OUT | PB4A | CSSPIN | | |
| 28/2 | Dout[3] | LOCATED | LVCMOS33_OUT | PB4B | | | |
| 29/2 | nWE | LOCATED | LVCMOS33_IN | PB4C | | | |
| 30/2 | Dout[0] | LOCATED | LVCMOS33_OUT | PB4D | | | |
| 31/2 | Dout[6] | LOCATED | LVCMOS33_OUT | PB6A | MCLK/CCLK | | |
| 32/2 | Dout[7] | LOCATED | LVCMOS33_OUT | PB6B | SO/SPISO | | |
| 34/2 | nC07X | LOCATED | LVCMOS33_IN | PB6C | PCLKT2_0 | | |
| 35/2 | LED | LOCATED | LVCMOS33_OUT | PB6D | PCLKC2_0 | | |
| 36/2 | RD[0] | LOCATED | LVCMOS33_BIDI | PB10A | | | |
| 37/2 | RD[1] | LOCATED | LVCMOS33_BIDI | PB10B | | | |
| 38/2 | RD[2] | LOCATED | LVCMOS33_BIDI | PB10C | PCLKT2_1 | | |
| 39/2 | RD[3] | LOCATED | LVCMOS33_BIDI | PB10D | PCLKC2_1 | | |
| 40/2 | RD[4] | LOCATED | LVCMOS33_BIDI | PB12A | | | |
| 41/2 | RD[5] | LOCATED | LVCMOS33_BIDI | PB12B | | | |
| 42/2 | RD[6] | LOCATED | LVCMOS33_BIDI | PB12C | | | |
| 43/2 | RD[7] | LOCATED | LVCMOS33_BIDI | PB12D | | | |
| 45/2 | unused, PULL:DOWN | | | PB14A | | | |
| 47/2 | nDHGROE | LOCATED | LVCMOS33_OUT | PB14B | | | |
| 48/2 | DQML | LOCATED | LVCMOS33_OUT | PB14C | SN | | |
| 49/2 | DQMH | LOCATED | LVCMOS33_OUT | PB14D | SI/SISPI | | |
| 51/1 | nRWEout | LOCATED | LVCMOS33_OUT | PR7D | | | |
| 52/1 | nCASout | LOCATED | LVCMOS33_OUT | PR7C | | | |
| 53/1 | CKEout | LOCATED | LVCMOS33_OUT | PR7B | | | |
| 54/1 | nRASout | LOCATED | LVCMOS33_OUT | PR7A | | | |
| 57/1 | nCSout | LOCATED | LVCMOS33_OUT | PR6D | | | |
| 58/1 | BA[0] | LOCATED | LVCMOS33_OUT | PR6C | | | |
| 59/1 | RAout[11] | LOCATED | LVCMOS33_OUT | PR6B | | | |
| 60/1 | BA[1] | LOCATED | LVCMOS33_OUT | PR6A | | | |
| 62/1 | C14M | LOCATED | LVCMOS33_IN | PR5D | PCLKC1_0 | | |
| 63/1 | RAout[9] | LOCATED | LVCMOS33_OUT | PR5C | PCLKT1_0 | | |
| 64/1 | RAout[10] | LOCATED | LVCMOS33_OUT | PR5B | | | |
| 65/1 | RAout[8] | LOCATED | LVCMOS33_OUT | PR5A | | | |
| 66/1 | RAout[0] | LOCATED | LVCMOS33_OUT | PR3D | | | |
| 67/1 | RAout[7] | LOCATED | LVCMOS33_OUT | PR3C | | | |
| 68/1 | RAout[1] | LOCATED | LVCMOS33_OUT | PR3B | | | |
| 69/1 | RAout[6] | LOCATED | LVCMOS33_OUT | PR3A | | | |
| 70/1 | RAout[2] | LOCATED | LVCMOS33_OUT | PR2D | | | |
| 71/1 | RAout[5] | LOCATED | LVCMOS33_OUT | PR2C | | | |
| 74/1 | RAout[3] | LOCATED | LVCMOS33_OUT | PR2B | | | |
| 75/1 | RAout[4] | LOCATED | LVCMOS33_OUT | PR2A | | | |
| 76/0 | unused, PULL:DOWN | | | PT11D | DONE | | |
| 77/0 | unused, PULL:DOWN | | | PT11C | INITN | | |
| 78/0 | Ain[4] | LOCATED | LVCMOS33_IN | PT11A | | | |
| 81/0 | unused, PULL:DOWN | | | PT10D | PROGRAMN | | |
| 82/0 | nEN80 | LOCATED | LVCMOS33_IN | PT10C | JTAGENB | | |
| 83/0 | unused, PULL:DOWN | | | PT10B | | | |
| 84/0 | Ain[5] | LOCATED | LVCMOS33_IN | PT10A | | | |
| 85/0 | PHI1 | LOCATED | LVCMOS33_IN | PT9D | SDA/PCLKC0_0 | | |
| 86/0 | Ain[6] | LOCATED | LVCMOS33_IN | PT9C | SCL/PCLKT0_0 | | |
| 87/0 | Din[7] | LOCATED | LVCMOS33_IN | PT9B | PCLKC0_1 | | |
| 88/0 | Din[6] | LOCATED | LVCMOS33_IN | PT9A | PCLKT0_1 | | |
| 90/0 | Reserved: sysCONFIG | | | PT7D | TMS | | |
| 91/0 | Reserved: sysCONFIG | | | PT7C | TCK | | |
| 94/0 | Reserved: sysCONFIG | | | PT7B | TDI | | |
| 95/0 | Reserved: sysCONFIG | | | PT7A | TDO | | |
| 96/0 | Din[0] | LOCATED | LVCMOS33_IN | PT6D | | | |
| 97/0 | Din[1] | LOCATED | LVCMOS33_IN | PT6C | | | |
| 98/0 | Din[2] | LOCATED | LVCMOS33_IN | PT6B | | | |
| 99/0 | Din[5] | LOCATED | LVCMOS33_IN | PT6A | | | |
| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | |
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
sysCONFIG Pins:
+----------+--------------------+--------------------+----------+-------------+-------------------+
| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode |
+----------+--------------------+--------------------+----------+-------------+-------------------+
| PT7D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP |
| PT7C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down |
| PT7B | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP |
| PT7A | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP |
+----------+--------------------+--------------------+----------+-------------+-------------------+
Dedicated sysCONFIG Pins:
List of All Pins' Locate Preferences Based on Final Placement After PAR
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste):
LOCATE COMP "Ain[0]" SITE "3";
LOCATE COMP "Ain[1]" SITE "2";
LOCATE COMP "Ain[2]" SITE "7";
LOCATE COMP "Ain[3]" SITE "4";
LOCATE COMP "Ain[4]" SITE "78";
LOCATE COMP "Ain[5]" SITE "84";
LOCATE COMP "Ain[6]" SITE "86";
LOCATE COMP "Ain[7]" SITE "8";
LOCATE COMP "BA[0]" SITE "58";
LOCATE COMP "BA[1]" SITE "60";
LOCATE COMP "C14M" SITE "62";
LOCATE COMP "CKEout" SITE "53";
LOCATE COMP "DQMH" SITE "49";
LOCATE COMP "DQML" SITE "48";
LOCATE COMP "Din[0]" SITE "96";
LOCATE COMP "Din[1]" SITE "97";
LOCATE COMP "Din[2]" SITE "98";
LOCATE COMP "Din[3]" SITE "9";
LOCATE COMP "Din[4]" SITE "1";
LOCATE COMP "Din[5]" SITE "99";
LOCATE COMP "Din[6]" SITE "88";
LOCATE COMP "Din[7]" SITE "87";
LOCATE COMP "Dout[0]" SITE "30";
LOCATE COMP "Dout[1]" SITE "27";
LOCATE COMP "Dout[2]" SITE "25";
LOCATE COMP "Dout[3]" SITE "28";
LOCATE COMP "Dout[4]" SITE "24";
LOCATE COMP "Dout[5]" SITE "21";
LOCATE COMP "Dout[6]" SITE "31";
LOCATE COMP "Dout[7]" SITE "32";
LOCATE COMP "LED" SITE "35";
LOCATE COMP "PHI1" SITE "85";
LOCATE COMP "RAout[0]" SITE "66";
LOCATE COMP "RAout[10]" SITE "64";
LOCATE COMP "RAout[11]" SITE "59";
LOCATE COMP "RAout[1]" SITE "68";
LOCATE COMP "RAout[2]" SITE "70";
LOCATE COMP "RAout[3]" SITE "74";
LOCATE COMP "RAout[4]" SITE "75";
LOCATE COMP "RAout[5]" SITE "71";
LOCATE COMP "RAout[6]" SITE "69";
LOCATE COMP "RAout[7]" SITE "67";
LOCATE COMP "RAout[8]" SITE "65";
LOCATE COMP "RAout[9]" SITE "63";
LOCATE COMP "RD[0]" SITE "36";
LOCATE COMP "RD[1]" SITE "37";
LOCATE COMP "RD[2]" SITE "38";
LOCATE COMP "RD[3]" SITE "39";
LOCATE COMP "RD[4]" SITE "40";
LOCATE COMP "RD[5]" SITE "41";
LOCATE COMP "RD[6]" SITE "42";
LOCATE COMP "RD[7]" SITE "43";
LOCATE COMP "Vout[0]" SITE "18";
LOCATE COMP "Vout[1]" SITE "15";
LOCATE COMP "Vout[2]" SITE "17";
LOCATE COMP "Vout[3]" SITE "13";
LOCATE COMP "Vout[4]" SITE "19";
LOCATE COMP "Vout[5]" SITE "16";
LOCATE COMP "Vout[6]" SITE "14";
LOCATE COMP "Vout[7]" SITE "12";
LOCATE COMP "nC07X" SITE "34";
LOCATE COMP "nCASout" SITE "52";
LOCATE COMP "nCSout" SITE "57";
LOCATE COMP "nDHGROE" SITE "47";
LOCATE COMP "nDOE" SITE "20";
LOCATE COMP "nEN80" SITE "82";
LOCATE COMP "nRASout" SITE "54";
LOCATE COMP "nRWEout" SITE "51";
LOCATE COMP "nVOE" SITE "10";
LOCATE COMP "nWE" SITE "29";
PAR: Place And Route Diamond (64-bit) 3.11.3.469.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Fri Jun 07 20:50:12 2024
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<PRE><A name="Par"></A>PAR: Place And Route Diamond (64-bit) 3.11.3.469.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&amp;T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Fri Jun 07 20:49:59 2024
C:/lscc/diamond/3.11_x64/ispfpga\bin\nt64\par -f RAM2E_LCMXO2_640HC_impl1.p2t
RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.dir
RAM2E_LCMXO2_640HC_impl1.prf -gui
Preference file: RAM2E_LCMXO2_640HC_impl1.prf.
<A name="par_cts"></A><B><U><big>Cost Table Summary</big></U></B>
Level/ Number Worst Timing Worst Timing Run NCD
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
---------- -------- ----- ------ ----------- ----------- ---- ------
5_1 * 0 56.334 0 0.379 0 16 Completed
* : Design saved.
Total (real) run time for 1-seed: 16 secs
par done!
Note: user must run &apos;Trace&apos; for timing closure signoff.
Lattice Place and Route Report for Design &quot;RAM2E_LCMXO2_640HC_impl1_map.ncd&quot;
Fri Jun 07 20:49:59 2024
<A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
PAR: Place And Route Diamond (64-bit) 3.11.3.469.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2E_LCMXO2_640HC_impl1.prf
Preference file: RAM2E_LCMXO2_640HC_impl1.prf.
Placement level-cost: 5-1.
Routing Iterations: 6
Loading design for application par from file RAM2E_LCMXO2_640HC_impl1_map.ncd.
Design name: RAM2E
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-640HC
Package: TQFP100
Performance: 4
Loading device for application par from file &apos;xo2c640.nph&apos; in environment: C:/lscc/diamond/3.11_x64/ispfpga.
Package Status: Final Version 1.39.
Performance Hardware Data Status: Final Version 34.4.
License checked out.
Ignore Preference Error(s): True
<A name="par_dus"></A><B><U><big>Device utilization summary:</big></U></B>
PIO (prelim) 70+4(JTAG)/80 93% used
70+4(JTAG)/79 94% bonded
IOLOGIC 22/80 27% used
SLICE 148/320 46% used
EFB 1/1 100% used
Number of Signals: 465
Number of Connections: 1330
Pin Constraint Summary:
70 out of 70 pins locked (100% locked).
The following 1 signal is selected to use the primary clock routing resources:
C14M_c (driver: C14M, clk load #: 85)
WARNING - par: Signal &quot;C14M_c&quot; is selected to use Primary clock resources. However, its driver comp &quot;C14M&quot; is located at &quot;62&quot;, which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
The following 1 signal is selected to use the secondary clock routing resources:
RWBank14 (driver: ram2e_ufm/SLICE_82, clk load #: 0, sr load #: 0, ce load #: 11)
No signal is selected as Global Set/Reset.
Starting Placer Phase 0.
............
Finished Placer Phase 0. REAL time: 2 secs
Starting Placer Phase 1.
.....................
Placer score = 71540.
Finished Placer Phase 1. REAL time: 9 secs
Starting Placer Phase 2.
.
Placer score = 70933
Finished Placer Phase 2. REAL time: 9 secs
<A name="par_clk"></A><B><U><big>Clock Report</big></U></B>
Global Clock Resources:
CLK_PIN : 0 out of 8 (0%)
General PIO: 1 out of 80 (1%)
DCM : 0 out of 2 (0%)
DCC : 0 out of 8 (0%)
Global Clocks:
PRIMARY &quot;C14M_c&quot; from comp &quot;C14M&quot; on PIO site &quot;62 (PR5D)&quot;, clk load = 85
SECONDARY &quot;RWBank14&quot; from F0 on comp &quot;ram2e_ufm/SLICE_82&quot; on site &quot;R2C9D&quot;, clk load = 0, ce load = 11, sr load = 0
PRIMARY : 1 out of 8 (12%)
SECONDARY: 1 out of 8 (12%)
I/O Usage Summary (final):
70 + 4(JTAG) out of 80 (92.5%) PIO sites used.
70 + 4(JTAG) out of 79 (93.7%) bonded PIO sites used.
Number of PIO comps: 70; differential: 0.
Number of Vref pins used: 0.
I/O Bank Usage Summary:
+----------+----------------+------------+-----------+
| I/O Bank | Usage | Bank Vccio | Bank Vref |
+----------+----------------+------------+-----------+
| 0 | 11 / 19 ( 57%) | 3.3V | - |
| 1 | 20 / 20 (100%) | 3.3V | - |
| 2 | 19 / 20 ( 95%) | 3.3V | - |
| 3 | 20 / 20 (100%) | 3.3V | - |
+----------+----------------+------------+-----------+
Total placer CPU time: 8 secs
Dumping design to file RAM2E_LCMXO2_640HC_impl1.dir/5_1.ncd.
0 connections routed; 1330 unrouted.
Starting router resource preassignment
WARNING - par: The driver of primary clock net C14M_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
Signal=PHI1_c loads=5 clock_loads=3
Completed router resource preassignment. Real time: 14 secs
Start NBR router at 20:50:13 06/07/24
*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
in the earlier iterations. In each iteration, it tries to
solve the conflicts while keeping the critical connections
routed as short as possible. The routing process is said to
be completed when no conflicts exist and all connections
are routed.
Note: NBR uses a different method to calculate timing slacks. The
worst slack and total negative slack may not be the same as
that in TRCE report. You should always run TRCE to verify
your design.
*****************************************************************
Start NBR special constraint process at 20:50:13 06/07/24
Start NBR section for initial routing at 20:50:13 06/07/24
Level 4, iteration 1
17(0.04%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 56.334ns/0.000ns; real time: 15 secs
Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area at 75% usage is 0 (0.00%)
Start NBR section for normal routing at 20:50:14 06/07/24
Level 4, iteration 1
7(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 56.334ns/0.000ns; real time: 15 secs
Level 4, iteration 2
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 56.334ns/0.000ns; real time: 15 secs
Start NBR section for setup/hold timing optimization with effort level 3 at 20:50:14 06/07/24
Start NBR section for re-routing at 20:50:14 06/07/24
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 56.334ns/0.000ns; real time: 15 secs
Start NBR section for post-routing at 20:50:14 06/07/24
End NBR router with 0 unrouted connection
NBR Summary
-----------
Number of unrouted connections : 0 (0.00%)
Number of connections with timing violations : 0 (0.00%)
Estimated worst slack&lt;setup&gt; : 56.334ns
Timing score&lt;setup&gt; : 0
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
Signal=PHI1_c loads=5 clock_loads=3
Total CPU time 13 secs
Total REAL time: 16 secs
Completely routed.
End of route. 1330 routed (100.00%); 0 unrouted.
Hold time timing score: 0, hold timing errors: 0
Timing score: 0
Dumping design to file RAM2E_LCMXO2_640HC_impl1.dir/5_1.ncd.
All signals are completely routed.
PAR_SUMMARY::Run status = Completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst slack&lt;setup/&lt;ns&gt;&gt; = 56.334
PAR_SUMMARY::Timing score&lt;setup/&lt;ns&gt;&gt; = 0.000
PAR_SUMMARY::Worst slack&lt;hold /&lt;ns&gt;&gt; = 0.379
PAR_SUMMARY::Timing score&lt;hold /&lt;ns&gt;&gt; = 0.000
PAR_SUMMARY::Number of errors = 0
Total CPU time to completion: 13 secs
Total REAL time to completion: 16 secs
par done!
Note: user must run &apos;Trace&apos; for timing closure signoff.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&amp;T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
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55
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Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
# Written on Fri Jun 7 20:49:53 2024
##### FILES SYNTAX CHECKED ##############################################
Constraint File(s): "\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc"
#Run constraint checker to find more issues with constraints.
#########################################################################
No issues found in constraint syntax.
Clock Summary
*************
Start Requested Requested Clock Clock Clock
Level Clock Frequency Period Type Group Load
-----------------------------------------------------------------------------------------------
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 121
0 - System 100.0 MHz 10.000 system system_clkgroup 0
0 - RAM2E|PHI1 100.0 MHz 10.000 inferred Inferred_clkgroup_0 9
===============================================================================================
Clock Load Summary
******************
Clock Source Clock Pin Non-clock Pin Non-clock Pin
Clock Load Pin Seq Example Seq Example Comb Example
--------------------------------------------------------------------------------------------
C14M 121 C14M(port) RAT.C - un1_C14M.I[0](inv)
System 0 - - - -
RAM2E|PHI1 9 PHI1(port) RefReq.C S[0].D[0] un1_PHI1.I[0](inv)
============================================================================================

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<PRE><TABLE border=1 width=100% cellspacing=0 cellpadding=2><small>
<TR>
<TD align='center' BGCOLOR='#000099' COLSPAN='4'><SPAN style="COLOR: #FFFFFF"><B>RAM2E_LCMXO2_640HC project summary</B></SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Module Name:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">RAM2E_LCMXO2_640HC</SPAN></TD>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Synthesis:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">SynplifyPro</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Name:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">impl1</SPAN></TD>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Strategy Name:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">Strategy1</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Last Process:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">JEDEC File</SPAN></TD>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">State:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">Passed</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Target Device:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">LCMXO2-640HC-4TG100C</SPAN></TD>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Device Family:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">MachXO2</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Device Type:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">LCMXO2-640HC</SPAN></TD>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Package Type:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">TQFP100</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Performance grade:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">4</SPAN></TD>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Operating conditions:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">COM</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Logic preference file:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">RAM2E-LCMXO2.lpf</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Physical Preference file:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">impl1/RAM2E_LCMXO2_640HC_impl1.prf</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Product Version:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">3.11.3.469</SPAN></TD>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Patch Version:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000"></SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Updated:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2024/06/07 20:50:21</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Location:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC-NODHGR/impl1</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Project File:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC-NODHGR/RAM2E_LCMXO2_640HC.ldf</SPAN></TD>
</TR>
</small></TABLE>
<BR>
<BR>
<BR>
<BR>
<BR>
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<PRE><A name="Syn"></A><B><U><big>Synthesis Report</big></U></B>
#Build: Synplify Pro (R) N-2018.03L-SP1-1, Build 443R, Apr 1 2019
#install: C:\lscc\diamond\3.11_x64\synpbase
#OS: Windows 8 6.2
#Hostname: ZANEMACWIN11
# Fri Jun 7 20:49:50 2024
#Implementation: impl1
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys HDL Compiler, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Verilog Compiler, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v" (library work)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\pmi_def.v" (library work)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v" (library work)
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v" (library work)
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC-NODHGR\REFB.v" (library work)
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\DHGR-OFF.v" (library work)
Verilog syntax check successful!
Selecting top level module RAM2E
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
Running optimization stage 1 on VHI .......
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
Running optimization stage 1 on VLO .......
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
Running optimization stage 1 on EFB .......
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC-NODHGR\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
Running optimization stage 1 on REFB .......
@W: CL318 :"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC-NODHGR\REFB.v":9:14:9:21|*Output wb_dat_o has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output.
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v":1:7:1:15|Synthesizing module RAM2E_UFM in library work.
Running optimization stage 1 on RAM2E_UFM .......
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\DHGR-OFF.v":1:7:1:10|Synthesizing module DHGR in library work.
Running optimization stage 1 on DHGR .......
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v":1:7:1:11|Synthesizing module RAM2E in library work.
Running optimization stage 1 on RAM2E .......
Running optimization stage 2 on RAM2E .......
@N: CL159 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v":11:15:11:19|Input nWE80 is unused.
Running optimization stage 2 on DHGR .......
Running optimization stage 2 on RAM2E_UFM .......
Running optimization stage 2 on REFB .......
Running optimization stage 2 on EFB .......
Running optimization stage 2 on VLO .......
Running optimization stage 2 on VHI .......
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Fri Jun 7 20:49:51 2024
###########################################################]
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Fri Jun 7 20:49:51 2024
###########################################################]
For a summary of runtime and memory usage for all design units, please see file:
==========================================================
@L: A:\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC-NODHGR\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_comp.rt.csv
@END
At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Fri Jun 7 20:49:51 2024
###########################################################]
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Database state : \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC-NODHGR\impl1\synwork\|impl1
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Fri Jun 7 20:49:52 2024
###########################################################]
Premap Report
# Fri Jun 7 20:49:53 2024
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Lattice Technology Pre-mapping, Version maplat2018q2p1, Build 055R, Built Apr 3 2019 09:51:54
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
Reading constraint file: \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
@N: MF284 |Setting synthesis effort to medium for the design
@L: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC-NODHGR\impl1\RAM2E_LCMXO2_640HC_impl1_scck.rpt
Printing clock summary report in "\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC-NODHGR\impl1\RAM2E_LCMXO2_640HC_impl1_scck.rpt" file
@N: MF916 |Option synthesis_strategy=base is enabled.
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB)
@N: MF284 |Setting synthesis effort to medium for the design
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":21:4:21:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
@N: MH105 |UMR3 is only supported for HAPS-80.
@N: MH105 |UMR3 is only supported for HAPS-80.
@N: BN115 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":140:9:140:12|Removing instance dhgr (in view: work.RAM2E(verilog)) of type view:work.DHGR(verilog) because it does not drive other instances.
syn_allowed_resources : blockrams=2 set on top level netlist RAM2E
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
Clock Summary
******************
Start Requested Requested Clock Clock Clock
Level Clock Frequency Period Type Group Load
-----------------------------------------------------------------------------------------------
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 121
0 - System 100.0 MHz 10.000 system system_clkgroup 0
0 - RAM2E|PHI1 100.0 MHz 10.000 inferred Inferred_clkgroup_0 9
===============================================================================================
Clock Load Summary
***********************
Clock Source Clock Pin Non-clock Pin Non-clock Pin
Clock Load Pin Seq Example Seq Example Comb Example
--------------------------------------------------------------------------------------------
C14M 121 C14M(port) RAT.C - un1_C14M.I[0](inv)
System 0 - - - -
RAM2E|PHI1 9 PHI1(port) RefReq.C S[0].D[0] un1_PHI1.I[0](inv)
============================================================================================
@W: MT529 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":20:19:20:24|Found inferred clock RAM2E|PHI1 which controls 9 sequential elements including PHI1r. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed: 0
@S |Clock Optimization Summary
#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
2 non-gated/non-generated clock tree(s) driving 125 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
---------------------------------------------------------------------------------------
@KP:ckid0_0 C14M port 121 PHI1r
@KP:ckid0_1 PHI1 Unconstrained_port 4 RC[2:0]
=======================================================================================
##### END OF CLOCK OPTIMIZATION REPORT ######
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
Finished Pre Mapping Phase.
Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
None
None
Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
Pre-mapping successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Jun 7 20:49:53 2024
###########################################################]
Map & Optimize Report
# Fri Jun 7 20:49:53 2024
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Lattice Technology Mapper, Version maplat2018q2p1, Build 055R, Built Apr 3 2019 09:51:54
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
@N: MF284 |Setting synthesis effort to medium for the design
@N: MF916 |Option synthesis_strategy=base is enabled.
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
@N: MF284 |Setting synthesis effort to medium for the design
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
Available hyper_sources - for debug and ip models
None Found
@N: FX493 |Applying initial value "00000000" on instance RWBank[7:0].
@N: FX493 |Applying initial value "0000" on instance S[3:0].
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)
@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":14:23:14:28|Found counter in view:work.RAM2E(verilog) instance FS[15:0]
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 142MB)
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:01s 6.90ns 281 / 125
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":171:4:171:9|Boundary register BA_1_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":171:4:171:9|Boundary register BA_0_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 158MB peak: 160MB)
Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 122MB peak: 160MB)
Writing Analyst data base \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC-NODHGR\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_m.srm
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 158MB peak: 160MB)
Writing EDIF Netlist and constraint files
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC-NODHGR\impl1\RAM2E_LCMXO2_640HC_impl1.edi
N-2018.03L-SP1-1
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 162MB peak: 164MB)
Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 161MB peak: 164MB)
@W: MT246 :"\\mac\icloud\repos\ram2e\cpld\lcmxo2-640hc-nodhgr\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@N: MT615 |Found clock C14M with period 69.84ns
@W: MT420 |Found inferred clock RAM2E|PHI1 with period 10.00ns. Please declare a user-defined clock on port PHI1.
##### START OF TIMING REPORT #####[
# Timing Report written on Fri Jun 7 20:49:57 2024
#
Top view: RAM2E
Requested Frequency: 14.3 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s): \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
Performance Summary
*******************
Worst slack in design: 6.897
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
----------------------------------------------------------------------------------------------------------------------
C14M 14.3 MHz 112.1 MHz 69.841 8.918 31.599 declared default_clkgroup
RAM2E|PHI1 100.0 MHz 322.2 MHz 10.000 3.103 6.897 inferred Inferred_clkgroup_0
System 100.0 MHz NA 10.000 NA 67.088 system system_clkgroup
======================================================================================================================
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
----------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
----------------------------------------------------------------------------------------------------------------
System C14M | 69.841 67.088 | No paths - | No paths - | No paths -
C14M System | 69.841 68.797 | No paths - | No paths - | No paths -
C14M C14M | 69.841 60.923 | No paths - | 34.920 31.599 | No paths -
RAM2E|PHI1 C14M | No paths - | No paths - | No paths - | Diff grp -
RAM2E|PHI1 RAM2E|PHI1 | No paths - | 10.000 6.897 | No paths - | No paths -
================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Interface Information
*********************
No IO constraint found
====================================
Detailed Report for Clock: C14M
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------
S[2] C14M FD1S3AX Q S[2] 1.366 31.599
S[3] C14M FD1S3AX Q S[3] 1.345 31.619
S[1] C14M FD1S3AX Q S[1] 1.344 31.800
S[0] C14M FD1S3AX Q S[0] 1.305 31.838
RA[0] C14M FD1P3AX Q RA[0] 1.108 33.707
RA[3] C14M FD1P3AX Q RA[3] 1.108 33.707
RA[1] C14M FD1P3AX Q RA[1] 1.044 33.771
RA[2] C14M FD1P3AX Q RA[2] 1.044 33.771
RA[4] C14M FD1P3AX Q RA[4] 1.044 33.771
RA[5] C14M FD1P3AX Q RA[5] 1.044 33.771
===========================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
-----------------------------------------------------------------------------------
VOE_i_0io C14M OFS1P3IX CD N_530 34.118 31.599
VOE_i_0io C14M OFS1P3IX D VOE_ic_i 35.009 31.800
Vout_0io[0] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[1] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[2] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[3] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[4] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[5] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[6] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[7] C14M OFS1P3DX SP Vout3 34.449 32.634
===================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 34.920
- Setup time: 0.803
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 34.118
- Propagation time: 2.519
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : 31.599
Number of logic level(s): 1
Starting point: S[2] / Q
Ending point: VOE_i_0io / CD
The start point is clocked by C14M [rising] on pin CK
The end point is clocked by C14M [falling] on pin SCLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
------------------------------------------------------------------------------------------------------------
S[2] FD1S3AX Q Out 1.366 1.366 -
S[2] Net - - - - 58
ram2e_ufm.un1_wb_adr_0_sqmuxa_2_0_a2_0[0] ORCALUT4 A In 0.000 1.366 -
ram2e_ufm.un1_wb_adr_0_sqmuxa_2_0_a2_0[0] ORCALUT4 Z Out 1.153 2.519 -
N_530 Net - - - - 3
VOE_i_0io OFS1P3IX CD In 0.000 2.519 -
============================================================================================================
====================================
Detailed Report for Clock: RAM2E|PHI1
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------
RC[1] RAM2E|PHI1 FD1S3IX Q RC[1] 1.148 6.897
RC[2] RAM2E|PHI1 FD1S3IX Q RC[2] 1.108 6.937
RC[0] RAM2E|PHI1 FD1S3IX Q RC[0] 1.148 8.179
===========================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------
RC[0] RAM2E|PHI1 FD1S3IX CD RC7 9.197 6.897
RC[1] RAM2E|PHI1 FD1S3IX CD RC7 9.197 6.897
RC[2] RAM2E|PHI1 FD1S3IX CD RC7 9.197 6.897
RC[0] RAM2E|PHI1 FD1S3IX D RC_i[0] 9.894 8.179
RC[1] RAM2E|PHI1 FD1S3IX D RC_RNO[1] 10.089 8.324
RC[2] RAM2E|PHI1 FD1S3IX D RC_RNO[2] 10.089 8.324
RefReq RAM2E|PHI1 FD1S3AX D RefReq_2 10.089 8.324
================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 10.000
- Setup time: 0.803
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 9.197
- Propagation time: 2.301
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : 6.897
Number of logic level(s): 1
Starting point: RC[1] / Q
Ending point: RC[0] / CD
The start point is clocked by RAM2E|PHI1 [falling] on pin CK
The end point is clocked by RAM2E|PHI1 [falling] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------
RC[1] FD1S3IX Q Out 1.148 1.148 -
RC[1] Net - - - - 4
RC7 ORCALUT4 A In 0.000 1.148 -
RC7 ORCALUT4 Z Out 1.153 2.301 -
RC7 Net - - - - 3
RC[0] FD1S3IX CD In 0.000 2.301 -
=================================================================================
====================================
Detailed Report for Clock: System
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------------------------------
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBACKO wb_ack 0.000 67.088
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO0 wb_dato[0] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO2 wb_dato[2] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO3 wb_dato[3] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO4 wb_dato[4] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO5 wb_dato[5] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO6 wb_dato[6] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO7 wb_dato[7] 0.000 69.313
===================================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
----------------------------------------------------------------------------------------
ram2e_ufm.RWMask[0] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[1] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[2] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[3] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[4] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[5] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[6] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[7] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.LEDEN System FD1P3AX SP N_98 69.369 67.736
ram2e_ufm.wb_cyc_stb System FD1P3AX SP N_111 69.369 67.736
========================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 69.841
- Setup time: 0.472
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 69.369
- Propagation time: 2.282
- Clock delay at starting point: 0.000 (ideal)
- Estimated clock delay at start point: -0.000
= Slack (non-critical) : 67.088
Number of logic level(s): 2
Starting point: ram2e_ufm.ufmefb.EFBInst_0 / WBACKO
Ending point: ram2e_ufm.RWMask[0] / SP
The start point is clocked by System [rising]
The end point is clocked by C14M [rising] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
----------------------------------------------------------------------------------------------------------------
ram2e_ufm.ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 -
wb_ack Net - - - - 5
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] ORCALUT4 B In 0.000 0.000 -
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] ORCALUT4 Z Out 1.017 1.017 -
un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] Net - - - - 1
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 D In 0.000 1.017 -
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 Z Out 1.265 2.282 -
N_104 Net - - - - 8
ram2e_ufm.RWMask[0] FD1P3AX SP In 0.000 2.282 -
================================================================================================================
##### END OF TIMING REPORT #####]
Timing exceptions that could not be applied
None
Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 161MB peak: 164MB)
Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 161MB peak: 164MB)
---------------------------------------
Resource Usage Report
Part: lcmxo2_640hc-4
Register bits: 125 of 640 (20%)
PIC Latch: 0
I/O cells: 70
Details:
BB: 8
CCU2D: 9
EFB: 1
FD1P3AX: 58
FD1P3IX: 1
FD1S3AX: 31
FD1S3AY: 4
FD1S3IX: 9
GSR: 1
IB: 21
IFS1P3DX: 1
INV: 4
OB: 41
OFS1P3BX: 6
OFS1P3DX: 12
OFS1P3IX: 3
ORCALUT4: 275
PUR: 1
VHI: 3
VLO: 3
Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 32MB peak: 164MB)
Process took 0h:00m:03s realtime, 0h:00m:03s cputime
# Fri Jun 7 20:49:57 2024
###########################################################]
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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE Report>
<ReportView version="2.0">
<Implement name="impl1">
<ToolReport id="tooldec" path="" status="0"/>
<ToolReport id="toolhle_genhierarchy" path="" status="0"/>
<ToolReport id="toolpio" path="" status="0"/>
<ToolReport id="toolsso" path="" status="0"/>
</Implement>
</ReportView>

6
CPLD/LCMXO2-640HC/.setting.ini
View File

@ -1,4 +1,4 @@
[General]
PAR.auto_tasks=PARTrace, IOTiming
Map.auto_tasks=MapTrace, MapVerilogSimFile
Export.auto_tasks=IBIS, TimingSimFileVlg, Bitgen, Jedecgen
PAR.auto_tasks=@@empty()
Map.auto_tasks=@@empty()
Export.auto_tasks=Jedecgen

6
CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC.ldf
View File

@ -12,6 +12,12 @@
<Source name="REFB.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../DHGR-ON.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="impl1/impl1.xcf" type="Programming Project File" type_short="Programming">
<Options/>
</Source>
<Source name="../RAM2E-LCMXO2.lpf" type="Logic Preference" type_short="LPF">
<Options/>
</Source>

2
CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC1.sty
View File

@ -129,7 +129,6 @@
<Property name="PROP_PAR_RoutingCDP" value="0" time="0"/>
<Property name="PROP_PAR_RoutingCDR" value="0" time="0"/>
<Property name="PROP_PAR_RunParWithTrce" value="False" time="0"/>
<Property name="PROP_PAR_RunTimeReduction" value="True" time="0"/>
<Property name="PROP_PAR_SaveBestRsltParDes" value="1" time="0"/>
<Property name="PROP_PAR_StopZero" value="False" time="0"/>
<Property name="PROP_PAR_parHold" value="On" time="0"/>
@ -166,7 +165,6 @@
<Property name="PROP_PRE_VSynoutd" value="0" time="0"/>
<Property name="PROP_SYN_ClockConversion" value="True" time="0"/>
<Property name="PROP_SYN_CmdLineArgs" value="" time="0"/>
<Property name="PROP_SYN_DisableRegisterRep" value="False" time="0"/>
<Property name="PROP_SYN_EdfAllowDUPMod" value="False" time="0"/>
<Property name="PROP_SYN_EdfArea" value="False" time="0"/>
<Property name="PROP_SYN_EdfArrangeVHDLFiles" value="True" time="0"/>

78
CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.alt Normal file
View File

@ -0,0 +1,78 @@
NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
NOTE All Rights Reserved *
NOTE DATE CREATED: Fri Jun 07 20:50:29 2024 *
NOTE DESIGN NAME: RAM2E *
NOTE DEVICE NAME: LCMXO2-640HC-4TQFP100 *
NOTE PIN ASSIGNMENTS *
NOTE PINS RD[0] : 36 : inout *
NOTE PINS LED : 35 : out *
NOTE PINS C14M : 62 : in *
NOTE PINS RD[7] : 43 : inout *
NOTE PINS RD[6] : 42 : inout *
NOTE PINS RD[5] : 41 : inout *
NOTE PINS RD[4] : 40 : inout *
NOTE PINS RD[3] : 39 : inout *
NOTE PINS RD[2] : 38 : inout *
NOTE PINS RD[1] : 37 : inout *
NOTE PINS DQMH : 49 : out *
NOTE PINS DQML : 48 : out *
NOTE PINS RAout[11] : 59 : out *
NOTE PINS RAout[10] : 64 : out *
NOTE PINS RAout[9] : 63 : out *
NOTE PINS RAout[8] : 65 : out *
NOTE PINS RAout[7] : 67 : out *
NOTE PINS RAout[6] : 69 : out *
NOTE PINS RAout[5] : 71 : out *
NOTE PINS RAout[4] : 75 : out *
NOTE PINS RAout[3] : 74 : out *
NOTE PINS RAout[2] : 70 : out *
NOTE PINS RAout[1] : 68 : out *
NOTE PINS RAout[0] : 66 : out *
NOTE PINS BA[1] : 60 : out *
NOTE PINS BA[0] : 58 : out *
NOTE PINS nRWEout : 51 : out *
NOTE PINS nCASout : 52 : out *
NOTE PINS nRASout : 54 : out *
NOTE PINS nCSout : 57 : out *
NOTE PINS CKEout : 53 : out *
NOTE PINS nVOE : 10 : out *
NOTE PINS Vout[7] : 12 : out *
NOTE PINS Vout[6] : 14 : out *
NOTE PINS Vout[5] : 16 : out *
NOTE PINS Vout[4] : 19 : out *
NOTE PINS Vout[3] : 13 : out *
NOTE PINS Vout[2] : 17 : out *
NOTE PINS Vout[1] : 15 : out *
NOTE PINS Vout[0] : 18 : out *
NOTE PINS nDOE : 20 : out *
NOTE PINS Dout[7] : 32 : out *
NOTE PINS Dout[6] : 31 : out *
NOTE PINS Dout[5] : 21 : out *
NOTE PINS Dout[4] : 24 : out *
NOTE PINS Dout[3] : 28 : out *
NOTE PINS Dout[2] : 25 : out *
NOTE PINS Dout[1] : 27 : out *
NOTE PINS Dout[0] : 30 : out *
NOTE PINS Din[7] : 87 : in *
NOTE PINS Din[6] : 88 : in *
NOTE PINS Din[5] : 99 : in *
NOTE PINS Din[4] : 1 : in *
NOTE PINS Din[3] : 9 : in *
NOTE PINS Din[2] : 98 : in *
NOTE PINS Din[1] : 97 : in *
NOTE PINS Din[0] : 96 : in *
NOTE PINS Ain[7] : 8 : in *
NOTE PINS Ain[6] : 86 : in *
NOTE PINS Ain[5] : 84 : in *
NOTE PINS Ain[4] : 78 : in *
NOTE PINS Ain[3] : 4 : in *
NOTE PINS Ain[2] : 7 : in *
NOTE PINS Ain[1] : 2 : in *
NOTE PINS Ain[0] : 3 : in *
NOTE PINS nC07X : 34 : in *
NOTE PINS nEN80 : 82 : in *
NOTE PINS nWE : 29 : in *
NOTE PINS nDHGROE : 47 : out *
NOTE PINS PHI1 : 85 : in *
NOTE CONFIGURATION MODE: NONE *
NOTE COMPRESSION: on *

59
CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.areasrr Normal file
View File

@ -0,0 +1,59 @@
----------------------------------------------------------------------
Report for cell RAM2E.verilog
Register bits: 125 of 640 (20%)
PIC Latch: 0
I/O cells: 70
Cell usage:
cell count Res Usage(%)
BB 8 100.0
CCU2D 9 100.0
EFB 1 100.0
FD1P3AX 58 100.0
FD1P3IX 1 100.0
FD1S3AX 31 100.0
FD1S3AY 4 100.0
FD1S3IX 9 100.0
GSR 1 100.0
IB 21 100.0
IFS1P3DX 1 100.0
INV 4 100.0
OB 41 100.0
OFS1P3BX 6 100.0
OFS1P3DX 12 100.0
OFS1P3IX 3 100.0
ORCALUT4 275 100.0
PUR 1 100.0
VHI 3 100.0
VLO 3 100.0
SUB MODULES
RAM2E_UFM 1 100.0
REFB 1 100.0
TOTAL 494
----------------------------------------------------------------------
Report for cell RAM2E_UFM.netlist
Instance path: ram2e_ufm
Cell usage:
cell count Res Usage(%)
EFB 1 100.0
FD1P3AX 29 50.0
FD1P3IX 1 100.0
FD1S3IX 1 11.1
ORCALUT4 268 97.5
VHI 2 66.7
VLO 2 66.7
SUB MODULES
REFB 1 100.0
TOTAL 305
----------------------------------------------------------------------
Report for cell REFB.netlist
Instance path: ram2e_ufm.ufmefb
Cell usage:
cell count Res Usage(%)
EFB 1 100.0
VHI 1 33.3
VLO 1 33.3
TOTAL 3

86
CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.bgn Normal file
View File

@ -0,0 +1,86 @@
BITGEN: Bitstream Generator Diamond (64-bit) 3.11.3.469
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Fri Jun 07 20:50:26 2024
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC -w -jedec -gui RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf
Loading design for application Bitgen from file RAM2E_LCMXO2_640HC_impl1.ncd.
Design name: RAM2E
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-640HC
Package: TQFP100
Performance: 4
Loading device for application Bitgen from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.11_x64/ispfpga.
Package Status: Final Version 1.39.
Performance Hardware Data Status: Final Version 34.4.
Running DRC.
DRC detected 0 errors and 0 warnings.
Reading Preference File from RAM2E_LCMXO2_640HC_impl1.prf.
Preference Summary:
+---------------------------------+---------------------------------+
| Preference | Current Setting |
+---------------------------------+---------------------------------+
| RamCfg | Reset** |
+---------------------------------+---------------------------------+
| MCCLK_FREQ | 2.08** |
+---------------------------------+---------------------------------+
| CONFIG_SECURE | OFF** |
+---------------------------------+---------------------------------+
| INBUF | ON** |
+---------------------------------+---------------------------------+
| JTAG_PORT | ENABLE** |
+---------------------------------+---------------------------------+
| SDM_PORT | DISABLE** |
+---------------------------------+---------------------------------+
| SLAVE_SPI_PORT | DISABLE** |
+---------------------------------+---------------------------------+
| MASTER_SPI_PORT | DISABLE** |
+---------------------------------+---------------------------------+
| I2C_PORT | DISABLE** |
+---------------------------------+---------------------------------+
| MUX_CONFIGURATION_PORTS | DISABLE** |
+---------------------------------+---------------------------------+
| CONFIGURATION | CFG** |
+---------------------------------+---------------------------------+
| COMPRESS_CONFIG | ON** |
+---------------------------------+---------------------------------+
| MY_ASSP | OFF** |
+---------------------------------+---------------------------------+
| ONE_TIME_PROGRAM | OFF** |
+---------------------------------+---------------------------------+
| ENABLE_TRANSFR | DISABLE** |
+---------------------------------+---------------------------------+
| SHAREDEBRINIT | DISABLE** |
+---------------------------------+---------------------------------+
| BACKGROUND_RECONFIG | OFF** |
+---------------------------------+---------------------------------+
* Default setting.
** The specified setting matches the default setting.
Creating bit map...
Bitstream Status: Final Version 1.95.
Saving bit stream in "RAM2E_LCMXO2_640HC_impl1.jed".
===========
UFM Summary.
===========
UFM Size: 191 Pages (128*191 Bits).
UFM Utilization: General Purpose Flash Memory.
Available General Purpose Flash Memory: 191 Pages (Page 0 to Page 190).
Initialized UFM Pages: 1 Page (Page 190).
Total CPU Time: 3 secs
Total REAL Time: 3 secs
Peak Memory Usage: 267 MB

5967
CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.edi Normal file
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File diff suppressed because it is too large Load Diff

1441
CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.jed Normal file
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File diff suppressed because it is too large Load Diff

468
CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.mrp Normal file
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@ -0,0 +1,468 @@
Lattice Mapping Report File for Design Module 'RAM2E'
Design Information
------------------
Command line: map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial
RAM2E_LCMXO2_640HC_impl1.ngd -o RAM2E_LCMXO2_640HC_impl1_map.ncd -pr
RAM2E_LCMXO2_640HC_impl1.prf -mp RAM2E_LCMXO2_640HC_impl1.mrp -lpf //Mac/iC
loud/Repos/RAM2E/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_synplify.
lpf -lpf //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf -c 0 -gui
Target Vendor: LATTICE
Target Device: LCMXO2-640HCTQFP100
Target Performance: 4
Mapper: xo2c00, version: Diamond (64-bit) 3.11.3.469
Mapped on: 06/07/24 20:50:09
Design Summary
--------------
Number of registers: 125 out of 877 (14%)
PFU registers: 103 out of 640 (16%)
PIO registers: 22 out of 237 (9%)
Number of SLICEs: 148 out of 320 (46%)
SLICEs as Logic/ROM: 148 out of 320 (46%)
SLICEs as RAM: 0 out of 240 (0%)
SLICEs as Carry: 9 out of 320 (3%)
Number of LUT4s: 295 out of 640 (46%)
Number used as logic LUTs: 277
Number used as distributed RAM: 0
Number used as ripple logic: 18
Number used as shift registers: 0
Number of PIO sites used: 70 + 4(JTAG) out of 79 (94%)
Number of block RAMs: 0 out of 2 (0%)
Number of GSRs: 0 out of 1 (0%)
EFB used : Yes
JTAG used : No
Readback used : No
Oscillator used : No
Startup used : No
POR : On
Bandgap : On
Number of Power Controller: 0 out of 1 (0%)
Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
Number of DCCA: 0 out of 8 (0%)
Number of DCMA: 0 out of 2 (0%)
Notes:-
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
distributed RAMs) + 2*(Number of ripple logic)
2. Number of logic LUT4s does not include count of distributed RAM and
ripple logic.
Number of clocks: 2
Net C14M_c: 85 loads, 63 rising, 22 falling (Driver: PIO C14M )
Net PHI1_c: 3 loads, 0 rising, 3 falling (Driver: PIO PHI1 )
Number of Clock Enables: 13
Net N_117_i: 2 loads, 0 LSLICEs
Net RWBank14: 11 loads, 11 LSLICEs
Net ram2e_ufm/wb_adr_0_sqmuxa_1_i: 1 loads, 1 LSLICEs
Net un9_VOE_0_a2_0_a2: 1 loads, 1 LSLICEs
Net un6_DOEEN_0_a2_0_a2: 2 loads, 2 LSLICEs
Net ram2e_ufm/un1_wb_adr_0_sqmuxa_2_i[0]: 8 loads, 8 LSLICEs
Page 1
Design: RAM2E Date: 06/07/24 20:50:09
Design Summary (cont)
---------------------
Net ram2e_ufm/un1_wb_cyc_stb_0_sqmuxa_1_i[0]: 1 loads, 1 LSLICEs
Net ram2e_ufm/N_111: 1 loads, 1 LSLICEs
Net ram2e_ufm/N_104: 4 loads, 4 LSLICEs
Net ram2e_ufm/N_98: 1 loads, 1 LSLICEs
Net un1_CKE48_0_i: 6 loads, 6 LSLICEs
Net N_389_i: 2 loads, 0 LSLICEs
Net Vout3: 8 loads, 0 LSLICEs
Number of LSRs: 8
Net N_148: 2 loads, 2 LSLICEs
Net N_430_i: 2 loads, 0 LSLICEs
Net RC7: 2 loads, 2 LSLICEs
Net S[2]: 2 loads, 2 LSLICEs
Net ram2e_ufm/wb_rst: 1 loads, 0 LSLICEs
Net ram2e_ufm/nRWE_0_i_o3_RNIP8E61: 1 loads, 1 LSLICEs
Net N_530: 1 loads, 0 LSLICEs
Net N_301_i: 1 loads, 1 LSLICEs
Number of nets driven by tri-state buffers: 0
Top 10 highest fanout non-clock nets:
Net S[2]: 60 loads
Net S[3]: 48 loads
Net S[1]: 46 loads
Net S[0]: 31 loads
Net FS[11]: 24 loads
Net FS[10]: 23 loads
Net FS[12]: 23 loads
Net FS[9]: 23 loads
Net FS[13]: 21 loads
Net FS[8]: 18 loads
Number of warnings: 3
Number of errors: 0
Design Errors/Warnings
----------------------
WARNING - map: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf(94): Semantic
error in "IOBUF PORT "nWE80" IO_TYPE=LVCMOS33 PULLMODE=NONE ;": Port
"nWE80" does not exist in the design. This preference has been disabled.
WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
temporarily disable certain features of the device including Power
Controller, GSR, Hardened User SPI Port, Hardened Primary User I2C Port.
Functionality is restored after the Flash Memory (UFM/Configuration)
Interface is disabled using Disable Configuration Interface command 0x26
followed by Bypass command 0xFF.
WARNING - map: IO buffer missing for top level port nWE80...logic will be
discarded.
IO (PIO) Attributes
-------------------
+---------------------+-----------+-----------+------------+
| IO Name | Direction | Levelmode | IO |
Page 2
Design: RAM2E Date: 06/07/24 20:50:09
IO (PIO) Attributes (cont)
--------------------------
| | | IO_TYPE | Register |
+---------------------+-----------+-----------+------------+
| RD[0] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| LED | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| C14M | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[7] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[6] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[5] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[4] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[3] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[2] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[1] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| DQMH | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| DQML | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RAout[11] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RAout[10] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RAout[9] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RAout[8] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RAout[7] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[6] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[5] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[4] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[3] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[2] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[1] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[0] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| BA[1] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| BA[0] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nRWEout | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
Page 3
Design: RAM2E Date: 06/07/24 20:50:09
IO (PIO) Attributes (cont)
--------------------------
| nCASout | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nRASout | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nCSout | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| CKEout | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nVOE | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[7] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[6] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[5] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[4] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[3] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[2] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[1] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[0] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nDOE | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[7] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[6] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[5] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[4] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[3] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[2] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[1] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[0] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[7] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[6] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[5] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[4] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[3] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[2] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
Page 4
Design: RAM2E Date: 06/07/24 20:50:09
IO (PIO) Attributes (cont)
--------------------------
| Din[1] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[0] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[7] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[6] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[5] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[4] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[3] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[2] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[1] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[0] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nC07X | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nEN80 | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nWE | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nDHGROE | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| PHI1 | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
Removed logic
-------------
Block GSR_INST undriven or does not drive anything - clipped.
Block ram2e_ufm/VCC undriven or does not drive anything - clipped.
Block ram2e_ufm/GND undriven or does not drive anything - clipped.
Signal RC_0_.CN was merged into signal PHI1_c
Signal RDOE_i was merged into signal RDOE
Signal RAT.CN was merged into signal C14M_c
Signal ram2e_ufm/ufmefb/VCC undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/GND undriven or does not drive anything - clipped.
Signal FS_s_0_S1[15] undriven or does not drive anything - clipped.
Signal FS_s_0_COUT[15] undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/CFGWAKE undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/wbc_ufm_irq undriven or does not drive anything -
clipped.
Signal ram2e_ufm/ufmefb/TCOC undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/TCINT undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIIRQO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPICSNEN undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
Page 5
Design: RAM2E Date: 06/07/24 20:50:09
Removed logic (cont)
--------------------
Signal ram2e_ufm/ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMOSIEN undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMOSIO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMISOEN undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMISOO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPISCKEN undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPISCKO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C2SDAOEN undriven or does not drive anything -
clipped.
Signal ram2e_ufm/ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C2SCLOEN undriven or does not drive anything -
clipped.
Signal ram2e_ufm/ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C1SDAOEN undriven or does not drive anything -
clipped.
Signal ram2e_ufm/ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C1SCLOEN undriven or does not drive anything -
clipped.
Signal ram2e_ufm/ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLADRO4 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLWEO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLL1STBO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLL0STBO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLRSTO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLCLKO undriven or does not drive anything - clipped.
Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped.
Signal N_1 undriven or does not drive anything - clipped.
Block RefReq.CN was optimized away.
Block RDOE_RNIAM8C was optimized away.
Block nCASout.CN was optimized away.
Block ram2e_ufm/ufmefb/VCC was optimized away.
Block ram2e_ufm/ufmefb/GND was optimized away.
Page 6
Design: RAM2E Date: 06/07/24 20:50:09
Embedded Functional Block Connection Summary
--------------------------------------------
Desired WISHBONE clock frequency: 14.4 MHz
Clock source: C14M_c
Reset source: ram2e_ufm/wb_rst
Functions mode:
I2C #1 (Primary) Function: DISABLED
I2C #2 (Secondary) Function: DISABLED
SPI Function: DISABLED
Timer/Counter Function: DISABLED
Timer/Counter Mode: WB
UFM Connection: ENABLED
PLL0 Connection: DISABLED
PLL1 Connection: DISABLED
I2C Function Summary:
--------------------
None
SPI Function Summary:
--------------------
None
Timer/Counter Function Summary:
------------------------------
None
UFM Function Summary:
--------------------
UFM Utilization: General Purpose Flash Memory
Initialized UFM Pages: 1 Pages (1*128 Bits)
Available General
Purpose Flash Memory: 191 Pages (191*128 Bits)
EBR Blocks with Unique
Initialization Data: 0
WID EBR Instance
--- ------------
ASIC Components
---------------
Instance Name: ram2e_ufm/ufmefb/EFBInst_0
Type: EFB
Run Time and Memory Usage
-------------------------
Total CPU Time: 0 secs
Total REAL Time: 0 secs
Peak Memory Usage: 59 MB
Page 7
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights
reserved.

287
CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.pad Normal file
View File

@ -0,0 +1,287 @@
PAD Specification File
***************************
PART TYPE: LCMXO2-640HC
Performance Grade: 4
PACKAGE: TQFP100
Package Status: Final Version 1.39
Fri Jun 07 20:50:19 2024
Pinout by Port Name:
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties |
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
| Ain[0] | 3/3 | LVCMOS33_IN | PL2C | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[1] | 2/3 | LVCMOS33_IN | PL2B | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[2] | 7/3 | LVCMOS33_IN | PL3A | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[3] | 4/3 | LVCMOS33_IN | PL2D | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[4] | 78/0 | LVCMOS33_IN | PT11A | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[5] | 84/0 | LVCMOS33_IN | PT10A | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[6] | 86/0 | LVCMOS33_IN | PT9C | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[7] | 8/3 | LVCMOS33_IN | PL3B | | | CLAMP:ON HYSTERESIS:SMALL |
| BA[0] | 58/1 | LVCMOS33_OUT | PR6C | | | DRIVE:4mA SLEW:SLOW |
| BA[1] | 60/1 | LVCMOS33_OUT | PR6A | | | DRIVE:4mA SLEW:SLOW |
| C14M | 62/1 | LVCMOS33_IN | PR5D | | | CLAMP:ON HYSTERESIS:SMALL |
| CKEout | 53/1 | LVCMOS33_OUT | PR7B | | | DRIVE:4mA SLEW:SLOW |
| DQMH | 49/2 | LVCMOS33_OUT | PB14D | | | DRIVE:4mA SLEW:SLOW |
| DQML | 48/2 | LVCMOS33_OUT | PB14C | | | DRIVE:4mA SLEW:SLOW |
| Din[0] | 96/0 | LVCMOS33_IN | PT6D | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[1] | 97/0 | LVCMOS33_IN | PT6C | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[2] | 98/0 | LVCMOS33_IN | PT6B | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[3] | 9/3 | LVCMOS33_IN | PL3C | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[4] | 1/3 | LVCMOS33_IN | PL2A | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[5] | 99/0 | LVCMOS33_IN | PT6A | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[6] | 88/0 | LVCMOS33_IN | PT9A | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[7] | 87/0 | LVCMOS33_IN | PT9B | | | CLAMP:ON HYSTERESIS:SMALL |
| Dout[0] | 30/2 | LVCMOS33_OUT | PB4D | | | DRIVE:4mA SLEW:SLOW |
| Dout[1] | 27/2 | LVCMOS33_OUT | PB4A | | | DRIVE:4mA SLEW:SLOW |
| Dout[2] | 25/3 | LVCMOS33_OUT | PL7D | | | DRIVE:4mA SLEW:SLOW |
| Dout[3] | 28/2 | LVCMOS33_OUT | PB4B | | | DRIVE:4mA SLEW:SLOW |
| Dout[4] | 24/3 | LVCMOS33_OUT | PL7C | | | DRIVE:4mA SLEW:SLOW |
| Dout[5] | 21/3 | LVCMOS33_OUT | PL7B | | | DRIVE:4mA SLEW:SLOW |
| Dout[6] | 31/2 | LVCMOS33_OUT | PB6A | | | DRIVE:4mA SLEW:SLOW |
| Dout[7] | 32/2 | LVCMOS33_OUT | PB6B | | | DRIVE:4mA SLEW:SLOW |
| LED | 35/2 | LVCMOS33_OUT | PB6D | | | DRIVE:4mA SLEW:SLOW |
| PHI1 | 85/0 | LVCMOS33_IN | PT9D | | | CLAMP:ON HYSTERESIS:SMALL |
| RAout[0] | 66/1 | LVCMOS33_OUT | PR3D | | | DRIVE:4mA SLEW:SLOW |
| RAout[10] | 64/1 | LVCMOS33_OUT | PR5B | | | DRIVE:4mA SLEW:SLOW |
| RAout[11] | 59/1 | LVCMOS33_OUT | PR6B | | | DRIVE:4mA SLEW:SLOW |
| RAout[1] | 68/1 | LVCMOS33_OUT | PR3B | | | DRIVE:4mA SLEW:SLOW |
| RAout[2] | 70/1 | LVCMOS33_OUT | PR2D | | | DRIVE:4mA SLEW:SLOW |
| RAout[3] | 74/1 | LVCMOS33_OUT | PR2B | | | DRIVE:4mA SLEW:SLOW |
| RAout[4] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA SLEW:SLOW |
| RAout[5] | 71/1 | LVCMOS33_OUT | PR2C | | | DRIVE:4mA SLEW:SLOW |
| RAout[6] | 69/1 | LVCMOS33_OUT | PR3A | | | DRIVE:4mA SLEW:SLOW |
| RAout[7] | 67/1 | LVCMOS33_OUT | PR3C | | | DRIVE:4mA SLEW:SLOW |
| RAout[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA SLEW:SLOW |
| RAout[9] | 63/1 | LVCMOS33_OUT | PR5C | | | DRIVE:4mA SLEW:SLOW |
| RD[0] | 36/2 | LVCMOS33_BIDI | PB10A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[1] | 37/2 | LVCMOS33_BIDI | PB10B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[2] | 38/2 | LVCMOS33_BIDI | PB10C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[3] | 39/2 | LVCMOS33_BIDI | PB10D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[4] | 40/2 | LVCMOS33_BIDI | PB12A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[5] | 41/2 | LVCMOS33_BIDI | PB12B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[6] | 42/2 | LVCMOS33_BIDI | PB12C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[7] | 43/2 | LVCMOS33_BIDI | PB12D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| Vout[0] | 18/3 | LVCMOS33_OUT | PL6C | | | DRIVE:4mA SLEW:SLOW |
| Vout[1] | 15/3 | LVCMOS33_OUT | PL5D | | | DRIVE:4mA SLEW:SLOW |
| Vout[2] | 17/3 | LVCMOS33_OUT | PL6B | | | DRIVE:4mA SLEW:SLOW |
| Vout[3] | 13/3 | LVCMOS33_OUT | PL5B | | | DRIVE:4mA SLEW:SLOW |
| Vout[4] | 19/3 | LVCMOS33_OUT | PL6D | | | DRIVE:4mA SLEW:SLOW |
| Vout[5] | 16/3 | LVCMOS33_OUT | PL6A | | | DRIVE:4mA SLEW:SLOW |
| Vout[6] | 14/3 | LVCMOS33_OUT | PL5C | | | DRIVE:4mA SLEW:SLOW |
| Vout[7] | 12/3 | LVCMOS33_OUT | PL5A | | | DRIVE:4mA SLEW:SLOW |
| nC07X | 34/2 | LVCMOS33_IN | PB6C | | | CLAMP:ON HYSTERESIS:SMALL |
| nCASout | 52/1 | LVCMOS33_OUT | PR7C | | | DRIVE:4mA SLEW:SLOW |
| nCSout | 57/1 | LVCMOS33_OUT | PR6D | | | DRIVE:4mA SLEW:SLOW |
| nDHGROE | 47/2 | LVCMOS33_OUT | PB14B | | | DRIVE:4mA SLEW:SLOW |
| nDOE | 20/3 | LVCMOS33_OUT | PL7A | | | DRIVE:4mA SLEW:SLOW |
| nEN80 | 82/0 | LVCMOS33_IN | PT10C | | | CLAMP:ON HYSTERESIS:SMALL |
| nRASout | 54/1 | LVCMOS33_OUT | PR7A | | | DRIVE:4mA SLEW:SLOW |
| nRWEout | 51/1 | LVCMOS33_OUT | PR7D | | | DRIVE:4mA SLEW:SLOW |
| nVOE | 10/3 | LVCMOS33_OUT | PL3D | | | DRIVE:4mA SLEW:SLOW |
| nWE | 29/2 | LVCMOS33_IN | PB4C | | | CLAMP:ON HYSTERESIS:SMALL |
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
Vccio by Bank:
+------+-------+
| Bank | Vccio |
+------+-------+
| 0 | 3.3V |
| 1 | 3.3V |
| 2 | 3.3V |
| 3 | 3.3V |
+------+-------+
Vref by Bank:
+------+-----+-----------------+---------+
| Vref | Pin | Bank # / Vref # | Load(s) |
+------+-----+-----------------+---------+
+------+-----+-----------------+---------+
Pinout by Pin Number:
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable |
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
| 1/3 | Din[4] | LOCATED | LVCMOS33_IN | PL2A | | | |
| 2/3 | Ain[1] | LOCATED | LVCMOS33_IN | PL2B | | | |
| 3/3 | Ain[0] | LOCATED | LVCMOS33_IN | PL2C | PCLKT3_2 | | |
| 4/3 | Ain[3] | LOCATED | LVCMOS33_IN | PL2D | PCLKC3_2 | | |
| 7/3 | Ain[2] | LOCATED | LVCMOS33_IN | PL3A | | | |
| 8/3 | Ain[7] | LOCATED | LVCMOS33_IN | PL3B | | | |
| 9/3 | Din[3] | LOCATED | LVCMOS33_IN | PL3C | | | |
| 10/3 | nVOE | LOCATED | LVCMOS33_OUT | PL3D | | | |
| 12/3 | Vout[7] | LOCATED | LVCMOS33_OUT | PL5A | PCLKT3_1 | | |
| 13/3 | Vout[3] | LOCATED | LVCMOS33_OUT | PL5B | PCLKC3_1 | | |
| 14/3 | Vout[6] | LOCATED | LVCMOS33_OUT | PL5C | | | |
| 15/3 | Vout[1] | LOCATED | LVCMOS33_OUT | PL5D | | | |
| 16/3 | Vout[5] | LOCATED | LVCMOS33_OUT | PL6A | | | |
| 17/3 | Vout[2] | LOCATED | LVCMOS33_OUT | PL6B | | | |
| 18/3 | Vout[0] | LOCATED | LVCMOS33_OUT | PL6C | | | |
| 19/3 | Vout[4] | LOCATED | LVCMOS33_OUT | PL6D | | | |
| 20/3 | nDOE | LOCATED | LVCMOS33_OUT | PL7A | PCLKT3_0 | | |
| 21/3 | Dout[5] | LOCATED | LVCMOS33_OUT | PL7B | PCLKC3_0 | | |
| 24/3 | Dout[4] | LOCATED | LVCMOS33_OUT | PL7C | | | |
| 25/3 | Dout[2] | LOCATED | LVCMOS33_OUT | PL7D | | | |
| 27/2 | Dout[1] | LOCATED | LVCMOS33_OUT | PB4A | CSSPIN | | |
| 28/2 | Dout[3] | LOCATED | LVCMOS33_OUT | PB4B | | | |
| 29/2 | nWE | LOCATED | LVCMOS33_IN | PB4C | | | |
| 30/2 | Dout[0] | LOCATED | LVCMOS33_OUT | PB4D | | | |
| 31/2 | Dout[6] | LOCATED | LVCMOS33_OUT | PB6A | MCLK/CCLK | | |
| 32/2 | Dout[7] | LOCATED | LVCMOS33_OUT | PB6B | SO/SPISO | | |
| 34/2 | nC07X | LOCATED | LVCMOS33_IN | PB6C | PCLKT2_0 | | |
| 35/2 | LED | LOCATED | LVCMOS33_OUT | PB6D | PCLKC2_0 | | |
| 36/2 | RD[0] | LOCATED | LVCMOS33_BIDI | PB10A | | | |
| 37/2 | RD[1] | LOCATED | LVCMOS33_BIDI | PB10B | | | |
| 38/2 | RD[2] | LOCATED | LVCMOS33_BIDI | PB10C | PCLKT2_1 | | |
| 39/2 | RD[3] | LOCATED | LVCMOS33_BIDI | PB10D | PCLKC2_1 | | |
| 40/2 | RD[4] | LOCATED | LVCMOS33_BIDI | PB12A | | | |
| 41/2 | RD[5] | LOCATED | LVCMOS33_BIDI | PB12B | | | |
| 42/2 | RD[6] | LOCATED | LVCMOS33_BIDI | PB12C | | | |
| 43/2 | RD[7] | LOCATED | LVCMOS33_BIDI | PB12D | | | |
| 45/2 | unused, PULL:DOWN | | | PB14A | | | |
| 47/2 | nDHGROE | LOCATED | LVCMOS33_OUT | PB14B | | | |
| 48/2 | DQML | LOCATED | LVCMOS33_OUT | PB14C | SN | | |
| 49/2 | DQMH | LOCATED | LVCMOS33_OUT | PB14D | SI/SISPI | | |
| 51/1 | nRWEout | LOCATED | LVCMOS33_OUT | PR7D | | | |
| 52/1 | nCASout | LOCATED | LVCMOS33_OUT | PR7C | | | |
| 53/1 | CKEout | LOCATED | LVCMOS33_OUT | PR7B | | | |
| 54/1 | nRASout | LOCATED | LVCMOS33_OUT | PR7A | | | |
| 57/1 | nCSout | LOCATED | LVCMOS33_OUT | PR6D | | | |
| 58/1 | BA[0] | LOCATED | LVCMOS33_OUT | PR6C | | | |
| 59/1 | RAout[11] | LOCATED | LVCMOS33_OUT | PR6B | | | |
| 60/1 | BA[1] | LOCATED | LVCMOS33_OUT | PR6A | | | |
| 62/1 | C14M | LOCATED | LVCMOS33_IN | PR5D | PCLKC1_0 | | |
| 63/1 | RAout[9] | LOCATED | LVCMOS33_OUT | PR5C | PCLKT1_0 | | |
| 64/1 | RAout[10] | LOCATED | LVCMOS33_OUT | PR5B | | | |
| 65/1 | RAout[8] | LOCATED | LVCMOS33_OUT | PR5A | | | |
| 66/1 | RAout[0] | LOCATED | LVCMOS33_OUT | PR3D | | | |
| 67/1 | RAout[7] | LOCATED | LVCMOS33_OUT | PR3C | | | |
| 68/1 | RAout[1] | LOCATED | LVCMOS33_OUT | PR3B | | | |
| 69/1 | RAout[6] | LOCATED | LVCMOS33_OUT | PR3A | | | |
| 70/1 | RAout[2] | LOCATED | LVCMOS33_OUT | PR2D | | | |
| 71/1 | RAout[5] | LOCATED | LVCMOS33_OUT | PR2C | | | |
| 74/1 | RAout[3] | LOCATED | LVCMOS33_OUT | PR2B | | | |
| 75/1 | RAout[4] | LOCATED | LVCMOS33_OUT | PR2A | | | |
| 76/0 | unused, PULL:DOWN | | | PT11D | DONE | | |
| 77/0 | unused, PULL:DOWN | | | PT11C | INITN | | |
| 78/0 | Ain[4] | LOCATED | LVCMOS33_IN | PT11A | | | |
| 81/0 | unused, PULL:DOWN | | | PT10D | PROGRAMN | | |
| 82/0 | nEN80 | LOCATED | LVCMOS33_IN | PT10C | JTAGENB | | |
| 83/0 | unused, PULL:DOWN | | | PT10B | | | |
| 84/0 | Ain[5] | LOCATED | LVCMOS33_IN | PT10A | | | |
| 85/0 | PHI1 | LOCATED | LVCMOS33_IN | PT9D | SDA/PCLKC0_0 | | |
| 86/0 | Ain[6] | LOCATED | LVCMOS33_IN | PT9C | SCL/PCLKT0_0 | | |
| 87/0 | Din[7] | LOCATED | LVCMOS33_IN | PT9B | PCLKC0_1 | | |
| 88/0 | Din[6] | LOCATED | LVCMOS33_IN | PT9A | PCLKT0_1 | | |
| 90/0 | Reserved: sysCONFIG | | | PT7D | TMS | | |
| 91/0 | Reserved: sysCONFIG | | | PT7C | TCK | | |
| 94/0 | Reserved: sysCONFIG | | | PT7B | TDI | | |
| 95/0 | Reserved: sysCONFIG | | | PT7A | TDO | | |
| 96/0 | Din[0] | LOCATED | LVCMOS33_IN | PT6D | | | |
| 97/0 | Din[1] | LOCATED | LVCMOS33_IN | PT6C | | | |
| 98/0 | Din[2] | LOCATED | LVCMOS33_IN | PT6B | | | |
| 99/0 | Din[5] | LOCATED | LVCMOS33_IN | PT6A | | | |
| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | |
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
sysCONFIG Pins:
+----------+--------------------+--------------------+----------+-------------+-------------------+
| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode |
+----------+--------------------+--------------------+----------+-------------+-------------------+
| PT7D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP |
| PT7C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down |
| PT7B | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP |
| PT7A | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP |
+----------+--------------------+--------------------+----------+-------------+-------------------+
Dedicated sysCONFIG Pins:
List of All Pins' Locate Preferences Based on Final Placement After PAR
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste):
LOCATE COMP "Ain[0]" SITE "3";
LOCATE COMP "Ain[1]" SITE "2";
LOCATE COMP "Ain[2]" SITE "7";
LOCATE COMP "Ain[3]" SITE "4";
LOCATE COMP "Ain[4]" SITE "78";
LOCATE COMP "Ain[5]" SITE "84";
LOCATE COMP "Ain[6]" SITE "86";
LOCATE COMP "Ain[7]" SITE "8";
LOCATE COMP "BA[0]" SITE "58";
LOCATE COMP "BA[1]" SITE "60";
LOCATE COMP "C14M" SITE "62";
LOCATE COMP "CKEout" SITE "53";
LOCATE COMP "DQMH" SITE "49";
LOCATE COMP "DQML" SITE "48";
LOCATE COMP "Din[0]" SITE "96";
LOCATE COMP "Din[1]" SITE "97";
LOCATE COMP "Din[2]" SITE "98";
LOCATE COMP "Din[3]" SITE "9";
LOCATE COMP "Din[4]" SITE "1";
LOCATE COMP "Din[5]" SITE "99";
LOCATE COMP "Din[6]" SITE "88";
LOCATE COMP "Din[7]" SITE "87";
LOCATE COMP "Dout[0]" SITE "30";
LOCATE COMP "Dout[1]" SITE "27";
LOCATE COMP "Dout[2]" SITE "25";
LOCATE COMP "Dout[3]" SITE "28";
LOCATE COMP "Dout[4]" SITE "24";
LOCATE COMP "Dout[5]" SITE "21";
LOCATE COMP "Dout[6]" SITE "31";
LOCATE COMP "Dout[7]" SITE "32";
LOCATE COMP "LED" SITE "35";
LOCATE COMP "PHI1" SITE "85";
LOCATE COMP "RAout[0]" SITE "66";
LOCATE COMP "RAout[10]" SITE "64";
LOCATE COMP "RAout[11]" SITE "59";
LOCATE COMP "RAout[1]" SITE "68";
LOCATE COMP "RAout[2]" SITE "70";
LOCATE COMP "RAout[3]" SITE "74";
LOCATE COMP "RAout[4]" SITE "75";
LOCATE COMP "RAout[5]" SITE "71";
LOCATE COMP "RAout[6]" SITE "69";
LOCATE COMP "RAout[7]" SITE "67";
LOCATE COMP "RAout[8]" SITE "65";
LOCATE COMP "RAout[9]" SITE "63";
LOCATE COMP "RD[0]" SITE "36";
LOCATE COMP "RD[1]" SITE "37";
LOCATE COMP "RD[2]" SITE "38";
LOCATE COMP "RD[3]" SITE "39";
LOCATE COMP "RD[4]" SITE "40";
LOCATE COMP "RD[5]" SITE "41";
LOCATE COMP "RD[6]" SITE "42";
LOCATE COMP "RD[7]" SITE "43";
LOCATE COMP "Vout[0]" SITE "18";
LOCATE COMP "Vout[1]" SITE "15";
LOCATE COMP "Vout[2]" SITE "17";
LOCATE COMP "Vout[3]" SITE "13";
LOCATE COMP "Vout[4]" SITE "19";
LOCATE COMP "Vout[5]" SITE "16";
LOCATE COMP "Vout[6]" SITE "14";
LOCATE COMP "Vout[7]" SITE "12";
LOCATE COMP "nC07X" SITE "34";
LOCATE COMP "nCASout" SITE "52";
LOCATE COMP "nCSout" SITE "57";
LOCATE COMP "nDHGROE" SITE "47";
LOCATE COMP "nDOE" SITE "20";
LOCATE COMP "nEN80" SITE "82";
LOCATE COMP "nRASout" SITE "54";
LOCATE COMP "nRWEout" SITE "51";
LOCATE COMP "nVOE" SITE "10";
LOCATE COMP "nWE" SITE "29";
PAR: Place And Route Diamond (64-bit) 3.11.3.469.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Fri Jun 07 20:50:23 2024

128
CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.prf Normal file
View File

@ -0,0 +1,128 @@
SCHEMATIC START ;
# map: version Diamond (64-bit) 3.11.3.469 -- WARNING: Map write only section -- Fri Jun 07 20:50:09 2024
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
LOCATE COMP "RD[0]" SITE "36" ;
LOCATE COMP "LED" SITE "35" ;
LOCATE COMP "C14M" SITE "62" ;
LOCATE COMP "RD[7]" SITE "43" ;
LOCATE COMP "RD[6]" SITE "42" ;
LOCATE COMP "RD[5]" SITE "41" ;
LOCATE COMP "RD[4]" SITE "40" ;
LOCATE COMP "RD[3]" SITE "39" ;
LOCATE COMP "RD[2]" SITE "38" ;
LOCATE COMP "RD[1]" SITE "37" ;
LOCATE COMP "DQMH" SITE "49" ;
LOCATE COMP "DQML" SITE "48" ;
LOCATE COMP "RAout[11]" SITE "59" ;
LOCATE COMP "RAout[10]" SITE "64" ;
LOCATE COMP "RAout[9]" SITE "63" ;
LOCATE COMP "RAout[8]" SITE "65" ;
LOCATE COMP "RAout[7]" SITE "67" ;
LOCATE COMP "RAout[6]" SITE "69" ;
LOCATE COMP "RAout[5]" SITE "71" ;
LOCATE COMP "RAout[4]" SITE "75" ;
LOCATE COMP "RAout[3]" SITE "74" ;
LOCATE COMP "RAout[2]" SITE "70" ;
LOCATE COMP "RAout[1]" SITE "68" ;
LOCATE COMP "RAout[0]" SITE "66" ;
LOCATE COMP "BA[1]" SITE "60" ;
LOCATE COMP "BA[0]" SITE "58" ;
LOCATE COMP "nRWEout" SITE "51" ;
LOCATE COMP "nCASout" SITE "52" ;
LOCATE COMP "nRASout" SITE "54" ;
LOCATE COMP "nCSout" SITE "57" ;
LOCATE COMP "CKEout" SITE "53" ;
LOCATE COMP "nVOE" SITE "10" ;
LOCATE COMP "Vout[7]" SITE "12" ;
LOCATE COMP "Vout[6]" SITE "14" ;
LOCATE COMP "Vout[5]" SITE "16" ;
LOCATE COMP "Vout[4]" SITE "19" ;
LOCATE COMP "Vout[3]" SITE "13" ;
LOCATE COMP "Vout[2]" SITE "17" ;
LOCATE COMP "Vout[1]" SITE "15" ;
LOCATE COMP "Vout[0]" SITE "18" ;
LOCATE COMP "nDOE" SITE "20" ;
LOCATE COMP "Dout[7]" SITE "32" ;
LOCATE COMP "Dout[6]" SITE "31" ;
LOCATE COMP "Dout[5]" SITE "21" ;
LOCATE COMP "Dout[4]" SITE "24" ;
LOCATE COMP "Dout[3]" SITE "28" ;
LOCATE COMP "Dout[2]" SITE "25" ;
LOCATE COMP "Dout[1]" SITE "27" ;
LOCATE COMP "Dout[0]" SITE "30" ;
LOCATE COMP "Din[7]" SITE "87" ;
LOCATE COMP "Din[6]" SITE "88" ;
LOCATE COMP "Din[5]" SITE "99" ;
LOCATE COMP "Din[4]" SITE "1" ;
LOCATE COMP "Din[3]" SITE "9" ;
LOCATE COMP "Din[2]" SITE "98" ;
LOCATE COMP "Din[1]" SITE "97" ;
LOCATE COMP "Din[0]" SITE "96" ;
LOCATE COMP "Ain[7]" SITE "8" ;
LOCATE COMP "Ain[6]" SITE "86" ;
LOCATE COMP "Ain[5]" SITE "84" ;
LOCATE COMP "Ain[4]" SITE "78" ;
LOCATE COMP "Ain[3]" SITE "4" ;
LOCATE COMP "Ain[2]" SITE "7" ;
LOCATE COMP "Ain[1]" SITE "2" ;
LOCATE COMP "Ain[0]" SITE "3" ;
LOCATE COMP "nC07X" SITE "34" ;
LOCATE COMP "nEN80" SITE "82" ;
LOCATE COMP "nWE" SITE "29" ;
LOCATE COMP "nDHGROE" SITE "47" ;
LOCATE COMP "PHI1" SITE "85" ;
FREQUENCY PORT "C14M" 14.300000 MHz ;
SCHEMATIC END ;
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
OUTPUT PORT "LED" LOAD 100.000000 pF ;
OUTPUT PORT "nDHGROE" LOAD 10.000000 pF ;
OUTPUT PORT "BA[1]" LOAD 5.000000 pF ;
OUTPUT PORT "BA[0]" LOAD 5.000000 pF ;
OUTPUT PORT "CKEout" LOAD 5.000000 pF ;
OUTPUT PORT "DQMH" LOAD 5.000000 pF ;
OUTPUT PORT "DQML" LOAD 5.000000 pF ;
OUTPUT PORT "Dout[0]" LOAD 15.000000 pF ;
OUTPUT PORT "Dout[1]" LOAD 15.000000 pF ;
OUTPUT PORT "Dout[2]" LOAD 15.000000 pF ;
OUTPUT PORT "Dout[3]" LOAD 15.000000 pF ;
OUTPUT PORT "Dout[4]" LOAD 15.000000 pF ;
OUTPUT PORT "Dout[5]" LOAD 15.000000 pF ;
OUTPUT PORT "Dout[6]" LOAD 15.000000 pF ;
OUTPUT PORT "Dout[7]" LOAD 15.000000 pF ;
OUTPUT PORT "RAout[0]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[1]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[2]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[3]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[4]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[5]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[6]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[7]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[8]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[9]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[10]" LOAD 5.000000 pF ;
OUTPUT PORT "RAout[11]" LOAD 5.000000 pF ;
OUTPUT PORT "Vout[0]" LOAD 15.000000 pF ;
OUTPUT PORT "Vout[1]" LOAD 15.000000 pF ;
OUTPUT PORT "Vout[2]" LOAD 15.000000 pF ;
OUTPUT PORT "Vout[3]" LOAD 15.000000 pF ;
OUTPUT PORT "Vout[4]" LOAD 15.000000 pF ;
OUTPUT PORT "Vout[5]" LOAD 15.000000 pF ;
OUTPUT PORT "Vout[6]" LOAD 15.000000 pF ;
OUTPUT PORT "Vout[7]" LOAD 15.000000 pF ;
OUTPUT PORT "nCASout" LOAD 5.000000 pF ;
OUTPUT PORT "nCSout" LOAD 5.000000 pF ;
OUTPUT PORT "nDOE" LOAD 10.000000 pF ;
OUTPUT PORT "nRASout" LOAD 5.000000 pF ;
OUTPUT PORT "nRWEout" LOAD 5.000000 pF ;
OUTPUT PORT "nVOE" LOAD 10.000000 pF ;
OUTPUT PORT "RD[0]" LOAD 9.000000 pF ;
OUTPUT PORT "RD[1]" LOAD 9.000000 pF ;
OUTPUT PORT "RD[2]" LOAD 9.000000 pF ;
OUTPUT PORT "RD[3]" LOAD 9.000000 pF ;
OUTPUT PORT "RD[4]" LOAD 9.000000 pF ;
OUTPUT PORT "RD[5]" LOAD 9.000000 pF ;
OUTPUT PORT "RD[6]" LOAD 9.000000 pF ;
OUTPUT PORT "RD[7]" LOAD 9.000000 pF ;
COMMERCIAL ;

740
CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.srr Normal file
View File

@ -0,0 +1,740 @@
#Build: Synplify Pro (R) N-2018.03L-SP1-1, Build 443R, Apr 1 2019
#install: C:\lscc\diamond\3.11_x64\synpbase
#OS: Windows 8 6.2
#Hostname: ZANEMACWIN11
# Fri Jun 7 20:50:00 2024
#Implementation: impl1
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys HDL Compiler, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Verilog Compiler, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v" (library work)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\pmi_def.v" (library work)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v" (library work)
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v" (library work)
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\REFB.v" (library work)
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\DHGR-ON.v" (library work)
Verilog syntax check successful!
Selecting top level module RAM2E
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
Running optimization stage 1 on VHI .......
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
Running optimization stage 1 on VLO .......
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
Running optimization stage 1 on EFB .......
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
Running optimization stage 1 on REFB .......
@W: CL318 :"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\REFB.v":9:14:9:21|*Output wb_dat_o has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output.
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v":1:7:1:15|Synthesizing module RAM2E_UFM in library work.
Running optimization stage 1 on RAM2E_UFM .......
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\DHGR-ON.v":1:7:1:10|Synthesizing module DHGR in library work.
Running optimization stage 1 on DHGR .......
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v":1:7:1:11|Synthesizing module RAM2E in library work.
Running optimization stage 1 on RAM2E .......
Running optimization stage 2 on RAM2E .......
@N: CL159 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v":11:15:11:19|Input nWE80 is unused.
Running optimization stage 2 on DHGR .......
Running optimization stage 2 on RAM2E_UFM .......
Running optimization stage 2 on REFB .......
Running optimization stage 2 on EFB .......
Running optimization stage 2 on VLO .......
Running optimization stage 2 on VHI .......
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Fri Jun 7 20:50:00 2024
###########################################################]
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Fri Jun 7 20:50:00 2024
###########################################################]
For a summary of runtime and memory usage for all design units, please see file:
==========================================================
@L: A:\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_comp.rt.csv
@END
At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Fri Jun 7 20:50:00 2024
###########################################################]
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Database state : \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\synwork\|impl1
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Fri Jun 7 20:50:02 2024
###########################################################]
Premap Report
# Fri Jun 7 20:50:02 2024
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Lattice Technology Pre-mapping, Version maplat2018q2p1, Build 055R, Built Apr 3 2019 09:51:54
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
Reading constraint file: \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
@N: MF284 |Setting synthesis effort to medium for the design
@L: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1_scck.rpt
Printing clock summary report in "\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1_scck.rpt" file
@N: MF916 |Option synthesis_strategy=base is enabled.
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
@N: MF284 |Setting synthesis effort to medium for the design
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":21:4:21:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
@N: MH105 |UMR3 is only supported for HAPS-80.
@N: MH105 |UMR3 is only supported for HAPS-80.
@N: BN115 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":140:9:140:12|Removing instance dhgr (in view: work.RAM2E(verilog)) of type view:work.DHGR(verilog) because it does not drive other instances.
syn_allowed_resources : blockrams=2 set on top level netlist RAM2E
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
Clock Summary
******************
Start Requested Requested Clock Clock Clock
Level Clock Frequency Period Type Group Load
-----------------------------------------------------------------------------------------------
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 121
0 - System 100.0 MHz 10.000 system system_clkgroup 0
0 - RAM2E|PHI1 100.0 MHz 10.000 inferred Inferred_clkgroup_0 9
===============================================================================================
Clock Load Summary
***********************
Clock Source Clock Pin Non-clock Pin Non-clock Pin
Clock Load Pin Seq Example Seq Example Comb Example
--------------------------------------------------------------------------------------------
C14M 121 C14M(port) RAT.C - un1_C14M.I[0](inv)
System 0 - - - -
RAM2E|PHI1 9 PHI1(port) RefReq.C S[0].D[0] un1_PHI1.I[0](inv)
============================================================================================
@W: MT529 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":20:19:20:24|Found inferred clock RAM2E|PHI1 which controls 9 sequential elements including PHI1r. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed: 0
@S |Clock Optimization Summary
#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
2 non-gated/non-generated clock tree(s) driving 125 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
---------------------------------------------------------------------------------------
@KP:ckid0_0 C14M port 121 PHI1r
@KP:ckid0_1 PHI1 Unconstrained_port 4 RC[2:0]
=======================================================================================
##### END OF CLOCK OPTIMIZATION REPORT ######
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
Finished Pre Mapping Phase.
Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
None
None
Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
Pre-mapping successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 143MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Jun 7 20:50:03 2024
###########################################################]
Map & Optimize Report
# Fri Jun 7 20:50:03 2024
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Lattice Technology Mapper, Version maplat2018q2p1, Build 055R, Built Apr 3 2019 09:51:54
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
@N: MF284 |Setting synthesis effort to medium for the design
@N: MF916 |Option synthesis_strategy=base is enabled.
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
@N: MF284 |Setting synthesis effort to medium for the design
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
Available hyper_sources - for debug and ip models
None Found
@N: FX493 |Applying initial value "00000000" on instance RWBank[7:0].
@N: FX493 |Applying initial value "0000" on instance S[3:0].
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)
@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":14:23:14:28|Found counter in view:work.RAM2E(verilog) instance FS[15:0]
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 142MB)
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:01s 6.90ns 281 / 125
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":171:4:171:9|Boundary register BA_1_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":171:4:171:9|Boundary register BA_0_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 158MB peak: 160MB)
Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 122MB peak: 160MB)
Writing Analyst data base \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_m.srm
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 158MB peak: 160MB)
Writing EDIF Netlist and constraint files
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1.edi
N-2018.03L-SP1-1
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 162MB peak: 164MB)
Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 164MB)
@W: MT246 :"\\mac\icloud\repos\ram2e\cpld\lcmxo2-640hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@N: MT615 |Found clock C14M with period 69.84ns
@W: MT420 |Found inferred clock RAM2E|PHI1 with period 10.00ns. Please declare a user-defined clock on port PHI1.
##### START OF TIMING REPORT #####[
# Timing Report written on Fri Jun 7 20:50:06 2024
#
Top view: RAM2E
Requested Frequency: 14.3 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s): \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
Performance Summary
*******************
Worst slack in design: 6.897
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
----------------------------------------------------------------------------------------------------------------------
C14M 14.3 MHz 112.1 MHz 69.841 8.918 31.599 declared default_clkgroup
RAM2E|PHI1 100.0 MHz 322.2 MHz 10.000 3.103 6.897 inferred Inferred_clkgroup_0
System 100.0 MHz NA 10.000 NA 67.088 system system_clkgroup
======================================================================================================================
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
----------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
----------------------------------------------------------------------------------------------------------------
System C14M | 69.841 67.088 | No paths - | No paths - | No paths -
C14M System | 69.841 68.797 | No paths - | No paths - | No paths -
C14M C14M | 69.841 60.923 | No paths - | 34.920 31.599 | No paths -
RAM2E|PHI1 C14M | No paths - | No paths - | No paths - | Diff grp -
RAM2E|PHI1 RAM2E|PHI1 | No paths - | 10.000 6.897 | No paths - | No paths -
================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Interface Information
*********************
No IO constraint found
====================================
Detailed Report for Clock: C14M
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------
S[2] C14M FD1S3AX Q S[2] 1.366 31.599
S[3] C14M FD1S3AX Q S[3] 1.345 31.619
S[1] C14M FD1S3AX Q S[1] 1.344 31.800
S[0] C14M FD1S3AX Q S[0] 1.305 31.838
RA[0] C14M FD1P3AX Q RA[0] 1.108 33.707
RA[3] C14M FD1P3AX Q RA[3] 1.108 33.707
RA[1] C14M FD1P3AX Q RA[1] 1.044 33.771
RA[2] C14M FD1P3AX Q RA[2] 1.044 33.771
RA[4] C14M FD1P3AX Q RA[4] 1.044 33.771
RA[5] C14M FD1P3AX Q RA[5] 1.044 33.771
===========================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
-----------------------------------------------------------------------------------
VOE_i_0io C14M OFS1P3IX CD N_530 34.118 31.599
VOE_i_0io C14M OFS1P3IX D VOE_ic_i 35.009 31.800
Vout_0io[0] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[1] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[2] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[3] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[4] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[5] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[6] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[7] C14M OFS1P3DX SP Vout3 34.449 32.634
===================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 34.920
- Setup time: 0.803
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 34.118
- Propagation time: 2.519
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : 31.599
Number of logic level(s): 1
Starting point: S[2] / Q
Ending point: VOE_i_0io / CD
The start point is clocked by C14M [rising] on pin CK
The end point is clocked by C14M [falling] on pin SCLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
------------------------------------------------------------------------------------------------------------
S[2] FD1S3AX Q Out 1.366 1.366 -
S[2] Net - - - - 58
ram2e_ufm.un1_wb_adr_0_sqmuxa_2_0_a2_0[0] ORCALUT4 A In 0.000 1.366 -
ram2e_ufm.un1_wb_adr_0_sqmuxa_2_0_a2_0[0] ORCALUT4 Z Out 1.153 2.519 -
N_530 Net - - - - 3
VOE_i_0io OFS1P3IX CD In 0.000 2.519 -
============================================================================================================
====================================
Detailed Report for Clock: RAM2E|PHI1
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------
RC[1] RAM2E|PHI1 FD1S3IX Q RC[1] 1.148 6.897
RC[2] RAM2E|PHI1 FD1S3IX Q RC[2] 1.108 6.937
RC[0] RAM2E|PHI1 FD1S3IX Q RC[0] 1.148 8.179
===========================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------
RC[0] RAM2E|PHI1 FD1S3IX CD RC7 9.197 6.897
RC[1] RAM2E|PHI1 FD1S3IX CD RC7 9.197 6.897
RC[2] RAM2E|PHI1 FD1S3IX CD RC7 9.197 6.897
RC[0] RAM2E|PHI1 FD1S3IX D RC_i[0] 9.894 8.179
RC[1] RAM2E|PHI1 FD1S3IX D RC_RNO[1] 10.089 8.324
RC[2] RAM2E|PHI1 FD1S3IX D RC_RNO[2] 10.089 8.324
RefReq RAM2E|PHI1 FD1S3AX D RefReq_2 10.089 8.324
================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 10.000
- Setup time: 0.803
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 9.197
- Propagation time: 2.301
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : 6.897
Number of logic level(s): 1
Starting point: RC[1] / Q
Ending point: RC[0] / CD
The start point is clocked by RAM2E|PHI1 [falling] on pin CK
The end point is clocked by RAM2E|PHI1 [falling] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------
RC[1] FD1S3IX Q Out 1.148 1.148 -
RC[1] Net - - - - 4
RC7 ORCALUT4 A In 0.000 1.148 -
RC7 ORCALUT4 Z Out 1.153 2.301 -
RC7 Net - - - - 3
RC[0] FD1S3IX CD In 0.000 2.301 -
=================================================================================
====================================
Detailed Report for Clock: System
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------------------------------
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBACKO wb_ack 0.000 67.088
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO0 wb_dato[0] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO2 wb_dato[2] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO3 wb_dato[3] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO4 wb_dato[4] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO5 wb_dato[5] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO6 wb_dato[6] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO7 wb_dato[7] 0.000 69.313
===================================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
----------------------------------------------------------------------------------------
ram2e_ufm.RWMask[0] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[1] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[2] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[3] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[4] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[5] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[6] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[7] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.LEDEN System FD1P3AX SP N_98 69.369 67.736
ram2e_ufm.wb_cyc_stb System FD1P3AX SP N_111 69.369 67.736
========================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 69.841
- Setup time: 0.472
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 69.369
- Propagation time: 2.282
- Clock delay at starting point: 0.000 (ideal)
- Estimated clock delay at start point: -0.000
= Slack (non-critical) : 67.088
Number of logic level(s): 2
Starting point: ram2e_ufm.ufmefb.EFBInst_0 / WBACKO
Ending point: ram2e_ufm.RWMask[0] / SP
The start point is clocked by System [rising]
The end point is clocked by C14M [rising] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
----------------------------------------------------------------------------------------------------------------
ram2e_ufm.ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 -
wb_ack Net - - - - 5
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] ORCALUT4 B In 0.000 0.000 -
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] ORCALUT4 Z Out 1.017 1.017 -
un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] Net - - - - 1
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 D In 0.000 1.017 -
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 Z Out 1.265 2.282 -
N_104 Net - - - - 8
ram2e_ufm.RWMask[0] FD1P3AX SP In 0.000 2.282 -
================================================================================================================
##### END OF TIMING REPORT #####]
Timing exceptions that could not be applied
None
Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 164MB)
Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 164MB)
---------------------------------------
Resource Usage Report
Part: lcmxo2_640hc-4
Register bits: 125 of 640 (20%)
PIC Latch: 0
I/O cells: 70
Details:
BB: 8
CCU2D: 9
EFB: 1
FD1P3AX: 58
FD1P3IX: 1
FD1S3AX: 31
FD1S3AY: 4
FD1S3IX: 9
GSR: 1
IB: 21
IFS1P3DX: 1
INV: 4
OB: 41
OFS1P3BX: 6
OFS1P3DX: 12
OFS1P3IX: 3
ORCALUT4: 275
PUR: 1
VHI: 3
VLO: 3
Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 33MB peak: 164MB)
Process took 0h:00m:03s realtime, 0h:00m:03s cputime
# Fri Jun 7 20:50:07 2024
###########################################################]

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Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
# Written on Fri Jun 7 20:50:03 2024
##### DESIGN INFO #######################################################
Top View: "RAM2E"
Constraint File(s): "\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc"
##### SUMMARY ############################################################
Found 0 issues in 0 out of 1 constraints
##### DETAILS ############################################################
Clock Relationships
*******************
Starting Ending | rise to rise | fall to fall | rise to fall | fall to rise
-----------------------------------------------------------------------------------------------------------------------------------------
System C14M | 69.841 | No paths | No paths | No paths
C14M System | 69.841 | No paths | No paths | No paths
C14M C14M | 69.841 | No paths | 34.920 | No paths
RAM2E|PHI1 C14M | No paths | No paths | No paths | Diff grp
RAM2E|PHI1 RAM2E|PHI1 | No paths | 10.000 | No paths | No paths
=========================================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Unconstrained Start/End Points
******************************
p:Ain[0]
p:Ain[1]
p:Ain[2]
p:Ain[3]
p:Ain[4]
p:Ain[5]
p:Ain[6]
p:Ain[7]
p:BA[0]
p:BA[1]
p:CKEout
p:DQMH
p:DQML
p:Din[0]
p:Din[1]
p:Din[2]
p:Din[3]
p:Din[4]
p:Din[5]
p:Din[6]
p:Din[7]
p:Dout[0]
p:Dout[1]
p:Dout[2]
p:Dout[3]
p:Dout[4]
p:Dout[5]
p:Dout[6]
p:Dout[7]
p:LED
p:RAout[0]
p:RAout[1]
p:RAout[2]
p:RAout[3]
p:RAout[4]
p:RAout[5]
p:RAout[6]
p:RAout[7]
p:RAout[8]
p:RAout[9]
p:RAout[10]
p:RAout[11]
p:RD[0] (bidir end point)
p:RD[0] (bidir start point)
p:RD[1] (bidir end point)
p:RD[1] (bidir start point)
p:RD[2] (bidir end point)
p:RD[2] (bidir start point)
p:RD[3] (bidir end point)
p:RD[3] (bidir start point)
p:RD[4] (bidir end point)
p:RD[4] (bidir start point)
p:RD[5] (bidir end point)
p:RD[5] (bidir start point)
p:RD[6] (bidir end point)
p:RD[6] (bidir start point)
p:RD[7] (bidir end point)
p:RD[7] (bidir start point)
p:Vout[0]
p:Vout[1]
p:Vout[2]
p:Vout[3]
p:Vout[4]
p:Vout[5]
p:Vout[6]
p:Vout[7]
p:nC07X
p:nCASout
p:nCSout
p:nDHGROE
p:nDOE
p:nEN80
p:nRASout
p:nRWEout
p:nVOE
p:nWE
p:nWE80
Inapplicable constraints
************************
(none)
Applicable constraints with issues
**********************************
(none)
Constraints with matching wildcard expressions
**********************************************
(none)
Library Report
**************
# End of Constraint Checker Report

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<HTML>
<HEAD><TITLE>Project Summary</TITLE>
<STYLE TYPE="text/css">
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<PRE><A name="Mrp"></A>
Lattice Mapping Report File for Design Module 'RAM2E'
<A name="mrp_di"></A><B><U><big>Design Information</big></U></B>
Command line: map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial
RAM2E_LCMXO2_640HC_impl1.ngd -o RAM2E_LCMXO2_640HC_impl1_map.ncd -pr
RAM2E_LCMXO2_640HC_impl1.prf -mp RAM2E_LCMXO2_640HC_impl1.mrp -lpf //Mac/iC
loud/Repos/RAM2E/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_synplify.
lpf -lpf //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf -c 0 -gui
Target Vendor: LATTICE
Target Device: LCMXO2-640HCTQFP100
Target Performance: 4
Mapper: xo2c00, version: Diamond (64-bit) 3.11.3.469
Mapped on: 06/07/24 20:50:09
<A name="mrp_ds"></A><B><U><big>Design Summary</big></U></B>
Number of registers: 125 out of 877 (14%)
PFU registers: 103 out of 640 (16%)
PIO registers: 22 out of 237 (9%)
Number of SLICEs: 148 out of 320 (46%)
SLICEs as Logic/ROM: 148 out of 320 (46%)
SLICEs as RAM: 0 out of 240 (0%)
SLICEs as Carry: 9 out of 320 (3%)
Number of LUT4s: 295 out of 640 (46%)
Number used as logic LUTs: 277
Number used as distributed RAM: 0
Number used as ripple logic: 18
Number used as shift registers: 0
Number of PIO sites used: 70 + 4(JTAG) out of 79 (94%)
Number of block RAMs: 0 out of 2 (0%)
Number of GSRs: 0 out of 1 (0%)
EFB used : Yes
JTAG used : No
Readback used : No
Oscillator used : No
Startup used : No
POR : On
Bandgap : On
Number of Power Controller: 0 out of 1 (0%)
Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
Number of DCCA: 0 out of 8 (0%)
Number of DCMA: 0 out of 2 (0%)
Notes:-
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
distributed RAMs) + 2*(Number of ripple logic)
2. Number of logic LUT4s does not include count of distributed RAM and
ripple logic.
Number of clocks: 2
Net C14M_c: 85 loads, 63 rising, 22 falling (Driver: PIO C14M )
Net PHI1_c: 3 loads, 0 rising, 3 falling (Driver: PIO PHI1 )
Number of Clock Enables: 13
Net N_117_i: 2 loads, 0 LSLICEs
Net RWBank14: 11 loads, 11 LSLICEs
Net ram2e_ufm/wb_adr_0_sqmuxa_1_i: 1 loads, 1 LSLICEs
Net un9_VOE_0_a2_0_a2: 1 loads, 1 LSLICEs
Net un6_DOEEN_0_a2_0_a2: 2 loads, 2 LSLICEs
Net ram2e_ufm/un1_wb_adr_0_sqmuxa_2_i[0]: 8 loads, 8 LSLICEs
Net ram2e_ufm/un1_wb_cyc_stb_0_sqmuxa_1_i[0]: 1 loads, 1 LSLICEs
Net ram2e_ufm/N_111: 1 loads, 1 LSLICEs
Net ram2e_ufm/N_104: 4 loads, 4 LSLICEs
Net ram2e_ufm/N_98: 1 loads, 1 LSLICEs
Net un1_CKE48_0_i: 6 loads, 6 LSLICEs
Net N_389_i: 2 loads, 0 LSLICEs
Net Vout3: 8 loads, 0 LSLICEs
Number of LSRs: 8
Net N_148: 2 loads, 2 LSLICEs
Net N_430_i: 2 loads, 0 LSLICEs
Net RC7: 2 loads, 2 LSLICEs
Net S[2]: 2 loads, 2 LSLICEs
Net ram2e_ufm/wb_rst: 1 loads, 0 LSLICEs
Net ram2e_ufm/nRWE_0_i_o3_RNIP8E61: 1 loads, 1 LSLICEs
Net N_530: 1 loads, 0 LSLICEs
Net N_301_i: 1 loads, 1 LSLICEs
Number of nets driven by tri-state buffers: 0
Top 10 highest fanout non-clock nets:
Net S[2]: 60 loads
Net S[3]: 48 loads
Net S[1]: 46 loads
Net S[0]: 31 loads
Net FS[11]: 24 loads
Net FS[10]: 23 loads
Net FS[12]: 23 loads
Net FS[9]: 23 loads
Net FS[13]: 21 loads
Net FS[8]: 18 loads
Number of warnings: 3
Number of errors: 0
<A name="mrp_dwe"></A><B><U><big>Design Errors/Warnings</big></U></B>
WARNING - map: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf(94): Semantic
error in "IOBUF PORT "nWE80" IO_TYPE=LVCMOS33 PULLMODE=NONE ;": Port
"nWE80" does not exist in the design. This preference has been disabled.
WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
temporarily disable certain features of the device including Power
Controller, GSR, Hardened User SPI Port, Hardened Primary User I2C Port.
Functionality is restored after the Flash Memory (UFM/Configuration)
Interface is disabled using Disable Configuration Interface command 0x26
followed by Bypass command 0xFF.
WARNING - map: IO buffer missing for top level port nWE80...logic will be
discarded.
<A name="mrp_ioa"></A><B><U><big>IO (PIO) Attributes</big></U></B>
+---------------------+-----------+-----------+------------+
| IO Name | Direction | Levelmode | IO |
| | | IO_TYPE | Register |
+---------------------+-----------+-----------+------------+
| RD[0] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| LED | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| C14M | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[7] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[6] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[5] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[4] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[3] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[2] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RD[1] | BIDIR | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| DQMH | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| DQML | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RAout[11] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RAout[10] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RAout[9] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RAout[8] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| RAout[7] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[6] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[5] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[4] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[3] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[2] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[1] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| RAout[0] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| BA[1] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| BA[0] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nRWEout | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nCASout | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nRASout | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nCSout | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| CKEout | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nVOE | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[7] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[6] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[5] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[4] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[3] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[2] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[1] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| Vout[0] | OUTPUT | LVCMOS33 | OUT |
+---------------------+-----------+-----------+------------+
| nDOE | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[7] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[6] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[5] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[4] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[3] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[2] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[1] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Dout[0] | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[7] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[6] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[5] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[4] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[3] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[2] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[1] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Din[0] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[7] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[6] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[5] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[4] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[3] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[2] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[1] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| Ain[0] | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nC07X | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nEN80 | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nWE | INPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| nDHGROE | OUTPUT | LVCMOS33 | |
+---------------------+-----------+-----------+------------+
| PHI1 | INPUT | LVCMOS33 | IN |
+---------------------+-----------+-----------+------------+
<A name="mrp_rm"></A><B><U><big>Removed logic</big></U></B>
Block GSR_INST undriven or does not drive anything - clipped.
Block ram2e_ufm/VCC undriven or does not drive anything - clipped.
Block ram2e_ufm/GND undriven or does not drive anything - clipped.
Signal RC_0_.CN was merged into signal PHI1_c
Signal RDOE_i was merged into signal RDOE
Signal RAT.CN was merged into signal C14M_c
Signal ram2e_ufm/ufmefb/VCC undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/GND undriven or does not drive anything - clipped.
Signal FS_s_0_S1[15] undriven or does not drive anything - clipped.
Signal FS_s_0_COUT[15] undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/CFGWAKE undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/wbc_ufm_irq undriven or does not drive anything -
clipped.
Signal ram2e_ufm/ufmefb/TCOC undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/TCINT undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIIRQO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPICSNEN undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMOSIEN undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMOSIO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMISOEN undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPIMISOO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPISCKEN undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/SPISCKO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C2SDAOEN undriven or does not drive anything -
clipped.
Signal ram2e_ufm/ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C2SCLOEN undriven or does not drive anything -
clipped.
Signal ram2e_ufm/ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C1SDAOEN undriven or does not drive anything -
clipped.
Signal ram2e_ufm/ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/I2C1SCLOEN undriven or does not drive anything -
clipped.
Signal ram2e_ufm/ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLADRO4 undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLWEO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLL1STBO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLL0STBO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLRSTO undriven or does not drive anything - clipped.
Signal ram2e_ufm/ufmefb/PLLCLKO undriven or does not drive anything - clipped.
Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped.
Signal N_1 undriven or does not drive anything - clipped.
Block RefReq.CN was optimized away.
Block RDOE_RNIAM8C was optimized away.
Block nCASout.CN was optimized away.
Block ram2e_ufm/ufmefb/VCC was optimized away.
Block ram2e_ufm/ufmefb/GND was optimized away.
<A name="mrp_efb"></A><B><U><big>Embedded Functional Block Connection Summary</big></U></B>
Desired WISHBONE clock frequency: 14.4 MHz
Clock source: C14M_c
Reset source: ram2e_ufm/wb_rst
Functions mode:
I2C #1 (Primary) Function: DISABLED
I2C #2 (Secondary) Function: DISABLED
SPI Function: DISABLED
Timer/Counter Function: DISABLED
Timer/Counter Mode: WB
UFM Connection: ENABLED
PLL0 Connection: DISABLED
PLL1 Connection: DISABLED
I2C Function Summary:
--------------------
None
SPI Function Summary:
--------------------
None
Timer/Counter Function Summary:
------------------------------
None
UFM Function Summary:
--------------------
UFM Utilization: General Purpose Flash Memory
Initialized UFM Pages: 1 Pages (1*128 Bits)
Available General
Purpose Flash Memory: 191 Pages (191*128 Bits)
EBR Blocks with Unique
Initialization Data: 0
WID EBR Instance
--- ------------
<A name="mrp_asic"></A><B><U><big>ASIC Components</big></U></B>
---------------
Instance Name: ram2e_ufm/ufmefb/EFBInst_0
Type: EFB
<A name="mrp_runtime"></A><B><U><big>Run Time and Memory Usage</big></U></B>
-------------------------
Total CPU Time: 0 secs
Total REAL Time: 0 secs
Peak Memory Usage: 59 MB
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights
reserved.
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<HEAD><TITLE>PAD Specification File</TITLE>
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<PRE><A name="Pad"></A>PAD Specification File
***************************
PART TYPE: LCMXO2-640HC
Performance Grade: 4
PACKAGE: TQFP100
Package Status: Final Version 1.39
Fri Jun 07 20:50:19 2024
Pinout by Port Name:
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties |
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
| Ain[0] | 3/3 | LVCMOS33_IN | PL2C | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[1] | 2/3 | LVCMOS33_IN | PL2B | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[2] | 7/3 | LVCMOS33_IN | PL3A | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[3] | 4/3 | LVCMOS33_IN | PL2D | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[4] | 78/0 | LVCMOS33_IN | PT11A | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[5] | 84/0 | LVCMOS33_IN | PT10A | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[6] | 86/0 | LVCMOS33_IN | PT9C | | | CLAMP:ON HYSTERESIS:SMALL |
| Ain[7] | 8/3 | LVCMOS33_IN | PL3B | | | CLAMP:ON HYSTERESIS:SMALL |
| BA[0] | 58/1 | LVCMOS33_OUT | PR6C | | | DRIVE:4mA SLEW:SLOW |
| BA[1] | 60/1 | LVCMOS33_OUT | PR6A | | | DRIVE:4mA SLEW:SLOW |
| C14M | 62/1 | LVCMOS33_IN | PR5D | | | CLAMP:ON HYSTERESIS:SMALL |
| CKEout | 53/1 | LVCMOS33_OUT | PR7B | | | DRIVE:4mA SLEW:SLOW |
| DQMH | 49/2 | LVCMOS33_OUT | PB14D | | | DRIVE:4mA SLEW:SLOW |
| DQML | 48/2 | LVCMOS33_OUT | PB14C | | | DRIVE:4mA SLEW:SLOW |
| Din[0] | 96/0 | LVCMOS33_IN | PT6D | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[1] | 97/0 | LVCMOS33_IN | PT6C | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[2] | 98/0 | LVCMOS33_IN | PT6B | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[3] | 9/3 | LVCMOS33_IN | PL3C | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[4] | 1/3 | LVCMOS33_IN | PL2A | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[5] | 99/0 | LVCMOS33_IN | PT6A | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[6] | 88/0 | LVCMOS33_IN | PT9A | | | CLAMP:ON HYSTERESIS:SMALL |
| Din[7] | 87/0 | LVCMOS33_IN | PT9B | | | CLAMP:ON HYSTERESIS:SMALL |
| Dout[0] | 30/2 | LVCMOS33_OUT | PB4D | | | DRIVE:4mA SLEW:SLOW |
| Dout[1] | 27/2 | LVCMOS33_OUT | PB4A | | | DRIVE:4mA SLEW:SLOW |
| Dout[2] | 25/3 | LVCMOS33_OUT | PL7D | | | DRIVE:4mA SLEW:SLOW |
| Dout[3] | 28/2 | LVCMOS33_OUT | PB4B | | | DRIVE:4mA SLEW:SLOW |
| Dout[4] | 24/3 | LVCMOS33_OUT | PL7C | | | DRIVE:4mA SLEW:SLOW |
| Dout[5] | 21/3 | LVCMOS33_OUT | PL7B | | | DRIVE:4mA SLEW:SLOW |
| Dout[6] | 31/2 | LVCMOS33_OUT | PB6A | | | DRIVE:4mA SLEW:SLOW |
| Dout[7] | 32/2 | LVCMOS33_OUT | PB6B | | | DRIVE:4mA SLEW:SLOW |
| LED | 35/2 | LVCMOS33_OUT | PB6D | | | DRIVE:4mA SLEW:SLOW |
| PHI1 | 85/0 | LVCMOS33_IN | PT9D | | | CLAMP:ON HYSTERESIS:SMALL |
| RAout[0] | 66/1 | LVCMOS33_OUT | PR3D | | | DRIVE:4mA SLEW:SLOW |
| RAout[10] | 64/1 | LVCMOS33_OUT | PR5B | | | DRIVE:4mA SLEW:SLOW |
| RAout[11] | 59/1 | LVCMOS33_OUT | PR6B | | | DRIVE:4mA SLEW:SLOW |
| RAout[1] | 68/1 | LVCMOS33_OUT | PR3B | | | DRIVE:4mA SLEW:SLOW |
| RAout[2] | 70/1 | LVCMOS33_OUT | PR2D | | | DRIVE:4mA SLEW:SLOW |
| RAout[3] | 74/1 | LVCMOS33_OUT | PR2B | | | DRIVE:4mA SLEW:SLOW |
| RAout[4] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA SLEW:SLOW |
| RAout[5] | 71/1 | LVCMOS33_OUT | PR2C | | | DRIVE:4mA SLEW:SLOW |
| RAout[6] | 69/1 | LVCMOS33_OUT | PR3A | | | DRIVE:4mA SLEW:SLOW |
| RAout[7] | 67/1 | LVCMOS33_OUT | PR3C | | | DRIVE:4mA SLEW:SLOW |
| RAout[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA SLEW:SLOW |
| RAout[9] | 63/1 | LVCMOS33_OUT | PR5C | | | DRIVE:4mA SLEW:SLOW |
| RD[0] | 36/2 | LVCMOS33_BIDI | PB10A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[1] | 37/2 | LVCMOS33_BIDI | PB10B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[2] | 38/2 | LVCMOS33_BIDI | PB10C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[3] | 39/2 | LVCMOS33_BIDI | PB10D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[4] | 40/2 | LVCMOS33_BIDI | PB12A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[5] | 41/2 | LVCMOS33_BIDI | PB12B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[6] | 42/2 | LVCMOS33_BIDI | PB12C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| RD[7] | 43/2 | LVCMOS33_BIDI | PB12D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
| Vout[0] | 18/3 | LVCMOS33_OUT | PL6C | | | DRIVE:4mA SLEW:SLOW |
| Vout[1] | 15/3 | LVCMOS33_OUT | PL5D | | | DRIVE:4mA SLEW:SLOW |
| Vout[2] | 17/3 | LVCMOS33_OUT | PL6B | | | DRIVE:4mA SLEW:SLOW |
| Vout[3] | 13/3 | LVCMOS33_OUT | PL5B | | | DRIVE:4mA SLEW:SLOW |
| Vout[4] | 19/3 | LVCMOS33_OUT | PL6D | | | DRIVE:4mA SLEW:SLOW |
| Vout[5] | 16/3 | LVCMOS33_OUT | PL6A | | | DRIVE:4mA SLEW:SLOW |
| Vout[6] | 14/3 | LVCMOS33_OUT | PL5C | | | DRIVE:4mA SLEW:SLOW |
| Vout[7] | 12/3 | LVCMOS33_OUT | PL5A | | | DRIVE:4mA SLEW:SLOW |
| nC07X | 34/2 | LVCMOS33_IN | PB6C | | | CLAMP:ON HYSTERESIS:SMALL |
| nCASout | 52/1 | LVCMOS33_OUT | PR7C | | | DRIVE:4mA SLEW:SLOW |
| nCSout | 57/1 | LVCMOS33_OUT | PR6D | | | DRIVE:4mA SLEW:SLOW |
| nDHGROE | 47/2 | LVCMOS33_OUT | PB14B | | | DRIVE:4mA SLEW:SLOW |
| nDOE | 20/3 | LVCMOS33_OUT | PL7A | | | DRIVE:4mA SLEW:SLOW |
| nEN80 | 82/0 | LVCMOS33_IN | PT10C | | | CLAMP:ON HYSTERESIS:SMALL |
| nRASout | 54/1 | LVCMOS33_OUT | PR7A | | | DRIVE:4mA SLEW:SLOW |
| nRWEout | 51/1 | LVCMOS33_OUT | PR7D | | | DRIVE:4mA SLEW:SLOW |
| nVOE | 10/3 | LVCMOS33_OUT | PL3D | | | DRIVE:4mA SLEW:SLOW |
| nWE | 29/2 | LVCMOS33_IN | PB4C | | | CLAMP:ON HYSTERESIS:SMALL |
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
Vccio by Bank:
+------+-------+
| Bank | Vccio |
+------+-------+
| 0 | 3.3V |
| 1 | 3.3V |
| 2 | 3.3V |
| 3 | 3.3V |
+------+-------+
<A name="pad_vref"></A><B><U><big>Vref by Bank:</big></U></B>
+------+-----+-----------------+---------+
| Vref | Pin | Bank # / Vref # | Load(s) |
+------+-----+-----------------+---------+
+------+-----+-----------------+---------+
<A name="pad_pin"></A><B><U><big>Pinout by Pin Number:</big></U></B>
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable |
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
| 1/3 | Din[4] | LOCATED | LVCMOS33_IN | PL2A | | | |
| 2/3 | Ain[1] | LOCATED | LVCMOS33_IN | PL2B | | | |
| 3/3 | Ain[0] | LOCATED | LVCMOS33_IN | PL2C | PCLKT3_2 | | |
| 4/3 | Ain[3] | LOCATED | LVCMOS33_IN | PL2D | PCLKC3_2 | | |
| 7/3 | Ain[2] | LOCATED | LVCMOS33_IN | PL3A | | | |
| 8/3 | Ain[7] | LOCATED | LVCMOS33_IN | PL3B | | | |
| 9/3 | Din[3] | LOCATED | LVCMOS33_IN | PL3C | | | |
| 10/3 | nVOE | LOCATED | LVCMOS33_OUT | PL3D | | | |
| 12/3 | Vout[7] | LOCATED | LVCMOS33_OUT | PL5A | PCLKT3_1 | | |
| 13/3 | Vout[3] | LOCATED | LVCMOS33_OUT | PL5B | PCLKC3_1 | | |
| 14/3 | Vout[6] | LOCATED | LVCMOS33_OUT | PL5C | | | |
| 15/3 | Vout[1] | LOCATED | LVCMOS33_OUT | PL5D | | | |
| 16/3 | Vout[5] | LOCATED | LVCMOS33_OUT | PL6A | | | |
| 17/3 | Vout[2] | LOCATED | LVCMOS33_OUT | PL6B | | | |
| 18/3 | Vout[0] | LOCATED | LVCMOS33_OUT | PL6C | | | |
| 19/3 | Vout[4] | LOCATED | LVCMOS33_OUT | PL6D | | | |
| 20/3 | nDOE | LOCATED | LVCMOS33_OUT | PL7A | PCLKT3_0 | | |
| 21/3 | Dout[5] | LOCATED | LVCMOS33_OUT | PL7B | PCLKC3_0 | | |
| 24/3 | Dout[4] | LOCATED | LVCMOS33_OUT | PL7C | | | |
| 25/3 | Dout[2] | LOCATED | LVCMOS33_OUT | PL7D | | | |
| 27/2 | Dout[1] | LOCATED | LVCMOS33_OUT | PB4A | CSSPIN | | |
| 28/2 | Dout[3] | LOCATED | LVCMOS33_OUT | PB4B | | | |
| 29/2 | nWE | LOCATED | LVCMOS33_IN | PB4C | | | |
| 30/2 | Dout[0] | LOCATED | LVCMOS33_OUT | PB4D | | | |
| 31/2 | Dout[6] | LOCATED | LVCMOS33_OUT | PB6A | MCLK/CCLK | | |
| 32/2 | Dout[7] | LOCATED | LVCMOS33_OUT | PB6B | SO/SPISO | | |
| 34/2 | nC07X | LOCATED | LVCMOS33_IN | PB6C | PCLKT2_0 | | |
| 35/2 | LED | LOCATED | LVCMOS33_OUT | PB6D | PCLKC2_0 | | |
| 36/2 | RD[0] | LOCATED | LVCMOS33_BIDI | PB10A | | | |
| 37/2 | RD[1] | LOCATED | LVCMOS33_BIDI | PB10B | | | |
| 38/2 | RD[2] | LOCATED | LVCMOS33_BIDI | PB10C | PCLKT2_1 | | |
| 39/2 | RD[3] | LOCATED | LVCMOS33_BIDI | PB10D | PCLKC2_1 | | |
| 40/2 | RD[4] | LOCATED | LVCMOS33_BIDI | PB12A | | | |
| 41/2 | RD[5] | LOCATED | LVCMOS33_BIDI | PB12B | | | |
| 42/2 | RD[6] | LOCATED | LVCMOS33_BIDI | PB12C | | | |
| 43/2 | RD[7] | LOCATED | LVCMOS33_BIDI | PB12D | | | |
| 45/2 | unused, PULL:DOWN | | | PB14A | | | |
| 47/2 | nDHGROE | LOCATED | LVCMOS33_OUT | PB14B | | | |
| 48/2 | DQML | LOCATED | LVCMOS33_OUT | PB14C | SN | | |
| 49/2 | DQMH | LOCATED | LVCMOS33_OUT | PB14D | SI/SISPI | | |
| 51/1 | nRWEout | LOCATED | LVCMOS33_OUT | PR7D | | | |
| 52/1 | nCASout | LOCATED | LVCMOS33_OUT | PR7C | | | |
| 53/1 | CKEout | LOCATED | LVCMOS33_OUT | PR7B | | | |
| 54/1 | nRASout | LOCATED | LVCMOS33_OUT | PR7A | | | |
| 57/1 | nCSout | LOCATED | LVCMOS33_OUT | PR6D | | | |
| 58/1 | BA[0] | LOCATED | LVCMOS33_OUT | PR6C | | | |
| 59/1 | RAout[11] | LOCATED | LVCMOS33_OUT | PR6B | | | |
| 60/1 | BA[1] | LOCATED | LVCMOS33_OUT | PR6A | | | |
| 62/1 | C14M | LOCATED | LVCMOS33_IN | PR5D | PCLKC1_0 | | |
| 63/1 | RAout[9] | LOCATED | LVCMOS33_OUT | PR5C | PCLKT1_0 | | |
| 64/1 | RAout[10] | LOCATED | LVCMOS33_OUT | PR5B | | | |
| 65/1 | RAout[8] | LOCATED | LVCMOS33_OUT | PR5A | | | |
| 66/1 | RAout[0] | LOCATED | LVCMOS33_OUT | PR3D | | | |
| 67/1 | RAout[7] | LOCATED | LVCMOS33_OUT | PR3C | | | |
| 68/1 | RAout[1] | LOCATED | LVCMOS33_OUT | PR3B | | | |
| 69/1 | RAout[6] | LOCATED | LVCMOS33_OUT | PR3A | | | |
| 70/1 | RAout[2] | LOCATED | LVCMOS33_OUT | PR2D | | | |
| 71/1 | RAout[5] | LOCATED | LVCMOS33_OUT | PR2C | | | |
| 74/1 | RAout[3] | LOCATED | LVCMOS33_OUT | PR2B | | | |
| 75/1 | RAout[4] | LOCATED | LVCMOS33_OUT | PR2A | | | |
| 76/0 | unused, PULL:DOWN | | | PT11D | DONE | | |
| 77/0 | unused, PULL:DOWN | | | PT11C | INITN | | |
| 78/0 | Ain[4] | LOCATED | LVCMOS33_IN | PT11A | | | |
| 81/0 | unused, PULL:DOWN | | | PT10D | PROGRAMN | | |
| 82/0 | nEN80 | LOCATED | LVCMOS33_IN | PT10C | JTAGENB | | |
| 83/0 | unused, PULL:DOWN | | | PT10B | | | |
| 84/0 | Ain[5] | LOCATED | LVCMOS33_IN | PT10A | | | |
| 85/0 | PHI1 | LOCATED | LVCMOS33_IN | PT9D | SDA/PCLKC0_0 | | |
| 86/0 | Ain[6] | LOCATED | LVCMOS33_IN | PT9C | SCL/PCLKT0_0 | | |
| 87/0 | Din[7] | LOCATED | LVCMOS33_IN | PT9B | PCLKC0_1 | | |
| 88/0 | Din[6] | LOCATED | LVCMOS33_IN | PT9A | PCLKT0_1 | | |
| 90/0 | Reserved: sysCONFIG | | | PT7D | TMS | | |
| 91/0 | Reserved: sysCONFIG | | | PT7C | TCK | | |
| 94/0 | Reserved: sysCONFIG | | | PT7B | TDI | | |
| 95/0 | Reserved: sysCONFIG | | | PT7A | TDO | | |
| 96/0 | Din[0] | LOCATED | LVCMOS33_IN | PT6D | | | |
| 97/0 | Din[1] | LOCATED | LVCMOS33_IN | PT6C | | | |
| 98/0 | Din[2] | LOCATED | LVCMOS33_IN | PT6B | | | |
| 99/0 | Din[5] | LOCATED | LVCMOS33_IN | PT6A | | | |
| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | |
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
sysCONFIG Pins:
+----------+--------------------+--------------------+----------+-------------+-------------------+
| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode |
+----------+--------------------+--------------------+----------+-------------+-------------------+
| PT7D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP |
| PT7C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down |
| PT7B | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP |
| PT7A | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP |
+----------+--------------------+--------------------+----------+-------------+-------------------+
Dedicated sysCONFIG Pins:
List of All Pins' Locate Preferences Based on Final Placement After PAR
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste):
LOCATE COMP "Ain[0]" SITE "3";
LOCATE COMP "Ain[1]" SITE "2";
LOCATE COMP "Ain[2]" SITE "7";
LOCATE COMP "Ain[3]" SITE "4";
LOCATE COMP "Ain[4]" SITE "78";
LOCATE COMP "Ain[5]" SITE "84";
LOCATE COMP "Ain[6]" SITE "86";
LOCATE COMP "Ain[7]" SITE "8";
LOCATE COMP "BA[0]" SITE "58";
LOCATE COMP "BA[1]" SITE "60";
LOCATE COMP "C14M" SITE "62";
LOCATE COMP "CKEout" SITE "53";
LOCATE COMP "DQMH" SITE "49";
LOCATE COMP "DQML" SITE "48";
LOCATE COMP "Din[0]" SITE "96";
LOCATE COMP "Din[1]" SITE "97";
LOCATE COMP "Din[2]" SITE "98";
LOCATE COMP "Din[3]" SITE "9";
LOCATE COMP "Din[4]" SITE "1";
LOCATE COMP "Din[5]" SITE "99";
LOCATE COMP "Din[6]" SITE "88";
LOCATE COMP "Din[7]" SITE "87";
LOCATE COMP "Dout[0]" SITE "30";
LOCATE COMP "Dout[1]" SITE "27";
LOCATE COMP "Dout[2]" SITE "25";
LOCATE COMP "Dout[3]" SITE "28";
LOCATE COMP "Dout[4]" SITE "24";
LOCATE COMP "Dout[5]" SITE "21";
LOCATE COMP "Dout[6]" SITE "31";
LOCATE COMP "Dout[7]" SITE "32";
LOCATE COMP "LED" SITE "35";
LOCATE COMP "PHI1" SITE "85";
LOCATE COMP "RAout[0]" SITE "66";
LOCATE COMP "RAout[10]" SITE "64";
LOCATE COMP "RAout[11]" SITE "59";
LOCATE COMP "RAout[1]" SITE "68";
LOCATE COMP "RAout[2]" SITE "70";
LOCATE COMP "RAout[3]" SITE "74";
LOCATE COMP "RAout[4]" SITE "75";
LOCATE COMP "RAout[5]" SITE "71";
LOCATE COMP "RAout[6]" SITE "69";
LOCATE COMP "RAout[7]" SITE "67";
LOCATE COMP "RAout[8]" SITE "65";
LOCATE COMP "RAout[9]" SITE "63";
LOCATE COMP "RD[0]" SITE "36";
LOCATE COMP "RD[1]" SITE "37";
LOCATE COMP "RD[2]" SITE "38";
LOCATE COMP "RD[3]" SITE "39";
LOCATE COMP "RD[4]" SITE "40";
LOCATE COMP "RD[5]" SITE "41";
LOCATE COMP "RD[6]" SITE "42";
LOCATE COMP "RD[7]" SITE "43";
LOCATE COMP "Vout[0]" SITE "18";
LOCATE COMP "Vout[1]" SITE "15";
LOCATE COMP "Vout[2]" SITE "17";
LOCATE COMP "Vout[3]" SITE "13";
LOCATE COMP "Vout[4]" SITE "19";
LOCATE COMP "Vout[5]" SITE "16";
LOCATE COMP "Vout[6]" SITE "14";
LOCATE COMP "Vout[7]" SITE "12";
LOCATE COMP "nC07X" SITE "34";
LOCATE COMP "nCASout" SITE "52";
LOCATE COMP "nCSout" SITE "57";
LOCATE COMP "nDHGROE" SITE "47";
LOCATE COMP "nDOE" SITE "20";
LOCATE COMP "nEN80" SITE "82";
LOCATE COMP "nRASout" SITE "54";
LOCATE COMP "nRWEout" SITE "51";
LOCATE COMP "nVOE" SITE "10";
LOCATE COMP "nWE" SITE "29";
PAR: Place And Route Diamond (64-bit) 3.11.3.469.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Fri Jun 07 20:50:23 2024
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<PRE><A name="Par"></A>PAR: Place And Route Diamond (64-bit) 3.11.3.469.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&amp;T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Fri Jun 07 20:50:10 2024
C:/lscc/diamond/3.11_x64/ispfpga\bin\nt64\par -f RAM2E_LCMXO2_640HC_impl1.p2t
RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.dir
RAM2E_LCMXO2_640HC_impl1.prf -gui
Preference file: RAM2E_LCMXO2_640HC_impl1.prf.
<A name="par_cts"></A><B><U><big>Cost Table Summary</big></U></B>
Level/ Number Worst Timing Worst Timing Run NCD
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
---------- -------- ----- ------ ----------- ----------- ---- ------
5_1 * 0 55.718 0 0.379 0 16 Completed
* : Design saved.
Total (real) run time for 1-seed: 16 secs
par done!
Note: user must run &apos;Trace&apos; for timing closure signoff.
Lattice Place and Route Report for Design &quot;RAM2E_LCMXO2_640HC_impl1_map.ncd&quot;
Fri Jun 07 20:50:10 2024
<A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
PAR: Place And Route Diamond (64-bit) 3.11.3.469.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2E_LCMXO2_640HC_impl1.prf
Preference file: RAM2E_LCMXO2_640HC_impl1.prf.
Placement level-cost: 5-1.
Routing Iterations: 6
Loading design for application par from file RAM2E_LCMXO2_640HC_impl1_map.ncd.
Design name: RAM2E
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-640HC
Package: TQFP100
Performance: 4
Loading device for application par from file &apos;xo2c640.nph&apos; in environment: C:/lscc/diamond/3.11_x64/ispfpga.
Package Status: Final Version 1.39.
Performance Hardware Data Status: Final Version 34.4.
License checked out.
Ignore Preference Error(s): True
<A name="par_dus"></A><B><U><big>Device utilization summary:</big></U></B>
PIO (prelim) 70+4(JTAG)/80 93% used
70+4(JTAG)/79 94% bonded
IOLOGIC 22/80 27% used
SLICE 148/320 46% used
EFB 1/1 100% used
Number of Signals: 464
Number of Connections: 1330
Pin Constraint Summary:
70 out of 70 pins locked (100% locked).
The following 1 signal is selected to use the primary clock routing resources:
C14M_c (driver: C14M, clk load #: 85)
WARNING - par: Signal &quot;C14M_c&quot; is selected to use Primary clock resources. However, its driver comp &quot;C14M&quot; is located at &quot;62&quot;, which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
The following 1 signal is selected to use the secondary clock routing resources:
RWBank14 (driver: ram2e_ufm/SLICE_82, clk load #: 0, sr load #: 0, ce load #: 11)
No signal is selected as Global Set/Reset.
Starting Placer Phase 0.
............
Finished Placer Phase 0. REAL time: 0 secs
Starting Placer Phase 1.
....................
Placer score = 70995.
Finished Placer Phase 1. REAL time: 9 secs
Starting Placer Phase 2.
.
Placer score = 70831
Finished Placer Phase 2. REAL time: 9 secs
<A name="par_clk"></A><B><U><big>Clock Report</big></U></B>
Global Clock Resources:
CLK_PIN : 0 out of 8 (0%)
General PIO: 1 out of 80 (1%)
DCM : 0 out of 2 (0%)
DCC : 0 out of 8 (0%)
Global Clocks:
PRIMARY &quot;C14M_c&quot; from comp &quot;C14M&quot; on PIO site &quot;62 (PR5D)&quot;, clk load = 85
SECONDARY &quot;RWBank14&quot; from F0 on comp &quot;ram2e_ufm/SLICE_82&quot; on site &quot;R2C9D&quot;, clk load = 0, ce load = 11, sr load = 0
PRIMARY : 1 out of 8 (12%)
SECONDARY: 1 out of 8 (12%)
I/O Usage Summary (final):
70 + 4(JTAG) out of 80 (92.5%) PIO sites used.
70 + 4(JTAG) out of 79 (93.7%) bonded PIO sites used.
Number of PIO comps: 70; differential: 0.
Number of Vref pins used: 0.
I/O Bank Usage Summary:
+----------+----------------+------------+-----------+
| I/O Bank | Usage | Bank Vccio | Bank Vref |
+----------+----------------+------------+-----------+
| 0 | 11 / 19 ( 57%) | 3.3V | - |
| 1 | 20 / 20 (100%) | 3.3V | - |
| 2 | 19 / 20 ( 95%) | 3.3V | - |
| 3 | 20 / 20 (100%) | 3.3V | - |
+----------+----------------+------------+-----------+
Total placer CPU time: 7 secs
Dumping design to file RAM2E_LCMXO2_640HC_impl1.dir/5_1.ncd.
0 connections routed; 1330 unrouted.
Starting router resource preassignment
WARNING - par: The driver of primary clock net C14M_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
Signal=PHI1_c loads=5 clock_loads=3
Completed router resource preassignment. Real time: 14 secs
Start NBR router at 20:50:24 06/07/24
*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
in the earlier iterations. In each iteration, it tries to
solve the conflicts while keeping the critical connections
routed as short as possible. The routing process is said to
be completed when no conflicts exist and all connections
are routed.
Note: NBR uses a different method to calculate timing slacks. The
worst slack and total negative slack may not be the same as
that in TRCE report. You should always run TRCE to verify
your design.
*****************************************************************
Start NBR special constraint process at 20:50:24 06/07/24
Start NBR section for initial routing at 20:50:24 06/07/24
Level 4, iteration 1
15(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 55.730ns/0.000ns; real time: 14 secs
Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area at 75% usage is 0 (0.00%)
Start NBR section for normal routing at 20:50:25 06/07/24
Level 4, iteration 1
5(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 55.718ns/0.000ns; real time: 15 secs
Level 4, iteration 2
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 55.718ns/0.000ns; real time: 15 secs
Level 4, iteration 3
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 55.718ns/0.000ns; real time: 15 secs
Start NBR section for setup/hold timing optimization with effort level 3 at 20:50:25 06/07/24
Start NBR section for re-routing at 20:50:25 06/07/24
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 55.718ns/0.000ns; real time: 15 secs
Start NBR section for post-routing at 20:50:25 06/07/24
End NBR router with 0 unrouted connection
NBR Summary
-----------
Number of unrouted connections : 0 (0.00%)
Number of connections with timing violations : 0 (0.00%)
Estimated worst slack&lt;setup&gt; : 55.718ns
Timing score&lt;setup&gt; : 0
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
Signal=PHI1_c loads=5 clock_loads=3
Total CPU time 13 secs
Total REAL time: 16 secs
Completely routed.
End of route. 1330 routed (100.00%); 0 unrouted.
Hold time timing score: 0, hold timing errors: 0
Timing score: 0
Dumping design to file RAM2E_LCMXO2_640HC_impl1.dir/5_1.ncd.
All signals are completely routed.
PAR_SUMMARY::Run status = Completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst slack&lt;setup/&lt;ns&gt;&gt; = 55.718
PAR_SUMMARY::Timing score&lt;setup/&lt;ns&gt;&gt; = 0.000
PAR_SUMMARY::Worst slack&lt;hold /&lt;ns&gt;&gt; = 0.379
PAR_SUMMARY::Timing score&lt;hold /&lt;ns&gt;&gt; = 0.000
PAR_SUMMARY::Number of errors = 0
Total CPU time to completion: 13 secs
Total REAL time to completion: 16 secs
par done!
Note: user must run &apos;Trace&apos; for timing closure signoff.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&amp;T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
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55
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Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
# Written on Fri Jun 7 20:50:02 2024
##### FILES SYNTAX CHECKED ##############################################
Constraint File(s): "\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc"
#Run constraint checker to find more issues with constraints.
#########################################################################
No issues found in constraint syntax.
Clock Summary
*************
Start Requested Requested Clock Clock Clock
Level Clock Frequency Period Type Group Load
-----------------------------------------------------------------------------------------------
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 121
0 - System 100.0 MHz 10.000 system system_clkgroup 0
0 - RAM2E|PHI1 100.0 MHz 10.000 inferred Inferred_clkgroup_0 9
===============================================================================================
Clock Load Summary
******************
Clock Source Clock Pin Non-clock Pin Non-clock Pin
Clock Load Pin Seq Example Seq Example Comb Example
--------------------------------------------------------------------------------------------
C14M 121 C14M(port) RAT.C - un1_C14M.I[0](inv)
System 0 - - - -
RAM2E|PHI1 9 PHI1(port) RefReq.C S[0].D[0] un1_PHI1.I[0](inv)
============================================================================================

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<PRE><TABLE border=1 width=100% cellspacing=0 cellpadding=2><small>
<TR>
<TD align='center' BGCOLOR='#000099' COLSPAN='4'><SPAN style="COLOR: #FFFFFF"><B>RAM2E_LCMXO2_640HC project summary</B></SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Module Name:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">RAM2E_LCMXO2_640HC</SPAN></TD>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Synthesis:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">SynplifyPro</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Name:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">impl1</SPAN></TD>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Strategy Name:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">Strategy1</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Last Process:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">JEDEC File</SPAN></TD>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">State:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">Passed</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Target Device:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">LCMXO2-640HC-4TG100C</SPAN></TD>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Device Family:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">MachXO2</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Device Type:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">LCMXO2-640HC</SPAN></TD>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Package Type:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">TQFP100</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Performance grade:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">4</SPAN></TD>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Operating conditions:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">COM</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Logic preference file:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">RAM2E-LCMXO2.lpf</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Physical Preference file:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">impl1/RAM2E_LCMXO2_640HC_impl1.prf</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Product Version:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">3.11.3.469</SPAN></TD>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Patch Version:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000"></SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Updated:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2024/06/07 20:50:30</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Location:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/impl1</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Project File:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC.ldf</SPAN></TD>
</TR>
</small></TABLE>
<BR>
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<BR>
<BR>
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<PRE><A name="Syn"></A><B><U><big>Synthesis Report</big></U></B>
#Build: Synplify Pro (R) N-2018.03L-SP1-1, Build 443R, Apr 1 2019
#install: C:\lscc\diamond\3.11_x64\synpbase
#OS: Windows 8 6.2
#Hostname: ZANEMACWIN11
# Fri Jun 7 20:50:00 2024
#Implementation: impl1
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys HDL Compiler, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Verilog Compiler, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v" (library work)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\pmi_def.v" (library work)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v" (library work)
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v" (library work)
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\REFB.v" (library work)
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\DHGR-ON.v" (library work)
Verilog syntax check successful!
Selecting top level module RAM2E
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
Running optimization stage 1 on VHI .......
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
Running optimization stage 1 on VLO .......
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
Running optimization stage 1 on EFB .......
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
Running optimization stage 1 on REFB .......
@W: CL318 :"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\REFB.v":9:14:9:21|*Output wb_dat_o has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output.
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v":1:7:1:15|Synthesizing module RAM2E_UFM in library work.
Running optimization stage 1 on RAM2E_UFM .......
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\DHGR-ON.v":1:7:1:10|Synthesizing module DHGR in library work.
Running optimization stage 1 on DHGR .......
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v":1:7:1:11|Synthesizing module RAM2E in library work.
Running optimization stage 1 on RAM2E .......
Running optimization stage 2 on RAM2E .......
@N: CL159 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v":11:15:11:19|Input nWE80 is unused.
Running optimization stage 2 on DHGR .......
Running optimization stage 2 on RAM2E_UFM .......
Running optimization stage 2 on REFB .......
Running optimization stage 2 on EFB .......
Running optimization stage 2 on VLO .......
Running optimization stage 2 on VHI .......
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Fri Jun 7 20:50:00 2024
###########################################################]
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Fri Jun 7 20:50:00 2024
###########################################################]
For a summary of runtime and memory usage for all design units, please see file:
==========================================================
@L: A:\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_comp.rt.csv
@END
At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Fri Jun 7 20:50:00 2024
###########################################################]
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Database state : \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\synwork\|impl1
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
@N|Running in 64-bit mode
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
Process completed successfully.
# Fri Jun 7 20:50:02 2024
###########################################################]
Premap Report
# Fri Jun 7 20:50:02 2024
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Lattice Technology Pre-mapping, Version maplat2018q2p1, Build 055R, Built Apr 3 2019 09:51:54
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
Reading constraint file: \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
@N: MF284 |Setting synthesis effort to medium for the design
@L: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1_scck.rpt
Printing clock summary report in "\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1_scck.rpt" file
@N: MF916 |Option synthesis_strategy=base is enabled.
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
@N: MF284 |Setting synthesis effort to medium for the design
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":21:4:21:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
@N: MH105 |UMR3 is only supported for HAPS-80.
@N: MH105 |UMR3 is only supported for HAPS-80.
@N: BN115 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":140:9:140:12|Removing instance dhgr (in view: work.RAM2E(verilog)) of type view:work.DHGR(verilog) because it does not drive other instances.
syn_allowed_resources : blockrams=2 set on top level netlist RAM2E
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
Clock Summary
******************
Start Requested Requested Clock Clock Clock
Level Clock Frequency Period Type Group Load
-----------------------------------------------------------------------------------------------
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 121
0 - System 100.0 MHz 10.000 system system_clkgroup 0
0 - RAM2E|PHI1 100.0 MHz 10.000 inferred Inferred_clkgroup_0 9
===============================================================================================
Clock Load Summary
***********************
Clock Source Clock Pin Non-clock Pin Non-clock Pin
Clock Load Pin Seq Example Seq Example Comb Example
--------------------------------------------------------------------------------------------
C14M 121 C14M(port) RAT.C - un1_C14M.I[0](inv)
System 0 - - - -
RAM2E|PHI1 9 PHI1(port) RefReq.C S[0].D[0] un1_PHI1.I[0](inv)
============================================================================================
@W: MT529 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":20:19:20:24|Found inferred clock RAM2E|PHI1 which controls 9 sequential elements including PHI1r. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed: 0
@S |Clock Optimization Summary
#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
2 non-gated/non-generated clock tree(s) driving 125 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
---------------------------------------------------------------------------------------
@KP:ckid0_0 C14M port 121 PHI1r
@KP:ckid0_1 PHI1 Unconstrained_port 4 RC[2:0]
=======================================================================================
##### END OF CLOCK OPTIMIZATION REPORT ######
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
Finished Pre Mapping Phase.
Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
None
None
Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
Pre-mapping successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 143MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Jun 7 20:50:03 2024
###########################################################]
Map & Optimize Report
# Fri Jun 7 20:50:03 2024
Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03L-SP1-1
Install: C:\lscc\diamond\3.11_x64\synpbase
OS: Windows 6.2
Hostname: ZANEMACWIN11
Implementation : impl1
Synopsys Lattice Technology Mapper, Version maplat2018q2p1, Build 055R, Built Apr 3 2019 09:51:54
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
@N: MF284 |Setting synthesis effort to medium for the design
@N: MF916 |Option synthesis_strategy=base is enabled.
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
@N: MF284 |Setting synthesis effort to medium for the design
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
Available hyper_sources - for debug and ip models
None Found
@N: FX493 |Applying initial value "00000000" on instance RWBank[7:0].
@N: FX493 |Applying initial value "0000" on instance S[3:0].
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)
@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":14:23:14:28|Found counter in view:work.RAM2E(verilog) instance FS[15:0]
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 142MB)
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:01s 6.90ns 281 / 125
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":171:4:171:9|Boundary register BA_1_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":171:4:171:9|Boundary register BA_0_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 158MB peak: 160MB)
Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 122MB peak: 160MB)
Writing Analyst data base \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_m.srm
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 158MB peak: 160MB)
Writing EDIF Netlist and constraint files
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1.edi
N-2018.03L-SP1-1
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 162MB peak: 164MB)
Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 164MB)
@W: MT246 :"\\mac\icloud\repos\ram2e\cpld\lcmxo2-640hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@N: MT615 |Found clock C14M with period 69.84ns
@W: MT420 |Found inferred clock RAM2E|PHI1 with period 10.00ns. Please declare a user-defined clock on port PHI1.
##### START OF TIMING REPORT #####[
# Timing Report written on Fri Jun 7 20:50:06 2024
#
Top view: RAM2E
Requested Frequency: 14.3 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s): \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
Performance Summary
*******************
Worst slack in design: 6.897
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
----------------------------------------------------------------------------------------------------------------------
C14M 14.3 MHz 112.1 MHz 69.841 8.918 31.599 declared default_clkgroup
RAM2E|PHI1 100.0 MHz 322.2 MHz 10.000 3.103 6.897 inferred Inferred_clkgroup_0
System 100.0 MHz NA 10.000 NA 67.088 system system_clkgroup
======================================================================================================================
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
----------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
----------------------------------------------------------------------------------------------------------------
System C14M | 69.841 67.088 | No paths - | No paths - | No paths -
C14M System | 69.841 68.797 | No paths - | No paths - | No paths -
C14M C14M | 69.841 60.923 | No paths - | 34.920 31.599 | No paths -
RAM2E|PHI1 C14M | No paths - | No paths - | No paths - | Diff grp -
RAM2E|PHI1 RAM2E|PHI1 | No paths - | 10.000 6.897 | No paths - | No paths -
================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Interface Information
*********************
No IO constraint found
====================================
Detailed Report for Clock: C14M
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------
S[2] C14M FD1S3AX Q S[2] 1.366 31.599
S[3] C14M FD1S3AX Q S[3] 1.345 31.619
S[1] C14M FD1S3AX Q S[1] 1.344 31.800
S[0] C14M FD1S3AX Q S[0] 1.305 31.838
RA[0] C14M FD1P3AX Q RA[0] 1.108 33.707
RA[3] C14M FD1P3AX Q RA[3] 1.108 33.707
RA[1] C14M FD1P3AX Q RA[1] 1.044 33.771
RA[2] C14M FD1P3AX Q RA[2] 1.044 33.771
RA[4] C14M FD1P3AX Q RA[4] 1.044 33.771
RA[5] C14M FD1P3AX Q RA[5] 1.044 33.771
===========================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
-----------------------------------------------------------------------------------
VOE_i_0io C14M OFS1P3IX CD N_530 34.118 31.599
VOE_i_0io C14M OFS1P3IX D VOE_ic_i 35.009 31.800
Vout_0io[0] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[1] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[2] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[3] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[4] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[5] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[6] C14M OFS1P3DX SP Vout3 34.449 32.634
Vout_0io[7] C14M OFS1P3DX SP Vout3 34.449 32.634
===================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 34.920
- Setup time: 0.803
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 34.118
- Propagation time: 2.519
- Clock delay at starting point: 0.000 (ideal)
= Slack (non-critical) : 31.599
Number of logic level(s): 1
Starting point: S[2] / Q
Ending point: VOE_i_0io / CD
The start point is clocked by C14M [rising] on pin CK
The end point is clocked by C14M [falling] on pin SCLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
------------------------------------------------------------------------------------------------------------
S[2] FD1S3AX Q Out 1.366 1.366 -
S[2] Net - - - - 58
ram2e_ufm.un1_wb_adr_0_sqmuxa_2_0_a2_0[0] ORCALUT4 A In 0.000 1.366 -
ram2e_ufm.un1_wb_adr_0_sqmuxa_2_0_a2_0[0] ORCALUT4 Z Out 1.153 2.519 -
N_530 Net - - - - 3
VOE_i_0io OFS1P3IX CD In 0.000 2.519 -
============================================================================================================
====================================
Detailed Report for Clock: RAM2E|PHI1
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------
RC[1] RAM2E|PHI1 FD1S3IX Q RC[1] 1.148 6.897
RC[2] RAM2E|PHI1 FD1S3IX Q RC[2] 1.108 6.937
RC[0] RAM2E|PHI1 FD1S3IX Q RC[0] 1.148 8.179
===========================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------
RC[0] RAM2E|PHI1 FD1S3IX CD RC7 9.197 6.897
RC[1] RAM2E|PHI1 FD1S3IX CD RC7 9.197 6.897
RC[2] RAM2E|PHI1 FD1S3IX CD RC7 9.197 6.897
RC[0] RAM2E|PHI1 FD1S3IX D RC_i[0] 9.894 8.179
RC[1] RAM2E|PHI1 FD1S3IX D RC_RNO[1] 10.089 8.324
RC[2] RAM2E|PHI1 FD1S3IX D RC_RNO[2] 10.089 8.324
RefReq RAM2E|PHI1 FD1S3AX D RefReq_2 10.089 8.324
================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 10.000
- Setup time: 0.803
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 9.197
- Propagation time: 2.301
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : 6.897
Number of logic level(s): 1
Starting point: RC[1] / Q
Ending point: RC[0] / CD
The start point is clocked by RAM2E|PHI1 [falling] on pin CK
The end point is clocked by RAM2E|PHI1 [falling] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------
RC[1] FD1S3IX Q Out 1.148 1.148 -
RC[1] Net - - - - 4
RC7 ORCALUT4 A In 0.000 1.148 -
RC7 ORCALUT4 Z Out 1.153 2.301 -
RC7 Net - - - - 3
RC[0] FD1S3IX CD In 0.000 2.301 -
=================================================================================
====================================
Detailed Report for Clock: System
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------------------------------
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBACKO wb_ack 0.000 67.088
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO0 wb_dato[0] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO2 wb_dato[2] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO3 wb_dato[3] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO4 wb_dato[4] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO5 wb_dato[5] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO6 wb_dato[6] 0.000 69.313
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO7 wb_dato[7] 0.000 69.313
===================================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
----------------------------------------------------------------------------------------
ram2e_ufm.RWMask[0] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[1] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[2] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[3] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[4] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[5] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[6] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.RWMask[7] System FD1P3AX SP N_104 69.369 67.088
ram2e_ufm.LEDEN System FD1P3AX SP N_98 69.369 67.736
ram2e_ufm.wb_cyc_stb System FD1P3AX SP N_111 69.369 67.736
========================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 69.841
- Setup time: 0.472
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 69.369
- Propagation time: 2.282
- Clock delay at starting point: 0.000 (ideal)
- Estimated clock delay at start point: -0.000
= Slack (non-critical) : 67.088
Number of logic level(s): 2
Starting point: ram2e_ufm.ufmefb.EFBInst_0 / WBACKO
Ending point: ram2e_ufm.RWMask[0] / SP
The start point is clocked by System [rising]
The end point is clocked by C14M [rising] on pin CK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
----------------------------------------------------------------------------------------------------------------
ram2e_ufm.ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 -
wb_ack Net - - - - 5
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] ORCALUT4 B In 0.000 0.000 -
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] ORCALUT4 Z Out 1.017 1.017 -
un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] Net - - - - 1
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 D In 0.000 1.017 -
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 Z Out 1.265 2.282 -
N_104 Net - - - - 8
ram2e_ufm.RWMask[0] FD1P3AX SP In 0.000 2.282 -
================================================================================================================
##### END OF TIMING REPORT #####]
Timing exceptions that could not be applied
None
Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 164MB)
Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 164MB)
---------------------------------------
Resource Usage Report
Part: lcmxo2_640hc-4
Register bits: 125 of 640 (20%)
PIC Latch: 0
I/O cells: 70
Details:
BB: 8
CCU2D: 9
EFB: 1
FD1P3AX: 58
FD1P3IX: 1
FD1S3AX: 31
FD1S3AY: 4
FD1S3IX: 9
GSR: 1
IB: 21
IFS1P3DX: 1
INV: 4
OB: 41
OFS1P3BX: 6
OFS1P3DX: 12
OFS1P3IX: 3
ORCALUT4: 275
PUR: 1
VHI: 3
VLO: 3
Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 33MB peak: 164MB)
Process took 0h:00m:03s realtime, 0h:00m:03s cputime
# Fri Jun 7 20:50:07 2024
###########################################################]
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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE Report>
<ReportView version="2.0">
<Implement name="impl1">
<ToolReport id="tooldec" path="" status="0"/>
<ToolReport id="toolhle_genhierarchy" path="" status="0"/>
<ToolReport id="toolpio" path="" status="0"/>
<ToolReport id="toolsso" path="" status="0"/>
</Implement>
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2019 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
# Date created = 07:26:23 August 20, 2023
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "19.1"
DATE = "07:26:23 August 20, 2023"
# Revisions
PROJECT_REVISION = "RAM2E"

258
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@ -0,0 +1,258 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2019 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
# Date created = 07:26:23 August 20, 2023
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# RAM2E_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "MAX II"
set_global_assignment -name DEVICE EPM240T100C5
set_global_assignment -name TOP_LEVEL_ENTITY RAM2E
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 19.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "07:26:23 AUGUST 20, 2023"
set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name NUM_PARALLEL_PROCESSORS 4
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS OUTPUT DRIVING GROUND"
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V
set_location_assignment PIN_12 -to C14M
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to C14M
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to C14M
set_location_assignment PIN_37 -to PHI1
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PHI1
set_instance_assignment -name PAD_TO_CORE_DELAY 1 -to PHI1
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to PHI1
set_location_assignment PIN_51 -to nWE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nWE
set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nWE
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nWE
set_location_assignment PIN_28 -to nEN80
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nEN80
set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nEN80
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nEN80
set_location_assignment PIN_33 -to nWE80
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nWE80
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nWE80
set_location_assignment PIN_52 -to nC07X
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nC07X
set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nC07X
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nC07X
set_location_assignment PIN_56 -to Ain[0]
set_location_assignment PIN_54 -to Ain[1]
set_location_assignment PIN_43 -to Ain[2]
set_location_assignment PIN_47 -to Ain[3]
set_location_assignment PIN_44 -to Ain[4]
set_location_assignment PIN_34 -to Ain[5]
set_location_assignment PIN_39 -to Ain[6]
set_location_assignment PIN_53 -to Ain[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Ain
set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to Ain
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Ain
set_location_assignment PIN_38 -to Din[0]
set_location_assignment PIN_40 -to Din[1]
set_location_assignment PIN_42 -to Din[2]
set_location_assignment PIN_41 -to Din[3]
set_location_assignment PIN_48 -to Din[4]
set_location_assignment PIN_49 -to Din[5]
set_location_assignment PIN_36 -to Din[6]
set_location_assignment PIN_35 -to Din[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Din
set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to Din
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Din
set_location_assignment PIN_55 -to nDOE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nDOE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nDOE
set_instance_assignment -name SLOW_SLEW_RATE ON -to nDOE
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nDOE
set_location_assignment PIN_77 -to Dout[0]
set_location_assignment PIN_76 -to Dout[1]
set_location_assignment PIN_74 -to Dout[2]
set_location_assignment PIN_75 -to Dout[3]
set_location_assignment PIN_73 -to Dout[4]
set_location_assignment PIN_72 -to Dout[5]
set_location_assignment PIN_84 -to Dout[6]
set_location_assignment PIN_85 -to Dout[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Dout
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to Dout
set_instance_assignment -name SLOW_SLEW_RATE ON -to Dout
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Dout
set_location_assignment PIN_50 -to nVOE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nVOE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nVOE
set_instance_assignment -name SLOW_SLEW_RATE OFF -to nVOE
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nVOE
set_location_assignment PIN_70 -to Vout[0]
set_location_assignment PIN_67 -to Vout[1]
set_location_assignment PIN_69 -to Vout[2]
set_location_assignment PIN_62 -to Vout[3]
set_location_assignment PIN_71 -to Vout[4]
set_location_assignment PIN_68 -to Vout[5]
set_location_assignment PIN_58 -to Vout[6]
set_location_assignment PIN_57 -to Vout[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Vout
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to Vout
set_instance_assignment -name SLOW_SLEW_RATE ON -to Vout
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to Vout
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Vout
set_location_assignment PIN_4 -to CKEout
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CKEout
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to CKEout
set_instance_assignment -name SLOW_SLEW_RATE ON -to CKEout
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CKEout
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to CKEout
set_location_assignment PIN_8 -to nCSout
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCSout
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nCSout
set_instance_assignment -name SLOW_SLEW_RATE ON -to nCSout
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nCSout
set_location_assignment PIN_2 -to nRWEout
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRWEout
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRWEout
set_instance_assignment -name SLOW_SLEW_RATE ON -to nRWEout
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRWEout
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRWEout
set_location_assignment PIN_5 -to nRASout
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRASout
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRASout
set_instance_assignment -name SLOW_SLEW_RATE ON -to nRASout
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRASout
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRASout
set_location_assignment PIN_3 -to nCASout
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCASout
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nCASout
set_instance_assignment -name SLOW_SLEW_RATE ON -to nCASout
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nCASout
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nCASout
set_location_assignment PIN_6 -to BA[0]
set_location_assignment PIN_14 -to BA[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to BA
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to BA
set_instance_assignment -name SLOW_SLEW_RATE ON -to BA
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to BA
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to BA
set_location_assignment PIN_18 -to RAout[0]
set_location_assignment PIN_20 -to RAout[1]
set_location_assignment PIN_30 -to RAout[2]
set_location_assignment PIN_27 -to RAout[3]
set_location_assignment PIN_26 -to RAout[4]
set_location_assignment PIN_29 -to RAout[5]
set_location_assignment PIN_21 -to RAout[6]
set_location_assignment PIN_19 -to RAout[7]
set_location_assignment PIN_17 -to RAout[8]
set_location_assignment PIN_15 -to RAout[9]
set_location_assignment PIN_16 -to RAout[10]
set_location_assignment PIN_7 -to RAout[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RAout
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RAout
set_instance_assignment -name SLOW_SLEW_RATE ON -to RAout
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to RAout
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RAout
set_location_assignment PIN_100 -to DQMH
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DQMH
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to DQMH
set_instance_assignment -name SLOW_SLEW_RATE ON -to DQMH
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DQMH
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to DQMH
set_location_assignment PIN_98 -to DQML
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DQML
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to DQML
set_instance_assignment -name SLOW_SLEW_RATE ON -to DQML
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DQML
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to DQML
set_location_assignment PIN_97 -to RD[0]
set_location_assignment PIN_90 -to RD[1]
set_location_assignment PIN_99 -to RD[2]
set_location_assignment PIN_89 -to RD[3]
set_location_assignment PIN_91 -to RD[4]
set_location_assignment PIN_92 -to RD[5]
set_location_assignment PIN_95 -to RD[6]
set_location_assignment PIN_96 -to RD[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RD
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RD
set_instance_assignment -name SLOW_SLEW_RATE ON -to RD
set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to RD
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to RD
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RD
set_location_assignment PIN_88 -to LED
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LED
set_instance_assignment -name SLOW_SLEW_RATE ON -to LED
set_location_assignment PIN_87 -to nDHGROE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nDHGROE
set_instance_assignment -name SLOW_SLEW_RATE ON -to nDHGROE
set_global_assignment -name VERILOG_FILE ../RAM2E.v
set_global_assignment -name VERILOG_FILE "../UFM-MAX.v"
set_global_assignment -name VERILOG_FILE "../DHGR-OFF.v"
set_global_assignment -name QIP_FILE UFM.qip
set_global_assignment -name MIF_FILE ../RAM2E.mif
set_global_assignment -name SDC_FILE ../RAM2E.sdc
set_global_assignment -name SDC_FILE "../RAM2E-MAX.sdc"
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
set_global_assignment -name ENABLE_OCT_DONE OFF
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name GENERATE_SVF_FILE ON

4
CPLD/MAXII-NODHGR/UFM.qip Normal file
View File

@ -0,0 +1,4 @@
set_global_assignment -name IP_TOOL_NAME "ALTUFM_NONE Intel FPGA IP"
set_global_assignment -name IP_TOOL_VERSION "19.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX II}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "UFM.v"]

269
CPLD/MAXII-NODHGR/UFM.v Normal file
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@ -0,0 +1,269 @@
// megafunction wizard: %ALTUFM_NONE Intel FPGA IP%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTUFM_NONE
// ============================================================
// File Name: UFM.v
// Megafunction Name(s):
// ALTUFM_NONE
//
// Simulation Library Files(s):
// maxii
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 19.1.0 Build 670 09/22/2019 SJ Lite Edition
// ************************************************************
//Copyright (C) 2019 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.
//altufm_none CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="MAX II" ERASE_TIME=500000000 LPM_FILE="../RAM2E.mif" OSC_FREQUENCY=180000 PORT_ARCLKENA="PORT_UNUSED" PORT_DRCLKENA="PORT_UNUSED" PROGRAM_TIME=1600000 WIDTH_UFM_ADDRESS=9 arclk ardin arshft busy drclk drdin drdout drshft erase osc oscena program rtpbusy
//VERSION_BEGIN 19.1 cbx_a_gray2bin 2019:09:22:11:00:27:SJ cbx_a_graycounter 2019:09:22:11:00:27:SJ cbx_altufm_none 2019:09:22:11:00:28:SJ cbx_cycloneii 2019:09:22:11:00:28:SJ cbx_lpm_add_sub 2019:09:22:11:00:28:SJ cbx_lpm_compare 2019:09:22:11:00:28:SJ cbx_lpm_counter 2019:09:22:11:00:28:SJ cbx_lpm_decode 2019:09:22:11:00:28:SJ cbx_lpm_mux 2019:09:22:11:00:28:SJ cbx_maxii 2019:09:22:11:00:28:SJ cbx_mgl 2019:09:22:11:02:15:SJ cbx_nadder 2019:09:22:11:00:28:SJ cbx_stratix 2019:09:22:11:00:28:SJ cbx_stratixii 2019:09:22:11:00:28:SJ cbx_util_mgl 2019:09:22:11:00:28:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = maxii_ufm 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module UFM_altufm_none_lbr
(
arclk,
ardin,
arshft,
busy,
drclk,
drdin,
drdout,
drshft,
erase,
osc,
oscena,
program,
rtpbusy) ;
input arclk;
input ardin;
input arshft;
output busy;
input drclk;
input drdin;
output drdout;
input drshft;
input erase;
output osc;
input oscena;
input program;
output rtpbusy;
wire wire_maxii_ufm_block1_bgpbusy;
wire wire_maxii_ufm_block1_busy;
wire wire_maxii_ufm_block1_drdout;
wire wire_maxii_ufm_block1_osc;
wire ufm_arclk;
wire ufm_ardin;
wire ufm_arshft;
wire ufm_bgpbusy;
wire ufm_busy;
wire ufm_drclk;
wire ufm_drdin;
wire ufm_drdout;
wire ufm_drshft;
wire ufm_erase;
wire ufm_osc;
wire ufm_oscena;
wire ufm_program;
maxii_ufm maxii_ufm_block1
(
.arclk(ufm_arclk),
.ardin(ufm_ardin),
.arshft(ufm_arshft),
.bgpbusy(wire_maxii_ufm_block1_bgpbusy),
.busy(wire_maxii_ufm_block1_busy),
.drclk(ufm_drclk),
.drdin(ufm_drdin),
.drdout(wire_maxii_ufm_block1_drdout),
.drshft(ufm_drshft),
.erase(ufm_erase),
.osc(wire_maxii_ufm_block1_osc),
.oscena(ufm_oscena),
.program(ufm_program)
// synopsys translate_off
,
.ctrl_bgpbusy(1'b0),
.devclrn(1'b1),
.devpor(1'b1),
.sbdin(1'b0),
.sbdout()
// synopsys translate_on
);
defparam
maxii_ufm_block1.address_width = 9,
maxii_ufm_block1.erase_time = 500000000,
maxii_ufm_block1.init_file = "../RAM2E.mif",
maxii_ufm_block1.mem1 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem10 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem11 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem12 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem13 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem14 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem15 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem16 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem2 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem3 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem4 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem5 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem6 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem7 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem8 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem9 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.osc_sim_setting = 180000,
maxii_ufm_block1.program_time = 1600000,
maxii_ufm_block1.lpm_type = "maxii_ufm";
assign
busy = ufm_busy,
drdout = ufm_drdout,
osc = ufm_osc,
rtpbusy = ufm_bgpbusy,
ufm_arclk = arclk,
ufm_ardin = ardin,
ufm_arshft = arshft,
ufm_bgpbusy = wire_maxii_ufm_block1_bgpbusy,
ufm_busy = wire_maxii_ufm_block1_busy,
ufm_drclk = drclk,
ufm_drdin = drdin,
ufm_drdout = wire_maxii_ufm_block1_drdout,
ufm_drshft = drshft,
ufm_erase = erase,
ufm_osc = wire_maxii_ufm_block1_osc,
ufm_oscena = oscena,
ufm_program = program;
endmodule //UFM_altufm_none_lbr
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module UFM (
arclk,
ardin,
arshft,
drclk,
drdin,
drshft,
erase,
oscena,
program,
busy,
drdout,
osc,
rtpbusy);
input arclk;
input ardin;
input arshft;
input drclk;
input drdin;
input drshft;
input erase;
input oscena;
input program;
output busy;
output drdout;
output osc;
output rtpbusy;
wire sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire sub_wire3;
wire busy = sub_wire0;
wire drdout = sub_wire1;
wire osc = sub_wire2;
wire rtpbusy = sub_wire3;
UFM_altufm_none_lbr UFM_altufm_none_lbr_component (
.arclk (arclk),
.ardin (ardin),
.arshft (arshft),
.drclk (drclk),
.drdin (drdin),
.drshft (drshft),
.erase (erase),
.oscena (oscena),
.program (program),
.busy (sub_wire0),
.drdout (sub_wire1),
.osc (sub_wire2),
.rtpbusy (sub_wire3));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX II"
// Retrieval info: CONSTANT: ERASE_TIME NUMERIC "500000000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX II"
// Retrieval info: CONSTANT: LPM_FILE STRING "../RAM2E.mif"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altufm_none"
// Retrieval info: CONSTANT: OSC_FREQUENCY NUMERIC "180000"
// Retrieval info: CONSTANT: PORT_ARCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_DRCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PROGRAM_TIME NUMERIC "1600000"
// Retrieval info: CONSTANT: WIDTH_UFM_ADDRESS NUMERIC "9"
// Retrieval info: USED_PORT: arclk 0 0 0 0 INPUT NODEFVAL "arclk"
// Retrieval info: CONNECT: @arclk 0 0 0 0 arclk 0 0 0 0
// Retrieval info: USED_PORT: ardin 0 0 0 0 INPUT NODEFVAL "ardin"
// Retrieval info: CONNECT: @ardin 0 0 0 0 ardin 0 0 0 0
// Retrieval info: USED_PORT: arshft 0 0 0 0 INPUT NODEFVAL "arshft"
// Retrieval info: CONNECT: @arshft 0 0 0 0 arshft 0 0 0 0
// Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy"
// Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
// Retrieval info: USED_PORT: drclk 0 0 0 0 INPUT NODEFVAL "drclk"
// Retrieval info: CONNECT: @drclk 0 0 0 0 drclk 0 0 0 0
// Retrieval info: USED_PORT: drdin 0 0 0 0 INPUT NODEFVAL "drdin"
// Retrieval info: CONNECT: @drdin 0 0 0 0 drdin 0 0 0 0
// Retrieval info: USED_PORT: drdout 0 0 0 0 OUTPUT NODEFVAL "drdout"
// Retrieval info: CONNECT: drdout 0 0 0 0 @drdout 0 0 0 0
// Retrieval info: USED_PORT: drshft 0 0 0 0 INPUT NODEFVAL "drshft"
// Retrieval info: CONNECT: @drshft 0 0 0 0 drshft 0 0 0 0
// Retrieval info: USED_PORT: erase 0 0 0 0 INPUT NODEFVAL "erase"
// Retrieval info: CONNECT: @erase 0 0 0 0 erase 0 0 0 0
// Retrieval info: USED_PORT: osc 0 0 0 0 OUTPUT NODEFVAL "osc"
// Retrieval info: CONNECT: osc 0 0 0 0 @osc 0 0 0 0
// Retrieval info: USED_PORT: oscena 0 0 0 0 INPUT NODEFVAL "oscena"
// Retrieval info: CONNECT: @oscena 0 0 0 0 oscena 0 0 0 0
// Retrieval info: USED_PORT: program 0 0 0 0 INPUT NODEFVAL "program"
// Retrieval info: CONNECT: @program 0 0 0 0 program 0 0 0 0
// Retrieval info: USED_PORT: rtpbusy 0 0 0 0 OUTPUT NODEFVAL "rtpbusy"
// Retrieval info: CONNECT: rtpbusy 0 0 0 0 @rtpbusy 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.qip TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.bsf FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM_inst.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM_bb.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.inc FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.cmp FALSE TRUE
// Retrieval info: LIB_FILE: maxii

102
CPLD/MAXII-NODHGR/output_files/RAM2E.asm.rpt Normal file
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Assembler report for RAM2E
Sat Jun 08 01:44:21 2024
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: /Repos/RAM2E/CPLD/MAXII-NODHGR/output_files/RAM2E.pof
6. Assembler Device Options: /Repos/RAM2E/CPLD/MAXII-NODHGR/output_files/RAM2E.svf
7. Assembler Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2019 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Sat Jun 08 01:44:21 2024 ;
; Revision Name ; RAM2E ;
; Top-level Entity Name ; RAM2E ;
; Family ; MAX II ;
; Device ; EPM240T100C5 ;
+-----------------------+---------------------------------------+
+----------------------------------+
; Assembler Settings ;
+--------+---------+---------------+
; Option ; Setting ; Default Value ;
+--------+---------+---------------+
+-------------------------------------------------------+
; Assembler Generated Files ;
+-------------------------------------------------------+
; File Name ;
+-------------------------------------------------------+
; /Repos/RAM2E/CPLD/MAXII-NODHGR/output_files/RAM2E.pof ;
; /Repos/RAM2E/CPLD/MAXII-NODHGR/output_files/RAM2E.svf ;
+-------------------------------------------------------+
+---------------------------------------------------------------------------------+
; Assembler Device Options: /Repos/RAM2E/CPLD/MAXII-NODHGR/output_files/RAM2E.pof ;
+----------------+----------------------------------------------------------------+
; Option ; Setting ;
+----------------+----------------------------------------------------------------+
; JTAG usercode ; 0x00164439 ;
; Checksum ; 0x00164839 ;
+----------------+----------------------------------------------------------------+
+---------------------------------------------------------------------------------+
; Assembler Device Options: /Repos/RAM2E/CPLD/MAXII-NODHGR/output_files/RAM2E.svf ;
+-----------+---------------------------------------------------------------------+
; Option ; Setting ;
+-----------+---------------------------------------------------------------------+
; SVF file ; ;
+-----------+---------------------------------------------------------------------+
+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus Prime Assembler
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Info: Processing started: Sat Jun 08 01:44:20 2024
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2E-MAXII -c RAM2E
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 13099 megabytes
Info: Processing ended: Sat Jun 08 01:44:21 2024
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01

1
CPLD/MAXII-NODHGR/output_files/RAM2E.done Normal file
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Sat Jun 08 01:44:26 2024

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