mirror of
https://github.com/garrettsworkshop/RAM2E.git
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741 lines
36 KiB
Plaintext
741 lines
36 KiB
Plaintext
#Build: Synplify Pro (R) N-2018.03L-SP1-1, Build 443R, Apr 1 2019
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#install: C:\lscc\diamond\3.11_x64\synpbase
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#OS: Windows 8 6.2
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#Hostname: ZANEMACWIN11
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# Fri Jun 7 20:50:04 2024
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#Implementation: impl1
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Copyright (C) 1994-2018 Synopsys, Inc.
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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
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and may only be used pursuant to the terms and conditions of a written license agreement
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with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
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Synopsys software or the associated documentation is strictly prohibited.
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Tool: Synplify Pro (R)
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Build: N-2018.03L-SP1-1
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Install: C:\lscc\diamond\3.11_x64\synpbase
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OS: Windows 6.2
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Hostname: ZANEMACWIN11
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Implementation : impl1
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Synopsys HDL Compiler, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
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@N|Running in 64-bit mode
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Copyright (C) 1994-2018 Synopsys, Inc.
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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
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and may only be used pursuant to the terms and conditions of a written license agreement
|
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with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
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Synopsys software or the associated documentation is strictly prohibited.
|
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Tool: Synplify Pro (R)
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Build: N-2018.03L-SP1-1
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Install: C:\lscc\diamond\3.11_x64\synpbase
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OS: Windows 6.2
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Hostname: ZANEMACWIN11
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Implementation : impl1
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Synopsys Verilog Compiler, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
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@N|Running in 64-bit mode
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@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v" (library work)
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@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\pmi_def.v" (library work)
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@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
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@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
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@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
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@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
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@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v" (library work)
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@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v" (library work)
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@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\REFB.v" (library work)
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@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\DHGR-ON.v" (library work)
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Verilog syntax check successful!
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Selecting top level module RAM2E
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@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
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Running optimization stage 1 on VHI .......
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@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
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Running optimization stage 1 on VLO .......
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@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
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Running optimization stage 1 on EFB .......
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@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
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Running optimization stage 1 on REFB .......
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@W: CL318 :"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\REFB.v":9:14:9:21|*Output wb_dat_o has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output.
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@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v":1:7:1:15|Synthesizing module RAM2E_UFM in library work.
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Running optimization stage 1 on RAM2E_UFM .......
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@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\DHGR-ON.v":1:7:1:10|Synthesizing module DHGR in library work.
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Running optimization stage 1 on DHGR .......
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@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v":1:7:1:11|Synthesizing module RAM2E in library work.
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Running optimization stage 1 on RAM2E .......
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Running optimization stage 2 on RAM2E .......
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@N: CL159 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v":11:15:11:19|Input nWE80 is unused.
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Running optimization stage 2 on DHGR .......
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Running optimization stage 2 on RAM2E_UFM .......
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Running optimization stage 2 on REFB .......
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Running optimization stage 2 on EFB .......
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Running optimization stage 2 on VLO .......
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Running optimization stage 2 on VHI .......
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At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Fri Jun 7 20:50:05 2024
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###########################################################]
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Copyright (C) 1994-2018 Synopsys, Inc.
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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
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and may only be used pursuant to the terms and conditions of a written license agreement
|
|
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
|
Synopsys software or the associated documentation is strictly prohibited.
|
|
Tool: Synplify Pro (R)
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Build: N-2018.03L-SP1-1
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Install: C:\lscc\diamond\3.11_x64\synpbase
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OS: Windows 6.2
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Hostname: ZANEMACWIN11
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Implementation : impl1
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Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
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@N|Running in 64-bit mode
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At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Fri Jun 7 20:50:05 2024
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###########################################################]
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For a summary of runtime and memory usage for all design units, please see file:
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==========================================================
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@L: A:\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_comp.rt.csv
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@END
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At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Fri Jun 7 20:50:05 2024
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###########################################################]
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Copyright (C) 1994-2018 Synopsys, Inc.
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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
|
and may only be used pursuant to the terms and conditions of a written license agreement
|
|
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
|
Synopsys software or the associated documentation is strictly prohibited.
|
|
Tool: Synplify Pro (R)
|
|
Build: N-2018.03L-SP1-1
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Install: C:\lscc\diamond\3.11_x64\synpbase
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OS: Windows 6.2
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Hostname: ZANEMACWIN11
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Database state : \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\|impl1
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Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
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@N|Running in 64-bit mode
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At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 68MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Fri Jun 7 20:50:07 2024
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###########################################################]
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Premap Report
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# Fri Jun 7 20:50:07 2024
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Copyright (C) 1994-2018 Synopsys, Inc.
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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
|
and may only be used pursuant to the terms and conditions of a written license agreement
|
|
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
|
Synopsys software or the associated documentation is strictly prohibited.
|
|
Tool: Synplify Pro (R)
|
|
Build: N-2018.03L-SP1-1
|
|
Install: C:\lscc\diamond\3.11_x64\synpbase
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OS: Windows 6.2
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Hostname: ZANEMACWIN11
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Implementation : impl1
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Synopsys Lattice Technology Pre-mapping, Version maplat2018q2p1, Build 055R, Built Apr 3 2019 09:51:54
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Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
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Reading constraint file: \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
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@N: MF284 |Setting synthesis effort to medium for the design
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@L: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1_scck.rpt
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Printing clock summary report in "\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1_scck.rpt" file
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@N: MF916 |Option synthesis_strategy=base is enabled.
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@N: MF248 |Running in 64-bit mode.
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@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
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Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
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Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
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Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB)
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Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB)
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@N: MF284 |Setting synthesis effort to medium for the design
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@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
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@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":21:4:21:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
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@N: MH105 |UMR3 is only supported for HAPS-80.
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@N: MH105 |UMR3 is only supported for HAPS-80.
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@N: BN115 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":140:9:140:12|Removing instance dhgr (in view: work.RAM2E(verilog)) of type view:work.DHGR(verilog) because it does not drive other instances.
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syn_allowed_resources : blockrams=7 set on top level netlist RAM2E
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Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
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Clock Summary
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******************
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Start Requested Requested Clock Clock Clock
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Level Clock Frequency Period Type Group Load
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-----------------------------------------------------------------------------------------------
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0 - C14M 14.3 MHz 69.841 declared default_clkgroup 121
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0 - System 100.0 MHz 10.000 system system_clkgroup 0
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0 - RAM2E|PHI1 100.0 MHz 10.000 inferred Inferred_clkgroup_0 9
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===============================================================================================
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Clock Load Summary
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***********************
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Clock Source Clock Pin Non-clock Pin Non-clock Pin
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Clock Load Pin Seq Example Seq Example Comb Example
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--------------------------------------------------------------------------------------------
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C14M 121 C14M(port) RAT.C - un1_C14M.I[0](inv)
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System 0 - - - -
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RAM2E|PHI1 9 PHI1(port) RefReq.C S[0].D[0] un1_PHI1.I[0](inv)
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============================================================================================
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@W: MT529 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":20:19:20:24|Found inferred clock RAM2E|PHI1 which controls 9 sequential elements including PHI1r. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
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ICG Latch Removal Summary:
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Number of ICG latches removed: 0
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Number of ICG latches not removed: 0
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@S |Clock Optimization Summary
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#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
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2 non-gated/non-generated clock tree(s) driving 125 clock pin(s) of sequential element(s)
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0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
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0 instances converted, 0 sequential instances remain driven by gated/generated clocks
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=========================== Non-Gated/Non-Generated Clocks ============================
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Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
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---------------------------------------------------------------------------------------
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@KP:ckid0_0 C14M port 121 PHI1r
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@KP:ckid0_1 PHI1 Unconstrained_port 4 RC[2:0]
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=======================================================================================
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##### END OF CLOCK OPTIMIZATION REPORT ######
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@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
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Finished Pre Mapping Phase.
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Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
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Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
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None
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None
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Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
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Pre-mapping successful!
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At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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# Fri Jun 7 20:50:08 2024
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###########################################################]
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Map & Optimize Report
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# Fri Jun 7 20:50:08 2024
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Copyright (C) 1994-2018 Synopsys, Inc.
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|
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
|
and may only be used pursuant to the terms and conditions of a written license agreement
|
|
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
|
Synopsys software or the associated documentation is strictly prohibited.
|
|
Tool: Synplify Pro (R)
|
|
Build: N-2018.03L-SP1-1
|
|
Install: C:\lscc\diamond\3.11_x64\synpbase
|
|
OS: Windows 6.2
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Hostname: ZANEMACWIN11
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|
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Implementation : impl1
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Synopsys Lattice Technology Mapper, Version maplat2018q2p1, Build 055R, Built Apr 3 2019 09:51:54
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Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
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@N: MF284 |Setting synthesis effort to medium for the design
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@N: MF916 |Option synthesis_strategy=base is enabled.
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@N: MF248 |Running in 64-bit mode.
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@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
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Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
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Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
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Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
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Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
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@N: MF284 |Setting synthesis effort to medium for the design
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Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
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Available hyper_sources - for debug and ip models
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None Found
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@N: FX493 |Applying initial value "00000000" on instance RWBank[7:0].
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@N: FX493 |Applying initial value "0000" on instance S[3:0].
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Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)
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@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":14:23:14:28|Found counter in view:work.RAM2E(verilog) instance FS[15:0]
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Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 142MB)
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Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 145MB)
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Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
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Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
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Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
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Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 146MB)
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Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB)
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Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
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Pass CPU time Worst Slack Luts / Registers
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------------------------------------------------------------
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1 0h:00m:01s 6.90ns 281 / 125
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Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 157MB peak: 160MB)
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@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
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@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":171:4:171:9|Boundary register BA_1_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
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@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":171:4:171:9|Boundary register BA_0_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
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Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 158MB peak: 160MB)
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Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 122MB peak: 160MB)
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Writing Analyst data base \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_m.srm
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Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 158MB peak: 160MB)
|
|
|
|
Writing EDIF Netlist and constraint files
|
|
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1.edi
|
|
N-2018.03L-SP1-1
|
|
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
|
|
|
|
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 162MB peak: 164MB)
|
|
|
|
|
|
Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 161MB peak: 164MB)
|
|
|
|
@W: MT246 :"\\mac\icloud\repos\ram2e\cpld\lcmxo2-1200hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
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|
@N: MT615 |Found clock C14M with period 69.84ns
|
|
@W: MT420 |Found inferred clock RAM2E|PHI1 with period 10.00ns. Please declare a user-defined clock on port PHI1.
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|
|
##### START OF TIMING REPORT #####[
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# Timing Report written on Fri Jun 7 20:50:12 2024
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#
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Top view: RAM2E
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Requested Frequency: 14.3 MHz
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Wire load mode: top
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Paths requested: 5
|
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Constraint File(s): \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
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@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
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@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
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Performance Summary
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*******************
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Worst slack in design: 6.897
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Requested Estimated Requested Estimated Clock Clock
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Starting Clock Frequency Frequency Period Period Slack Type Group
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----------------------------------------------------------------------------------------------------------------------
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C14M 14.3 MHz 112.1 MHz 69.841 8.918 31.599 declared default_clkgroup
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RAM2E|PHI1 100.0 MHz 322.2 MHz 10.000 3.103 6.897 inferred Inferred_clkgroup_0
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System 100.0 MHz NA 10.000 NA 67.088 system system_clkgroup
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======================================================================================================================
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Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
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|
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Clock Relationships
|
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*******************
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Clocks | rise to rise | fall to fall | rise to fall | fall to rise
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----------------------------------------------------------------------------------------------------------------
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Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
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----------------------------------------------------------------------------------------------------------------
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System C14M | 69.841 67.088 | No paths - | No paths - | No paths -
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C14M System | 69.841 68.797 | No paths - | No paths - | No paths -
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C14M C14M | 69.841 60.923 | No paths - | 34.920 31.599 | No paths -
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RAM2E|PHI1 C14M | No paths - | No paths - | No paths - | Diff grp -
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RAM2E|PHI1 RAM2E|PHI1 | No paths - | 10.000 6.897 | No paths - | No paths -
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|
================================================================================================================
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Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
|
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'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
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Interface Information
|
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*********************
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No IO constraint found
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====================================
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Detailed Report for Clock: C14M
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====================================
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Starting Points with Worst Slack
|
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********************************
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Starting Arrival
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Instance Reference Type Pin Net Time Slack
|
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Clock
|
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---------------------------------------------------------------------------
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S[2] C14M FD1S3AX Q S[2] 1.366 31.599
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S[3] C14M FD1S3AX Q S[3] 1.345 31.619
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S[1] C14M FD1S3AX Q S[1] 1.344 31.800
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S[0] C14M FD1S3AX Q S[0] 1.305 31.838
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RA[0] C14M FD1P3AX Q RA[0] 1.108 33.707
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RA[3] C14M FD1P3AX Q RA[3] 1.108 33.707
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RA[1] C14M FD1P3AX Q RA[1] 1.044 33.771
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RA[2] C14M FD1P3AX Q RA[2] 1.044 33.771
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RA[4] C14M FD1P3AX Q RA[4] 1.044 33.771
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RA[5] C14M FD1P3AX Q RA[5] 1.044 33.771
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|
===========================================================================
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|
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Ending Points with Worst Slack
|
|
******************************
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Starting Required
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Instance Reference Type Pin Net Time Slack
|
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Clock
|
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-----------------------------------------------------------------------------------
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VOE_i_0io C14M OFS1P3IX CD N_530 34.118 31.599
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VOE_i_0io C14M OFS1P3IX D VOE_ic_i 35.009 31.800
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Vout_0io[0] C14M OFS1P3DX SP Vout3 34.449 32.634
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Vout_0io[1] C14M OFS1P3DX SP Vout3 34.449 32.634
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Vout_0io[2] C14M OFS1P3DX SP Vout3 34.449 32.634
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Vout_0io[3] C14M OFS1P3DX SP Vout3 34.449 32.634
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Vout_0io[4] C14M OFS1P3DX SP Vout3 34.449 32.634
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Vout_0io[5] C14M OFS1P3DX SP Vout3 34.449 32.634
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Vout_0io[6] C14M OFS1P3DX SP Vout3 34.449 32.634
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Vout_0io[7] C14M OFS1P3DX SP Vout3 34.449 32.634
|
|
===================================================================================
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|
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Worst Path Information
|
|
***********************
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|
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Path information for path number 1:
|
|
Requested Period: 34.920
|
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- Setup time: 0.803
|
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+ Clock delay at ending point: 0.000 (ideal)
|
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= Required time: 34.118
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|
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- Propagation time: 2.519
|
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- Clock delay at starting point: 0.000 (ideal)
|
|
= Slack (non-critical) : 31.599
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|
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Number of logic level(s): 1
|
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Starting point: S[2] / Q
|
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Ending point: VOE_i_0io / CD
|
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The start point is clocked by C14M [rising] on pin CK
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The end point is clocked by C14M [falling] on pin SCLK
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Instance / Net Pin Pin Arrival No. of
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Name Type Name Dir Delay Time Fan Out(s)
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------------------------------------------------------------------------------------------------------------
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S[2] FD1S3AX Q Out 1.366 1.366 -
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S[2] Net - - - - 58
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ram2e_ufm.un1_wb_adr_0_sqmuxa_2_0_a2_0[0] ORCALUT4 A In 0.000 1.366 -
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ram2e_ufm.un1_wb_adr_0_sqmuxa_2_0_a2_0[0] ORCALUT4 Z Out 1.153 2.519 -
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N_530 Net - - - - 3
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VOE_i_0io OFS1P3IX CD In 0.000 2.519 -
|
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============================================================================================================
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|
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====================================
|
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Detailed Report for Clock: RAM2E|PHI1
|
|
====================================
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|
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Starting Points with Worst Slack
|
|
********************************
|
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|
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Starting Arrival
|
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Instance Reference Type Pin Net Time Slack
|
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Clock
|
|
---------------------------------------------------------------------------
|
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RC[1] RAM2E|PHI1 FD1S3IX Q RC[1] 1.148 6.897
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RC[2] RAM2E|PHI1 FD1S3IX Q RC[2] 1.108 6.937
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RC[0] RAM2E|PHI1 FD1S3IX Q RC[0] 1.148 8.179
|
|
===========================================================================
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|
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Ending Points with Worst Slack
|
|
******************************
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|
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Starting Required
|
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Instance Reference Type Pin Net Time Slack
|
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Clock
|
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--------------------------------------------------------------------------------
|
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RC[0] RAM2E|PHI1 FD1S3IX CD RC7 9.197 6.897
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RC[1] RAM2E|PHI1 FD1S3IX CD RC7 9.197 6.897
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RC[2] RAM2E|PHI1 FD1S3IX CD RC7 9.197 6.897
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RC[0] RAM2E|PHI1 FD1S3IX D RC_i[0] 9.894 8.179
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RC[1] RAM2E|PHI1 FD1S3IX D RC_RNO[1] 10.089 8.324
|
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RC[2] RAM2E|PHI1 FD1S3IX D RC_RNO[2] 10.089 8.324
|
|
RefReq RAM2E|PHI1 FD1S3AX D RefReq_2 10.089 8.324
|
|
================================================================================
|
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|
|
|
|
Worst Path Information
|
|
***********************
|
|
|
|
|
|
Path information for path number 1:
|
|
Requested Period: 10.000
|
|
- Setup time: 0.803
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
= Required time: 9.197
|
|
|
|
- Propagation time: 2.301
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
= Slack (critical) : 6.897
|
|
|
|
Number of logic level(s): 1
|
|
Starting point: RC[1] / Q
|
|
Ending point: RC[0] / CD
|
|
The start point is clocked by RAM2E|PHI1 [falling] on pin CK
|
|
The end point is clocked by RAM2E|PHI1 [falling] on pin CK
|
|
|
|
Instance / Net Pin Pin Arrival No. of
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
|
---------------------------------------------------------------------------------
|
|
RC[1] FD1S3IX Q Out 1.148 1.148 -
|
|
RC[1] Net - - - - 4
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RC7 ORCALUT4 A In 0.000 1.148 -
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RC7 ORCALUT4 Z Out 1.153 2.301 -
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RC7 Net - - - - 3
|
|
RC[0] FD1S3IX CD In 0.000 2.301 -
|
|
=================================================================================
|
|
|
|
|
|
|
|
|
|
====================================
|
|
Detailed Report for Clock: System
|
|
====================================
|
|
|
|
|
|
|
|
Starting Points with Worst Slack
|
|
********************************
|
|
|
|
Starting Arrival
|
|
Instance Reference Type Pin Net Time Slack
|
|
Clock
|
|
---------------------------------------------------------------------------------------------------
|
|
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBACKO wb_ack 0.000 67.088
|
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ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO0 wb_dato[0] 0.000 69.313
|
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ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000 69.313
|
|
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO2 wb_dato[2] 0.000 69.313
|
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ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO3 wb_dato[3] 0.000 69.313
|
|
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO4 wb_dato[4] 0.000 69.313
|
|
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO5 wb_dato[5] 0.000 69.313
|
|
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO6 wb_dato[6] 0.000 69.313
|
|
ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO7 wb_dato[7] 0.000 69.313
|
|
===================================================================================================
|
|
|
|
|
|
Ending Points with Worst Slack
|
|
******************************
|
|
|
|
Starting Required
|
|
Instance Reference Type Pin Net Time Slack
|
|
Clock
|
|
----------------------------------------------------------------------------------------
|
|
ram2e_ufm.RWMask[0] System FD1P3AX SP N_104 69.369 67.088
|
|
ram2e_ufm.RWMask[1] System FD1P3AX SP N_104 69.369 67.088
|
|
ram2e_ufm.RWMask[2] System FD1P3AX SP N_104 69.369 67.088
|
|
ram2e_ufm.RWMask[3] System FD1P3AX SP N_104 69.369 67.088
|
|
ram2e_ufm.RWMask[4] System FD1P3AX SP N_104 69.369 67.088
|
|
ram2e_ufm.RWMask[5] System FD1P3AX SP N_104 69.369 67.088
|
|
ram2e_ufm.RWMask[6] System FD1P3AX SP N_104 69.369 67.088
|
|
ram2e_ufm.RWMask[7] System FD1P3AX SP N_104 69.369 67.088
|
|
ram2e_ufm.LEDEN System FD1P3AX SP N_98 69.369 67.736
|
|
ram2e_ufm.wb_cyc_stb System FD1P3AX SP N_111 69.369 67.736
|
|
========================================================================================
|
|
|
|
|
|
|
|
Worst Path Information
|
|
***********************
|
|
|
|
|
|
Path information for path number 1:
|
|
Requested Period: 69.841
|
|
- Setup time: 0.472
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
|
= Required time: 69.369
|
|
|
|
- Propagation time: 2.282
|
|
- Clock delay at starting point: 0.000 (ideal)
|
|
- Estimated clock delay at start point: -0.000
|
|
= Slack (non-critical) : 67.088
|
|
|
|
Number of logic level(s): 2
|
|
Starting point: ram2e_ufm.ufmefb.EFBInst_0 / WBACKO
|
|
Ending point: ram2e_ufm.RWMask[0] / SP
|
|
The start point is clocked by System [rising]
|
|
The end point is clocked by C14M [rising] on pin CK
|
|
|
|
Instance / Net Pin Pin Arrival No. of
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
|
----------------------------------------------------------------------------------------------------------------
|
|
ram2e_ufm.ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 -
|
|
wb_ack Net - - - - 5
|
|
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] ORCALUT4 B In 0.000 0.000 -
|
|
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] ORCALUT4 Z Out 1.017 1.017 -
|
|
un1_RWMask_0_sqmuxa_1_i_a2_0_0[0] Net - - - - 1
|
|
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 D In 0.000 1.017 -
|
|
ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 Z Out 1.265 2.282 -
|
|
N_104 Net - - - - 8
|
|
ram2e_ufm.RWMask[0] FD1P3AX SP In 0.000 2.282 -
|
|
================================================================================================================
|
|
|
|
|
|
|
|
##### END OF TIMING REPORT #####]
|
|
|
|
Timing exceptions that could not be applied
|
|
None
|
|
|
|
Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 161MB peak: 164MB)
|
|
|
|
|
|
Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 161MB peak: 164MB)
|
|
|
|
---------------------------------------
|
|
Resource Usage Report
|
|
Part: lcmxo2_1200hc-4
|
|
|
|
Register bits: 125 of 1280 (10%)
|
|
PIC Latch: 0
|
|
I/O cells: 70
|
|
|
|
|
|
Details:
|
|
BB: 8
|
|
CCU2D: 9
|
|
EFB: 1
|
|
FD1P3AX: 58
|
|
FD1P3IX: 1
|
|
FD1S3AX: 31
|
|
FD1S3AY: 4
|
|
FD1S3IX: 9
|
|
GSR: 1
|
|
IB: 21
|
|
IFS1P3DX: 1
|
|
INV: 4
|
|
OB: 41
|
|
OFS1P3BX: 6
|
|
OFS1P3DX: 12
|
|
OFS1P3IX: 3
|
|
ORCALUT4: 275
|
|
PUR: 1
|
|
VHI: 3
|
|
VLO: 3
|
|
Mapper successful!
|
|
|
|
At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 33MB peak: 164MB)
|
|
|
|
Process took 0h:00m:03s realtime, 0h:00m:02s cputime
|
|
# Fri Jun 7 20:50:12 2024
|
|
|
|
###########################################################]
|