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RAM2E/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.twr
Zane Kaminski dec33238f1 RC
2023-09-21 05:45:21 -04:00

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Loading design for application trce from file ram2e_lcmxo2_640hc_impl1.ncd.
Design name: RAM2E
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-640HC
Package: TQFP100
Performance: 4
Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.39.
Performance Hardware Data Status: Final Version 34.4.
Setup and Hold Report
--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
Thu Sep 21 05:35:07 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2E_LCMXO2_640HC_impl1.twr -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf
Design file: ram2e_lcmxo2_640hc_impl1.ncd
Preference file: ram2e_lcmxo2_640hc_impl1.prf
Device,speed: LCMXO2-640HC,4
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
1491 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 57.366ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[11] (from C14M_c +)
Destination: FF Data in nRWE_0io (to C14M_c +)
Delay: 12.584ns (27.2% logic, 72.8% route), 7 logic levels.
Constraint Details:
12.584ns physical path delay SLICE_3 to nRWE_MGIOL meets
69.930ns delay constraint less
-0.173ns skew and
0.153ns DO_SET requirement (totaling 69.950ns) by 57.366ns
Physical Path Details:
Data path SLICE_3 to nRWE_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R2C8C.CLK to R2C8C.Q0 SLICE_3 (from C14M_c)
ROUTE 19 2.765 R2C8C.Q0 to R2C6A.A1 FS[11]
CTOF_DEL --- 0.495 R2C6A.A1 to R2C6A.F1 SLICE_64
ROUTE 4 0.791 R2C6A.F1 to R3C6A.C0 N_577
CTOF_DEL --- 0.495 R3C6A.C0 to R3C6A.F0 SLICE_97
ROUTE 3 1.345 R3C6A.F0 to R3C9C.B1 N_489
CTOF_DEL --- 0.495 R3C9C.B1 to R3C9C.F1 SLICE_75
ROUTE 3 0.453 R3C9C.F1 to R3C9C.C0 N_628
CTOF_DEL --- 0.495 R3C9C.C0 to R3C9C.F0 SLICE_75
ROUTE 2 0.993 R3C9C.F0 to R5C9A.A1 N_640
CTOF_DEL --- 0.495 R5C9A.A1 to R5C9A.F1 SLICE_71
ROUTE 1 0.623 R5C9A.F1 to R5C10B.D0 un1_nCS61_1_i
CTOF_DEL --- 0.495 R5C10B.D0 to R5C10B.F0 SLICE_115
ROUTE 1 2.192 R5C10B.F0 to IOL_R7D.OPOS nRWE_r_0 (to C14M_c)
--------
12.584 (27.2% logic, 72.8% route), 7 logic levels.
Clock Skew Details:
Source Clock Path C14M to SLICE_3:
Name Fanout Delay (ns) Site Resource
ROUTE 84 3.070 62.PADDI to R2C8C.CLK C14M_c
--------
3.070 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path C14M to nRWE_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 84 3.243 62.PADDI to IOL_R7D.CLK C14M_c
--------
3.243 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 57.494ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[11] (from C14M_c +)
Destination: FF Data in nRAS_0io (to C14M_c +)
Delay: 12.456ns (23.5% logic, 76.5% route), 6 logic levels.
Constraint Details:
12.456ns physical path delay SLICE_3 to nRAS_MGIOL meets
69.930ns delay constraint less
-0.173ns skew and
0.153ns DO_SET requirement (totaling 69.950ns) by 57.494ns
Physical Path Details:
Data path SLICE_3 to nRAS_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R2C8C.CLK to R2C8C.Q0 SLICE_3 (from C14M_c)
ROUTE 19 2.765 R2C8C.Q0 to R2C6A.A1 FS[11]
CTOF_DEL --- 0.495 R2C6A.A1 to R2C6A.F1 SLICE_64
ROUTE 4 0.791 R2C6A.F1 to R3C6A.C0 N_577
CTOF_DEL --- 0.495 R3C6A.C0 to R3C6A.F0 SLICE_97
ROUTE 3 1.345 R3C6A.F0 to R3C9C.B1 N_489
CTOF_DEL --- 0.495 R3C9C.B1 to R3C9C.F1 SLICE_75
ROUTE 3 1.003 R3C9C.F1 to R3C10D.A0 N_628
CTOF_DEL --- 0.495 R3C10D.A0 to R3C10D.F0 SLICE_83
ROUTE 2 1.505 R3C10D.F0 to R5C10A.A0 N_559_1
CTOF_DEL --- 0.495 R5C10A.A0 to R5C10A.F0 SLICE_80
ROUTE 1 2.120 R5C10A.F0 to IOL_R7A.OPOS nRAS_2_iv_i (to C14M_c)
--------
12.456 (23.5% logic, 76.5% route), 6 logic levels.
Clock Skew Details:
Source Clock Path C14M to SLICE_3:
Name Fanout Delay (ns) Site Resource
ROUTE 84 3.070 62.PADDI to R2C8C.CLK C14M_c
--------
3.070 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path C14M to nRAS_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 84 3.243 62.PADDI to IOL_R7A.CLK C14M_c
--------
3.243 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 57.502ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[11] (from C14M_c +)
Destination: FF Data in nRWE_0io (to C14M_c +)
Delay: 12.448ns (23.5% logic, 76.5% route), 6 logic levels.
Constraint Details:
12.448ns physical path delay SLICE_3 to nRWE_MGIOL meets
69.930ns delay constraint less
-0.173ns skew and
0.153ns DO_SET requirement (totaling 69.950ns) by 57.502ns
Physical Path Details:
Data path SLICE_3 to nRWE_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R2C8C.CLK to R2C8C.Q0 SLICE_3 (from C14M_c)
ROUTE 19 2.765 R2C8C.Q0 to R2C6A.A1 FS[11]
CTOF_DEL --- 0.495 R2C6A.A1 to R2C6A.F1 SLICE_64
ROUTE 4 0.791 R2C6A.F1 to R3C6A.C0 N_577
CTOF_DEL --- 0.495 R3C6A.C0 to R3C6A.F0 SLICE_97
ROUTE 3 1.345 R3C6A.F0 to R3C9C.B1 N_489
CTOF_DEL --- 0.495 R3C9C.B1 to R3C9C.F1 SLICE_75
ROUTE 3 0.710 R3C9C.F1 to R3C9B.B0 N_628
CTOF_DEL --- 0.495 R3C9B.B0 to R3C9B.F0 SLICE_76
ROUTE 3 1.718 R3C9B.F0 to R5C10B.C0 nCAS_0_sqmuxa
CTOF_DEL --- 0.495 R5C10B.C0 to R5C10B.F0 SLICE_115
ROUTE 1 2.192 R5C10B.F0 to IOL_R7D.OPOS nRWE_r_0 (to C14M_c)
--------
12.448 (23.5% logic, 76.5% route), 6 logic levels.
Clock Skew Details:
Source Clock Path C14M to SLICE_3:
Name Fanout Delay (ns) Site Resource
ROUTE 84 3.070 62.PADDI to R2C8C.CLK C14M_c
--------
3.070 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path C14M to nRWE_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 84 3.243 62.PADDI to IOL_R7D.CLK C14M_c
--------
3.243 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 57.921ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[11] (from C14M_c +)
Destination: FF Data in nCS_0io (to C14M_c +)
Delay: 12.029ns (24.3% logic, 75.7% route), 6 logic levels.
Constraint Details:
12.029ns physical path delay SLICE_3 to nCS_MGIOL meets
69.930ns delay constraint less
-0.173ns skew and
0.153ns DO_SET requirement (totaling 69.950ns) by 57.921ns
Physical Path Details:
Data path SLICE_3 to nCS_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R2C8C.CLK to R2C8C.Q0 SLICE_3 (from C14M_c)
ROUTE 19 2.765 R2C8C.Q0 to R2C6A.A1 FS[11]
CTOF_DEL --- 0.495 R2C6A.A1 to R2C6A.F1 SLICE_64
ROUTE 4 0.791 R2C6A.F1 to R3C6A.C0 N_577
CTOF_DEL --- 0.495 R3C6A.C0 to R3C6A.F0 SLICE_97
ROUTE 3 1.345 R3C6A.F0 to R3C9C.B1 N_489
CTOF_DEL --- 0.495 R3C9C.B1 to R3C9C.F1 SLICE_75
ROUTE 3 1.003 R3C9C.F1 to R3C10D.A0 N_628
CTOF_DEL --- 0.495 R3C10D.A0 to R3C10D.F0 SLICE_83
ROUTE 2 1.505 R3C10D.F0 to R6C10A.A0 N_559_1
CTOF_DEL --- 0.495 R6C10A.A0 to R6C10A.F0 SLICE_79
ROUTE 1 1.693 R6C10A.F0 to IOL_R6D.OPOS N_559_i (to C14M_c)
--------
12.029 (24.3% logic, 75.7% route), 6 logic levels.
Clock Skew Details:
Source Clock Path C14M to SLICE_3:
Name Fanout Delay (ns) Site Resource
ROUTE 84 3.070 62.PADDI to R2C8C.CLK C14M_c
--------
3.070 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path C14M to nCS_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 84 3.243 62.PADDI to IOL_R6D.CLK C14M_c
--------
3.243 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 58.106ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[11] (from C14M_c +)
Destination: FF Data in nCAS_0io (to C14M_c +)
Delay: 11.844ns (24.7% logic, 75.3% route), 6 logic levels.
Constraint Details:
11.844ns physical path delay SLICE_3 to nCAS_MGIOL meets
69.930ns delay constraint less
-0.173ns skew and
0.153ns DO_SET requirement (totaling 69.950ns) by 58.106ns
Physical Path Details:
Data path SLICE_3 to nCAS_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R2C8C.CLK to R2C8C.Q0 SLICE_3 (from C14M_c)
ROUTE 19 2.765 R2C8C.Q0 to R2C6A.A1 FS[11]
CTOF_DEL --- 0.495 R2C6A.A1 to R2C6A.F1 SLICE_64
ROUTE 4 0.791 R2C6A.F1 to R3C6A.C0 N_577
CTOF_DEL --- 0.495 R3C6A.C0 to R3C6A.F0 SLICE_97
ROUTE 3 1.345 R3C6A.F0 to R3C9C.B1 N_489
CTOF_DEL --- 0.495 R3C9C.B1 to R3C9C.F1 SLICE_75
ROUTE 3 0.710 R3C9C.F1 to R3C9B.B0 N_628
CTOF_DEL --- 0.495 R3C9B.B0 to R3C9B.F0 SLICE_76
ROUTE 3 1.511 R3C9B.F0 to R5C9C.A0 nCAS_0_sqmuxa
CTOF_DEL --- 0.495 R5C9C.A0 to R5C9C.F0 SLICE_78
ROUTE 1 1.795 R5C9C.F0 to IOL_R7C.OPOS N_561_i (to C14M_c)
--------
11.844 (24.7% logic, 75.3% route), 6 logic levels.
Clock Skew Details:
Source Clock Path C14M to SLICE_3:
Name Fanout Delay (ns) Site Resource
ROUTE 84 3.070 62.PADDI to R2C8C.CLK C14M_c
--------
3.070 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path C14M to nCAS_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 84 3.243 62.PADDI to IOL_R7C.CLK C14M_c
--------
3.243 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 58.447ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[11] (from C14M_c +)
Destination: FF Data in RA_0io[10] (to C14M_c +)
Delay: 11.503ns (25.4% logic, 74.6% route), 6 logic levels.
Constraint Details:
11.503ns physical path delay SLICE_3 to RA[10]_MGIOL meets
69.930ns delay constraint less
-0.173ns skew and
0.153ns DO_SET requirement (totaling 69.950ns) by 58.447ns
Physical Path Details:
Data path SLICE_3 to RA[10]_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R2C8C.CLK to R2C8C.Q0 SLICE_3 (from C14M_c)
ROUTE 19 2.765 R2C8C.Q0 to R2C6A.A1 FS[11]
CTOF_DEL --- 0.495 R2C6A.A1 to R2C6A.F1 SLICE_64
ROUTE 4 0.791 R2C6A.F1 to R3C6A.C0 N_577
CTOF_DEL --- 0.495 R3C6A.C0 to R3C6A.F0 SLICE_97
ROUTE 3 1.345 R3C6A.F0 to R3C9C.B1 N_489
CTOF_DEL --- 0.495 R3C9C.B1 to R3C9C.F1 SLICE_75
ROUTE 3 0.710 R3C9C.F1 to R3C9B.B0 N_628
CTOF_DEL --- 0.495 R3C9B.B0 to R3C9B.F0 SLICE_76
ROUTE 3 1.170 R3C9B.F0 to R5C9D.D1 nCAS_0_sqmuxa
CTOF_DEL --- 0.495 R5C9D.D1 to R5C9D.F1 SLICE_69
ROUTE 1 1.795 R5C9D.F1 to IOL_R5B.OPOS RA_42[10] (to C14M_c)
--------
11.503 (25.4% logic, 74.6% route), 6 logic levels.
Clock Skew Details:
Source Clock Path C14M to SLICE_3:
Name Fanout Delay (ns) Site Resource
ROUTE 84 3.070 62.PADDI to R2C8C.CLK C14M_c
--------
3.070 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path C14M to RA[10]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 84 3.243 62.PADDI to IOL_R5B.CLK C14M_c
--------
3.243 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 58.587ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q S[2] (from C14M_c +)
Destination: FF Data in wb_adr[0] (to C14M_c +)
Delay: 11.177ns (26.2% logic, 73.8% route), 6 logic levels.
Constraint Details:
11.177ns physical path delay SLICE_34 to SLICE_35 meets
69.930ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 69.764ns) by 58.587ns
Physical Path Details:
Data path SLICE_34 to SLICE_35:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R4C9C.CLK to R4C9C.Q0 SLICE_34 (from C14M_c)
ROUTE 48 1.873 R4C9C.Q0 to R6C9B.B0 S[2]
CTOF_DEL --- 0.495 R6C9B.B0 to R6C9B.F0 SLICE_47
ROUTE 7 2.435 R6C9B.F0 to R4C5B.B0 S_RNII9DO1[1]
CTOF_DEL --- 0.495 R4C5B.B0 to R4C5B.F0 SLICE_73
ROUTE 8 1.931 R4C5B.F0 to R4C4C.D0 N_455
CTOF_DEL --- 0.495 R4C4C.D0 to R4C4C.F0 SLICE_89
ROUTE 1 0.626 R4C4C.F0 to R4C4A.D0 N_378
CTOF_DEL --- 0.495 R4C4A.D0 to R4C4A.F0 SLICE_85
ROUTE 1 1.385 R4C4A.F0 to R2C4B.D0 wb_adr_7_0_4[0]
CTOF_DEL --- 0.495 R2C4B.D0 to R2C4B.F0 SLICE_35
ROUTE 1 0.000 R2C4B.F0 to R2C4B.DI0 wb_adr_7[0] (to C14M_c)
--------
11.177 (26.2% logic, 73.8% route), 6 logic levels.
Clock Skew Details:
Source Clock Path C14M to SLICE_34:
Name Fanout Delay (ns) Site Resource
ROUTE 84 3.070 62.PADDI to R4C9C.CLK C14M_c
--------
3.070 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path C14M to SLICE_35:
Name Fanout Delay (ns) Site Resource
ROUTE 84 3.070 62.PADDI to R2C4B.CLK C14M_c
--------
3.070 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 58.757ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[12] (from C14M_c +)
Destination: FF Data in nRWE_0io (to C14M_c +)
Delay: 11.193ns (30.6% logic, 69.4% route), 7 logic levels.
Constraint Details:
11.193ns physical path delay SLICE_3 to nRWE_MGIOL meets
69.930ns delay constraint less
-0.173ns skew and
0.153ns DO_SET requirement (totaling 69.950ns) by 58.757ns
Physical Path Details:
Data path SLICE_3 to nRWE_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R2C8C.CLK to R2C8C.Q1 SLICE_3 (from C14M_c)
ROUTE 22 1.463 R2C8C.Q1 to R3C6A.A1 FS[12]
CTOF_DEL --- 0.495 R3C6A.A1 to R3C6A.F1 SLICE_97
ROUTE 2 0.702 R3C6A.F1 to R3C6A.B0 N_456
CTOF_DEL --- 0.495 R3C6A.B0 to R3C6A.F0 SLICE_97
ROUTE 3 1.345 R3C6A.F0 to R3C9C.B1 N_489
CTOF_DEL --- 0.495 R3C9C.B1 to R3C9C.F1 SLICE_75
ROUTE 3 0.453 R3C9C.F1 to R3C9C.C0 N_628
CTOF_DEL --- 0.495 R3C9C.C0 to R3C9C.F0 SLICE_75
ROUTE 2 0.993 R3C9C.F0 to R5C9A.A1 N_640
CTOF_DEL --- 0.495 R5C9A.A1 to R5C9A.F1 SLICE_71
ROUTE 1 0.623 R5C9A.F1 to R5C10B.D0 un1_nCS61_1_i
CTOF_DEL --- 0.495 R5C10B.D0 to R5C10B.F0 SLICE_115
ROUTE 1 2.192 R5C10B.F0 to IOL_R7D.OPOS nRWE_r_0 (to C14M_c)
--------
11.193 (30.6% logic, 69.4% route), 7 logic levels.
Clock Skew Details:
Source Clock Path C14M to SLICE_3:
Name Fanout Delay (ns) Site Resource
ROUTE 84 3.070 62.PADDI to R2C8C.CLK C14M_c
--------
3.070 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path C14M to nRWE_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 84 3.243 62.PADDI to IOL_R7D.CLK C14M_c
--------
3.243 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 58.784ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q S[0] (from C14M_c +)
Destination: FF Data in wb_adr[0] (to C14M_c +)
Delay: 10.980ns (26.7% logic, 73.3% route), 6 logic levels.
Constraint Details:
10.980ns physical path delay SLICE_33 to SLICE_35 meets
69.930ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 69.764ns) by 58.784ns
Physical Path Details:
Data path SLICE_33 to SLICE_35:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R4C9D.CLK to R4C9D.Q0 SLICE_33 (from C14M_c)
ROUTE 30 1.676 R4C9D.Q0 to R6C9B.C0 S[0]
CTOF_DEL --- 0.495 R6C9B.C0 to R6C9B.F0 SLICE_47
ROUTE 7 2.435 R6C9B.F0 to R4C5B.B0 S_RNII9DO1[1]
CTOF_DEL --- 0.495 R4C5B.B0 to R4C5B.F0 SLICE_73
ROUTE 8 1.931 R4C5B.F0 to R4C4C.D0 N_455
CTOF_DEL --- 0.495 R4C4C.D0 to R4C4C.F0 SLICE_89
ROUTE 1 0.626 R4C4C.F0 to R4C4A.D0 N_378
CTOF_DEL --- 0.495 R4C4A.D0 to R4C4A.F0 SLICE_85
ROUTE 1 1.385 R4C4A.F0 to R2C4B.D0 wb_adr_7_0_4[0]
CTOF_DEL --- 0.495 R2C4B.D0 to R2C4B.F0 SLICE_35
ROUTE 1 0.000 R2C4B.F0 to R2C4B.DI0 wb_adr_7[0] (to C14M_c)
--------
10.980 (26.7% logic, 73.3% route), 6 logic levels.
Clock Skew Details:
Source Clock Path C14M to SLICE_33:
Name Fanout Delay (ns) Site Resource
ROUTE 84 3.070 62.PADDI to R4C9D.CLK C14M_c
--------
3.070 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path C14M to SLICE_35:
Name Fanout Delay (ns) Site Resource
ROUTE 84 3.070 62.PADDI to R2C4B.CLK C14M_c
--------
3.070 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 29.415ns (weighted slack = 58.830ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q S[0] (from C14M_c +)
Destination: FF Data in Dout_0io[0] (to C14M_c -)
Delay: 5.676ns (16.7% logic, 83.3% route), 2 logic levels.
Constraint Details:
5.676ns physical path delay SLICE_33 to Dout[0]_MGIOL meets
34.965ns delay constraint less
-0.173ns skew and
0.047ns CE_SET requirement (totaling 35.091ns) by 29.415ns
Physical Path Details:
Data path SLICE_33 to Dout[0]_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R4C9D.CLK to R4C9D.Q0 SLICE_33 (from C14M_c)
ROUTE 30 1.881 R4C9D.Q0 to R6C8A.A1 S[0]
CTOF_DEL --- 0.495 R6C8A.A1 to R6C8A.F1 SLICE_20
ROUTE 17 2.848 R6C8A.F1 to IOL_B4D.CE N_576_i (to C14M_c)
--------
5.676 (16.7% logic, 83.3% route), 2 logic levels.
Clock Skew Details:
Source Clock Path C14M to SLICE_33:
Name Fanout Delay (ns) Site Resource
ROUTE 84 3.070 62.PADDI to R4C9D.CLK C14M_c
--------
3.070 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path C14M to Dout[0]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 84 3.243 62.PADDI to IOL_B4D.CLK C14M_c
--------
3.243 (0.0% logic, 100.0% route), 0 logic levels.
Report: 79.592MHz is the maximum frequency for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "C14M" 14.300000 MHz ; | 14.300 MHz| 79.592 MHz| 7
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 1 clocks:
Clock Domain: C14M_c Source: C14M.PAD Loads: 84
Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
Timing summary (Setup):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
Thu Sep 21 05:35:07 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2E_LCMXO2_640HC_impl1.twr -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf
Design file: ram2e_lcmxo2_640hc_impl1.ncd
Preference file: ram2e_lcmxo2_640hc_impl1.prf
Device,speed: LCMXO2-640HC,m
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
1491 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.346ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q wb_dati[3] (from C14M_c +)
Destination: EFB Port ufmefb/EFBInst_0(ASIC) (to C14M_c +)
Delay: 0.305ns (43.6% logic, 56.4% route), 1 logic levels.
Constraint Details:
0.305ns physical path delay SLICE_41 to ufmefb/EFBInst_0 meets
-0.095ns WBDATI_HLD and
0.000ns delay constraint less
-0.054ns skew requirement (totaling -0.041ns) by 0.346ns
Physical Path Details:
Data path SLICE_41 to ufmefb/EFBInst_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R2C3B.CLK to R2C3B.Q1 SLICE_41 (from C14M_c)
ROUTE 1 0.172 R2C3B.Q1 to EFB.WBDATI3 wb_dati[3] (to C14M_c)
--------
0.305 (43.6% logic, 56.4% route), 1 logic levels.
Clock Skew Details:
Source Clock Path C14M to SLICE_41:
Name Fanout Delay (ns) Site Resource
ROUTE 84 1.059 62.PADDI to R2C3B.CLK C14M_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path C14M to ufmefb/EFBInst_0:
Name Fanout Delay (ns) Site Resource
ROUTE 84 1.113 62.PADDI to EFB.WBCLKI C14M_c
--------
1.113 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.348ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q wb_dati[4] (from C14M_c +)
Destination: EFB Port ufmefb/EFBInst_0(ASIC) (to C14M_c +)
Delay: 0.305ns (43.6% logic, 56.4% route), 1 logic levels.
Constraint Details:
0.305ns physical path delay SLICE_42 to ufmefb/EFBInst_0 meets
-0.097ns WBDATI_HLD and
0.000ns delay constraint less
-0.054ns skew requirement (totaling -0.043ns) by 0.348ns
Physical Path Details:
Data path SLICE_42 to ufmefb/EFBInst_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R2C3D.CLK to R2C3D.Q0 SLICE_42 (from C14M_c)
ROUTE 1 0.172 R2C3D.Q0 to EFB.WBDATI4 wb_dati[4] (to C14M_c)
--------
0.305 (43.6% logic, 56.4% route), 1 logic levels.
Clock Skew Details:
Source Clock Path C14M to SLICE_42:
Name Fanout Delay (ns) Site Resource
ROUTE 84 1.059 62.PADDI to R2C3D.CLK C14M_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path C14M to ufmefb/EFBInst_0:
Name Fanout Delay (ns) Site Resource
ROUTE 84 1.113 62.PADDI to EFB.WBCLKI C14M_c
--------
1.113 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[0] (from C14M_c +)
Destination: FF Data in FS[0] (to C14M_c +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_0 to SLICE_0 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_0 to SLICE_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R2C7A.CLK to R2C7A.Q1 SLICE_0 (from C14M_c)
ROUTE 5 0.132 R2C7A.Q1 to R2C7A.A1 FS[0]
CTOF_DEL --- 0.101 R2C7A.A1 to R2C7A.F1 SLICE_0
ROUTE 1 0.000 R2C7A.F1 to R2C7A.DI1 FS_s[0] (to C14M_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path C14M to SLICE_0:
Name Fanout Delay (ns) Site Resource
ROUTE 84 1.059 62.PADDI to R2C7A.CLK C14M_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path C14M to SLICE_0:
Name Fanout Delay (ns) Site Resource
ROUTE 84 1.059 62.PADDI to R2C7A.CLK C14M_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdBitbangMXO2 (from C14M_c +)
Destination: FF Data in CmdBitbangMXO2 (to C14M_c +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_12 to SLICE_12 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_12 to SLICE_12:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R4C6C.CLK to R4C6C.Q0 SLICE_12 (from C14M_c)
ROUTE 2 0.132 R4C6C.Q0 to R4C6C.A0 CmdBitbangMXO2
CTOF_DEL --- 0.101 R4C6C.A0 to R4C6C.F0 SLICE_12
ROUTE 1 0.000 R4C6C.F0 to R4C6C.DI0 CmdBitbangMXO2_4 (to C14M_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path C14M to SLICE_12:
Name Fanout Delay (ns) Site Resource
ROUTE 84 1.059 62.PADDI to R4C6C.CLK C14M_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path C14M to SLICE_12:
Name Fanout Delay (ns) Site Resource
ROUTE 84 1.059 62.PADDI to R4C6C.CLK C14M_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdLEDSet (from C14M_c +)
Destination: FF Data in CmdLEDSet (to C14M_c +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_15 to SLICE_15 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_15 to SLICE_15:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C5B.CLK to R5C5B.Q0 SLICE_15 (from C14M_c)
ROUTE 2 0.132 R5C5B.Q0 to R5C5B.A0 CmdLEDSet
CTOF_DEL --- 0.101 R5C5B.A0 to R5C5B.F0 SLICE_15
ROUTE 1 0.000 R5C5B.F0 to R5C5B.DI0 CmdLEDSet_4 (to C14M_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path C14M to SLICE_15:
Name Fanout Delay (ns) Site Resource
ROUTE 84 1.059 62.PADDI to R5C5B.CLK C14M_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path C14M to SLICE_15:
Name Fanout Delay (ns) Site Resource
ROUTE 84 1.059 62.PADDI to R5C5B.CLK C14M_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdRWMaskSet (from C14M_c +)
Destination: FF Data in CmdRWMaskSet (to C14M_c +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_16 to SLICE_16 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_16 to SLICE_16:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C5C.CLK to R5C5C.Q0 SLICE_16 (from C14M_c)
ROUTE 2 0.132 R5C5C.Q0 to R5C5C.A0 CmdRWMaskSet
CTOF_DEL --- 0.101 R5C5C.A0 to R5C5C.F0 SLICE_16
ROUTE 1 0.000 R5C5C.F0 to R5C5C.DI0 CmdRWMaskSet_4 (to C14M_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path C14M to SLICE_16:
Name Fanout Delay (ns) Site Resource
ROUTE 84 1.059 62.PADDI to R5C5C.CLK C14M_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path C14M to SLICE_16:
Name Fanout Delay (ns) Site Resource
ROUTE 84 1.059 62.PADDI to R5C5C.CLK C14M_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdSetRWBankFFLED (from C14M_c +)
Destination: FF Data in CmdSetRWBankFFLED (to C14M_c +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_17 to SLICE_17 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_17 to SLICE_17:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R6C5C.CLK to R6C5C.Q0 SLICE_17 (from C14M_c)
ROUTE 2 0.132 R6C5C.Q0 to R6C5C.A0 CmdSetRWBankFFLED
CTOF_DEL --- 0.101 R6C5C.A0 to R6C5C.F0 SLICE_17
ROUTE 1 0.000 R6C5C.F0 to R6C5C.DI0 CmdSetRWBankFFLED_4 (to C14M_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path C14M to SLICE_17:
Name Fanout Delay (ns) Site Resource
ROUTE 84 1.059 62.PADDI to R6C5C.CLK C14M_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path C14M to SLICE_17:
Name Fanout Delay (ns) Site Resource
ROUTE 84 1.059 62.PADDI to R6C5C.CLK C14M_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdSetRWBankFFMXO2 (from C14M_c +)
Destination: FF Data in CmdSetRWBankFFMXO2 (to C14M_c +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_18 to SLICE_18 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_18 to SLICE_18:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R6C6D.CLK to R6C6D.Q0 SLICE_18 (from C14M_c)
ROUTE 2 0.132 R6C6D.Q0 to R6C6D.A0 CmdSetRWBankFFMXO2
CTOF_DEL --- 0.101 R6C6D.A0 to R6C6D.F0 SLICE_18
ROUTE 1 0.000 R6C6D.F0 to R6C6D.DI0 CmdSetRWBankFFMXO2_4 (to C14M_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path C14M to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 84 1.059 62.PADDI to R6C6D.CLK C14M_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path C14M to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 84 1.059 62.PADDI to R6C6D.CLK C14M_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[11] (from C14M_c +)
Destination: FF Data in FS[11] (to C14M_c +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_3 to SLICE_3 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_3 to SLICE_3:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R2C8C.CLK to R2C8C.Q0 SLICE_3 (from C14M_c)
ROUTE 19 0.132 R2C8C.Q0 to R2C8C.A0 FS[11]
CTOF_DEL --- 0.101 R2C8C.A0 to R2C8C.F0 SLICE_3
ROUTE 1 0.000 R2C8C.F0 to R2C8C.DI0 FS_s[11] (to C14M_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path C14M to SLICE_3:
Name Fanout Delay (ns) Site Resource
ROUTE 84 1.059 62.PADDI to R2C8C.CLK C14M_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path C14M to SLICE_3:
Name Fanout Delay (ns) Site Resource
ROUTE 84 1.059 62.PADDI to R2C8C.CLK C14M_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Ready (from C14M_c +)
Destination: FF Data in Ready (to C14M_c +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_32 to SLICE_32 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_32 to SLICE_32:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R2C9C.CLK to R2C9C.Q0 SLICE_32 (from C14M_c)
ROUTE 2 0.132 R2C9C.Q0 to R2C9C.A0 Ready
CTOF_DEL --- 0.101 R2C9C.A0 to R2C9C.F0 SLICE_32
ROUTE 1 0.000 R2C9C.F0 to R2C9C.DI0 N_876_0 (to C14M_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path C14M to SLICE_32:
Name Fanout Delay (ns) Site Resource
ROUTE 84 1.059 62.PADDI to R2C9C.CLK C14M_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path C14M to SLICE_32:
Name Fanout Delay (ns) Site Resource
ROUTE 84 1.059 62.PADDI to R2C9C.CLK C14M_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "C14M" 14.300000 MHz ; | -| -| 1
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 1 clocks:
Clock Domain: C14M_c Source: C14M.PAD Loads: 84
Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
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