This commit is contained in:
Zane Kaminski
parent
7a4150866d
commit
dec33238f1
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@ -14,18 +14,41 @@ _autosave-*
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*-save.pro
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*-save.kicad_pcb
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fp-info-cache
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Hardware/*/*-backups
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# Netlist files (exported from Eeschema)
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*.net
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# Autorouter files (exported from Pcbnew)
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*.dsn
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*.ses
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# Exported BOM files
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*.xml
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# Mac
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*.DS_Store
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Documentation/~$4203BManual.docx
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*.cdf
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Documentation/~$4203BDevNote.docx
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# Altera MAX II/V
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CPLD/MAX*/db
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CPLD/MAX*/incremental_db
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CPLD/MAX*/greybox_tmp
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# Lattice Diamond
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CPLD/LCMXO*/*.dir
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CPLD/LCMXO*/.build_status
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CPLD/LCMXO*/.run_manager.ini
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CPLD/LCMXO*/.recovery
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CPLD/LCMXO*/.spread_sheet.ini
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CPLD/LCMXO*/.spreadsheet_view.ini
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CPLD/LCMXO*/impl1/*
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!CPLD/LCMXO*/impl1/*.jed
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!CPLD/LCMXO*/impl1/*.bit
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!CPLD/LCMXO*/impl1/*.html
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!CPLD/LCMXO*/impl1/*.rpt
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!CPLD/LCMXO*/impl1/*.sdf
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!CPLD/LCMXO*/impl1/*.vo
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!CPLD/LCMXO*/impl1/*.alt
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!CPLD/LCMXO*/impl1/*.areasrr
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!CPLD/LCMXO*/impl1/*.bgn
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!CPLD/LCMXO*/impl1/*.edi
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!CPLD/LCMXO*/impl1/*.ior
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!CPLD/LCMXO*/impl1/*.mrp
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!CPLD/LCMXO*/impl1/*.pad
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!CPLD/LCMXO*/impl1/*.prf
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!CPLD/LCMXO*/impl1/*.srr
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!CPLD/LCMXO*/impl1/*.twr
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!CPLD/LCMXO*/impl1/*.tw1
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@ -0,0 +1,4 @@
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[General]
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Map.auto_tasks=MapTrace, MapVerilogSimFile
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PAR.auto_tasks=PARTrace, IOTiming
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Export.auto_tasks=IBIS, TimingSimFileVlg, Bitgen, Jedecgen
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@ -0,0 +1,20 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<BaliProject version="3.2" title="RAM2E_LCMXO2_1200HC" device="LCMXO2-1200HC-4TG100C" default_implementation="impl1">
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<Options/>
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<Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
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<Options def_top="RAM2E" top="RAM2E"/>
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<Source name="../RAM2E-LCMXO2.v" type="Verilog" type_short="Verilog">
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<Options top_module="RAM2E"/>
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</Source>
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<Source name="REFB.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../RAM2E-LCMXO2.lpf" type="Logic Preference" type_short="LPF">
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<Options/>
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</Source>
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<Source name="../RAM2E.sdc" type="Synplify Design Constraints File" type_short="SDC">
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<Options/>
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</Source>
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</Implementation>
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<Strategy name="Strategy1" file="RAM2E_LCMXO2_1200HC1.sty"/>
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</BaliProject>
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@ -0,0 +1,205 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<!DOCTYPE strategy>
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<Strategy version="1.0" predefined="0" description="" label="Strategy1">
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<Property name="PROP_BD_CmdLineArgs" value="" time="0"/>
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<Property name="PROP_BD_EdfHardtimer" value="Enable" time="0"/>
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<Property name="PROP_BD_EdfInBusNameConv" value="None" time="0"/>
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<Property name="PROP_BD_EdfInLibPath" value="" time="0"/>
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<Property name="PROP_BD_EdfInRemLoc" value="Off" time="0"/>
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<Property name="PROP_BD_EdfMemPath" value="" time="0"/>
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<Property name="PROP_BD_ParSearchPath" value="" time="0"/>
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<Property name="PROP_BIT_AddressBitGen" value="Increment" time="0"/>
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<Property name="PROP_BIT_AllowReadBitGen" value="Disable" time="0"/>
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<Property name="PROP_BIT_ByteWideBitMirror" value="Disable" time="0"/>
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<Property name="PROP_BIT_CapReadBitGen" value="Disable" time="0"/>
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<Property name="PROP_BIT_ConModBitGen" value="Disable" time="0"/>
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<Property name="PROP_BIT_CreateBitFile" value="True" time="0"/>
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<Property name="PROP_BIT_DisRAMResBitGen" value="True" time="0"/>
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<Property name="PROP_BIT_DisableUESBitgen" value="False" time="0"/>
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<Property name="PROP_BIT_DonePinBitGen" value="Pullup" time="0"/>
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<Property name="PROP_BIT_DoneSigBitGen" value="4" time="0"/>
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<Property name="PROP_BIT_EnIOBitGen" value="TriStateDuringReConfig" time="0"/>
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<Property name="PROP_BIT_EnIntOscBitGen" value="Disable" time="0"/>
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<Property name="PROP_BIT_ExtClockBitGen" value="False" time="0"/>
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<Property name="PROP_BIT_GSREnableBitGen" value="True" time="0"/>
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<Property name="PROP_BIT_GSRRelOnBitGen" value="DoneIn" time="0"/>
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<Property name="PROP_BIT_GranTimBitGen" value="0" time="0"/>
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<Property name="PROP_BIT_IOTriRelBitGen" value="Cycle 2" time="0"/>
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<Property name="PROP_BIT_JTAGEnableBitGen" value="False" time="0"/>
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<Property name="PROP_BIT_LenBitsBitGen" value="24" time="0"/>
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<Property name="PROP_BIT_MIFFileBitGen" value="" time="0"/>
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<Property name="PROP_BIT_NoHeader" value="False" time="0"/>
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<Property name="PROP_BIT_OutFormatBitGen" value="Bit File (Binary)" time="0"/>
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<Property name="PROP_BIT_OutFormatBitGen_REF" value="" time="0"/>
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<Property name="PROP_BIT_OutFormatPromGen" value="Intel Hex 32-bit" time="0"/>
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<Property name="PROP_BIT_ParityCheckBitGen" value="True" time="0"/>
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<Property name="PROP_BIT_ReadBackBitGen" value="Flash" time="0"/>
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<Property name="PROP_BIT_ReadCaptureBitGen" value="Disable" time="0"/>
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<Property name="PROP_BIT_RemZeroFramesBitGen" value="False" time="0"/>
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<Property name="PROP_BIT_RunDRCBitGen" value="True" time="0"/>
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<Property name="PROP_BIT_SearchPthBitGen" value="" time="0"/>
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<Property name="PROP_BIT_StartUpClkBitGen" value="Cclk" time="0"/>
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<Property name="PROP_BIT_SynchIOBitGen" value="True" time="0"/>
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<Property name="PROP_BIT_SysClockConBitGen" value="Reset" time="0"/>
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<Property name="PROP_BIT_SysConBitGen" value="Reset" time="0"/>
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<Property name="PROP_BIT_WaitStTimBitGen" value="5" time="0"/>
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<Property name="PROP_IOTIMING_AllSpeed" value="False" time="0"/>
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<Property name="PROP_LST_AllowDUPMod" value="False" time="0"/>
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<Property name="PROP_LST_CarryChain" value="True" time="0"/>
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<Property name="PROP_LST_CarryChainLength" value="0" time="0"/>
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<Property name="PROP_LST_CmdLineArgs" value="" time="0"/>
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<Property name="PROP_LST_DSPStyle" value="DSP" time="0"/>
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<Property name="PROP_LST_DSPUtil" value="100" time="0"/>
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<Property name="PROP_LST_DecodeUnreachableStates" value="False" time="0"/>
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<Property name="PROP_LST_DisableDistRam" value="False" time="0"/>
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<Property name="PROP_LST_EBRUtil" value="100" time="0"/>
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<Property name="PROP_LST_EdfFrequency" value="200" time="0"/>
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<Property name="PROP_LST_EdfHardtimer" value="Enable" time="0"/>
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<Property name="PROP_LST_EdfInLibPath" value="" time="0"/>
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<Property name="PROP_LST_EdfInRemLoc" value="Off" time="0"/>
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<Property name="PROP_LST_EdfMemPath" value="" time="0"/>
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<Property name="PROP_LST_FIXGATEDCLKS" value="True" time="0"/>
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<Property name="PROP_LST_FSMEncodeStyle" value="Auto" time="0"/>
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<Property name="PROP_LST_ForceGSRInfer" value="Auto" time="0"/>
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<Property name="PROP_LST_IOInsertion" value="True" time="0"/>
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<Property name="PROP_LST_InterFileDump" value="False" time="0"/>
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<Property name="PROP_LST_LoopLimit" value="1950" time="0"/>
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<Property name="PROP_LST_MaxFanout" value="1000" time="0"/>
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<Property name="PROP_LST_MuxStyle" value="Auto" time="0"/>
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<Property name="PROP_LST_NumCriticalPaths" value="3" time="0"/>
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<Property name="PROP_LST_OptimizeGoal" value="Balanced" time="0"/>
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<Property name="PROP_LST_PropagatConst" value="True" time="0"/>
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<Property name="PROP_LST_RAMStyle" value="Auto" time="0"/>
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<Property name="PROP_LST_ROMStyle" value="Auto" time="0"/>
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<Property name="PROP_LST_RemoveDupRegs" value="True" time="0"/>
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<Property name="PROP_LST_ResolvedMixedDrivers" value="False" time="0"/>
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<Property name="PROP_LST_ResourceShare" value="True" time="0"/>
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<Property name="PROP_LST_UseIOReg" value="Auto" time="0"/>
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<Property name="PROP_LST_UseLPF" value="True" time="0"/>
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<Property name="PROP_LST_VHDL2008" value="False" time="0"/>
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<Property name="PROP_MAPSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
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<Property name="PROP_MAPSTA_AutoTiming" value="True" time="0"/>
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<Property name="PROP_MAPSTA_CheckUnconstrainedConns" value="False" time="0"/>
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<Property name="PROP_MAPSTA_CheckUnconstrainedPaths" value="False" time="0"/>
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<Property name="PROP_MAPSTA_FullName" value="False" time="0"/>
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<Property name="PROP_MAPSTA_NumUnconstrainedPaths" value="0" time="0"/>
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<Property name="PROP_MAPSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
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<Property name="PROP_MAPSTA_RouteEstAlogtithm" value="0" time="0"/>
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<Property name="PROP_MAPSTA_RptAsynTimLoop" value="False" time="0"/>
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<Property name="PROP_MAPSTA_WordCasePaths" value="1" time="0"/>
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<Property name="PROP_MAP_IgnorePreErr" value="True" time="0"/>
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<Property name="PROP_MAP_MAPIORegister" value="Auto" time="0"/>
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<Property name="PROP_MAP_MAPInferGSR" value="True" time="0"/>
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<Property name="PROP_MAP_MapModArgs" value="" time="0"/>
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<Property name="PROP_MAP_OvermapDevice" value="False" time="0"/>
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<Property name="PROP_MAP_PackLogMapDes" value="0" time="0"/>
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<Property name="PROP_MAP_RegRetiming" value="False" time="0"/>
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<Property name="PROP_MAP_SigCrossRef" value="False" time="0"/>
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<Property name="PROP_MAP_SymCrossRef" value="False" time="0"/>
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<Property name="PROP_MAP_TimingDriven" value="False" time="0"/>
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<Property name="PROP_MAP_TimingDrivenNodeRep" value="False" time="0"/>
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<Property name="PROP_MAP_TimingDrivenPack" value="False" time="0"/>
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<Property name="PROP_PARSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
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<Property name="PROP_PARSTA_AutoTiming" value="True" time="0"/>
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<Property name="PROP_PARSTA_CheckUnconstrainedConns" value="False" time="0"/>
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<Property name="PROP_PARSTA_CheckUnconstrainedPaths" value="False" time="0"/>
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<Property name="PROP_PARSTA_FullName" value="False" time="0"/>
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<Property name="PROP_PARSTA_NumUnconstrainedPaths" value="0" time="0"/>
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<Property name="PROP_PARSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
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<Property name="PROP_PARSTA_RptAsynTimLoop" value="False" time="0"/>
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<Property name="PROP_PARSTA_SpeedForHoldAnalysis" value="m" time="0"/>
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<Property name="PROP_PARSTA_SpeedForSetupAnalysis" value="default" time="0"/>
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<Property name="PROP_PARSTA_WordCasePaths" value="10" time="0"/>
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<Property name="PROP_PAR_CrDlyStFileParDes" value="False" time="0"/>
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<Property name="PROP_PAR_DisableTDParDes" value="False" time="0"/>
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<Property name="PROP_PAR_EffortParDes" value="5" time="0"/>
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<Property name="PROP_PAR_MultiSeedSortMode" value="Worst Slack" time="0"/>
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<Property name="PROP_PAR_NewRouteParDes" value="NBR" time="0"/>
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<Property name="PROP_PAR_PARClockSkew" value="Off" time="0"/>
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<Property name="PROP_PAR_PARModArgs" value="" time="0"/>
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<Property name="PROP_PAR_ParMultiNodeList" value="" time="0"/>
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<Property name="PROP_PAR_ParRunPlaceOnly" value="False" time="0"/>
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||||
<Property name="PROP_PAR_PlcIterParDes" value="1" time="0"/>
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<Property name="PROP_PAR_PlcStCostTblParDes" value="1" time="0"/>
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<Property name="PROP_PAR_PrefErrorOut" value="True" time="0"/>
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||||
<Property name="PROP_PAR_RemoveDir" value="True" time="0"/>
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||||
<Property name="PROP_PAR_RouteDlyRedParDes" value="0" time="0"/>
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||||
<Property name="PROP_PAR_RoutePassParDes" value="6" time="0"/>
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||||
<Property name="PROP_PAR_RouteResOptParDes" value="0" time="0"/>
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||||
<Property name="PROP_PAR_RoutingCDP" value="0" time="0"/>
|
||||
<Property name="PROP_PAR_RoutingCDR" value="0" time="0"/>
|
||||
<Property name="PROP_PAR_RunParWithTrce" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_RunTimeReduction" value="True" time="0"/>
|
||||
<Property name="PROP_PAR_SaveBestRsltParDes" value="1" time="0"/>
|
||||
<Property name="PROP_PAR_StopZero" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_parHold" value="On" time="0"/>
|
||||
<Property name="PROP_PAR_parPathBased" value="Off" time="0"/>
|
||||
<Property name="PROP_PRE_CmdLineArgs" value="" time="0"/>
|
||||
<Property name="PROP_PRE_EdfArrayBoundsCase" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfAutoResOfRam" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfClockDomainCross" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfDSPAcrossHie" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfFullCase" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfIgnoreRamRWCol" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfMissConstraint" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfNetFanout" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfParaCase" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfReencodeFSM" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfResSharing" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfTimingViolation" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfUseSafeFSM" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfVlog2001" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynComArea" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynCritcal" value="3" time="0"/>
|
||||
<Property name="PROP_PRE_VSynFSM" value="Auto" time="0"/>
|
||||
<Property name="PROP_PRE_VSynFreq" value="200" time="0"/>
|
||||
<Property name="PROP_PRE_VSynGSR" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_VSynGatedClk" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_VSynIOPad" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_VSynOutNetForm" value="None" time="0"/>
|
||||
<Property name="PROP_PRE_VSynOutPref" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynRepClkFreq" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynRetime" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynTimSum" value="10" time="0"/>
|
||||
<Property name="PROP_PRE_VSynTransform" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSyninpd" value="0" time="0"/>
|
||||
<Property name="PROP_PRE_VSynoutd" value="0" time="0"/>
|
||||
<Property name="PROP_SYN_ClockConversion" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_CmdLineArgs" value="" time="0"/>
|
||||
<Property name="PROP_SYN_DisableRegisterRep" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfAllowDUPMod" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfArea" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfArrangeVHDLFiles" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfDefEnumEncode" value="Default" time="0"/>
|
||||
<Property name="PROP_SYN_EdfFanout" value="1000" time="0"/>
|
||||
<Property name="PROP_SYN_EdfFrequency" value="100" time="0"/>
|
||||
<Property name="PROP_SYN_EdfGSR" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfInsertIO" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfNumCritPath" value="" time="0"/>
|
||||
<Property name="PROP_SYN_EdfNumStartEnd" value="" time="0"/>
|
||||
<Property name="PROP_SYN_EdfOutNetForm" value="None" time="0"/>
|
||||
<Property name="PROP_SYN_EdfPushTirstates" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfResSharing" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfRunRetiming" value="Pipelining Only" time="0"/>
|
||||
<Property name="PROP_SYN_EdfSymFSM" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfUnconsClk" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfVerilogInput" value="Verilog 2001" time="0"/>
|
||||
<Property name="PROP_SYN_ExportSetting" value="No" time="0"/>
|
||||
<Property name="PROP_SYN_LibPath" value="" time="0"/>
|
||||
<Property name="PROP_SYN_ResolvedMixedDrivers" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_UpdateCompilePtTimData" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_UseLPF" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_VHDL2008" value="False" time="0"/>
|
||||
<Property name="PROP_THERMAL_DefaultFreq" value="0" time="0"/>
|
||||
<Property name="PROP_TIM_MaxDelSimDes" value="" time="0"/>
|
||||
<Property name="PROP_TIM_MinSpeedGrade" value="False" time="0"/>
|
||||
<Property name="PROP_TIM_ModPreSimDes" value="" time="0"/>
|
||||
<Property name="PROP_TIM_NegStupHldTim" value="True" time="0"/>
|
||||
<Property name="PROP_TIM_TimSimGenPUR" value="True" time="0"/>
|
||||
<Property name="PROP_TIM_TimSimGenX" value="False" time="0"/>
|
||||
<Property name="PROP_TIM_TimSimHierSep" value="" time="0"/>
|
||||
<Property name="PROP_TIM_TransportModeOfPathDelay" value="False" time="0"/>
|
||||
<Property name="PROP_TIM_TrgtSpeedGrade" value="" time="0"/>
|
||||
<Property name="PROP_TIM_WriteVerboseNetlist" value="False" time="0"/>
|
||||
<Property name="PROP_TMCHK_EnableCheck" value="True" time="0"/>
|
||||
</Strategy>
|
||||
|
|
@ -0,0 +1,71 @@
|
|||
<HTML>
|
||||
<HEAD><TITLE>Lattice TCL Log</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="pn230921045934"></A><B><U><big>pn230921045934</big></U></B>
|
||||
#Start recording tcl command: 9/21/2023 04:58:28
|
||||
#Project Location: //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC; Project name: RAM2E_LCMXO2_1200HC
|
||||
prj_project open "//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC.ldf"
|
||||
prj_run PAR -impl impl1 -task IOTiming
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
#Stop recording: 9/21/2023 04:59:34
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
|
|
@ -0,0 +1,550 @@
|
|||
(edif REFB
|
||||
(edifVersion 2 0 0)
|
||||
(edifLevel 0)
|
||||
(keywordMap (keywordLevel 0))
|
||||
(status
|
||||
(written
|
||||
(timestamp 2023 9 20 4 45 58)
|
||||
(program "SCUBA" (version "Diamond (64-bit) 3.12.1.454"))))
|
||||
(comment "C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 14.4 -ufm -ufm_ebr 190 -mem_size 321 -memfile ../RAM2E-LCMXO2.mem -memformat hex -wb -dev 1200 ")
|
||||
(library ORCLIB
|
||||
(edifLevel 0)
|
||||
(technology
|
||||
(numberDefinition))
|
||||
(cell VHI
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port Z
|
||||
(direction OUTPUT)))))
|
||||
(cell VLO
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port Z
|
||||
(direction OUTPUT)))))
|
||||
(cell EFB
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port WBCLKI
|
||||
(direction INPUT))
|
||||
(port WBRSTI
|
||||
(direction INPUT))
|
||||
(port WBCYCI
|
||||
(direction INPUT))
|
||||
(port WBSTBI
|
||||
(direction INPUT))
|
||||
(port WBWEI
|
||||
(direction INPUT))
|
||||
(port WBADRI7
|
||||
(direction INPUT))
|
||||
(port WBADRI6
|
||||
(direction INPUT))
|
||||
(port WBADRI5
|
||||
(direction INPUT))
|
||||
(port WBADRI4
|
||||
(direction INPUT))
|
||||
(port WBADRI3
|
||||
(direction INPUT))
|
||||
(port WBADRI2
|
||||
(direction INPUT))
|
||||
(port WBADRI1
|
||||
(direction INPUT))
|
||||
(port WBADRI0
|
||||
(direction INPUT))
|
||||
(port WBDATI7
|
||||
(direction INPUT))
|
||||
(port WBDATI6
|
||||
(direction INPUT))
|
||||
(port WBDATI5
|
||||
(direction INPUT))
|
||||
(port WBDATI4
|
||||
(direction INPUT))
|
||||
(port WBDATI3
|
||||
(direction INPUT))
|
||||
(port WBDATI2
|
||||
(direction INPUT))
|
||||
(port WBDATI1
|
||||
(direction INPUT))
|
||||
(port WBDATI0
|
||||
(direction INPUT))
|
||||
(port PLL0DATI7
|
||||
(direction INPUT))
|
||||
(port PLL0DATI6
|
||||
(direction INPUT))
|
||||
(port PLL0DATI5
|
||||
(direction INPUT))
|
||||
(port PLL0DATI4
|
||||
(direction INPUT))
|
||||
(port PLL0DATI3
|
||||
(direction INPUT))
|
||||
(port PLL0DATI2
|
||||
(direction INPUT))
|
||||
(port PLL0DATI1
|
||||
(direction INPUT))
|
||||
(port PLL0DATI0
|
||||
(direction INPUT))
|
||||
(port PLL0ACKI
|
||||
(direction INPUT))
|
||||
(port PLL1DATI7
|
||||
(direction INPUT))
|
||||
(port PLL1DATI6
|
||||
(direction INPUT))
|
||||
(port PLL1DATI5
|
||||
(direction INPUT))
|
||||
(port PLL1DATI4
|
||||
(direction INPUT))
|
||||
(port PLL1DATI3
|
||||
(direction INPUT))
|
||||
(port PLL1DATI2
|
||||
(direction INPUT))
|
||||
(port PLL1DATI1
|
||||
(direction INPUT))
|
||||
(port PLL1DATI0
|
||||
(direction INPUT))
|
||||
(port PLL1ACKI
|
||||
(direction INPUT))
|
||||
(port I2C1SCLI
|
||||
(direction INPUT))
|
||||
(port I2C1SDAI
|
||||
(direction INPUT))
|
||||
(port I2C2SCLI
|
||||
(direction INPUT))
|
||||
(port I2C2SDAI
|
||||
(direction INPUT))
|
||||
(port SPISCKI
|
||||
(direction INPUT))
|
||||
(port SPIMISOI
|
||||
(direction INPUT))
|
||||
(port SPIMOSII
|
||||
(direction INPUT))
|
||||
(port SPISCSN
|
||||
(direction INPUT))
|
||||
(port TCCLKI
|
||||
(direction INPUT))
|
||||
(port TCRSTN
|
||||
(direction INPUT))
|
||||
(port TCIC
|
||||
(direction INPUT))
|
||||
(port UFMSN
|
||||
(direction INPUT))
|
||||
(port WBDATO7
|
||||
(direction OUTPUT))
|
||||
(port WBDATO6
|
||||
(direction OUTPUT))
|
||||
(port WBDATO5
|
||||
(direction OUTPUT))
|
||||
(port WBDATO4
|
||||
(direction OUTPUT))
|
||||
(port WBDATO3
|
||||
(direction OUTPUT))
|
||||
(port WBDATO2
|
||||
(direction OUTPUT))
|
||||
(port WBDATO1
|
||||
(direction OUTPUT))
|
||||
(port WBDATO0
|
||||
(direction OUTPUT))
|
||||
(port WBACKO
|
||||
(direction OUTPUT))
|
||||
(port PLLCLKO
|
||||
(direction OUTPUT))
|
||||
(port PLLRSTO
|
||||
(direction OUTPUT))
|
||||
(port PLL0STBO
|
||||
(direction OUTPUT))
|
||||
(port PLL1STBO
|
||||
(direction OUTPUT))
|
||||
(port PLLWEO
|
||||
(direction OUTPUT))
|
||||
(port PLLADRO4
|
||||
(direction OUTPUT))
|
||||
(port PLLADRO3
|
||||
(direction OUTPUT))
|
||||
(port PLLADRO2
|
||||
(direction OUTPUT))
|
||||
(port PLLADRO1
|
||||
(direction OUTPUT))
|
||||
(port PLLADRO0
|
||||
(direction OUTPUT))
|
||||
(port PLLDATO7
|
||||
(direction OUTPUT))
|
||||
(port PLLDATO6
|
||||
(direction OUTPUT))
|
||||
(port PLLDATO5
|
||||
(direction OUTPUT))
|
||||
(port PLLDATO4
|
||||
(direction OUTPUT))
|
||||
(port PLLDATO3
|
||||
(direction OUTPUT))
|
||||
(port PLLDATO2
|
||||
(direction OUTPUT))
|
||||
(port PLLDATO1
|
||||
(direction OUTPUT))
|
||||
(port PLLDATO0
|
||||
(direction OUTPUT))
|
||||
(port I2C1SCLO
|
||||
(direction OUTPUT))
|
||||
(port I2C1SCLOEN
|
||||
(direction OUTPUT))
|
||||
(port I2C1SDAO
|
||||
(direction OUTPUT))
|
||||
(port I2C1SDAOEN
|
||||
(direction OUTPUT))
|
||||
(port I2C2SCLO
|
||||
(direction OUTPUT))
|
||||
(port I2C2SCLOEN
|
||||
(direction OUTPUT))
|
||||
(port I2C2SDAO
|
||||
(direction OUTPUT))
|
||||
(port I2C2SDAOEN
|
||||
(direction OUTPUT))
|
||||
(port I2C1IRQO
|
||||
(direction OUTPUT))
|
||||
(port I2C2IRQO
|
||||
(direction OUTPUT))
|
||||
(port SPISCKO
|
||||
(direction OUTPUT))
|
||||
(port SPISCKEN
|
||||
(direction OUTPUT))
|
||||
(port SPIMISOO
|
||||
(direction OUTPUT))
|
||||
(port SPIMISOEN
|
||||
(direction OUTPUT))
|
||||
(port SPIMOSIO
|
||||
(direction OUTPUT))
|
||||
(port SPIMOSIEN
|
||||
(direction OUTPUT))
|
||||
(port SPIMCSN7
|
||||
(direction OUTPUT))
|
||||
(port SPIMCSN6
|
||||
(direction OUTPUT))
|
||||
(port SPIMCSN5
|
||||
(direction OUTPUT))
|
||||
(port SPIMCSN4
|
||||
(direction OUTPUT))
|
||||
(port SPIMCSN3
|
||||
(direction OUTPUT))
|
||||
(port SPIMCSN2
|
||||
(direction OUTPUT))
|
||||
(port SPIMCSN1
|
||||
(direction OUTPUT))
|
||||
(port SPIMCSN0
|
||||
(direction OUTPUT))
|
||||
(port SPICSNEN
|
||||
(direction OUTPUT))
|
||||
(port SPIIRQO
|
||||
(direction OUTPUT))
|
||||
(port TCINT
|
||||
(direction OUTPUT))
|
||||
(port TCOC
|
||||
(direction OUTPUT))
|
||||
(port WBCUFMIRQ
|
||||
(direction OUTPUT))
|
||||
(port CFGWAKE
|
||||
(direction OUTPUT))
|
||||
(port CFGSTDBY
|
||||
(direction OUTPUT)))))
|
||||
(cell REFB
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port wb_clk_i
|
||||
(direction INPUT))
|
||||
(port wb_rst_i
|
||||
(direction INPUT))
|
||||
(port wb_cyc_i
|
||||
(direction INPUT))
|
||||
(port wb_stb_i
|
||||
(direction INPUT))
|
||||
(port wb_we_i
|
||||
(direction INPUT))
|
||||
(port (array (rename wb_adr_i "wb_adr_i(7:0)") 8)
|
||||
(direction INPUT))
|
||||
(port (array (rename wb_dat_i "wb_dat_i(7:0)") 8)
|
||||
(direction INPUT))
|
||||
(port (array (rename wb_dat_o "wb_dat_o(7:0)") 8)
|
||||
(direction OUTPUT))
|
||||
(port wb_ack_o
|
||||
(direction OUTPUT))
|
||||
(port wbc_ufm_irq
|
||||
(direction OUTPUT)))
|
||||
(property NGD_DRC_MASK (integer 1))
|
||||
(contents
|
||||
(instance scuba_vhi_inst
|
||||
(viewRef view1
|
||||
(cellRef VHI)))
|
||||
(instance scuba_vlo_inst
|
||||
(viewRef view1
|
||||
(cellRef VLO)))
|
||||
(instance EFBInst_0
|
||||
(viewRef view1
|
||||
(cellRef EFB))
|
||||
(property UFM_INIT_FILE_FORMAT
|
||||
(string "HEX"))
|
||||
(property UFM_INIT_FILE_NAME
|
||||
(string "../RAM2E-LCMXO2.mem"))
|
||||
(property UFM_INIT_ALL_ZEROS
|
||||
(string "DISABLED"))
|
||||
(property UFM_INIT_START_PAGE
|
||||
(string "190"))
|
||||
(property UFM_INIT_PAGES
|
||||
(string "321"))
|
||||
(property DEV_DENSITY
|
||||
(string "1200L"))
|
||||
(property EFB_UFM
|
||||
(string "ENABLED"))
|
||||
(property TC_ICAPTURE
|
||||
(string "DISABLED"))
|
||||
(property TC_OVERFLOW
|
||||
(string "DISABLED"))
|
||||
(property TC_ICR_INT
|
||||
(string "OFF"))
|
||||
(property TC_OCR_INT
|
||||
(string "OFF"))
|
||||
(property TC_OV_INT
|
||||
(string "OFF"))
|
||||
(property TC_TOP_SEL
|
||||
(string "OFF"))
|
||||
(property TC_RESETN
|
||||
(string "ENABLED"))
|
||||
(property TC_OC_MODE
|
||||
(string "TOGGLE"))
|
||||
(property TC_OCR_SET
|
||||
(string "32767"))
|
||||
(property TC_TOP_SET
|
||||
(string "65535"))
|
||||
(property GSR
|
||||
(string "ENABLED"))
|
||||
(property TC_CCLK_SEL
|
||||
(string "1"))
|
||||
(property TC_MODE
|
||||
(string "CTCM"))
|
||||
(property TC_SCLK_SEL
|
||||
(string "PCLOCK"))
|
||||
(property EFB_TC_PORTMODE
|
||||
(string "WB"))
|
||||
(property EFB_TC
|
||||
(string "DISABLED"))
|
||||
(property SPI_WAKEUP
|
||||
(string "DISABLED"))
|
||||
(property SPI_INTR_RXOVR
|
||||
(string "DISABLED"))
|
||||
(property SPI_INTR_TXOVR
|
||||
(string "DISABLED"))
|
||||
(property SPI_INTR_RXRDY
|
||||
(string "DISABLED"))
|
||||
(property SPI_INTR_TXRDY
|
||||
(string "DISABLED"))
|
||||
(property SPI_SLAVE_HANDSHAKE
|
||||
(string "DISABLED"))
|
||||
(property SPI_PHASE_ADJ
|
||||
(string "DISABLED"))
|
||||
(property SPI_CLK_INV
|
||||
(string "DISABLED"))
|
||||
(property SPI_LSB_FIRST
|
||||
(string "DISABLED"))
|
||||
(property SPI_CLK_DIVIDER
|
||||
(string "1"))
|
||||
(property SPI_MODE
|
||||
(string "MASTER"))
|
||||
(property EFB_SPI
|
||||
(string "DISABLED"))
|
||||
(property I2C2_WAKEUP
|
||||
(string "DISABLED"))
|
||||
(property I2C2_GEN_CALL
|
||||
(string "DISABLED"))
|
||||
(property I2C2_CLK_DIVIDER
|
||||
(string "1"))
|
||||
(property I2C2_BUS_PERF
|
||||
(string "100kHz"))
|
||||
(property I2C2_SLAVE_ADDR
|
||||
(string "0b1000010"))
|
||||
(property I2C2_ADDRESSING
|
||||
(string "7BIT"))
|
||||
(property EFB_I2C2
|
||||
(string "DISABLED"))
|
||||
(property I2C1_WAKEUP
|
||||
(string "DISABLED"))
|
||||
(property I2C1_GEN_CALL
|
||||
(string "DISABLED"))
|
||||
(property I2C1_CLK_DIVIDER
|
||||
(string "1"))
|
||||
(property I2C1_BUS_PERF
|
||||
(string "100kHz"))
|
||||
(property I2C1_SLAVE_ADDR
|
||||
(string "0b1000001"))
|
||||
(property I2C1_ADDRESSING
|
||||
(string "7BIT"))
|
||||
(property EFB_I2C1
|
||||
(string "DISABLED"))
|
||||
(property EFB_WB_CLK_FREQ
|
||||
(string "14.4")))
|
||||
(net scuba_vhi
|
||||
(joined
|
||||
(portRef Z (instanceRef scuba_vhi_inst))
|
||||
(portRef UFMSN (instanceRef EFBInst_0))))
|
||||
(net scuba_vlo
|
||||
(joined
|
||||
(portRef Z (instanceRef scuba_vlo_inst))
|
||||
(portRef PLL1DATI7 (instanceRef EFBInst_0))
|
||||
(portRef PLL1DATI6 (instanceRef EFBInst_0))
|
||||
(portRef PLL1DATI5 (instanceRef EFBInst_0))
|
||||
(portRef PLL1DATI4 (instanceRef EFBInst_0))
|
||||
(portRef PLL1DATI3 (instanceRef EFBInst_0))
|
||||
(portRef PLL1DATI2 (instanceRef EFBInst_0))
|
||||
(portRef PLL1DATI1 (instanceRef EFBInst_0))
|
||||
(portRef PLL1DATI0 (instanceRef EFBInst_0))
|
||||
(portRef PLL1ACKI (instanceRef EFBInst_0))
|
||||
(portRef PLL0DATI7 (instanceRef EFBInst_0))
|
||||
(portRef PLL0DATI6 (instanceRef EFBInst_0))
|
||||
(portRef PLL0DATI5 (instanceRef EFBInst_0))
|
||||
(portRef PLL0DATI4 (instanceRef EFBInst_0))
|
||||
(portRef PLL0DATI3 (instanceRef EFBInst_0))
|
||||
(portRef PLL0DATI2 (instanceRef EFBInst_0))
|
||||
(portRef PLL0DATI1 (instanceRef EFBInst_0))
|
||||
(portRef PLL0DATI0 (instanceRef EFBInst_0))
|
||||
(portRef PLL0ACKI (instanceRef EFBInst_0))
|
||||
(portRef TCIC (instanceRef EFBInst_0))
|
||||
(portRef TCRSTN (instanceRef EFBInst_0))
|
||||
(portRef TCCLKI (instanceRef EFBInst_0))
|
||||
(portRef SPISCSN (instanceRef EFBInst_0))
|
||||
(portRef SPIMOSII (instanceRef EFBInst_0))
|
||||
(portRef SPIMISOI (instanceRef EFBInst_0))
|
||||
(portRef SPISCKI (instanceRef EFBInst_0))
|
||||
(portRef I2C2SDAI (instanceRef EFBInst_0))
|
||||
(portRef I2C2SCLI (instanceRef EFBInst_0))
|
||||
(portRef I2C1SDAI (instanceRef EFBInst_0))
|
||||
(portRef I2C1SCLI (instanceRef EFBInst_0))))
|
||||
(net wbc_ufm_irq
|
||||
(joined
|
||||
(portRef wbc_ufm_irq)
|
||||
(portRef WBCUFMIRQ (instanceRef EFBInst_0))))
|
||||
(net wb_ack_o
|
||||
(joined
|
||||
(portRef wb_ack_o)
|
||||
(portRef WBACKO (instanceRef EFBInst_0))))
|
||||
(net wb_dat_o7
|
||||
(joined
|
||||
(portRef (member wb_dat_o 0))
|
||||
(portRef WBDATO7 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_o6
|
||||
(joined
|
||||
(portRef (member wb_dat_o 1))
|
||||
(portRef WBDATO6 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_o5
|
||||
(joined
|
||||
(portRef (member wb_dat_o 2))
|
||||
(portRef WBDATO5 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_o4
|
||||
(joined
|
||||
(portRef (member wb_dat_o 3))
|
||||
(portRef WBDATO4 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_o3
|
||||
(joined
|
||||
(portRef (member wb_dat_o 4))
|
||||
(portRef WBDATO3 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_o2
|
||||
(joined
|
||||
(portRef (member wb_dat_o 5))
|
||||
(portRef WBDATO2 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_o1
|
||||
(joined
|
||||
(portRef (member wb_dat_o 6))
|
||||
(portRef WBDATO1 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_o0
|
||||
(joined
|
||||
(portRef (member wb_dat_o 7))
|
||||
(portRef WBDATO0 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_i7
|
||||
(joined
|
||||
(portRef (member wb_dat_i 0))
|
||||
(portRef WBDATI7 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_i6
|
||||
(joined
|
||||
(portRef (member wb_dat_i 1))
|
||||
(portRef WBDATI6 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_i5
|
||||
(joined
|
||||
(portRef (member wb_dat_i 2))
|
||||
(portRef WBDATI5 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_i4
|
||||
(joined
|
||||
(portRef (member wb_dat_i 3))
|
||||
(portRef WBDATI4 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_i3
|
||||
(joined
|
||||
(portRef (member wb_dat_i 4))
|
||||
(portRef WBDATI3 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_i2
|
||||
(joined
|
||||
(portRef (member wb_dat_i 5))
|
||||
(portRef WBDATI2 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_i1
|
||||
(joined
|
||||
(portRef (member wb_dat_i 6))
|
||||
(portRef WBDATI1 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_i0
|
||||
(joined
|
||||
(portRef (member wb_dat_i 7))
|
||||
(portRef WBDATI0 (instanceRef EFBInst_0))))
|
||||
(net wb_adr_i7
|
||||
(joined
|
||||
(portRef (member wb_adr_i 0))
|
||||
(portRef WBADRI7 (instanceRef EFBInst_0))))
|
||||
(net wb_adr_i6
|
||||
(joined
|
||||
(portRef (member wb_adr_i 1))
|
||||
(portRef WBADRI6 (instanceRef EFBInst_0))))
|
||||
(net wb_adr_i5
|
||||
(joined
|
||||
(portRef (member wb_adr_i 2))
|
||||
(portRef WBADRI5 (instanceRef EFBInst_0))))
|
||||
(net wb_adr_i4
|
||||
(joined
|
||||
(portRef (member wb_adr_i 3))
|
||||
(portRef WBADRI4 (instanceRef EFBInst_0))))
|
||||
(net wb_adr_i3
|
||||
(joined
|
||||
(portRef (member wb_adr_i 4))
|
||||
(portRef WBADRI3 (instanceRef EFBInst_0))))
|
||||
(net wb_adr_i2
|
||||
(joined
|
||||
(portRef (member wb_adr_i 5))
|
||||
(portRef WBADRI2 (instanceRef EFBInst_0))))
|
||||
(net wb_adr_i1
|
||||
(joined
|
||||
(portRef (member wb_adr_i 6))
|
||||
(portRef WBADRI1 (instanceRef EFBInst_0))))
|
||||
(net wb_adr_i0
|
||||
(joined
|
||||
(portRef (member wb_adr_i 7))
|
||||
(portRef WBADRI0 (instanceRef EFBInst_0))))
|
||||
(net wb_we_i
|
||||
(joined
|
||||
(portRef wb_we_i)
|
||||
(portRef WBWEI (instanceRef EFBInst_0))))
|
||||
(net wb_stb_i
|
||||
(joined
|
||||
(portRef wb_stb_i)
|
||||
(portRef WBSTBI (instanceRef EFBInst_0))))
|
||||
(net wb_cyc_i
|
||||
(joined
|
||||
(portRef wb_cyc_i)
|
||||
(portRef WBCYCI (instanceRef EFBInst_0))))
|
||||
(net wb_rst_i
|
||||
(joined
|
||||
(portRef wb_rst_i)
|
||||
(portRef WBRSTI (instanceRef EFBInst_0))))
|
||||
(net wb_clk_i
|
||||
(joined
|
||||
(portRef wb_clk_i)
|
||||
(portRef WBCLKI (instanceRef EFBInst_0))))))))
|
||||
(design REFB
|
||||
(cellRef REFB
|
||||
(libraryRef ORCLIB)))
|
||||
)
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<DiamondModule name="REFB" module="EFB" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2023 09 20 04:46:00.352" version="1.2" type="Module" synthesis="synplify" source_format="Verilog">
|
||||
<Package>
|
||||
<File name="REFB.lpc" type="lpc" modified="2023 09 20 04:45:58.427"/>
|
||||
<File name="REFB.v" type="top_level_verilog" modified="2023 09 20 04:45:58.515"/>
|
||||
<File name="REFB_tmpl.v" type="template_verilog" modified="2023 09 20 04:45:58.515"/>
|
||||
</Package>
|
||||
</DiamondModule>
|
||||
|
|
@ -0,0 +1,141 @@
|
|||
[Device]
|
||||
Family=machxo2
|
||||
PartType=LCMXO2-1200HC
|
||||
PartName=LCMXO2-1200HC-4TG100C
|
||||
SpeedGrade=4
|
||||
Package=TQFP100
|
||||
OperatingCondition=COM
|
||||
Status=S
|
||||
|
||||
[IP]
|
||||
VendorName=Lattice Semiconductor Corporation
|
||||
CoreType=LPM
|
||||
CoreStatus=Demo
|
||||
CoreName=EFB
|
||||
CoreRevision=1.2
|
||||
ModuleName=REFB
|
||||
SourceFormat=Verilog HDL
|
||||
ParameterFileVersion=1.0
|
||||
Date=09/20/2023
|
||||
Time=04:45:58
|
||||
|
||||
[Parameters]
|
||||
Verilog=1
|
||||
VHDL=0
|
||||
EDIF=1
|
||||
Destination=Synplicity
|
||||
Expression=BusA(0 to 7)
|
||||
Order=Big Endian [MSB:LSB]
|
||||
IO=0
|
||||
freq=
|
||||
i2c1=0
|
||||
i2c1config=0
|
||||
i2c1_addr=7-Bit Addressing
|
||||
i2c1_ce=0
|
||||
i2c1_freq=100
|
||||
i2c1_sa=10000
|
||||
i2c1_we=0
|
||||
i2c2=0
|
||||
i2c2_addr=7-Bit Addressing
|
||||
i2c2_ce=0
|
||||
i2c2_freq=100
|
||||
i2c2_sa=10000
|
||||
i2c2_we=0
|
||||
ufm_addr=7-Bit Addressing
|
||||
ufm_sa=10000
|
||||
pll=0
|
||||
pll_cnt=1
|
||||
spi=0
|
||||
spi_clkinv=0
|
||||
spi_cs=1
|
||||
spi_en=0
|
||||
spi_freq=1
|
||||
spi_lsb=0
|
||||
spi_mode=Slave
|
||||
spi_ib=0
|
||||
spi_ph=0
|
||||
spi_hs=0
|
||||
spi_rxo=0
|
||||
spi_rxr=0
|
||||
spi_txo=0
|
||||
spi_txr=0
|
||||
spi_we=0
|
||||
static_tc=Static
|
||||
tc=0
|
||||
tc_clkinv=Positive
|
||||
tc_ctr=1
|
||||
tc_div=1
|
||||
tc_ipcap=0
|
||||
tc_mode=CTCM
|
||||
tc_ocr=32767
|
||||
tc_oflow=1
|
||||
tc_o=TOGGLE
|
||||
tc_opcomp=0
|
||||
tc_osc=0
|
||||
tc_sa_oflow=0
|
||||
tc_top=65535
|
||||
ufm=1
|
||||
ufm0=0
|
||||
ufm1=0
|
||||
ufm2=0
|
||||
ufm3=0
|
||||
ufm_cfg0=0
|
||||
ufm_cfg1=0
|
||||
wb_clk_freq=14.4
|
||||
ufm_usage=SHARED_EBR_TAG
|
||||
ufm_ebr=190
|
||||
ufm_remain=
|
||||
mem_size=321
|
||||
ufm_start=
|
||||
ufm_init=mem
|
||||
memfile=../RAM2E-LCMXO2.mem
|
||||
ufm_dt=hex
|
||||
ufm0_ebr=
|
||||
mem_size0=1
|
||||
ufm0_init=0
|
||||
memfile0=
|
||||
ufm0_dt=hex
|
||||
ufm1_ebr=
|
||||
mem_size1=1
|
||||
ufm1_init=0
|
||||
memfile1=
|
||||
ufm1_dt=hex
|
||||
ufm2_ebr=
|
||||
mem_size2=1
|
||||
ufm2_init=0
|
||||
memfile2=
|
||||
ufm2_dt=hex
|
||||
ufm3_ebr=
|
||||
mem_size3=1
|
||||
ufm3_init=0
|
||||
memfile3=
|
||||
ufm3_dt=hex
|
||||
ufm_cfg0_ebr=
|
||||
mem_size_cfg0=1
|
||||
ufm_cfg0_init=0
|
||||
memfile_cfg0=
|
||||
ufm_cfg0_dt=hex
|
||||
ufm_cfg1_ebr=
|
||||
mem_size_cfg1=1
|
||||
ufm_cfg1_init=0
|
||||
memfile_cfg1=
|
||||
ufm_cfg1_dt=hex
|
||||
wb=1
|
||||
boot_option=Internal
|
||||
efb_ufm=0
|
||||
boot_option_internal=Single Boot
|
||||
internal_ufm0=0
|
||||
internal_ufm1=0
|
||||
efb_ufm_boot=
|
||||
tamperdr=0
|
||||
t_pwd=0
|
||||
t_lockflash=0
|
||||
t_manmode=0
|
||||
t_jtagport=0
|
||||
t_sspiport=0
|
||||
t_sic2port=0
|
||||
t_wbport=0
|
||||
t_portlock=0
|
||||
|
||||
[Command]
|
||||
cmd_line= -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 14.4 -ufm -ufm_ebr 190 -mem_size 321 -memfile ../RAM2E-LCMXO2.mem -memformat hex -wb -dev 1200
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
wb_clk_i i
|
||||
wb_rst_i i
|
||||
wb_cyc_i i
|
||||
wb_stb_i i
|
||||
wb_we_i i
|
||||
wb_adr_i[7] i
|
||||
wb_adr_i[6] i
|
||||
wb_adr_i[5] i
|
||||
wb_adr_i[4] i
|
||||
wb_adr_i[3] i
|
||||
wb_adr_i[2] i
|
||||
wb_adr_i[1] i
|
||||
wb_adr_i[0] i
|
||||
wb_dat_i[7] i
|
||||
wb_dat_i[6] i
|
||||
wb_dat_i[5] i
|
||||
wb_dat_i[4] i
|
||||
wb_dat_i[3] i
|
||||
wb_dat_i[2] i
|
||||
wb_dat_i[1] i
|
||||
wb_dat_i[0] i
|
||||
wb_dat_o[7] o
|
||||
wb_dat_o[6] o
|
||||
wb_dat_o[5] o
|
||||
wb_dat_o[4] o
|
||||
wb_dat_o[3] o
|
||||
wb_dat_o[2] o
|
||||
wb_dat_o[1] o
|
||||
wb_dat_o[0] o
|
||||
wb_ack_o o
|
||||
wbc_ufm_irq o
|
||||
|
|
@ -0,0 +1 @@
|
|||
REFB.v
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
SCUBA, Version Diamond (64-bit) 3.12.1.454
|
||||
Wed Sep 20 04:45:58 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 14.4 -ufm -ufm_ebr 190 -mem_size 321 -memfile ../RAM2E-LCMXO2.mem -memformat hex -wb -dev 1200
|
||||
Circuit name : REFB
|
||||
Module type : efb
|
||||
Module Version : 1.2
|
||||
Ports :
|
||||
Inputs : wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i[7:0], wb_dat_i[7:0]
|
||||
Outputs : wb_dat_o[7:0], wb_ack_o, wbc_ufm_irq
|
||||
I/O buffer : not inserted
|
||||
EDIF output : REFB.edn
|
||||
Verilog output : REFB.v
|
||||
Verilog template : REFB_tmpl.v
|
||||
Verilog purpose : for synthesis and simulation
|
||||
Bus notation : big endian
|
||||
Report output : REFB.srp
|
||||
Element Usage :
|
||||
EFB : 1
|
||||
Estimated Resource Usage:
|
||||
Binary file not shown.
|
|
@ -0,0 +1,113 @@
|
|||
/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 */
|
||||
/* Module Version: 1.2 */
|
||||
/* C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 14.4 -ufm -ufm_ebr 190 -mem_size 321 -memfile ../RAM2E-LCMXO2.mem -memformat hex -wb -dev 1200 */
|
||||
/* Wed Sep 20 04:45:58 2023 */
|
||||
|
||||
|
||||
`timescale 1 ns / 1 ps
|
||||
module REFB (wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i,
|
||||
wb_dat_i, wb_dat_o, wb_ack_o, wbc_ufm_irq)/* synthesis NGD_DRC_MASK=1 */;
|
||||
input wire wb_clk_i;
|
||||
input wire wb_rst_i;
|
||||
input wire wb_cyc_i;
|
||||
input wire wb_stb_i;
|
||||
input wire wb_we_i;
|
||||
input wire [7:0] wb_adr_i;
|
||||
input wire [7:0] wb_dat_i;
|
||||
output wire [7:0] wb_dat_o;
|
||||
output wire wb_ack_o;
|
||||
output wire wbc_ufm_irq;
|
||||
|
||||
wire scuba_vhi;
|
||||
wire scuba_vlo;
|
||||
|
||||
VHI scuba_vhi_inst (.Z(scuba_vhi));
|
||||
|
||||
VLO scuba_vlo_inst (.Z(scuba_vlo));
|
||||
|
||||
defparam EFBInst_0.UFM_INIT_FILE_FORMAT = "HEX" ;
|
||||
defparam EFBInst_0.UFM_INIT_FILE_NAME = "../RAM2E-LCMXO2.mem" ;
|
||||
defparam EFBInst_0.UFM_INIT_ALL_ZEROS = "DISABLED" ;
|
||||
defparam EFBInst_0.UFM_INIT_START_PAGE = 190 ;
|
||||
defparam EFBInst_0.UFM_INIT_PAGES = 321 ;
|
||||
defparam EFBInst_0.DEV_DENSITY = "1200L" ;
|
||||
defparam EFBInst_0.EFB_UFM = "ENABLED" ;
|
||||
defparam EFBInst_0.TC_ICAPTURE = "DISABLED" ;
|
||||
defparam EFBInst_0.TC_OVERFLOW = "DISABLED" ;
|
||||
defparam EFBInst_0.TC_ICR_INT = "OFF" ;
|
||||
defparam EFBInst_0.TC_OCR_INT = "OFF" ;
|
||||
defparam EFBInst_0.TC_OV_INT = "OFF" ;
|
||||
defparam EFBInst_0.TC_TOP_SEL = "OFF" ;
|
||||
defparam EFBInst_0.TC_RESETN = "ENABLED" ;
|
||||
defparam EFBInst_0.TC_OC_MODE = "TOGGLE" ;
|
||||
defparam EFBInst_0.TC_OCR_SET = 32767 ;
|
||||
defparam EFBInst_0.TC_TOP_SET = 65535 ;
|
||||
defparam EFBInst_0.GSR = "ENABLED" ;
|
||||
defparam EFBInst_0.TC_CCLK_SEL = 1 ;
|
||||
defparam EFBInst_0.TC_MODE = "CTCM" ;
|
||||
defparam EFBInst_0.TC_SCLK_SEL = "PCLOCK" ;
|
||||
defparam EFBInst_0.EFB_TC_PORTMODE = "WB" ;
|
||||
defparam EFBInst_0.EFB_TC = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_WAKEUP = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_INTR_RXOVR = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_INTR_TXOVR = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_INTR_RXRDY = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_INTR_TXRDY = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_SLAVE_HANDSHAKE = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_PHASE_ADJ = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_CLK_INV = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_LSB_FIRST = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_CLK_DIVIDER = 1 ;
|
||||
defparam EFBInst_0.SPI_MODE = "MASTER" ;
|
||||
defparam EFBInst_0.EFB_SPI = "DISABLED" ;
|
||||
defparam EFBInst_0.I2C2_WAKEUP = "DISABLED" ;
|
||||
defparam EFBInst_0.I2C2_GEN_CALL = "DISABLED" ;
|
||||
defparam EFBInst_0.I2C2_CLK_DIVIDER = 1 ;
|
||||
defparam EFBInst_0.I2C2_BUS_PERF = "100kHz" ;
|
||||
defparam EFBInst_0.I2C2_SLAVE_ADDR = "0b1000010" ;
|
||||
defparam EFBInst_0.I2C2_ADDRESSING = "7BIT" ;
|
||||
defparam EFBInst_0.EFB_I2C2 = "DISABLED" ;
|
||||
defparam EFBInst_0.I2C1_WAKEUP = "DISABLED" ;
|
||||
defparam EFBInst_0.I2C1_GEN_CALL = "DISABLED" ;
|
||||
defparam EFBInst_0.I2C1_CLK_DIVIDER = 1 ;
|
||||
defparam EFBInst_0.I2C1_BUS_PERF = "100kHz" ;
|
||||
defparam EFBInst_0.I2C1_SLAVE_ADDR = "0b1000001" ;
|
||||
defparam EFBInst_0.I2C1_ADDRESSING = "7BIT" ;
|
||||
defparam EFBInst_0.EFB_I2C1 = "DISABLED" ;
|
||||
defparam EFBInst_0.EFB_WB_CLK_FREQ = "14.4" ;
|
||||
EFB EFBInst_0 (.WBCLKI(wb_clk_i), .WBRSTI(wb_rst_i), .WBCYCI(wb_cyc_i),
|
||||
.WBSTBI(wb_stb_i), .WBWEI(wb_we_i), .WBADRI7(wb_adr_i[7]), .WBADRI6(wb_adr_i[6]),
|
||||
.WBADRI5(wb_adr_i[5]), .WBADRI4(wb_adr_i[4]), .WBADRI3(wb_adr_i[3]),
|
||||
.WBADRI2(wb_adr_i[2]), .WBADRI1(wb_adr_i[1]), .WBADRI0(wb_adr_i[0]),
|
||||
.WBDATI7(wb_dat_i[7]), .WBDATI6(wb_dat_i[6]), .WBDATI5(wb_dat_i[5]),
|
||||
.WBDATI4(wb_dat_i[4]), .WBDATI3(wb_dat_i[3]), .WBDATI2(wb_dat_i[2]),
|
||||
.WBDATI1(wb_dat_i[1]), .WBDATI0(wb_dat_i[0]), .PLL0DATI7(scuba_vlo),
|
||||
.PLL0DATI6(scuba_vlo), .PLL0DATI5(scuba_vlo), .PLL0DATI4(scuba_vlo),
|
||||
.PLL0DATI3(scuba_vlo), .PLL0DATI2(scuba_vlo), .PLL0DATI1(scuba_vlo),
|
||||
.PLL0DATI0(scuba_vlo), .PLL0ACKI(scuba_vlo), .PLL1DATI7(scuba_vlo),
|
||||
.PLL1DATI6(scuba_vlo), .PLL1DATI5(scuba_vlo), .PLL1DATI4(scuba_vlo),
|
||||
.PLL1DATI3(scuba_vlo), .PLL1DATI2(scuba_vlo), .PLL1DATI1(scuba_vlo),
|
||||
.PLL1DATI0(scuba_vlo), .PLL1ACKI(scuba_vlo), .I2C1SCLI(scuba_vlo),
|
||||
.I2C1SDAI(scuba_vlo), .I2C2SCLI(scuba_vlo), .I2C2SDAI(scuba_vlo),
|
||||
.SPISCKI(scuba_vlo), .SPIMISOI(scuba_vlo), .SPIMOSII(scuba_vlo),
|
||||
.SPISCSN(scuba_vlo), .TCCLKI(scuba_vlo), .TCRSTN(scuba_vlo), .TCIC(scuba_vlo),
|
||||
.UFMSN(scuba_vhi), .WBDATO7(wb_dat_o[7]), .WBDATO6(wb_dat_o[6]),
|
||||
.WBDATO5(wb_dat_o[5]), .WBDATO4(wb_dat_o[4]), .WBDATO3(wb_dat_o[3]),
|
||||
.WBDATO2(wb_dat_o[2]), .WBDATO1(wb_dat_o[1]), .WBDATO0(wb_dat_o[0]),
|
||||
.WBACKO(wb_ack_o), .PLLCLKO(), .PLLRSTO(), .PLL0STBO(), .PLL1STBO(),
|
||||
.PLLWEO(), .PLLADRO4(), .PLLADRO3(), .PLLADRO2(), .PLLADRO1(), .PLLADRO0(),
|
||||
.PLLDATO7(), .PLLDATO6(), .PLLDATO5(), .PLLDATO4(), .PLLDATO3(),
|
||||
.PLLDATO2(), .PLLDATO1(), .PLLDATO0(), .I2C1SCLO(), .I2C1SCLOEN(),
|
||||
.I2C1SDAO(), .I2C1SDAOEN(), .I2C2SCLO(), .I2C2SCLOEN(), .I2C2SDAO(),
|
||||
.I2C2SDAOEN(), .I2C1IRQO(), .I2C2IRQO(), .SPISCKO(), .SPISCKEN(),
|
||||
.SPIMISOO(), .SPIMISOEN(), .SPIMOSIO(), .SPIMOSIEN(), .SPIMCSN7(),
|
||||
.SPIMCSN6(), .SPIMCSN5(), .SPIMCSN4(), .SPIMCSN3(), .SPIMCSN2(),
|
||||
.SPIMCSN1(), .SPIMCSN0(), .SPICSNEN(), .SPIIRQO(), .TCINT(), .TCOC(),
|
||||
.WBCUFMIRQ(wbc_ufm_irq), .CFGWAKE(), .CFGSTDBY());
|
||||
|
||||
|
||||
|
||||
// exemplar begin
|
||||
// exemplar end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
Starting process: Module
|
||||
|
||||
Starting process:
|
||||
|
||||
SCUBA, Version Diamond (64-bit) 3.12.1.454
|
||||
Wed Sep 20 04:45:58 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
BEGIN SCUBA Module Synthesis
|
||||
|
||||
Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 14.4 -ufm -ufm_ebr 190 -mem_size 321 -memfile ../RAM2E-LCMXO2.mem -memformat hex -wb -dev 1200
|
||||
Circuit name : REFB
|
||||
Module type : efb
|
||||
Module Version : 1.2
|
||||
Ports :
|
||||
Inputs : wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i[7:0], wb_dat_i[7:0]
|
||||
Outputs : wb_dat_o[7:0], wb_ack_o, wbc_ufm_irq
|
||||
I/O buffer : not inserted
|
||||
EDIF output : REFB.edn
|
||||
Verilog output : REFB.v
|
||||
Verilog template : REFB_tmpl.v
|
||||
Verilog purpose : for synthesis and simulation
|
||||
Bus notation : big endian
|
||||
Report output : REFB.srp
|
||||
Estimated Resource Usage:
|
||||
|
||||
END SCUBA Module Synthesis
|
||||
|
||||
File: REFB.lpc created.
|
||||
|
||||
|
||||
End process: completed successfully.
|
||||
|
||||
|
||||
Total Warnings: 0
|
||||
|
||||
Total Errors: 0
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.12.1.454 */
|
||||
/* Module Version: 1.2 */
|
||||
/* Wed Sep 20 04:45:58 2023 */
|
||||
|
||||
/* parameterized module instance */
|
||||
REFB __ (.wb_clk_i( ), .wb_rst_i( ), .wb_cyc_i( ), .wb_stb_i( ),
|
||||
.wb_we_i( ), .wb_adr_i( ), .wb_dat_i( ), .wb_dat_o( ), .wb_ack_o( ),
|
||||
.wbc_ufm_irq( ));
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,100 @@
|
|||
#!/usr/local/bin/wish
|
||||
|
||||
proc GetPlatform {} {
|
||||
global tcl_platform
|
||||
|
||||
set cpu $tcl_platform(machine)
|
||||
|
||||
switch $cpu {
|
||||
intel -
|
||||
i*86* {
|
||||
set cpu ix86
|
||||
}
|
||||
x86_64 {
|
||||
if {$tcl_platform(wordSize) == 4} {
|
||||
set cpu ix86
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
switch $tcl_platform(platform) {
|
||||
windows {
|
||||
if {$cpu == "amd64"} {
|
||||
# Do not check wordSize, win32-x64 is an IL32P64 platform.
|
||||
set cpu x86_64
|
||||
}
|
||||
if {$cpu == "x86_64"} {
|
||||
return "nt64"
|
||||
} else {
|
||||
return "nt"
|
||||
}
|
||||
}
|
||||
unix {
|
||||
if {$tcl_platform(os) == "Linux"} {
|
||||
if {$cpu == "x86_64"} {
|
||||
return "lin64"
|
||||
} else {
|
||||
return "lin"
|
||||
}
|
||||
} else {
|
||||
return "sol"
|
||||
}
|
||||
}
|
||||
}
|
||||
return "nt"
|
||||
}
|
||||
|
||||
proc GetCmdLine {lpcfile} {
|
||||
global Para
|
||||
|
||||
if [catch {open $lpcfile r} fileid] {
|
||||
puts "Cannot open $para_file file!"
|
||||
exit -1
|
||||
}
|
||||
|
||||
seek $fileid 0 start
|
||||
set default_match 0
|
||||
while {[gets $fileid line] >= 0} {
|
||||
if {[string first "\[Command\]" $line] == 0} {
|
||||
set default_match 1
|
||||
continue
|
||||
}
|
||||
if {[string first "\[" $line] == 0} {
|
||||
set default_match 0
|
||||
}
|
||||
if {$default_match == 1} {
|
||||
if [regexp {([^=]*)=(.*)} $line match parameter value] {
|
||||
if [regexp {([ |\t]*;)} $parameter match] {continue}
|
||||
if [regexp {(.*)[ |\t]*;} $value match temp] {
|
||||
set Para($parameter) $temp
|
||||
} else {
|
||||
set Para($parameter) $value
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
set default_match 0
|
||||
close $fileid
|
||||
|
||||
return $Para(cmd_line)
|
||||
}
|
||||
|
||||
set platformpath [GetPlatform]
|
||||
set Para(sbp_path) [file dirname [info script]]
|
||||
set Para(install_dir) $env(TOOLRTF)
|
||||
set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
|
||||
|
||||
set scuba "$Para(FPGAPath)/scuba"
|
||||
set modulename "REFB"
|
||||
set lang "verilog"
|
||||
set lpcfile "$Para(sbp_path)/$modulename.lpc"
|
||||
set arch "xo2c00"
|
||||
set cmd_line [GetCmdLine $lpcfile]
|
||||
set fdcfile "$Para(sbp_path)/$modulename.fdc"
|
||||
if {[file exists $fdcfile] == 0} {
|
||||
append scuba " " $cmd_line
|
||||
} else {
|
||||
append scuba " " $cmd_line " " -fdc " " \"$fdcfile\"
|
||||
}
|
||||
set Para(result) [catch {eval exec "$scuba"} msg]
|
||||
#puts $msg
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
#!/usr/local/bin/wish
|
||||
|
||||
proc GetPlatform {} {
|
||||
global tcl_platform
|
||||
|
||||
set cpu $tcl_platform(machine)
|
||||
|
||||
switch $cpu {
|
||||
intel -
|
||||
i*86* {
|
||||
set cpu ix86
|
||||
}
|
||||
x86_64 {
|
||||
if {$tcl_platform(wordSize) == 4} {
|
||||
set cpu ix86
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
switch $tcl_platform(platform) {
|
||||
windows {
|
||||
if {$cpu == "amd64"} {
|
||||
# Do not check wordSize, win32-x64 is an IL32P64 platform.
|
||||
set cpu x86_64
|
||||
}
|
||||
if {$cpu == "x86_64"} {
|
||||
return "nt64"
|
||||
} else {
|
||||
return "nt"
|
||||
}
|
||||
}
|
||||
unix {
|
||||
if {$tcl_platform(os) == "Linux"} {
|
||||
if {$cpu == "x86_64"} {
|
||||
return "lin64"
|
||||
} else {
|
||||
return "lin"
|
||||
}
|
||||
} else {
|
||||
return "sol"
|
||||
}
|
||||
}
|
||||
}
|
||||
return "nt"
|
||||
}
|
||||
|
||||
set platformpath [GetPlatform]
|
||||
set Para(sbp_path) [file dirname [info script]]
|
||||
set Para(install_dir) $env(TOOLRTF)
|
||||
set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
|
||||
set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]"
|
||||
|
||||
set Para(ModuleName) "REFB"
|
||||
set Para(Module) "EFB"
|
||||
set Para(libname) machxo2
|
||||
set Para(arch_name) xo2c00
|
||||
set Para(PartType) "LCMXO2-1200HC"
|
||||
|
||||
set Para(tech_syn) machxo2
|
||||
set Para(tech_cae) machxo2
|
||||
set Para(Package) "TQFP100"
|
||||
set Para(SpeedGrade) "4"
|
||||
set Para(FMax) "100"
|
||||
set fdcfile "$Para(sbp_path)/$Para(ModuleName).fdc"
|
||||
|
||||
#edif2ngd
|
||||
set edif2ngd "$Para(FPGAPath)/edif2ngd"
|
||||
set Para(result) [catch {eval exec $edif2ngd -l $Para(libname) -d $Para(PartType) -nopropwarn $Para(ModuleName).edn $Para(ModuleName).ngo} msg]
|
||||
#puts $msg
|
||||
|
||||
#ngdbuild
|
||||
set ngdbuild "$Para(FPGAPath)/ngdbuild"
|
||||
set Para(result) [catch {eval exec $ngdbuild -addiobuf -dt -a $Para(arch_name) $Para(ModuleName).ngo $Para(ModuleName).ngd} msg]
|
||||
#puts $msg
|
||||
|
|
@ -0,0 +1,78 @@
|
|||
NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
|
||||
NOTE All Rights Reserved *
|
||||
NOTE DATE CREATED: Thu Sep 21 05:35:26 2023 *
|
||||
NOTE DESIGN NAME: RAM2E *
|
||||
NOTE DEVICE NAME: LCMXO2-1200HC-4TQFP100 *
|
||||
NOTE PIN ASSIGNMENTS *
|
||||
NOTE PINS RD[0] : 36 : inout *
|
||||
NOTE PINS LED : 35 : out *
|
||||
NOTE PINS C14M : 62 : in *
|
||||
NOTE PINS DQMH : 49 : out *
|
||||
NOTE PINS DQML : 48 : out *
|
||||
NOTE PINS RD[7] : 43 : inout *
|
||||
NOTE PINS RD[6] : 42 : inout *
|
||||
NOTE PINS RD[5] : 41 : inout *
|
||||
NOTE PINS RD[4] : 40 : inout *
|
||||
NOTE PINS RD[3] : 39 : inout *
|
||||
NOTE PINS RD[2] : 38 : inout *
|
||||
NOTE PINS RD[1] : 37 : inout *
|
||||
NOTE PINS RA[11] : 59 : out *
|
||||
NOTE PINS RA[10] : 64 : out *
|
||||
NOTE PINS RA[9] : 63 : out *
|
||||
NOTE PINS RA[8] : 65 : out *
|
||||
NOTE PINS RA[7] : 67 : out *
|
||||
NOTE PINS RA[6] : 69 : out *
|
||||
NOTE PINS RA[5] : 71 : out *
|
||||
NOTE PINS RA[4] : 75 : out *
|
||||
NOTE PINS RA[3] : 74 : out *
|
||||
NOTE PINS RA[2] : 70 : out *
|
||||
NOTE PINS RA[1] : 68 : out *
|
||||
NOTE PINS RA[0] : 66 : out *
|
||||
NOTE PINS BA[1] : 60 : out *
|
||||
NOTE PINS BA[0] : 58 : out *
|
||||
NOTE PINS nRWE : 51 : out *
|
||||
NOTE PINS nCAS : 52 : out *
|
||||
NOTE PINS nRAS : 54 : out *
|
||||
NOTE PINS nCS : 57 : out *
|
||||
NOTE PINS CKE : 53 : out *
|
||||
NOTE PINS nVOE : 10 : out *
|
||||
NOTE PINS Vout[7] : 12 : out *
|
||||
NOTE PINS Vout[6] : 14 : out *
|
||||
NOTE PINS Vout[5] : 16 : out *
|
||||
NOTE PINS Vout[4] : 19 : out *
|
||||
NOTE PINS Vout[3] : 13 : out *
|
||||
NOTE PINS Vout[2] : 17 : out *
|
||||
NOTE PINS Vout[1] : 15 : out *
|
||||
NOTE PINS Vout[0] : 18 : out *
|
||||
NOTE PINS nDOE : 20 : out *
|
||||
NOTE PINS Dout[7] : 32 : out *
|
||||
NOTE PINS Dout[6] : 31 : out *
|
||||
NOTE PINS Dout[5] : 21 : out *
|
||||
NOTE PINS Dout[4] : 24 : out *
|
||||
NOTE PINS Dout[3] : 28 : out *
|
||||
NOTE PINS Dout[2] : 25 : out *
|
||||
NOTE PINS Dout[1] : 27 : out *
|
||||
NOTE PINS Dout[0] : 30 : out *
|
||||
NOTE PINS Din[7] : 87 : in *
|
||||
NOTE PINS Din[6] : 88 : in *
|
||||
NOTE PINS Din[5] : 99 : in *
|
||||
NOTE PINS Din[4] : 1 : in *
|
||||
NOTE PINS Din[3] : 9 : in *
|
||||
NOTE PINS Din[2] : 98 : in *
|
||||
NOTE PINS Din[1] : 97 : in *
|
||||
NOTE PINS Din[0] : 96 : in *
|
||||
NOTE PINS Ain[7] : 8 : in *
|
||||
NOTE PINS Ain[6] : 86 : in *
|
||||
NOTE PINS Ain[5] : 84 : in *
|
||||
NOTE PINS Ain[4] : 78 : in *
|
||||
NOTE PINS Ain[3] : 4 : in *
|
||||
NOTE PINS Ain[2] : 7 : in *
|
||||
NOTE PINS Ain[1] : 2 : in *
|
||||
NOTE PINS Ain[0] : 3 : in *
|
||||
NOTE PINS nC07X : 34 : in *
|
||||
NOTE PINS nEN80 : 82 : in *
|
||||
NOTE PINS nWE80 : 83 : in *
|
||||
NOTE PINS nWE : 29 : in *
|
||||
NOTE PINS PHI1 : 85 : in *
|
||||
NOTE CONFIGURATION MODE: NONE *
|
||||
NOTE COMPRESSION: on *
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
----------------------------------------------------------------------
|
||||
Report for cell RAM2E.verilog
|
||||
|
||||
Register bits: 111 of 1280 (9%)
|
||||
PIC Latch: 0
|
||||
I/O cells: 70
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
BB 8 100.0
|
||||
CCU2D 9 100.0
|
||||
EFB 1 100.0
|
||||
FD1P3AX 48 100.0
|
||||
FD1P3IX 1 100.0
|
||||
FD1S3AX 22 100.0
|
||||
FD1S3IX 4 100.0
|
||||
GSR 1 100.0
|
||||
IB 22 100.0
|
||||
IFS1P3DX 1 100.0
|
||||
INV 1 100.0
|
||||
OB 40 100.0
|
||||
OFS1P3BX 6 100.0
|
||||
OFS1P3DX 27 100.0
|
||||
OFS1P3IX 2 100.0
|
||||
ORCALUT4 221 100.0
|
||||
PUR 1 100.0
|
||||
VHI 2 100.0
|
||||
VLO 2 100.0
|
||||
SUB MODULES
|
||||
REFB 1 100.0
|
||||
|
||||
TOTAL 420
|
||||
----------------------------------------------------------------------
|
||||
Report for cell REFB.netlist
|
||||
Instance path: ufmefb
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
EFB 1 100.0
|
||||
VHI 1 50.0
|
||||
VLO 1 50.0
|
||||
|
||||
TOTAL 3
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Thu Sep 21 05:35:21 2023
|
||||
|
||||
|
||||
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC -w -jedec -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1.ncd RAM2E_LCMXO2_1200HC_impl1.prf
|
||||
|
||||
Loading design for application Bitgen from file RAM2E_LCMXO2_1200HC_impl1.ncd.
|
||||
Design name: RAM2E
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-1200HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application Bitgen from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.44.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
|
||||
Running DRC.
|
||||
DRC detected 0 errors and 0 warnings.
|
||||
Reading Preference File from RAM2E_LCMXO2_1200HC_impl1.prf.
|
||||
|
||||
Preference Summary:
|
||||
+---------------------------------+---------------------------------+
|
||||
| Preference | Current Setting |
|
||||
+---------------------------------+---------------------------------+
|
||||
| RamCfg | Reset** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MCCLK_FREQ | 2.08** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| CONFIG_SECURE | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| INBUF | ON** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| JTAG_PORT | ENABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SDM_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SLAVE_SPI_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MASTER_SPI_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| I2C_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MUX_CONFIGURATION_PORTS | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| CONFIGURATION | CFG** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| COMPRESS_CONFIG | ON** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MY_ASSP | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| ONE_TIME_PROGRAM | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| ENABLE_TRANSFR | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SHAREDEBRINIT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| BACKGROUND_RECONFIG | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
* Default setting.
|
||||
** The specified setting matches the default setting.
|
||||
|
||||
|
||||
Creating bit map...
|
||||
|
||||
Bitstream Status: Final Version 1.95.
|
||||
|
||||
Saving bit stream in "RAM2E_LCMXO2_1200HC_impl1.jed".
|
||||
|
||||
===========
|
||||
UFM Summary.
|
||||
===========
|
||||
UFM Size: 511 Pages (128*511 Bits).
|
||||
UFM Utilization: General Purpose Flash Memory.
|
||||
|
||||
Available General Purpose Flash Memory: 511 Pages (Page 0 to Page 510).
|
||||
Initialized UFM Pages: 321 Pages (Page 190 to Page 510).
|
||||
|
||||
Total CPU Time: 4 secs
|
||||
Total REAL Time: 5 secs
|
||||
Peak Memory Usage: 275 MB
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,468 @@
|
|||
|
||||
Lattice Mapping Report File for Design Module 'RAM2E'
|
||||
|
||||
|
||||
Design Information
|
||||
------------------
|
||||
|
||||
Command line: map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 4 -oc Commercial
|
||||
RAM2E_LCMXO2_1200HC_impl1.ngd -o RAM2E_LCMXO2_1200HC_impl1_map.ncd -pr
|
||||
RAM2E_LCMXO2_1200HC_impl1.prf -mp RAM2E_LCMXO2_1200HC_impl1.mrp -lpf //Mac/
|
||||
iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_synpl
|
||||
ify.lpf -lpf //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf -c 0 -gui
|
||||
-msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml
|
||||
Target Vendor: LATTICE
|
||||
Target Device: LCMXO2-1200HCTQFP100
|
||||
Target Performance: 4
|
||||
Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454
|
||||
Mapped on: 09/21/23 05:34:46
|
||||
|
||||
Design Summary
|
||||
--------------
|
||||
|
||||
Number of registers: 111 out of 1520 (7%)
|
||||
PFU registers: 75 out of 1280 (6%)
|
||||
PIO registers: 36 out of 240 (15%)
|
||||
Number of SLICEs: 120 out of 640 (19%)
|
||||
SLICEs as Logic/ROM: 120 out of 640 (19%)
|
||||
SLICEs as RAM: 0 out of 480 (0%)
|
||||
SLICEs as Carry: 9 out of 640 (1%)
|
||||
Number of LUT4s: 239 out of 1280 (19%)
|
||||
Number used as logic LUTs: 221
|
||||
Number used as distributed RAM: 0
|
||||
Number used as ripple logic: 18
|
||||
Number used as shift registers: 0
|
||||
Number of PIO sites used: 70 + 4(JTAG) out of 80 (93%)
|
||||
Number of block RAMs: 0 out of 7 (0%)
|
||||
Number of GSRs: 0 out of 1 (0%)
|
||||
EFB used : Yes
|
||||
JTAG used : No
|
||||
Readback used : No
|
||||
Oscillator used : No
|
||||
Startup used : No
|
||||
POR : On
|
||||
Bandgap : On
|
||||
Number of Power Controller: 0 out of 1 (0%)
|
||||
Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
|
||||
Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%)
|
||||
Number of DCCA: 0 out of 8 (0%)
|
||||
Number of DCMA: 0 out of 2 (0%)
|
||||
Number of PLLs: 0 out of 1 (0%)
|
||||
Number of DQSDLLs: 0 out of 2 (0%)
|
||||
Number of CLKDIVC: 0 out of 4 (0%)
|
||||
Number of ECLKSYNCA: 0 out of 4 (0%)
|
||||
Number of ECLKBRIDGECS: 0 out of 2 (0%)
|
||||
Notes:-
|
||||
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
|
||||
distributed RAMs) + 2*(Number of ripple logic)
|
||||
2. Number of logic LUT4s does not include count of distributed RAM and
|
||||
ripple logic.
|
||||
Number of clocks: 1
|
||||
Net C14M_c: 84 loads, 68 rising, 16 falling (Driver: PIO C14M )
|
||||
Number of Clock Enables: 11
|
||||
|
||||
Page 1
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 09/21/23 05:34:46
|
||||
|
||||
Design Summary (cont)
|
||||
---------------------
|
||||
Net wb_adr_0_sqmuxa_i: 1 loads, 1 LSLICEs
|
||||
Net N_576_i: 17 loads, 9 LSLICEs
|
||||
Net LEDEN13: 4 loads, 4 LSLICEs
|
||||
Net nCS61: 1 loads, 1 LSLICEs
|
||||
Net Vout3: 8 loads, 0 LSLICEs
|
||||
Net S_RNII9DO1_1[1]: 7 loads, 1 LSLICEs
|
||||
Net un1_wb_cyc_stb_0_sqmuxa_1_i[0]: 1 loads, 1 LSLICEs
|
||||
Net un1_wb_adr_0_sqmuxa_2_i[0]: 8 loads, 8 LSLICEs
|
||||
Net N_104: 1 loads, 1 LSLICEs
|
||||
Net N_88: 4 loads, 4 LSLICEs
|
||||
Net un1_LEDEN_0_sqmuxa_1_i_0[0]: 1 loads, 1 LSLICEs
|
||||
Number of LSRs: 5
|
||||
Net un1_CS_0_sqmuxa_i: 2 loads, 2 LSLICEs
|
||||
Net S[2]: 1 loads, 1 LSLICEs
|
||||
Net N_566_i: 2 loads, 0 LSLICEs
|
||||
Net wb_rst: 1 loads, 0 LSLICEs
|
||||
Net S_RNII9DO1[1]: 1 loads, 1 LSLICEs
|
||||
Number of nets driven by tri-state buffers: 0
|
||||
Top 10 highest fanout non-clock nets:
|
||||
Net S[2]: 48 loads
|
||||
Net S[3]: 48 loads
|
||||
Net S[0]: 30 loads
|
||||
Net FS[12]: 22 loads
|
||||
Net FS[9]: 21 loads
|
||||
Net S[1]: 21 loads
|
||||
Net FS[10]: 20 loads
|
||||
Net FS[11]: 19 loads
|
||||
Net RWSel: 19 loads
|
||||
Net FS[13]: 17 loads
|
||||
|
||||
|
||||
|
||||
|
||||
Number of warnings: 1
|
||||
Number of errors: 0
|
||||
|
||||
|
||||
Design Errors/Warnings
|
||||
----------------------
|
||||
|
||||
WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
||||
temporarily disable certain features of the device including Power
|
||||
Controller, GSR, Hardened User SPI Port, Hardened Primary User I2C Port.
|
||||
Functionality is restored after the Flash Memory (UFM/Configuration)
|
||||
Interface is disabled using Disable Configuration Interface command 0x26
|
||||
followed by Bypass command 0xFF.
|
||||
|
||||
IO (PIO) Attributes
|
||||
-------------------
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| IO Name | Direction | Levelmode | IO |
|
||||
| | | IO_TYPE | Register |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[0] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
Page 2
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 09/21/23 05:34:46
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
| LED | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| C14M | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| DQMH | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| DQML | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[7] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[6] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[5] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[4] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[3] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[2] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[1] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[11] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[10] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[9] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[8] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[7] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[6] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[5] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[4] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[3] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[2] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[1] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[0] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| BA[1] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| BA[0] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRWE | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nCAS | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRAS | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
Page 3
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 09/21/23 05:34:46
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
| nCS | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| CKE | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nVOE | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Vout[7] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Vout[6] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Vout[5] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Vout[4] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Vout[3] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Vout[2] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Vout[1] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Vout[0] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nDOE | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[7] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[6] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[5] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[4] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[3] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[2] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[1] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[0] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[7] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[6] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[5] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[4] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[3] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[2] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[1] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[0] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
Page 4
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 09/21/23 05:34:46
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
| Ain[7] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Ain[6] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Ain[5] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Ain[4] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Ain[3] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Ain[2] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Ain[1] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Ain[0] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nC07X | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nEN80 | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nWE80 | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nWE | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| PHI1 | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
Removed logic
|
||||
-------------
|
||||
|
||||
Block GSR_INST undriven or does not drive anything - clipped.
|
||||
Signal Dout_0_.CN was merged into signal C14M_c
|
||||
Signal GND undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/VCC undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/GND undriven or does not drive anything - clipped.
|
||||
Signal FS_s_0_S1[15] undriven or does not drive anything - clipped.
|
||||
Signal FS_s_0_COUT[15] undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/CFGWAKE undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wbc_ufm_irq undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/TCOC undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/TCINT undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIIRQO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPICSNEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMOSIEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMOSIO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMISOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMISOO undriven or does not drive anything - clipped.
|
||||
|
||||
Page 5
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 09/21/23 05:34:46
|
||||
|
||||
Removed logic (cont)
|
||||
--------------------
|
||||
Signal ufmefb/SPISCKEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPISCKO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SDAOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SCLOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SDAOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SCLOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO4 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLWEO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLL1STBO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLL0STBO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLRSTO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLCLKO undriven or does not drive anything - clipped.
|
||||
Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped.
|
||||
Signal N_1 undriven or does not drive anything - clipped.
|
||||
Block Vout_0_.CN was optimized away.
|
||||
Block GND was optimized away.
|
||||
Block ufmefb/VCC was optimized away.
|
||||
Block ufmefb/GND was optimized away.
|
||||
|
||||
|
||||
|
||||
Embedded Functional Block Connection Summary
|
||||
--------------------------------------------
|
||||
|
||||
Desired WISHBONE clock frequency: 14.4 MHz
|
||||
Clock source: C14M_c
|
||||
Reset source: wb_rst
|
||||
Functions mode:
|
||||
I2C #1 (Primary) Function: DISABLED
|
||||
I2C #2 (Secondary) Function: DISABLED
|
||||
SPI Function: DISABLED
|
||||
Timer/Counter Function: DISABLED
|
||||
Timer/Counter Mode: WB
|
||||
UFM Connection: ENABLED
|
||||
PLL0 Connection: DISABLED
|
||||
PLL1 Connection: DISABLED
|
||||
I2C Function Summary:
|
||||
--------------------
|
||||
|
||||
Page 6
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 09/21/23 05:34:46
|
||||
|
||||
Embedded Functional Block Connection Summary (cont)
|
||||
---------------------------------------------------
|
||||
None
|
||||
SPI Function Summary:
|
||||
--------------------
|
||||
None
|
||||
Timer/Counter Function Summary:
|
||||
------------------------------
|
||||
None
|
||||
UFM Function Summary:
|
||||
--------------------
|
||||
UFM Utilization: General Purpose Flash Memory
|
||||
Initialized UFM Pages: 321 Pages (321*128 Bits)
|
||||
Available General
|
||||
Purpose Flash Memory: 511 Pages (511*128 Bits)
|
||||
|
||||
EBR Blocks with Unique
|
||||
Initialization Data: 0
|
||||
|
||||
WID EBR Instance
|
||||
--- ------------
|
||||
|
||||
|
||||
ASIC Components
|
||||
---------------
|
||||
|
||||
Instance Name: ufmefb/EFBInst_0
|
||||
Type: EFB
|
||||
|
||||
Run Time and Memory Usage
|
||||
-------------------------
|
||||
|
||||
Total CPU Time: 1 secs
|
||||
Total REAL Time: 0 secs
|
||||
Peak Memory Usage: 63 MB
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Page 7
|
||||
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights
|
||||
reserved.
|
||||
|
|
@ -0,0 +1,315 @@
|
|||
PAD Specification File
|
||||
***************************
|
||||
|
||||
PART TYPE: LCMXO2-1200HC
|
||||
Performance Grade: 4
|
||||
PACKAGE: TQFP100
|
||||
Package Status: Final Version 1.44
|
||||
|
||||
Thu Sep 21 05:34:59 2023
|
||||
|
||||
Pinout by Port Name:
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties |
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
| Ain[0] | 3/3 | LVCMOS33_IN | PL3A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Ain[1] | 2/3 | LVCMOS33_IN | PL2D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Ain[2] | 7/3 | LVCMOS33_IN | PL3C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Ain[3] | 4/3 | LVCMOS33_IN | PL3B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Ain[4] | 78/0 | LVCMOS33_IN | PT16C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Ain[5] | 84/0 | LVCMOS33_IN | PT15A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Ain[6] | 86/0 | LVCMOS33_IN | PT12C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Ain[7] | 8/3 | LVCMOS33_IN | PL3D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| BA[0] | 58/1 | LVCMOS33_OUT | PR9A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| BA[1] | 60/1 | LVCMOS33_OUT | PR8C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| C14M | 62/1 | LVCMOS33_IN | PR5D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| CKE | 53/1 | LVCMOS33_OUT | PR9D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| DQMH | 49/2 | LVCMOS33_OUT | PB20D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| DQML | 48/2 | LVCMOS33_OUT | PB20C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Din[0] | 96/0 | LVCMOS33_IN | PT10B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[1] | 97/0 | LVCMOS33_IN | PT10A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[2] | 98/0 | LVCMOS33_IN | PT9B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[3] | 9/3 | LVCMOS33_IN | PL4A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[4] | 1/3 | LVCMOS33_IN | PL2C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[5] | 99/0 | LVCMOS33_IN | PT9A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[6] | 88/0 | LVCMOS33_IN | PT12A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[7] | 87/0 | LVCMOS33_IN | PT12B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Dout[0] | 30/2 | LVCMOS33_OUT | PB6B | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[1] | 27/2 | LVCMOS33_OUT | PB4C | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[2] | 25/3 | LVCMOS33_OUT | PL10D | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[3] | 28/2 | LVCMOS33_OUT | PB4D | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[4] | 24/3 | LVCMOS33_OUT | PL10C | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[5] | 21/3 | LVCMOS33_OUT | PL9B | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[6] | 31/2 | LVCMOS33_OUT | PB6C | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[7] | 32/2 | LVCMOS33_OUT | PB6D | | | DRIVE:4mA SLEW:FAST |
|
||||
| LED | 35/2 | LVCMOS33_OUT | PB9B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| PHI1 | 85/0 | LVCMOS33_IN | PT12D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| RA[0] | 66/1 | LVCMOS33_OUT | PR4D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[10] | 64/1 | LVCMOS33_OUT | PR5B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[11] | 59/1 | LVCMOS33_OUT | PR8D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[1] | 68/1 | LVCMOS33_OUT | PR4B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[2] | 70/1 | LVCMOS33_OUT | PR3B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[3] | 74/1 | LVCMOS33_OUT | PR2B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[4] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[5] | 71/1 | LVCMOS33_OUT | PR3A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[6] | 69/1 | LVCMOS33_OUT | PR4A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[7] | 67/1 | LVCMOS33_OUT | PR4C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[9] | 63/1 | LVCMOS33_OUT | PR5C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RD[0] | 36/2 | LVCMOS33_BIDI | PB11C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[1] | 37/2 | LVCMOS33_BIDI | PB11D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[2] | 38/2 | LVCMOS33_BIDI | PB11A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[3] | 39/2 | LVCMOS33_BIDI | PB11B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[4] | 40/2 | LVCMOS33_BIDI | PB15A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[5] | 41/2 | LVCMOS33_BIDI | PB15B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[6] | 42/2 | LVCMOS33_BIDI | PB18A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[7] | 43/2 | LVCMOS33_BIDI | PB18B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| Vout[0] | 18/3 | LVCMOS33_OUT | PL8C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Vout[1] | 15/3 | LVCMOS33_OUT | PL5D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Vout[2] | 17/3 | LVCMOS33_OUT | PL8B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Vout[3] | 13/3 | LVCMOS33_OUT | PL5B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Vout[4] | 19/3 | LVCMOS33_OUT | PL8D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Vout[5] | 16/3 | LVCMOS33_OUT | PL8A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Vout[6] | 14/3 | LVCMOS33_OUT | PL5C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Vout[7] | 12/3 | LVCMOS33_OUT | PL5A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nC07X | 34/2 | LVCMOS33_IN | PB9A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nCAS | 52/1 | LVCMOS33_OUT | PR10C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nCS | 57/1 | LVCMOS33_OUT | PR9B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nDOE | 20/3 | LVCMOS33_OUT | PL9A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nEN80 | 82/0 | LVCMOS33_IN | PT15C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nRAS | 54/1 | LVCMOS33_OUT | PR9C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nRWE | 51/1 | LVCMOS33_OUT | PR10D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nVOE | 10/3 | LVCMOS33_OUT | PL4B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nWE | 29/2 | LVCMOS33_IN | PB6A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nWE80 | 83/0 | LVCMOS33_IN | PT15B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
|
||||
Vccio by Bank:
|
||||
+------+-------+
|
||||
| Bank | Vccio |
|
||||
+------+-------+
|
||||
| 0 | 3.3V |
|
||||
| 1 | 3.3V |
|
||||
| 2 | 3.3V |
|
||||
| 3 | 3.3V |
|
||||
+------+-------+
|
||||
|
||||
Vref by Bank:
|
||||
+------+-----+-----------------+---------+
|
||||
| Vref | Pin | Bank # / Vref # | Load(s) |
|
||||
+------+-----+-----------------+---------+
|
||||
+------+-----+-----------------+---------+
|
||||
|
||||
Pinout by Pin Number:
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable |
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
| 1/3 | Din[4] | LOCATED | LVCMOS33_IN | PL2C | L_GPLLT_IN | | |
|
||||
| 2/3 | Ain[1] | LOCATED | LVCMOS33_IN | PL2D | L_GPLLC_IN | | |
|
||||
| 3/3 | Ain[0] | LOCATED | LVCMOS33_IN | PL3A | PCLKT3_2 | | |
|
||||
| 4/3 | Ain[3] | LOCATED | LVCMOS33_IN | PL3B | PCLKC3_2 | | |
|
||||
| 7/3 | Ain[2] | LOCATED | LVCMOS33_IN | PL3C | | | |
|
||||
| 8/3 | Ain[7] | LOCATED | LVCMOS33_IN | PL3D | | | |
|
||||
| 9/3 | Din[3] | LOCATED | LVCMOS33_IN | PL4A | | | |
|
||||
| 10/3 | nVOE | LOCATED | LVCMOS33_OUT | PL4B | | | |
|
||||
| 12/3 | Vout[7] | LOCATED | LVCMOS33_OUT | PL5A | PCLKT3_1 | | |
|
||||
| 13/3 | Vout[3] | LOCATED | LVCMOS33_OUT | PL5B | PCLKC3_1 | | |
|
||||
| 14/3 | Vout[6] | LOCATED | LVCMOS33_OUT | PL5C | | | |
|
||||
| 15/3 | Vout[1] | LOCATED | LVCMOS33_OUT | PL5D | | | |
|
||||
| 16/3 | Vout[5] | LOCATED | LVCMOS33_OUT | PL8A | | | |
|
||||
| 17/3 | Vout[2] | LOCATED | LVCMOS33_OUT | PL8B | | | |
|
||||
| 18/3 | Vout[0] | LOCATED | LVCMOS33_OUT | PL8C | | | |
|
||||
| 19/3 | Vout[4] | LOCATED | LVCMOS33_OUT | PL8D | | | |
|
||||
| 20/3 | nDOE | LOCATED | LVCMOS33_OUT | PL9A | PCLKT3_0 | | |
|
||||
| 21/3 | Dout[5] | LOCATED | LVCMOS33_OUT | PL9B | PCLKC3_0 | | |
|
||||
| 24/3 | Dout[4] | LOCATED | LVCMOS33_OUT | PL10C | | | |
|
||||
| 25/3 | Dout[2] | LOCATED | LVCMOS33_OUT | PL10D | | | |
|
||||
| 27/2 | Dout[1] | LOCATED | LVCMOS33_OUT | PB4C | CSSPIN | | |
|
||||
| 28/2 | Dout[3] | LOCATED | LVCMOS33_OUT | PB4D | | | |
|
||||
| 29/2 | nWE | LOCATED | LVCMOS33_IN | PB6A | | | |
|
||||
| 30/2 | Dout[0] | LOCATED | LVCMOS33_OUT | PB6B | | | |
|
||||
| 31/2 | Dout[6] | LOCATED | LVCMOS33_OUT | PB6C | MCLK/CCLK | | |
|
||||
| 32/2 | Dout[7] | LOCATED | LVCMOS33_OUT | PB6D | SO/SPISO | | |
|
||||
| 34/2 | nC07X | LOCATED | LVCMOS33_IN | PB9A | PCLKT2_0 | | |
|
||||
| 35/2 | LED | LOCATED | LVCMOS33_OUT | PB9B | PCLKC2_0 | | |
|
||||
| 36/2 | RD[0] | LOCATED | LVCMOS33_BIDI | PB11C | | | |
|
||||
| 37/2 | RD[1] | LOCATED | LVCMOS33_BIDI | PB11D | | | |
|
||||
| 38/2 | RD[2] | LOCATED | LVCMOS33_BIDI | PB11A | PCLKT2_1 | | |
|
||||
| 39/2 | RD[3] | LOCATED | LVCMOS33_BIDI | PB11B | PCLKC2_1 | | |
|
||||
| 40/2 | RD[4] | LOCATED | LVCMOS33_BIDI | PB15A | | | |
|
||||
| 41/2 | RD[5] | LOCATED | LVCMOS33_BIDI | PB15B | | | |
|
||||
| 42/2 | RD[6] | LOCATED | LVCMOS33_BIDI | PB18A | | | |
|
||||
| 43/2 | RD[7] | LOCATED | LVCMOS33_BIDI | PB18B | | | |
|
||||
| 45/2 | unused, PULL:DOWN | | | PB18C | | | |
|
||||
| 47/2 | unused, PULL:DOWN | | | PB18D | | | |
|
||||
| 48/2 | DQML | LOCATED | LVCMOS33_OUT | PB20C | SN | | |
|
||||
| 49/2 | DQMH | LOCATED | LVCMOS33_OUT | PB20D | SI/SISPI | | |
|
||||
| 51/1 | nRWE | LOCATED | LVCMOS33_OUT | PR10D | DQ1 | | |
|
||||
| 52/1 | nCAS | LOCATED | LVCMOS33_OUT | PR10C | DQ1 | | |
|
||||
| 53/1 | CKE | LOCATED | LVCMOS33_OUT | PR9D | DQ1 | | |
|
||||
| 54/1 | nRAS | LOCATED | LVCMOS33_OUT | PR9C | DQ1 | | |
|
||||
| 57/1 | nCS | LOCATED | LVCMOS33_OUT | PR9B | DQ1 | | |
|
||||
| 58/1 | BA[0] | LOCATED | LVCMOS33_OUT | PR9A | DQ1 | | |
|
||||
| 59/1 | RA[11] | LOCATED | LVCMOS33_OUT | PR8D | DQ1 | | |
|
||||
| 60/1 | BA[1] | LOCATED | LVCMOS33_OUT | PR8C | DQ1 | | |
|
||||
| 61/1 | unused, PULL:DOWN | | | PR8A | DQS1 | | |
|
||||
| 62/1 | C14M | LOCATED | LVCMOS33_IN | PR5D | PCLKC1_0/DQ0 | | |
|
||||
| 63/1 | RA[9] | LOCATED | LVCMOS33_OUT | PR5C | PCLKT1_0/DQ0 | | |
|
||||
| 64/1 | RA[10] | LOCATED | LVCMOS33_OUT | PR5B | DQS0N | | |
|
||||
| 65/1 | RA[8] | LOCATED | LVCMOS33_OUT | PR5A | DQS0 | | |
|
||||
| 66/1 | RA[0] | LOCATED | LVCMOS33_OUT | PR4D | DQ0 | | |
|
||||
| 67/1 | RA[7] | LOCATED | LVCMOS33_OUT | PR4C | DQ0 | | |
|
||||
| 68/1 | RA[1] | LOCATED | LVCMOS33_OUT | PR4B | DQ0 | | |
|
||||
| 69/1 | RA[6] | LOCATED | LVCMOS33_OUT | PR4A | DQ0 | | |
|
||||
| 70/1 | RA[2] | LOCATED | LVCMOS33_OUT | PR3B | DQ0 | | |
|
||||
| 71/1 | RA[5] | LOCATED | LVCMOS33_OUT | PR3A | DQ0 | | |
|
||||
| 74/1 | RA[3] | LOCATED | LVCMOS33_OUT | PR2B | DQ0 | | |
|
||||
| 75/1 | RA[4] | LOCATED | LVCMOS33_OUT | PR2A | DQ0 | | |
|
||||
| 76/0 | unused, PULL:DOWN | | | PT17D | DONE | | |
|
||||
| 77/0 | unused, PULL:DOWN | | | PT17C | INITN | | |
|
||||
| 78/0 | Ain[4] | LOCATED | LVCMOS33_IN | PT16C | | | |
|
||||
| 81/0 | unused, PULL:DOWN | | | PT15D | PROGRAMN | | |
|
||||
| 82/0 | nEN80 | LOCATED | LVCMOS33_IN | PT15C | JTAGENB | | |
|
||||
| 83/0 | nWE80 | LOCATED | LVCMOS33_IN | PT15B | | | |
|
||||
| 84/0 | Ain[5] | LOCATED | LVCMOS33_IN | PT15A | | | |
|
||||
| 85/0 | PHI1 | LOCATED | LVCMOS33_IN | PT12D | SDA/PCLKC0_0 | | |
|
||||
| 86/0 | Ain[6] | LOCATED | LVCMOS33_IN | PT12C | SCL/PCLKT0_0 | | |
|
||||
| 87/0 | Din[7] | LOCATED | LVCMOS33_IN | PT12B | PCLKC0_1 | | |
|
||||
| 88/0 | Din[6] | LOCATED | LVCMOS33_IN | PT12A | PCLKT0_1 | | |
|
||||
| 90/0 | Reserved: sysCONFIG | | | PT11D | TMS | | |
|
||||
| 91/0 | Reserved: sysCONFIG | | | PT11C | TCK | | |
|
||||
| 94/0 | Reserved: sysCONFIG | | | PT10D | TDI | | |
|
||||
| 95/0 | Reserved: sysCONFIG | | | PT10C | TDO | | |
|
||||
| 96/0 | Din[0] | LOCATED | LVCMOS33_IN | PT10B | | | |
|
||||
| 97/0 | Din[1] | LOCATED | LVCMOS33_IN | PT10A | | | |
|
||||
| 98/0 | Din[2] | LOCATED | LVCMOS33_IN | PT9B | | | |
|
||||
| 99/0 | Din[5] | LOCATED | LVCMOS33_IN | PT9A | | | |
|
||||
| PB4A/2 | unused, PULL:DOWN | | | PB4A | | | |
|
||||
| PB4B/2 | unused, PULL:DOWN | | | PB4B | | | |
|
||||
| PB9C/2 | unused, PULL:DOWN | | | PB9C | | | |
|
||||
| PB9D/2 | unused, PULL:DOWN | | | PB9D | | | |
|
||||
| PB15C/2 | unused, PULL:DOWN | | | PB15C | | | |
|
||||
| PB15D/2 | unused, PULL:DOWN | | | PB15D | | | |
|
||||
| PB20A/2 | unused, PULL:DOWN | | | PB20A | | | |
|
||||
| PB20B/2 | unused, PULL:DOWN | | | PB20B | | | |
|
||||
| PL2A/3 | unused, PULL:DOWN | | | PL2A | L_GPLLT_FB | | |
|
||||
| PL2B/3 | unused, PULL:DOWN | | | PL2B | L_GPLLC_FB | | |
|
||||
| PL4C/3 | unused, PULL:DOWN | | | PL4C | | | |
|
||||
| PL4D/3 | unused, PULL:DOWN | | | PL4D | | | |
|
||||
| PL10A/3 | unused, PULL:DOWN | | | PL10A | | | |
|
||||
| PL10B/3 | unused, PULL:DOWN | | | PL10B | | | |
|
||||
| PR2C/1 | unused, PULL:DOWN | | | PR2C | DQ0 | | |
|
||||
| PR2D/1 | unused, PULL:DOWN | | | PR2D | DQ0 | | |
|
||||
| PR8B/1 | unused, PULL:DOWN | | | PR8B | DQS1N | | |
|
||||
| PR10A/1 | unused, PULL:DOWN | | | PR10A | DQ1 | | |
|
||||
| PR10B/1 | unused, PULL:DOWN | | | PR10B | DQ1 | | |
|
||||
| PT9C/0 | unused, PULL:DOWN | | | PT9C | | | |
|
||||
| PT9D/0 | unused, PULL:DOWN | | | PT9D | | | |
|
||||
| PT11A/0 | unused, PULL:DOWN | | | PT11A | | | |
|
||||
| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | |
|
||||
| PT16A/0 | unused, PULL:DOWN | | | PT16A | | | |
|
||||
| PT16B/0 | unused, PULL:DOWN | | | PT16B | | | |
|
||||
| PT16D/0 | unused, PULL:DOWN | | | PT16D | | | |
|
||||
| PT17A/0 | unused, PULL:DOWN | | | PT17A | | | |
|
||||
| PT17B/0 | unused, PULL:DOWN | | | PT17B | | | |
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
|
||||
sysCONFIG Pins:
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode |
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
| PT11D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP |
|
||||
| PT11C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down |
|
||||
| PT10D | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP |
|
||||
| PT10C | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP |
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
|
||||
Dedicated sysCONFIG Pins:
|
||||
|
||||
|
||||
List of All Pins' Locate Preferences Based on Final Placement After PAR
|
||||
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste):
|
||||
|
||||
LOCATE COMP "Ain[0]" SITE "3";
|
||||
LOCATE COMP "Ain[1]" SITE "2";
|
||||
LOCATE COMP "Ain[2]" SITE "7";
|
||||
LOCATE COMP "Ain[3]" SITE "4";
|
||||
LOCATE COMP "Ain[4]" SITE "78";
|
||||
LOCATE COMP "Ain[5]" SITE "84";
|
||||
LOCATE COMP "Ain[6]" SITE "86";
|
||||
LOCATE COMP "Ain[7]" SITE "8";
|
||||
LOCATE COMP "BA[0]" SITE "58";
|
||||
LOCATE COMP "BA[1]" SITE "60";
|
||||
LOCATE COMP "C14M" SITE "62";
|
||||
LOCATE COMP "CKE" SITE "53";
|
||||
LOCATE COMP "DQMH" SITE "49";
|
||||
LOCATE COMP "DQML" SITE "48";
|
||||
LOCATE COMP "Din[0]" SITE "96";
|
||||
LOCATE COMP "Din[1]" SITE "97";
|
||||
LOCATE COMP "Din[2]" SITE "98";
|
||||
LOCATE COMP "Din[3]" SITE "9";
|
||||
LOCATE COMP "Din[4]" SITE "1";
|
||||
LOCATE COMP "Din[5]" SITE "99";
|
||||
LOCATE COMP "Din[6]" SITE "88";
|
||||
LOCATE COMP "Din[7]" SITE "87";
|
||||
LOCATE COMP "Dout[0]" SITE "30";
|
||||
LOCATE COMP "Dout[1]" SITE "27";
|
||||
LOCATE COMP "Dout[2]" SITE "25";
|
||||
LOCATE COMP "Dout[3]" SITE "28";
|
||||
LOCATE COMP "Dout[4]" SITE "24";
|
||||
LOCATE COMP "Dout[5]" SITE "21";
|
||||
LOCATE COMP "Dout[6]" SITE "31";
|
||||
LOCATE COMP "Dout[7]" SITE "32";
|
||||
LOCATE COMP "LED" SITE "35";
|
||||
LOCATE COMP "PHI1" SITE "85";
|
||||
LOCATE COMP "RA[0]" SITE "66";
|
||||
LOCATE COMP "RA[10]" SITE "64";
|
||||
LOCATE COMP "RA[11]" SITE "59";
|
||||
LOCATE COMP "RA[1]" SITE "68";
|
||||
LOCATE COMP "RA[2]" SITE "70";
|
||||
LOCATE COMP "RA[3]" SITE "74";
|
||||
LOCATE COMP "RA[4]" SITE "75";
|
||||
LOCATE COMP "RA[5]" SITE "71";
|
||||
LOCATE COMP "RA[6]" SITE "69";
|
||||
LOCATE COMP "RA[7]" SITE "67";
|
||||
LOCATE COMP "RA[8]" SITE "65";
|
||||
LOCATE COMP "RA[9]" SITE "63";
|
||||
LOCATE COMP "RD[0]" SITE "36";
|
||||
LOCATE COMP "RD[1]" SITE "37";
|
||||
LOCATE COMP "RD[2]" SITE "38";
|
||||
LOCATE COMP "RD[3]" SITE "39";
|
||||
LOCATE COMP "RD[4]" SITE "40";
|
||||
LOCATE COMP "RD[5]" SITE "41";
|
||||
LOCATE COMP "RD[6]" SITE "42";
|
||||
LOCATE COMP "RD[7]" SITE "43";
|
||||
LOCATE COMP "Vout[0]" SITE "18";
|
||||
LOCATE COMP "Vout[1]" SITE "15";
|
||||
LOCATE COMP "Vout[2]" SITE "17";
|
||||
LOCATE COMP "Vout[3]" SITE "13";
|
||||
LOCATE COMP "Vout[4]" SITE "19";
|
||||
LOCATE COMP "Vout[5]" SITE "16";
|
||||
LOCATE COMP "Vout[6]" SITE "14";
|
||||
LOCATE COMP "Vout[7]" SITE "12";
|
||||
LOCATE COMP "nC07X" SITE "34";
|
||||
LOCATE COMP "nCAS" SITE "52";
|
||||
LOCATE COMP "nCS" SITE "57";
|
||||
LOCATE COMP "nDOE" SITE "20";
|
||||
LOCATE COMP "nEN80" SITE "82";
|
||||
LOCATE COMP "nRAS" SITE "54";
|
||||
LOCATE COMP "nRWE" SITE "51";
|
||||
LOCATE COMP "nVOE" SITE "10";
|
||||
LOCATE COMP "nWE" SITE "29";
|
||||
LOCATE COMP "nWE80" SITE "83";
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Thu Sep 21 05:35:04 2023
|
||||
|
||||
|
|
@ -0,0 +1,127 @@
|
|||
SCHEMATIC START ;
|
||||
# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Thu Sep 21 05:34:47 2023
|
||||
|
||||
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
|
||||
LOCATE COMP "RD[0]" SITE "36" ;
|
||||
LOCATE COMP "LED" SITE "35" ;
|
||||
LOCATE COMP "C14M" SITE "62" ;
|
||||
LOCATE COMP "DQMH" SITE "49" ;
|
||||
LOCATE COMP "DQML" SITE "48" ;
|
||||
LOCATE COMP "RD[7]" SITE "43" ;
|
||||
LOCATE COMP "RD[6]" SITE "42" ;
|
||||
LOCATE COMP "RD[5]" SITE "41" ;
|
||||
LOCATE COMP "RD[4]" SITE "40" ;
|
||||
LOCATE COMP "RD[3]" SITE "39" ;
|
||||
LOCATE COMP "RD[2]" SITE "38" ;
|
||||
LOCATE COMP "RD[1]" SITE "37" ;
|
||||
LOCATE COMP "RA[11]" SITE "59" ;
|
||||
LOCATE COMP "RA[10]" SITE "64" ;
|
||||
LOCATE COMP "RA[9]" SITE "63" ;
|
||||
LOCATE COMP "RA[8]" SITE "65" ;
|
||||
LOCATE COMP "RA[7]" SITE "67" ;
|
||||
LOCATE COMP "RA[6]" SITE "69" ;
|
||||
LOCATE COMP "RA[5]" SITE "71" ;
|
||||
LOCATE COMP "RA[4]" SITE "75" ;
|
||||
LOCATE COMP "RA[3]" SITE "74" ;
|
||||
LOCATE COMP "RA[2]" SITE "70" ;
|
||||
LOCATE COMP "RA[1]" SITE "68" ;
|
||||
LOCATE COMP "RA[0]" SITE "66" ;
|
||||
LOCATE COMP "BA[1]" SITE "60" ;
|
||||
LOCATE COMP "BA[0]" SITE "58" ;
|
||||
LOCATE COMP "nRWE" SITE "51" ;
|
||||
LOCATE COMP "nCAS" SITE "52" ;
|
||||
LOCATE COMP "nRAS" SITE "54" ;
|
||||
LOCATE COMP "nCS" SITE "57" ;
|
||||
LOCATE COMP "CKE" SITE "53" ;
|
||||
LOCATE COMP "nVOE" SITE "10" ;
|
||||
LOCATE COMP "Vout[7]" SITE "12" ;
|
||||
LOCATE COMP "Vout[6]" SITE "14" ;
|
||||
LOCATE COMP "Vout[5]" SITE "16" ;
|
||||
LOCATE COMP "Vout[4]" SITE "19" ;
|
||||
LOCATE COMP "Vout[3]" SITE "13" ;
|
||||
LOCATE COMP "Vout[2]" SITE "17" ;
|
||||
LOCATE COMP "Vout[1]" SITE "15" ;
|
||||
LOCATE COMP "Vout[0]" SITE "18" ;
|
||||
LOCATE COMP "nDOE" SITE "20" ;
|
||||
LOCATE COMP "Dout[7]" SITE "32" ;
|
||||
LOCATE COMP "Dout[6]" SITE "31" ;
|
||||
LOCATE COMP "Dout[5]" SITE "21" ;
|
||||
LOCATE COMP "Dout[4]" SITE "24" ;
|
||||
LOCATE COMP "Dout[3]" SITE "28" ;
|
||||
LOCATE COMP "Dout[2]" SITE "25" ;
|
||||
LOCATE COMP "Dout[1]" SITE "27" ;
|
||||
LOCATE COMP "Dout[0]" SITE "30" ;
|
||||
LOCATE COMP "Din[7]" SITE "87" ;
|
||||
LOCATE COMP "Din[6]" SITE "88" ;
|
||||
LOCATE COMP "Din[5]" SITE "99" ;
|
||||
LOCATE COMP "Din[4]" SITE "1" ;
|
||||
LOCATE COMP "Din[3]" SITE "9" ;
|
||||
LOCATE COMP "Din[2]" SITE "98" ;
|
||||
LOCATE COMP "Din[1]" SITE "97" ;
|
||||
LOCATE COMP "Din[0]" SITE "96" ;
|
||||
LOCATE COMP "Ain[7]" SITE "8" ;
|
||||
LOCATE COMP "Ain[6]" SITE "86" ;
|
||||
LOCATE COMP "Ain[5]" SITE "84" ;
|
||||
LOCATE COMP "Ain[4]" SITE "78" ;
|
||||
LOCATE COMP "Ain[3]" SITE "4" ;
|
||||
LOCATE COMP "Ain[2]" SITE "7" ;
|
||||
LOCATE COMP "Ain[1]" SITE "2" ;
|
||||
LOCATE COMP "Ain[0]" SITE "3" ;
|
||||
LOCATE COMP "nC07X" SITE "34" ;
|
||||
LOCATE COMP "nEN80" SITE "82" ;
|
||||
LOCATE COMP "nWE80" SITE "83" ;
|
||||
LOCATE COMP "nWE" SITE "29" ;
|
||||
LOCATE COMP "PHI1" SITE "85" ;
|
||||
FREQUENCY PORT "C14M" 14.300000 MHz ;
|
||||
SCHEMATIC END ;
|
||||
BLOCK RESETPATHS ;
|
||||
BLOCK ASYNCPATHS ;
|
||||
OUTPUT PORT "LED" LOAD 100.000000 pF ;
|
||||
OUTPUT PORT "BA[1]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "BA[0]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "CKE" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "DQMH" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "DQML" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "Dout[0]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Dout[1]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Dout[2]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Dout[3]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Dout[4]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Dout[5]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Dout[6]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Dout[7]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "RA[0]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[1]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[2]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[3]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[4]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[5]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[6]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[7]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[8]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[9]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[10]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[11]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "Vout[0]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Vout[1]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Vout[2]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Vout[3]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Vout[4]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Vout[5]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Vout[6]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Vout[7]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "nCAS" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "nCS" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "nDOE" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "nRAS" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "nRWE" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "nVOE" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RD[0]" LOAD 9.000000 pF ;
|
||||
OUTPUT PORT "RD[1]" LOAD 9.000000 pF ;
|
||||
OUTPUT PORT "RD[2]" LOAD 9.000000 pF ;
|
||||
OUTPUT PORT "RD[3]" LOAD 9.000000 pF ;
|
||||
OUTPUT PORT "RD[4]" LOAD 9.000000 pF ;
|
||||
OUTPUT PORT "RD[5]" LOAD 9.000000 pF ;
|
||||
OUTPUT PORT "RD[6]" LOAD 9.000000 pF ;
|
||||
OUTPUT PORT "RD[7]" LOAD 9.000000 pF ;
|
||||
COMMERCIAL ;
|
||||
|
|
@ -0,0 +1,690 @@
|
|||
#Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021
|
||||
#install: C:\lscc\diamond\3.12\synpbase
|
||||
#OS: Windows 8 6.2
|
||||
#Hostname: ZANEMACWIN11
|
||||
|
||||
# Thu Sep 21 05:34:34 2023
|
||||
|
||||
#Implementation: impl1
|
||||
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: R-2021.03L-SP1
|
||||
Install: C:\lscc\diamond\3.12\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
###########################################################[
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: R-2021.03L-SP1
|
||||
Install: C:\lscc\diamond\3.12\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v" (library work)
|
||||
@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
|
||||
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
|
||||
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
|
||||
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
|
||||
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
|
||||
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E-LCMXO2.v" (library work)
|
||||
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\REFB.v" (library work)
|
||||
Verilog syntax check successful!
|
||||
|
||||
Compiler output is up to date. No re-compile necessary
|
||||
|
||||
Selecting top level module RAM2E
|
||||
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
|
||||
Running optimization stage 1 on VHI .......
|
||||
Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
|
||||
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
|
||||
Running optimization stage 1 on VLO .......
|
||||
Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
|
||||
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
|
||||
Running optimization stage 1 on EFB .......
|
||||
Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
|
||||
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
|
||||
Running optimization stage 1 on REFB .......
|
||||
Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
|
||||
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E-LCMXO2.v":1:7:1:11|Synthesizing module RAM2E in library work.
|
||||
Running optimization stage 1 on RAM2E .......
|
||||
Finished optimization stage 1 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB)
|
||||
Running optimization stage 2 on RAM2E .......
|
||||
Finished optimization stage 2 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
|
||||
Running optimization stage 2 on REFB .......
|
||||
Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
|
||||
Running optimization stage 2 on EFB .......
|
||||
Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
|
||||
Running optimization stage 2 on VLO .......
|
||||
Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
|
||||
Running optimization stage 2 on VHI .......
|
||||
Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
|
||||
|
||||
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 97MB peak: 97MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:34:34 2023
|
||||
|
||||
###########################################################]
|
||||
###########################################################[
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: R-2021.03L-SP1
|
||||
Install: C:\lscc\diamond\3.12\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:34:34 2023
|
||||
|
||||
###########################################################]
|
||||
|
||||
For a summary of runtime and memory usage for all design units, please see file:
|
||||
==========================================================
|
||||
@L: A:\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_comp.rt.csv
|
||||
|
||||
@END
|
||||
|
||||
At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:34:34 2023
|
||||
|
||||
###########################################################]
|
||||
###########################################################[
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: R-2021.03L-SP1
|
||||
Install: C:\lscc\diamond\3.12\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
File \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_comp.srs changed - recompiling
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:34:36 2023
|
||||
|
||||
###########################################################]
|
||||
# Thu Sep 21 05:34:36 2023
|
||||
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: R-2021.03L-SP1
|
||||
Install: C:\lscc\diamond\3.12\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @
|
||||
|
||||
|
||||
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
|
||||
|
||||
|
||||
Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 141MB)
|
||||
|
||||
Reading constraint file: \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
|
||||
@L: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1_scck.rpt
|
||||
See clock summary report "\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1_scck.rpt"
|
||||
@N: MF916 |Option synthesis_strategy=base is enabled.
|
||||
@N: MF248 |Running in 64-bit mode.
|
||||
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
|
||||
|
||||
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 141MB)
|
||||
|
||||
|
||||
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 141MB)
|
||||
|
||||
|
||||
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 149MB)
|
||||
|
||||
|
||||
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 151MB)
|
||||
|
||||
@N: FX493 |Applying initial value "0" on instance PHI1reg.
|
||||
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
|
||||
@N: FX493 |Applying initial value "0" on instance DOEEN.
|
||||
@N: FX493 |Applying initial value "0" on instance RWSel.
|
||||
@N: FX493 |Applying initial value "00000000" on instance RWBank[7:0].
|
||||
@N: FX493 |Applying initial value "1" on instance DQMH.
|
||||
@N: FX493 |Applying initial value "0" on instance Ready.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdBitbangMXO2.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdExecMXO2.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdLEDGet.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdLEDSet.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdRWMaskSet.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdSetRWBankFFLED.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdSetRWBankFFMXO2.
|
||||
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":375:4:375:9|Initial value on register nRWE is non-zero which can prevent the register from being packed into a block RAM or DSP.
|
||||
@N: FX493 |Applying initial value "1" on instance nRWE.
|
||||
@N: FX493 |Applying initial value "0" on instance LEDEN.
|
||||
@N: FX493 |Applying initial value "00000000" on instance RWMask[7:0].
|
||||
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":102:4:102:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
|
||||
@N: FX493 |Applying initial value "0000" on instance S[3:0].
|
||||
@N: FX493 |Applying initial value "1" on instance DQML.
|
||||
@N: FX493 |Applying initial value "0" on instance CKE.
|
||||
@N: FX493 |Applying initial value "1" on instance nCS.
|
||||
@N: FX493 |Applying initial value "1" on instance nRAS.
|
||||
@N: FX493 |Applying initial value "1" on instance nCAS.
|
||||
|
||||
Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
|
||||
|
||||
|
||||
Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
|
||||
|
||||
|
||||
Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
|
||||
|
||||
|
||||
Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
|
||||
|
||||
@N: FX1184 |Applying syn_allowed_resources blockrams=7 on top level netlist RAM2E
|
||||
|
||||
Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 181MB peak: 182MB)
|
||||
|
||||
|
||||
|
||||
Clock Summary
|
||||
******************
|
||||
|
||||
Start Requested Requested Clock Clock Clock
|
||||
Level Clock Frequency Period Type Group Load
|
||||
----------------------------------------------------------------------------------------
|
||||
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 111
|
||||
|
||||
0 - System 100.0 MHz 10.000 system system_clkgroup 0
|
||||
========================================================================================
|
||||
|
||||
|
||||
|
||||
Clock Load Summary
|
||||
***********************
|
||||
|
||||
Clock Source Clock Pin Non-clock Pin Non-clock Pin
|
||||
Clock Load Pin Seq Example Seq Example Comb Example
|
||||
----------------------------------------------------------------------------------------
|
||||
C14M 111 C14M(port) wb_rst.C - un1_C14M.I[0](inv)
|
||||
|
||||
System 0 - - - -
|
||||
========================================================================================
|
||||
|
||||
ICG Latch Removal Summary:
|
||||
Number of ICG latches removed: 0
|
||||
Number of ICG latches not removed: 0
|
||||
For details review file gcc_ICG_report.rpt
|
||||
|
||||
|
||||
@S |Clock Optimization Summary
|
||||
|
||||
|
||||
|
||||
#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
|
||||
|
||||
1 non-gated/non-generated clock tree(s) driving 111 clock pin(s) of sequential element(s)
|
||||
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
|
||||
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
|
||||
|
||||
=========================== Non-Gated/Non-Generated Clocks ============================
|
||||
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
|
||||
---------------------------------------------------------------------------------------
|
||||
@KP:ckid0_0 C14M port 111 nCAS
|
||||
=======================================================================================
|
||||
|
||||
|
||||
##### END OF CLOCK OPTIMIZATION REPORT ######
|
||||
|
||||
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
|
||||
Finished Pre Mapping Phase.
|
||||
|
||||
Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
|
||||
|
||||
|
||||
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
|
||||
|
||||
|
||||
Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
|
||||
|
||||
Pre-mapping successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 99MB peak: 185MB)
|
||||
|
||||
Process took 0h:00m:02s realtime, 0h:00m:01s cputime
|
||||
# Thu Sep 21 05:34:38 2023
|
||||
|
||||
###########################################################]
|
||||
# Thu Sep 21 05:34:38 2023
|
||||
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: R-2021.03L-SP1
|
||||
Install: C:\lscc\diamond\3.12\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @
|
||||
|
||||
|
||||
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
|
||||
|
||||
@N: MF916 |Option synthesis_strategy=base is enabled.
|
||||
@N: MF248 |Running in 64-bit mode.
|
||||
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
|
||||
|
||||
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
|
||||
|
||||
|
||||
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
|
||||
|
||||
|
||||
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
|
||||
|
||||
|
||||
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB)
|
||||
|
||||
|
||||
|
||||
Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 179MB peak: 179MB)
|
||||
|
||||
@W: FA239 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":376:8:376:9|ROM DOEEN_2 (in view: work.RAM2E(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
|
||||
@N: MO106 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":376:8:376:9|Found ROM DOEEN_2 (in view: work.RAM2E(verilog)) with 16 words by 1 bit.
|
||||
|
||||
Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
|
||||
|
||||
@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":102:4:102:9|Found counter in view:work.RAM2E(verilog) instance FS[15:0]
|
||||
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
|
||||
|
||||
Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB)
|
||||
|
||||
|
||||
Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
|
||||
|
||||
|
||||
Available hyper_sources - for debug and ip models
|
||||
None Found
|
||||
|
||||
|
||||
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
|
||||
|
||||
|
||||
Starting Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
|
||||
|
||||
|
||||
Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
|
||||
|
||||
|
||||
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
|
||||
|
||||
|
||||
Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
|
||||
|
||||
|
||||
Finished technology mapping (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 205MB peak: 205MB)
|
||||
|
||||
Pass CPU time Worst Slack Luts / Registers
|
||||
------------------------------------------------------------
|
||||
1 0h:00m:02s 29.35ns 222 / 111
|
||||
|
||||
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 205MB peak: 205MB)
|
||||
|
||||
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
|
||||
|
||||
Finished restoring hierarchy (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 206MB peak: 206MB)
|
||||
|
||||
|
||||
Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 168MB peak: 206MB)
|
||||
|
||||
Writing Analyst data base \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_m.srm
|
||||
|
||||
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:02s; Memory used current: 206MB peak: 206MB)
|
||||
|
||||
Writing EDIF Netlist and constraint files
|
||||
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1.edi
|
||||
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
|
||||
|
||||
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:03s; Memory used current: 211MB peak: 211MB)
|
||||
|
||||
|
||||
Finished Writing Netlists (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:03s; Memory used current: 211MB peak: 211MB)
|
||||
|
||||
|
||||
Start final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 209MB peak: 211MB)
|
||||
|
||||
@W: MT246 :"\\mac\icloud\repos\ram2e\cpld\lcmxo2-1200hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
|
||||
@N: MT615 |Found clock C14M with period 69.84ns
|
||||
|
||||
|
||||
##### START OF TIMING REPORT #####[
|
||||
# Timing report written on Thu Sep 21 05:34:44 2023
|
||||
#
|
||||
|
||||
|
||||
Top view: RAM2E
|
||||
Requested Frequency: 14.3 MHz
|
||||
Wire load mode: top
|
||||
Paths requested: 5
|
||||
Constraint File(s): \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
|
||||
|
||||
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
|
||||
|
||||
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
|
||||
|
||||
|
||||
|
||||
Performance Summary
|
||||
*******************
|
||||
|
||||
|
||||
Worst slack in design: 31.782
|
||||
|
||||
Requested Estimated Requested Estimated Clock Clock
|
||||
Starting Clock Frequency Frequency Period Period Slack Type Group
|
||||
-------------------------------------------------------------------------------------------------------------------
|
||||
C14M 14.3 MHz 131.4 MHz 69.841 7.610 31.782 declared default_clkgroup
|
||||
System 100.0 MHz NA 10.000 NA 67.088 system system_clkgroup
|
||||
===================================================================================================================
|
||||
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Clock Relationships
|
||||
*******************
|
||||
|
||||
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
System C14M | 69.841 67.088 | No paths - | No paths - | No paths -
|
||||
C14M System | 69.841 68.797 | No paths - | No paths - | No paths -
|
||||
C14M C14M | 69.841 62.231 | No paths - | 34.920 31.782 | No paths -
|
||||
==========================================================================================================
|
||||
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
|
||||
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
|
||||
|
||||
|
||||
|
||||
Interface Information
|
||||
*********************
|
||||
|
||||
No IO constraint found
|
||||
|
||||
|
||||
|
||||
====================================
|
||||
Detailed Report for Clock: C14M
|
||||
====================================
|
||||
|
||||
|
||||
|
||||
Starting Points with Worst Slack
|
||||
********************************
|
||||
|
||||
Starting Arrival
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------
|
||||
S[2] C14M FD1S3AX Q S[2] 1.350 31.782
|
||||
S[3] C14M FD1S3AX Q S[3] 1.350 31.782
|
||||
S[0] C14M FD1S3AX Q S[0] 1.312 31.820
|
||||
S[1] C14M FD1S3AX Q S[1] 1.280 31.852
|
||||
FS[9] C14M FD1S3AX Q FS[9] 1.284 62.425
|
||||
FS[11] C14M FD1S3AX Q FS[11] 1.276 62.433
|
||||
FS[8] C14M FD1S3AX Q FS[8] 1.260 62.449
|
||||
FS[12] C14M FD1S3AX Q FS[12] 1.288 62.525
|
||||
FS[10] C14M FD1S3AX Q FS[10] 1.280 62.533
|
||||
RWSel C14M FD1P3AX Q RWSel 1.276 63.482
|
||||
============================================================================
|
||||
|
||||
|
||||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------------
|
||||
Dout_0io[0] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[1] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[2] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[3] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[4] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[5] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[6] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[7] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Vout_0io[0] C14M OFS1P3DX SP Vout3 34.449 31.826
|
||||
Vout_0io[1] C14M OFS1P3DX SP Vout3 34.449 31.826
|
||||
==================================================================================
|
||||
|
||||
|
||||
|
||||
Worst Path Information
|
||||
***********************
|
||||
|
||||
|
||||
Path information for path number 1:
|
||||
Requested Period: 34.920
|
||||
- Setup time: 0.472
|
||||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
= Required time: 34.449
|
||||
|
||||
- Propagation time: 2.667
|
||||
- Clock delay at starting point: 0.000 (ideal)
|
||||
= Slack (critical) : 31.782
|
||||
|
||||
Number of logic level(s): 1
|
||||
Starting point: S[2] / Q
|
||||
Ending point: Dout_0io[0] / SP
|
||||
The start point is clocked by C14M [rising] (rise=0.000 fall=34.920 period=69.841) on pin CK
|
||||
The end point is clocked by C14M [falling] (rise=0.000 fall=34.920 period=69.841) on pin SCLK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
----------------------------------------------------------------------------------
|
||||
S[2] FD1S3AX Q Out 1.350 1.350 r -
|
||||
S[2] Net - - - - 48
|
||||
S_RNII9DO1_2[1] ORCALUT4 B In 0.000 1.350 r -
|
||||
S_RNII9DO1_2[1] ORCALUT4 Z Out 1.317 2.667 r -
|
||||
N_576_i Net - - - - 18
|
||||
Dout_0io[0] OFS1P3DX SP In 0.000 2.667 r -
|
||||
==================================================================================
|
||||
|
||||
|
||||
|
||||
|
||||
====================================
|
||||
Detailed Report for Clock: System
|
||||
====================================
|
||||
|
||||
|
||||
|
||||
Starting Points with Worst Slack
|
||||
********************************
|
||||
|
||||
Starting Arrival
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
-----------------------------------------------------------------------------------------
|
||||
ufmefb.EFBInst_0 System EFB WBACKO wb_ack 0.000 67.088
|
||||
ufmefb.EFBInst_0 System EFB WBDATO0 wb_dato[0] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO2 wb_dato[2] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO3 wb_dato[3] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO4 wb_dato[4] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO5 wb_dato[5] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO6 wb_dato[6] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO7 wb_dato[7] 0.000 69.313
|
||||
=========================================================================================
|
||||
|
||||
|
||||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------------------------------
|
||||
RWMask[0] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[1] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[2] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[3] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[4] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[5] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[6] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[7] System FD1P3AX SP N_88 69.369 67.088
|
||||
LEDEN System FD1P3AX SP un1_LEDEN_0_sqmuxa_1_i_0[0] 69.369 67.736
|
||||
wb_cyc_stb System FD1P3AX SP N_104 69.369 67.736
|
||||
====================================================================================================
|
||||
|
||||
|
||||
|
||||
Worst Path Information
|
||||
***********************
|
||||
|
||||
|
||||
Path information for path number 1:
|
||||
Requested Period: 69.841
|
||||
- Setup time: 0.472
|
||||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
= Required time: 69.369
|
||||
|
||||
- Propagation time: 2.282
|
||||
- Clock delay at starting point: 0.000 (ideal)
|
||||
- Estimated clock delay at start point: -0.000
|
||||
= Slack (non-critical) : 67.088
|
||||
|
||||
Number of logic level(s): 2
|
||||
Starting point: ufmefb.EFBInst_0 / WBACKO
|
||||
Ending point: RWMask[0] / SP
|
||||
The start point is clocked by System [rising]
|
||||
The end point is clocked by C14M [rising] (rise=0.000 fall=34.920 period=69.841) on pin CK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
------------------------------------------------------------------------------------------------------
|
||||
ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 r -
|
||||
wb_ack Net - - - - 5
|
||||
un1_RWMask_0_sqmuxa_1_i_0_RNO[0] ORCALUT4 A In 0.000 0.000 r -
|
||||
un1_RWMask_0_sqmuxa_1_i_0_RNO[0] ORCALUT4 Z Out 1.017 1.017 r -
|
||||
un1_RWMask_0_sqmuxa_1_i_a2_0_1[0] Net - - - - 1
|
||||
un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 D In 0.000 1.017 r -
|
||||
un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 Z Out 1.265 2.282 r -
|
||||
N_88 Net - - - - 8
|
||||
RWMask[0] FD1P3AX SP In 0.000 2.282 r -
|
||||
======================================================================================================
|
||||
|
||||
|
||||
|
||||
##### END OF TIMING REPORT #####]
|
||||
|
||||
Timing exceptions that could not be applied
|
||||
|
||||
Finished final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 210MB peak: 211MB)
|
||||
|
||||
|
||||
Finished timing report (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 210MB peak: 211MB)
|
||||
|
||||
---------------------------------------
|
||||
Resource Usage Report
|
||||
Part: lcmxo2_1200hc-4
|
||||
|
||||
Register bits: 111 of 1280 (9%)
|
||||
PIC Latch: 0
|
||||
I/O cells: 70
|
||||
|
||||
|
||||
Details:
|
||||
BB: 8
|
||||
CCU2D: 9
|
||||
EFB: 1
|
||||
FD1P3AX: 48
|
||||
FD1P3IX: 1
|
||||
FD1S3AX: 22
|
||||
FD1S3IX: 4
|
||||
GSR: 1
|
||||
IB: 22
|
||||
IFS1P3DX: 1
|
||||
INV: 1
|
||||
OB: 40
|
||||
OFS1P3BX: 6
|
||||
OFS1P3DX: 27
|
||||
OFS1P3IX: 2
|
||||
ORCALUT4: 221
|
||||
PUR: 1
|
||||
VHI: 2
|
||||
VLO: 2
|
||||
Mapper successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 78MB peak: 211MB)
|
||||
|
||||
Process took 0h:00m:06s realtime, 0h:00m:04s cputime
|
||||
# Thu Sep 21 05:34:44 2023
|
||||
|
||||
###########################################################]
|
||||
|
|
@ -0,0 +1,215 @@
|
|||
|
||||
Loading design for application trce from file ram2e_lcmxo2_1200hc_impl1_map.ncd.
|
||||
Design name: RAM2E
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-1200HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.44.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
Setup and Hold Report
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
|
||||
Thu Sep 21 05:34:48 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
Report Information
|
||||
------------------
|
||||
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2E_LCMXO2_1200HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1_map.ncd RAM2E_LCMXO2_1200HC_impl1.prf
|
||||
Design file: ram2e_lcmxo2_1200hc_impl1_map.ncd
|
||||
Preference file: ram2e_lcmxo2_1200hc_impl1.prf
|
||||
Device,speed: LCMXO2-1200HC,4
|
||||
Report level: verbose report, limited to 1 item per preference
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
BLOCK ASYNCPATHS
|
||||
BLOCK RESETPATHS
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
================================================================================
|
||||
Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
|
||||
1491 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 58.471ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q FS[11] (from C14M_c +)
|
||||
Destination: FF Data in nRWE_0io (to C14M_c +)
|
||||
|
||||
Delay: 11.306ns (30.3% logic, 69.7% route), 7 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
11.306ns physical path delay SLICE_3 to nRWE_MGIOL meets
|
||||
69.930ns delay constraint less
|
||||
0.153ns DO_SET requirement (totaling 69.777ns) by 58.471ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path SLICE_3 to nRWE_MGIOL:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.452 SLICE_3.CLK to SLICE_3.Q0 SLICE_3 (from C14M_c)
|
||||
ROUTE 19 e 1.234 SLICE_3.Q0 to SLICE_64.A1 FS[11]
|
||||
CTOF_DEL --- 0.495 SLICE_64.A1 to SLICE_64.F1 SLICE_64
|
||||
ROUTE 4 e 1.234 SLICE_64.F1 to SLICE_97.D0 N_577
|
||||
CTOF_DEL --- 0.495 SLICE_97.D0 to SLICE_97.F0 SLICE_97
|
||||
ROUTE 3 e 1.234 SLICE_97.F0 to SLICE_75.D1 N_489
|
||||
CTOF_DEL --- 0.495 SLICE_75.D1 to SLICE_75.F1 SLICE_75
|
||||
ROUTE 3 e 0.480 SLICE_75.F1 to SLICE_75.A0 N_628
|
||||
CTOF_DEL --- 0.495 SLICE_75.A0 to SLICE_75.F0 SLICE_75
|
||||
ROUTE 2 e 1.234 SLICE_75.F0 to SLICE_71.C1 N_640
|
||||
CTOF_DEL --- 0.495 SLICE_71.C1 to SLICE_71.F1 SLICE_71
|
||||
ROUTE 1 e 1.234 SLICE_71.F1 to SLICE_115.A0 un1_nCS61_1_i
|
||||
CTOF_DEL --- 0.495 SLICE_115.A0 to SLICE_115.F0 SLICE_115
|
||||
ROUTE 1 e 1.234 SLICE_115.F0 to *WE_MGIOL.OPOS nRWE_r_0 (to C14M_c)
|
||||
--------
|
||||
11.306 (30.3% logic, 69.7% route), 7 logic levels.
|
||||
|
||||
Report: 87.268MHz is the maximum frequency for this preference.
|
||||
|
||||
Report Summary
|
||||
--------------
|
||||
----------------------------------------------------------------------------
|
||||
Preference | Constraint| Actual|Levels
|
||||
----------------------------------------------------------------------------
|
||||
| | |
|
||||
FREQUENCY PORT "C14M" 14.300000 MHz ; | 14.300 MHz| 87.268 MHz| 7
|
||||
| | |
|
||||
----------------------------------------------------------------------------
|
||||
|
||||
|
||||
All preferences were met.
|
||||
|
||||
|
||||
Clock Domains Analysis
|
||||
------------------------
|
||||
|
||||
Found 1 clocks:
|
||||
|
||||
Clock Domain: C14M_c Source: C14M.PAD Loads: 84
|
||||
Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
|
||||
|
||||
|
||||
Timing summary (Setup):
|
||||
---------------
|
||||
|
||||
Timing errors: 0 Score: 0
|
||||
Cumulative negative slack: 0
|
||||
|
||||
Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
|
||||
Thu Sep 21 05:34:49 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
Report Information
|
||||
------------------
|
||||
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2E_LCMXO2_1200HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1_map.ncd RAM2E_LCMXO2_1200HC_impl1.prf
|
||||
Design file: ram2e_lcmxo2_1200hc_impl1_map.ncd
|
||||
Preference file: ram2e_lcmxo2_1200hc_impl1.prf
|
||||
Device,speed: LCMXO2-1200HC,M
|
||||
Report level: verbose report, limited to 1 item per preference
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
BLOCK ASYNCPATHS
|
||||
BLOCK RESETPATHS
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
================================================================================
|
||||
Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
|
||||
1491 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 0.447ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q FS[0] (from C14M_c +)
|
||||
Destination: FF Data in FS[0] (to C14M_c +)
|
||||
|
||||
Delay: 0.434ns (53.9% logic, 46.1% route), 2 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
0.434ns physical path delay SLICE_0 to SLICE_0 meets
|
||||
-0.013ns DIN_HLD and
|
||||
0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path SLICE_0 to SLICE_0:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.133 SLICE_0.CLK to SLICE_0.Q1 SLICE_0 (from C14M_c)
|
||||
ROUTE 5 e 0.199 SLICE_0.Q1 to SLICE_0.A1 FS[0]
|
||||
CTOF_DEL --- 0.101 SLICE_0.A1 to SLICE_0.F1 SLICE_0
|
||||
ROUTE 1 e 0.001 SLICE_0.F1 to SLICE_0.DI1 FS_s[0] (to C14M_c)
|
||||
--------
|
||||
0.434 (53.9% logic, 46.1% route), 2 logic levels.
|
||||
|
||||
Report Summary
|
||||
--------------
|
||||
----------------------------------------------------------------------------
|
||||
Preference(MIN Delays) | Constraint| Actual|Levels
|
||||
----------------------------------------------------------------------------
|
||||
| | |
|
||||
FREQUENCY PORT "C14M" 14.300000 MHz ; | -| -| 2
|
||||
| | |
|
||||
----------------------------------------------------------------------------
|
||||
|
||||
|
||||
All preferences were met.
|
||||
|
||||
|
||||
Clock Domains Analysis
|
||||
------------------------
|
||||
|
||||
Found 1 clocks:
|
||||
|
||||
Clock Domain: C14M_c Source: C14M.PAD Loads: 84
|
||||
Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
|
||||
|
||||
|
||||
Timing summary (Hold):
|
||||
---------------
|
||||
|
||||
Timing errors: 0 Score: 0
|
||||
Cumulative negative slack: 0
|
||||
|
||||
Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage)
|
||||
|
||||
|
||||
|
||||
Timing summary (Setup and Hold):
|
||||
---------------
|
||||
|
||||
Timing errors: 0 (setup), 0 (hold)
|
||||
Score: 0 (setup), 0 (hold)
|
||||
Cumulative negative slack: 0 (0+0)
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,142 @@
|
|||
<HTML>
|
||||
<HEAD><TITLE>Bitgen Report</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Bgn"></A>BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Thu Sep 21 05:35:17 2023
|
||||
|
||||
|
||||
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC -w -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1.ncd RAM2E_LCMXO2_1200HC_impl1.prf
|
||||
|
||||
Loading design for application Bitgen from file RAM2E_LCMXO2_1200HC_impl1.ncd.
|
||||
Design name: RAM2E
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-1200HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application Bitgen from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.44.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
|
||||
Running DRC.
|
||||
DRC detected 0 errors and 0 warnings.
|
||||
Reading Preference File from RAM2E_LCMXO2_1200HC_impl1.prf.
|
||||
|
||||
<A name="bgn_ps"></A>
|
||||
<B><U><big>Preference Summary:</big></U></B>
|
||||
|
||||
+---------------------------------+---------------------------------+
|
||||
| Preference | Current Setting |
|
||||
+---------------------------------+---------------------------------+
|
||||
| RamCfg | Reset** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MCCLK_FREQ | 2.08** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| CONFIG_SECURE | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| INBUF | ON** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| JTAG_PORT | ENABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SDM_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SLAVE_SPI_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MASTER_SPI_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| I2C_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MUX_CONFIGURATION_PORTS | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| CONFIGURATION | CFG** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| COMPRESS_CONFIG | ON** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MY_ASSP | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| ONE_TIME_PROGRAM | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| ENABLE_TRANSFR | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SHAREDEBRINIT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| BACKGROUND_RECONFIG | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
* Default setting.
|
||||
** The specified setting matches the default setting.
|
||||
|
||||
|
||||
Creating bit map...
|
||||
|
||||
Bitstream Status: Final Version 1.95.
|
||||
|
||||
Saving bit stream in "RAM2E_LCMXO2_1200HC_impl1.bit".
|
||||
Total CPU Time: 4 secs
|
||||
Total REAL Time: 4 secs
|
||||
Peak Memory Usage: 275 MB
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
|
|
@ -0,0 +1,152 @@
|
|||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: R-2021.03L-SP1
|
||||
Install: C:\lscc\diamond\3.12\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
|
||||
# Written on Thu Sep 21 05:34:38 2023
|
||||
|
||||
##### DESIGN INFO #######################################################
|
||||
|
||||
Top View: "RAM2E"
|
||||
Constraint File(s): "\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc"
|
||||
|
||||
|
||||
|
||||
|
||||
##### SUMMARY ############################################################
|
||||
|
||||
Found 0 issues in 0 out of 1 constraints
|
||||
|
||||
|
||||
##### DETAILS ############################################################
|
||||
|
||||
|
||||
|
||||
Clock Relationships
|
||||
*******************
|
||||
|
||||
Starting Ending | rise to rise | fall to fall | rise to fall | fall to rise
|
||||
-----------------------------------------------------------------------------------------------------------------------------------
|
||||
System C14M | 69.841 | No paths | No paths | No paths
|
||||
C14M System | 69.841 | No paths | No paths | No paths
|
||||
C14M C14M | 69.841 | No paths | 34.920 | No paths
|
||||
===================================================================================================================================
|
||||
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
|
||||
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
|
||||
|
||||
|
||||
Unconstrained Start/End Points
|
||||
******************************
|
||||
|
||||
p:Ain[0]
|
||||
p:Ain[1]
|
||||
p:Ain[2]
|
||||
p:Ain[3]
|
||||
p:Ain[4]
|
||||
p:Ain[5]
|
||||
p:Ain[6]
|
||||
p:Ain[7]
|
||||
p:BA[0]
|
||||
p:BA[1]
|
||||
p:CKE
|
||||
p:DQMH
|
||||
p:DQML
|
||||
p:Din[0]
|
||||
p:Din[1]
|
||||
p:Din[2]
|
||||
p:Din[3]
|
||||
p:Din[4]
|
||||
p:Din[5]
|
||||
p:Din[6]
|
||||
p:Din[7]
|
||||
p:Dout[0]
|
||||
p:Dout[1]
|
||||
p:Dout[2]
|
||||
p:Dout[3]
|
||||
p:Dout[4]
|
||||
p:Dout[5]
|
||||
p:Dout[6]
|
||||
p:Dout[7]
|
||||
p:LED
|
||||
p:PHI1
|
||||
p:RA[0]
|
||||
p:RA[1]
|
||||
p:RA[2]
|
||||
p:RA[3]
|
||||
p:RA[4]
|
||||
p:RA[5]
|
||||
p:RA[6]
|
||||
p:RA[7]
|
||||
p:RA[8]
|
||||
p:RA[9]
|
||||
p:RA[10]
|
||||
p:RA[11]
|
||||
p:RD[0] (bidir end point)
|
||||
p:RD[0] (bidir start point)
|
||||
p:RD[1] (bidir end point)
|
||||
p:RD[1] (bidir start point)
|
||||
p:RD[2] (bidir end point)
|
||||
p:RD[2] (bidir start point)
|
||||
p:RD[3] (bidir end point)
|
||||
p:RD[3] (bidir start point)
|
||||
p:RD[4] (bidir end point)
|
||||
p:RD[4] (bidir start point)
|
||||
p:RD[5] (bidir end point)
|
||||
p:RD[5] (bidir start point)
|
||||
p:RD[6] (bidir end point)
|
||||
p:RD[6] (bidir start point)
|
||||
p:RD[7] (bidir end point)
|
||||
p:RD[7] (bidir start point)
|
||||
p:Vout[0]
|
||||
p:Vout[1]
|
||||
p:Vout[2]
|
||||
p:Vout[3]
|
||||
p:Vout[4]
|
||||
p:Vout[5]
|
||||
p:Vout[6]
|
||||
p:Vout[7]
|
||||
p:nC07X
|
||||
p:nCAS
|
||||
p:nCS
|
||||
p:nDOE
|
||||
p:nEN80
|
||||
p:nRAS
|
||||
p:nRWE
|
||||
p:nVOE
|
||||
p:nWE
|
||||
p:nWE80
|
||||
|
||||
|
||||
Inapplicable constraints
|
||||
************************
|
||||
|
||||
(none)
|
||||
|
||||
|
||||
Applicable constraints with issues
|
||||
**********************************
|
||||
|
||||
(none)
|
||||
|
||||
|
||||
Constraints with matching wildcard expressions
|
||||
**********************************************
|
||||
|
||||
(none)
|
||||
|
||||
|
||||
Library Report
|
||||
**************
|
||||
|
||||
|
||||
# End of Constraint Checker Report
|
||||
|
|
@ -0,0 +1,185 @@
|
|||
<HTML>
|
||||
<HEAD><TITLE>I/O Timing Report</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Top"></A><B><U><big>I/O Timing Report</big></U></B>
|
||||
Loading design for application iotiming from file ram2e_lcmxo2_1200hc_impl1.ncd.
|
||||
Design name: RAM2E
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-1200HC
|
||||
Package: TQFP100
|
||||
Performance: 5
|
||||
Package Status: Final Version 1.44.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
Loading design for application iotiming from file ram2e_lcmxo2_1200hc_impl1.ncd.
|
||||
Design name: RAM2E
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-1200HC
|
||||
Package: TQFP100
|
||||
Performance: 6
|
||||
Package Status: Final Version 1.44.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
Loading design for application iotiming from file ram2e_lcmxo2_1200hc_impl1.ncd.
|
||||
Design name: RAM2E
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-1200HC
|
||||
Package: TQFP100
|
||||
Performance: M
|
||||
Package Status: Final Version 1.44.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
// Design: RAM2E
|
||||
// Package: TQFP100
|
||||
// ncd File: ram2e_lcmxo2_1200hc_impl1.ncd
|
||||
// Version: Diamond (64-bit) 3.12.1.454
|
||||
// Written on Thu Sep 21 05:35:11 2023
|
||||
// M: Minimum Performance Grade
|
||||
// iotiming RAM2E_LCMXO2_1200HC_impl1.ncd RAM2E_LCMXO2_1200HC_impl1.prf -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml
|
||||
|
||||
I/O Timing Report (All units are in ns)
|
||||
|
||||
Worst Case Results across Performance Grades (M, 6, 5, 4):
|
||||
|
||||
// Input Setup and Hold Times
|
||||
|
||||
Port Clock Edge Setup Performance_Grade Hold Performance_Grade
|
||||
----------------------------------------------------------------------
|
||||
Ain[0] C14M R -0.231 M 2.350 4
|
||||
Ain[1] C14M R 1.429 4 0.543 4
|
||||
Ain[2] C14M R 1.518 4 0.412 4
|
||||
Ain[3] C14M R -0.231 M 2.350 4
|
||||
Ain[4] C14M R 0.212 4 1.560 4
|
||||
Ain[5] C14M R 0.742 4 1.110 4
|
||||
Ain[6] C14M R 0.469 4 1.329 4
|
||||
Ain[7] C14M R 1.416 4 0.531 4
|
||||
Din[0] C14M R 8.327 4 1.958 4
|
||||
Din[1] C14M R 5.826 4 2.521 4
|
||||
Din[2] C14M R 6.539 4 2.135 4
|
||||
Din[3] C14M R 5.849 4 2.648 4
|
||||
Din[4] C14M R 7.061 4 2.095 4
|
||||
Din[5] C14M R 6.295 4 2.894 4
|
||||
Din[6] C14M R 4.991 4 2.892 4
|
||||
Din[7] C14M R 6.416 4 2.971 4
|
||||
PHI1 C14M R 1.151 4 4.842 4
|
||||
RD[0] C14M F -0.266 M 3.107 4
|
||||
RD[1] C14M F -0.248 M 3.183 4
|
||||
RD[2] C14M F -0.105 M 2.610 4
|
||||
RD[3] C14M F -0.243 M 3.107 4
|
||||
RD[4] C14M F 0.103 4 2.201 4
|
||||
RD[5] C14M F -0.092 M 2.192 4
|
||||
RD[6] C14M F -0.084 M 1.756 4
|
||||
RD[7] C14M F -0.092 M 2.661 4
|
||||
nC07X C14M R -0.316 M 2.625 4
|
||||
nEN80 C14M R 5.220 4 0.032 M
|
||||
nWE C14M R -0.093 M 2.033 4
|
||||
nWE80 C14M R 1.630 4 0.329 6
|
||||
|
||||
|
||||
// Clock to Output Delay
|
||||
|
||||
Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
|
||||
------------------------------------------------------------------------
|
||||
BA[0] C14M R 10.424 4 3.355 M
|
||||
BA[1] C14M R 10.424 4 3.355 M
|
||||
CKE C14M R 10.424 4 3.355 M
|
||||
DQMH C14M R 10.404 4 3.362 M
|
||||
DQML C14M R 10.404 4 3.362 M
|
||||
Dout[0] C14M F 10.750 4 3.634 M
|
||||
Dout[1] C14M F 10.750 4 3.634 M
|
||||
Dout[2] C14M F 10.739 4 3.628 M
|
||||
Dout[3] C14M F 10.750 4 3.634 M
|
||||
Dout[4] C14M F 10.739 4 3.628 M
|
||||
Dout[5] C14M F 10.739 4 3.628 M
|
||||
Dout[6] C14M F 10.750 4 3.634 M
|
||||
Dout[7] C14M F 10.750 4 3.634 M
|
||||
LED C14M R 21.299 4 8.576 M
|
||||
RA[0] C14M R 12.236 4 3.758 M
|
||||
RA[10] C14M R 10.490 4 3.360 M
|
||||
RA[11] C14M R 10.424 4 3.355 M
|
||||
RA[1] C14M R 10.490 4 3.360 M
|
||||
RA[2] C14M R 10.490 4 3.360 M
|
||||
RA[3] C14M R 11.808 4 3.656 M
|
||||
RA[4] C14M R 10.490 4 3.360 M
|
||||
RA[5] C14M R 10.490 4 3.360 M
|
||||
RA[6] C14M R 10.490 4 3.360 M
|
||||
RA[7] C14M R 10.490 4 3.360 M
|
||||
RA[8] C14M R 10.490 4 3.360 M
|
||||
RA[9] C14M R 10.490 4 3.360 M
|
||||
Vout[0] C14M F 11.348 4 3.872 M
|
||||
Vout[1] C14M F 11.434 4 3.871 M
|
||||
Vout[2] C14M F 11.348 4 3.872 M
|
||||
Vout[3] C14M F 11.434 4 3.871 M
|
||||
Vout[4] C14M F 11.348 4 3.872 M
|
||||
Vout[5] C14M F 11.348 4 3.872 M
|
||||
Vout[6] C14M F 11.434 4 3.871 M
|
||||
Vout[7] C14M F 11.434 4 3.871 M
|
||||
nCAS C14M R 10.424 4 3.355 M
|
||||
nCS C14M R 10.424 4 3.355 M
|
||||
nDOE C14M R 14.217 4 4.353 M
|
||||
nRAS C14M R 10.424 4 3.355 M
|
||||
nRWE C14M R 10.424 4 3.355 M
|
||||
WARNING: you must also run trce with hold speed: 4
|
||||
WARNING: you must also run trce with hold speed: 6
|
||||
WARNING: you must also run trce with setup speed: M
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
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|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
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|
||||
<BR>
|
||||
<BR>
|
||||
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|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,485 @@
|
|||
<HTML>
|
||||
<HEAD><TITLE>Project Summary</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Mrp"></A>
|
||||
Lattice Mapping Report File for Design Module 'RAM2E'
|
||||
|
||||
|
||||
|
||||
<A name="mrp_di"></A><B><U><big>Design Information</big></U></B>
|
||||
|
||||
Command line: map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 4 -oc Commercial
|
||||
RAM2E_LCMXO2_1200HC_impl1.ngd -o RAM2E_LCMXO2_1200HC_impl1_map.ncd -pr
|
||||
RAM2E_LCMXO2_1200HC_impl1.prf -mp RAM2E_LCMXO2_1200HC_impl1.mrp -lpf //Mac/
|
||||
iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_synpl
|
||||
ify.lpf -lpf //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf -c 0 -gui
|
||||
-msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml
|
||||
Target Vendor: LATTICE
|
||||
Target Device: LCMXO2-1200HCTQFP100
|
||||
Target Performance: 4
|
||||
Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454
|
||||
Mapped on: 09/21/23 05:34:46
|
||||
|
||||
|
||||
<A name="mrp_ds"></A><B><U><big>Design Summary</big></U></B>
|
||||
Number of registers: 111 out of 1520 (7%)
|
||||
PFU registers: 75 out of 1280 (6%)
|
||||
PIO registers: 36 out of 240 (15%)
|
||||
Number of SLICEs: 120 out of 640 (19%)
|
||||
SLICEs as Logic/ROM: 120 out of 640 (19%)
|
||||
SLICEs as RAM: 0 out of 480 (0%)
|
||||
SLICEs as Carry: 9 out of 640 (1%)
|
||||
Number of LUT4s: 239 out of 1280 (19%)
|
||||
Number used as logic LUTs: 221
|
||||
Number used as distributed RAM: 0
|
||||
Number used as ripple logic: 18
|
||||
Number used as shift registers: 0
|
||||
Number of PIO sites used: 70 + 4(JTAG) out of 80 (93%)
|
||||
Number of block RAMs: 0 out of 7 (0%)
|
||||
Number of GSRs: 0 out of 1 (0%)
|
||||
EFB used : Yes
|
||||
JTAG used : No
|
||||
Readback used : No
|
||||
Oscillator used : No
|
||||
Startup used : No
|
||||
POR : On
|
||||
Bandgap : On
|
||||
Number of Power Controller: 0 out of 1 (0%)
|
||||
Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
|
||||
Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%)
|
||||
Number of DCCA: 0 out of 8 (0%)
|
||||
Number of DCMA: 0 out of 2 (0%)
|
||||
Number of PLLs: 0 out of 1 (0%)
|
||||
Number of DQSDLLs: 0 out of 2 (0%)
|
||||
Number of CLKDIVC: 0 out of 4 (0%)
|
||||
Number of ECLKSYNCA: 0 out of 4 (0%)
|
||||
Number of ECLKBRIDGECS: 0 out of 2 (0%)
|
||||
Notes:-
|
||||
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
|
||||
distributed RAMs) + 2*(Number of ripple logic)
|
||||
2. Number of logic LUT4s does not include count of distributed RAM and
|
||||
ripple logic.
|
||||
Number of clocks: 1
|
||||
Net C14M_c: 84 loads, 68 rising, 16 falling (Driver: PIO C14M )
|
||||
Number of Clock Enables: 11
|
||||
|
||||
Net wb_adr_0_sqmuxa_i: 1 loads, 1 LSLICEs
|
||||
Net N_576_i: 17 loads, 9 LSLICEs
|
||||
Net LEDEN13: 4 loads, 4 LSLICEs
|
||||
Net nCS61: 1 loads, 1 LSLICEs
|
||||
Net Vout3: 8 loads, 0 LSLICEs
|
||||
Net S_RNII9DO1_1[1]: 7 loads, 1 LSLICEs
|
||||
Net un1_wb_cyc_stb_0_sqmuxa_1_i[0]: 1 loads, 1 LSLICEs
|
||||
Net un1_wb_adr_0_sqmuxa_2_i[0]: 8 loads, 8 LSLICEs
|
||||
Net N_104: 1 loads, 1 LSLICEs
|
||||
Net N_88: 4 loads, 4 LSLICEs
|
||||
Net un1_LEDEN_0_sqmuxa_1_i_0[0]: 1 loads, 1 LSLICEs
|
||||
Number of LSRs: 5
|
||||
Net un1_CS_0_sqmuxa_i: 2 loads, 2 LSLICEs
|
||||
Net S[2]: 1 loads, 1 LSLICEs
|
||||
Net N_566_i: 2 loads, 0 LSLICEs
|
||||
Net wb_rst: 1 loads, 0 LSLICEs
|
||||
Net S_RNII9DO1[1]: 1 loads, 1 LSLICEs
|
||||
Number of nets driven by tri-state buffers: 0
|
||||
Top 10 highest fanout non-clock nets:
|
||||
Net S[2]: 48 loads
|
||||
Net S[3]: 48 loads
|
||||
Net S[0]: 30 loads
|
||||
Net FS[12]: 22 loads
|
||||
Net FS[9]: 21 loads
|
||||
Net S[1]: 21 loads
|
||||
Net FS[10]: 20 loads
|
||||
Net FS[11]: 19 loads
|
||||
Net RWSel: 19 loads
|
||||
Net FS[13]: 17 loads
|
||||
|
||||
|
||||
|
||||
|
||||
Number of warnings: 1
|
||||
Number of errors: 0
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<A name="mrp_dwe"></A><B><U><big>Design Errors/Warnings</big></U></B>
|
||||
|
||||
WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
||||
temporarily disable certain features of the device including Power
|
||||
Controller, GSR, Hardened User SPI Port, Hardened Primary User I2C Port.
|
||||
Functionality is restored after the Flash Memory (UFM/Configuration)
|
||||
Interface is disabled using Disable Configuration Interface command 0x26
|
||||
followed by Bypass command 0xFF.
|
||||
|
||||
|
||||
|
||||
<A name="mrp_ioa"></A><B><U><big>IO (PIO) Attributes</big></U></B>
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| IO Name | Direction | Levelmode | IO |
|
||||
| | | IO_TYPE | Register |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[0] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
| LED | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| C14M | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| DQMH | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| DQML | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[7] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[6] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[5] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[4] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[3] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[2] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[1] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[11] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[10] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[9] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[8] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[7] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[6] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[5] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[4] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[3] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[2] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[1] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[0] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| BA[1] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| BA[0] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRWE | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nCAS | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRAS | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
| nCS | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| CKE | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nVOE | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Vout[7] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Vout[6] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Vout[5] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Vout[4] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Vout[3] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Vout[2] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Vout[1] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Vout[0] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nDOE | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[7] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[6] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[5] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[4] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[3] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[2] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[1] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[0] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[7] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[6] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[5] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[4] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[3] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[2] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[1] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[0] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
| Ain[7] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Ain[6] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Ain[5] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Ain[4] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Ain[3] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Ain[2] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Ain[1] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Ain[0] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nC07X | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nEN80 | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nWE80 | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nWE | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| PHI1 | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
|
||||
|
||||
<A name="mrp_rm"></A><B><U><big>Removed logic</big></U></B>
|
||||
|
||||
Block GSR_INST undriven or does not drive anything - clipped.
|
||||
Signal Dout_0_.CN was merged into signal C14M_c
|
||||
Signal GND undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/VCC undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/GND undriven or does not drive anything - clipped.
|
||||
Signal FS_s_0_S1[15] undriven or does not drive anything - clipped.
|
||||
Signal FS_s_0_COUT[15] undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/CFGWAKE undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wbc_ufm_irq undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/TCOC undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/TCINT undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIIRQO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPICSNEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMOSIEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMOSIO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMISOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMISOO undriven or does not drive anything - clipped.
|
||||
|
||||
Signal ufmefb/SPISCKEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPISCKO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SDAOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SCLOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SDAOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SCLOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO4 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLWEO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLL1STBO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLL0STBO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLRSTO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLCLKO undriven or does not drive anything - clipped.
|
||||
Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped.
|
||||
Signal N_1 undriven or does not drive anything - clipped.
|
||||
Block Vout_0_.CN was optimized away.
|
||||
Block GND was optimized away.
|
||||
Block ufmefb/VCC was optimized away.
|
||||
Block ufmefb/GND was optimized away.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<A name="mrp_efb"></A><B><U><big>Embedded Functional Block Connection Summary</big></U></B>
|
||||
|
||||
Desired WISHBONE clock frequency: 14.4 MHz
|
||||
Clock source: C14M_c
|
||||
Reset source: wb_rst
|
||||
Functions mode:
|
||||
I2C #1 (Primary) Function: DISABLED
|
||||
I2C #2 (Secondary) Function: DISABLED
|
||||
SPI Function: DISABLED
|
||||
Timer/Counter Function: DISABLED
|
||||
Timer/Counter Mode: WB
|
||||
UFM Connection: ENABLED
|
||||
PLL0 Connection: DISABLED
|
||||
PLL1 Connection: DISABLED
|
||||
I2C Function Summary:
|
||||
--------------------
|
||||
|
||||
None
|
||||
SPI Function Summary:
|
||||
--------------------
|
||||
None
|
||||
Timer/Counter Function Summary:
|
||||
------------------------------
|
||||
None
|
||||
UFM Function Summary:
|
||||
--------------------
|
||||
UFM Utilization: General Purpose Flash Memory
|
||||
Initialized UFM Pages: 321 Pages (321*128 Bits)
|
||||
Available General
|
||||
Purpose Flash Memory: 511 Pages (511*128 Bits)
|
||||
|
||||
EBR Blocks with Unique
|
||||
Initialization Data: 0
|
||||
|
||||
WID EBR Instance
|
||||
--- ------------
|
||||
|
||||
|
||||
|
||||
|
||||
<A name="mrp_asic"></A><B><U><big>ASIC Components</big></U></B>
|
||||
---------------
|
||||
|
||||
Instance Name: ufmefb/EFBInst_0
|
||||
Type: EFB
|
||||
|
||||
|
||||
|
||||
<A name="mrp_runtime"></A><B><U><big>Run Time and Memory Usage</big></U></B>
|
||||
-------------------------
|
||||
|
||||
Total CPU Time: 1 secs
|
||||
Total REAL Time: 0 secs
|
||||
Peak Memory Usage: 63 MB
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights
|
||||
reserved.
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
|
|
@ -0,0 +1,380 @@
|
|||
<HTML>
|
||||
<HEAD><TITLE>PAD Specification File</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Pad"></A>PAD Specification File
|
||||
***************************
|
||||
|
||||
PART TYPE: LCMXO2-1200HC
|
||||
Performance Grade: 4
|
||||
PACKAGE: TQFP100
|
||||
Package Status: Final Version 1.44
|
||||
|
||||
Thu Sep 21 05:34:59 2023
|
||||
|
||||
Pinout by Port Name:
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties |
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
| Ain[0] | 3/3 | LVCMOS33_IN | PL3A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Ain[1] | 2/3 | LVCMOS33_IN | PL2D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Ain[2] | 7/3 | LVCMOS33_IN | PL3C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Ain[3] | 4/3 | LVCMOS33_IN | PL3B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Ain[4] | 78/0 | LVCMOS33_IN | PT16C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Ain[5] | 84/0 | LVCMOS33_IN | PT15A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Ain[6] | 86/0 | LVCMOS33_IN | PT12C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Ain[7] | 8/3 | LVCMOS33_IN | PL3D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| BA[0] | 58/1 | LVCMOS33_OUT | PR9A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| BA[1] | 60/1 | LVCMOS33_OUT | PR8C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| C14M | 62/1 | LVCMOS33_IN | PR5D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| CKE | 53/1 | LVCMOS33_OUT | PR9D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| DQMH | 49/2 | LVCMOS33_OUT | PB20D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| DQML | 48/2 | LVCMOS33_OUT | PB20C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Din[0] | 96/0 | LVCMOS33_IN | PT10B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[1] | 97/0 | LVCMOS33_IN | PT10A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[2] | 98/0 | LVCMOS33_IN | PT9B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[3] | 9/3 | LVCMOS33_IN | PL4A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[4] | 1/3 | LVCMOS33_IN | PL2C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[5] | 99/0 | LVCMOS33_IN | PT9A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[6] | 88/0 | LVCMOS33_IN | PT12A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[7] | 87/0 | LVCMOS33_IN | PT12B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Dout[0] | 30/2 | LVCMOS33_OUT | PB6B | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[1] | 27/2 | LVCMOS33_OUT | PB4C | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[2] | 25/3 | LVCMOS33_OUT | PL10D | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[3] | 28/2 | LVCMOS33_OUT | PB4D | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[4] | 24/3 | LVCMOS33_OUT | PL10C | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[5] | 21/3 | LVCMOS33_OUT | PL9B | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[6] | 31/2 | LVCMOS33_OUT | PB6C | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[7] | 32/2 | LVCMOS33_OUT | PB6D | | | DRIVE:4mA SLEW:FAST |
|
||||
| LED | 35/2 | LVCMOS33_OUT | PB9B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| PHI1 | 85/0 | LVCMOS33_IN | PT12D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| RA[0] | 66/1 | LVCMOS33_OUT | PR4D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[10] | 64/1 | LVCMOS33_OUT | PR5B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[11] | 59/1 | LVCMOS33_OUT | PR8D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[1] | 68/1 | LVCMOS33_OUT | PR4B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[2] | 70/1 | LVCMOS33_OUT | PR3B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[3] | 74/1 | LVCMOS33_OUT | PR2B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[4] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[5] | 71/1 | LVCMOS33_OUT | PR3A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[6] | 69/1 | LVCMOS33_OUT | PR4A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[7] | 67/1 | LVCMOS33_OUT | PR4C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[9] | 63/1 | LVCMOS33_OUT | PR5C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RD[0] | 36/2 | LVCMOS33_BIDI | PB11C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[1] | 37/2 | LVCMOS33_BIDI | PB11D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[2] | 38/2 | LVCMOS33_BIDI | PB11A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[3] | 39/2 | LVCMOS33_BIDI | PB11B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[4] | 40/2 | LVCMOS33_BIDI | PB15A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[5] | 41/2 | LVCMOS33_BIDI | PB15B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[6] | 42/2 | LVCMOS33_BIDI | PB18A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[7] | 43/2 | LVCMOS33_BIDI | PB18B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| Vout[0] | 18/3 | LVCMOS33_OUT | PL8C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Vout[1] | 15/3 | LVCMOS33_OUT | PL5D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Vout[2] | 17/3 | LVCMOS33_OUT | PL8B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Vout[3] | 13/3 | LVCMOS33_OUT | PL5B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Vout[4] | 19/3 | LVCMOS33_OUT | PL8D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Vout[5] | 16/3 | LVCMOS33_OUT | PL8A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Vout[6] | 14/3 | LVCMOS33_OUT | PL5C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Vout[7] | 12/3 | LVCMOS33_OUT | PL5A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nC07X | 34/2 | LVCMOS33_IN | PB9A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nCAS | 52/1 | LVCMOS33_OUT | PR10C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nCS | 57/1 | LVCMOS33_OUT | PR9B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nDOE | 20/3 | LVCMOS33_OUT | PL9A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nEN80 | 82/0 | LVCMOS33_IN | PT15C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nRAS | 54/1 | LVCMOS33_OUT | PR9C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nRWE | 51/1 | LVCMOS33_OUT | PR10D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nVOE | 10/3 | LVCMOS33_OUT | PL4B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nWE | 29/2 | LVCMOS33_IN | PB6A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nWE80 | 83/0 | LVCMOS33_IN | PT15B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
|
||||
Vccio by Bank:
|
||||
+------+-------+
|
||||
| Bank | Vccio |
|
||||
+------+-------+
|
||||
| 0 | 3.3V |
|
||||
| 1 | 3.3V |
|
||||
| 2 | 3.3V |
|
||||
| 3 | 3.3V |
|
||||
+------+-------+
|
||||
|
||||
|
||||
<A name="pad_vref"></A><B><U><big>Vref by Bank:</big></U></B>
|
||||
+------+-----+-----------------+---------+
|
||||
| Vref | Pin | Bank # / Vref # | Load(s) |
|
||||
+------+-----+-----------------+---------+
|
||||
+------+-----+-----------------+---------+
|
||||
|
||||
<A name="pad_pin"></A><B><U><big>Pinout by Pin Number:</big></U></B>
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable |
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
| 1/3 | Din[4] | LOCATED | LVCMOS33_IN | PL2C | L_GPLLT_IN | | |
|
||||
| 2/3 | Ain[1] | LOCATED | LVCMOS33_IN | PL2D | L_GPLLC_IN | | |
|
||||
| 3/3 | Ain[0] | LOCATED | LVCMOS33_IN | PL3A | PCLKT3_2 | | |
|
||||
| 4/3 | Ain[3] | LOCATED | LVCMOS33_IN | PL3B | PCLKC3_2 | | |
|
||||
| 7/3 | Ain[2] | LOCATED | LVCMOS33_IN | PL3C | | | |
|
||||
| 8/3 | Ain[7] | LOCATED | LVCMOS33_IN | PL3D | | | |
|
||||
| 9/3 | Din[3] | LOCATED | LVCMOS33_IN | PL4A | | | |
|
||||
| 10/3 | nVOE | LOCATED | LVCMOS33_OUT | PL4B | | | |
|
||||
| 12/3 | Vout[7] | LOCATED | LVCMOS33_OUT | PL5A | PCLKT3_1 | | |
|
||||
| 13/3 | Vout[3] | LOCATED | LVCMOS33_OUT | PL5B | PCLKC3_1 | | |
|
||||
| 14/3 | Vout[6] | LOCATED | LVCMOS33_OUT | PL5C | | | |
|
||||
| 15/3 | Vout[1] | LOCATED | LVCMOS33_OUT | PL5D | | | |
|
||||
| 16/3 | Vout[5] | LOCATED | LVCMOS33_OUT | PL8A | | | |
|
||||
| 17/3 | Vout[2] | LOCATED | LVCMOS33_OUT | PL8B | | | |
|
||||
| 18/3 | Vout[0] | LOCATED | LVCMOS33_OUT | PL8C | | | |
|
||||
| 19/3 | Vout[4] | LOCATED | LVCMOS33_OUT | PL8D | | | |
|
||||
| 20/3 | nDOE | LOCATED | LVCMOS33_OUT | PL9A | PCLKT3_0 | | |
|
||||
| 21/3 | Dout[5] | LOCATED | LVCMOS33_OUT | PL9B | PCLKC3_0 | | |
|
||||
| 24/3 | Dout[4] | LOCATED | LVCMOS33_OUT | PL10C | | | |
|
||||
| 25/3 | Dout[2] | LOCATED | LVCMOS33_OUT | PL10D | | | |
|
||||
| 27/2 | Dout[1] | LOCATED | LVCMOS33_OUT | PB4C | CSSPIN | | |
|
||||
| 28/2 | Dout[3] | LOCATED | LVCMOS33_OUT | PB4D | | | |
|
||||
| 29/2 | nWE | LOCATED | LVCMOS33_IN | PB6A | | | |
|
||||
| 30/2 | Dout[0] | LOCATED | LVCMOS33_OUT | PB6B | | | |
|
||||
| 31/2 | Dout[6] | LOCATED | LVCMOS33_OUT | PB6C | MCLK/CCLK | | |
|
||||
| 32/2 | Dout[7] | LOCATED | LVCMOS33_OUT | PB6D | SO/SPISO | | |
|
||||
| 34/2 | nC07X | LOCATED | LVCMOS33_IN | PB9A | PCLKT2_0 | | |
|
||||
| 35/2 | LED | LOCATED | LVCMOS33_OUT | PB9B | PCLKC2_0 | | |
|
||||
| 36/2 | RD[0] | LOCATED | LVCMOS33_BIDI | PB11C | | | |
|
||||
| 37/2 | RD[1] | LOCATED | LVCMOS33_BIDI | PB11D | | | |
|
||||
| 38/2 | RD[2] | LOCATED | LVCMOS33_BIDI | PB11A | PCLKT2_1 | | |
|
||||
| 39/2 | RD[3] | LOCATED | LVCMOS33_BIDI | PB11B | PCLKC2_1 | | |
|
||||
| 40/2 | RD[4] | LOCATED | LVCMOS33_BIDI | PB15A | | | |
|
||||
| 41/2 | RD[5] | LOCATED | LVCMOS33_BIDI | PB15B | | | |
|
||||
| 42/2 | RD[6] | LOCATED | LVCMOS33_BIDI | PB18A | | | |
|
||||
| 43/2 | RD[7] | LOCATED | LVCMOS33_BIDI | PB18B | | | |
|
||||
| 45/2 | unused, PULL:DOWN | | | PB18C | | | |
|
||||
| 47/2 | unused, PULL:DOWN | | | PB18D | | | |
|
||||
| 48/2 | DQML | LOCATED | LVCMOS33_OUT | PB20C | SN | | |
|
||||
| 49/2 | DQMH | LOCATED | LVCMOS33_OUT | PB20D | SI/SISPI | | |
|
||||
| 51/1 | nRWE | LOCATED | LVCMOS33_OUT | PR10D | DQ1 | | |
|
||||
| 52/1 | nCAS | LOCATED | LVCMOS33_OUT | PR10C | DQ1 | | |
|
||||
| 53/1 | CKE | LOCATED | LVCMOS33_OUT | PR9D | DQ1 | | |
|
||||
| 54/1 | nRAS | LOCATED | LVCMOS33_OUT | PR9C | DQ1 | | |
|
||||
| 57/1 | nCS | LOCATED | LVCMOS33_OUT | PR9B | DQ1 | | |
|
||||
| 58/1 | BA[0] | LOCATED | LVCMOS33_OUT | PR9A | DQ1 | | |
|
||||
| 59/1 | RA[11] | LOCATED | LVCMOS33_OUT | PR8D | DQ1 | | |
|
||||
| 60/1 | BA[1] | LOCATED | LVCMOS33_OUT | PR8C | DQ1 | | |
|
||||
| 61/1 | unused, PULL:DOWN | | | PR8A | DQS1 | | |
|
||||
| 62/1 | C14M | LOCATED | LVCMOS33_IN | PR5D | PCLKC1_0/DQ0 | | |
|
||||
| 63/1 | RA[9] | LOCATED | LVCMOS33_OUT | PR5C | PCLKT1_0/DQ0 | | |
|
||||
| 64/1 | RA[10] | LOCATED | LVCMOS33_OUT | PR5B | DQS0N | | |
|
||||
| 65/1 | RA[8] | LOCATED | LVCMOS33_OUT | PR5A | DQS0 | | |
|
||||
| 66/1 | RA[0] | LOCATED | LVCMOS33_OUT | PR4D | DQ0 | | |
|
||||
| 67/1 | RA[7] | LOCATED | LVCMOS33_OUT | PR4C | DQ0 | | |
|
||||
| 68/1 | RA[1] | LOCATED | LVCMOS33_OUT | PR4B | DQ0 | | |
|
||||
| 69/1 | RA[6] | LOCATED | LVCMOS33_OUT | PR4A | DQ0 | | |
|
||||
| 70/1 | RA[2] | LOCATED | LVCMOS33_OUT | PR3B | DQ0 | | |
|
||||
| 71/1 | RA[5] | LOCATED | LVCMOS33_OUT | PR3A | DQ0 | | |
|
||||
| 74/1 | RA[3] | LOCATED | LVCMOS33_OUT | PR2B | DQ0 | | |
|
||||
| 75/1 | RA[4] | LOCATED | LVCMOS33_OUT | PR2A | DQ0 | | |
|
||||
| 76/0 | unused, PULL:DOWN | | | PT17D | DONE | | |
|
||||
| 77/0 | unused, PULL:DOWN | | | PT17C | INITN | | |
|
||||
| 78/0 | Ain[4] | LOCATED | LVCMOS33_IN | PT16C | | | |
|
||||
| 81/0 | unused, PULL:DOWN | | | PT15D | PROGRAMN | | |
|
||||
| 82/0 | nEN80 | LOCATED | LVCMOS33_IN | PT15C | JTAGENB | | |
|
||||
| 83/0 | nWE80 | LOCATED | LVCMOS33_IN | PT15B | | | |
|
||||
| 84/0 | Ain[5] | LOCATED | LVCMOS33_IN | PT15A | | | |
|
||||
| 85/0 | PHI1 | LOCATED | LVCMOS33_IN | PT12D | SDA/PCLKC0_0 | | |
|
||||
| 86/0 | Ain[6] | LOCATED | LVCMOS33_IN | PT12C | SCL/PCLKT0_0 | | |
|
||||
| 87/0 | Din[7] | LOCATED | LVCMOS33_IN | PT12B | PCLKC0_1 | | |
|
||||
| 88/0 | Din[6] | LOCATED | LVCMOS33_IN | PT12A | PCLKT0_1 | | |
|
||||
| 90/0 | Reserved: sysCONFIG | | | PT11D | TMS | | |
|
||||
| 91/0 | Reserved: sysCONFIG | | | PT11C | TCK | | |
|
||||
| 94/0 | Reserved: sysCONFIG | | | PT10D | TDI | | |
|
||||
| 95/0 | Reserved: sysCONFIG | | | PT10C | TDO | | |
|
||||
| 96/0 | Din[0] | LOCATED | LVCMOS33_IN | PT10B | | | |
|
||||
| 97/0 | Din[1] | LOCATED | LVCMOS33_IN | PT10A | | | |
|
||||
| 98/0 | Din[2] | LOCATED | LVCMOS33_IN | PT9B | | | |
|
||||
| 99/0 | Din[5] | LOCATED | LVCMOS33_IN | PT9A | | | |
|
||||
| PB4A/2 | unused, PULL:DOWN | | | PB4A | | | |
|
||||
| PB4B/2 | unused, PULL:DOWN | | | PB4B | | | |
|
||||
| PB9C/2 | unused, PULL:DOWN | | | PB9C | | | |
|
||||
| PB9D/2 | unused, PULL:DOWN | | | PB9D | | | |
|
||||
| PB15C/2 | unused, PULL:DOWN | | | PB15C | | | |
|
||||
| PB15D/2 | unused, PULL:DOWN | | | PB15D | | | |
|
||||
| PB20A/2 | unused, PULL:DOWN | | | PB20A | | | |
|
||||
| PB20B/2 | unused, PULL:DOWN | | | PB20B | | | |
|
||||
| PL2A/3 | unused, PULL:DOWN | | | PL2A | L_GPLLT_FB | | |
|
||||
| PL2B/3 | unused, PULL:DOWN | | | PL2B | L_GPLLC_FB | | |
|
||||
| PL4C/3 | unused, PULL:DOWN | | | PL4C | | | |
|
||||
| PL4D/3 | unused, PULL:DOWN | | | PL4D | | | |
|
||||
| PL10A/3 | unused, PULL:DOWN | | | PL10A | | | |
|
||||
| PL10B/3 | unused, PULL:DOWN | | | PL10B | | | |
|
||||
| PR2C/1 | unused, PULL:DOWN | | | PR2C | DQ0 | | |
|
||||
| PR2D/1 | unused, PULL:DOWN | | | PR2D | DQ0 | | |
|
||||
| PR8B/1 | unused, PULL:DOWN | | | PR8B | DQS1N | | |
|
||||
| PR10A/1 | unused, PULL:DOWN | | | PR10A | DQ1 | | |
|
||||
| PR10B/1 | unused, PULL:DOWN | | | PR10B | DQ1 | | |
|
||||
| PT9C/0 | unused, PULL:DOWN | | | PT9C | | | |
|
||||
| PT9D/0 | unused, PULL:DOWN | | | PT9D | | | |
|
||||
| PT11A/0 | unused, PULL:DOWN | | | PT11A | | | |
|
||||
| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | |
|
||||
| PT16A/0 | unused, PULL:DOWN | | | PT16A | | | |
|
||||
| PT16B/0 | unused, PULL:DOWN | | | PT16B | | | |
|
||||
| PT16D/0 | unused, PULL:DOWN | | | PT16D | | | |
|
||||
| PT17A/0 | unused, PULL:DOWN | | | PT17A | | | |
|
||||
| PT17B/0 | unused, PULL:DOWN | | | PT17B | | | |
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
|
||||
sysCONFIG Pins:
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode |
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
| PT11D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP |
|
||||
| PT11C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down |
|
||||
| PT10D | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP |
|
||||
| PT10C | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP |
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
|
||||
Dedicated sysCONFIG Pins:
|
||||
|
||||
|
||||
List of All Pins' Locate Preferences Based on Final Placement After PAR
|
||||
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste):
|
||||
|
||||
LOCATE COMP "Ain[0]" SITE "3";
|
||||
LOCATE COMP "Ain[1]" SITE "2";
|
||||
LOCATE COMP "Ain[2]" SITE "7";
|
||||
LOCATE COMP "Ain[3]" SITE "4";
|
||||
LOCATE COMP "Ain[4]" SITE "78";
|
||||
LOCATE COMP "Ain[5]" SITE "84";
|
||||
LOCATE COMP "Ain[6]" SITE "86";
|
||||
LOCATE COMP "Ain[7]" SITE "8";
|
||||
LOCATE COMP "BA[0]" SITE "58";
|
||||
LOCATE COMP "BA[1]" SITE "60";
|
||||
LOCATE COMP "C14M" SITE "62";
|
||||
LOCATE COMP "CKE" SITE "53";
|
||||
LOCATE COMP "DQMH" SITE "49";
|
||||
LOCATE COMP "DQML" SITE "48";
|
||||
LOCATE COMP "Din[0]" SITE "96";
|
||||
LOCATE COMP "Din[1]" SITE "97";
|
||||
LOCATE COMP "Din[2]" SITE "98";
|
||||
LOCATE COMP "Din[3]" SITE "9";
|
||||
LOCATE COMP "Din[4]" SITE "1";
|
||||
LOCATE COMP "Din[5]" SITE "99";
|
||||
LOCATE COMP "Din[6]" SITE "88";
|
||||
LOCATE COMP "Din[7]" SITE "87";
|
||||
LOCATE COMP "Dout[0]" SITE "30";
|
||||
LOCATE COMP "Dout[1]" SITE "27";
|
||||
LOCATE COMP "Dout[2]" SITE "25";
|
||||
LOCATE COMP "Dout[3]" SITE "28";
|
||||
LOCATE COMP "Dout[4]" SITE "24";
|
||||
LOCATE COMP "Dout[5]" SITE "21";
|
||||
LOCATE COMP "Dout[6]" SITE "31";
|
||||
LOCATE COMP "Dout[7]" SITE "32";
|
||||
LOCATE COMP "LED" SITE "35";
|
||||
LOCATE COMP "PHI1" SITE "85";
|
||||
LOCATE COMP "RA[0]" SITE "66";
|
||||
LOCATE COMP "RA[10]" SITE "64";
|
||||
LOCATE COMP "RA[11]" SITE "59";
|
||||
LOCATE COMP "RA[1]" SITE "68";
|
||||
LOCATE COMP "RA[2]" SITE "70";
|
||||
LOCATE COMP "RA[3]" SITE "74";
|
||||
LOCATE COMP "RA[4]" SITE "75";
|
||||
LOCATE COMP "RA[5]" SITE "71";
|
||||
LOCATE COMP "RA[6]" SITE "69";
|
||||
LOCATE COMP "RA[7]" SITE "67";
|
||||
LOCATE COMP "RA[8]" SITE "65";
|
||||
LOCATE COMP "RA[9]" SITE "63";
|
||||
LOCATE COMP "RD[0]" SITE "36";
|
||||
LOCATE COMP "RD[1]" SITE "37";
|
||||
LOCATE COMP "RD[2]" SITE "38";
|
||||
LOCATE COMP "RD[3]" SITE "39";
|
||||
LOCATE COMP "RD[4]" SITE "40";
|
||||
LOCATE COMP "RD[5]" SITE "41";
|
||||
LOCATE COMP "RD[6]" SITE "42";
|
||||
LOCATE COMP "RD[7]" SITE "43";
|
||||
LOCATE COMP "Vout[0]" SITE "18";
|
||||
LOCATE COMP "Vout[1]" SITE "15";
|
||||
LOCATE COMP "Vout[2]" SITE "17";
|
||||
LOCATE COMP "Vout[3]" SITE "13";
|
||||
LOCATE COMP "Vout[4]" SITE "19";
|
||||
LOCATE COMP "Vout[5]" SITE "16";
|
||||
LOCATE COMP "Vout[6]" SITE "14";
|
||||
LOCATE COMP "Vout[7]" SITE "12";
|
||||
LOCATE COMP "nC07X" SITE "34";
|
||||
LOCATE COMP "nCAS" SITE "52";
|
||||
LOCATE COMP "nCS" SITE "57";
|
||||
LOCATE COMP "nDOE" SITE "20";
|
||||
LOCATE COMP "nEN80" SITE "82";
|
||||
LOCATE COMP "nRAS" SITE "54";
|
||||
LOCATE COMP "nRWE" SITE "51";
|
||||
LOCATE COMP "nVOE" SITE "10";
|
||||
LOCATE COMP "nWE" SITE "29";
|
||||
LOCATE COMP "nWE80" SITE "83";
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Thu Sep 21 05:35:04 2023
|
||||
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
|
|
@ -0,0 +1,299 @@
|
|||
<HTML>
|
||||
<HEAD><TITLE>Place & Route Report</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Par"></A>PAR: Place And Route Diamond (64-bit) 3.12.1.454.
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Thu Sep 21 05:34:51 2023
|
||||
|
||||
C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2E_LCMXO2_1200HC_impl1.p2t
|
||||
RAM2E_LCMXO2_1200HC_impl1_map.ncd RAM2E_LCMXO2_1200HC_impl1.dir
|
||||
RAM2E_LCMXO2_1200HC_impl1.prf -gui -msgset
|
||||
//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml
|
||||
|
||||
|
||||
Preference file: RAM2E_LCMXO2_1200HC_impl1.prf.
|
||||
|
||||
<A name="par_cts"></A><B><U><big>Cost Table Summary</big></U></B>
|
||||
Level/ Number Worst Timing Worst Timing Run NCD
|
||||
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
|
||||
---------- -------- ----- ------ ----------- ----------- ---- ------
|
||||
5_1 * 0 57.121 0 0.333 0 15 Completed
|
||||
* : Design saved.
|
||||
|
||||
Total (real) run time for 1-seed: 15 secs
|
||||
|
||||
par done!
|
||||
|
||||
Note: user must run 'Trace' for timing closure signoff.
|
||||
|
||||
Lattice Place and Route Report for Design "RAM2E_LCMXO2_1200HC_impl1_map.ncd"
|
||||
Thu Sep 21 05:34:51 2023
|
||||
|
||||
|
||||
<A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
|
||||
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
|
||||
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2E_LCMXO2_1200HC_impl1_map.ncd RAM2E_LCMXO2_1200HC_impl1.dir/5_1.ncd RAM2E_LCMXO2_1200HC_impl1.prf
|
||||
Preference file: RAM2E_LCMXO2_1200HC_impl1.prf.
|
||||
Placement level-cost: 5-1.
|
||||
Routing Iterations: 6
|
||||
|
||||
Loading design for application par from file RAM2E_LCMXO2_1200HC_impl1_map.ncd.
|
||||
Design name: RAM2E
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-1200HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.44.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
License checked out.
|
||||
|
||||
|
||||
Ignore Preference Error(s): True
|
||||
|
||||
<A name="par_dus"></A><B><U><big>Device utilization summary:</big></U></B>
|
||||
|
||||
PIO (prelim) 70+4(JTAG)/108 69% used
|
||||
70+4(JTAG)/80 93% bonded
|
||||
IOLOGIC 36/108 33% used
|
||||
|
||||
SLICE 120/640 18% used
|
||||
|
||||
EFB 1/1 100% used
|
||||
|
||||
|
||||
Number of Signals: 395
|
||||
Number of Connections: 1126
|
||||
|
||||
Pin Constraint Summary:
|
||||
70 out of 70 pins locked (100% locked).
|
||||
|
||||
The following 1 signal is selected to use the primary clock routing resources:
|
||||
C14M_c (driver: C14M, clk load #: 84)
|
||||
|
||||
WARNING - par: Signal "C14M_c" is selected to use Primary clock resources. However, its driver comp "C14M" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
|
||||
The following 1 signal is selected to use the secondary clock routing resources:
|
||||
N_576_i (driver: SLICE_20, clk load #: 0, sr load #: 0, ce load #: 17)
|
||||
|
||||
No signal is selected as Global Set/Reset.
|
||||
Starting Placer Phase 0.
|
||||
........
|
||||
Finished Placer Phase 0. REAL time: 2 secs
|
||||
|
||||
Starting Placer Phase 1.
|
||||
..................
|
||||
Placer score = 78271.
|
||||
Finished Placer Phase 1. REAL time: 8 secs
|
||||
|
||||
Starting Placer Phase 2.
|
||||
.
|
||||
Placer score = 77117
|
||||
Finished Placer Phase 2. REAL time: 8 secs
|
||||
|
||||
|
||||
|
||||
<A name="par_clk"></A><B><U><big>Clock Report</big></U></B>
|
||||
|
||||
Global Clock Resources:
|
||||
CLK_PIN : 0 out of 8 (0%)
|
||||
General PIO: 1 out of 108 (0%)
|
||||
PLL : 0 out of 1 (0%)
|
||||
DCM : 0 out of 2 (0%)
|
||||
DCC : 0 out of 8 (0%)
|
||||
|
||||
Global Clocks:
|
||||
PRIMARY "C14M_c" from comp "C14M" on PIO site "62 (PR5D)", clk load = 84
|
||||
SECONDARY "N_576_i" from F1 on comp "SLICE_20" on site "R7C12C", clk load = 0, ce load = 17, sr load = 0
|
||||
|
||||
PRIMARY : 1 out of 8 (12%)
|
||||
SECONDARY: 1 out of 8 (12%)
|
||||
|
||||
Edge Clocks:
|
||||
No edge clock selected.
|
||||
|
||||
|
||||
|
||||
|
||||
I/O Usage Summary (final):
|
||||
70 + 4(JTAG) out of 108 (68.5%) PIO sites used.
|
||||
70 + 4(JTAG) out of 80 (92.5%) bonded PIO sites used.
|
||||
Number of PIO comps: 70; differential: 0.
|
||||
Number of Vref pins used: 0.
|
||||
|
||||
I/O Bank Usage Summary:
|
||||
+----------+----------------+------------+-----------+
|
||||
| I/O Bank | Usage | Bank Vccio | Bank Vref |
|
||||
+----------+----------------+------------+-----------+
|
||||
| 0 | 12 / 19 ( 63%) | 3.3V | - |
|
||||
| 1 | 20 / 21 ( 95%) | 3.3V | - |
|
||||
| 2 | 18 / 20 ( 90%) | 3.3V | - |
|
||||
| 3 | 20 / 20 (100%) | 3.3V | - |
|
||||
+----------+----------------+------------+-----------+
|
||||
|
||||
Total placer CPU time: 7 secs
|
||||
|
||||
Dumping design to file RAM2E_LCMXO2_1200HC_impl1.dir/5_1.ncd.
|
||||
|
||||
0 connections routed; 1126 unrouted.
|
||||
Starting router resource preassignment
|
||||
WARNING - par: The driver of primary clock net C14M_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
|
||||
|
||||
Completed router resource preassignment. Real time: 13 secs
|
||||
|
||||
Start NBR router at 05:35:04 09/21/23
|
||||
|
||||
*****************************************************************
|
||||
Info: NBR allows conflicts(one node used by more than one signal)
|
||||
in the earlier iterations. In each iteration, it tries to
|
||||
solve the conflicts while keeping the critical connections
|
||||
routed as short as possible. The routing process is said to
|
||||
be completed when no conflicts exist and all connections
|
||||
are routed.
|
||||
Note: NBR uses a different method to calculate timing slacks. The
|
||||
worst slack and total negative slack may not be the same as
|
||||
that in TRCE report. You should always run TRCE to verify
|
||||
your design.
|
||||
*****************************************************************
|
||||
|
||||
Start NBR special constraint process at 05:35:05 09/21/23
|
||||
|
||||
Start NBR section for initial routing at 05:35:05 09/21/23
|
||||
Level 4, iteration 1
|
||||
13(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 57.121ns/0.000ns; real time: 14 secs
|
||||
|
||||
Info: Initial congestion level at 75% usage is 0
|
||||
Info: Initial congestion area at 75% usage is 0 (0.00%)
|
||||
|
||||
Start NBR section for normal routing at 05:35:05 09/21/23
|
||||
Level 4, iteration 1
|
||||
4(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 57.121ns/0.000ns; real time: 14 secs
|
||||
Level 4, iteration 2
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 57.121ns/0.000ns; real time: 14 secs
|
||||
|
||||
Start NBR section for setup/hold timing optimization with effort level 3 at 05:35:05 09/21/23
|
||||
|
||||
Start NBR section for re-routing at 05:35:05 09/21/23
|
||||
Level 4, iteration 1
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 57.121ns/0.000ns; real time: 14 secs
|
||||
|
||||
Start NBR section for post-routing at 05:35:05 09/21/23
|
||||
|
||||
End NBR router with 0 unrouted connection
|
||||
|
||||
NBR Summary
|
||||
-----------
|
||||
Number of unrouted connections : 0 (0.00%)
|
||||
Number of connections with timing violations : 0 (0.00%)
|
||||
Estimated worst slack<setup> : 57.121ns
|
||||
Timing score<setup> : 0
|
||||
-----------
|
||||
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
|
||||
|
||||
|
||||
|
||||
Total CPU time 14 secs
|
||||
Total REAL time: 15 secs
|
||||
Completely routed.
|
||||
End of route. 1126 routed (100.00%); 0 unrouted.
|
||||
|
||||
Hold time timing score: 0, hold timing errors: 0
|
||||
|
||||
Timing score: 0
|
||||
|
||||
Dumping design to file RAM2E_LCMXO2_1200HC_impl1.dir/5_1.ncd.
|
||||
|
||||
|
||||
All signals are completely routed.
|
||||
|
||||
|
||||
PAR_SUMMARY::Run status = Completed
|
||||
PAR_SUMMARY::Number of unrouted conns = 0
|
||||
PAR_SUMMARY::Worst slack<setup/<ns>> = 57.121
|
||||
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
|
||||
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.333
|
||||
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
|
||||
PAR_SUMMARY::Number of errors = 0
|
||||
|
||||
Total CPU time to completion: 15 secs
|
||||
Total REAL time to completion: 15 secs
|
||||
|
||||
par done!
|
||||
|
||||
Note: user must run 'Trace' for timing closure signoff.
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: R-2021.03L-SP1
|
||||
Install: C:\lscc\diamond\3.12\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
|
||||
# Written on Thu Sep 21 05:34:37 2023
|
||||
|
||||
##### FILES SYNTAX CHECKED ##############################################
|
||||
Constraint File(s): "\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc"
|
||||
|
||||
#Run constraint checker to find more issues with constraints.
|
||||
#########################################################################
|
||||
|
||||
|
||||
|
||||
No issues found in constraint syntax.
|
||||
|
||||
|
||||
|
||||
Clock Summary
|
||||
*************
|
||||
|
||||
Start Requested Requested Clock Clock Clock
|
||||
Level Clock Frequency Period Type Group Load
|
||||
----------------------------------------------------------------------------------------
|
||||
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 111
|
||||
|
||||
0 - System 100.0 MHz 10.000 system system_clkgroup 0
|
||||
========================================================================================
|
||||
|
||||
|
||||
Clock Load Summary
|
||||
******************
|
||||
|
||||
Clock Source Clock Pin Non-clock Pin Non-clock Pin
|
||||
Clock Load Pin Seq Example Seq Example Comb Example
|
||||
----------------------------------------------------------------------------------------
|
||||
C14M 111 C14M(port) wb_rst.C - un1_C14M.I[0](inv)
|
||||
|
||||
System 0 - - - -
|
||||
========================================================================================
|
||||
|
|
@ -0,0 +1,83 @@
|
|||
<HTML>
|
||||
<HEAD><TITLE>Project Summary</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><TABLE border=1 width=100% cellspacing=0 cellpadding=2><small>
|
||||
<TR>
|
||||
<TD align='center' BGCOLOR='#000099' COLSPAN='4'><SPAN style="COLOR: #FFFFFF"><B>RAM2E_LCMXO2_1200HC project summary</B></SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Module Name:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">RAM2E_LCMXO2_1200HC</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Synthesis:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">SynplifyPro</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Name:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">impl1</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Strategy Name:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">Strategy1</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Last Process:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">JEDEC File</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">State:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">Passed</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Target Device:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">LCMXO2-1200HC-4TG100C</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Device Family:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">MachXO2</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Device Type:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">LCMXO2-1200HC</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Package Type:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">TQFP100</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Performance grade:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">4</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Operating conditions:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">COM</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Logic preference file:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">RAM2E-LCMXO2.lpf</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Physical Preference file:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">impl1/RAM2E_LCMXO2_1200HC_impl1.prf</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Product Version:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">3.12.1.454</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Patch Version:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000"></SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Updated:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2023/09/21 05:35:26</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Location:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/impl1</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Project File:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC.ldf</SPAN></TD>
|
||||
</TR>
|
||||
</small></TABLE>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
|
|
@ -0,0 +1,755 @@
|
|||
<HTML>
|
||||
<HEAD><TITLE>Synthesis Report</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
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background-color: #ffffff;
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h1 {
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border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
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font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
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border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
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font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Syn"></A><B><U><big>Synthesis Report</big></U></B>
|
||||
#Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021
|
||||
#install: C:\lscc\diamond\3.12\synpbase
|
||||
#OS: Windows 8 6.2
|
||||
#Hostname: ZANEMACWIN11
|
||||
|
||||
# Thu Sep 21 05:34:34 2023
|
||||
|
||||
#Implementation: impl1
|
||||
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: R-2021.03L-SP1
|
||||
Install: C:\lscc\diamond\3.12\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
###########################################################[
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: R-2021.03L-SP1
|
||||
Install: C:\lscc\diamond\3.12\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v" (library work)
|
||||
@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
|
||||
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
|
||||
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
|
||||
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
|
||||
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
|
||||
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E-LCMXO2.v" (library work)
|
||||
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\REFB.v" (library work)
|
||||
Verilog syntax check successful!
|
||||
|
||||
Compiler output is up to date. No re-compile necessary
|
||||
|
||||
Selecting top level module RAM2E
|
||||
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
|
||||
Running optimization stage 1 on VHI .......
|
||||
Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
|
||||
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
|
||||
Running optimization stage 1 on VLO .......
|
||||
Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
|
||||
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
|
||||
Running optimization stage 1 on EFB .......
|
||||
Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
|
||||
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
|
||||
Running optimization stage 1 on REFB .......
|
||||
Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
|
||||
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E-LCMXO2.v":1:7:1:11|Synthesizing module RAM2E in library work.
|
||||
Running optimization stage 1 on RAM2E .......
|
||||
Finished optimization stage 1 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB)
|
||||
Running optimization stage 2 on RAM2E .......
|
||||
Finished optimization stage 2 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
|
||||
Running optimization stage 2 on REFB .......
|
||||
Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
|
||||
Running optimization stage 2 on EFB .......
|
||||
Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
|
||||
Running optimization stage 2 on VLO .......
|
||||
Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
|
||||
Running optimization stage 2 on VHI .......
|
||||
Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
|
||||
|
||||
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 97MB peak: 97MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:34:34 2023
|
||||
|
||||
###########################################################]
|
||||
###########################################################[
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: R-2021.03L-SP1
|
||||
Install: C:\lscc\diamond\3.12\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:34:34 2023
|
||||
|
||||
###########################################################]
|
||||
|
||||
For a summary of runtime and memory usage for all design units, please see file:
|
||||
==========================================================
|
||||
@L: A:\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_comp.rt.csv
|
||||
|
||||
@END
|
||||
|
||||
At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:34:34 2023
|
||||
|
||||
###########################################################]
|
||||
###########################################################[
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: R-2021.03L-SP1
|
||||
Install: C:\lscc\diamond\3.12\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
File \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_comp.srs changed - recompiling
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:34:36 2023
|
||||
|
||||
###########################################################]
|
||||
# Thu Sep 21 05:34:36 2023
|
||||
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: R-2021.03L-SP1
|
||||
Install: C:\lscc\diamond\3.12\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @
|
||||
|
||||
|
||||
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
|
||||
|
||||
|
||||
Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 141MB)
|
||||
|
||||
Reading constraint file: \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
|
||||
@L: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1_scck.rpt
|
||||
See clock summary report "\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1_scck.rpt"
|
||||
@N: MF916 |Option synthesis_strategy=base is enabled.
|
||||
@N: MF248 |Running in 64-bit mode.
|
||||
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
|
||||
|
||||
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 141MB)
|
||||
|
||||
|
||||
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 141MB)
|
||||
|
||||
|
||||
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 149MB)
|
||||
|
||||
|
||||
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 151MB)
|
||||
|
||||
@N: FX493 |Applying initial value "0" on instance PHI1reg.
|
||||
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
|
||||
@N: FX493 |Applying initial value "0" on instance DOEEN.
|
||||
@N: FX493 |Applying initial value "0" on instance RWSel.
|
||||
@N: FX493 |Applying initial value "00000000" on instance RWBank[7:0].
|
||||
@N: FX493 |Applying initial value "1" on instance DQMH.
|
||||
@N: FX493 |Applying initial value "0" on instance Ready.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdBitbangMXO2.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdExecMXO2.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdLEDGet.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdLEDSet.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdRWMaskSet.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdSetRWBankFFLED.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdSetRWBankFFMXO2.
|
||||
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":375:4:375:9|Initial value on register nRWE is non-zero which can prevent the register from being packed into a block RAM or DSP.
|
||||
@N: FX493 |Applying initial value "1" on instance nRWE.
|
||||
@N: FX493 |Applying initial value "0" on instance LEDEN.
|
||||
@N: FX493 |Applying initial value "00000000" on instance RWMask[7:0].
|
||||
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":102:4:102:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
|
||||
@N: FX493 |Applying initial value "0000" on instance S[3:0].
|
||||
@N: FX493 |Applying initial value "1" on instance DQML.
|
||||
@N: FX493 |Applying initial value "0" on instance CKE.
|
||||
@N: FX493 |Applying initial value "1" on instance nCS.
|
||||
@N: FX493 |Applying initial value "1" on instance nRAS.
|
||||
@N: FX493 |Applying initial value "1" on instance nCAS.
|
||||
|
||||
Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
|
||||
|
||||
|
||||
Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
|
||||
|
||||
|
||||
Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
|
||||
|
||||
|
||||
Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
|
||||
|
||||
@N: FX1184 |Applying syn_allowed_resources blockrams=7 on top level netlist RAM2E
|
||||
|
||||
Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 181MB peak: 182MB)
|
||||
|
||||
|
||||
|
||||
Clock Summary
|
||||
******************
|
||||
|
||||
Start Requested Requested Clock Clock Clock
|
||||
Level Clock Frequency Period Type Group Load
|
||||
----------------------------------------------------------------------------------------
|
||||
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 111
|
||||
|
||||
0 - System 100.0 MHz 10.000 system system_clkgroup 0
|
||||
========================================================================================
|
||||
|
||||
|
||||
|
||||
Clock Load Summary
|
||||
***********************
|
||||
|
||||
Clock Source Clock Pin Non-clock Pin Non-clock Pin
|
||||
Clock Load Pin Seq Example Seq Example Comb Example
|
||||
----------------------------------------------------------------------------------------
|
||||
C14M 111 C14M(port) wb_rst.C - un1_C14M.I[0](inv)
|
||||
|
||||
System 0 - - - -
|
||||
========================================================================================
|
||||
|
||||
ICG Latch Removal Summary:
|
||||
Number of ICG latches removed: 0
|
||||
Number of ICG latches not removed: 0
|
||||
For details review file gcc_ICG_report.rpt
|
||||
|
||||
|
||||
@S |Clock Optimization Summary
|
||||
|
||||
|
||||
|
||||
#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
|
||||
|
||||
1 non-gated/non-generated clock tree(s) driving 111 clock pin(s) of sequential element(s)
|
||||
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
|
||||
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
|
||||
|
||||
=========================== Non-Gated/Non-Generated Clocks ============================
|
||||
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
|
||||
---------------------------------------------------------------------------------------
|
||||
@KP:ckid0_0 C14M port 111 nCAS
|
||||
=======================================================================================
|
||||
|
||||
|
||||
##### END OF CLOCK OPTIMIZATION REPORT ######
|
||||
|
||||
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
|
||||
Finished Pre Mapping Phase.
|
||||
|
||||
Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
|
||||
|
||||
|
||||
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
|
||||
|
||||
|
||||
Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
|
||||
|
||||
Pre-mapping successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 99MB peak: 185MB)
|
||||
|
||||
Process took 0h:00m:02s realtime, 0h:00m:01s cputime
|
||||
# Thu Sep 21 05:34:38 2023
|
||||
|
||||
###########################################################]
|
||||
# Thu Sep 21 05:34:38 2023
|
||||
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: R-2021.03L-SP1
|
||||
Install: C:\lscc\diamond\3.12\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @
|
||||
|
||||
|
||||
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
|
||||
|
||||
@N: MF916 |Option synthesis_strategy=base is enabled.
|
||||
@N: MF248 |Running in 64-bit mode.
|
||||
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
|
||||
|
||||
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
|
||||
|
||||
|
||||
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
|
||||
|
||||
|
||||
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
|
||||
|
||||
|
||||
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB)
|
||||
|
||||
|
||||
|
||||
Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 179MB peak: 179MB)
|
||||
|
||||
@W: FA239 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":376:8:376:9|ROM DOEEN_2 (in view: work.RAM2E(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
|
||||
@N: MO106 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":376:8:376:9|Found ROM DOEEN_2 (in view: work.RAM2E(verilog)) with 16 words by 1 bit.
|
||||
|
||||
Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
|
||||
|
||||
@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":102:4:102:9|Found counter in view:work.RAM2E(verilog) instance FS[15:0]
|
||||
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
|
||||
|
||||
Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB)
|
||||
|
||||
|
||||
Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
|
||||
|
||||
|
||||
Available hyper_sources - for debug and ip models
|
||||
None Found
|
||||
|
||||
|
||||
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
|
||||
|
||||
|
||||
Starting Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
|
||||
|
||||
|
||||
Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
|
||||
|
||||
|
||||
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
|
||||
|
||||
|
||||
Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
|
||||
|
||||
|
||||
Finished technology mapping (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 205MB peak: 205MB)
|
||||
|
||||
Pass CPU time Worst Slack Luts / Registers
|
||||
------------------------------------------------------------
|
||||
1 0h:00m:02s 29.35ns 222 / 111
|
||||
|
||||
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 205MB peak: 205MB)
|
||||
|
||||
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
|
||||
|
||||
Finished restoring hierarchy (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 206MB peak: 206MB)
|
||||
|
||||
|
||||
Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 168MB peak: 206MB)
|
||||
|
||||
Writing Analyst data base \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_m.srm
|
||||
|
||||
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:02s; Memory used current: 206MB peak: 206MB)
|
||||
|
||||
Writing EDIF Netlist and constraint files
|
||||
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1.edi
|
||||
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
|
||||
|
||||
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:03s; Memory used current: 211MB peak: 211MB)
|
||||
|
||||
|
||||
Finished Writing Netlists (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:03s; Memory used current: 211MB peak: 211MB)
|
||||
|
||||
|
||||
Start final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 209MB peak: 211MB)
|
||||
|
||||
@W: MT246 :"\\mac\icloud\repos\ram2e\cpld\lcmxo2-1200hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
|
||||
@N: MT615 |Found clock C14M with period 69.84ns
|
||||
|
||||
|
||||
##### START OF TIMING REPORT #####[
|
||||
# Timing report written on Thu Sep 21 05:34:44 2023
|
||||
#
|
||||
|
||||
|
||||
Top view: RAM2E
|
||||
Requested Frequency: 14.3 MHz
|
||||
Wire load mode: top
|
||||
Paths requested: 5
|
||||
Constraint File(s): \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
|
||||
|
||||
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
|
||||
|
||||
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
|
||||
|
||||
|
||||
|
||||
Performance Summary
|
||||
*******************
|
||||
|
||||
|
||||
Worst slack in design: 31.782
|
||||
|
||||
Requested Estimated Requested Estimated Clock Clock
|
||||
Starting Clock Frequency Frequency Period Period Slack Type Group
|
||||
-------------------------------------------------------------------------------------------------------------------
|
||||
C14M 14.3 MHz 131.4 MHz 69.841 7.610 31.782 declared default_clkgroup
|
||||
System 100.0 MHz NA 10.000 NA 67.088 system system_clkgroup
|
||||
===================================================================================================================
|
||||
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Clock Relationships
|
||||
*******************
|
||||
|
||||
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
System C14M | 69.841 67.088 | No paths - | No paths - | No paths -
|
||||
C14M System | 69.841 68.797 | No paths - | No paths - | No paths -
|
||||
C14M C14M | 69.841 62.231 | No paths - | 34.920 31.782 | No paths -
|
||||
==========================================================================================================
|
||||
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
|
||||
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
|
||||
|
||||
|
||||
|
||||
Interface Information
|
||||
*********************
|
||||
|
||||
No IO constraint found
|
||||
|
||||
|
||||
|
||||
====================================
|
||||
Detailed Report for Clock: C14M
|
||||
====================================
|
||||
|
||||
|
||||
|
||||
Starting Points with Worst Slack
|
||||
********************************
|
||||
|
||||
Starting Arrival
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------
|
||||
S[2] C14M FD1S3AX Q S[2] 1.350 31.782
|
||||
S[3] C14M FD1S3AX Q S[3] 1.350 31.782
|
||||
S[0] C14M FD1S3AX Q S[0] 1.312 31.820
|
||||
S[1] C14M FD1S3AX Q S[1] 1.280 31.852
|
||||
FS[9] C14M FD1S3AX Q FS[9] 1.284 62.425
|
||||
FS[11] C14M FD1S3AX Q FS[11] 1.276 62.433
|
||||
FS[8] C14M FD1S3AX Q FS[8] 1.260 62.449
|
||||
FS[12] C14M FD1S3AX Q FS[12] 1.288 62.525
|
||||
FS[10] C14M FD1S3AX Q FS[10] 1.280 62.533
|
||||
RWSel C14M FD1P3AX Q RWSel 1.276 63.482
|
||||
============================================================================
|
||||
|
||||
|
||||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------------
|
||||
Dout_0io[0] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[1] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[2] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[3] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[4] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[5] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[6] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[7] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Vout_0io[0] C14M OFS1P3DX SP Vout3 34.449 31.826
|
||||
Vout_0io[1] C14M OFS1P3DX SP Vout3 34.449 31.826
|
||||
==================================================================================
|
||||
|
||||
|
||||
|
||||
Worst Path Information
|
||||
***********************
|
||||
|
||||
|
||||
Path information for path number 1:
|
||||
Requested Period: 34.920
|
||||
- Setup time: 0.472
|
||||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
= Required time: 34.449
|
||||
|
||||
- Propagation time: 2.667
|
||||
- Clock delay at starting point: 0.000 (ideal)
|
||||
= Slack (critical) : 31.782
|
||||
|
||||
Number of logic level(s): 1
|
||||
Starting point: S[2] / Q
|
||||
Ending point: Dout_0io[0] / SP
|
||||
The start point is clocked by C14M [rising] (rise=0.000 fall=34.920 period=69.841) on pin CK
|
||||
The end point is clocked by C14M [falling] (rise=0.000 fall=34.920 period=69.841) on pin SCLK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
----------------------------------------------------------------------------------
|
||||
S[2] FD1S3AX Q Out 1.350 1.350 r -
|
||||
S[2] Net - - - - 48
|
||||
S_RNII9DO1_2[1] ORCALUT4 B In 0.000 1.350 r -
|
||||
S_RNII9DO1_2[1] ORCALUT4 Z Out 1.317 2.667 r -
|
||||
N_576_i Net - - - - 18
|
||||
Dout_0io[0] OFS1P3DX SP In 0.000 2.667 r -
|
||||
==================================================================================
|
||||
|
||||
|
||||
|
||||
|
||||
====================================
|
||||
Detailed Report for Clock: System
|
||||
====================================
|
||||
|
||||
|
||||
|
||||
Starting Points with Worst Slack
|
||||
********************************
|
||||
|
||||
Starting Arrival
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
-----------------------------------------------------------------------------------------
|
||||
ufmefb.EFBInst_0 System EFB WBACKO wb_ack 0.000 67.088
|
||||
ufmefb.EFBInst_0 System EFB WBDATO0 wb_dato[0] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO2 wb_dato[2] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO3 wb_dato[3] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO4 wb_dato[4] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO5 wb_dato[5] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO6 wb_dato[6] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO7 wb_dato[7] 0.000 69.313
|
||||
=========================================================================================
|
||||
|
||||
|
||||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------------------------------
|
||||
RWMask[0] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[1] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[2] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[3] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[4] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[5] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[6] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[7] System FD1P3AX SP N_88 69.369 67.088
|
||||
LEDEN System FD1P3AX SP un1_LEDEN_0_sqmuxa_1_i_0[0] 69.369 67.736
|
||||
wb_cyc_stb System FD1P3AX SP N_104 69.369 67.736
|
||||
====================================================================================================
|
||||
|
||||
|
||||
|
||||
Worst Path Information
|
||||
***********************
|
||||
|
||||
|
||||
Path information for path number 1:
|
||||
Requested Period: 69.841
|
||||
- Setup time: 0.472
|
||||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
= Required time: 69.369
|
||||
|
||||
- Propagation time: 2.282
|
||||
- Clock delay at starting point: 0.000 (ideal)
|
||||
- Estimated clock delay at start point: -0.000
|
||||
= Slack (non-critical) : 67.088
|
||||
|
||||
Number of logic level(s): 2
|
||||
Starting point: ufmefb.EFBInst_0 / WBACKO
|
||||
Ending point: RWMask[0] / SP
|
||||
The start point is clocked by System [rising]
|
||||
The end point is clocked by C14M [rising] (rise=0.000 fall=34.920 period=69.841) on pin CK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
------------------------------------------------------------------------------------------------------
|
||||
ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 r -
|
||||
wb_ack Net - - - - 5
|
||||
un1_RWMask_0_sqmuxa_1_i_0_RNO[0] ORCALUT4 A In 0.000 0.000 r -
|
||||
un1_RWMask_0_sqmuxa_1_i_0_RNO[0] ORCALUT4 Z Out 1.017 1.017 r -
|
||||
un1_RWMask_0_sqmuxa_1_i_a2_0_1[0] Net - - - - 1
|
||||
un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 D In 0.000 1.017 r -
|
||||
un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 Z Out 1.265 2.282 r -
|
||||
N_88 Net - - - - 8
|
||||
RWMask[0] FD1P3AX SP In 0.000 2.282 r -
|
||||
======================================================================================================
|
||||
|
||||
|
||||
|
||||
##### END OF TIMING REPORT #####]
|
||||
|
||||
Timing exceptions that could not be applied
|
||||
|
||||
Finished final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 210MB peak: 211MB)
|
||||
|
||||
|
||||
Finished timing report (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 210MB peak: 211MB)
|
||||
|
||||
---------------------------------------
|
||||
Resource Usage Report
|
||||
Part: lcmxo2_1200hc-4
|
||||
|
||||
Register bits: 111 of 1280 (9%)
|
||||
PIC Latch: 0
|
||||
I/O cells: 70
|
||||
|
||||
|
||||
Details:
|
||||
BB: 8
|
||||
CCU2D: 9
|
||||
EFB: 1
|
||||
FD1P3AX: 48
|
||||
FD1P3IX: 1
|
||||
FD1S3AX: 22
|
||||
FD1S3IX: 4
|
||||
GSR: 1
|
||||
IB: 22
|
||||
IFS1P3DX: 1
|
||||
INV: 1
|
||||
OB: 40
|
||||
OFS1P3BX: 6
|
||||
OFS1P3DX: 27
|
||||
OFS1P3IX: 2
|
||||
ORCALUT4: 221
|
||||
PUR: 1
|
||||
VHI: 2
|
||||
VLO: 2
|
||||
Mapper successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 78MB peak: 211MB)
|
||||
|
||||
Process took 0h:00m:06s realtime, 0h:00m:04s cputime
|
||||
# Thu Sep 21 05:34:44 2023
|
||||
|
||||
###########################################################]
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
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|
||||
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</HEAD>
|
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<PRE><A name="Map_Twr"></A><B><U><big>Map TRACE Report</big></U></B>
|
||||
|
||||
Loading design for application trce from file ram2e_lcmxo2_1200hc_impl1_map.ncd.
|
||||
Design name: RAM2E
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-1200HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.44.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
Setup and Hold Report
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
<A name="Map_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454</big></U></B>
|
||||
Thu Sep 21 05:34:48 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
<A name="mtw1_set_ri"></A><B><U><big>Report Information</big></U></B>
|
||||
------------------
|
||||
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2E_LCMXO2_1200HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1_map.ncd RAM2E_LCMXO2_1200HC_impl1.prf
|
||||
Design file: ram2e_lcmxo2_1200hc_impl1_map.ncd
|
||||
Preference file: ram2e_lcmxo2_1200hc_impl1.prf
|
||||
Device,speed: LCMXO2-1200HC,4
|
||||
Report level: verbose report, limited to 1 item per preference
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
<A name="mtw1_set_ps"></A><B><U><big>Preference Summary</big></U></B>
|
||||
|
||||
<LI><A href='#map_twr_pref_0_0' Target='right'>FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)</A></LI> 1491 items scored, 0 timing errors detected.
|
||||
Report: 87.268MHz is the maximum frequency for this preference.
|
||||
|
||||
BLOCK ASYNCPATHS
|
||||
BLOCK RESETPATHS
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
================================================================================
|
||||
<A name="map_twr_pref_0_0"></A>Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
|
||||
1491 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 58.471ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q FS[11] (from C14M_c +)
|
||||
Destination: FF Data in nRWE_0io (to C14M_c +)
|
||||
|
||||
Delay: 11.306ns (30.3% logic, 69.7% route), 7 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
11.306ns physical path delay SLICE_3 to nRWE_MGIOL meets
|
||||
69.930ns delay constraint less
|
||||
0.153ns DO_SET requirement (totaling 69.777ns) by 58.471ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path SLICE_3 to nRWE_MGIOL:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.452 SLICE_3.CLK to SLICE_3.Q0 SLICE_3 (from C14M_c)
|
||||
ROUTE 19 e 1.234 SLICE_3.Q0 to SLICE_64.A1 FS[11]
|
||||
CTOF_DEL --- 0.495 SLICE_64.A1 to SLICE_64.F1 SLICE_64
|
||||
ROUTE 4 e 1.234 SLICE_64.F1 to SLICE_97.D0 N_577
|
||||
CTOF_DEL --- 0.495 SLICE_97.D0 to SLICE_97.F0 SLICE_97
|
||||
ROUTE 3 e 1.234 SLICE_97.F0 to SLICE_75.D1 N_489
|
||||
CTOF_DEL --- 0.495 SLICE_75.D1 to SLICE_75.F1 SLICE_75
|
||||
ROUTE 3 e 0.480 SLICE_75.F1 to SLICE_75.A0 N_628
|
||||
CTOF_DEL --- 0.495 SLICE_75.A0 to SLICE_75.F0 SLICE_75
|
||||
ROUTE 2 e 1.234 SLICE_75.F0 to SLICE_71.C1 N_640
|
||||
CTOF_DEL --- 0.495 SLICE_71.C1 to SLICE_71.F1 SLICE_71
|
||||
ROUTE 1 e 1.234 SLICE_71.F1 to SLICE_115.A0 un1_nCS61_1_i
|
||||
CTOF_DEL --- 0.495 SLICE_115.A0 to SLICE_115.F0 SLICE_115
|
||||
ROUTE 1 e 1.234 SLICE_115.F0 to *WE_MGIOL.OPOS nRWE_r_0 (to C14M_c)
|
||||
--------
|
||||
11.306 (30.3% logic, 69.7% route), 7 logic levels.
|
||||
|
||||
Report: 87.268MHz is the maximum frequency for this preference.
|
||||
|
||||
<A name="mtw1_set_rs"></A><B><U><big>Report Summary</big></U></B>
|
||||
--------------
|
||||
----------------------------------------------------------------------------
|
||||
Preference | Constraint| Actual|Levels
|
||||
----------------------------------------------------------------------------
|
||||
| | |
|
||||
FREQUENCY PORT "C14M" 14.300000 MHz ; | 14.300 MHz| 87.268 MHz| 7
|
||||
| | |
|
||||
----------------------------------------------------------------------------
|
||||
|
||||
|
||||
All preferences were met.
|
||||
|
||||
|
||||
<A name="mtw1_set_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
|
||||
------------------------
|
||||
|
||||
Found 1 clocks:
|
||||
|
||||
Clock Domain: C14M_c Source: C14M.PAD Loads: 84
|
||||
Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
|
||||
|
||||
|
||||
<A name="mtw1_set_ts"></A><B><U><big>Timing summary (Setup):</big></U></B>
|
||||
---------------
|
||||
|
||||
Timing errors: 0 Score: 0
|
||||
Cumulative negative slack: 0
|
||||
|
||||
Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
<A name="Map_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454</big></U></B>
|
||||
Thu Sep 21 05:34:49 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
<A name="mtw1_hold_ri"></A><B><U><big>Report Information</big></U></B>
|
||||
------------------
|
||||
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2E_LCMXO2_1200HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1_map.ncd RAM2E_LCMXO2_1200HC_impl1.prf
|
||||
Design file: ram2e_lcmxo2_1200hc_impl1_map.ncd
|
||||
Preference file: ram2e_lcmxo2_1200hc_impl1.prf
|
||||
Device,speed: LCMXO2-1200HC,M
|
||||
Report level: verbose report, limited to 1 item per preference
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
<A name="mtw1_hold_ps"></A><B><U><big>Preference Summary</big></U></B>
|
||||
|
||||
<LI><A href='#map_twr_pref_1_0' Target='right'>FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)</A></LI> 1491 items scored, 0 timing errors detected.
|
||||
|
||||
BLOCK ASYNCPATHS
|
||||
BLOCK RESETPATHS
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
================================================================================
|
||||
<A name="map_twr_pref_1_0"></A>Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
|
||||
1491 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 0.447ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q FS[0] (from C14M_c +)
|
||||
Destination: FF Data in FS[0] (to C14M_c +)
|
||||
|
||||
Delay: 0.434ns (53.9% logic, 46.1% route), 2 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
0.434ns physical path delay SLICE_0 to SLICE_0 meets
|
||||
-0.013ns DIN_HLD and
|
||||
0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path SLICE_0 to SLICE_0:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.133 SLICE_0.CLK to SLICE_0.Q1 SLICE_0 (from C14M_c)
|
||||
ROUTE 5 e 0.199 SLICE_0.Q1 to SLICE_0.A1 FS[0]
|
||||
CTOF_DEL --- 0.101 SLICE_0.A1 to SLICE_0.F1 SLICE_0
|
||||
ROUTE 1 e 0.001 SLICE_0.F1 to SLICE_0.DI1 FS_s[0] (to C14M_c)
|
||||
--------
|
||||
0.434 (53.9% logic, 46.1% route), 2 logic levels.
|
||||
|
||||
<A name="mtw1_hold_rs"></A><B><U><big>Report Summary</big></U></B>
|
||||
--------------
|
||||
----------------------------------------------------------------------------
|
||||
Preference(MIN Delays) | Constraint| Actual|Levels
|
||||
----------------------------------------------------------------------------
|
||||
| | |
|
||||
FREQUENCY PORT "C14M" 14.300000 MHz ; | -| -| 2
|
||||
| | |
|
||||
----------------------------------------------------------------------------
|
||||
|
||||
|
||||
All preferences were met.
|
||||
|
||||
|
||||
<A name="mtw1_hold_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
|
||||
------------------------
|
||||
|
||||
Found 1 clocks:
|
||||
|
||||
Clock Domain: C14M_c Source: C14M.PAD Loads: 84
|
||||
Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
|
||||
|
||||
|
||||
<A name="mtw1_hold_ts"></A><B><U><big>Timing summary (Hold):</big></U></B>
|
||||
---------------
|
||||
|
||||
Timing errors: 0 Score: 0
|
||||
Cumulative negative slack: 0
|
||||
|
||||
Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage)
|
||||
|
||||
|
||||
|
||||
<A name="mtw1_ts"></A><B><U><big>Timing summary (Setup and Hold):</big></U></B>
|
||||
---------------
|
||||
|
||||
Timing errors: 0 (setup), 0 (hold)
|
||||
Score: 0 (setup), 0 (hold)
|
||||
Cumulative negative slack: 0 (0+0)
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
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|
|||
Loading design for application iotiming from file ram2e_lcmxo2_1200hc_impl1.ncd.
|
||||
Design name: RAM2E
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-1200HC
|
||||
Package: TQFP100
|
||||
Performance: 5
|
||||
Package Status: Final Version 1.44.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
Loading design for application iotiming from file ram2e_lcmxo2_1200hc_impl1.ncd.
|
||||
Design name: RAM2E
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-1200HC
|
||||
Package: TQFP100
|
||||
Performance: 6
|
||||
Package Status: Final Version 1.44.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
Loading design for application iotiming from file ram2e_lcmxo2_1200hc_impl1.ncd.
|
||||
Design name: RAM2E
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-1200HC
|
||||
Package: TQFP100
|
||||
Performance: M
|
||||
Package Status: Final Version 1.44.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
// Design: RAM2E
|
||||
// Package: TQFP100
|
||||
// ncd File: ram2e_lcmxo2_1200hc_impl1.ncd
|
||||
// Version: Diamond (64-bit) 3.12.1.454
|
||||
// Written on Thu Sep 21 05:35:11 2023
|
||||
// M: Minimum Performance Grade
|
||||
// iotiming RAM2E_LCMXO2_1200HC_impl1.ncd RAM2E_LCMXO2_1200HC_impl1.prf -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml
|
||||
|
||||
I/O Timing Report (All units are in ns)
|
||||
|
||||
Worst Case Results across Performance Grades (M, 6, 5, 4):
|
||||
|
||||
// Input Setup and Hold Times
|
||||
|
||||
Port Clock Edge Setup Performance_Grade Hold Performance_Grade
|
||||
----------------------------------------------------------------------
|
||||
Ain[0] C14M R -0.231 M 2.350 4
|
||||
Ain[1] C14M R 1.429 4 0.543 4
|
||||
Ain[2] C14M R 1.518 4 0.412 4
|
||||
Ain[3] C14M R -0.231 M 2.350 4
|
||||
Ain[4] C14M R 0.212 4 1.560 4
|
||||
Ain[5] C14M R 0.742 4 1.110 4
|
||||
Ain[6] C14M R 0.469 4 1.329 4
|
||||
Ain[7] C14M R 1.416 4 0.531 4
|
||||
Din[0] C14M R 8.327 4 1.958 4
|
||||
Din[1] C14M R 5.826 4 2.521 4
|
||||
Din[2] C14M R 6.539 4 2.135 4
|
||||
Din[3] C14M R 5.849 4 2.648 4
|
||||
Din[4] C14M R 7.061 4 2.095 4
|
||||
Din[5] C14M R 6.295 4 2.894 4
|
||||
Din[6] C14M R 4.991 4 2.892 4
|
||||
Din[7] C14M R 6.416 4 2.971 4
|
||||
PHI1 C14M R 1.151 4 4.842 4
|
||||
RD[0] C14M F -0.266 M 3.107 4
|
||||
RD[1] C14M F -0.248 M 3.183 4
|
||||
RD[2] C14M F -0.105 M 2.610 4
|
||||
RD[3] C14M F -0.243 M 3.107 4
|
||||
RD[4] C14M F 0.103 4 2.201 4
|
||||
RD[5] C14M F -0.092 M 2.192 4
|
||||
RD[6] C14M F -0.084 M 1.756 4
|
||||
RD[7] C14M F -0.092 M 2.661 4
|
||||
nC07X C14M R -0.316 M 2.625 4
|
||||
nEN80 C14M R 5.220 4 0.032 M
|
||||
nWE C14M R -0.093 M 2.033 4
|
||||
nWE80 C14M R 1.630 4 0.329 6
|
||||
|
||||
|
||||
// Clock to Output Delay
|
||||
|
||||
Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
|
||||
------------------------------------------------------------------------
|
||||
BA[0] C14M R 10.424 4 3.355 M
|
||||
BA[1] C14M R 10.424 4 3.355 M
|
||||
CKE C14M R 10.424 4 3.355 M
|
||||
DQMH C14M R 10.404 4 3.362 M
|
||||
DQML C14M R 10.404 4 3.362 M
|
||||
Dout[0] C14M F 10.750 4 3.634 M
|
||||
Dout[1] C14M F 10.750 4 3.634 M
|
||||
Dout[2] C14M F 10.739 4 3.628 M
|
||||
Dout[3] C14M F 10.750 4 3.634 M
|
||||
Dout[4] C14M F 10.739 4 3.628 M
|
||||
Dout[5] C14M F 10.739 4 3.628 M
|
||||
Dout[6] C14M F 10.750 4 3.634 M
|
||||
Dout[7] C14M F 10.750 4 3.634 M
|
||||
LED C14M R 21.299 4 8.576 M
|
||||
RA[0] C14M R 12.236 4 3.758 M
|
||||
RA[10] C14M R 10.490 4 3.360 M
|
||||
RA[11] C14M R 10.424 4 3.355 M
|
||||
RA[1] C14M R 10.490 4 3.360 M
|
||||
RA[2] C14M R 10.490 4 3.360 M
|
||||
RA[3] C14M R 11.808 4 3.656 M
|
||||
RA[4] C14M R 10.490 4 3.360 M
|
||||
RA[5] C14M R 10.490 4 3.360 M
|
||||
RA[6] C14M R 10.490 4 3.360 M
|
||||
RA[7] C14M R 10.490 4 3.360 M
|
||||
RA[8] C14M R 10.490 4 3.360 M
|
||||
RA[9] C14M R 10.490 4 3.360 M
|
||||
Vout[0] C14M F 11.348 4 3.872 M
|
||||
Vout[1] C14M F 11.434 4 3.871 M
|
||||
Vout[2] C14M F 11.348 4 3.872 M
|
||||
Vout[3] C14M F 11.434 4 3.871 M
|
||||
Vout[4] C14M F 11.348 4 3.872 M
|
||||
Vout[5] C14M F 11.348 4 3.872 M
|
||||
Vout[6] C14M F 11.434 4 3.871 M
|
||||
Vout[7] C14M F 11.434 4 3.871 M
|
||||
nCAS C14M R 10.424 4 3.355 M
|
||||
nCS C14M R 10.424 4 3.355 M
|
||||
nDOE C14M R 14.217 4 4.353 M
|
||||
nRAS C14M R 10.424 4 3.355 M
|
||||
nRWE C14M R 10.424 4 3.355 M
|
||||
WARNING: you must also run trce with hold speed: 4
|
||||
WARNING: you must also run trce with hold speed: 6
|
||||
WARNING: you must also run trce with setup speed: M
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
SCUBA, Version Diamond (64-bit) 3.12.1.454
|
||||
Wed Sep 20 04:45:58 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
BEGIN SCUBA Module Synthesis
|
||||
|
||||
Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 14.4 -ufm -ufm_ebr 190 -mem_size 321 -memfile ../RAM2E-LCMXO2.mem -memformat hex -wb -dev 1200
|
||||
Circuit name : REFB
|
||||
Module type : efb
|
||||
Module Version : 1.2
|
||||
Ports :
|
||||
Inputs : wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i[7:0], wb_dat_i[7:0]
|
||||
Outputs : wb_dat_o[7:0], wb_ack_o, wbc_ufm_irq
|
||||
I/O buffer : not inserted
|
||||
EDIF output : REFB.edn
|
||||
Verilog output : REFB.v
|
||||
Verilog template : REFB_tmpl.v
|
||||
Verilog purpose : for synthesis and simulation
|
||||
Bus notation : big endian
|
||||
Report output : REFB.srp
|
||||
Estimated Resource Usage:
|
||||
|
||||
END SCUBA Module Synthesis
|
||||
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<userSetting name="//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml" version="Diamond (64-bit) 3.12.1.454" date="Thu Sep 21 05:35:49 2023" vendor="Lattice Semiconductor Corporation" >
|
||||
</userSetting>
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!DOCTYPE Report>
|
||||
<ReportView version="2.0">
|
||||
<Implement name="impl1">
|
||||
<ToolReport id="tooldec" path="" status="0"/>
|
||||
<ToolReport id="toolhle_genhierarchy" path="Y:/Repos/RAM2E/CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html" status="1"/>
|
||||
<ToolReport id="toolpio" path="" status="2"/>
|
||||
<ToolReport id="toolsso" path="" status="2"/>
|
||||
</Implement>
|
||||
</ReportView>
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
[General]
|
||||
PAR.auto_tasks=PARTrace, IOTiming
|
||||
Map.auto_tasks=MapTrace, MapVerilogSimFile
|
||||
Export.auto_tasks=IBIS, TimingSimFileVlg, Bitgen, Jedecgen
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<BaliProject version="3.2" title="RAM2E_LCMXO2_640HC" device="LCMXO2-640HC-4TG100C" default_implementation="impl1">
|
||||
<Options/>
|
||||
<Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
|
||||
<Options def_top="RAM2E" top="RAM2E"/>
|
||||
<Source name="../RAM2E-LCMXO2.v" type="Verilog" type_short="Verilog">
|
||||
<Options top_module="RAM2E"/>
|
||||
</Source>
|
||||
<Source name="REFB.v" type="Verilog" type_short="Verilog">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="../RAM2E-LCMXO2.lpf" type="Logic Preference" type_short="LPF">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="../RAM2E.sdc" type="Synplify Design Constraints File" type_short="SDC">
|
||||
<Options/>
|
||||
</Source>
|
||||
</Implementation>
|
||||
<Strategy name="Strategy1" file="RAM2E_LCMXO2_640HC1.sty"/>
|
||||
</BaliProject>
|
||||
|
|
@ -0,0 +1,205 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!DOCTYPE strategy>
|
||||
<Strategy version="1.0" predefined="0" description="" label="Strategy1">
|
||||
<Property name="PROP_BD_CmdLineArgs" value="" time="0"/>
|
||||
<Property name="PROP_BD_EdfHardtimer" value="Enable" time="0"/>
|
||||
<Property name="PROP_BD_EdfInBusNameConv" value="None" time="0"/>
|
||||
<Property name="PROP_BD_EdfInLibPath" value="" time="0"/>
|
||||
<Property name="PROP_BD_EdfInRemLoc" value="Off" time="0"/>
|
||||
<Property name="PROP_BD_EdfMemPath" value="" time="0"/>
|
||||
<Property name="PROP_BD_ParSearchPath" value="" time="0"/>
|
||||
<Property name="PROP_BIT_AddressBitGen" value="Increment" time="0"/>
|
||||
<Property name="PROP_BIT_AllowReadBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_ByteWideBitMirror" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_CapReadBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_ConModBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_CreateBitFile" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_DisRAMResBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_DisableUESBitgen" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_DonePinBitGen" value="Pullup" time="0"/>
|
||||
<Property name="PROP_BIT_DoneSigBitGen" value="4" time="0"/>
|
||||
<Property name="PROP_BIT_EnIOBitGen" value="TriStateDuringReConfig" time="0"/>
|
||||
<Property name="PROP_BIT_EnIntOscBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_ExtClockBitGen" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_GSREnableBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_GSRRelOnBitGen" value="DoneIn" time="0"/>
|
||||
<Property name="PROP_BIT_GranTimBitGen" value="0" time="0"/>
|
||||
<Property name="PROP_BIT_IOTriRelBitGen" value="Cycle 2" time="0"/>
|
||||
<Property name="PROP_BIT_JTAGEnableBitGen" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_LenBitsBitGen" value="24" time="0"/>
|
||||
<Property name="PROP_BIT_MIFFileBitGen" value="" time="0"/>
|
||||
<Property name="PROP_BIT_NoHeader" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_OutFormatBitGen" value="Bit File (Binary)" time="0"/>
|
||||
<Property name="PROP_BIT_OutFormatBitGen_REF" value="" time="0"/>
|
||||
<Property name="PROP_BIT_OutFormatPromGen" value="Intel Hex 32-bit" time="0"/>
|
||||
<Property name="PROP_BIT_ParityCheckBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_ReadBackBitGen" value="Flash" time="0"/>
|
||||
<Property name="PROP_BIT_ReadCaptureBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_RemZeroFramesBitGen" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_RunDRCBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_SearchPthBitGen" value="" time="0"/>
|
||||
<Property name="PROP_BIT_StartUpClkBitGen" value="Cclk" time="0"/>
|
||||
<Property name="PROP_BIT_SynchIOBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_SysClockConBitGen" value="Reset" time="0"/>
|
||||
<Property name="PROP_BIT_SysConBitGen" value="Reset" time="0"/>
|
||||
<Property name="PROP_BIT_WaitStTimBitGen" value="5" time="0"/>
|
||||
<Property name="PROP_IOTIMING_AllSpeed" value="False" time="0"/>
|
||||
<Property name="PROP_LST_AllowDUPMod" value="False" time="0"/>
|
||||
<Property name="PROP_LST_CarryChain" value="True" time="0"/>
|
||||
<Property name="PROP_LST_CarryChainLength" value="0" time="0"/>
|
||||
<Property name="PROP_LST_CmdLineArgs" value="" time="0"/>
|
||||
<Property name="PROP_LST_DSPStyle" value="DSP" time="0"/>
|
||||
<Property name="PROP_LST_DSPUtil" value="100" time="0"/>
|
||||
<Property name="PROP_LST_DecodeUnreachableStates" value="False" time="0"/>
|
||||
<Property name="PROP_LST_DisableDistRam" value="False" time="0"/>
|
||||
<Property name="PROP_LST_EBRUtil" value="100" time="0"/>
|
||||
<Property name="PROP_LST_EdfFrequency" value="200" time="0"/>
|
||||
<Property name="PROP_LST_EdfHardtimer" value="Enable" time="0"/>
|
||||
<Property name="PROP_LST_EdfInLibPath" value="" time="0"/>
|
||||
<Property name="PROP_LST_EdfInRemLoc" value="Off" time="0"/>
|
||||
<Property name="PROP_LST_EdfMemPath" value="" time="0"/>
|
||||
<Property name="PROP_LST_FIXGATEDCLKS" value="True" time="0"/>
|
||||
<Property name="PROP_LST_FSMEncodeStyle" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_ForceGSRInfer" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_IOInsertion" value="True" time="0"/>
|
||||
<Property name="PROP_LST_InterFileDump" value="False" time="0"/>
|
||||
<Property name="PROP_LST_LoopLimit" value="1950" time="0"/>
|
||||
<Property name="PROP_LST_MaxFanout" value="1000" time="0"/>
|
||||
<Property name="PROP_LST_MuxStyle" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_NumCriticalPaths" value="3" time="0"/>
|
||||
<Property name="PROP_LST_OptimizeGoal" value="Balanced" time="0"/>
|
||||
<Property name="PROP_LST_PropagatConst" value="True" time="0"/>
|
||||
<Property name="PROP_LST_RAMStyle" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_ROMStyle" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_RemoveDupRegs" value="True" time="0"/>
|
||||
<Property name="PROP_LST_ResolvedMixedDrivers" value="False" time="0"/>
|
||||
<Property name="PROP_LST_ResourceShare" value="True" time="0"/>
|
||||
<Property name="PROP_LST_UseIOReg" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_UseLPF" value="True" time="0"/>
|
||||
<Property name="PROP_LST_VHDL2008" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
|
||||
<Property name="PROP_MAPSTA_AutoTiming" value="True" time="0"/>
|
||||
<Property name="PROP_MAPSTA_CheckUnconstrainedConns" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_CheckUnconstrainedPaths" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_FullName" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_NumUnconstrainedPaths" value="0" time="0"/>
|
||||
<Property name="PROP_MAPSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
|
||||
<Property name="PROP_MAPSTA_RouteEstAlogtithm" value="0" time="0"/>
|
||||
<Property name="PROP_MAPSTA_RptAsynTimLoop" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_WordCasePaths" value="1" time="0"/>
|
||||
<Property name="PROP_MAP_IgnorePreErr" value="True" time="0"/>
|
||||
<Property name="PROP_MAP_MAPIORegister" value="Auto" time="0"/>
|
||||
<Property name="PROP_MAP_MAPInferGSR" value="True" time="0"/>
|
||||
<Property name="PROP_MAP_MapModArgs" value="" time="0"/>
|
||||
<Property name="PROP_MAP_OvermapDevice" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_PackLogMapDes" value="0" time="0"/>
|
||||
<Property name="PROP_MAP_RegRetiming" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_SigCrossRef" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_SymCrossRef" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_TimingDriven" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_TimingDrivenNodeRep" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_TimingDrivenPack" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
|
||||
<Property name="PROP_PARSTA_AutoTiming" value="True" time="0"/>
|
||||
<Property name="PROP_PARSTA_CheckUnconstrainedConns" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_CheckUnconstrainedPaths" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_FullName" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_NumUnconstrainedPaths" value="0" time="0"/>
|
||||
<Property name="PROP_PARSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
|
||||
<Property name="PROP_PARSTA_RptAsynTimLoop" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_SpeedForHoldAnalysis" value="m" time="0"/>
|
||||
<Property name="PROP_PARSTA_SpeedForSetupAnalysis" value="default" time="0"/>
|
||||
<Property name="PROP_PARSTA_WordCasePaths" value="10" time="0"/>
|
||||
<Property name="PROP_PAR_CrDlyStFileParDes" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_DisableTDParDes" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_EffortParDes" value="5" time="0"/>
|
||||
<Property name="PROP_PAR_MultiSeedSortMode" value="Worst Slack" time="0"/>
|
||||
<Property name="PROP_PAR_NewRouteParDes" value="NBR" time="0"/>
|
||||
<Property name="PROP_PAR_PARClockSkew" value="Off" time="0"/>
|
||||
<Property name="PROP_PAR_PARModArgs" value="" time="0"/>
|
||||
<Property name="PROP_PAR_ParMultiNodeList" value="" time="0"/>
|
||||
<Property name="PROP_PAR_ParRunPlaceOnly" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_PlcIterParDes" value="1" time="0"/>
|
||||
<Property name="PROP_PAR_PlcStCostTblParDes" value="1" time="0"/>
|
||||
<Property name="PROP_PAR_PrefErrorOut" value="True" time="0"/>
|
||||
<Property name="PROP_PAR_RemoveDir" value="True" time="0"/>
|
||||
<Property name="PROP_PAR_RouteDlyRedParDes" value="0" time="0"/>
|
||||
<Property name="PROP_PAR_RoutePassParDes" value="6" time="0"/>
|
||||
<Property name="PROP_PAR_RouteResOptParDes" value="0" time="0"/>
|
||||
<Property name="PROP_PAR_RoutingCDP" value="0" time="0"/>
|
||||
<Property name="PROP_PAR_RoutingCDR" value="0" time="0"/>
|
||||
<Property name="PROP_PAR_RunParWithTrce" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_RunTimeReduction" value="True" time="0"/>
|
||||
<Property name="PROP_PAR_SaveBestRsltParDes" value="1" time="0"/>
|
||||
<Property name="PROP_PAR_StopZero" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_parHold" value="On" time="0"/>
|
||||
<Property name="PROP_PAR_parPathBased" value="Off" time="0"/>
|
||||
<Property name="PROP_PRE_CmdLineArgs" value="" time="0"/>
|
||||
<Property name="PROP_PRE_EdfArrayBoundsCase" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfAutoResOfRam" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfClockDomainCross" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfDSPAcrossHie" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfFullCase" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfIgnoreRamRWCol" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfMissConstraint" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfNetFanout" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfParaCase" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfReencodeFSM" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfResSharing" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfTimingViolation" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfUseSafeFSM" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfVlog2001" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynComArea" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynCritcal" value="3" time="0"/>
|
||||
<Property name="PROP_PRE_VSynFSM" value="Auto" time="0"/>
|
||||
<Property name="PROP_PRE_VSynFreq" value="200" time="0"/>
|
||||
<Property name="PROP_PRE_VSynGSR" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_VSynGatedClk" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_VSynIOPad" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_VSynOutNetForm" value="None" time="0"/>
|
||||
<Property name="PROP_PRE_VSynOutPref" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynRepClkFreq" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynRetime" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynTimSum" value="10" time="0"/>
|
||||
<Property name="PROP_PRE_VSynTransform" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSyninpd" value="0" time="0"/>
|
||||
<Property name="PROP_PRE_VSynoutd" value="0" time="0"/>
|
||||
<Property name="PROP_SYN_ClockConversion" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_CmdLineArgs" value="" time="0"/>
|
||||
<Property name="PROP_SYN_DisableRegisterRep" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfAllowDUPMod" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfArea" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfArrangeVHDLFiles" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfDefEnumEncode" value="Default" time="0"/>
|
||||
<Property name="PROP_SYN_EdfFanout" value="1000" time="0"/>
|
||||
<Property name="PROP_SYN_EdfFrequency" value="100" time="0"/>
|
||||
<Property name="PROP_SYN_EdfGSR" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfInsertIO" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfNumCritPath" value="" time="0"/>
|
||||
<Property name="PROP_SYN_EdfNumStartEnd" value="" time="0"/>
|
||||
<Property name="PROP_SYN_EdfOutNetForm" value="None" time="0"/>
|
||||
<Property name="PROP_SYN_EdfPushTirstates" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfResSharing" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfRunRetiming" value="Pipelining Only" time="0"/>
|
||||
<Property name="PROP_SYN_EdfSymFSM" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfUnconsClk" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfVerilogInput" value="Verilog 2001" time="0"/>
|
||||
<Property name="PROP_SYN_ExportSetting" value="No" time="0"/>
|
||||
<Property name="PROP_SYN_LibPath" value="" time="0"/>
|
||||
<Property name="PROP_SYN_ResolvedMixedDrivers" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_UpdateCompilePtTimData" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_UseLPF" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_VHDL2008" value="False" time="0"/>
|
||||
<Property name="PROP_THERMAL_DefaultFreq" value="0" time="0"/>
|
||||
<Property name="PROP_TIM_MaxDelSimDes" value="" time="0"/>
|
||||
<Property name="PROP_TIM_MinSpeedGrade" value="False" time="0"/>
|
||||
<Property name="PROP_TIM_ModPreSimDes" value="" time="0"/>
|
||||
<Property name="PROP_TIM_NegStupHldTim" value="True" time="0"/>
|
||||
<Property name="PROP_TIM_TimSimGenPUR" value="True" time="0"/>
|
||||
<Property name="PROP_TIM_TimSimGenX" value="False" time="0"/>
|
||||
<Property name="PROP_TIM_TimSimHierSep" value="" time="0"/>
|
||||
<Property name="PROP_TIM_TransportModeOfPathDelay" value="False" time="0"/>
|
||||
<Property name="PROP_TIM_TrgtSpeedGrade" value="" time="0"/>
|
||||
<Property name="PROP_TIM_WriteVerboseNetlist" value="False" time="0"/>
|
||||
<Property name="PROP_TMCHK_EnableCheck" value="True" time="0"/>
|
||||
</Strategy>
|
||||
|
|
@ -0,0 +1,70 @@
|
|||
<HTML>
|
||||
<HEAD><TITLE>Lattice TCL Log</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="pn230921045933"></A><B><U><big>pn230921045933</big></U></B>
|
||||
#Start recording tcl command: 9/21/2023 04:58:25
|
||||
#Project Location: //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC; Project name: RAM2E_LCMXO2_640HC
|
||||
prj_project open "//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC.ldf"
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
#Stop recording: 9/21/2023 04:59:33
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
|
|
@ -0,0 +1,550 @@
|
|||
(edif REFB
|
||||
(edifVersion 2 0 0)
|
||||
(edifLevel 0)
|
||||
(keywordMap (keywordLevel 0))
|
||||
(status
|
||||
(written
|
||||
(timestamp 2023 9 20 4 17 14)
|
||||
(program "SCUBA" (version "Diamond (64-bit) 3.12.1.454"))))
|
||||
(comment "C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 14.4 -ufm -ufm_ebr 190 -mem_size 1 -memfile ../RAM2E-LCMXO2.mem -memformat hex -wb -dev 640 ")
|
||||
(library ORCLIB
|
||||
(edifLevel 0)
|
||||
(technology
|
||||
(numberDefinition))
|
||||
(cell VHI
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port Z
|
||||
(direction OUTPUT)))))
|
||||
(cell VLO
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port Z
|
||||
(direction OUTPUT)))))
|
||||
(cell EFB
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port WBCLKI
|
||||
(direction INPUT))
|
||||
(port WBRSTI
|
||||
(direction INPUT))
|
||||
(port WBCYCI
|
||||
(direction INPUT))
|
||||
(port WBSTBI
|
||||
(direction INPUT))
|
||||
(port WBWEI
|
||||
(direction INPUT))
|
||||
(port WBADRI7
|
||||
(direction INPUT))
|
||||
(port WBADRI6
|
||||
(direction INPUT))
|
||||
(port WBADRI5
|
||||
(direction INPUT))
|
||||
(port WBADRI4
|
||||
(direction INPUT))
|
||||
(port WBADRI3
|
||||
(direction INPUT))
|
||||
(port WBADRI2
|
||||
(direction INPUT))
|
||||
(port WBADRI1
|
||||
(direction INPUT))
|
||||
(port WBADRI0
|
||||
(direction INPUT))
|
||||
(port WBDATI7
|
||||
(direction INPUT))
|
||||
(port WBDATI6
|
||||
(direction INPUT))
|
||||
(port WBDATI5
|
||||
(direction INPUT))
|
||||
(port WBDATI4
|
||||
(direction INPUT))
|
||||
(port WBDATI3
|
||||
(direction INPUT))
|
||||
(port WBDATI2
|
||||
(direction INPUT))
|
||||
(port WBDATI1
|
||||
(direction INPUT))
|
||||
(port WBDATI0
|
||||
(direction INPUT))
|
||||
(port PLL0DATI7
|
||||
(direction INPUT))
|
||||
(port PLL0DATI6
|
||||
(direction INPUT))
|
||||
(port PLL0DATI5
|
||||
(direction INPUT))
|
||||
(port PLL0DATI4
|
||||
(direction INPUT))
|
||||
(port PLL0DATI3
|
||||
(direction INPUT))
|
||||
(port PLL0DATI2
|
||||
(direction INPUT))
|
||||
(port PLL0DATI1
|
||||
(direction INPUT))
|
||||
(port PLL0DATI0
|
||||
(direction INPUT))
|
||||
(port PLL0ACKI
|
||||
(direction INPUT))
|
||||
(port PLL1DATI7
|
||||
(direction INPUT))
|
||||
(port PLL1DATI6
|
||||
(direction INPUT))
|
||||
(port PLL1DATI5
|
||||
(direction INPUT))
|
||||
(port PLL1DATI4
|
||||
(direction INPUT))
|
||||
(port PLL1DATI3
|
||||
(direction INPUT))
|
||||
(port PLL1DATI2
|
||||
(direction INPUT))
|
||||
(port PLL1DATI1
|
||||
(direction INPUT))
|
||||
(port PLL1DATI0
|
||||
(direction INPUT))
|
||||
(port PLL1ACKI
|
||||
(direction INPUT))
|
||||
(port I2C1SCLI
|
||||
(direction INPUT))
|
||||
(port I2C1SDAI
|
||||
(direction INPUT))
|
||||
(port I2C2SCLI
|
||||
(direction INPUT))
|
||||
(port I2C2SDAI
|
||||
(direction INPUT))
|
||||
(port SPISCKI
|
||||
(direction INPUT))
|
||||
(port SPIMISOI
|
||||
(direction INPUT))
|
||||
(port SPIMOSII
|
||||
(direction INPUT))
|
||||
(port SPISCSN
|
||||
(direction INPUT))
|
||||
(port TCCLKI
|
||||
(direction INPUT))
|
||||
(port TCRSTN
|
||||
(direction INPUT))
|
||||
(port TCIC
|
||||
(direction INPUT))
|
||||
(port UFMSN
|
||||
(direction INPUT))
|
||||
(port WBDATO7
|
||||
(direction OUTPUT))
|
||||
(port WBDATO6
|
||||
(direction OUTPUT))
|
||||
(port WBDATO5
|
||||
(direction OUTPUT))
|
||||
(port WBDATO4
|
||||
(direction OUTPUT))
|
||||
(port WBDATO3
|
||||
(direction OUTPUT))
|
||||
(port WBDATO2
|
||||
(direction OUTPUT))
|
||||
(port WBDATO1
|
||||
(direction OUTPUT))
|
||||
(port WBDATO0
|
||||
(direction OUTPUT))
|
||||
(port WBACKO
|
||||
(direction OUTPUT))
|
||||
(port PLLCLKO
|
||||
(direction OUTPUT))
|
||||
(port PLLRSTO
|
||||
(direction OUTPUT))
|
||||
(port PLL0STBO
|
||||
(direction OUTPUT))
|
||||
(port PLL1STBO
|
||||
(direction OUTPUT))
|
||||
(port PLLWEO
|
||||
(direction OUTPUT))
|
||||
(port PLLADRO4
|
||||
(direction OUTPUT))
|
||||
(port PLLADRO3
|
||||
(direction OUTPUT))
|
||||
(port PLLADRO2
|
||||
(direction OUTPUT))
|
||||
(port PLLADRO1
|
||||
(direction OUTPUT))
|
||||
(port PLLADRO0
|
||||
(direction OUTPUT))
|
||||
(port PLLDATO7
|
||||
(direction OUTPUT))
|
||||
(port PLLDATO6
|
||||
(direction OUTPUT))
|
||||
(port PLLDATO5
|
||||
(direction OUTPUT))
|
||||
(port PLLDATO4
|
||||
(direction OUTPUT))
|
||||
(port PLLDATO3
|
||||
(direction OUTPUT))
|
||||
(port PLLDATO2
|
||||
(direction OUTPUT))
|
||||
(port PLLDATO1
|
||||
(direction OUTPUT))
|
||||
(port PLLDATO0
|
||||
(direction OUTPUT))
|
||||
(port I2C1SCLO
|
||||
(direction OUTPUT))
|
||||
(port I2C1SCLOEN
|
||||
(direction OUTPUT))
|
||||
(port I2C1SDAO
|
||||
(direction OUTPUT))
|
||||
(port I2C1SDAOEN
|
||||
(direction OUTPUT))
|
||||
(port I2C2SCLO
|
||||
(direction OUTPUT))
|
||||
(port I2C2SCLOEN
|
||||
(direction OUTPUT))
|
||||
(port I2C2SDAO
|
||||
(direction OUTPUT))
|
||||
(port I2C2SDAOEN
|
||||
(direction OUTPUT))
|
||||
(port I2C1IRQO
|
||||
(direction OUTPUT))
|
||||
(port I2C2IRQO
|
||||
(direction OUTPUT))
|
||||
(port SPISCKO
|
||||
(direction OUTPUT))
|
||||
(port SPISCKEN
|
||||
(direction OUTPUT))
|
||||
(port SPIMISOO
|
||||
(direction OUTPUT))
|
||||
(port SPIMISOEN
|
||||
(direction OUTPUT))
|
||||
(port SPIMOSIO
|
||||
(direction OUTPUT))
|
||||
(port SPIMOSIEN
|
||||
(direction OUTPUT))
|
||||
(port SPIMCSN7
|
||||
(direction OUTPUT))
|
||||
(port SPIMCSN6
|
||||
(direction OUTPUT))
|
||||
(port SPIMCSN5
|
||||
(direction OUTPUT))
|
||||
(port SPIMCSN4
|
||||
(direction OUTPUT))
|
||||
(port SPIMCSN3
|
||||
(direction OUTPUT))
|
||||
(port SPIMCSN2
|
||||
(direction OUTPUT))
|
||||
(port SPIMCSN1
|
||||
(direction OUTPUT))
|
||||
(port SPIMCSN0
|
||||
(direction OUTPUT))
|
||||
(port SPICSNEN
|
||||
(direction OUTPUT))
|
||||
(port SPIIRQO
|
||||
(direction OUTPUT))
|
||||
(port TCINT
|
||||
(direction OUTPUT))
|
||||
(port TCOC
|
||||
(direction OUTPUT))
|
||||
(port WBCUFMIRQ
|
||||
(direction OUTPUT))
|
||||
(port CFGWAKE
|
||||
(direction OUTPUT))
|
||||
(port CFGSTDBY
|
||||
(direction OUTPUT)))))
|
||||
(cell REFB
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port wb_clk_i
|
||||
(direction INPUT))
|
||||
(port wb_rst_i
|
||||
(direction INPUT))
|
||||
(port wb_cyc_i
|
||||
(direction INPUT))
|
||||
(port wb_stb_i
|
||||
(direction INPUT))
|
||||
(port wb_we_i
|
||||
(direction INPUT))
|
||||
(port (array (rename wb_adr_i "wb_adr_i(7:0)") 8)
|
||||
(direction INPUT))
|
||||
(port (array (rename wb_dat_i "wb_dat_i(7:0)") 8)
|
||||
(direction INPUT))
|
||||
(port (array (rename wb_dat_o "wb_dat_o(7:0)") 8)
|
||||
(direction OUTPUT))
|
||||
(port wb_ack_o
|
||||
(direction OUTPUT))
|
||||
(port wbc_ufm_irq
|
||||
(direction OUTPUT)))
|
||||
(property NGD_DRC_MASK (integer 1))
|
||||
(contents
|
||||
(instance scuba_vhi_inst
|
||||
(viewRef view1
|
||||
(cellRef VHI)))
|
||||
(instance scuba_vlo_inst
|
||||
(viewRef view1
|
||||
(cellRef VLO)))
|
||||
(instance EFBInst_0
|
||||
(viewRef view1
|
||||
(cellRef EFB))
|
||||
(property UFM_INIT_FILE_FORMAT
|
||||
(string "HEX"))
|
||||
(property UFM_INIT_FILE_NAME
|
||||
(string "../RAM2E-LCMXO2.mem"))
|
||||
(property UFM_INIT_ALL_ZEROS
|
||||
(string "DISABLED"))
|
||||
(property UFM_INIT_START_PAGE
|
||||
(string "190"))
|
||||
(property UFM_INIT_PAGES
|
||||
(string "1"))
|
||||
(property DEV_DENSITY
|
||||
(string "640L"))
|
||||
(property EFB_UFM
|
||||
(string "ENABLED"))
|
||||
(property TC_ICAPTURE
|
||||
(string "DISABLED"))
|
||||
(property TC_OVERFLOW
|
||||
(string "DISABLED"))
|
||||
(property TC_ICR_INT
|
||||
(string "OFF"))
|
||||
(property TC_OCR_INT
|
||||
(string "OFF"))
|
||||
(property TC_OV_INT
|
||||
(string "OFF"))
|
||||
(property TC_TOP_SEL
|
||||
(string "OFF"))
|
||||
(property TC_RESETN
|
||||
(string "ENABLED"))
|
||||
(property TC_OC_MODE
|
||||
(string "TOGGLE"))
|
||||
(property TC_OCR_SET
|
||||
(string "32767"))
|
||||
(property TC_TOP_SET
|
||||
(string "65535"))
|
||||
(property GSR
|
||||
(string "ENABLED"))
|
||||
(property TC_CCLK_SEL
|
||||
(string "1"))
|
||||
(property TC_MODE
|
||||
(string "CTCM"))
|
||||
(property TC_SCLK_SEL
|
||||
(string "PCLOCK"))
|
||||
(property EFB_TC_PORTMODE
|
||||
(string "WB"))
|
||||
(property EFB_TC
|
||||
(string "DISABLED"))
|
||||
(property SPI_WAKEUP
|
||||
(string "DISABLED"))
|
||||
(property SPI_INTR_RXOVR
|
||||
(string "DISABLED"))
|
||||
(property SPI_INTR_TXOVR
|
||||
(string "DISABLED"))
|
||||
(property SPI_INTR_RXRDY
|
||||
(string "DISABLED"))
|
||||
(property SPI_INTR_TXRDY
|
||||
(string "DISABLED"))
|
||||
(property SPI_SLAVE_HANDSHAKE
|
||||
(string "DISABLED"))
|
||||
(property SPI_PHASE_ADJ
|
||||
(string "DISABLED"))
|
||||
(property SPI_CLK_INV
|
||||
(string "DISABLED"))
|
||||
(property SPI_LSB_FIRST
|
||||
(string "DISABLED"))
|
||||
(property SPI_CLK_DIVIDER
|
||||
(string "1"))
|
||||
(property SPI_MODE
|
||||
(string "MASTER"))
|
||||
(property EFB_SPI
|
||||
(string "DISABLED"))
|
||||
(property I2C2_WAKEUP
|
||||
(string "DISABLED"))
|
||||
(property I2C2_GEN_CALL
|
||||
(string "DISABLED"))
|
||||
(property I2C2_CLK_DIVIDER
|
||||
(string "1"))
|
||||
(property I2C2_BUS_PERF
|
||||
(string "100kHz"))
|
||||
(property I2C2_SLAVE_ADDR
|
||||
(string "0b1000010"))
|
||||
(property I2C2_ADDRESSING
|
||||
(string "7BIT"))
|
||||
(property EFB_I2C2
|
||||
(string "DISABLED"))
|
||||
(property I2C1_WAKEUP
|
||||
(string "DISABLED"))
|
||||
(property I2C1_GEN_CALL
|
||||
(string "DISABLED"))
|
||||
(property I2C1_CLK_DIVIDER
|
||||
(string "1"))
|
||||
(property I2C1_BUS_PERF
|
||||
(string "100kHz"))
|
||||
(property I2C1_SLAVE_ADDR
|
||||
(string "0b1000001"))
|
||||
(property I2C1_ADDRESSING
|
||||
(string "7BIT"))
|
||||
(property EFB_I2C1
|
||||
(string "DISABLED"))
|
||||
(property EFB_WB_CLK_FREQ
|
||||
(string "14.4")))
|
||||
(net scuba_vhi
|
||||
(joined
|
||||
(portRef Z (instanceRef scuba_vhi_inst))
|
||||
(portRef UFMSN (instanceRef EFBInst_0))))
|
||||
(net scuba_vlo
|
||||
(joined
|
||||
(portRef Z (instanceRef scuba_vlo_inst))
|
||||
(portRef PLL1DATI7 (instanceRef EFBInst_0))
|
||||
(portRef PLL1DATI6 (instanceRef EFBInst_0))
|
||||
(portRef PLL1DATI5 (instanceRef EFBInst_0))
|
||||
(portRef PLL1DATI4 (instanceRef EFBInst_0))
|
||||
(portRef PLL1DATI3 (instanceRef EFBInst_0))
|
||||
(portRef PLL1DATI2 (instanceRef EFBInst_0))
|
||||
(portRef PLL1DATI1 (instanceRef EFBInst_0))
|
||||
(portRef PLL1DATI0 (instanceRef EFBInst_0))
|
||||
(portRef PLL1ACKI (instanceRef EFBInst_0))
|
||||
(portRef PLL0DATI7 (instanceRef EFBInst_0))
|
||||
(portRef PLL0DATI6 (instanceRef EFBInst_0))
|
||||
(portRef PLL0DATI5 (instanceRef EFBInst_0))
|
||||
(portRef PLL0DATI4 (instanceRef EFBInst_0))
|
||||
(portRef PLL0DATI3 (instanceRef EFBInst_0))
|
||||
(portRef PLL0DATI2 (instanceRef EFBInst_0))
|
||||
(portRef PLL0DATI1 (instanceRef EFBInst_0))
|
||||
(portRef PLL0DATI0 (instanceRef EFBInst_0))
|
||||
(portRef PLL0ACKI (instanceRef EFBInst_0))
|
||||
(portRef TCIC (instanceRef EFBInst_0))
|
||||
(portRef TCRSTN (instanceRef EFBInst_0))
|
||||
(portRef TCCLKI (instanceRef EFBInst_0))
|
||||
(portRef SPISCSN (instanceRef EFBInst_0))
|
||||
(portRef SPIMOSII (instanceRef EFBInst_0))
|
||||
(portRef SPIMISOI (instanceRef EFBInst_0))
|
||||
(portRef SPISCKI (instanceRef EFBInst_0))
|
||||
(portRef I2C2SDAI (instanceRef EFBInst_0))
|
||||
(portRef I2C2SCLI (instanceRef EFBInst_0))
|
||||
(portRef I2C1SDAI (instanceRef EFBInst_0))
|
||||
(portRef I2C1SCLI (instanceRef EFBInst_0))))
|
||||
(net wbc_ufm_irq
|
||||
(joined
|
||||
(portRef wbc_ufm_irq)
|
||||
(portRef WBCUFMIRQ (instanceRef EFBInst_0))))
|
||||
(net wb_ack_o
|
||||
(joined
|
||||
(portRef wb_ack_o)
|
||||
(portRef WBACKO (instanceRef EFBInst_0))))
|
||||
(net wb_dat_o7
|
||||
(joined
|
||||
(portRef (member wb_dat_o 0))
|
||||
(portRef WBDATO7 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_o6
|
||||
(joined
|
||||
(portRef (member wb_dat_o 1))
|
||||
(portRef WBDATO6 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_o5
|
||||
(joined
|
||||
(portRef (member wb_dat_o 2))
|
||||
(portRef WBDATO5 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_o4
|
||||
(joined
|
||||
(portRef (member wb_dat_o 3))
|
||||
(portRef WBDATO4 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_o3
|
||||
(joined
|
||||
(portRef (member wb_dat_o 4))
|
||||
(portRef WBDATO3 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_o2
|
||||
(joined
|
||||
(portRef (member wb_dat_o 5))
|
||||
(portRef WBDATO2 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_o1
|
||||
(joined
|
||||
(portRef (member wb_dat_o 6))
|
||||
(portRef WBDATO1 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_o0
|
||||
(joined
|
||||
(portRef (member wb_dat_o 7))
|
||||
(portRef WBDATO0 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_i7
|
||||
(joined
|
||||
(portRef (member wb_dat_i 0))
|
||||
(portRef WBDATI7 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_i6
|
||||
(joined
|
||||
(portRef (member wb_dat_i 1))
|
||||
(portRef WBDATI6 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_i5
|
||||
(joined
|
||||
(portRef (member wb_dat_i 2))
|
||||
(portRef WBDATI5 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_i4
|
||||
(joined
|
||||
(portRef (member wb_dat_i 3))
|
||||
(portRef WBDATI4 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_i3
|
||||
(joined
|
||||
(portRef (member wb_dat_i 4))
|
||||
(portRef WBDATI3 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_i2
|
||||
(joined
|
||||
(portRef (member wb_dat_i 5))
|
||||
(portRef WBDATI2 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_i1
|
||||
(joined
|
||||
(portRef (member wb_dat_i 6))
|
||||
(portRef WBDATI1 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_i0
|
||||
(joined
|
||||
(portRef (member wb_dat_i 7))
|
||||
(portRef WBDATI0 (instanceRef EFBInst_0))))
|
||||
(net wb_adr_i7
|
||||
(joined
|
||||
(portRef (member wb_adr_i 0))
|
||||
(portRef WBADRI7 (instanceRef EFBInst_0))))
|
||||
(net wb_adr_i6
|
||||
(joined
|
||||
(portRef (member wb_adr_i 1))
|
||||
(portRef WBADRI6 (instanceRef EFBInst_0))))
|
||||
(net wb_adr_i5
|
||||
(joined
|
||||
(portRef (member wb_adr_i 2))
|
||||
(portRef WBADRI5 (instanceRef EFBInst_0))))
|
||||
(net wb_adr_i4
|
||||
(joined
|
||||
(portRef (member wb_adr_i 3))
|
||||
(portRef WBADRI4 (instanceRef EFBInst_0))))
|
||||
(net wb_adr_i3
|
||||
(joined
|
||||
(portRef (member wb_adr_i 4))
|
||||
(portRef WBADRI3 (instanceRef EFBInst_0))))
|
||||
(net wb_adr_i2
|
||||
(joined
|
||||
(portRef (member wb_adr_i 5))
|
||||
(portRef WBADRI2 (instanceRef EFBInst_0))))
|
||||
(net wb_adr_i1
|
||||
(joined
|
||||
(portRef (member wb_adr_i 6))
|
||||
(portRef WBADRI1 (instanceRef EFBInst_0))))
|
||||
(net wb_adr_i0
|
||||
(joined
|
||||
(portRef (member wb_adr_i 7))
|
||||
(portRef WBADRI0 (instanceRef EFBInst_0))))
|
||||
(net wb_we_i
|
||||
(joined
|
||||
(portRef wb_we_i)
|
||||
(portRef WBWEI (instanceRef EFBInst_0))))
|
||||
(net wb_stb_i
|
||||
(joined
|
||||
(portRef wb_stb_i)
|
||||
(portRef WBSTBI (instanceRef EFBInst_0))))
|
||||
(net wb_cyc_i
|
||||
(joined
|
||||
(portRef wb_cyc_i)
|
||||
(portRef WBCYCI (instanceRef EFBInst_0))))
|
||||
(net wb_rst_i
|
||||
(joined
|
||||
(portRef wb_rst_i)
|
||||
(portRef WBRSTI (instanceRef EFBInst_0))))
|
||||
(net wb_clk_i
|
||||
(joined
|
||||
(portRef wb_clk_i)
|
||||
(portRef WBCLKI (instanceRef EFBInst_0))))))))
|
||||
(design REFB
|
||||
(cellRef REFB
|
||||
(libraryRef ORCLIB)))
|
||||
)
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<DiamondModule name="REFB" module="EFB" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2023 09 20 04:17:25.073" version="1.2" type="Module" synthesis="synplify" source_format="Verilog">
|
||||
<Package>
|
||||
<File name="REFB.lpc" type="lpc" modified="2023 09 20 04:17:14.513"/>
|
||||
<File name="REFB.v" type="top_level_verilog" modified="2023 09 20 04:17:14.586"/>
|
||||
<File name="REFB_tmpl.v" type="template_verilog" modified="2023 09 20 04:17:14.586"/>
|
||||
</Package>
|
||||
</DiamondModule>
|
||||
|
|
@ -0,0 +1,141 @@
|
|||
[Device]
|
||||
Family=machxo2
|
||||
PartType=LCMXO2-640HC
|
||||
PartName=LCMXO2-640HC-4TG100C
|
||||
SpeedGrade=4
|
||||
Package=TQFP100
|
||||
OperatingCondition=COM
|
||||
Status=S
|
||||
|
||||
[IP]
|
||||
VendorName=Lattice Semiconductor Corporation
|
||||
CoreType=LPM
|
||||
CoreStatus=Demo
|
||||
CoreName=EFB
|
||||
CoreRevision=1.2
|
||||
ModuleName=REFB
|
||||
SourceFormat=Verilog HDL
|
||||
ParameterFileVersion=1.0
|
||||
Date=09/20/2023
|
||||
Time=04:17:14
|
||||
|
||||
[Parameters]
|
||||
Verilog=1
|
||||
VHDL=0
|
||||
EDIF=1
|
||||
Destination=Synplicity
|
||||
Expression=BusA(0 to 7)
|
||||
Order=Big Endian [MSB:LSB]
|
||||
IO=0
|
||||
freq=
|
||||
i2c1=0
|
||||
i2c1config=0
|
||||
i2c1_addr=7-Bit Addressing
|
||||
i2c1_ce=0
|
||||
i2c1_freq=100
|
||||
i2c1_sa=10000
|
||||
i2c1_we=0
|
||||
i2c2=0
|
||||
i2c2_addr=7-Bit Addressing
|
||||
i2c2_ce=0
|
||||
i2c2_freq=100
|
||||
i2c2_sa=10000
|
||||
i2c2_we=0
|
||||
ufm_addr=7-Bit Addressing
|
||||
ufm_sa=10000
|
||||
pll=0
|
||||
pll_cnt=1
|
||||
spi=0
|
||||
spi_clkinv=0
|
||||
spi_cs=1
|
||||
spi_en=0
|
||||
spi_freq=1
|
||||
spi_lsb=0
|
||||
spi_mode=Slave
|
||||
spi_ib=0
|
||||
spi_ph=0
|
||||
spi_hs=0
|
||||
spi_rxo=0
|
||||
spi_rxr=0
|
||||
spi_txo=0
|
||||
spi_txr=0
|
||||
spi_we=0
|
||||
static_tc=Static
|
||||
tc=0
|
||||
tc_clkinv=Positive
|
||||
tc_ctr=1
|
||||
tc_div=1
|
||||
tc_ipcap=0
|
||||
tc_mode=CTCM
|
||||
tc_ocr=32767
|
||||
tc_oflow=1
|
||||
tc_o=TOGGLE
|
||||
tc_opcomp=0
|
||||
tc_osc=0
|
||||
tc_sa_oflow=0
|
||||
tc_top=65535
|
||||
ufm=1
|
||||
ufm0=0
|
||||
ufm1=0
|
||||
ufm2=0
|
||||
ufm3=0
|
||||
ufm_cfg0=0
|
||||
ufm_cfg1=0
|
||||
wb_clk_freq=14.4
|
||||
ufm_usage=SHARED_EBR_TAG
|
||||
ufm_ebr=190
|
||||
ufm_remain=
|
||||
mem_size=1
|
||||
ufm_start=
|
||||
ufm_init=mem
|
||||
memfile=../RAM2E-LCMXO2.mem
|
||||
ufm_dt=hex
|
||||
ufm0_ebr=
|
||||
mem_size0=1
|
||||
ufm0_init=0
|
||||
memfile0=
|
||||
ufm0_dt=hex
|
||||
ufm1_ebr=
|
||||
mem_size1=1
|
||||
ufm1_init=0
|
||||
memfile1=
|
||||
ufm1_dt=hex
|
||||
ufm2_ebr=
|
||||
mem_size2=1
|
||||
ufm2_init=0
|
||||
memfile2=
|
||||
ufm2_dt=hex
|
||||
ufm3_ebr=
|
||||
mem_size3=1
|
||||
ufm3_init=0
|
||||
memfile3=
|
||||
ufm3_dt=hex
|
||||
ufm_cfg0_ebr=
|
||||
mem_size_cfg0=1
|
||||
ufm_cfg0_init=0
|
||||
memfile_cfg0=
|
||||
ufm_cfg0_dt=hex
|
||||
ufm_cfg1_ebr=
|
||||
mem_size_cfg1=1
|
||||
ufm_cfg1_init=0
|
||||
memfile_cfg1=
|
||||
ufm_cfg1_dt=hex
|
||||
wb=1
|
||||
boot_option=Internal
|
||||
efb_ufm=0
|
||||
boot_option_internal=Single Boot
|
||||
internal_ufm0=0
|
||||
internal_ufm1=0
|
||||
efb_ufm_boot=
|
||||
tamperdr=0
|
||||
t_pwd=0
|
||||
t_lockflash=0
|
||||
t_manmode=0
|
||||
t_jtagport=0
|
||||
t_sspiport=0
|
||||
t_sic2port=0
|
||||
t_wbport=0
|
||||
t_portlock=0
|
||||
|
||||
[Command]
|
||||
cmd_line= -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 14.4 -ufm -ufm_ebr 190 -mem_size 1 -memfile ../RAM2E-LCMXO2.mem -memformat hex -wb -dev 640
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
wb_clk_i i
|
||||
wb_rst_i i
|
||||
wb_cyc_i i
|
||||
wb_stb_i i
|
||||
wb_we_i i
|
||||
wb_adr_i[7] i
|
||||
wb_adr_i[6] i
|
||||
wb_adr_i[5] i
|
||||
wb_adr_i[4] i
|
||||
wb_adr_i[3] i
|
||||
wb_adr_i[2] i
|
||||
wb_adr_i[1] i
|
||||
wb_adr_i[0] i
|
||||
wb_dat_i[7] i
|
||||
wb_dat_i[6] i
|
||||
wb_dat_i[5] i
|
||||
wb_dat_i[4] i
|
||||
wb_dat_i[3] i
|
||||
wb_dat_i[2] i
|
||||
wb_dat_i[1] i
|
||||
wb_dat_i[0] i
|
||||
wb_dat_o[7] o
|
||||
wb_dat_o[6] o
|
||||
wb_dat_o[5] o
|
||||
wb_dat_o[4] o
|
||||
wb_dat_o[3] o
|
||||
wb_dat_o[2] o
|
||||
wb_dat_o[1] o
|
||||
wb_dat_o[0] o
|
||||
wb_ack_o o
|
||||
wbc_ufm_irq o
|
||||
|
|
@ -0,0 +1 @@
|
|||
REFB.v
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
SCUBA, Version Diamond (64-bit) 3.12.1.454
|
||||
Wed Sep 20 04:17:14 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 14.4 -ufm -ufm_ebr 190 -mem_size 1 -memfile ../RAM2E-LCMXO2.mem -memformat hex -wb -dev 640
|
||||
Circuit name : REFB
|
||||
Module type : efb
|
||||
Module Version : 1.2
|
||||
Ports :
|
||||
Inputs : wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i[7:0], wb_dat_i[7:0]
|
||||
Outputs : wb_dat_o[7:0], wb_ack_o, wbc_ufm_irq
|
||||
I/O buffer : not inserted
|
||||
EDIF output : REFB.edn
|
||||
Verilog output : REFB.v
|
||||
Verilog template : REFB_tmpl.v
|
||||
Verilog purpose : for synthesis and simulation
|
||||
Bus notation : big endian
|
||||
Report output : REFB.srp
|
||||
Element Usage :
|
||||
EFB : 1
|
||||
Estimated Resource Usage:
|
||||
Binary file not shown.
|
|
@ -0,0 +1,113 @@
|
|||
/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 */
|
||||
/* Module Version: 1.2 */
|
||||
/* C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 14.4 -ufm -ufm_ebr 190 -mem_size 1 -memfile ../RAM2E-LCMXO2.mem -memformat hex -wb -dev 640 */
|
||||
/* Wed Sep 20 04:17:14 2023 */
|
||||
|
||||
|
||||
`timescale 1 ns / 1 ps
|
||||
module REFB (wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i,
|
||||
wb_dat_i, wb_dat_o, wb_ack_o, wbc_ufm_irq)/* synthesis NGD_DRC_MASK=1 */;
|
||||
input wire wb_clk_i;
|
||||
input wire wb_rst_i;
|
||||
input wire wb_cyc_i;
|
||||
input wire wb_stb_i;
|
||||
input wire wb_we_i;
|
||||
input wire [7:0] wb_adr_i;
|
||||
input wire [7:0] wb_dat_i;
|
||||
output wire [7:0] wb_dat_o;
|
||||
output wire wb_ack_o;
|
||||
output wire wbc_ufm_irq;
|
||||
|
||||
wire scuba_vhi;
|
||||
wire scuba_vlo;
|
||||
|
||||
VHI scuba_vhi_inst (.Z(scuba_vhi));
|
||||
|
||||
VLO scuba_vlo_inst (.Z(scuba_vlo));
|
||||
|
||||
defparam EFBInst_0.UFM_INIT_FILE_FORMAT = "HEX" ;
|
||||
defparam EFBInst_0.UFM_INIT_FILE_NAME = "../RAM2E-LCMXO2.mem" ;
|
||||
defparam EFBInst_0.UFM_INIT_ALL_ZEROS = "DISABLED" ;
|
||||
defparam EFBInst_0.UFM_INIT_START_PAGE = 190 ;
|
||||
defparam EFBInst_0.UFM_INIT_PAGES = 1 ;
|
||||
defparam EFBInst_0.DEV_DENSITY = "640L" ;
|
||||
defparam EFBInst_0.EFB_UFM = "ENABLED" ;
|
||||
defparam EFBInst_0.TC_ICAPTURE = "DISABLED" ;
|
||||
defparam EFBInst_0.TC_OVERFLOW = "DISABLED" ;
|
||||
defparam EFBInst_0.TC_ICR_INT = "OFF" ;
|
||||
defparam EFBInst_0.TC_OCR_INT = "OFF" ;
|
||||
defparam EFBInst_0.TC_OV_INT = "OFF" ;
|
||||
defparam EFBInst_0.TC_TOP_SEL = "OFF" ;
|
||||
defparam EFBInst_0.TC_RESETN = "ENABLED" ;
|
||||
defparam EFBInst_0.TC_OC_MODE = "TOGGLE" ;
|
||||
defparam EFBInst_0.TC_OCR_SET = 32767 ;
|
||||
defparam EFBInst_0.TC_TOP_SET = 65535 ;
|
||||
defparam EFBInst_0.GSR = "ENABLED" ;
|
||||
defparam EFBInst_0.TC_CCLK_SEL = 1 ;
|
||||
defparam EFBInst_0.TC_MODE = "CTCM" ;
|
||||
defparam EFBInst_0.TC_SCLK_SEL = "PCLOCK" ;
|
||||
defparam EFBInst_0.EFB_TC_PORTMODE = "WB" ;
|
||||
defparam EFBInst_0.EFB_TC = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_WAKEUP = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_INTR_RXOVR = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_INTR_TXOVR = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_INTR_RXRDY = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_INTR_TXRDY = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_SLAVE_HANDSHAKE = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_PHASE_ADJ = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_CLK_INV = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_LSB_FIRST = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_CLK_DIVIDER = 1 ;
|
||||
defparam EFBInst_0.SPI_MODE = "MASTER" ;
|
||||
defparam EFBInst_0.EFB_SPI = "DISABLED" ;
|
||||
defparam EFBInst_0.I2C2_WAKEUP = "DISABLED" ;
|
||||
defparam EFBInst_0.I2C2_GEN_CALL = "DISABLED" ;
|
||||
defparam EFBInst_0.I2C2_CLK_DIVIDER = 1 ;
|
||||
defparam EFBInst_0.I2C2_BUS_PERF = "100kHz" ;
|
||||
defparam EFBInst_0.I2C2_SLAVE_ADDR = "0b1000010" ;
|
||||
defparam EFBInst_0.I2C2_ADDRESSING = "7BIT" ;
|
||||
defparam EFBInst_0.EFB_I2C2 = "DISABLED" ;
|
||||
defparam EFBInst_0.I2C1_WAKEUP = "DISABLED" ;
|
||||
defparam EFBInst_0.I2C1_GEN_CALL = "DISABLED" ;
|
||||
defparam EFBInst_0.I2C1_CLK_DIVIDER = 1 ;
|
||||
defparam EFBInst_0.I2C1_BUS_PERF = "100kHz" ;
|
||||
defparam EFBInst_0.I2C1_SLAVE_ADDR = "0b1000001" ;
|
||||
defparam EFBInst_0.I2C1_ADDRESSING = "7BIT" ;
|
||||
defparam EFBInst_0.EFB_I2C1 = "DISABLED" ;
|
||||
defparam EFBInst_0.EFB_WB_CLK_FREQ = "14.4" ;
|
||||
EFB EFBInst_0 (.WBCLKI(wb_clk_i), .WBRSTI(wb_rst_i), .WBCYCI(wb_cyc_i),
|
||||
.WBSTBI(wb_stb_i), .WBWEI(wb_we_i), .WBADRI7(wb_adr_i[7]), .WBADRI6(wb_adr_i[6]),
|
||||
.WBADRI5(wb_adr_i[5]), .WBADRI4(wb_adr_i[4]), .WBADRI3(wb_adr_i[3]),
|
||||
.WBADRI2(wb_adr_i[2]), .WBADRI1(wb_adr_i[1]), .WBADRI0(wb_adr_i[0]),
|
||||
.WBDATI7(wb_dat_i[7]), .WBDATI6(wb_dat_i[6]), .WBDATI5(wb_dat_i[5]),
|
||||
.WBDATI4(wb_dat_i[4]), .WBDATI3(wb_dat_i[3]), .WBDATI2(wb_dat_i[2]),
|
||||
.WBDATI1(wb_dat_i[1]), .WBDATI0(wb_dat_i[0]), .PLL0DATI7(scuba_vlo),
|
||||
.PLL0DATI6(scuba_vlo), .PLL0DATI5(scuba_vlo), .PLL0DATI4(scuba_vlo),
|
||||
.PLL0DATI3(scuba_vlo), .PLL0DATI2(scuba_vlo), .PLL0DATI1(scuba_vlo),
|
||||
.PLL0DATI0(scuba_vlo), .PLL0ACKI(scuba_vlo), .PLL1DATI7(scuba_vlo),
|
||||
.PLL1DATI6(scuba_vlo), .PLL1DATI5(scuba_vlo), .PLL1DATI4(scuba_vlo),
|
||||
.PLL1DATI3(scuba_vlo), .PLL1DATI2(scuba_vlo), .PLL1DATI1(scuba_vlo),
|
||||
.PLL1DATI0(scuba_vlo), .PLL1ACKI(scuba_vlo), .I2C1SCLI(scuba_vlo),
|
||||
.I2C1SDAI(scuba_vlo), .I2C2SCLI(scuba_vlo), .I2C2SDAI(scuba_vlo),
|
||||
.SPISCKI(scuba_vlo), .SPIMISOI(scuba_vlo), .SPIMOSII(scuba_vlo),
|
||||
.SPISCSN(scuba_vlo), .TCCLKI(scuba_vlo), .TCRSTN(scuba_vlo), .TCIC(scuba_vlo),
|
||||
.UFMSN(scuba_vhi), .WBDATO7(wb_dat_o[7]), .WBDATO6(wb_dat_o[6]),
|
||||
.WBDATO5(wb_dat_o[5]), .WBDATO4(wb_dat_o[4]), .WBDATO3(wb_dat_o[3]),
|
||||
.WBDATO2(wb_dat_o[2]), .WBDATO1(wb_dat_o[1]), .WBDATO0(wb_dat_o[0]),
|
||||
.WBACKO(wb_ack_o), .PLLCLKO(), .PLLRSTO(), .PLL0STBO(), .PLL1STBO(),
|
||||
.PLLWEO(), .PLLADRO4(), .PLLADRO3(), .PLLADRO2(), .PLLADRO1(), .PLLADRO0(),
|
||||
.PLLDATO7(), .PLLDATO6(), .PLLDATO5(), .PLLDATO4(), .PLLDATO3(),
|
||||
.PLLDATO2(), .PLLDATO1(), .PLLDATO0(), .I2C1SCLO(), .I2C1SCLOEN(),
|
||||
.I2C1SDAO(), .I2C1SDAOEN(), .I2C2SCLO(), .I2C2SCLOEN(), .I2C2SDAO(),
|
||||
.I2C2SDAOEN(), .I2C1IRQO(), .I2C2IRQO(), .SPISCKO(), .SPISCKEN(),
|
||||
.SPIMISOO(), .SPIMISOEN(), .SPIMOSIO(), .SPIMOSIEN(), .SPIMCSN7(),
|
||||
.SPIMCSN6(), .SPIMCSN5(), .SPIMCSN4(), .SPIMCSN3(), .SPIMCSN2(),
|
||||
.SPIMCSN1(), .SPIMCSN0(), .SPICSNEN(), .SPIIRQO(), .TCINT(), .TCOC(),
|
||||
.WBCUFMIRQ(wbc_ufm_irq), .CFGWAKE(), .CFGSTDBY());
|
||||
|
||||
|
||||
|
||||
// exemplar begin
|
||||
// exemplar end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
Starting process: Module
|
||||
|
||||
Starting process:
|
||||
|
||||
SCUBA, Version Diamond (64-bit) 3.12.1.454
|
||||
Wed Sep 20 04:17:14 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
BEGIN SCUBA Module Synthesis
|
||||
|
||||
Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 14.4 -ufm -ufm_ebr 190 -mem_size 1 -memfile ../RAM2E-LCMXO2.mem -memformat hex -wb -dev 640
|
||||
Circuit name : REFB
|
||||
Module type : efb
|
||||
Module Version : 1.2
|
||||
Ports :
|
||||
Inputs : wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i[7:0], wb_dat_i[7:0]
|
||||
Outputs : wb_dat_o[7:0], wb_ack_o, wbc_ufm_irq
|
||||
I/O buffer : not inserted
|
||||
EDIF output : REFB.edn
|
||||
Verilog output : REFB.v
|
||||
Verilog template : REFB_tmpl.v
|
||||
Verilog purpose : for synthesis and simulation
|
||||
Bus notation : big endian
|
||||
Report output : REFB.srp
|
||||
Estimated Resource Usage:
|
||||
|
||||
END SCUBA Module Synthesis
|
||||
|
||||
File: REFB.lpc created.
|
||||
|
||||
|
||||
End process: completed successfully.
|
||||
|
||||
|
||||
Total Warnings: 0
|
||||
|
||||
Total Errors: 0
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.12.1.454 */
|
||||
/* Module Version: 1.2 */
|
||||
/* Wed Sep 20 04:17:14 2023 */
|
||||
|
||||
/* parameterized module instance */
|
||||
REFB __ (.wb_clk_i( ), .wb_rst_i( ), .wb_cyc_i( ), .wb_stb_i( ),
|
||||
.wb_we_i( ), .wb_adr_i( ), .wb_dat_i( ), .wb_dat_o( ), .wb_ack_o( ),
|
||||
.wbc_ufm_irq( ));
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,100 @@
|
|||
#!/usr/local/bin/wish
|
||||
|
||||
proc GetPlatform {} {
|
||||
global tcl_platform
|
||||
|
||||
set cpu $tcl_platform(machine)
|
||||
|
||||
switch $cpu {
|
||||
intel -
|
||||
i*86* {
|
||||
set cpu ix86
|
||||
}
|
||||
x86_64 {
|
||||
if {$tcl_platform(wordSize) == 4} {
|
||||
set cpu ix86
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
switch $tcl_platform(platform) {
|
||||
windows {
|
||||
if {$cpu == "amd64"} {
|
||||
# Do not check wordSize, win32-x64 is an IL32P64 platform.
|
||||
set cpu x86_64
|
||||
}
|
||||
if {$cpu == "x86_64"} {
|
||||
return "nt64"
|
||||
} else {
|
||||
return "nt"
|
||||
}
|
||||
}
|
||||
unix {
|
||||
if {$tcl_platform(os) == "Linux"} {
|
||||
if {$cpu == "x86_64"} {
|
||||
return "lin64"
|
||||
} else {
|
||||
return "lin"
|
||||
}
|
||||
} else {
|
||||
return "sol"
|
||||
}
|
||||
}
|
||||
}
|
||||
return "nt"
|
||||
}
|
||||
|
||||
proc GetCmdLine {lpcfile} {
|
||||
global Para
|
||||
|
||||
if [catch {open $lpcfile r} fileid] {
|
||||
puts "Cannot open $para_file file!"
|
||||
exit -1
|
||||
}
|
||||
|
||||
seek $fileid 0 start
|
||||
set default_match 0
|
||||
while {[gets $fileid line] >= 0} {
|
||||
if {[string first "\[Command\]" $line] == 0} {
|
||||
set default_match 1
|
||||
continue
|
||||
}
|
||||
if {[string first "\[" $line] == 0} {
|
||||
set default_match 0
|
||||
}
|
||||
if {$default_match == 1} {
|
||||
if [regexp {([^=]*)=(.*)} $line match parameter value] {
|
||||
if [regexp {([ |\t]*;)} $parameter match] {continue}
|
||||
if [regexp {(.*)[ |\t]*;} $value match temp] {
|
||||
set Para($parameter) $temp
|
||||
} else {
|
||||
set Para($parameter) $value
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
set default_match 0
|
||||
close $fileid
|
||||
|
||||
return $Para(cmd_line)
|
||||
}
|
||||
|
||||
set platformpath [GetPlatform]
|
||||
set Para(sbp_path) [file dirname [info script]]
|
||||
set Para(install_dir) $env(TOOLRTF)
|
||||
set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
|
||||
|
||||
set scuba "$Para(FPGAPath)/scuba"
|
||||
set modulename "REFB"
|
||||
set lang "verilog"
|
||||
set lpcfile "$Para(sbp_path)/$modulename.lpc"
|
||||
set arch "xo2c00"
|
||||
set cmd_line [GetCmdLine $lpcfile]
|
||||
set fdcfile "$Para(sbp_path)/$modulename.fdc"
|
||||
if {[file exists $fdcfile] == 0} {
|
||||
append scuba " " $cmd_line
|
||||
} else {
|
||||
append scuba " " $cmd_line " " -fdc " " \"$fdcfile\"
|
||||
}
|
||||
set Para(result) [catch {eval exec "$scuba"} msg]
|
||||
#puts $msg
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
#!/usr/local/bin/wish
|
||||
|
||||
proc GetPlatform {} {
|
||||
global tcl_platform
|
||||
|
||||
set cpu $tcl_platform(machine)
|
||||
|
||||
switch $cpu {
|
||||
intel -
|
||||
i*86* {
|
||||
set cpu ix86
|
||||
}
|
||||
x86_64 {
|
||||
if {$tcl_platform(wordSize) == 4} {
|
||||
set cpu ix86
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
switch $tcl_platform(platform) {
|
||||
windows {
|
||||
if {$cpu == "amd64"} {
|
||||
# Do not check wordSize, win32-x64 is an IL32P64 platform.
|
||||
set cpu x86_64
|
||||
}
|
||||
if {$cpu == "x86_64"} {
|
||||
return "nt64"
|
||||
} else {
|
||||
return "nt"
|
||||
}
|
||||
}
|
||||
unix {
|
||||
if {$tcl_platform(os) == "Linux"} {
|
||||
if {$cpu == "x86_64"} {
|
||||
return "lin64"
|
||||
} else {
|
||||
return "lin"
|
||||
}
|
||||
} else {
|
||||
return "sol"
|
||||
}
|
||||
}
|
||||
}
|
||||
return "nt"
|
||||
}
|
||||
|
||||
set platformpath [GetPlatform]
|
||||
set Para(sbp_path) [file dirname [info script]]
|
||||
set Para(install_dir) $env(TOOLRTF)
|
||||
set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
|
||||
set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]"
|
||||
|
||||
set Para(ModuleName) "REFB"
|
||||
set Para(Module) "EFB"
|
||||
set Para(libname) machxo2
|
||||
set Para(arch_name) xo2c00
|
||||
set Para(PartType) "LCMXO2-640HC"
|
||||
|
||||
set Para(tech_syn) machxo2
|
||||
set Para(tech_cae) machxo2
|
||||
set Para(Package) "TQFP100"
|
||||
set Para(SpeedGrade) "4"
|
||||
set Para(FMax) "100"
|
||||
set fdcfile "$Para(sbp_path)/$Para(ModuleName).fdc"
|
||||
|
||||
#edif2ngd
|
||||
set edif2ngd "$Para(FPGAPath)/edif2ngd"
|
||||
set Para(result) [catch {eval exec $edif2ngd -l $Para(libname) -d $Para(PartType) -nopropwarn $Para(ModuleName).edn $Para(ModuleName).ngo} msg]
|
||||
#puts $msg
|
||||
|
||||
#ngdbuild
|
||||
set ngdbuild "$Para(FPGAPath)/ngdbuild"
|
||||
set Para(result) [catch {eval exec $ngdbuild -addiobuf -dt -a $Para(arch_name) $Para(ModuleName).ngo $Para(ModuleName).ngd} msg]
|
||||
#puts $msg
|
||||
|
|
@ -0,0 +1,78 @@
|
|||
NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
|
||||
NOTE All Rights Reserved *
|
||||
NOTE DATE CREATED: Thu Sep 21 05:35:24 2023 *
|
||||
NOTE DESIGN NAME: RAM2E *
|
||||
NOTE DEVICE NAME: LCMXO2-640HC-4TQFP100 *
|
||||
NOTE PIN ASSIGNMENTS *
|
||||
NOTE PINS RD[0] : 36 : inout *
|
||||
NOTE PINS LED : 35 : out *
|
||||
NOTE PINS C14M : 62 : in *
|
||||
NOTE PINS DQMH : 49 : out *
|
||||
NOTE PINS DQML : 48 : out *
|
||||
NOTE PINS RD[7] : 43 : inout *
|
||||
NOTE PINS RD[6] : 42 : inout *
|
||||
NOTE PINS RD[5] : 41 : inout *
|
||||
NOTE PINS RD[4] : 40 : inout *
|
||||
NOTE PINS RD[3] : 39 : inout *
|
||||
NOTE PINS RD[2] : 38 : inout *
|
||||
NOTE PINS RD[1] : 37 : inout *
|
||||
NOTE PINS RA[11] : 59 : out *
|
||||
NOTE PINS RA[10] : 64 : out *
|
||||
NOTE PINS RA[9] : 63 : out *
|
||||
NOTE PINS RA[8] : 65 : out *
|
||||
NOTE PINS RA[7] : 67 : out *
|
||||
NOTE PINS RA[6] : 69 : out *
|
||||
NOTE PINS RA[5] : 71 : out *
|
||||
NOTE PINS RA[4] : 75 : out *
|
||||
NOTE PINS RA[3] : 74 : out *
|
||||
NOTE PINS RA[2] : 70 : out *
|
||||
NOTE PINS RA[1] : 68 : out *
|
||||
NOTE PINS RA[0] : 66 : out *
|
||||
NOTE PINS BA[1] : 60 : out *
|
||||
NOTE PINS BA[0] : 58 : out *
|
||||
NOTE PINS nRWE : 51 : out *
|
||||
NOTE PINS nCAS : 52 : out *
|
||||
NOTE PINS nRAS : 54 : out *
|
||||
NOTE PINS nCS : 57 : out *
|
||||
NOTE PINS CKE : 53 : out *
|
||||
NOTE PINS nVOE : 10 : out *
|
||||
NOTE PINS Vout[7] : 12 : out *
|
||||
NOTE PINS Vout[6] : 14 : out *
|
||||
NOTE PINS Vout[5] : 16 : out *
|
||||
NOTE PINS Vout[4] : 19 : out *
|
||||
NOTE PINS Vout[3] : 13 : out *
|
||||
NOTE PINS Vout[2] : 17 : out *
|
||||
NOTE PINS Vout[1] : 15 : out *
|
||||
NOTE PINS Vout[0] : 18 : out *
|
||||
NOTE PINS nDOE : 20 : out *
|
||||
NOTE PINS Dout[7] : 32 : out *
|
||||
NOTE PINS Dout[6] : 31 : out *
|
||||
NOTE PINS Dout[5] : 21 : out *
|
||||
NOTE PINS Dout[4] : 24 : out *
|
||||
NOTE PINS Dout[3] : 28 : out *
|
||||
NOTE PINS Dout[2] : 25 : out *
|
||||
NOTE PINS Dout[1] : 27 : out *
|
||||
NOTE PINS Dout[0] : 30 : out *
|
||||
NOTE PINS Din[7] : 87 : in *
|
||||
NOTE PINS Din[6] : 88 : in *
|
||||
NOTE PINS Din[5] : 99 : in *
|
||||
NOTE PINS Din[4] : 1 : in *
|
||||
NOTE PINS Din[3] : 9 : in *
|
||||
NOTE PINS Din[2] : 98 : in *
|
||||
NOTE PINS Din[1] : 97 : in *
|
||||
NOTE PINS Din[0] : 96 : in *
|
||||
NOTE PINS Ain[7] : 8 : in *
|
||||
NOTE PINS Ain[6] : 86 : in *
|
||||
NOTE PINS Ain[5] : 84 : in *
|
||||
NOTE PINS Ain[4] : 78 : in *
|
||||
NOTE PINS Ain[3] : 4 : in *
|
||||
NOTE PINS Ain[2] : 7 : in *
|
||||
NOTE PINS Ain[1] : 2 : in *
|
||||
NOTE PINS Ain[0] : 3 : in *
|
||||
NOTE PINS nC07X : 34 : in *
|
||||
NOTE PINS nEN80 : 82 : in *
|
||||
NOTE PINS nWE80 : 83 : in *
|
||||
NOTE PINS nWE : 29 : in *
|
||||
NOTE PINS PHI1 : 85 : in *
|
||||
NOTE CONFIGURATION MODE: NONE *
|
||||
NOTE COMPRESSION: on *
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
----------------------------------------------------------------------
|
||||
Report for cell RAM2E.verilog
|
||||
|
||||
Register bits: 111 of 640 (17%)
|
||||
PIC Latch: 0
|
||||
I/O cells: 70
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
BB 8 100.0
|
||||
CCU2D 9 100.0
|
||||
EFB 1 100.0
|
||||
FD1P3AX 48 100.0
|
||||
FD1P3IX 1 100.0
|
||||
FD1S3AX 22 100.0
|
||||
FD1S3IX 4 100.0
|
||||
GSR 1 100.0
|
||||
IB 22 100.0
|
||||
IFS1P3DX 1 100.0
|
||||
INV 1 100.0
|
||||
OB 40 100.0
|
||||
OFS1P3BX 6 100.0
|
||||
OFS1P3DX 27 100.0
|
||||
OFS1P3IX 2 100.0
|
||||
ORCALUT4 221 100.0
|
||||
PUR 1 100.0
|
||||
VHI 2 100.0
|
||||
VLO 2 100.0
|
||||
SUB MODULES
|
||||
REFB 1 100.0
|
||||
|
||||
TOTAL 420
|
||||
----------------------------------------------------------------------
|
||||
Report for cell REFB.netlist
|
||||
Instance path: ufmefb
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
EFB 1 100.0
|
||||
VHI 1 50.0
|
||||
VLO 1 50.0
|
||||
|
||||
TOTAL 3
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Thu Sep 21 05:35:20 2023
|
||||
|
||||
|
||||
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC -w -jedec -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf
|
||||
|
||||
Loading design for application Bitgen from file RAM2E_LCMXO2_640HC_impl1.ncd.
|
||||
Design name: RAM2E
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-640HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application Bitgen from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.39.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
|
||||
Running DRC.
|
||||
DRC detected 0 errors and 0 warnings.
|
||||
Reading Preference File from RAM2E_LCMXO2_640HC_impl1.prf.
|
||||
|
||||
Preference Summary:
|
||||
+---------------------------------+---------------------------------+
|
||||
| Preference | Current Setting |
|
||||
+---------------------------------+---------------------------------+
|
||||
| RamCfg | Reset** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MCCLK_FREQ | 2.08** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| CONFIG_SECURE | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| INBUF | ON** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| JTAG_PORT | ENABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SDM_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SLAVE_SPI_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MASTER_SPI_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| I2C_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MUX_CONFIGURATION_PORTS | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| CONFIGURATION | CFG** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| COMPRESS_CONFIG | ON** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MY_ASSP | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| ONE_TIME_PROGRAM | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| ENABLE_TRANSFR | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SHAREDEBRINIT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| BACKGROUND_RECONFIG | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
* Default setting.
|
||||
** The specified setting matches the default setting.
|
||||
|
||||
|
||||
Creating bit map...
|
||||
|
||||
Bitstream Status: Final Version 1.95.
|
||||
|
||||
Saving bit stream in "RAM2E_LCMXO2_640HC_impl1.jed".
|
||||
|
||||
===========
|
||||
UFM Summary.
|
||||
===========
|
||||
UFM Size: 191 Pages (128*191 Bits).
|
||||
UFM Utilization: General Purpose Flash Memory.
|
||||
|
||||
Available General Purpose Flash Memory: 191 Pages (Page 0 to Page 190).
|
||||
Initialized UFM Pages: 1 Page (Page 190).
|
||||
|
||||
Total CPU Time: 3 secs
|
||||
Total REAL Time: 4 secs
|
||||
Peak Memory Usage: 267 MB
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,468 @@
|
|||
|
||||
Lattice Mapping Report File for Design Module 'RAM2E'
|
||||
|
||||
|
||||
Design Information
|
||||
------------------
|
||||
|
||||
Command line: map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial
|
||||
RAM2E_LCMXO2_640HC_impl1.ngd -o RAM2E_LCMXO2_640HC_impl1_map.ncd -pr
|
||||
RAM2E_LCMXO2_640HC_impl1.prf -mp RAM2E_LCMXO2_640HC_impl1.mrp -lpf //Mac/iC
|
||||
loud/Repos/RAM2E/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_synplify.
|
||||
lpf -lpf //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf -c 0 -gui -msgset
|
||||
//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml
|
||||
Target Vendor: LATTICE
|
||||
Target Device: LCMXO2-640HCTQFP100
|
||||
Target Performance: 4
|
||||
Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454
|
||||
Mapped on: 09/21/23 05:34:46
|
||||
|
||||
Design Summary
|
||||
--------------
|
||||
|
||||
Number of registers: 111 out of 877 (13%)
|
||||
PFU registers: 75 out of 640 (12%)
|
||||
PIO registers: 36 out of 237 (15%)
|
||||
Number of SLICEs: 120 out of 320 (38%)
|
||||
SLICEs as Logic/ROM: 120 out of 320 (38%)
|
||||
SLICEs as RAM: 0 out of 240 (0%)
|
||||
SLICEs as Carry: 9 out of 320 (3%)
|
||||
Number of LUT4s: 239 out of 640 (37%)
|
||||
Number used as logic LUTs: 221
|
||||
Number used as distributed RAM: 0
|
||||
Number used as ripple logic: 18
|
||||
Number used as shift registers: 0
|
||||
Number of PIO sites used: 70 + 4(JTAG) out of 79 (94%)
|
||||
Number of block RAMs: 0 out of 2 (0%)
|
||||
Number of GSRs: 0 out of 1 (0%)
|
||||
EFB used : Yes
|
||||
JTAG used : No
|
||||
Readback used : No
|
||||
Oscillator used : No
|
||||
Startup used : No
|
||||
POR : On
|
||||
Bandgap : On
|
||||
Number of Power Controller: 0 out of 1 (0%)
|
||||
Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
|
||||
Number of DCCA: 0 out of 8 (0%)
|
||||
Number of DCMA: 0 out of 2 (0%)
|
||||
Notes:-
|
||||
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
|
||||
distributed RAMs) + 2*(Number of ripple logic)
|
||||
2. Number of logic LUT4s does not include count of distributed RAM and
|
||||
ripple logic.
|
||||
Number of clocks: 1
|
||||
Net C14M_c: 84 loads, 68 rising, 16 falling (Driver: PIO C14M )
|
||||
Number of Clock Enables: 11
|
||||
Net wb_adr_0_sqmuxa_i: 1 loads, 1 LSLICEs
|
||||
Net N_576_i: 17 loads, 9 LSLICEs
|
||||
Net LEDEN13: 4 loads, 4 LSLICEs
|
||||
Net nCS61: 1 loads, 1 LSLICEs
|
||||
Net Vout3: 8 loads, 0 LSLICEs
|
||||
Net S_RNII9DO1_1[1]: 7 loads, 1 LSLICEs
|
||||
|
||||
Page 1
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 09/21/23 05:34:46
|
||||
|
||||
Design Summary (cont)
|
||||
---------------------
|
||||
Net un1_wb_cyc_stb_0_sqmuxa_1_i[0]: 1 loads, 1 LSLICEs
|
||||
Net un1_wb_adr_0_sqmuxa_2_i[0]: 8 loads, 8 LSLICEs
|
||||
Net N_104: 1 loads, 1 LSLICEs
|
||||
Net N_88: 4 loads, 4 LSLICEs
|
||||
Net un1_LEDEN_0_sqmuxa_1_i_0[0]: 1 loads, 1 LSLICEs
|
||||
Number of LSRs: 5
|
||||
Net un1_CS_0_sqmuxa_i: 2 loads, 2 LSLICEs
|
||||
Net S[2]: 1 loads, 1 LSLICEs
|
||||
Net N_566_i: 2 loads, 0 LSLICEs
|
||||
Net wb_rst: 1 loads, 0 LSLICEs
|
||||
Net S_RNII9DO1[1]: 1 loads, 1 LSLICEs
|
||||
Number of nets driven by tri-state buffers: 0
|
||||
Top 10 highest fanout non-clock nets:
|
||||
Net S[2]: 48 loads
|
||||
Net S[3]: 48 loads
|
||||
Net S[0]: 30 loads
|
||||
Net FS[12]: 22 loads
|
||||
Net FS[9]: 21 loads
|
||||
Net S[1]: 21 loads
|
||||
Net FS[10]: 20 loads
|
||||
Net FS[11]: 19 loads
|
||||
Net RWSel: 19 loads
|
||||
Net FS[13]: 17 loads
|
||||
|
||||
|
||||
|
||||
|
||||
Number of warnings: 1
|
||||
Number of errors: 0
|
||||
|
||||
|
||||
Design Errors/Warnings
|
||||
----------------------
|
||||
|
||||
WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
||||
temporarily disable certain features of the device including Power
|
||||
Controller, GSR, Hardened User SPI Port, Hardened Primary User I2C Port.
|
||||
Functionality is restored after the Flash Memory (UFM/Configuration)
|
||||
Interface is disabled using Disable Configuration Interface command 0x26
|
||||
followed by Bypass command 0xFF.
|
||||
|
||||
IO (PIO) Attributes
|
||||
-------------------
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| IO Name | Direction | Levelmode | IO |
|
||||
| | | IO_TYPE | Register |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[0] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| LED | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| C14M | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| DQMH | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
Page 2
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 09/21/23 05:34:46
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
| DQML | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[7] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[6] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[5] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[4] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[3] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[2] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[1] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[11] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[10] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[9] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[8] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[7] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[6] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[5] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[4] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[3] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[2] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[1] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[0] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| BA[1] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| BA[0] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRWE | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nCAS | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRAS | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nCS | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| CKE | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nVOE | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
Page 3
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 09/21/23 05:34:46
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
| Vout[7] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Vout[6] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Vout[5] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Vout[4] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Vout[3] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Vout[2] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Vout[1] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Vout[0] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nDOE | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[7] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[6] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[5] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[4] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[3] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[2] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[1] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[0] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[7] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[6] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[5] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[4] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[3] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[2] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[1] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[0] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Ain[7] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Ain[6] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Ain[5] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
Page 4
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 09/21/23 05:34:46
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
| Ain[4] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Ain[3] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Ain[2] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Ain[1] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Ain[0] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nC07X | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nEN80 | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nWE80 | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nWE | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| PHI1 | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
Removed logic
|
||||
-------------
|
||||
|
||||
Block GSR_INST undriven or does not drive anything - clipped.
|
||||
Signal Dout_0_.CN was merged into signal C14M_c
|
||||
Signal GND undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/VCC undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/GND undriven or does not drive anything - clipped.
|
||||
Signal FS_s_0_S1[15] undriven or does not drive anything - clipped.
|
||||
Signal FS_s_0_COUT[15] undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/CFGWAKE undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wbc_ufm_irq undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/TCOC undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/TCINT undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIIRQO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPICSNEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMOSIEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMOSIO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMISOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMISOO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPISCKEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPISCKO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SDAOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
|
||||
|
||||
Page 5
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 09/21/23 05:34:46
|
||||
|
||||
Removed logic (cont)
|
||||
--------------------
|
||||
Signal ufmefb/I2C2SCLOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SDAOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SCLOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO4 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLWEO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLL1STBO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLL0STBO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLRSTO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLCLKO undriven or does not drive anything - clipped.
|
||||
Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped.
|
||||
Signal N_1 undriven or does not drive anything - clipped.
|
||||
Block Vout_0_.CN was optimized away.
|
||||
Block GND was optimized away.
|
||||
Block ufmefb/VCC was optimized away.
|
||||
Block ufmefb/GND was optimized away.
|
||||
|
||||
|
||||
|
||||
Embedded Functional Block Connection Summary
|
||||
--------------------------------------------
|
||||
|
||||
Desired WISHBONE clock frequency: 14.4 MHz
|
||||
Clock source: C14M_c
|
||||
Reset source: wb_rst
|
||||
Functions mode:
|
||||
I2C #1 (Primary) Function: DISABLED
|
||||
I2C #2 (Secondary) Function: DISABLED
|
||||
SPI Function: DISABLED
|
||||
Timer/Counter Function: DISABLED
|
||||
Timer/Counter Mode: WB
|
||||
UFM Connection: ENABLED
|
||||
PLL0 Connection: DISABLED
|
||||
PLL1 Connection: DISABLED
|
||||
I2C Function Summary:
|
||||
--------------------
|
||||
None
|
||||
SPI Function Summary:
|
||||
--------------------
|
||||
None
|
||||
Timer/Counter Function Summary:
|
||||
------------------------------
|
||||
|
||||
Page 6
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2E Date: 09/21/23 05:34:46
|
||||
|
||||
Embedded Functional Block Connection Summary (cont)
|
||||
---------------------------------------------------
|
||||
None
|
||||
UFM Function Summary:
|
||||
--------------------
|
||||
UFM Utilization: General Purpose Flash Memory
|
||||
Initialized UFM Pages: 1 Pages (1*128 Bits)
|
||||
Available General
|
||||
Purpose Flash Memory: 191 Pages (191*128 Bits)
|
||||
|
||||
EBR Blocks with Unique
|
||||
Initialization Data: 0
|
||||
|
||||
WID EBR Instance
|
||||
--- ------------
|
||||
|
||||
|
||||
ASIC Components
|
||||
---------------
|
||||
|
||||
Instance Name: ufmefb/EFBInst_0
|
||||
Type: EFB
|
||||
|
||||
Run Time and Memory Usage
|
||||
-------------------------
|
||||
|
||||
Total CPU Time: 0 secs
|
||||
Total REAL Time: 0 secs
|
||||
Peak Memory Usage: 58 MB
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Page 7
|
||||
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights
|
||||
reserved.
|
||||
|
|
@ -0,0 +1,287 @@
|
|||
PAD Specification File
|
||||
***************************
|
||||
|
||||
PART TYPE: LCMXO2-640HC
|
||||
Performance Grade: 4
|
||||
PACKAGE: TQFP100
|
||||
Package Status: Final Version 1.39
|
||||
|
||||
Thu Sep 21 05:35:00 2023
|
||||
|
||||
Pinout by Port Name:
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties |
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
| Ain[0] | 3/3 | LVCMOS33_IN | PL2C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Ain[1] | 2/3 | LVCMOS33_IN | PL2B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Ain[2] | 7/3 | LVCMOS33_IN | PL3A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Ain[3] | 4/3 | LVCMOS33_IN | PL2D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Ain[4] | 78/0 | LVCMOS33_IN | PT11A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Ain[5] | 84/0 | LVCMOS33_IN | PT10A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Ain[6] | 86/0 | LVCMOS33_IN | PT9C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Ain[7] | 8/3 | LVCMOS33_IN | PL3B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| BA[0] | 58/1 | LVCMOS33_OUT | PR6C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| BA[1] | 60/1 | LVCMOS33_OUT | PR6A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| C14M | 62/1 | LVCMOS33_IN | PR5D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| CKE | 53/1 | LVCMOS33_OUT | PR7B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| DQMH | 49/2 | LVCMOS33_OUT | PB14D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| DQML | 48/2 | LVCMOS33_OUT | PB14C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Din[0] | 96/0 | LVCMOS33_IN | PT6D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[1] | 97/0 | LVCMOS33_IN | PT6C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[2] | 98/0 | LVCMOS33_IN | PT6B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[3] | 9/3 | LVCMOS33_IN | PL3C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[4] | 1/3 | LVCMOS33_IN | PL2A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[5] | 99/0 | LVCMOS33_IN | PT6A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[6] | 88/0 | LVCMOS33_IN | PT9A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[7] | 87/0 | LVCMOS33_IN | PT9B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Dout[0] | 30/2 | LVCMOS33_OUT | PB4D | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[1] | 27/2 | LVCMOS33_OUT | PB4A | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[2] | 25/3 | LVCMOS33_OUT | PL7D | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[3] | 28/2 | LVCMOS33_OUT | PB4B | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[4] | 24/3 | LVCMOS33_OUT | PL7C | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[5] | 21/3 | LVCMOS33_OUT | PL7B | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[6] | 31/2 | LVCMOS33_OUT | PB6A | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[7] | 32/2 | LVCMOS33_OUT | PB6B | | | DRIVE:4mA SLEW:FAST |
|
||||
| LED | 35/2 | LVCMOS33_OUT | PB6D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| PHI1 | 85/0 | LVCMOS33_IN | PT9D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| RA[0] | 66/1 | LVCMOS33_OUT | PR3D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[10] | 64/1 | LVCMOS33_OUT | PR5B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[11] | 59/1 | LVCMOS33_OUT | PR6B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[1] | 68/1 | LVCMOS33_OUT | PR3B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[2] | 70/1 | LVCMOS33_OUT | PR2D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[3] | 74/1 | LVCMOS33_OUT | PR2B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[4] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[5] | 71/1 | LVCMOS33_OUT | PR2C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[6] | 69/1 | LVCMOS33_OUT | PR3A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[7] | 67/1 | LVCMOS33_OUT | PR3C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[9] | 63/1 | LVCMOS33_OUT | PR5C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RD[0] | 36/2 | LVCMOS33_BIDI | PB10A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[1] | 37/2 | LVCMOS33_BIDI | PB10B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[2] | 38/2 | LVCMOS33_BIDI | PB10C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[3] | 39/2 | LVCMOS33_BIDI | PB10D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[4] | 40/2 | LVCMOS33_BIDI | PB12A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[5] | 41/2 | LVCMOS33_BIDI | PB12B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[6] | 42/2 | LVCMOS33_BIDI | PB12C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[7] | 43/2 | LVCMOS33_BIDI | PB12D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| Vout[0] | 18/3 | LVCMOS33_OUT | PL6C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Vout[1] | 15/3 | LVCMOS33_OUT | PL5D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Vout[2] | 17/3 | LVCMOS33_OUT | PL6B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Vout[3] | 13/3 | LVCMOS33_OUT | PL5B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Vout[4] | 19/3 | LVCMOS33_OUT | PL6D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Vout[5] | 16/3 | LVCMOS33_OUT | PL6A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Vout[6] | 14/3 | LVCMOS33_OUT | PL5C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Vout[7] | 12/3 | LVCMOS33_OUT | PL5A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nC07X | 34/2 | LVCMOS33_IN | PB6C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nCAS | 52/1 | LVCMOS33_OUT | PR7C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nCS | 57/1 | LVCMOS33_OUT | PR6D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nDOE | 20/3 | LVCMOS33_OUT | PL7A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nEN80 | 82/0 | LVCMOS33_IN | PT10C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nRAS | 54/1 | LVCMOS33_OUT | PR7A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nRWE | 51/1 | LVCMOS33_OUT | PR7D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nVOE | 10/3 | LVCMOS33_OUT | PL3D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nWE | 29/2 | LVCMOS33_IN | PB4C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nWE80 | 83/0 | LVCMOS33_IN | PT10B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
|
||||
Vccio by Bank:
|
||||
+------+-------+
|
||||
| Bank | Vccio |
|
||||
+------+-------+
|
||||
| 0 | 3.3V |
|
||||
| 1 | 3.3V |
|
||||
| 2 | 3.3V |
|
||||
| 3 | 3.3V |
|
||||
+------+-------+
|
||||
|
||||
Vref by Bank:
|
||||
+------+-----+-----------------+---------+
|
||||
| Vref | Pin | Bank # / Vref # | Load(s) |
|
||||
+------+-----+-----------------+---------+
|
||||
+------+-----+-----------------+---------+
|
||||
|
||||
Pinout by Pin Number:
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable |
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
| 1/3 | Din[4] | LOCATED | LVCMOS33_IN | PL2A | | | |
|
||||
| 2/3 | Ain[1] | LOCATED | LVCMOS33_IN | PL2B | | | |
|
||||
| 3/3 | Ain[0] | LOCATED | LVCMOS33_IN | PL2C | PCLKT3_2 | | |
|
||||
| 4/3 | Ain[3] | LOCATED | LVCMOS33_IN | PL2D | PCLKC3_2 | | |
|
||||
| 7/3 | Ain[2] | LOCATED | LVCMOS33_IN | PL3A | | | |
|
||||
| 8/3 | Ain[7] | LOCATED | LVCMOS33_IN | PL3B | | | |
|
||||
| 9/3 | Din[3] | LOCATED | LVCMOS33_IN | PL3C | | | |
|
||||
| 10/3 | nVOE | LOCATED | LVCMOS33_OUT | PL3D | | | |
|
||||
| 12/3 | Vout[7] | LOCATED | LVCMOS33_OUT | PL5A | PCLKT3_1 | | |
|
||||
| 13/3 | Vout[3] | LOCATED | LVCMOS33_OUT | PL5B | PCLKC3_1 | | |
|
||||
| 14/3 | Vout[6] | LOCATED | LVCMOS33_OUT | PL5C | | | |
|
||||
| 15/3 | Vout[1] | LOCATED | LVCMOS33_OUT | PL5D | | | |
|
||||
| 16/3 | Vout[5] | LOCATED | LVCMOS33_OUT | PL6A | | | |
|
||||
| 17/3 | Vout[2] | LOCATED | LVCMOS33_OUT | PL6B | | | |
|
||||
| 18/3 | Vout[0] | LOCATED | LVCMOS33_OUT | PL6C | | | |
|
||||
| 19/3 | Vout[4] | LOCATED | LVCMOS33_OUT | PL6D | | | |
|
||||
| 20/3 | nDOE | LOCATED | LVCMOS33_OUT | PL7A | PCLKT3_0 | | |
|
||||
| 21/3 | Dout[5] | LOCATED | LVCMOS33_OUT | PL7B | PCLKC3_0 | | |
|
||||
| 24/3 | Dout[4] | LOCATED | LVCMOS33_OUT | PL7C | | | |
|
||||
| 25/3 | Dout[2] | LOCATED | LVCMOS33_OUT | PL7D | | | |
|
||||
| 27/2 | Dout[1] | LOCATED | LVCMOS33_OUT | PB4A | CSSPIN | | |
|
||||
| 28/2 | Dout[3] | LOCATED | LVCMOS33_OUT | PB4B | | | |
|
||||
| 29/2 | nWE | LOCATED | LVCMOS33_IN | PB4C | | | |
|
||||
| 30/2 | Dout[0] | LOCATED | LVCMOS33_OUT | PB4D | | | |
|
||||
| 31/2 | Dout[6] | LOCATED | LVCMOS33_OUT | PB6A | MCLK/CCLK | | |
|
||||
| 32/2 | Dout[7] | LOCATED | LVCMOS33_OUT | PB6B | SO/SPISO | | |
|
||||
| 34/2 | nC07X | LOCATED | LVCMOS33_IN | PB6C | PCLKT2_0 | | |
|
||||
| 35/2 | LED | LOCATED | LVCMOS33_OUT | PB6D | PCLKC2_0 | | |
|
||||
| 36/2 | RD[0] | LOCATED | LVCMOS33_BIDI | PB10A | | | |
|
||||
| 37/2 | RD[1] | LOCATED | LVCMOS33_BIDI | PB10B | | | |
|
||||
| 38/2 | RD[2] | LOCATED | LVCMOS33_BIDI | PB10C | PCLKT2_1 | | |
|
||||
| 39/2 | RD[3] | LOCATED | LVCMOS33_BIDI | PB10D | PCLKC2_1 | | |
|
||||
| 40/2 | RD[4] | LOCATED | LVCMOS33_BIDI | PB12A | | | |
|
||||
| 41/2 | RD[5] | LOCATED | LVCMOS33_BIDI | PB12B | | | |
|
||||
| 42/2 | RD[6] | LOCATED | LVCMOS33_BIDI | PB12C | | | |
|
||||
| 43/2 | RD[7] | LOCATED | LVCMOS33_BIDI | PB12D | | | |
|
||||
| 45/2 | unused, PULL:DOWN | | | PB14A | | | |
|
||||
| 47/2 | unused, PULL:DOWN | | | PB14B | | | |
|
||||
| 48/2 | DQML | LOCATED | LVCMOS33_OUT | PB14C | SN | | |
|
||||
| 49/2 | DQMH | LOCATED | LVCMOS33_OUT | PB14D | SI/SISPI | | |
|
||||
| 51/1 | nRWE | LOCATED | LVCMOS33_OUT | PR7D | | | |
|
||||
| 52/1 | nCAS | LOCATED | LVCMOS33_OUT | PR7C | | | |
|
||||
| 53/1 | CKE | LOCATED | LVCMOS33_OUT | PR7B | | | |
|
||||
| 54/1 | nRAS | LOCATED | LVCMOS33_OUT | PR7A | | | |
|
||||
| 57/1 | nCS | LOCATED | LVCMOS33_OUT | PR6D | | | |
|
||||
| 58/1 | BA[0] | LOCATED | LVCMOS33_OUT | PR6C | | | |
|
||||
| 59/1 | RA[11] | LOCATED | LVCMOS33_OUT | PR6B | | | |
|
||||
| 60/1 | BA[1] | LOCATED | LVCMOS33_OUT | PR6A | | | |
|
||||
| 62/1 | C14M | LOCATED | LVCMOS33_IN | PR5D | PCLKC1_0 | | |
|
||||
| 63/1 | RA[9] | LOCATED | LVCMOS33_OUT | PR5C | PCLKT1_0 | | |
|
||||
| 64/1 | RA[10] | LOCATED | LVCMOS33_OUT | PR5B | | | |
|
||||
| 65/1 | RA[8] | LOCATED | LVCMOS33_OUT | PR5A | | | |
|
||||
| 66/1 | RA[0] | LOCATED | LVCMOS33_OUT | PR3D | | | |
|
||||
| 67/1 | RA[7] | LOCATED | LVCMOS33_OUT | PR3C | | | |
|
||||
| 68/1 | RA[1] | LOCATED | LVCMOS33_OUT | PR3B | | | |
|
||||
| 69/1 | RA[6] | LOCATED | LVCMOS33_OUT | PR3A | | | |
|
||||
| 70/1 | RA[2] | LOCATED | LVCMOS33_OUT | PR2D | | | |
|
||||
| 71/1 | RA[5] | LOCATED | LVCMOS33_OUT | PR2C | | | |
|
||||
| 74/1 | RA[3] | LOCATED | LVCMOS33_OUT | PR2B | | | |
|
||||
| 75/1 | RA[4] | LOCATED | LVCMOS33_OUT | PR2A | | | |
|
||||
| 76/0 | unused, PULL:DOWN | | | PT11D | DONE | | |
|
||||
| 77/0 | unused, PULL:DOWN | | | PT11C | INITN | | |
|
||||
| 78/0 | Ain[4] | LOCATED | LVCMOS33_IN | PT11A | | | |
|
||||
| 81/0 | unused, PULL:DOWN | | | PT10D | PROGRAMN | | |
|
||||
| 82/0 | nEN80 | LOCATED | LVCMOS33_IN | PT10C | JTAGENB | | |
|
||||
| 83/0 | nWE80 | LOCATED | LVCMOS33_IN | PT10B | | | |
|
||||
| 84/0 | Ain[5] | LOCATED | LVCMOS33_IN | PT10A | | | |
|
||||
| 85/0 | PHI1 | LOCATED | LVCMOS33_IN | PT9D | SDA/PCLKC0_0 | | |
|
||||
| 86/0 | Ain[6] | LOCATED | LVCMOS33_IN | PT9C | SCL/PCLKT0_0 | | |
|
||||
| 87/0 | Din[7] | LOCATED | LVCMOS33_IN | PT9B | PCLKC0_1 | | |
|
||||
| 88/0 | Din[6] | LOCATED | LVCMOS33_IN | PT9A | PCLKT0_1 | | |
|
||||
| 90/0 | Reserved: sysCONFIG | | | PT7D | TMS | | |
|
||||
| 91/0 | Reserved: sysCONFIG | | | PT7C | TCK | | |
|
||||
| 94/0 | Reserved: sysCONFIG | | | PT7B | TDI | | |
|
||||
| 95/0 | Reserved: sysCONFIG | | | PT7A | TDO | | |
|
||||
| 96/0 | Din[0] | LOCATED | LVCMOS33_IN | PT6D | | | |
|
||||
| 97/0 | Din[1] | LOCATED | LVCMOS33_IN | PT6C | | | |
|
||||
| 98/0 | Din[2] | LOCATED | LVCMOS33_IN | PT6B | | | |
|
||||
| 99/0 | Din[5] | LOCATED | LVCMOS33_IN | PT6A | | | |
|
||||
| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | |
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
|
||||
sysCONFIG Pins:
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode |
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
| PT7D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP |
|
||||
| PT7C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down |
|
||||
| PT7B | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP |
|
||||
| PT7A | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP |
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
|
||||
Dedicated sysCONFIG Pins:
|
||||
|
||||
|
||||
List of All Pins' Locate Preferences Based on Final Placement After PAR
|
||||
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste):
|
||||
|
||||
LOCATE COMP "Ain[0]" SITE "3";
|
||||
LOCATE COMP "Ain[1]" SITE "2";
|
||||
LOCATE COMP "Ain[2]" SITE "7";
|
||||
LOCATE COMP "Ain[3]" SITE "4";
|
||||
LOCATE COMP "Ain[4]" SITE "78";
|
||||
LOCATE COMP "Ain[5]" SITE "84";
|
||||
LOCATE COMP "Ain[6]" SITE "86";
|
||||
LOCATE COMP "Ain[7]" SITE "8";
|
||||
LOCATE COMP "BA[0]" SITE "58";
|
||||
LOCATE COMP "BA[1]" SITE "60";
|
||||
LOCATE COMP "C14M" SITE "62";
|
||||
LOCATE COMP "CKE" SITE "53";
|
||||
LOCATE COMP "DQMH" SITE "49";
|
||||
LOCATE COMP "DQML" SITE "48";
|
||||
LOCATE COMP "Din[0]" SITE "96";
|
||||
LOCATE COMP "Din[1]" SITE "97";
|
||||
LOCATE COMP "Din[2]" SITE "98";
|
||||
LOCATE COMP "Din[3]" SITE "9";
|
||||
LOCATE COMP "Din[4]" SITE "1";
|
||||
LOCATE COMP "Din[5]" SITE "99";
|
||||
LOCATE COMP "Din[6]" SITE "88";
|
||||
LOCATE COMP "Din[7]" SITE "87";
|
||||
LOCATE COMP "Dout[0]" SITE "30";
|
||||
LOCATE COMP "Dout[1]" SITE "27";
|
||||
LOCATE COMP "Dout[2]" SITE "25";
|
||||
LOCATE COMP "Dout[3]" SITE "28";
|
||||
LOCATE COMP "Dout[4]" SITE "24";
|
||||
LOCATE COMP "Dout[5]" SITE "21";
|
||||
LOCATE COMP "Dout[6]" SITE "31";
|
||||
LOCATE COMP "Dout[7]" SITE "32";
|
||||
LOCATE COMP "LED" SITE "35";
|
||||
LOCATE COMP "PHI1" SITE "85";
|
||||
LOCATE COMP "RA[0]" SITE "66";
|
||||
LOCATE COMP "RA[10]" SITE "64";
|
||||
LOCATE COMP "RA[11]" SITE "59";
|
||||
LOCATE COMP "RA[1]" SITE "68";
|
||||
LOCATE COMP "RA[2]" SITE "70";
|
||||
LOCATE COMP "RA[3]" SITE "74";
|
||||
LOCATE COMP "RA[4]" SITE "75";
|
||||
LOCATE COMP "RA[5]" SITE "71";
|
||||
LOCATE COMP "RA[6]" SITE "69";
|
||||
LOCATE COMP "RA[7]" SITE "67";
|
||||
LOCATE COMP "RA[8]" SITE "65";
|
||||
LOCATE COMP "RA[9]" SITE "63";
|
||||
LOCATE COMP "RD[0]" SITE "36";
|
||||
LOCATE COMP "RD[1]" SITE "37";
|
||||
LOCATE COMP "RD[2]" SITE "38";
|
||||
LOCATE COMP "RD[3]" SITE "39";
|
||||
LOCATE COMP "RD[4]" SITE "40";
|
||||
LOCATE COMP "RD[5]" SITE "41";
|
||||
LOCATE COMP "RD[6]" SITE "42";
|
||||
LOCATE COMP "RD[7]" SITE "43";
|
||||
LOCATE COMP "Vout[0]" SITE "18";
|
||||
LOCATE COMP "Vout[1]" SITE "15";
|
||||
LOCATE COMP "Vout[2]" SITE "17";
|
||||
LOCATE COMP "Vout[3]" SITE "13";
|
||||
LOCATE COMP "Vout[4]" SITE "19";
|
||||
LOCATE COMP "Vout[5]" SITE "16";
|
||||
LOCATE COMP "Vout[6]" SITE "14";
|
||||
LOCATE COMP "Vout[7]" SITE "12";
|
||||
LOCATE COMP "nC07X" SITE "34";
|
||||
LOCATE COMP "nCAS" SITE "52";
|
||||
LOCATE COMP "nCS" SITE "57";
|
||||
LOCATE COMP "nDOE" SITE "20";
|
||||
LOCATE COMP "nEN80" SITE "82";
|
||||
LOCATE COMP "nRAS" SITE "54";
|
||||
LOCATE COMP "nRWE" SITE "51";
|
||||
LOCATE COMP "nVOE" SITE "10";
|
||||
LOCATE COMP "nWE" SITE "29";
|
||||
LOCATE COMP "nWE80" SITE "83";
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Thu Sep 21 05:35:04 2023
|
||||
|
||||
|
|
@ -0,0 +1,127 @@
|
|||
SCHEMATIC START ;
|
||||
# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Thu Sep 21 05:34:47 2023
|
||||
|
||||
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
|
||||
LOCATE COMP "RD[0]" SITE "36" ;
|
||||
LOCATE COMP "LED" SITE "35" ;
|
||||
LOCATE COMP "C14M" SITE "62" ;
|
||||
LOCATE COMP "DQMH" SITE "49" ;
|
||||
LOCATE COMP "DQML" SITE "48" ;
|
||||
LOCATE COMP "RD[7]" SITE "43" ;
|
||||
LOCATE COMP "RD[6]" SITE "42" ;
|
||||
LOCATE COMP "RD[5]" SITE "41" ;
|
||||
LOCATE COMP "RD[4]" SITE "40" ;
|
||||
LOCATE COMP "RD[3]" SITE "39" ;
|
||||
LOCATE COMP "RD[2]" SITE "38" ;
|
||||
LOCATE COMP "RD[1]" SITE "37" ;
|
||||
LOCATE COMP "RA[11]" SITE "59" ;
|
||||
LOCATE COMP "RA[10]" SITE "64" ;
|
||||
LOCATE COMP "RA[9]" SITE "63" ;
|
||||
LOCATE COMP "RA[8]" SITE "65" ;
|
||||
LOCATE COMP "RA[7]" SITE "67" ;
|
||||
LOCATE COMP "RA[6]" SITE "69" ;
|
||||
LOCATE COMP "RA[5]" SITE "71" ;
|
||||
LOCATE COMP "RA[4]" SITE "75" ;
|
||||
LOCATE COMP "RA[3]" SITE "74" ;
|
||||
LOCATE COMP "RA[2]" SITE "70" ;
|
||||
LOCATE COMP "RA[1]" SITE "68" ;
|
||||
LOCATE COMP "RA[0]" SITE "66" ;
|
||||
LOCATE COMP "BA[1]" SITE "60" ;
|
||||
LOCATE COMP "BA[0]" SITE "58" ;
|
||||
LOCATE COMP "nRWE" SITE "51" ;
|
||||
LOCATE COMP "nCAS" SITE "52" ;
|
||||
LOCATE COMP "nRAS" SITE "54" ;
|
||||
LOCATE COMP "nCS" SITE "57" ;
|
||||
LOCATE COMP "CKE" SITE "53" ;
|
||||
LOCATE COMP "nVOE" SITE "10" ;
|
||||
LOCATE COMP "Vout[7]" SITE "12" ;
|
||||
LOCATE COMP "Vout[6]" SITE "14" ;
|
||||
LOCATE COMP "Vout[5]" SITE "16" ;
|
||||
LOCATE COMP "Vout[4]" SITE "19" ;
|
||||
LOCATE COMP "Vout[3]" SITE "13" ;
|
||||
LOCATE COMP "Vout[2]" SITE "17" ;
|
||||
LOCATE COMP "Vout[1]" SITE "15" ;
|
||||
LOCATE COMP "Vout[0]" SITE "18" ;
|
||||
LOCATE COMP "nDOE" SITE "20" ;
|
||||
LOCATE COMP "Dout[7]" SITE "32" ;
|
||||
LOCATE COMP "Dout[6]" SITE "31" ;
|
||||
LOCATE COMP "Dout[5]" SITE "21" ;
|
||||
LOCATE COMP "Dout[4]" SITE "24" ;
|
||||
LOCATE COMP "Dout[3]" SITE "28" ;
|
||||
LOCATE COMP "Dout[2]" SITE "25" ;
|
||||
LOCATE COMP "Dout[1]" SITE "27" ;
|
||||
LOCATE COMP "Dout[0]" SITE "30" ;
|
||||
LOCATE COMP "Din[7]" SITE "87" ;
|
||||
LOCATE COMP "Din[6]" SITE "88" ;
|
||||
LOCATE COMP "Din[5]" SITE "99" ;
|
||||
LOCATE COMP "Din[4]" SITE "1" ;
|
||||
LOCATE COMP "Din[3]" SITE "9" ;
|
||||
LOCATE COMP "Din[2]" SITE "98" ;
|
||||
LOCATE COMP "Din[1]" SITE "97" ;
|
||||
LOCATE COMP "Din[0]" SITE "96" ;
|
||||
LOCATE COMP "Ain[7]" SITE "8" ;
|
||||
LOCATE COMP "Ain[6]" SITE "86" ;
|
||||
LOCATE COMP "Ain[5]" SITE "84" ;
|
||||
LOCATE COMP "Ain[4]" SITE "78" ;
|
||||
LOCATE COMP "Ain[3]" SITE "4" ;
|
||||
LOCATE COMP "Ain[2]" SITE "7" ;
|
||||
LOCATE COMP "Ain[1]" SITE "2" ;
|
||||
LOCATE COMP "Ain[0]" SITE "3" ;
|
||||
LOCATE COMP "nC07X" SITE "34" ;
|
||||
LOCATE COMP "nEN80" SITE "82" ;
|
||||
LOCATE COMP "nWE80" SITE "83" ;
|
||||
LOCATE COMP "nWE" SITE "29" ;
|
||||
LOCATE COMP "PHI1" SITE "85" ;
|
||||
FREQUENCY PORT "C14M" 14.300000 MHz ;
|
||||
SCHEMATIC END ;
|
||||
BLOCK RESETPATHS ;
|
||||
BLOCK ASYNCPATHS ;
|
||||
OUTPUT PORT "LED" LOAD 100.000000 pF ;
|
||||
OUTPUT PORT "BA[1]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "BA[0]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "CKE" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "DQMH" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "DQML" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "Dout[0]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Dout[1]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Dout[2]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Dout[3]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Dout[4]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Dout[5]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Dout[6]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Dout[7]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "RA[0]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[1]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[2]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[3]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[4]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[5]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[6]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[7]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[8]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[9]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[10]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[11]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "Vout[0]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Vout[1]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Vout[2]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Vout[3]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Vout[4]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Vout[5]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Vout[6]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Vout[7]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "nCAS" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "nCS" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "nDOE" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "nRAS" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "nRWE" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "nVOE" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RD[0]" LOAD 9.000000 pF ;
|
||||
OUTPUT PORT "RD[1]" LOAD 9.000000 pF ;
|
||||
OUTPUT PORT "RD[2]" LOAD 9.000000 pF ;
|
||||
OUTPUT PORT "RD[3]" LOAD 9.000000 pF ;
|
||||
OUTPUT PORT "RD[4]" LOAD 9.000000 pF ;
|
||||
OUTPUT PORT "RD[5]" LOAD 9.000000 pF ;
|
||||
OUTPUT PORT "RD[6]" LOAD 9.000000 pF ;
|
||||
OUTPUT PORT "RD[7]" LOAD 9.000000 pF ;
|
||||
COMMERCIAL ;
|
||||
|
|
@ -0,0 +1,690 @@
|
|||
#Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021
|
||||
#install: C:\lscc\diamond\3.12\synpbase
|
||||
#OS: Windows 8 6.2
|
||||
#Hostname: ZANEMACWIN11
|
||||
|
||||
# Thu Sep 21 05:34:32 2023
|
||||
|
||||
#Implementation: impl1
|
||||
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: R-2021.03L-SP1
|
||||
Install: C:\lscc\diamond\3.12\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
###########################################################[
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: R-2021.03L-SP1
|
||||
Install: C:\lscc\diamond\3.12\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v" (library work)
|
||||
@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
|
||||
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
|
||||
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
|
||||
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
|
||||
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
|
||||
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E-LCMXO2.v" (library work)
|
||||
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\REFB.v" (library work)
|
||||
Verilog syntax check successful!
|
||||
|
||||
Compiler output is up to date. No re-compile necessary
|
||||
|
||||
Selecting top level module RAM2E
|
||||
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
|
||||
Running optimization stage 1 on VHI .......
|
||||
Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
|
||||
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
|
||||
Running optimization stage 1 on VLO .......
|
||||
Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
|
||||
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
|
||||
Running optimization stage 1 on EFB .......
|
||||
Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
|
||||
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
|
||||
Running optimization stage 1 on REFB .......
|
||||
Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
|
||||
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E-LCMXO2.v":1:7:1:11|Synthesizing module RAM2E in library work.
|
||||
Running optimization stage 1 on RAM2E .......
|
||||
Finished optimization stage 1 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB)
|
||||
Running optimization stage 2 on RAM2E .......
|
||||
Finished optimization stage 2 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
|
||||
Running optimization stage 2 on REFB .......
|
||||
Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
|
||||
Running optimization stage 2 on EFB .......
|
||||
Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
|
||||
Running optimization stage 2 on VLO .......
|
||||
Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
|
||||
Running optimization stage 2 on VHI .......
|
||||
Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
|
||||
|
||||
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 97MB peak: 98MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:34:32 2023
|
||||
|
||||
###########################################################]
|
||||
###########################################################[
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: R-2021.03L-SP1
|
||||
Install: C:\lscc\diamond\3.12\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:34:33 2023
|
||||
|
||||
###########################################################]
|
||||
|
||||
For a summary of runtime and memory usage for all design units, please see file:
|
||||
==========================================================
|
||||
@L: A:\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_comp.rt.csv
|
||||
|
||||
@END
|
||||
|
||||
At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:34:33 2023
|
||||
|
||||
###########################################################]
|
||||
###########################################################[
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: R-2021.03L-SP1
|
||||
Install: C:\lscc\diamond\3.12\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
File \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_comp.srs changed - recompiling
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:34:34 2023
|
||||
|
||||
###########################################################]
|
||||
# Thu Sep 21 05:34:34 2023
|
||||
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: R-2021.03L-SP1
|
||||
Install: C:\lscc\diamond\3.12\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @
|
||||
|
||||
|
||||
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
|
||||
|
||||
|
||||
Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 140MB)
|
||||
|
||||
Reading constraint file: \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
|
||||
@L: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1_scck.rpt
|
||||
See clock summary report "\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1_scck.rpt"
|
||||
@N: MF916 |Option synthesis_strategy=base is enabled.
|
||||
@N: MF248 |Running in 64-bit mode.
|
||||
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
|
||||
|
||||
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
|
||||
|
||||
|
||||
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
|
||||
|
||||
|
||||
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 149MB)
|
||||
|
||||
|
||||
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 151MB)
|
||||
|
||||
@N: FX493 |Applying initial value "0" on instance PHI1reg.
|
||||
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
|
||||
@N: FX493 |Applying initial value "0" on instance DOEEN.
|
||||
@N: FX493 |Applying initial value "0" on instance RWSel.
|
||||
@N: FX493 |Applying initial value "00000000" on instance RWBank[7:0].
|
||||
@N: FX493 |Applying initial value "1" on instance DQMH.
|
||||
@N: FX493 |Applying initial value "0" on instance Ready.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdBitbangMXO2.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdExecMXO2.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdLEDGet.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdLEDSet.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdRWMaskSet.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdSetRWBankFFLED.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdSetRWBankFFMXO2.
|
||||
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":375:4:375:9|Initial value on register nRWE is non-zero which can prevent the register from being packed into a block RAM or DSP.
|
||||
@N: FX493 |Applying initial value "1" on instance nRWE.
|
||||
@N: FX493 |Applying initial value "0" on instance LEDEN.
|
||||
@N: FX493 |Applying initial value "00000000" on instance RWMask[7:0].
|
||||
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":102:4:102:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
|
||||
@N: FX493 |Applying initial value "0000" on instance S[3:0].
|
||||
@N: FX493 |Applying initial value "1" on instance DQML.
|
||||
@N: FX493 |Applying initial value "0" on instance CKE.
|
||||
@N: FX493 |Applying initial value "1" on instance nCS.
|
||||
@N: FX493 |Applying initial value "1" on instance nRAS.
|
||||
@N: FX493 |Applying initial value "1" on instance nCAS.
|
||||
|
||||
Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
|
||||
|
||||
|
||||
Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
|
||||
|
||||
|
||||
Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
|
||||
|
||||
|
||||
Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
|
||||
|
||||
@N: FX1184 |Applying syn_allowed_resources blockrams=2 on top level netlist RAM2E
|
||||
|
||||
Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
|
||||
|
||||
|
||||
|
||||
Clock Summary
|
||||
******************
|
||||
|
||||
Start Requested Requested Clock Clock Clock
|
||||
Level Clock Frequency Period Type Group Load
|
||||
----------------------------------------------------------------------------------------
|
||||
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 111
|
||||
|
||||
0 - System 100.0 MHz 10.000 system system_clkgroup 0
|
||||
========================================================================================
|
||||
|
||||
|
||||
|
||||
Clock Load Summary
|
||||
***********************
|
||||
|
||||
Clock Source Clock Pin Non-clock Pin Non-clock Pin
|
||||
Clock Load Pin Seq Example Seq Example Comb Example
|
||||
----------------------------------------------------------------------------------------
|
||||
C14M 111 C14M(port) wb_rst.C - un1_C14M.I[0](inv)
|
||||
|
||||
System 0 - - - -
|
||||
========================================================================================
|
||||
|
||||
ICG Latch Removal Summary:
|
||||
Number of ICG latches removed: 0
|
||||
Number of ICG latches not removed: 0
|
||||
For details review file gcc_ICG_report.rpt
|
||||
|
||||
|
||||
@S |Clock Optimization Summary
|
||||
|
||||
|
||||
|
||||
#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
|
||||
|
||||
1 non-gated/non-generated clock tree(s) driving 111 clock pin(s) of sequential element(s)
|
||||
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
|
||||
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
|
||||
|
||||
=========================== Non-Gated/Non-Generated Clocks ============================
|
||||
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
|
||||
---------------------------------------------------------------------------------------
|
||||
@KP:ckid0_0 C14M port 111 nCAS
|
||||
=======================================================================================
|
||||
|
||||
|
||||
##### END OF CLOCK OPTIMIZATION REPORT ######
|
||||
|
||||
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
|
||||
Finished Pre Mapping Phase.
|
||||
|
||||
Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
|
||||
|
||||
|
||||
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
|
||||
|
||||
|
||||
Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
|
||||
|
||||
Pre-mapping successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 99MB peak: 185MB)
|
||||
|
||||
Process took 0h:00m:02s realtime, 0h:00m:01s cputime
|
||||
# Thu Sep 21 05:34:37 2023
|
||||
|
||||
###########################################################]
|
||||
# Thu Sep 21 05:34:37 2023
|
||||
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: R-2021.03L-SP1
|
||||
Install: C:\lscc\diamond\3.12\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @
|
||||
|
||||
|
||||
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
|
||||
|
||||
@N: MF916 |Option synthesis_strategy=base is enabled.
|
||||
@N: MF248 |Running in 64-bit mode.
|
||||
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
|
||||
|
||||
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
|
||||
|
||||
|
||||
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
|
||||
|
||||
|
||||
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
|
||||
|
||||
|
||||
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB)
|
||||
|
||||
|
||||
|
||||
Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 179MB peak: 179MB)
|
||||
|
||||
@W: FA239 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":376:8:376:9|ROM DOEEN_2 (in view: work.RAM2E(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
|
||||
@N: MO106 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":376:8:376:9|Found ROM DOEEN_2 (in view: work.RAM2E(verilog)) with 16 words by 1 bit.
|
||||
|
||||
Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
|
||||
|
||||
@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":102:4:102:9|Found counter in view:work.RAM2E(verilog) instance FS[15:0]
|
||||
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
|
||||
|
||||
Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB)
|
||||
|
||||
|
||||
Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
|
||||
|
||||
|
||||
Available hyper_sources - for debug and ip models
|
||||
None Found
|
||||
|
||||
|
||||
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
|
||||
|
||||
|
||||
Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
|
||||
|
||||
|
||||
Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
|
||||
|
||||
|
||||
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
|
||||
|
||||
|
||||
Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
|
||||
|
||||
|
||||
Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 205MB peak: 205MB)
|
||||
|
||||
Pass CPU time Worst Slack Luts / Registers
|
||||
------------------------------------------------------------
|
||||
1 0h:00m:02s 29.35ns 222 / 111
|
||||
|
||||
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 205MB peak: 205MB)
|
||||
|
||||
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
|
||||
|
||||
Finished restoring hierarchy (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 206MB peak: 206MB)
|
||||
|
||||
|
||||
Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 168MB peak: 206MB)
|
||||
|
||||
Writing Analyst data base \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_m.srm
|
||||
|
||||
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 206MB peak: 206MB)
|
||||
|
||||
Writing EDIF Netlist and constraint files
|
||||
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1.edi
|
||||
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
|
||||
|
||||
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 211MB peak: 211MB)
|
||||
|
||||
|
||||
Finished Writing Netlists (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 211MB peak: 211MB)
|
||||
|
||||
|
||||
Start final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 209MB peak: 211MB)
|
||||
|
||||
@W: MT246 :"\\mac\icloud\repos\ram2e\cpld\lcmxo2-640hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
|
||||
@N: MT615 |Found clock C14M with period 69.84ns
|
||||
|
||||
|
||||
##### START OF TIMING REPORT #####[
|
||||
# Timing report written on Thu Sep 21 05:34:43 2023
|
||||
#
|
||||
|
||||
|
||||
Top view: RAM2E
|
||||
Requested Frequency: 14.3 MHz
|
||||
Wire load mode: top
|
||||
Paths requested: 5
|
||||
Constraint File(s): \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
|
||||
|
||||
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
|
||||
|
||||
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
|
||||
|
||||
|
||||
|
||||
Performance Summary
|
||||
*******************
|
||||
|
||||
|
||||
Worst slack in design: 31.782
|
||||
|
||||
Requested Estimated Requested Estimated Clock Clock
|
||||
Starting Clock Frequency Frequency Period Period Slack Type Group
|
||||
-------------------------------------------------------------------------------------------------------------------
|
||||
C14M 14.3 MHz 131.4 MHz 69.841 7.610 31.782 declared default_clkgroup
|
||||
System 100.0 MHz NA 10.000 NA 67.088 system system_clkgroup
|
||||
===================================================================================================================
|
||||
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Clock Relationships
|
||||
*******************
|
||||
|
||||
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
System C14M | 69.841 67.088 | No paths - | No paths - | No paths -
|
||||
C14M System | 69.841 68.797 | No paths - | No paths - | No paths -
|
||||
C14M C14M | 69.841 62.231 | No paths - | 34.920 31.782 | No paths -
|
||||
==========================================================================================================
|
||||
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
|
||||
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
|
||||
|
||||
|
||||
|
||||
Interface Information
|
||||
*********************
|
||||
|
||||
No IO constraint found
|
||||
|
||||
|
||||
|
||||
====================================
|
||||
Detailed Report for Clock: C14M
|
||||
====================================
|
||||
|
||||
|
||||
|
||||
Starting Points with Worst Slack
|
||||
********************************
|
||||
|
||||
Starting Arrival
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------
|
||||
S[2] C14M FD1S3AX Q S[2] 1.350 31.782
|
||||
S[3] C14M FD1S3AX Q S[3] 1.350 31.782
|
||||
S[0] C14M FD1S3AX Q S[0] 1.312 31.820
|
||||
S[1] C14M FD1S3AX Q S[1] 1.280 31.852
|
||||
FS[9] C14M FD1S3AX Q FS[9] 1.284 62.425
|
||||
FS[11] C14M FD1S3AX Q FS[11] 1.276 62.433
|
||||
FS[8] C14M FD1S3AX Q FS[8] 1.260 62.449
|
||||
FS[12] C14M FD1S3AX Q FS[12] 1.288 62.525
|
||||
FS[10] C14M FD1S3AX Q FS[10] 1.280 62.533
|
||||
RWSel C14M FD1P3AX Q RWSel 1.276 63.482
|
||||
============================================================================
|
||||
|
||||
|
||||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------------
|
||||
Dout_0io[0] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[1] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[2] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[3] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[4] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[5] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[6] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[7] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Vout_0io[0] C14M OFS1P3DX SP Vout3 34.449 31.826
|
||||
Vout_0io[1] C14M OFS1P3DX SP Vout3 34.449 31.826
|
||||
==================================================================================
|
||||
|
||||
|
||||
|
||||
Worst Path Information
|
||||
***********************
|
||||
|
||||
|
||||
Path information for path number 1:
|
||||
Requested Period: 34.920
|
||||
- Setup time: 0.472
|
||||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
= Required time: 34.449
|
||||
|
||||
- Propagation time: 2.667
|
||||
- Clock delay at starting point: 0.000 (ideal)
|
||||
= Slack (critical) : 31.782
|
||||
|
||||
Number of logic level(s): 1
|
||||
Starting point: S[2] / Q
|
||||
Ending point: Dout_0io[0] / SP
|
||||
The start point is clocked by C14M [rising] (rise=0.000 fall=34.920 period=69.841) on pin CK
|
||||
The end point is clocked by C14M [falling] (rise=0.000 fall=34.920 period=69.841) on pin SCLK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
----------------------------------------------------------------------------------
|
||||
S[2] FD1S3AX Q Out 1.350 1.350 r -
|
||||
S[2] Net - - - - 48
|
||||
S_RNII9DO1_2[1] ORCALUT4 B In 0.000 1.350 r -
|
||||
S_RNII9DO1_2[1] ORCALUT4 Z Out 1.317 2.667 r -
|
||||
N_576_i Net - - - - 18
|
||||
Dout_0io[0] OFS1P3DX SP In 0.000 2.667 r -
|
||||
==================================================================================
|
||||
|
||||
|
||||
|
||||
|
||||
====================================
|
||||
Detailed Report for Clock: System
|
||||
====================================
|
||||
|
||||
|
||||
|
||||
Starting Points with Worst Slack
|
||||
********************************
|
||||
|
||||
Starting Arrival
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
-----------------------------------------------------------------------------------------
|
||||
ufmefb.EFBInst_0 System EFB WBACKO wb_ack 0.000 67.088
|
||||
ufmefb.EFBInst_0 System EFB WBDATO0 wb_dato[0] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO2 wb_dato[2] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO3 wb_dato[3] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO4 wb_dato[4] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO5 wb_dato[5] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO6 wb_dato[6] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO7 wb_dato[7] 0.000 69.313
|
||||
=========================================================================================
|
||||
|
||||
|
||||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------------------------------
|
||||
RWMask[0] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[1] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[2] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[3] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[4] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[5] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[6] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[7] System FD1P3AX SP N_88 69.369 67.088
|
||||
LEDEN System FD1P3AX SP un1_LEDEN_0_sqmuxa_1_i_0[0] 69.369 67.736
|
||||
wb_cyc_stb System FD1P3AX SP N_104 69.369 67.736
|
||||
====================================================================================================
|
||||
|
||||
|
||||
|
||||
Worst Path Information
|
||||
***********************
|
||||
|
||||
|
||||
Path information for path number 1:
|
||||
Requested Period: 69.841
|
||||
- Setup time: 0.472
|
||||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
= Required time: 69.369
|
||||
|
||||
- Propagation time: 2.282
|
||||
- Clock delay at starting point: 0.000 (ideal)
|
||||
- Estimated clock delay at start point: -0.000
|
||||
= Slack (non-critical) : 67.088
|
||||
|
||||
Number of logic level(s): 2
|
||||
Starting point: ufmefb.EFBInst_0 / WBACKO
|
||||
Ending point: RWMask[0] / SP
|
||||
The start point is clocked by System [rising]
|
||||
The end point is clocked by C14M [rising] (rise=0.000 fall=34.920 period=69.841) on pin CK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
------------------------------------------------------------------------------------------------------
|
||||
ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 r -
|
||||
wb_ack Net - - - - 5
|
||||
un1_RWMask_0_sqmuxa_1_i_0_RNO[0] ORCALUT4 A In 0.000 0.000 r -
|
||||
un1_RWMask_0_sqmuxa_1_i_0_RNO[0] ORCALUT4 Z Out 1.017 1.017 r -
|
||||
un1_RWMask_0_sqmuxa_1_i_a2_0_1[0] Net - - - - 1
|
||||
un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 D In 0.000 1.017 r -
|
||||
un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 Z Out 1.265 2.282 r -
|
||||
N_88 Net - - - - 8
|
||||
RWMask[0] FD1P3AX SP In 0.000 2.282 r -
|
||||
======================================================================================================
|
||||
|
||||
|
||||
|
||||
##### END OF TIMING REPORT #####]
|
||||
|
||||
Timing exceptions that could not be applied
|
||||
|
||||
Finished final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:04s; Memory used current: 210MB peak: 211MB)
|
||||
|
||||
|
||||
Finished timing report (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:04s; Memory used current: 210MB peak: 211MB)
|
||||
|
||||
---------------------------------------
|
||||
Resource Usage Report
|
||||
Part: lcmxo2_640hc-4
|
||||
|
||||
Register bits: 111 of 640 (17%)
|
||||
PIC Latch: 0
|
||||
I/O cells: 70
|
||||
|
||||
|
||||
Details:
|
||||
BB: 8
|
||||
CCU2D: 9
|
||||
EFB: 1
|
||||
FD1P3AX: 48
|
||||
FD1P3IX: 1
|
||||
FD1S3AX: 22
|
||||
FD1S3IX: 4
|
||||
GSR: 1
|
||||
IB: 22
|
||||
IFS1P3DX: 1
|
||||
INV: 1
|
||||
OB: 40
|
||||
OFS1P3BX: 6
|
||||
OFS1P3DX: 27
|
||||
OFS1P3IX: 2
|
||||
ORCALUT4: 221
|
||||
PUR: 1
|
||||
VHI: 2
|
||||
VLO: 2
|
||||
Mapper successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:04s; Memory used current: 77MB peak: 211MB)
|
||||
|
||||
Process took 0h:00m:06s realtime, 0h:00m:04s cputime
|
||||
# Thu Sep 21 05:34:44 2023
|
||||
|
||||
###########################################################]
|
||||
|
|
@ -0,0 +1,215 @@
|
|||
|
||||
Loading design for application trce from file ram2e_lcmxo2_640hc_impl1_map.ncd.
|
||||
Design name: RAM2E
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-640HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.39.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
Setup and Hold Report
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
|
||||
Thu Sep 21 05:34:48 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
Report Information
|
||||
------------------
|
||||
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2E_LCMXO2_640HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.prf
|
||||
Design file: ram2e_lcmxo2_640hc_impl1_map.ncd
|
||||
Preference file: ram2e_lcmxo2_640hc_impl1.prf
|
||||
Device,speed: LCMXO2-640HC,4
|
||||
Report level: verbose report, limited to 1 item per preference
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
BLOCK ASYNCPATHS
|
||||
BLOCK RESETPATHS
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
================================================================================
|
||||
Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
|
||||
1491 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 58.471ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q FS[11] (from C14M_c +)
|
||||
Destination: FF Data in nRWE_0io (to C14M_c +)
|
||||
|
||||
Delay: 11.306ns (30.3% logic, 69.7% route), 7 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
11.306ns physical path delay SLICE_3 to nRWE_MGIOL meets
|
||||
69.930ns delay constraint less
|
||||
0.153ns DO_SET requirement (totaling 69.777ns) by 58.471ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path SLICE_3 to nRWE_MGIOL:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.452 SLICE_3.CLK to SLICE_3.Q0 SLICE_3 (from C14M_c)
|
||||
ROUTE 19 e 1.234 SLICE_3.Q0 to SLICE_64.A1 FS[11]
|
||||
CTOF_DEL --- 0.495 SLICE_64.A1 to SLICE_64.F1 SLICE_64
|
||||
ROUTE 4 e 1.234 SLICE_64.F1 to SLICE_97.D0 N_577
|
||||
CTOF_DEL --- 0.495 SLICE_97.D0 to SLICE_97.F0 SLICE_97
|
||||
ROUTE 3 e 1.234 SLICE_97.F0 to SLICE_75.D1 N_489
|
||||
CTOF_DEL --- 0.495 SLICE_75.D1 to SLICE_75.F1 SLICE_75
|
||||
ROUTE 3 e 0.480 SLICE_75.F1 to SLICE_75.A0 N_628
|
||||
CTOF_DEL --- 0.495 SLICE_75.A0 to SLICE_75.F0 SLICE_75
|
||||
ROUTE 2 e 1.234 SLICE_75.F0 to SLICE_71.C1 N_640
|
||||
CTOF_DEL --- 0.495 SLICE_71.C1 to SLICE_71.F1 SLICE_71
|
||||
ROUTE 1 e 1.234 SLICE_71.F1 to SLICE_115.A0 un1_nCS61_1_i
|
||||
CTOF_DEL --- 0.495 SLICE_115.A0 to SLICE_115.F0 SLICE_115
|
||||
ROUTE 1 e 1.234 SLICE_115.F0 to *WE_MGIOL.OPOS nRWE_r_0 (to C14M_c)
|
||||
--------
|
||||
11.306 (30.3% logic, 69.7% route), 7 logic levels.
|
||||
|
||||
Report: 87.268MHz is the maximum frequency for this preference.
|
||||
|
||||
Report Summary
|
||||
--------------
|
||||
----------------------------------------------------------------------------
|
||||
Preference | Constraint| Actual|Levels
|
||||
----------------------------------------------------------------------------
|
||||
| | |
|
||||
FREQUENCY PORT "C14M" 14.300000 MHz ; | 14.300 MHz| 87.268 MHz| 7
|
||||
| | |
|
||||
----------------------------------------------------------------------------
|
||||
|
||||
|
||||
All preferences were met.
|
||||
|
||||
|
||||
Clock Domains Analysis
|
||||
------------------------
|
||||
|
||||
Found 1 clocks:
|
||||
|
||||
Clock Domain: C14M_c Source: C14M.PAD Loads: 84
|
||||
Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
|
||||
|
||||
|
||||
Timing summary (Setup):
|
||||
---------------
|
||||
|
||||
Timing errors: 0 Score: 0
|
||||
Cumulative negative slack: 0
|
||||
|
||||
Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
|
||||
Thu Sep 21 05:34:48 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
Report Information
|
||||
------------------
|
||||
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2E_LCMXO2_640HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.prf
|
||||
Design file: ram2e_lcmxo2_640hc_impl1_map.ncd
|
||||
Preference file: ram2e_lcmxo2_640hc_impl1.prf
|
||||
Device,speed: LCMXO2-640HC,M
|
||||
Report level: verbose report, limited to 1 item per preference
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
BLOCK ASYNCPATHS
|
||||
BLOCK RESETPATHS
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
================================================================================
|
||||
Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
|
||||
1491 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 0.447ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q FS[0] (from C14M_c +)
|
||||
Destination: FF Data in FS[0] (to C14M_c +)
|
||||
|
||||
Delay: 0.434ns (53.9% logic, 46.1% route), 2 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
0.434ns physical path delay SLICE_0 to SLICE_0 meets
|
||||
-0.013ns DIN_HLD and
|
||||
0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path SLICE_0 to SLICE_0:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.133 SLICE_0.CLK to SLICE_0.Q1 SLICE_0 (from C14M_c)
|
||||
ROUTE 5 e 0.199 SLICE_0.Q1 to SLICE_0.A1 FS[0]
|
||||
CTOF_DEL --- 0.101 SLICE_0.A1 to SLICE_0.F1 SLICE_0
|
||||
ROUTE 1 e 0.001 SLICE_0.F1 to SLICE_0.DI1 FS_s[0] (to C14M_c)
|
||||
--------
|
||||
0.434 (53.9% logic, 46.1% route), 2 logic levels.
|
||||
|
||||
Report Summary
|
||||
--------------
|
||||
----------------------------------------------------------------------------
|
||||
Preference(MIN Delays) | Constraint| Actual|Levels
|
||||
----------------------------------------------------------------------------
|
||||
| | |
|
||||
FREQUENCY PORT "C14M" 14.300000 MHz ; | -| -| 2
|
||||
| | |
|
||||
----------------------------------------------------------------------------
|
||||
|
||||
|
||||
All preferences were met.
|
||||
|
||||
|
||||
Clock Domains Analysis
|
||||
------------------------
|
||||
|
||||
Found 1 clocks:
|
||||
|
||||
Clock Domain: C14M_c Source: C14M.PAD Loads: 84
|
||||
Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
|
||||
|
||||
|
||||
Timing summary (Hold):
|
||||
---------------
|
||||
|
||||
Timing errors: 0 Score: 0
|
||||
Cumulative negative slack: 0
|
||||
|
||||
Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage)
|
||||
|
||||
|
||||
|
||||
Timing summary (Setup and Hold):
|
||||
---------------
|
||||
|
||||
Timing errors: 0 (setup), 0 (hold)
|
||||
Score: 0 (setup), 0 (hold)
|
||||
Cumulative negative slack: 0 (0+0)
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,142 @@
|
|||
<HTML>
|
||||
<HEAD><TITLE>Bitgen Report</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Bgn"></A>BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Thu Sep 21 05:35:15 2023
|
||||
|
||||
|
||||
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC -w -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf
|
||||
|
||||
Loading design for application Bitgen from file RAM2E_LCMXO2_640HC_impl1.ncd.
|
||||
Design name: RAM2E
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-640HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application Bitgen from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.39.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
|
||||
Running DRC.
|
||||
DRC detected 0 errors and 0 warnings.
|
||||
Reading Preference File from RAM2E_LCMXO2_640HC_impl1.prf.
|
||||
|
||||
<A name="bgn_ps"></A>
|
||||
<B><U><big>Preference Summary:</big></U></B>
|
||||
|
||||
+---------------------------------+---------------------------------+
|
||||
| Preference | Current Setting |
|
||||
+---------------------------------+---------------------------------+
|
||||
| RamCfg | Reset** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MCCLK_FREQ | 2.08** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| CONFIG_SECURE | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| INBUF | ON** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| JTAG_PORT | ENABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SDM_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SLAVE_SPI_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MASTER_SPI_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| I2C_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MUX_CONFIGURATION_PORTS | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| CONFIGURATION | CFG** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| COMPRESS_CONFIG | ON** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MY_ASSP | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| ONE_TIME_PROGRAM | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| ENABLE_TRANSFR | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SHAREDEBRINIT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| BACKGROUND_RECONFIG | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
* Default setting.
|
||||
** The specified setting matches the default setting.
|
||||
|
||||
|
||||
Creating bit map...
|
||||
|
||||
Bitstream Status: Final Version 1.95.
|
||||
|
||||
Saving bit stream in "RAM2E_LCMXO2_640HC_impl1.bit".
|
||||
Total CPU Time: 4 secs
|
||||
Total REAL Time: 5 secs
|
||||
Peak Memory Usage: 267 MB
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
|
|
@ -0,0 +1,152 @@
|
|||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: R-2021.03L-SP1
|
||||
Install: C:\lscc\diamond\3.12\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
|
||||
# Written on Thu Sep 21 05:34:37 2023
|
||||
|
||||
##### DESIGN INFO #######################################################
|
||||
|
||||
Top View: "RAM2E"
|
||||
Constraint File(s): "\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc"
|
||||
|
||||
|
||||
|
||||
|
||||
##### SUMMARY ############################################################
|
||||
|
||||
Found 0 issues in 0 out of 1 constraints
|
||||
|
||||
|
||||
##### DETAILS ############################################################
|
||||
|
||||
|
||||
|
||||
Clock Relationships
|
||||
*******************
|
||||
|
||||
Starting Ending | rise to rise | fall to fall | rise to fall | fall to rise
|
||||
-----------------------------------------------------------------------------------------------------------------------------------
|
||||
System C14M | 69.841 | No paths | No paths | No paths
|
||||
C14M System | 69.841 | No paths | No paths | No paths
|
||||
C14M C14M | 69.841 | No paths | 34.920 | No paths
|
||||
===================================================================================================================================
|
||||
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
|
||||
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
|
||||
|
||||
|
||||
Unconstrained Start/End Points
|
||||
******************************
|
||||
|
||||
p:Ain[0]
|
||||
p:Ain[1]
|
||||
p:Ain[2]
|
||||
p:Ain[3]
|
||||
p:Ain[4]
|
||||
p:Ain[5]
|
||||
p:Ain[6]
|
||||
p:Ain[7]
|
||||
p:BA[0]
|
||||
p:BA[1]
|
||||
p:CKE
|
||||
p:DQMH
|
||||
p:DQML
|
||||
p:Din[0]
|
||||
p:Din[1]
|
||||
p:Din[2]
|
||||
p:Din[3]
|
||||
p:Din[4]
|
||||
p:Din[5]
|
||||
p:Din[6]
|
||||
p:Din[7]
|
||||
p:Dout[0]
|
||||
p:Dout[1]
|
||||
p:Dout[2]
|
||||
p:Dout[3]
|
||||
p:Dout[4]
|
||||
p:Dout[5]
|
||||
p:Dout[6]
|
||||
p:Dout[7]
|
||||
p:LED
|
||||
p:PHI1
|
||||
p:RA[0]
|
||||
p:RA[1]
|
||||
p:RA[2]
|
||||
p:RA[3]
|
||||
p:RA[4]
|
||||
p:RA[5]
|
||||
p:RA[6]
|
||||
p:RA[7]
|
||||
p:RA[8]
|
||||
p:RA[9]
|
||||
p:RA[10]
|
||||
p:RA[11]
|
||||
p:RD[0] (bidir end point)
|
||||
p:RD[0] (bidir start point)
|
||||
p:RD[1] (bidir end point)
|
||||
p:RD[1] (bidir start point)
|
||||
p:RD[2] (bidir end point)
|
||||
p:RD[2] (bidir start point)
|
||||
p:RD[3] (bidir end point)
|
||||
p:RD[3] (bidir start point)
|
||||
p:RD[4] (bidir end point)
|
||||
p:RD[4] (bidir start point)
|
||||
p:RD[5] (bidir end point)
|
||||
p:RD[5] (bidir start point)
|
||||
p:RD[6] (bidir end point)
|
||||
p:RD[6] (bidir start point)
|
||||
p:RD[7] (bidir end point)
|
||||
p:RD[7] (bidir start point)
|
||||
p:Vout[0]
|
||||
p:Vout[1]
|
||||
p:Vout[2]
|
||||
p:Vout[3]
|
||||
p:Vout[4]
|
||||
p:Vout[5]
|
||||
p:Vout[6]
|
||||
p:Vout[7]
|
||||
p:nC07X
|
||||
p:nCAS
|
||||
p:nCS
|
||||
p:nDOE
|
||||
p:nEN80
|
||||
p:nRAS
|
||||
p:nRWE
|
||||
p:nVOE
|
||||
p:nWE
|
||||
p:nWE80
|
||||
|
||||
|
||||
Inapplicable constraints
|
||||
************************
|
||||
|
||||
(none)
|
||||
|
||||
|
||||
Applicable constraints with issues
|
||||
**********************************
|
||||
|
||||
(none)
|
||||
|
||||
|
||||
Constraints with matching wildcard expressions
|
||||
**********************************************
|
||||
|
||||
(none)
|
||||
|
||||
|
||||
Library Report
|
||||
**************
|
||||
|
||||
|
||||
# End of Constraint Checker Report
|
||||
|
|
@ -0,0 +1,183 @@
|
|||
<HTML>
|
||||
<HEAD><TITLE>I/O Timing Report</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Top"></A><B><U><big>I/O Timing Report</big></U></B>
|
||||
Loading design for application iotiming from file ram2e_lcmxo2_640hc_impl1.ncd.
|
||||
Design name: RAM2E
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-640HC
|
||||
Package: TQFP100
|
||||
Performance: 5
|
||||
Package Status: Final Version 1.39.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
Loading design for application iotiming from file ram2e_lcmxo2_640hc_impl1.ncd.
|
||||
Design name: RAM2E
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-640HC
|
||||
Package: TQFP100
|
||||
Performance: 6
|
||||
Package Status: Final Version 1.39.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
Loading design for application iotiming from file ram2e_lcmxo2_640hc_impl1.ncd.
|
||||
Design name: RAM2E
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-640HC
|
||||
Package: TQFP100
|
||||
Performance: M
|
||||
Package Status: Final Version 1.39.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
// Design: RAM2E
|
||||
// Package: TQFP100
|
||||
// ncd File: ram2e_lcmxo2_640hc_impl1.ncd
|
||||
// Version: Diamond (64-bit) 3.12.1.454
|
||||
// Written on Thu Sep 21 05:35:10 2023
|
||||
// M: Minimum Performance Grade
|
||||
// iotiming RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml
|
||||
|
||||
I/O Timing Report (All units are in ns)
|
||||
|
||||
Worst Case Results across Performance Grades (M, 6, 5, 4):
|
||||
|
||||
// Input Setup and Hold Times
|
||||
|
||||
Port Clock Edge Setup Performance_Grade Hold Performance_Grade
|
||||
----------------------------------------------------------------------
|
||||
Ain[0] C14M R 0.502 4 0.868 4
|
||||
Ain[1] C14M R 2.364 4 -0.126 M
|
||||
Ain[2] C14M R 2.421 4 -0.129 M
|
||||
Ain[3] C14M R 0.574 4 0.786 4
|
||||
Ain[4] C14M R 1.452 4 0.140 M
|
||||
Ain[5] C14M R 2.076 4 -0.039 M
|
||||
Ain[6] C14M R 1.515 4 0.124 M
|
||||
Ain[7] C14M R 2.270 4 -0.095 M
|
||||
Din[0] C14M R 9.252 4 1.162 4
|
||||
Din[1] C14M R 8.868 4 0.657 4
|
||||
Din[2] C14M R 8.368 4 0.864 4
|
||||
Din[3] C14M R 8.749 4 1.339 4
|
||||
Din[4] C14M R 9.095 4 0.770 4
|
||||
Din[5] C14M R 8.195 4 1.176 4
|
||||
Din[6] C14M R 6.162 4 0.760 4
|
||||
Din[7] C14M R 7.060 4 1.093 4
|
||||
PHI1 C14M R 2.045 4 3.047 4
|
||||
RD[0] C14M F 0.267 4 0.866 4
|
||||
RD[1] C14M F 0.173 4 1.383 4
|
||||
RD[2] C14M F 0.924 4 1.018 4
|
||||
RD[3] C14M F 0.267 4 0.866 4
|
||||
RD[4] C14M F 0.173 4 0.937 4
|
||||
RD[5] C14M F 0.267 4 0.866 4
|
||||
RD[6] C14M F 0.766 4 0.866 4
|
||||
RD[7] C14M F 0.267 4 1.312 4
|
||||
nC07X C14M R 0.077 4 1.144 4
|
||||
nEN80 C14M R 6.415 4 -0.286 M
|
||||
nWE C14M R 0.691 4 0.684 4
|
||||
nWE80 C14M R 2.845 4 -0.260 M
|
||||
|
||||
|
||||
// Clock to Output Delay
|
||||
|
||||
Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
|
||||
------------------------------------------------------------------------
|
||||
BA[0] C14M R 8.629 4 2.885 M
|
||||
BA[1] C14M R 8.629 4 2.885 M
|
||||
CKE C14M R 8.629 4 2.885 M
|
||||
DQMH C14M R 8.609 4 2.892 M
|
||||
DQML C14M R 8.609 4 2.892 M
|
||||
Dout[0] C14M F 8.955 4 3.164 M
|
||||
Dout[1] C14M F 8.955 4 3.164 M
|
||||
Dout[2] C14M F 8.944 4 3.158 M
|
||||
Dout[3] C14M F 8.955 4 3.164 M
|
||||
Dout[4] C14M F 8.944 4 3.158 M
|
||||
Dout[5] C14M F 8.944 4 3.158 M
|
||||
Dout[6] C14M F 8.955 4 3.164 M
|
||||
Dout[7] C14M F 8.955 4 3.164 M
|
||||
LED C14M R 19.941 4 8.191 M
|
||||
RA[0] C14M R 10.013 4 3.186 M
|
||||
RA[10] C14M R 8.629 4 2.885 M
|
||||
RA[11] C14M R 8.629 4 2.885 M
|
||||
RA[1] C14M R 8.695 4 2.890 M
|
||||
RA[2] C14M R 8.695 4 2.890 M
|
||||
RA[3] C14M R 10.013 4 3.186 M
|
||||
RA[4] C14M R 8.695 4 2.890 M
|
||||
RA[5] C14M R 8.695 4 2.890 M
|
||||
RA[6] C14M R 8.695 4 2.890 M
|
||||
RA[7] C14M R 8.695 4 2.890 M
|
||||
RA[8] C14M R 8.629 4 2.885 M
|
||||
RA[9] C14M R 8.629 4 2.885 M
|
||||
Vout[0] C14M F 9.553 4 3.402 M
|
||||
Vout[1] C14M F 9.553 4 3.402 M
|
||||
Vout[2] C14M F 9.553 4 3.402 M
|
||||
Vout[3] C14M F 9.553 4 3.402 M
|
||||
Vout[4] C14M F 9.553 4 3.402 M
|
||||
Vout[5] C14M F 9.553 4 3.402 M
|
||||
Vout[6] C14M F 9.553 4 3.402 M
|
||||
Vout[7] C14M F 9.553 4 3.402 M
|
||||
nCAS C14M R 8.629 4 2.885 M
|
||||
nCS C14M R 8.629 4 2.885 M
|
||||
nDOE C14M R 11.976 4 3.776 M
|
||||
nRAS C14M R 8.629 4 2.885 M
|
||||
nRWE C14M R 8.629 4 2.885 M
|
||||
WARNING: you must also run trce with hold speed: 4
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,485 @@
|
|||
<HTML>
|
||||
<HEAD><TITLE>Project Summary</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
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font-weight: bold;
margin-top: 24px;
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border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Mrp"></A>
|
||||
Lattice Mapping Report File for Design Module 'RAM2E'
|
||||
|
||||
|
||||
|
||||
<A name="mrp_di"></A><B><U><big>Design Information</big></U></B>
|
||||
|
||||
Command line: map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial
|
||||
RAM2E_LCMXO2_640HC_impl1.ngd -o RAM2E_LCMXO2_640HC_impl1_map.ncd -pr
|
||||
RAM2E_LCMXO2_640HC_impl1.prf -mp RAM2E_LCMXO2_640HC_impl1.mrp -lpf //Mac/iC
|
||||
loud/Repos/RAM2E/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_synplify.
|
||||
lpf -lpf //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf -c 0 -gui -msgset
|
||||
//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml
|
||||
Target Vendor: LATTICE
|
||||
Target Device: LCMXO2-640HCTQFP100
|
||||
Target Performance: 4
|
||||
Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454
|
||||
Mapped on: 09/21/23 05:34:46
|
||||
|
||||
|
||||
<A name="mrp_ds"></A><B><U><big>Design Summary</big></U></B>
|
||||
Number of registers: 111 out of 877 (13%)
|
||||
PFU registers: 75 out of 640 (12%)
|
||||
PIO registers: 36 out of 237 (15%)
|
||||
Number of SLICEs: 120 out of 320 (38%)
|
||||
SLICEs as Logic/ROM: 120 out of 320 (38%)
|
||||
SLICEs as RAM: 0 out of 240 (0%)
|
||||
SLICEs as Carry: 9 out of 320 (3%)
|
||||
Number of LUT4s: 239 out of 640 (37%)
|
||||
Number used as logic LUTs: 221
|
||||
Number used as distributed RAM: 0
|
||||
Number used as ripple logic: 18
|
||||
Number used as shift registers: 0
|
||||
Number of PIO sites used: 70 + 4(JTAG) out of 79 (94%)
|
||||
Number of block RAMs: 0 out of 2 (0%)
|
||||
Number of GSRs: 0 out of 1 (0%)
|
||||
EFB used : Yes
|
||||
JTAG used : No
|
||||
Readback used : No
|
||||
Oscillator used : No
|
||||
Startup used : No
|
||||
POR : On
|
||||
Bandgap : On
|
||||
Number of Power Controller: 0 out of 1 (0%)
|
||||
Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
|
||||
Number of DCCA: 0 out of 8 (0%)
|
||||
Number of DCMA: 0 out of 2 (0%)
|
||||
Notes:-
|
||||
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
|
||||
distributed RAMs) + 2*(Number of ripple logic)
|
||||
2. Number of logic LUT4s does not include count of distributed RAM and
|
||||
ripple logic.
|
||||
Number of clocks: 1
|
||||
Net C14M_c: 84 loads, 68 rising, 16 falling (Driver: PIO C14M )
|
||||
Number of Clock Enables: 11
|
||||
Net wb_adr_0_sqmuxa_i: 1 loads, 1 LSLICEs
|
||||
Net N_576_i: 17 loads, 9 LSLICEs
|
||||
Net LEDEN13: 4 loads, 4 LSLICEs
|
||||
Net nCS61: 1 loads, 1 LSLICEs
|
||||
Net Vout3: 8 loads, 0 LSLICEs
|
||||
Net S_RNII9DO1_1[1]: 7 loads, 1 LSLICEs
|
||||
|
||||
Net un1_wb_cyc_stb_0_sqmuxa_1_i[0]: 1 loads, 1 LSLICEs
|
||||
Net un1_wb_adr_0_sqmuxa_2_i[0]: 8 loads, 8 LSLICEs
|
||||
Net N_104: 1 loads, 1 LSLICEs
|
||||
Net N_88: 4 loads, 4 LSLICEs
|
||||
Net un1_LEDEN_0_sqmuxa_1_i_0[0]: 1 loads, 1 LSLICEs
|
||||
Number of LSRs: 5
|
||||
Net un1_CS_0_sqmuxa_i: 2 loads, 2 LSLICEs
|
||||
Net S[2]: 1 loads, 1 LSLICEs
|
||||
Net N_566_i: 2 loads, 0 LSLICEs
|
||||
Net wb_rst: 1 loads, 0 LSLICEs
|
||||
Net S_RNII9DO1[1]: 1 loads, 1 LSLICEs
|
||||
Number of nets driven by tri-state buffers: 0
|
||||
Top 10 highest fanout non-clock nets:
|
||||
Net S[2]: 48 loads
|
||||
Net S[3]: 48 loads
|
||||
Net S[0]: 30 loads
|
||||
Net FS[12]: 22 loads
|
||||
Net FS[9]: 21 loads
|
||||
Net S[1]: 21 loads
|
||||
Net FS[10]: 20 loads
|
||||
Net FS[11]: 19 loads
|
||||
Net RWSel: 19 loads
|
||||
Net FS[13]: 17 loads
|
||||
|
||||
|
||||
|
||||
|
||||
Number of warnings: 1
|
||||
Number of errors: 0
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<A name="mrp_dwe"></A><B><U><big>Design Errors/Warnings</big></U></B>
|
||||
|
||||
WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
||||
temporarily disable certain features of the device including Power
|
||||
Controller, GSR, Hardened User SPI Port, Hardened Primary User I2C Port.
|
||||
Functionality is restored after the Flash Memory (UFM/Configuration)
|
||||
Interface is disabled using Disable Configuration Interface command 0x26
|
||||
followed by Bypass command 0xFF.
|
||||
|
||||
|
||||
|
||||
<A name="mrp_ioa"></A><B><U><big>IO (PIO) Attributes</big></U></B>
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| IO Name | Direction | Levelmode | IO |
|
||||
| | | IO_TYPE | Register |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[0] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| LED | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| C14M | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| DQMH | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
| DQML | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[7] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[6] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[5] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[4] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[3] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[2] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[1] | BIDIR | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[11] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[10] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[9] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[8] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[7] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[6] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[5] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[4] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[3] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[2] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[1] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[0] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| BA[1] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| BA[0] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRWE | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nCAS | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRAS | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nCS | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| CKE | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nVOE | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
| Vout[7] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Vout[6] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Vout[5] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Vout[4] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Vout[3] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Vout[2] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Vout[1] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Vout[0] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nDOE | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[7] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[6] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[5] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[4] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[3] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[2] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[1] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[0] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[7] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[6] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[5] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[4] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[3] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[2] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[1] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[0] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Ain[7] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Ain[6] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Ain[5] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
| Ain[4] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Ain[3] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Ain[2] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Ain[1] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Ain[0] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nC07X | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nEN80 | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nWE80 | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nWE | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| PHI1 | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
|
||||
|
||||
<A name="mrp_rm"></A><B><U><big>Removed logic</big></U></B>
|
||||
|
||||
Block GSR_INST undriven or does not drive anything - clipped.
|
||||
Signal Dout_0_.CN was merged into signal C14M_c
|
||||
Signal GND undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/VCC undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/GND undriven or does not drive anything - clipped.
|
||||
Signal FS_s_0_S1[15] undriven or does not drive anything - clipped.
|
||||
Signal FS_s_0_COUT[15] undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/CFGWAKE undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wbc_ufm_irq undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/TCOC undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/TCINT undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIIRQO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPICSNEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMOSIEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMOSIO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMISOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMISOO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPISCKEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPISCKO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SDAOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
|
||||
|
||||
Signal ufmefb/I2C2SCLOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SDAOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SCLOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO4 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLWEO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLL1STBO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLL0STBO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLRSTO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLCLKO undriven or does not drive anything - clipped.
|
||||
Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped.
|
||||
Signal N_1 undriven or does not drive anything - clipped.
|
||||
Block Vout_0_.CN was optimized away.
|
||||
Block GND was optimized away.
|
||||
Block ufmefb/VCC was optimized away.
|
||||
Block ufmefb/GND was optimized away.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<A name="mrp_efb"></A><B><U><big>Embedded Functional Block Connection Summary</big></U></B>
|
||||
|
||||
Desired WISHBONE clock frequency: 14.4 MHz
|
||||
Clock source: C14M_c
|
||||
Reset source: wb_rst
|
||||
Functions mode:
|
||||
I2C #1 (Primary) Function: DISABLED
|
||||
I2C #2 (Secondary) Function: DISABLED
|
||||
SPI Function: DISABLED
|
||||
Timer/Counter Function: DISABLED
|
||||
Timer/Counter Mode: WB
|
||||
UFM Connection: ENABLED
|
||||
PLL0 Connection: DISABLED
|
||||
PLL1 Connection: DISABLED
|
||||
I2C Function Summary:
|
||||
--------------------
|
||||
None
|
||||
SPI Function Summary:
|
||||
--------------------
|
||||
None
|
||||
Timer/Counter Function Summary:
|
||||
------------------------------
|
||||
|
||||
None
|
||||
UFM Function Summary:
|
||||
--------------------
|
||||
UFM Utilization: General Purpose Flash Memory
|
||||
Initialized UFM Pages: 1 Pages (1*128 Bits)
|
||||
Available General
|
||||
Purpose Flash Memory: 191 Pages (191*128 Bits)
|
||||
|
||||
EBR Blocks with Unique
|
||||
Initialization Data: 0
|
||||
|
||||
WID EBR Instance
|
||||
--- ------------
|
||||
|
||||
|
||||
|
||||
|
||||
<A name="mrp_asic"></A><B><U><big>ASIC Components</big></U></B>
|
||||
---------------
|
||||
|
||||
Instance Name: ufmefb/EFBInst_0
|
||||
Type: EFB
|
||||
|
||||
|
||||
|
||||
<A name="mrp_runtime"></A><B><U><big>Run Time and Memory Usage</big></U></B>
|
||||
-------------------------
|
||||
|
||||
Total CPU Time: 0 secs
|
||||
Total REAL Time: 0 secs
|
||||
Peak Memory Usage: 58 MB
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights
|
||||
reserved.
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
|
|
@ -0,0 +1,352 @@
|
|||
<HTML>
|
||||
<HEAD><TITLE>PAD Specification File</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Pad"></A>PAD Specification File
|
||||
***************************
|
||||
|
||||
PART TYPE: LCMXO2-640HC
|
||||
Performance Grade: 4
|
||||
PACKAGE: TQFP100
|
||||
Package Status: Final Version 1.39
|
||||
|
||||
Thu Sep 21 05:35:00 2023
|
||||
|
||||
Pinout by Port Name:
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties |
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
| Ain[0] | 3/3 | LVCMOS33_IN | PL2C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Ain[1] | 2/3 | LVCMOS33_IN | PL2B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Ain[2] | 7/3 | LVCMOS33_IN | PL3A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Ain[3] | 4/3 | LVCMOS33_IN | PL2D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Ain[4] | 78/0 | LVCMOS33_IN | PT11A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Ain[5] | 84/0 | LVCMOS33_IN | PT10A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Ain[6] | 86/0 | LVCMOS33_IN | PT9C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Ain[7] | 8/3 | LVCMOS33_IN | PL3B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| BA[0] | 58/1 | LVCMOS33_OUT | PR6C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| BA[1] | 60/1 | LVCMOS33_OUT | PR6A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| C14M | 62/1 | LVCMOS33_IN | PR5D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| CKE | 53/1 | LVCMOS33_OUT | PR7B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| DQMH | 49/2 | LVCMOS33_OUT | PB14D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| DQML | 48/2 | LVCMOS33_OUT | PB14C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Din[0] | 96/0 | LVCMOS33_IN | PT6D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[1] | 97/0 | LVCMOS33_IN | PT6C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[2] | 98/0 | LVCMOS33_IN | PT6B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[3] | 9/3 | LVCMOS33_IN | PL3C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[4] | 1/3 | LVCMOS33_IN | PL2A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[5] | 99/0 | LVCMOS33_IN | PT6A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[6] | 88/0 | LVCMOS33_IN | PT9A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[7] | 87/0 | LVCMOS33_IN | PT9B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Dout[0] | 30/2 | LVCMOS33_OUT | PB4D | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[1] | 27/2 | LVCMOS33_OUT | PB4A | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[2] | 25/3 | LVCMOS33_OUT | PL7D | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[3] | 28/2 | LVCMOS33_OUT | PB4B | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[4] | 24/3 | LVCMOS33_OUT | PL7C | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[5] | 21/3 | LVCMOS33_OUT | PL7B | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[6] | 31/2 | LVCMOS33_OUT | PB6A | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[7] | 32/2 | LVCMOS33_OUT | PB6B | | | DRIVE:4mA SLEW:FAST |
|
||||
| LED | 35/2 | LVCMOS33_OUT | PB6D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| PHI1 | 85/0 | LVCMOS33_IN | PT9D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| RA[0] | 66/1 | LVCMOS33_OUT | PR3D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[10] | 64/1 | LVCMOS33_OUT | PR5B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[11] | 59/1 | LVCMOS33_OUT | PR6B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[1] | 68/1 | LVCMOS33_OUT | PR3B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[2] | 70/1 | LVCMOS33_OUT | PR2D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[3] | 74/1 | LVCMOS33_OUT | PR2B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[4] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[5] | 71/1 | LVCMOS33_OUT | PR2C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[6] | 69/1 | LVCMOS33_OUT | PR3A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[7] | 67/1 | LVCMOS33_OUT | PR3C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[9] | 63/1 | LVCMOS33_OUT | PR5C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RD[0] | 36/2 | LVCMOS33_BIDI | PB10A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[1] | 37/2 | LVCMOS33_BIDI | PB10B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[2] | 38/2 | LVCMOS33_BIDI | PB10C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[3] | 39/2 | LVCMOS33_BIDI | PB10D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[4] | 40/2 | LVCMOS33_BIDI | PB12A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[5] | 41/2 | LVCMOS33_BIDI | PB12B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[6] | 42/2 | LVCMOS33_BIDI | PB12C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[7] | 43/2 | LVCMOS33_BIDI | PB12D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| Vout[0] | 18/3 | LVCMOS33_OUT | PL6C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Vout[1] | 15/3 | LVCMOS33_OUT | PL5D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Vout[2] | 17/3 | LVCMOS33_OUT | PL6B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Vout[3] | 13/3 | LVCMOS33_OUT | PL5B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Vout[4] | 19/3 | LVCMOS33_OUT | PL6D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Vout[5] | 16/3 | LVCMOS33_OUT | PL6A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Vout[6] | 14/3 | LVCMOS33_OUT | PL5C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| Vout[7] | 12/3 | LVCMOS33_OUT | PL5A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nC07X | 34/2 | LVCMOS33_IN | PB6C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nCAS | 52/1 | LVCMOS33_OUT | PR7C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nCS | 57/1 | LVCMOS33_OUT | PR6D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nDOE | 20/3 | LVCMOS33_OUT | PL7A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nEN80 | 82/0 | LVCMOS33_IN | PT10C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nRAS | 54/1 | LVCMOS33_OUT | PR7A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nRWE | 51/1 | LVCMOS33_OUT | PR7D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nVOE | 10/3 | LVCMOS33_OUT | PL3D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nWE | 29/2 | LVCMOS33_IN | PB4C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nWE80 | 83/0 | LVCMOS33_IN | PT10B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
|
||||
Vccio by Bank:
|
||||
+------+-------+
|
||||
| Bank | Vccio |
|
||||
+------+-------+
|
||||
| 0 | 3.3V |
|
||||
| 1 | 3.3V |
|
||||
| 2 | 3.3V |
|
||||
| 3 | 3.3V |
|
||||
+------+-------+
|
||||
|
||||
|
||||
<A name="pad_vref"></A><B><U><big>Vref by Bank:</big></U></B>
|
||||
+------+-----+-----------------+---------+
|
||||
| Vref | Pin | Bank # / Vref # | Load(s) |
|
||||
+------+-----+-----------------+---------+
|
||||
+------+-----+-----------------+---------+
|
||||
|
||||
<A name="pad_pin"></A><B><U><big>Pinout by Pin Number:</big></U></B>
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable |
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
| 1/3 | Din[4] | LOCATED | LVCMOS33_IN | PL2A | | | |
|
||||
| 2/3 | Ain[1] | LOCATED | LVCMOS33_IN | PL2B | | | |
|
||||
| 3/3 | Ain[0] | LOCATED | LVCMOS33_IN | PL2C | PCLKT3_2 | | |
|
||||
| 4/3 | Ain[3] | LOCATED | LVCMOS33_IN | PL2D | PCLKC3_2 | | |
|
||||
| 7/3 | Ain[2] | LOCATED | LVCMOS33_IN | PL3A | | | |
|
||||
| 8/3 | Ain[7] | LOCATED | LVCMOS33_IN | PL3B | | | |
|
||||
| 9/3 | Din[3] | LOCATED | LVCMOS33_IN | PL3C | | | |
|
||||
| 10/3 | nVOE | LOCATED | LVCMOS33_OUT | PL3D | | | |
|
||||
| 12/3 | Vout[7] | LOCATED | LVCMOS33_OUT | PL5A | PCLKT3_1 | | |
|
||||
| 13/3 | Vout[3] | LOCATED | LVCMOS33_OUT | PL5B | PCLKC3_1 | | |
|
||||
| 14/3 | Vout[6] | LOCATED | LVCMOS33_OUT | PL5C | | | |
|
||||
| 15/3 | Vout[1] | LOCATED | LVCMOS33_OUT | PL5D | | | |
|
||||
| 16/3 | Vout[5] | LOCATED | LVCMOS33_OUT | PL6A | | | |
|
||||
| 17/3 | Vout[2] | LOCATED | LVCMOS33_OUT | PL6B | | | |
|
||||
| 18/3 | Vout[0] | LOCATED | LVCMOS33_OUT | PL6C | | | |
|
||||
| 19/3 | Vout[4] | LOCATED | LVCMOS33_OUT | PL6D | | | |
|
||||
| 20/3 | nDOE | LOCATED | LVCMOS33_OUT | PL7A | PCLKT3_0 | | |
|
||||
| 21/3 | Dout[5] | LOCATED | LVCMOS33_OUT | PL7B | PCLKC3_0 | | |
|
||||
| 24/3 | Dout[4] | LOCATED | LVCMOS33_OUT | PL7C | | | |
|
||||
| 25/3 | Dout[2] | LOCATED | LVCMOS33_OUT | PL7D | | | |
|
||||
| 27/2 | Dout[1] | LOCATED | LVCMOS33_OUT | PB4A | CSSPIN | | |
|
||||
| 28/2 | Dout[3] | LOCATED | LVCMOS33_OUT | PB4B | | | |
|
||||
| 29/2 | nWE | LOCATED | LVCMOS33_IN | PB4C | | | |
|
||||
| 30/2 | Dout[0] | LOCATED | LVCMOS33_OUT | PB4D | | | |
|
||||
| 31/2 | Dout[6] | LOCATED | LVCMOS33_OUT | PB6A | MCLK/CCLK | | |
|
||||
| 32/2 | Dout[7] | LOCATED | LVCMOS33_OUT | PB6B | SO/SPISO | | |
|
||||
| 34/2 | nC07X | LOCATED | LVCMOS33_IN | PB6C | PCLKT2_0 | | |
|
||||
| 35/2 | LED | LOCATED | LVCMOS33_OUT | PB6D | PCLKC2_0 | | |
|
||||
| 36/2 | RD[0] | LOCATED | LVCMOS33_BIDI | PB10A | | | |
|
||||
| 37/2 | RD[1] | LOCATED | LVCMOS33_BIDI | PB10B | | | |
|
||||
| 38/2 | RD[2] | LOCATED | LVCMOS33_BIDI | PB10C | PCLKT2_1 | | |
|
||||
| 39/2 | RD[3] | LOCATED | LVCMOS33_BIDI | PB10D | PCLKC2_1 | | |
|
||||
| 40/2 | RD[4] | LOCATED | LVCMOS33_BIDI | PB12A | | | |
|
||||
| 41/2 | RD[5] | LOCATED | LVCMOS33_BIDI | PB12B | | | |
|
||||
| 42/2 | RD[6] | LOCATED | LVCMOS33_BIDI | PB12C | | | |
|
||||
| 43/2 | RD[7] | LOCATED | LVCMOS33_BIDI | PB12D | | | |
|
||||
| 45/2 | unused, PULL:DOWN | | | PB14A | | | |
|
||||
| 47/2 | unused, PULL:DOWN | | | PB14B | | | |
|
||||
| 48/2 | DQML | LOCATED | LVCMOS33_OUT | PB14C | SN | | |
|
||||
| 49/2 | DQMH | LOCATED | LVCMOS33_OUT | PB14D | SI/SISPI | | |
|
||||
| 51/1 | nRWE | LOCATED | LVCMOS33_OUT | PR7D | | | |
|
||||
| 52/1 | nCAS | LOCATED | LVCMOS33_OUT | PR7C | | | |
|
||||
| 53/1 | CKE | LOCATED | LVCMOS33_OUT | PR7B | | | |
|
||||
| 54/1 | nRAS | LOCATED | LVCMOS33_OUT | PR7A | | | |
|
||||
| 57/1 | nCS | LOCATED | LVCMOS33_OUT | PR6D | | | |
|
||||
| 58/1 | BA[0] | LOCATED | LVCMOS33_OUT | PR6C | | | |
|
||||
| 59/1 | RA[11] | LOCATED | LVCMOS33_OUT | PR6B | | | |
|
||||
| 60/1 | BA[1] | LOCATED | LVCMOS33_OUT | PR6A | | | |
|
||||
| 62/1 | C14M | LOCATED | LVCMOS33_IN | PR5D | PCLKC1_0 | | |
|
||||
| 63/1 | RA[9] | LOCATED | LVCMOS33_OUT | PR5C | PCLKT1_0 | | |
|
||||
| 64/1 | RA[10] | LOCATED | LVCMOS33_OUT | PR5B | | | |
|
||||
| 65/1 | RA[8] | LOCATED | LVCMOS33_OUT | PR5A | | | |
|
||||
| 66/1 | RA[0] | LOCATED | LVCMOS33_OUT | PR3D | | | |
|
||||
| 67/1 | RA[7] | LOCATED | LVCMOS33_OUT | PR3C | | | |
|
||||
| 68/1 | RA[1] | LOCATED | LVCMOS33_OUT | PR3B | | | |
|
||||
| 69/1 | RA[6] | LOCATED | LVCMOS33_OUT | PR3A | | | |
|
||||
| 70/1 | RA[2] | LOCATED | LVCMOS33_OUT | PR2D | | | |
|
||||
| 71/1 | RA[5] | LOCATED | LVCMOS33_OUT | PR2C | | | |
|
||||
| 74/1 | RA[3] | LOCATED | LVCMOS33_OUT | PR2B | | | |
|
||||
| 75/1 | RA[4] | LOCATED | LVCMOS33_OUT | PR2A | | | |
|
||||
| 76/0 | unused, PULL:DOWN | | | PT11D | DONE | | |
|
||||
| 77/0 | unused, PULL:DOWN | | | PT11C | INITN | | |
|
||||
| 78/0 | Ain[4] | LOCATED | LVCMOS33_IN | PT11A | | | |
|
||||
| 81/0 | unused, PULL:DOWN | | | PT10D | PROGRAMN | | |
|
||||
| 82/0 | nEN80 | LOCATED | LVCMOS33_IN | PT10C | JTAGENB | | |
|
||||
| 83/0 | nWE80 | LOCATED | LVCMOS33_IN | PT10B | | | |
|
||||
| 84/0 | Ain[5] | LOCATED | LVCMOS33_IN | PT10A | | | |
|
||||
| 85/0 | PHI1 | LOCATED | LVCMOS33_IN | PT9D | SDA/PCLKC0_0 | | |
|
||||
| 86/0 | Ain[6] | LOCATED | LVCMOS33_IN | PT9C | SCL/PCLKT0_0 | | |
|
||||
| 87/0 | Din[7] | LOCATED | LVCMOS33_IN | PT9B | PCLKC0_1 | | |
|
||||
| 88/0 | Din[6] | LOCATED | LVCMOS33_IN | PT9A | PCLKT0_1 | | |
|
||||
| 90/0 | Reserved: sysCONFIG | | | PT7D | TMS | | |
|
||||
| 91/0 | Reserved: sysCONFIG | | | PT7C | TCK | | |
|
||||
| 94/0 | Reserved: sysCONFIG | | | PT7B | TDI | | |
|
||||
| 95/0 | Reserved: sysCONFIG | | | PT7A | TDO | | |
|
||||
| 96/0 | Din[0] | LOCATED | LVCMOS33_IN | PT6D | | | |
|
||||
| 97/0 | Din[1] | LOCATED | LVCMOS33_IN | PT6C | | | |
|
||||
| 98/0 | Din[2] | LOCATED | LVCMOS33_IN | PT6B | | | |
|
||||
| 99/0 | Din[5] | LOCATED | LVCMOS33_IN | PT6A | | | |
|
||||
| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | |
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
|
||||
sysCONFIG Pins:
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode |
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
| PT7D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP |
|
||||
| PT7C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down |
|
||||
| PT7B | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP |
|
||||
| PT7A | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP |
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
|
||||
Dedicated sysCONFIG Pins:
|
||||
|
||||
|
||||
List of All Pins' Locate Preferences Based on Final Placement After PAR
|
||||
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste):
|
||||
|
||||
LOCATE COMP "Ain[0]" SITE "3";
|
||||
LOCATE COMP "Ain[1]" SITE "2";
|
||||
LOCATE COMP "Ain[2]" SITE "7";
|
||||
LOCATE COMP "Ain[3]" SITE "4";
|
||||
LOCATE COMP "Ain[4]" SITE "78";
|
||||
LOCATE COMP "Ain[5]" SITE "84";
|
||||
LOCATE COMP "Ain[6]" SITE "86";
|
||||
LOCATE COMP "Ain[7]" SITE "8";
|
||||
LOCATE COMP "BA[0]" SITE "58";
|
||||
LOCATE COMP "BA[1]" SITE "60";
|
||||
LOCATE COMP "C14M" SITE "62";
|
||||
LOCATE COMP "CKE" SITE "53";
|
||||
LOCATE COMP "DQMH" SITE "49";
|
||||
LOCATE COMP "DQML" SITE "48";
|
||||
LOCATE COMP "Din[0]" SITE "96";
|
||||
LOCATE COMP "Din[1]" SITE "97";
|
||||
LOCATE COMP "Din[2]" SITE "98";
|
||||
LOCATE COMP "Din[3]" SITE "9";
|
||||
LOCATE COMP "Din[4]" SITE "1";
|
||||
LOCATE COMP "Din[5]" SITE "99";
|
||||
LOCATE COMP "Din[6]" SITE "88";
|
||||
LOCATE COMP "Din[7]" SITE "87";
|
||||
LOCATE COMP "Dout[0]" SITE "30";
|
||||
LOCATE COMP "Dout[1]" SITE "27";
|
||||
LOCATE COMP "Dout[2]" SITE "25";
|
||||
LOCATE COMP "Dout[3]" SITE "28";
|
||||
LOCATE COMP "Dout[4]" SITE "24";
|
||||
LOCATE COMP "Dout[5]" SITE "21";
|
||||
LOCATE COMP "Dout[6]" SITE "31";
|
||||
LOCATE COMP "Dout[7]" SITE "32";
|
||||
LOCATE COMP "LED" SITE "35";
|
||||
LOCATE COMP "PHI1" SITE "85";
|
||||
LOCATE COMP "RA[0]" SITE "66";
|
||||
LOCATE COMP "RA[10]" SITE "64";
|
||||
LOCATE COMP "RA[11]" SITE "59";
|
||||
LOCATE COMP "RA[1]" SITE "68";
|
||||
LOCATE COMP "RA[2]" SITE "70";
|
||||
LOCATE COMP "RA[3]" SITE "74";
|
||||
LOCATE COMP "RA[4]" SITE "75";
|
||||
LOCATE COMP "RA[5]" SITE "71";
|
||||
LOCATE COMP "RA[6]" SITE "69";
|
||||
LOCATE COMP "RA[7]" SITE "67";
|
||||
LOCATE COMP "RA[8]" SITE "65";
|
||||
LOCATE COMP "RA[9]" SITE "63";
|
||||
LOCATE COMP "RD[0]" SITE "36";
|
||||
LOCATE COMP "RD[1]" SITE "37";
|
||||
LOCATE COMP "RD[2]" SITE "38";
|
||||
LOCATE COMP "RD[3]" SITE "39";
|
||||
LOCATE COMP "RD[4]" SITE "40";
|
||||
LOCATE COMP "RD[5]" SITE "41";
|
||||
LOCATE COMP "RD[6]" SITE "42";
|
||||
LOCATE COMP "RD[7]" SITE "43";
|
||||
LOCATE COMP "Vout[0]" SITE "18";
|
||||
LOCATE COMP "Vout[1]" SITE "15";
|
||||
LOCATE COMP "Vout[2]" SITE "17";
|
||||
LOCATE COMP "Vout[3]" SITE "13";
|
||||
LOCATE COMP "Vout[4]" SITE "19";
|
||||
LOCATE COMP "Vout[5]" SITE "16";
|
||||
LOCATE COMP "Vout[6]" SITE "14";
|
||||
LOCATE COMP "Vout[7]" SITE "12";
|
||||
LOCATE COMP "nC07X" SITE "34";
|
||||
LOCATE COMP "nCAS" SITE "52";
|
||||
LOCATE COMP "nCS" SITE "57";
|
||||
LOCATE COMP "nDOE" SITE "20";
|
||||
LOCATE COMP "nEN80" SITE "82";
|
||||
LOCATE COMP "nRAS" SITE "54";
|
||||
LOCATE COMP "nRWE" SITE "51";
|
||||
LOCATE COMP "nVOE" SITE "10";
|
||||
LOCATE COMP "nWE" SITE "29";
|
||||
LOCATE COMP "nWE80" SITE "83";
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Thu Sep 21 05:35:04 2023
|
||||
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
|
|
@ -0,0 +1,295 @@
|
|||
<HTML>
|
||||
<HEAD><TITLE>Place & Route Report</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Par"></A>PAR: Place And Route Diamond (64-bit) 3.12.1.454.
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Thu Sep 21 05:34:51 2023
|
||||
|
||||
C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2E_LCMXO2_640HC_impl1.p2t
|
||||
RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.dir
|
||||
RAM2E_LCMXO2_640HC_impl1.prf -gui -msgset
|
||||
//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml
|
||||
|
||||
|
||||
Preference file: RAM2E_LCMXO2_640HC_impl1.prf.
|
||||
|
||||
<A name="par_cts"></A><B><U><big>Cost Table Summary</big></U></B>
|
||||
Level/ Number Worst Timing Worst Timing Run NCD
|
||||
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
|
||||
---------- -------- ----- ------ ----------- ----------- ---- ------
|
||||
5_1 * 0 57.366 0 0.346 0 15 Completed
|
||||
* : Design saved.
|
||||
|
||||
Total (real) run time for 1-seed: 15 secs
|
||||
|
||||
par done!
|
||||
|
||||
Note: user must run 'Trace' for timing closure signoff.
|
||||
|
||||
Lattice Place and Route Report for Design "RAM2E_LCMXO2_640HC_impl1_map.ncd"
|
||||
Thu Sep 21 05:34:51 2023
|
||||
|
||||
|
||||
<A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
|
||||
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
|
||||
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2E_LCMXO2_640HC_impl1.prf
|
||||
Preference file: RAM2E_LCMXO2_640HC_impl1.prf.
|
||||
Placement level-cost: 5-1.
|
||||
Routing Iterations: 6
|
||||
|
||||
Loading design for application par from file RAM2E_LCMXO2_640HC_impl1_map.ncd.
|
||||
Design name: RAM2E
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-640HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application par from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.39.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
License checked out.
|
||||
|
||||
|
||||
Ignore Preference Error(s): True
|
||||
|
||||
<A name="par_dus"></A><B><U><big>Device utilization summary:</big></U></B>
|
||||
|
||||
PIO (prelim) 70+4(JTAG)/80 93% used
|
||||
70+4(JTAG)/79 94% bonded
|
||||
IOLOGIC 36/80 45% used
|
||||
|
||||
SLICE 120/320 37% used
|
||||
|
||||
EFB 1/1 100% used
|
||||
|
||||
|
||||
Number of Signals: 395
|
||||
Number of Connections: 1126
|
||||
|
||||
Pin Constraint Summary:
|
||||
70 out of 70 pins locked (100% locked).
|
||||
|
||||
The following 1 signal is selected to use the primary clock routing resources:
|
||||
C14M_c (driver: C14M, clk load #: 84)
|
||||
|
||||
WARNING - par: Signal "C14M_c" is selected to use Primary clock resources. However, its driver comp "C14M" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
|
||||
The following 1 signal is selected to use the secondary clock routing resources:
|
||||
N_576_i (driver: SLICE_20, clk load #: 0, sr load #: 0, ce load #: 17)
|
||||
|
||||
No signal is selected as Global Set/Reset.
|
||||
Starting Placer Phase 0.
|
||||
............
|
||||
Finished Placer Phase 0. REAL time: 0 secs
|
||||
|
||||
Starting Placer Phase 1.
|
||||
.....................
|
||||
Placer score = 63243.
|
||||
Finished Placer Phase 1. REAL time: 8 secs
|
||||
|
||||
Starting Placer Phase 2.
|
||||
.
|
||||
Placer score = 62715
|
||||
Finished Placer Phase 2. REAL time: 8 secs
|
||||
|
||||
|
||||
|
||||
<A name="par_clk"></A><B><U><big>Clock Report</big></U></B>
|
||||
|
||||
Global Clock Resources:
|
||||
CLK_PIN : 0 out of 8 (0%)
|
||||
General PIO: 1 out of 80 (1%)
|
||||
DCM : 0 out of 2 (0%)
|
||||
DCC : 0 out of 8 (0%)
|
||||
|
||||
Global Clocks:
|
||||
PRIMARY "C14M_c" from comp "C14M" on PIO site "62 (PR5D)", clk load = 84
|
||||
SECONDARY "N_576_i" from F1 on comp "SLICE_20" on site "R6C8A", clk load = 0, ce load = 17, sr load = 0
|
||||
|
||||
PRIMARY : 1 out of 8 (12%)
|
||||
SECONDARY: 1 out of 8 (12%)
|
||||
|
||||
|
||||
|
||||
|
||||
I/O Usage Summary (final):
|
||||
70 + 4(JTAG) out of 80 (92.5%) PIO sites used.
|
||||
70 + 4(JTAG) out of 79 (93.7%) bonded PIO sites used.
|
||||
Number of PIO comps: 70; differential: 0.
|
||||
Number of Vref pins used: 0.
|
||||
|
||||
I/O Bank Usage Summary:
|
||||
+----------+----------------+------------+-----------+
|
||||
| I/O Bank | Usage | Bank Vccio | Bank Vref |
|
||||
+----------+----------------+------------+-----------+
|
||||
| 0 | 12 / 19 ( 63%) | 3.3V | - |
|
||||
| 1 | 20 / 20 (100%) | 3.3V | - |
|
||||
| 2 | 18 / 20 ( 90%) | 3.3V | - |
|
||||
| 3 | 20 / 20 (100%) | 3.3V | - |
|
||||
+----------+----------------+------------+-----------+
|
||||
|
||||
Total placer CPU time: 8 secs
|
||||
|
||||
Dumping design to file RAM2E_LCMXO2_640HC_impl1.dir/5_1.ncd.
|
||||
|
||||
0 connections routed; 1126 unrouted.
|
||||
Starting router resource preassignment
|
||||
WARNING - par: The driver of primary clock net C14M_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
|
||||
|
||||
Completed router resource preassignment. Real time: 13 secs
|
||||
|
||||
Start NBR router at 05:35:04 09/21/23
|
||||
|
||||
*****************************************************************
|
||||
Info: NBR allows conflicts(one node used by more than one signal)
|
||||
in the earlier iterations. In each iteration, it tries to
|
||||
solve the conflicts while keeping the critical connections
|
||||
routed as short as possible. The routing process is said to
|
||||
be completed when no conflicts exist and all connections
|
||||
are routed.
|
||||
Note: NBR uses a different method to calculate timing slacks. The
|
||||
worst slack and total negative slack may not be the same as
|
||||
that in TRCE report. You should always run TRCE to verify
|
||||
your design.
|
||||
*****************************************************************
|
||||
|
||||
Start NBR special constraint process at 05:35:05 09/21/23
|
||||
|
||||
Start NBR section for initial routing at 05:35:05 09/21/23
|
||||
Level 4, iteration 1
|
||||
14(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 57.366ns/0.000ns; real time: 14 secs
|
||||
|
||||
Info: Initial congestion level at 75% usage is 0
|
||||
Info: Initial congestion area at 75% usage is 0 (0.00%)
|
||||
|
||||
Start NBR section for normal routing at 05:35:05 09/21/23
|
||||
Level 4, iteration 1
|
||||
4(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 57.366ns/0.000ns; real time: 14 secs
|
||||
Level 4, iteration 2
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 57.366ns/0.000ns; real time: 14 secs
|
||||
|
||||
Start NBR section for setup/hold timing optimization with effort level 3 at 05:35:05 09/21/23
|
||||
|
||||
Start NBR section for re-routing at 05:35:05 09/21/23
|
||||
Level 4, iteration 1
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 57.366ns/0.000ns; real time: 14 secs
|
||||
|
||||
Start NBR section for post-routing at 05:35:05 09/21/23
|
||||
|
||||
End NBR router with 0 unrouted connection
|
||||
|
||||
NBR Summary
|
||||
-----------
|
||||
Number of unrouted connections : 0 (0.00%)
|
||||
Number of connections with timing violations : 0 (0.00%)
|
||||
Estimated worst slack<setup> : 57.366ns
|
||||
Timing score<setup> : 0
|
||||
-----------
|
||||
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
|
||||
|
||||
|
||||
|
||||
Total CPU time 14 secs
|
||||
Total REAL time: 15 secs
|
||||
Completely routed.
|
||||
End of route. 1126 routed (100.00%); 0 unrouted.
|
||||
|
||||
Hold time timing score: 0, hold timing errors: 0
|
||||
|
||||
Timing score: 0
|
||||
|
||||
Dumping design to file RAM2E_LCMXO2_640HC_impl1.dir/5_1.ncd.
|
||||
|
||||
|
||||
All signals are completely routed.
|
||||
|
||||
|
||||
PAR_SUMMARY::Run status = Completed
|
||||
PAR_SUMMARY::Number of unrouted conns = 0
|
||||
PAR_SUMMARY::Worst slack<setup/<ns>> = 57.366
|
||||
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
|
||||
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.346
|
||||
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
|
||||
PAR_SUMMARY::Number of errors = 0
|
||||
|
||||
Total CPU time to completion: 15 secs
|
||||
Total REAL time to completion: 15 secs
|
||||
|
||||
par done!
|
||||
|
||||
Note: user must run 'Trace' for timing closure signoff.
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: R-2021.03L-SP1
|
||||
Install: C:\lscc\diamond\3.12\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
|
||||
# Written on Thu Sep 21 05:34:35 2023
|
||||
|
||||
##### FILES SYNTAX CHECKED ##############################################
|
||||
Constraint File(s): "\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc"
|
||||
|
||||
#Run constraint checker to find more issues with constraints.
|
||||
#########################################################################
|
||||
|
||||
|
||||
|
||||
No issues found in constraint syntax.
|
||||
|
||||
|
||||
|
||||
Clock Summary
|
||||
*************
|
||||
|
||||
Start Requested Requested Clock Clock Clock
|
||||
Level Clock Frequency Period Type Group Load
|
||||
----------------------------------------------------------------------------------------
|
||||
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 111
|
||||
|
||||
0 - System 100.0 MHz 10.000 system system_clkgroup 0
|
||||
========================================================================================
|
||||
|
||||
|
||||
Clock Load Summary
|
||||
******************
|
||||
|
||||
Clock Source Clock Pin Non-clock Pin Non-clock Pin
|
||||
Clock Load Pin Seq Example Seq Example Comb Example
|
||||
----------------------------------------------------------------------------------------
|
||||
C14M 111 C14M(port) wb_rst.C - un1_C14M.I[0](inv)
|
||||
|
||||
System 0 - - - -
|
||||
========================================================================================
|
||||
|
|
@ -0,0 +1,83 @@
|
|||
<HTML>
|
||||
<HEAD><TITLE>Project Summary</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><TABLE border=1 width=100% cellspacing=0 cellpadding=2><small>
|
||||
<TR>
|
||||
<TD align='center' BGCOLOR='#000099' COLSPAN='4'><SPAN style="COLOR: #FFFFFF"><B>RAM2E_LCMXO2_640HC project summary</B></SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Module Name:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">RAM2E_LCMXO2_640HC</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Synthesis:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">SynplifyPro</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Name:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">impl1</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Strategy Name:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">Strategy1</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Last Process:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">JEDEC File</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">State:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">Passed</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Target Device:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">LCMXO2-640HC-4TG100C</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Device Family:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">MachXO2</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Device Type:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">LCMXO2-640HC</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Package Type:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">TQFP100</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Performance grade:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">4</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Operating conditions:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">COM</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Logic preference file:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">RAM2E-LCMXO2.lpf</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Physical Preference file:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">impl1/RAM2E_LCMXO2_640HC_impl1.prf</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Product Version:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">3.12.1.454</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Patch Version:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000"></SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Updated:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2023/09/21 05:35:24</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Location:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/impl1</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Project File:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC.ldf</SPAN></TD>
|
||||
</TR>
|
||||
</small></TABLE>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
|
|
@ -0,0 +1,755 @@
|
|||
<HTML>
|
||||
<HEAD><TITLE>Synthesis Report</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Syn"></A><B><U><big>Synthesis Report</big></U></B>
|
||||
#Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021
|
||||
#install: C:\lscc\diamond\3.12\synpbase
|
||||
#OS: Windows 8 6.2
|
||||
#Hostname: ZANEMACWIN11
|
||||
|
||||
# Thu Sep 21 05:34:32 2023
|
||||
|
||||
#Implementation: impl1
|
||||
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: R-2021.03L-SP1
|
||||
Install: C:\lscc\diamond\3.12\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
###########################################################[
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: R-2021.03L-SP1
|
||||
Install: C:\lscc\diamond\3.12\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v" (library work)
|
||||
@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
|
||||
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
|
||||
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
|
||||
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
|
||||
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
|
||||
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E-LCMXO2.v" (library work)
|
||||
@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\REFB.v" (library work)
|
||||
Verilog syntax check successful!
|
||||
|
||||
Compiler output is up to date. No re-compile necessary
|
||||
|
||||
Selecting top level module RAM2E
|
||||
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
|
||||
Running optimization stage 1 on VHI .......
|
||||
Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
|
||||
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
|
||||
Running optimization stage 1 on VLO .......
|
||||
Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
|
||||
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
|
||||
Running optimization stage 1 on EFB .......
|
||||
Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
|
||||
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
|
||||
Running optimization stage 1 on REFB .......
|
||||
Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
|
||||
@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E-LCMXO2.v":1:7:1:11|Synthesizing module RAM2E in library work.
|
||||
Running optimization stage 1 on RAM2E .......
|
||||
Finished optimization stage 1 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB)
|
||||
Running optimization stage 2 on RAM2E .......
|
||||
Finished optimization stage 2 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
|
||||
Running optimization stage 2 on REFB .......
|
||||
Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
|
||||
Running optimization stage 2 on EFB .......
|
||||
Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
|
||||
Running optimization stage 2 on VLO .......
|
||||
Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
|
||||
Running optimization stage 2 on VHI .......
|
||||
Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
|
||||
|
||||
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 97MB peak: 98MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:34:32 2023
|
||||
|
||||
###########################################################]
|
||||
###########################################################[
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: R-2021.03L-SP1
|
||||
Install: C:\lscc\diamond\3.12\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:34:33 2023
|
||||
|
||||
###########################################################]
|
||||
|
||||
For a summary of runtime and memory usage for all design units, please see file:
|
||||
==========================================================
|
||||
@L: A:\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_comp.rt.csv
|
||||
|
||||
@END
|
||||
|
||||
At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:34:33 2023
|
||||
|
||||
###########################################################]
|
||||
###########################################################[
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: R-2021.03L-SP1
|
||||
Install: C:\lscc\diamond\3.12\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
File \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_comp.srs changed - recompiling
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:34:34 2023
|
||||
|
||||
###########################################################]
|
||||
# Thu Sep 21 05:34:34 2023
|
||||
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: R-2021.03L-SP1
|
||||
Install: C:\lscc\diamond\3.12\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @
|
||||
|
||||
|
||||
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
|
||||
|
||||
|
||||
Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 140MB)
|
||||
|
||||
Reading constraint file: \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
|
||||
@L: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1_scck.rpt
|
||||
See clock summary report "\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1_scck.rpt"
|
||||
@N: MF916 |Option synthesis_strategy=base is enabled.
|
||||
@N: MF248 |Running in 64-bit mode.
|
||||
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
|
||||
|
||||
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
|
||||
|
||||
|
||||
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
|
||||
|
||||
|
||||
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 149MB)
|
||||
|
||||
|
||||
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 151MB)
|
||||
|
||||
@N: FX493 |Applying initial value "0" on instance PHI1reg.
|
||||
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
|
||||
@N: FX493 |Applying initial value "0" on instance DOEEN.
|
||||
@N: FX493 |Applying initial value "0" on instance RWSel.
|
||||
@N: FX493 |Applying initial value "00000000" on instance RWBank[7:0].
|
||||
@N: FX493 |Applying initial value "1" on instance DQMH.
|
||||
@N: FX493 |Applying initial value "0" on instance Ready.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdBitbangMXO2.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdExecMXO2.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdLEDGet.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdLEDSet.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdRWMaskSet.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdSetRWBankFFLED.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdSetRWBankFFMXO2.
|
||||
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":375:4:375:9|Initial value on register nRWE is non-zero which can prevent the register from being packed into a block RAM or DSP.
|
||||
@N: FX493 |Applying initial value "1" on instance nRWE.
|
||||
@N: FX493 |Applying initial value "0" on instance LEDEN.
|
||||
@N: FX493 |Applying initial value "00000000" on instance RWMask[7:0].
|
||||
@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":102:4:102:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
|
||||
@N: FX493 |Applying initial value "0000" on instance S[3:0].
|
||||
@N: FX493 |Applying initial value "1" on instance DQML.
|
||||
@N: FX493 |Applying initial value "0" on instance CKE.
|
||||
@N: FX493 |Applying initial value "1" on instance nCS.
|
||||
@N: FX493 |Applying initial value "1" on instance nRAS.
|
||||
@N: FX493 |Applying initial value "1" on instance nCAS.
|
||||
|
||||
Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
|
||||
|
||||
|
||||
Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
|
||||
|
||||
|
||||
Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
|
||||
|
||||
|
||||
Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
|
||||
|
||||
@N: FX1184 |Applying syn_allowed_resources blockrams=2 on top level netlist RAM2E
|
||||
|
||||
Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
|
||||
|
||||
|
||||
|
||||
Clock Summary
|
||||
******************
|
||||
|
||||
Start Requested Requested Clock Clock Clock
|
||||
Level Clock Frequency Period Type Group Load
|
||||
----------------------------------------------------------------------------------------
|
||||
0 - C14M 14.3 MHz 69.841 declared default_clkgroup 111
|
||||
|
||||
0 - System 100.0 MHz 10.000 system system_clkgroup 0
|
||||
========================================================================================
|
||||
|
||||
|
||||
|
||||
Clock Load Summary
|
||||
***********************
|
||||
|
||||
Clock Source Clock Pin Non-clock Pin Non-clock Pin
|
||||
Clock Load Pin Seq Example Seq Example Comb Example
|
||||
----------------------------------------------------------------------------------------
|
||||
C14M 111 C14M(port) wb_rst.C - un1_C14M.I[0](inv)
|
||||
|
||||
System 0 - - - -
|
||||
========================================================================================
|
||||
|
||||
ICG Latch Removal Summary:
|
||||
Number of ICG latches removed: 0
|
||||
Number of ICG latches not removed: 0
|
||||
For details review file gcc_ICG_report.rpt
|
||||
|
||||
|
||||
@S |Clock Optimization Summary
|
||||
|
||||
|
||||
|
||||
#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
|
||||
|
||||
1 non-gated/non-generated clock tree(s) driving 111 clock pin(s) of sequential element(s)
|
||||
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
|
||||
0 instances converted, 0 sequential instances remain driven by gated/generated clocks
|
||||
|
||||
=========================== Non-Gated/Non-Generated Clocks ============================
|
||||
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
|
||||
---------------------------------------------------------------------------------------
|
||||
@KP:ckid0_0 C14M port 111 nCAS
|
||||
=======================================================================================
|
||||
|
||||
|
||||
##### END OF CLOCK OPTIMIZATION REPORT ######
|
||||
|
||||
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
|
||||
Finished Pre Mapping Phase.
|
||||
|
||||
Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
|
||||
|
||||
|
||||
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
|
||||
|
||||
|
||||
Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
|
||||
|
||||
Pre-mapping successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 99MB peak: 185MB)
|
||||
|
||||
Process took 0h:00m:02s realtime, 0h:00m:01s cputime
|
||||
# Thu Sep 21 05:34:37 2023
|
||||
|
||||
###########################################################]
|
||||
# Thu Sep 21 05:34:37 2023
|
||||
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: R-2021.03L-SP1
|
||||
Install: C:\lscc\diamond\3.12\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @
|
||||
|
||||
|
||||
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
|
||||
|
||||
@N: MF916 |Option synthesis_strategy=base is enabled.
|
||||
@N: MF248 |Running in 64-bit mode.
|
||||
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
|
||||
|
||||
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
|
||||
|
||||
|
||||
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
|
||||
|
||||
|
||||
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
|
||||
|
||||
|
||||
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB)
|
||||
|
||||
|
||||
|
||||
Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 179MB peak: 179MB)
|
||||
|
||||
@W: FA239 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":376:8:376:9|ROM DOEEN_2 (in view: work.RAM2E(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
|
||||
@N: MO106 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":376:8:376:9|Found ROM DOEEN_2 (in view: work.RAM2E(verilog)) with 16 words by 1 bit.
|
||||
|
||||
Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
|
||||
|
||||
@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":102:4:102:9|Found counter in view:work.RAM2E(verilog) instance FS[15:0]
|
||||
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
|
||||
|
||||
Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB)
|
||||
|
||||
|
||||
Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
|
||||
|
||||
|
||||
Available hyper_sources - for debug and ip models
|
||||
None Found
|
||||
|
||||
|
||||
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
|
||||
|
||||
|
||||
Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
|
||||
|
||||
|
||||
Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
|
||||
|
||||
|
||||
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
|
||||
|
||||
|
||||
Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
|
||||
|
||||
|
||||
Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 205MB peak: 205MB)
|
||||
|
||||
Pass CPU time Worst Slack Luts / Registers
|
||||
------------------------------------------------------------
|
||||
1 0h:00m:02s 29.35ns 222 / 111
|
||||
|
||||
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 205MB peak: 205MB)
|
||||
|
||||
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
|
||||
|
||||
Finished restoring hierarchy (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 206MB peak: 206MB)
|
||||
|
||||
|
||||
Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 168MB peak: 206MB)
|
||||
|
||||
Writing Analyst data base \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_m.srm
|
||||
|
||||
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 206MB peak: 206MB)
|
||||
|
||||
Writing EDIF Netlist and constraint files
|
||||
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1.edi
|
||||
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
|
||||
|
||||
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 211MB peak: 211MB)
|
||||
|
||||
|
||||
Finished Writing Netlists (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 211MB peak: 211MB)
|
||||
|
||||
|
||||
Start final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 209MB peak: 211MB)
|
||||
|
||||
@W: MT246 :"\\mac\icloud\repos\ram2e\cpld\lcmxo2-640hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
|
||||
@N: MT615 |Found clock C14M with period 69.84ns
|
||||
|
||||
|
||||
##### START OF TIMING REPORT #####[
|
||||
# Timing report written on Thu Sep 21 05:34:43 2023
|
||||
#
|
||||
|
||||
|
||||
Top view: RAM2E
|
||||
Requested Frequency: 14.3 MHz
|
||||
Wire load mode: top
|
||||
Paths requested: 5
|
||||
Constraint File(s): \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
|
||||
|
||||
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
|
||||
|
||||
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
|
||||
|
||||
|
||||
|
||||
Performance Summary
|
||||
*******************
|
||||
|
||||
|
||||
Worst slack in design: 31.782
|
||||
|
||||
Requested Estimated Requested Estimated Clock Clock
|
||||
Starting Clock Frequency Frequency Period Period Slack Type Group
|
||||
-------------------------------------------------------------------------------------------------------------------
|
||||
C14M 14.3 MHz 131.4 MHz 69.841 7.610 31.782 declared default_clkgroup
|
||||
System 100.0 MHz NA 10.000 NA 67.088 system system_clkgroup
|
||||
===================================================================================================================
|
||||
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Clock Relationships
|
||||
*******************
|
||||
|
||||
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
System C14M | 69.841 67.088 | No paths - | No paths - | No paths -
|
||||
C14M System | 69.841 68.797 | No paths - | No paths - | No paths -
|
||||
C14M C14M | 69.841 62.231 | No paths - | 34.920 31.782 | No paths -
|
||||
==========================================================================================================
|
||||
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
|
||||
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
|
||||
|
||||
|
||||
|
||||
Interface Information
|
||||
*********************
|
||||
|
||||
No IO constraint found
|
||||
|
||||
|
||||
|
||||
====================================
|
||||
Detailed Report for Clock: C14M
|
||||
====================================
|
||||
|
||||
|
||||
|
||||
Starting Points with Worst Slack
|
||||
********************************
|
||||
|
||||
Starting Arrival
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------
|
||||
S[2] C14M FD1S3AX Q S[2] 1.350 31.782
|
||||
S[3] C14M FD1S3AX Q S[3] 1.350 31.782
|
||||
S[0] C14M FD1S3AX Q S[0] 1.312 31.820
|
||||
S[1] C14M FD1S3AX Q S[1] 1.280 31.852
|
||||
FS[9] C14M FD1S3AX Q FS[9] 1.284 62.425
|
||||
FS[11] C14M FD1S3AX Q FS[11] 1.276 62.433
|
||||
FS[8] C14M FD1S3AX Q FS[8] 1.260 62.449
|
||||
FS[12] C14M FD1S3AX Q FS[12] 1.288 62.525
|
||||
FS[10] C14M FD1S3AX Q FS[10] 1.280 62.533
|
||||
RWSel C14M FD1P3AX Q RWSel 1.276 63.482
|
||||
============================================================================
|
||||
|
||||
|
||||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------------
|
||||
Dout_0io[0] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[1] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[2] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[3] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[4] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[5] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[6] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Dout_0io[7] C14M OFS1P3DX SP N_576_i 34.449 31.782
|
||||
Vout_0io[0] C14M OFS1P3DX SP Vout3 34.449 31.826
|
||||
Vout_0io[1] C14M OFS1P3DX SP Vout3 34.449 31.826
|
||||
==================================================================================
|
||||
|
||||
|
||||
|
||||
Worst Path Information
|
||||
***********************
|
||||
|
||||
|
||||
Path information for path number 1:
|
||||
Requested Period: 34.920
|
||||
- Setup time: 0.472
|
||||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
= Required time: 34.449
|
||||
|
||||
- Propagation time: 2.667
|
||||
- Clock delay at starting point: 0.000 (ideal)
|
||||
= Slack (critical) : 31.782
|
||||
|
||||
Number of logic level(s): 1
|
||||
Starting point: S[2] / Q
|
||||
Ending point: Dout_0io[0] / SP
|
||||
The start point is clocked by C14M [rising] (rise=0.000 fall=34.920 period=69.841) on pin CK
|
||||
The end point is clocked by C14M [falling] (rise=0.000 fall=34.920 period=69.841) on pin SCLK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
----------------------------------------------------------------------------------
|
||||
S[2] FD1S3AX Q Out 1.350 1.350 r -
|
||||
S[2] Net - - - - 48
|
||||
S_RNII9DO1_2[1] ORCALUT4 B In 0.000 1.350 r -
|
||||
S_RNII9DO1_2[1] ORCALUT4 Z Out 1.317 2.667 r -
|
||||
N_576_i Net - - - - 18
|
||||
Dout_0io[0] OFS1P3DX SP In 0.000 2.667 r -
|
||||
==================================================================================
|
||||
|
||||
|
||||
|
||||
|
||||
====================================
|
||||
Detailed Report for Clock: System
|
||||
====================================
|
||||
|
||||
|
||||
|
||||
Starting Points with Worst Slack
|
||||
********************************
|
||||
|
||||
Starting Arrival
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
-----------------------------------------------------------------------------------------
|
||||
ufmefb.EFBInst_0 System EFB WBACKO wb_ack 0.000 67.088
|
||||
ufmefb.EFBInst_0 System EFB WBDATO0 wb_dato[0] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO2 wb_dato[2] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO3 wb_dato[3] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO4 wb_dato[4] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO5 wb_dato[5] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO6 wb_dato[6] 0.000 69.313
|
||||
ufmefb.EFBInst_0 System EFB WBDATO7 wb_dato[7] 0.000 69.313
|
||||
=========================================================================================
|
||||
|
||||
|
||||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------------------------------
|
||||
RWMask[0] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[1] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[2] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[3] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[4] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[5] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[6] System FD1P3AX SP N_88 69.369 67.088
|
||||
RWMask[7] System FD1P3AX SP N_88 69.369 67.088
|
||||
LEDEN System FD1P3AX SP un1_LEDEN_0_sqmuxa_1_i_0[0] 69.369 67.736
|
||||
wb_cyc_stb System FD1P3AX SP N_104 69.369 67.736
|
||||
====================================================================================================
|
||||
|
||||
|
||||
|
||||
Worst Path Information
|
||||
***********************
|
||||
|
||||
|
||||
Path information for path number 1:
|
||||
Requested Period: 69.841
|
||||
- Setup time: 0.472
|
||||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
= Required time: 69.369
|
||||
|
||||
- Propagation time: 2.282
|
||||
- Clock delay at starting point: 0.000 (ideal)
|
||||
- Estimated clock delay at start point: -0.000
|
||||
= Slack (non-critical) : 67.088
|
||||
|
||||
Number of logic level(s): 2
|
||||
Starting point: ufmefb.EFBInst_0 / WBACKO
|
||||
Ending point: RWMask[0] / SP
|
||||
The start point is clocked by System [rising]
|
||||
The end point is clocked by C14M [rising] (rise=0.000 fall=34.920 period=69.841) on pin CK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
------------------------------------------------------------------------------------------------------
|
||||
ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 r -
|
||||
wb_ack Net - - - - 5
|
||||
un1_RWMask_0_sqmuxa_1_i_0_RNO[0] ORCALUT4 A In 0.000 0.000 r -
|
||||
un1_RWMask_0_sqmuxa_1_i_0_RNO[0] ORCALUT4 Z Out 1.017 1.017 r -
|
||||
un1_RWMask_0_sqmuxa_1_i_a2_0_1[0] Net - - - - 1
|
||||
un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 D In 0.000 1.017 r -
|
||||
un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 Z Out 1.265 2.282 r -
|
||||
N_88 Net - - - - 8
|
||||
RWMask[0] FD1P3AX SP In 0.000 2.282 r -
|
||||
======================================================================================================
|
||||
|
||||
|
||||
|
||||
##### END OF TIMING REPORT #####]
|
||||
|
||||
Timing exceptions that could not be applied
|
||||
|
||||
Finished final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:04s; Memory used current: 210MB peak: 211MB)
|
||||
|
||||
|
||||
Finished timing report (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:04s; Memory used current: 210MB peak: 211MB)
|
||||
|
||||
---------------------------------------
|
||||
Resource Usage Report
|
||||
Part: lcmxo2_640hc-4
|
||||
|
||||
Register bits: 111 of 640 (17%)
|
||||
PIC Latch: 0
|
||||
I/O cells: 70
|
||||
|
||||
|
||||
Details:
|
||||
BB: 8
|
||||
CCU2D: 9
|
||||
EFB: 1
|
||||
FD1P3AX: 48
|
||||
FD1P3IX: 1
|
||||
FD1S3AX: 22
|
||||
FD1S3IX: 4
|
||||
GSR: 1
|
||||
IB: 22
|
||||
IFS1P3DX: 1
|
||||
INV: 1
|
||||
OB: 40
|
||||
OFS1P3BX: 6
|
||||
OFS1P3DX: 27
|
||||
OFS1P3IX: 2
|
||||
ORCALUT4: 221
|
||||
PUR: 1
|
||||
VHI: 2
|
||||
VLO: 2
|
||||
Mapper successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:04s; Memory used current: 77MB peak: 211MB)
|
||||
|
||||
Process took 0h:00m:06s realtime, 0h:00m:04s cputime
|
||||
# Thu Sep 21 05:34:44 2023
|
||||
|
||||
###########################################################]
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
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|
||||
<BR>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
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|
||||
<BR>
|
||||
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|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
|
|
@ -0,0 +1,289 @@
|
|||
<HTML>
|
||||
<HEAD><TITLE>Lattice Map TRACE Report</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Map_Twr"></A><B><U><big>Map TRACE Report</big></U></B>
|
||||
|
||||
Loading design for application trce from file ram2e_lcmxo2_640hc_impl1_map.ncd.
|
||||
Design name: RAM2E
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-640HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.39.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
Setup and Hold Report
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
<A name="Map_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454</big></U></B>
|
||||
Thu Sep 21 05:34:48 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
<A name="mtw1_set_ri"></A><B><U><big>Report Information</big></U></B>
|
||||
------------------
|
||||
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2E_LCMXO2_640HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.prf
|
||||
Design file: ram2e_lcmxo2_640hc_impl1_map.ncd
|
||||
Preference file: ram2e_lcmxo2_640hc_impl1.prf
|
||||
Device,speed: LCMXO2-640HC,4
|
||||
Report level: verbose report, limited to 1 item per preference
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
<A name="mtw1_set_ps"></A><B><U><big>Preference Summary</big></U></B>
|
||||
|
||||
<LI><A href='#map_twr_pref_0_0' Target='right'>FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)</A></LI> 1491 items scored, 0 timing errors detected.
|
||||
Report: 87.268MHz is the maximum frequency for this preference.
|
||||
|
||||
BLOCK ASYNCPATHS
|
||||
BLOCK RESETPATHS
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
================================================================================
|
||||
<A name="map_twr_pref_0_0"></A>Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
|
||||
1491 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 58.471ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q FS[11] (from C14M_c +)
|
||||
Destination: FF Data in nRWE_0io (to C14M_c +)
|
||||
|
||||
Delay: 11.306ns (30.3% logic, 69.7% route), 7 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
11.306ns physical path delay SLICE_3 to nRWE_MGIOL meets
|
||||
69.930ns delay constraint less
|
||||
0.153ns DO_SET requirement (totaling 69.777ns) by 58.471ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path SLICE_3 to nRWE_MGIOL:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.452 SLICE_3.CLK to SLICE_3.Q0 SLICE_3 (from C14M_c)
|
||||
ROUTE 19 e 1.234 SLICE_3.Q0 to SLICE_64.A1 FS[11]
|
||||
CTOF_DEL --- 0.495 SLICE_64.A1 to SLICE_64.F1 SLICE_64
|
||||
ROUTE 4 e 1.234 SLICE_64.F1 to SLICE_97.D0 N_577
|
||||
CTOF_DEL --- 0.495 SLICE_97.D0 to SLICE_97.F0 SLICE_97
|
||||
ROUTE 3 e 1.234 SLICE_97.F0 to SLICE_75.D1 N_489
|
||||
CTOF_DEL --- 0.495 SLICE_75.D1 to SLICE_75.F1 SLICE_75
|
||||
ROUTE 3 e 0.480 SLICE_75.F1 to SLICE_75.A0 N_628
|
||||
CTOF_DEL --- 0.495 SLICE_75.A0 to SLICE_75.F0 SLICE_75
|
||||
ROUTE 2 e 1.234 SLICE_75.F0 to SLICE_71.C1 N_640
|
||||
CTOF_DEL --- 0.495 SLICE_71.C1 to SLICE_71.F1 SLICE_71
|
||||
ROUTE 1 e 1.234 SLICE_71.F1 to SLICE_115.A0 un1_nCS61_1_i
|
||||
CTOF_DEL --- 0.495 SLICE_115.A0 to SLICE_115.F0 SLICE_115
|
||||
ROUTE 1 e 1.234 SLICE_115.F0 to *WE_MGIOL.OPOS nRWE_r_0 (to C14M_c)
|
||||
--------
|
||||
11.306 (30.3% logic, 69.7% route), 7 logic levels.
|
||||
|
||||
Report: 87.268MHz is the maximum frequency for this preference.
|
||||
|
||||
<A name="mtw1_set_rs"></A><B><U><big>Report Summary</big></U></B>
|
||||
--------------
|
||||
----------------------------------------------------------------------------
|
||||
Preference | Constraint| Actual|Levels
|
||||
----------------------------------------------------------------------------
|
||||
| | |
|
||||
FREQUENCY PORT "C14M" 14.300000 MHz ; | 14.300 MHz| 87.268 MHz| 7
|
||||
| | |
|
||||
----------------------------------------------------------------------------
|
||||
|
||||
|
||||
All preferences were met.
|
||||
|
||||
|
||||
<A name="mtw1_set_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
|
||||
------------------------
|
||||
|
||||
Found 1 clocks:
|
||||
|
||||
Clock Domain: C14M_c Source: C14M.PAD Loads: 84
|
||||
Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
|
||||
|
||||
|
||||
<A name="mtw1_set_ts"></A><B><U><big>Timing summary (Setup):</big></U></B>
|
||||
---------------
|
||||
|
||||
Timing errors: 0 Score: 0
|
||||
Cumulative negative slack: 0
|
||||
|
||||
Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
<A name="Map_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454</big></U></B>
|
||||
Thu Sep 21 05:34:48 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
<A name="mtw1_hold_ri"></A><B><U><big>Report Information</big></U></B>
|
||||
------------------
|
||||
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2E_LCMXO2_640HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.prf
|
||||
Design file: ram2e_lcmxo2_640hc_impl1_map.ncd
|
||||
Preference file: ram2e_lcmxo2_640hc_impl1.prf
|
||||
Device,speed: LCMXO2-640HC,M
|
||||
Report level: verbose report, limited to 1 item per preference
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
<A name="mtw1_hold_ps"></A><B><U><big>Preference Summary</big></U></B>
|
||||
|
||||
<LI><A href='#map_twr_pref_1_0' Target='right'>FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)</A></LI> 1491 items scored, 0 timing errors detected.
|
||||
|
||||
BLOCK ASYNCPATHS
|
||||
BLOCK RESETPATHS
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
================================================================================
|
||||
<A name="map_twr_pref_1_0"></A>Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
|
||||
1491 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 0.447ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q FS[0] (from C14M_c +)
|
||||
Destination: FF Data in FS[0] (to C14M_c +)
|
||||
|
||||
Delay: 0.434ns (53.9% logic, 46.1% route), 2 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
0.434ns physical path delay SLICE_0 to SLICE_0 meets
|
||||
-0.013ns DIN_HLD and
|
||||
0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path SLICE_0 to SLICE_0:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.133 SLICE_0.CLK to SLICE_0.Q1 SLICE_0 (from C14M_c)
|
||||
ROUTE 5 e 0.199 SLICE_0.Q1 to SLICE_0.A1 FS[0]
|
||||
CTOF_DEL --- 0.101 SLICE_0.A1 to SLICE_0.F1 SLICE_0
|
||||
ROUTE 1 e 0.001 SLICE_0.F1 to SLICE_0.DI1 FS_s[0] (to C14M_c)
|
||||
--------
|
||||
0.434 (53.9% logic, 46.1% route), 2 logic levels.
|
||||
|
||||
<A name="mtw1_hold_rs"></A><B><U><big>Report Summary</big></U></B>
|
||||
--------------
|
||||
----------------------------------------------------------------------------
|
||||
Preference(MIN Delays) | Constraint| Actual|Levels
|
||||
----------------------------------------------------------------------------
|
||||
| | |
|
||||
FREQUENCY PORT "C14M" 14.300000 MHz ; | -| -| 2
|
||||
| | |
|
||||
----------------------------------------------------------------------------
|
||||
|
||||
|
||||
All preferences were met.
|
||||
|
||||
|
||||
<A name="mtw1_hold_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
|
||||
------------------------
|
||||
|
||||
Found 1 clocks:
|
||||
|
||||
Clock Domain: C14M_c Source: C14M.PAD Loads: 84
|
||||
Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
|
||||
|
||||
|
||||
<A name="mtw1_hold_ts"></A><B><U><big>Timing summary (Hold):</big></U></B>
|
||||
---------------
|
||||
|
||||
Timing errors: 0 Score: 0
|
||||
Cumulative negative slack: 0
|
||||
|
||||
Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage)
|
||||
|
||||
|
||||
|
||||
<A name="mtw1_ts"></A><B><U><big>Timing summary (Setup and Hold):</big></U></B>
|
||||
---------------
|
||||
|
||||
Timing errors: 0 (setup), 0 (hold)
|
||||
Score: 0 (setup), 0 (hold)
|
||||
Cumulative negative slack: 0 (0+0)
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
|
|
@ -0,0 +1,118 @@
|
|||
Loading design for application iotiming from file ram2e_lcmxo2_640hc_impl1.ncd.
|
||||
Design name: RAM2E
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-640HC
|
||||
Package: TQFP100
|
||||
Performance: 5
|
||||
Package Status: Final Version 1.39.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
Loading design for application iotiming from file ram2e_lcmxo2_640hc_impl1.ncd.
|
||||
Design name: RAM2E
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-640HC
|
||||
Package: TQFP100
|
||||
Performance: 6
|
||||
Package Status: Final Version 1.39.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
Loading design for application iotiming from file ram2e_lcmxo2_640hc_impl1.ncd.
|
||||
Design name: RAM2E
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-640HC
|
||||
Package: TQFP100
|
||||
Performance: M
|
||||
Package Status: Final Version 1.39.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
// Design: RAM2E
|
||||
// Package: TQFP100
|
||||
// ncd File: ram2e_lcmxo2_640hc_impl1.ncd
|
||||
// Version: Diamond (64-bit) 3.12.1.454
|
||||
// Written on Thu Sep 21 05:35:10 2023
|
||||
// M: Minimum Performance Grade
|
||||
// iotiming RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml
|
||||
|
||||
I/O Timing Report (All units are in ns)
|
||||
|
||||
Worst Case Results across Performance Grades (M, 6, 5, 4):
|
||||
|
||||
// Input Setup and Hold Times
|
||||
|
||||
Port Clock Edge Setup Performance_Grade Hold Performance_Grade
|
||||
----------------------------------------------------------------------
|
||||
Ain[0] C14M R 0.502 4 0.868 4
|
||||
Ain[1] C14M R 2.364 4 -0.126 M
|
||||
Ain[2] C14M R 2.421 4 -0.129 M
|
||||
Ain[3] C14M R 0.574 4 0.786 4
|
||||
Ain[4] C14M R 1.452 4 0.140 M
|
||||
Ain[5] C14M R 2.076 4 -0.039 M
|
||||
Ain[6] C14M R 1.515 4 0.124 M
|
||||
Ain[7] C14M R 2.270 4 -0.095 M
|
||||
Din[0] C14M R 9.252 4 1.162 4
|
||||
Din[1] C14M R 8.868 4 0.657 4
|
||||
Din[2] C14M R 8.368 4 0.864 4
|
||||
Din[3] C14M R 8.749 4 1.339 4
|
||||
Din[4] C14M R 9.095 4 0.770 4
|
||||
Din[5] C14M R 8.195 4 1.176 4
|
||||
Din[6] C14M R 6.162 4 0.760 4
|
||||
Din[7] C14M R 7.060 4 1.093 4
|
||||
PHI1 C14M R 2.045 4 3.047 4
|
||||
RD[0] C14M F 0.267 4 0.866 4
|
||||
RD[1] C14M F 0.173 4 1.383 4
|
||||
RD[2] C14M F 0.924 4 1.018 4
|
||||
RD[3] C14M F 0.267 4 0.866 4
|
||||
RD[4] C14M F 0.173 4 0.937 4
|
||||
RD[5] C14M F 0.267 4 0.866 4
|
||||
RD[6] C14M F 0.766 4 0.866 4
|
||||
RD[7] C14M F 0.267 4 1.312 4
|
||||
nC07X C14M R 0.077 4 1.144 4
|
||||
nEN80 C14M R 6.415 4 -0.286 M
|
||||
nWE C14M R 0.691 4 0.684 4
|
||||
nWE80 C14M R 2.845 4 -0.260 M
|
||||
|
||||
|
||||
// Clock to Output Delay
|
||||
|
||||
Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
|
||||
------------------------------------------------------------------------
|
||||
BA[0] C14M R 8.629 4 2.885 M
|
||||
BA[1] C14M R 8.629 4 2.885 M
|
||||
CKE C14M R 8.629 4 2.885 M
|
||||
DQMH C14M R 8.609 4 2.892 M
|
||||
DQML C14M R 8.609 4 2.892 M
|
||||
Dout[0] C14M F 8.955 4 3.164 M
|
||||
Dout[1] C14M F 8.955 4 3.164 M
|
||||
Dout[2] C14M F 8.944 4 3.158 M
|
||||
Dout[3] C14M F 8.955 4 3.164 M
|
||||
Dout[4] C14M F 8.944 4 3.158 M
|
||||
Dout[5] C14M F 8.944 4 3.158 M
|
||||
Dout[6] C14M F 8.955 4 3.164 M
|
||||
Dout[7] C14M F 8.955 4 3.164 M
|
||||
LED C14M R 19.941 4 8.191 M
|
||||
RA[0] C14M R 10.013 4 3.186 M
|
||||
RA[10] C14M R 8.629 4 2.885 M
|
||||
RA[11] C14M R 8.629 4 2.885 M
|
||||
RA[1] C14M R 8.695 4 2.890 M
|
||||
RA[2] C14M R 8.695 4 2.890 M
|
||||
RA[3] C14M R 10.013 4 3.186 M
|
||||
RA[4] C14M R 8.695 4 2.890 M
|
||||
RA[5] C14M R 8.695 4 2.890 M
|
||||
RA[6] C14M R 8.695 4 2.890 M
|
||||
RA[7] C14M R 8.695 4 2.890 M
|
||||
RA[8] C14M R 8.629 4 2.885 M
|
||||
RA[9] C14M R 8.629 4 2.885 M
|
||||
Vout[0] C14M F 9.553 4 3.402 M
|
||||
Vout[1] C14M F 9.553 4 3.402 M
|
||||
Vout[2] C14M F 9.553 4 3.402 M
|
||||
Vout[3] C14M F 9.553 4 3.402 M
|
||||
Vout[4] C14M F 9.553 4 3.402 M
|
||||
Vout[5] C14M F 9.553 4 3.402 M
|
||||
Vout[6] C14M F 9.553 4 3.402 M
|
||||
Vout[7] C14M F 9.553 4 3.402 M
|
||||
nCAS C14M R 8.629 4 2.885 M
|
||||
nCS C14M R 8.629 4 2.885 M
|
||||
nDOE C14M R 11.976 4 3.776 M
|
||||
nRAS C14M R 8.629 4 2.885 M
|
||||
nRWE C14M R 8.629 4 2.885 M
|
||||
WARNING: you must also run trce with hold speed: 4
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
SCUBA, Version Diamond (64-bit) 3.12.1.454
|
||||
Wed Sep 20 04:17:14 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
BEGIN SCUBA Module Synthesis
|
||||
|
||||
Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 14.4 -ufm -ufm_ebr 190 -mem_size 1 -memfile ../RAM2E-LCMXO2.mem -memformat hex -wb -dev 640
|
||||
Circuit name : REFB
|
||||
Module type : efb
|
||||
Module Version : 1.2
|
||||
Ports :
|
||||
Inputs : wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i[7:0], wb_dat_i[7:0]
|
||||
Outputs : wb_dat_o[7:0], wb_ack_o, wbc_ufm_irq
|
||||
I/O buffer : not inserted
|
||||
EDIF output : REFB.edn
|
||||
Verilog output : REFB.v
|
||||
Verilog template : REFB_tmpl.v
|
||||
Verilog purpose : for synthesis and simulation
|
||||
Bus notation : big endian
|
||||
Report output : REFB.srp
|
||||
Estimated Resource Usage:
|
||||
|
||||
END SCUBA Module Synthesis
|
||||
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<userSetting name="//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml" version="Diamond (64-bit) 3.12.1.454" date="Thu Sep 21 05:35:47 2023" vendor="Lattice Semiconductor Corporation" >
|
||||
</userSetting>
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!DOCTYPE Report>
|
||||
<ReportView version="2.0">
|
||||
<Implement name="impl1">
|
||||
<ToolReport id="tooldec" path="" status="0"/>
|
||||
<ToolReport id="toolhle_genhierarchy" path="Y:/Repos/RAM2E/CPLD/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html" status="1"/>
|
||||
<ToolReport id="toolpio" path="" status="2"/>
|
||||
<ToolReport id="toolsso" path="" status="2"/>
|
||||
</Implement>
|
||||
</ReportView>
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions
|
||||
# and other software and tools, and any partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License
|
||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
# the Intel FPGA IP License Agreement, or other applicable license
|
||||
# agreement, including, without limitation, that your use is for
|
||||
# the sole purpose of programming logic devices manufactured by
|
||||
# Intel and sold by Intel or its authorized distributors. Please
|
||||
# refer to the applicable agreement for further details, at
|
||||
# https://fpgasoftware.intel.com/eula.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus Prime
|
||||
# Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
# Date created = 07:26:23 August 20, 2023
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "19.1"
|
||||
DATE = "07:26:23 August 20, 2023"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "RAM2E"
|
||||
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Reference in New Issue