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RAM2E/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_tw1.html
Zane Kaminski dec33238f1 RC
2023-09-21 05:45:21 -04:00

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<HEAD><TITLE>Lattice Map TRACE Report</TITLE>
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<PRE><A name="Map_Twr"></A><B><U><big>Map TRACE Report</big></U></B>
Loading design for application trce from file ram2e_lcmxo2_640hc_impl1_map.ncd.
Design name: RAM2E
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-640HC
Package: TQFP100
Performance: 4
Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.39.
Performance Hardware Data Status: Final Version 34.4.
Setup and Hold Report
--------------------------------------------------------------------------------
<A name="Map_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454</big></U></B>
Thu Sep 21 05:34:48 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
<A name="mtw1_set_ri"></A><B><U><big>Report Information</big></U></B>
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2E_LCMXO2_640HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.prf
Design file: ram2e_lcmxo2_640hc_impl1_map.ncd
Preference file: ram2e_lcmxo2_640hc_impl1.prf
Device,speed: LCMXO2-640HC,4
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
<A name="mtw1_set_ps"></A><B><U><big>Preference Summary</big></U></B>
<LI><A href='#map_twr_pref_0_0' Target='right'>FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)</A></LI> 1491 items scored, 0 timing errors detected.
Report: 87.268MHz is the maximum frequency for this preference.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
<A name="map_twr_pref_0_0"></A>Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
1491 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 58.471ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[11] (from C14M_c +)
Destination: FF Data in nRWE_0io (to C14M_c +)
Delay: 11.306ns (30.3% logic, 69.7% route), 7 logic levels.
Constraint Details:
11.306ns physical path delay SLICE_3 to nRWE_MGIOL meets
69.930ns delay constraint less
0.153ns DO_SET requirement (totaling 69.777ns) by 58.471ns
Physical Path Details:
Data path SLICE_3 to nRWE_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 SLICE_3.CLK to SLICE_3.Q0 SLICE_3 (from C14M_c)
ROUTE 19 e 1.234 SLICE_3.Q0 to SLICE_64.A1 FS[11]
CTOF_DEL --- 0.495 SLICE_64.A1 to SLICE_64.F1 SLICE_64
ROUTE 4 e 1.234 SLICE_64.F1 to SLICE_97.D0 N_577
CTOF_DEL --- 0.495 SLICE_97.D0 to SLICE_97.F0 SLICE_97
ROUTE 3 e 1.234 SLICE_97.F0 to SLICE_75.D1 N_489
CTOF_DEL --- 0.495 SLICE_75.D1 to SLICE_75.F1 SLICE_75
ROUTE 3 e 0.480 SLICE_75.F1 to SLICE_75.A0 N_628
CTOF_DEL --- 0.495 SLICE_75.A0 to SLICE_75.F0 SLICE_75
ROUTE 2 e 1.234 SLICE_75.F0 to SLICE_71.C1 N_640
CTOF_DEL --- 0.495 SLICE_71.C1 to SLICE_71.F1 SLICE_71
ROUTE 1 e 1.234 SLICE_71.F1 to SLICE_115.A0 un1_nCS61_1_i
CTOF_DEL --- 0.495 SLICE_115.A0 to SLICE_115.F0 SLICE_115
ROUTE 1 e 1.234 SLICE_115.F0 to *WE_MGIOL.OPOS nRWE_r_0 (to C14M_c)
--------
11.306 (30.3% logic, 69.7% route), 7 logic levels.
Report: 87.268MHz is the maximum frequency for this preference.
<A name="mtw1_set_rs"></A><B><U><big>Report Summary</big></U></B>
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "C14M" 14.300000 MHz ; | 14.300 MHz| 87.268 MHz| 7
| | |
----------------------------------------------------------------------------
All preferences were met.
<A name="mtw1_set_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
------------------------
Found 1 clocks:
Clock Domain: C14M_c Source: C14M.PAD Loads: 84
Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
<A name="mtw1_set_ts"></A><B><U><big>Timing summary (Setup):</big></U></B>
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage)
--------------------------------------------------------------------------------
<A name="Map_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454</big></U></B>
Thu Sep 21 05:34:48 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
<A name="mtw1_hold_ri"></A><B><U><big>Report Information</big></U></B>
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2E_LCMXO2_640HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.prf
Design file: ram2e_lcmxo2_640hc_impl1_map.ncd
Preference file: ram2e_lcmxo2_640hc_impl1.prf
Device,speed: LCMXO2-640HC,M
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
<A name="mtw1_hold_ps"></A><B><U><big>Preference Summary</big></U></B>
<LI><A href='#map_twr_pref_1_0' Target='right'>FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)</A></LI> 1491 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
<A name="map_twr_pref_1_0"></A>Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
1491 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.447ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[0] (from C14M_c +)
Destination: FF Data in FS[0] (to C14M_c +)
Delay: 0.434ns (53.9% logic, 46.1% route), 2 logic levels.
Constraint Details:
0.434ns physical path delay SLICE_0 to SLICE_0 meets
-0.013ns DIN_HLD and
0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns
Physical Path Details:
Data path SLICE_0 to SLICE_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 SLICE_0.CLK to SLICE_0.Q1 SLICE_0 (from C14M_c)
ROUTE 5 e 0.199 SLICE_0.Q1 to SLICE_0.A1 FS[0]
CTOF_DEL --- 0.101 SLICE_0.A1 to SLICE_0.F1 SLICE_0
ROUTE 1 e 0.001 SLICE_0.F1 to SLICE_0.DI1 FS_s[0] (to C14M_c)
--------
0.434 (53.9% logic, 46.1% route), 2 logic levels.
<A name="mtw1_hold_rs"></A><B><U><big>Report Summary</big></U></B>
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "C14M" 14.300000 MHz ; | -| -| 2
| | |
----------------------------------------------------------------------------
All preferences were met.
<A name="mtw1_hold_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
------------------------
Found 1 clocks:
Clock Domain: C14M_c Source: C14M.PAD Loads: 84
Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
<A name="mtw1_hold_ts"></A><B><U><big>Timing summary (Hold):</big></U></B>
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage)
<A name="mtw1_ts"></A><B><U><big>Timing summary (Setup and Hold):</big></U></B>
---------------
Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
--------------------------------------------------------------------------------
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