mirror of
https://github.com/garrettsworkshop/RAM2E.git
synced 2024-11-22 02:30:50 +00:00
7136 lines
258 KiB
Plaintext
7136 lines
258 KiB
Plaintext
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// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454
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// ldbanno -n Verilog -o RAM2E_LCMXO2_640HC_impl1_mapvo.vo -w -neg -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1_map.ncd
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// Netlist created on Thu Dec 28 23:23:28 2023
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// Netlist written on Thu Dec 28 23:23:31 2023
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// Design is for device LCMXO2-640HC
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// Design is for package TQFP100
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// Design is for performance grade 4
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`timescale 1 ns / 1 ps
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module RAM2E ( C14M, PHI1, LED, nWE, nWE80, nEN80, nC07X, Ain, Din, Dout, nDOE,
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Vout, nVOE, CKEout, nCSout, nRASout, nCASout, nRWEout, BA,
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RAout, DQML, DQMH, RD );
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input C14M, PHI1, nWE, nWE80, nEN80, nC07X;
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input [7:0] Ain;
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input [7:0] Din;
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output LED;
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output [7:0] Dout;
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output nDOE;
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output [7:0] Vout;
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output nVOE, CKEout, nCSout, nRASout, nCASout, nRWEout;
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output [1:0] BA;
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output [11:0] RAout;
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output DQML, DQMH;
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inout [7:0] RD;
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wire \FS[0] , \FS_s[0] , C14M_c, \FS_cry[0] , \FS[15] , \FS_s[15] ,
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\FS_cry[14] , \FS[14] , \FS[13] , \FS_s[14] , \FS_s[13] ,
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\FS_cry[12] , \FS[12] , \FS[11] , \FS_s[12] , \FS_s[11] ,
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\FS_cry[10] , \FS[10] , \FS[9] , \FS_s[10] , \FS_s[9] , \FS_cry[8] ,
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\FS[8] , \FS[7] , \FS_s[8] , \FS_s[7] , \FS_cry[6] , \FS[6] , \FS[5] ,
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\FS_s[6] , \FS_s[5] , \FS_cry[4] , \FS[4] , \FS[3] , \FS_s[4] ,
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\FS_s[3] , \FS_cry[2] , \FS[2] , \FS[1] , \FS_s[2] , \FS_s[1] , N_551,
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\S[1] , \S[0] , \ram2e_ufm/CKE_7 , CKE_7_RNIS77M1, CKE,
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\ram2e_ufm/wb_adr_0_sqmuxa_1_i , RWSel, CO0_0, \CmdTout_3[0] ,
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N_185_i, GND, \RC[2] , CO0_1, \RC[1] , N_360_i, RC12,
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\ram2e_ufm/N_821 , \ram2e_ufm/SUM1_0_0 , \ram2e_ufm/SUM0_i_a3_4_0 ,
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\ram2e_ufm/N_886 , \ram2e_ufm/N_215 , \ram2e_ufm/SUM0_i_4 , \CS[2] ,
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\CS[1] , CmdExecMXO2_3_0_a3_0_RNI6S1P8, N_547_i, un1_CS_0_sqmuxa_i,
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\CS[0] , \ram2e_ufm/N_234 , CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514,
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\ram2e_ufm/N_800 , \Din_c[5] , \Din_c[3] ,
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\ram2e_ufm/CmdLEDGet_3_0_a3_1 , \ram2e_ufm/N_847 , \Din_c[2] ,
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\Din_c[1] , CmdLEDGet_3, N_187_i, CmdLEDGet, \Din_c[7] , \Din_c[4] ,
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\ram2e_ufm/N_883 , CmdLEDSet_3, CmdLEDSet,
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\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_5_1 , CmdRWMaskSet_3, CmdRWMaskSet,
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\ram2e_ufm/N_850 , \Din_c[0] , CmdSetRWBankFFLED_4, CmdSetRWBankFFLED,
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\CmdTout[2] , \CmdTout[1] , N_369_i, N_368_i, \RA[1] ,
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\ram2e_ufm/N_186 , \S[3] , N_1080_0, \ram2e_ufm/N_660 , DOEEN,
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\ram2e_ufm/N_193 , \ram2e_ufm/N_659 , \ram2e_ufm/N_182 , \Ain_c[1] ,
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\ram2e_ufm/RA_35_0_0_1[0] , \ram2e_ufm/N_801 , \ram2e_ufm/N_684 ,
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N_223, \RA_35[0] , N_126, \RA[0] , \ram2e_ufm/RA_35_0_0_0[3] ,
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\ram2e_ufm/N_680 , \ram2e_ufm/N_679 , \Ain_c[2] , \RA_35[3] ,
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\RA_35[2] , \RA[2] , \RA[3] , \ram2e_ufm/RA_35_0_0_0[5] ,
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\ram2e_ufm/N_621 , \Ain_c[5] , \ram2e_ufm/RA_35_0_0_0[4] , \RA_35[5] ,
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\RA_35[4] , \RA[4] , \RA[5] , \ram2e_ufm/RA_35_0_0_0_0[7] ,
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\ram2e_ufm/RA_35_0_0_0_0[6] , \RA_35[7] , \RA_35[6] , \RA[6] ,
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\RA[7] , \ram2e_ufm/RA_35_0_0_0[9] , \RA[9] , \ram2e_ufm/N_242 ,
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\RA[8] , \ram2e_ufm/N_699 , \ram2e_ufm/N_698 , \ram2e_ufm/N_221 ,
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\RA_35[9] , un2_S_2_i_0_0_o3_RNIHFHN3, \RWBank[4] , \RA[11] ,
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\ram2e_ufm/N_845 , \ram2e_ufm/RA_35_2_0_0[10] , \ram2e_ufm/N_628 ,
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\ram2e_ufm/N_627 , \ram2e_ufm/N_624 , \RA_35[11] , \RA_35[10] ,
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\RA[10] , \RC_3[2] , \RC_3[1] , \ram2e_ufm/RWMask[1] ,
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\ram2e_ufm/N_188 , \ram2e_ufm/RWMask[0] , \RWBank_3[1] ,
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\RWBank_3[0] , \RWBank[0] , \RWBank[1] , \ram2e_ufm/RWMask[3] ,
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\ram2e_ufm/RWMask[2] , \RWBank_3[3] , \RWBank_3[2] , \RWBank[2] ,
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\RWBank[3] , \ram2e_ufm/RWMask[5] , \ram2e_ufm/RWMask[4] ,
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\RWBank_3[5] , \RWBank_3[4] , \RWBank[5] , \ram2e_ufm/RWMask[7] ,
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\ram2e_ufm/RWMask[6] , \Din_c[6] , \RWBank_3[7] , \RWBank_3[6] ,
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\RWBank[6] , \RWBank[7] , \Ain_c[3] , nWE_c, nC07X_c, RWSel_2,
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un9_VOEEN_0_a2_0_a3_0_a3, \ram2e_ufm/Ready3_0_a3_5 ,
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\ram2e_ufm/Ready3_0_a3_4 , \ram2e_ufm/Ready3_0_a3_3 ,
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\ram2e_ufm/N_885 , Ready, Ready3, N_1026_0, \ram2e_ufm/S_r_i_0_o2[1] ,
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\ram2e_ufm/N_271 , \ram2e_ufm/N_194 , S_1, \ram2e_ufm/N_643 , N_362_i,
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\S_s_0_0[0] , \S[2] , N_372_i, N_361_i, N_1078_0, VOEEN, BA_0_sqmuxa,
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\ram2e_ufm/N_285_i , \ram2e_ufm/N_804 , \ram2e_ufm/N_872 ,
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\ram2e_ufm/N_641 , \ram2e_ufm/N_640 , N_370_i, nCAS,
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\ram2e_ufm/nRAS_s_i_0_0 , \ram2e_ufm/N_617 , \ram2e_ufm/N_616 ,
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\ram2e_ufm/N_615 , N_358_i, nRAS, \ram2e_ufm/N_226 ,
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\ram2e_ufm/N_866 , \ram2e_ufm/S_r_i_0_o2_RNI62C53[1] , N_359_i, nRWE,
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\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ,
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\ram2e_ufm/CmdBitbangMXO2_3_0_a3_1 , \ram2e_ufm/CmdBitbangMXO2_3 ,
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\ram2e_ufm/CmdBitbangMXO2 , \ram2e_ufm/N_851 ,
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\ram2e_ufm/CmdExecMXO2_3 , \ram2e_ufm/CmdExecMXO2 ,
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\ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3_0 , \ram2e_ufm/N_190 ,
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\ram2e_ufm/CmdSetRWBankFFChip_3 , \ram2e_ufm/CmdSetRWBankFFChip ,
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\ram2e_ufm/wb_dato[0] , \ram2e_ufm/N_295 ,
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\ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0] , \ram2e_ufm/LEDEN ,
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\ram2e_ufm/N_212 , \ram2e_ufm/wb_dato[1] , \ram2e_ufm/N_307_i ,
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\ram2e_ufm/N_309_i , \ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ,
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\ram2e_ufm/wb_dato[3] , \ram2e_ufm/wb_dato[2] , \ram2e_ufm/N_302_i ,
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\ram2e_ufm/N_304_i , \ram2e_ufm/wb_dato[5] , \ram2e_ufm/wb_dato[4] ,
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\ram2e_ufm/N_301_i , \ram2e_ufm/N_310_i , \ram2e_ufm/wb_dato[7] ,
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\ram2e_ufm/wb_dato[6] , \ram2e_ufm/N_296 , \ram2e_ufm/N_300_i ,
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\ram2e_ufm/wb_adr_7_5_41_0_1 , \ram2e_ufm/N_768 ,
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\ram2e_ufm/wb_adr_7_i_i_5[0] , \ram2e_ufm/wb_adr_7_i_i_4[0] ,
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\ram2e_ufm/N_793 , \ram2e_ufm/wb_adr_RNO[1] ,
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\ram2e_ufm/wb_adr_7_i_i[0] , \ram2e_ufm/CmdBitbangMXO2_RNINSM62 ,
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\ram2e_ufm/wb_adr[0] , \ram2e_ufm/wb_adr[1] , \ram2e_ufm/N_268_i ,
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\ram2e_ufm/N_80_i , \ram2e_ufm/wb_adr[2] , \ram2e_ufm/wb_adr[3] ,
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\ram2e_ufm/N_290 , \ram2e_ufm/N_294 , \ram2e_ufm/wb_adr[4] ,
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\ram2e_ufm/wb_adr[5] , \ram2e_ufm/N_267_i , \ram2e_ufm/N_284 ,
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\ram2e_ufm/wb_adr[6] , \ram2e_ufm/wb_adr[7] , \ram2e_ufm/wb_ack ,
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\ram2e_ufm/N_336 , \ram2e_ufm/N_687 , \ram2e_ufm/wb_cyc_stb_RNO ,
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\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0] ,
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\ram2e_ufm/wb_cyc_stb , \ram2e_ufm/wb_dati_7_0_0_0[1] ,
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\ram2e_ufm/N_849 , \ram2e_ufm/N_611 ,
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\ram2e_ufm/wb_dati_7_0_0_0_a3_0[0] , \ram2e_ufm/N_856 ,
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\ram2e_ufm/wb_dati_7[1] , \ram2e_ufm/wb_dati_7[0] ,
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\ram2e_ufm/wb_dati[0] , \ram2e_ufm/wb_dati[1] ,
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\ram2e_ufm/wb_dati_7_0_0_0_0[3] , \ram2e_ufm/N_783 ,
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\ram2e_ufm/wb_dati_7_0_0_o3_0[2] , \ram2e_ufm/N_760 ,
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\ram2e_ufm/wb_dati_7[3] , \ram2e_ufm/wb_dati_7[2] ,
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\ram2e_ufm/wb_dati[2] , \ram2e_ufm/wb_dati[3] ,
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\ram2e_ufm/wb_dati_7_0_0_0[4] , \ram2e_ufm/N_763 , \ram2e_ufm/N_757 ,
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\ram2e_ufm/wb_dati_7[5] , \ram2e_ufm/wb_dati_7[4] ,
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\ram2e_ufm/wb_dati[4] , \ram2e_ufm/wb_dati[5] ,
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\ram2e_ufm/wb_dati_7_0_0_0_0[7] , \ram2e_ufm/wb_dati_7_0_0_RNO_0[7] ,
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\ram2e_ufm/N_604 , \ram2e_ufm/N_602 , \ram2e_ufm/wb_dati_7_0_0_0[6] ,
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\ram2e_ufm/wb_dati_7[7] , \ram2e_ufm/wb_dati_7[6] ,
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\ram2e_ufm/wb_dati[6] , \ram2e_ufm/wb_dati[7] , \ram2e_ufm/wb_reqc_1 ,
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\ram2e_ufm/wb_reqc_i , \ram2e_ufm/wb_req , \ram2e_ufm/wb_rst8 ,
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\ram2e_ufm/wb_rst16_i , \ram2e_ufm/wb_rst ,
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\ram2e_ufm/wb_we_7_iv_0_0_3_0_0 , \ram2e_ufm/N_799 ,
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\ram2e_ufm/wb_we_7_iv_0_0_3_0_1 , \ram2e_ufm/N_208 ,
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\ram2e_ufm/wb_we_RNO , \ram2e_ufm/wb_we_RNO_0 , \ram2e_ufm/wb_we ,
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\ram2e_ufm/N_338 , \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_2_2 ,
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\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0 , \ram2e_ufm/N_817 ,
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\ram2e_ufm/CKE_7_sm0 , \ram2e_ufm/N_720_tz , \ram2e_ufm/SUM0_i_0 ,
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\ram2e_ufm/N_350 , \ram2e_ufm/SUM0_i_3 , \ram2e_ufm/SUM0_i_1 ,
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\ram2e_ufm/N_187 , \ram2e_ufm/N_755 , \ram2e_ufm/N_735 ,
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\ram2e_ufm/N_345 ,
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\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0[0] ,
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\ram2e_ufm/N_777 , \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_0[0] ,
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\ram2e_ufm/N_250 , \ram2e_ufm/N_256 , \ram2e_ufm/wb_adr_7_i_i_3_1[0] ,
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\ram2e_ufm/wb_adr_7_i_i_3[0] , \ram2e_ufm/N_254 , \ram2e_ufm/N_807 ,
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\ram2e_ufm/N_876 , \ram2e_ufm/N_784 , \ram2e_ufm/N_560 , \BA_4[0] ,
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\ram2e_ufm/N_873 , \ram2e_ufm/N_781 , \ram2e_ufm/N_184 ,
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\ram2e_ufm/N_625 , \ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_a3_0_1[0] ,
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\ram2e_ufm/N_811 , \ram2e_ufm/N_206 ,
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\ram2e_ufm/wb_dati_7_0_0_a3_8_0[7] , \ram2e_ufm/N_185 ,
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\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_0_1 ,
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\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o2 ,
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\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S , \ram2e_ufm/N_637 ,
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\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0 , \ram2e_ufm/N_592 ,
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\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] ,
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\ram2e_ufm/wb_adr_7_i_i_1[0] , \ram2e_ufm/N_753 , \ram2e_ufm/N_634 ,
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\ram2e_ufm/wb_dati_7_0_0_a3_6_1[3] ,
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\ram2e_ufm/wb_dati_7_0_0_0_a3_0[3] ,
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\ram2e_ufm/wb_dati_7_0_0_a3_1[6] , \ram2e_ufm/N_890 ,
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\ram2e_ufm/N_220 , \ram2e_ufm/N_196 , \ram2e_ufm/N_243 , \Ain_c[4] ,
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\Ain_c[6] , \ram2e_ufm/wb_dati_7_0_0_a3_0_0[1] ,
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\ram2e_ufm/wb_adr_7_i_i_a3_2_0[0] , \ram2e_ufm/N_565 ,
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\ram2e_ufm/CKE_7s2_0_0_0 , \ram2e_ufm/wb_adr_7_5_41_a3_3_0 ,
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\ram2e_ufm/N_204 , \ram2e_ufm/N_595 , \ram2e_ufm/nRWE_s_i_0_63_1 ,
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\ram2e_ufm/N_792 ,
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\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3[0] ,
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\ram2e_ufm/N_553 , nEN80_c, \ram2e_ufm/N_241_i , \ram2e_ufm/N_814 ,
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N_225_i, N_201_i, N_507_i, N_508, Vout3, \BA_4[1] , \Ain_c[0] ,
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\Ain_c[7] , nDOE_c, LED_c, RDOE_i, PHI1_c, PHI1r, nVOE_c, N_263_i,
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N_667, N_648, N_662, N_666, N_663, N_665, N_664, \RD_in[0] ,
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\RD_in[7] , \RD_in[6] , \RD_in[5] , \RD_in[4] , \RD_in[3] ,
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\RD_in[2] , \RD_in[1] , DQMH_c, DQML_c, \RAout_c[11] , \RAout_c[10] ,
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\RAout_c[9] , \RAout_c[8] , \RAout_c[7] , \RAout_c[6] , \RAout_c[5] ,
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\RAout_c[4] , \RAout_c[3] , \RAout_c[2] , \RAout_c[1] , \RAout_c[0] ,
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\BA_c[1] , \BA_c[0] , nRWEout_c, nCASout_c, nRASout_c, CKEout_c,
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\Vout_c[7] , \Vout_c[6] , \Vout_c[5] , \Vout_c[4] , \Vout_c[3] ,
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\Vout_c[2] , \Vout_c[1] , \Vout_c[0] , VCCI;
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SLICE_0 SLICE_0( .A1(\FS[0] ), .DI1(\FS_s[0] ), .CLK(C14M_c), .F1(\FS_s[0] ),
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.Q1(\FS[0] ), .FCO(\FS_cry[0] ));
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SLICE_1 SLICE_1( .A0(\FS[15] ), .DI0(\FS_s[15] ), .CLK(C14M_c),
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.FCI(\FS_cry[14] ), .F0(\FS_s[15] ), .Q0(\FS[15] ));
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SLICE_2 SLICE_2( .A1(\FS[14] ), .A0(\FS[13] ), .DI1(\FS_s[14] ),
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.DI0(\FS_s[13] ), .CLK(C14M_c), .FCI(\FS_cry[12] ), .F0(\FS_s[13] ),
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.Q0(\FS[13] ), .F1(\FS_s[14] ), .Q1(\FS[14] ), .FCO(\FS_cry[14] ));
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SLICE_3 SLICE_3( .A1(\FS[12] ), .A0(\FS[11] ), .DI1(\FS_s[12] ),
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.DI0(\FS_s[11] ), .CLK(C14M_c), .FCI(\FS_cry[10] ), .F0(\FS_s[11] ),
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.Q0(\FS[11] ), .F1(\FS_s[12] ), .Q1(\FS[12] ), .FCO(\FS_cry[12] ));
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SLICE_4 SLICE_4( .A1(\FS[10] ), .A0(\FS[9] ), .DI1(\FS_s[10] ),
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.DI0(\FS_s[9] ), .CLK(C14M_c), .FCI(\FS_cry[8] ), .F0(\FS_s[9] ),
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.Q0(\FS[9] ), .F1(\FS_s[10] ), .Q1(\FS[10] ), .FCO(\FS_cry[10] ));
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SLICE_5 SLICE_5( .A1(\FS[8] ), .A0(\FS[7] ), .DI1(\FS_s[8] ),
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.DI0(\FS_s[7] ), .CLK(C14M_c), .FCI(\FS_cry[6] ), .F0(\FS_s[7] ),
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.Q0(\FS[7] ), .F1(\FS_s[8] ), .Q1(\FS[8] ), .FCO(\FS_cry[8] ));
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SLICE_6 SLICE_6( .A1(\FS[6] ), .A0(\FS[5] ), .DI1(\FS_s[6] ),
|
|
.DI0(\FS_s[5] ), .CLK(C14M_c), .FCI(\FS_cry[4] ), .F0(\FS_s[5] ),
|
|
.Q0(\FS[5] ), .F1(\FS_s[6] ), .Q1(\FS[6] ), .FCO(\FS_cry[6] ));
|
|
SLICE_7 SLICE_7( .A1(\FS[4] ), .A0(\FS[3] ), .DI1(\FS_s[4] ),
|
|
.DI0(\FS_s[3] ), .CLK(C14M_c), .FCI(\FS_cry[2] ), .F0(\FS_s[3] ),
|
|
.Q0(\FS[3] ), .F1(\FS_s[4] ), .Q1(\FS[4] ), .FCO(\FS_cry[4] ));
|
|
SLICE_8 SLICE_8( .A1(\FS[2] ), .A0(\FS[1] ), .DI1(\FS_s[2] ),
|
|
.DI0(\FS_s[1] ), .CLK(C14M_c), .FCI(\FS_cry[0] ), .F0(\FS_s[1] ),
|
|
.Q0(\FS[1] ), .F1(\FS_s[2] ), .Q1(\FS[2] ), .FCO(\FS_cry[2] ));
|
|
SLICE_9 SLICE_9( .D1(N_551), .C1(\S[1] ), .B1(\S[0] ), .A1(\FS[15] ),
|
|
.D0(N_551), .C0(\S[1] ), .B0(\S[0] ), .A0(\ram2e_ufm/CKE_7 ),
|
|
.DI0(CKE_7_RNIS77M1), .CLK(C14M_c), .F0(CKE_7_RNIS77M1), .Q0(CKE),
|
|
.F1(\ram2e_ufm/wb_adr_0_sqmuxa_1_i ));
|
|
SLICE_10 SLICE_10( .B0(RWSel), .A0(CO0_0), .DI0(\CmdTout_3[0] ),
|
|
.CE(N_185_i), .CLK(C14M_c), .F0(\CmdTout_3[0] ), .Q0(CO0_0), .F1(GND));
|
|
SLICE_11 SLICE_11( .B1(\RC[2] ), .A1(CO0_1), .C0(\RC[2] ), .B0(\RC[1] ),
|
|
.A0(CO0_1), .DI0(N_360_i), .CE(RC12), .CLK(C14M_c), .F0(N_360_i),
|
|
.Q0(CO0_1), .F1(\ram2e_ufm/N_821 ));
|
|
SLICE_12 SLICE_12( .D1(\ram2e_ufm/SUM1_0_0 ), .C1(\ram2e_ufm/SUM0_i_a3_4_0 ),
|
|
.B1(\ram2e_ufm/N_886 ), .A1(\ram2e_ufm/N_215 ), .D0(\ram2e_ufm/SUM0_i_4 ),
|
|
.C0(\ram2e_ufm/N_215 ), .B0(\CS[2] ), .A0(\CS[1] ),
|
|
.DI1(CmdExecMXO2_3_0_a3_0_RNI6S1P8), .DI0(N_547_i),
|
|
.LSR(un1_CS_0_sqmuxa_i), .CLK(C14M_c), .F0(N_547_i), .Q0(\CS[0] ),
|
|
.F1(CmdExecMXO2_3_0_a3_0_RNI6S1P8), .Q1(\CS[1] ));
|
|
SLICE_13 SLICE_13( .D1(\ram2e_ufm/N_234 ), .C1(\ram2e_ufm/N_215 ),
|
|
.B1(\CS[2] ), .A1(\CS[1] ), .D0(\ram2e_ufm/N_234 ), .C0(\ram2e_ufm/N_215 ),
|
|
.B0(\CS[2] ), .A0(\CS[1] ), .DI0(CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514),
|
|
.LSR(un1_CS_0_sqmuxa_i), .CLK(C14M_c),
|
|
.F0(CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514), .Q0(\CS[2] ),
|
|
.F1(\ram2e_ufm/SUM1_0_0 ));
|
|
SLICE_14 SLICE_14( .C1(\ram2e_ufm/N_800 ), .B1(\Din_c[5] ), .A1(\Din_c[3] ),
|
|
.D0(\ram2e_ufm/CmdLEDGet_3_0_a3_1 ), .C0(\ram2e_ufm/N_847 ),
|
|
.B0(\Din_c[2] ), .A0(\Din_c[1] ), .DI0(CmdLEDGet_3), .CE(N_187_i),
|
|
.CLK(C14M_c), .F0(CmdLEDGet_3), .Q0(CmdLEDGet), .F1(\ram2e_ufm/N_847 ));
|
|
SLICE_15 SLICE_15( .C1(\Din_c[7] ), .B1(\Din_c[1] ), .A1(\CS[2] ),
|
|
.D0(\Din_c[4] ), .C0(\Din_c[7] ), .B0(\Din_c[1] ), .A0(\ram2e_ufm/N_883 ),
|
|
.DI0(CmdLEDSet_3), .CE(N_187_i), .CLK(C14M_c), .F0(CmdLEDSet_3),
|
|
.Q0(CmdLEDSet), .F1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_5_1 ));
|
|
SLICE_16 SLICE_16( .D1(\Din_c[7] ), .C1(\Din_c[5] ), .B1(\Din_c[3] ),
|
|
.A1(\Din_c[1] ), .D0(\Din_c[4] ), .C0(\Din_c[7] ), .B0(\Din_c[1] ),
|
|
.A0(\ram2e_ufm/N_883 ), .DI0(CmdRWMaskSet_3), .CE(N_187_i), .CLK(C14M_c),
|
|
.F0(CmdRWMaskSet_3), .Q0(CmdRWMaskSet), .F1(\ram2e_ufm/N_850 ));
|
|
SLICE_17 SLICE_17( .C1(\ram2e_ufm/N_847 ), .B1(\Din_c[2] ), .A1(\Din_c[0] ),
|
|
.D0(\ram2e_ufm/N_883 ), .C0(\Din_c[7] ), .B0(\Din_c[4] ), .A0(\Din_c[1] ),
|
|
.DI0(CmdSetRWBankFFLED_4), .CE(N_187_i), .CLK(C14M_c),
|
|
.F0(CmdSetRWBankFFLED_4), .Q0(CmdSetRWBankFFLED), .F1(\ram2e_ufm/N_883 ));
|
|
SLICE_18 SLICE_18( .D1(RWSel), .C1(\CmdTout[2] ), .B1(\CmdTout[1] ),
|
|
.A1(CO0_0), .C0(RWSel), .B0(\CmdTout[1] ), .A0(CO0_0), .DI1(N_369_i),
|
|
.DI0(N_368_i), .CE(N_185_i), .CLK(C14M_c), .F0(N_368_i), .Q0(\CmdTout[1] ),
|
|
.F1(N_369_i), .Q1(\CmdTout[2] ));
|
|
SLICE_19 SLICE_19( .B1(\CS[2] ), .A1(\CS[1] ), .B0(\RA[1] ),
|
|
.A0(\ram2e_ufm/N_186 ), .M0(\S[3] ), .LSR(N_1080_0), .CLK(C14M_c),
|
|
.F0(\ram2e_ufm/N_660 ), .Q0(DOEEN), .F1(\ram2e_ufm/N_193 ));
|
|
SLICE_20 SLICE_20( .D1(\ram2e_ufm/N_660 ), .C1(\ram2e_ufm/N_659 ),
|
|
.B1(\ram2e_ufm/N_182 ), .A1(\Ain_c[1] ), .D0(\ram2e_ufm/RA_35_0_0_1[0] ),
|
|
.C0(\ram2e_ufm/N_801 ), .B0(\ram2e_ufm/N_684 ), .A0(\FS[7] ), .DI1(N_223),
|
|
.DI0(\RA_35[0] ), .CE(N_126), .CLK(C14M_c), .F0(\RA_35[0] ), .Q0(\RA[0] ),
|
|
.F1(N_223), .Q1(\RA[1] ));
|
|
SLICE_21 SLICE_21( .C1(\ram2e_ufm/RA_35_0_0_0[3] ), .B1(\ram2e_ufm/N_801 ),
|
|
.A1(\FS[10] ), .D0(\ram2e_ufm/N_680 ), .C0(\ram2e_ufm/N_679 ),
|
|
.B0(\ram2e_ufm/N_182 ), .A0(\Ain_c[2] ), .DI1(\RA_35[3] ),
|
|
.DI0(\RA_35[2] ), .CE(N_126), .CLK(C14M_c), .F0(\RA_35[2] ), .Q0(\RA[2] ),
|
|
.F1(\RA_35[3] ), .Q1(\RA[3] ));
|
|
SLICE_22 SLICE_22( .D1(\ram2e_ufm/RA_35_0_0_0[5] ), .C1(\ram2e_ufm/N_621 ),
|
|
.B1(\ram2e_ufm/N_182 ), .A1(\Ain_c[5] ), .C0(\ram2e_ufm/RA_35_0_0_0[4] ),
|
|
.B0(\ram2e_ufm/N_801 ), .A0(\FS[11] ), .DI1(\RA_35[5] ), .DI0(\RA_35[4] ),
|
|
.CE(N_126), .CLK(C14M_c), .F0(\RA_35[4] ), .Q0(\RA[4] ), .F1(\RA_35[5] ),
|
|
.Q1(\RA[5] ));
|
|
SLICE_23 SLICE_23( .C1(\ram2e_ufm/RA_35_0_0_0_0[7] ), .B1(\ram2e_ufm/N_801 ),
|
|
.A1(\FS[14] ), .C0(\ram2e_ufm/RA_35_0_0_0_0[6] ), .B0(\ram2e_ufm/N_801 ),
|
|
.A0(\FS[13] ), .DI1(\RA_35[7] ), .DI0(\RA_35[6] ), .CE(N_126),
|
|
.CLK(C14M_c), .F0(\RA_35[6] ), .Q0(\RA[6] ), .F1(\RA_35[7] ), .Q1(\RA[7] ));
|
|
SLICE_24 SLICE_24( .C1(\ram2e_ufm/RA_35_0_0_0[9] ), .B1(\RA[9] ),
|
|
.A1(\ram2e_ufm/N_242 ), .D0(\RA[8] ), .C0(\ram2e_ufm/N_699 ),
|
|
.B0(\ram2e_ufm/N_698 ), .A0(\ram2e_ufm/N_221 ), .DI1(\RA_35[9] ),
|
|
.DI0(un2_S_2_i_0_0_o3_RNIHFHN3), .CE(N_126), .CLK(C14M_c),
|
|
.F0(un2_S_2_i_0_0_o3_RNIHFHN3), .Q0(\RA[8] ), .F1(\RA_35[9] ),
|
|
.Q1(\RA[9] ));
|
|
SLICE_25 SLICE_25( .D1(\RWBank[4] ), .C1(\RA[11] ), .B1(\ram2e_ufm/N_845 ),
|
|
.A1(\ram2e_ufm/N_242 ), .D0(\ram2e_ufm/RA_35_2_0_0[10] ),
|
|
.C0(\ram2e_ufm/N_628 ), .B0(\ram2e_ufm/N_627 ), .A0(\ram2e_ufm/N_624 ),
|
|
.DI1(\RA_35[11] ), .DI0(\RA_35[10] ), .CE(N_126), .CLK(C14M_c),
|
|
.F0(\RA_35[10] ), .Q0(\RA[10] ), .F1(\RA_35[11] ), .Q1(\RA[11] ));
|
|
SLICE_26 SLICE_26( .C1(\RC[2] ), .B1(\RC[1] ), .A1(CO0_1), .C0(\RC[2] ),
|
|
.B0(CO0_1), .A0(\RC[1] ), .DI1(\RC_3[2] ), .DI0(\RC_3[1] ), .CE(RC12),
|
|
.CLK(C14M_c), .F0(\RC_3[1] ), .Q0(\RC[1] ), .F1(\RC_3[2] ), .Q1(\RC[2] ));
|
|
SLICE_27 SLICE_27( .C1(\ram2e_ufm/RWMask[1] ), .B1(\ram2e_ufm/N_188 ),
|
|
.A1(\Din_c[1] ), .C0(\ram2e_ufm/RWMask[0] ), .B0(\ram2e_ufm/N_188 ),
|
|
.A0(\Din_c[0] ), .DI1(\RWBank_3[1] ), .DI0(\RWBank_3[0] ), .CE(N_187_i),
|
|
.CLK(C14M_c), .F0(\RWBank_3[0] ), .Q0(\RWBank[0] ), .F1(\RWBank_3[1] ),
|
|
.Q1(\RWBank[1] ));
|
|
SLICE_28 SLICE_28( .C1(\ram2e_ufm/RWMask[3] ), .B1(\ram2e_ufm/N_188 ),
|
|
.A1(\Din_c[3] ), .C0(\ram2e_ufm/RWMask[2] ), .B0(\ram2e_ufm/N_188 ),
|
|
.A0(\Din_c[2] ), .DI1(\RWBank_3[3] ), .DI0(\RWBank_3[2] ), .CE(N_187_i),
|
|
.CLK(C14M_c), .F0(\RWBank_3[2] ), .Q0(\RWBank[2] ), .F1(\RWBank_3[3] ),
|
|
.Q1(\RWBank[3] ));
|
|
SLICE_29 SLICE_29( .C1(\ram2e_ufm/RWMask[5] ), .B1(\ram2e_ufm/N_188 ),
|
|
.A1(\Din_c[5] ), .C0(\ram2e_ufm/RWMask[4] ), .B0(\ram2e_ufm/N_188 ),
|
|
.A0(\Din_c[4] ), .DI1(\RWBank_3[5] ), .DI0(\RWBank_3[4] ), .CE(N_187_i),
|
|
.CLK(C14M_c), .F0(\RWBank_3[4] ), .Q0(\RWBank[4] ), .F1(\RWBank_3[5] ),
|
|
.Q1(\RWBank[5] ));
|
|
SLICE_30 SLICE_30( .C1(\ram2e_ufm/RWMask[7] ), .B1(\ram2e_ufm/N_188 ),
|
|
.A1(\Din_c[7] ), .C0(\ram2e_ufm/RWMask[6] ), .B0(\ram2e_ufm/N_188 ),
|
|
.A0(\Din_c[6] ), .DI1(\RWBank_3[7] ), .DI0(\RWBank_3[6] ), .CE(N_187_i),
|
|
.CLK(C14M_c), .F0(\RWBank_3[6] ), .Q0(\RWBank[6] ), .F1(\RWBank_3[7] ),
|
|
.Q1(\RWBank[7] ));
|
|
SLICE_31 SLICE_31( .D1(\RA[3] ), .C1(\ram2e_ufm/N_186 ),
|
|
.B1(\ram2e_ufm/N_182 ), .A1(\Ain_c[3] ), .D0(nWE_c), .C0(nC07X_c),
|
|
.B0(\RA[3] ), .A0(\RA[0] ), .DI0(RWSel_2), .CE(un9_VOEEN_0_a2_0_a3_0_a3),
|
|
.CLK(C14M_c), .F0(RWSel_2), .Q0(RWSel), .F1(\ram2e_ufm/RA_35_0_0_0[3] ));
|
|
SLICE_32 SLICE_32( .D1(\ram2e_ufm/Ready3_0_a3_5 ),
|
|
.C1(\ram2e_ufm/Ready3_0_a3_4 ), .B1(\ram2e_ufm/Ready3_0_a3_3 ),
|
|
.A1(\ram2e_ufm/N_885 ), .B0(Ready), .A0(Ready3), .DI0(N_1026_0),
|
|
.CLK(C14M_c), .F0(N_1026_0), .Q0(Ready), .F1(Ready3));
|
|
SLICE_33 SLICE_33( .D1(\ram2e_ufm/S_r_i_0_o2[1] ), .C1(\ram2e_ufm/N_271 ),
|
|
.B1(\ram2e_ufm/N_194 ), .A1(S_1), .D0(\S[1] ), .C0(\ram2e_ufm/N_643 ),
|
|
.B0(\ram2e_ufm/N_271 ), .A0(S_1), .DI1(N_362_i), .DI0(\S_s_0_0[0] ),
|
|
.CLK(C14M_c), .F0(\S_s_0_0[0] ), .Q0(\S[0] ), .F1(N_362_i), .Q1(\S[1] ));
|
|
SLICE_34 SLICE_34( .D1(\S[2] ), .C1(S_1), .B1(\ram2e_ufm/N_194 ),
|
|
.A1(\S[3] ), .D0(\S[3] ), .C0(\S[2] ), .B0(\ram2e_ufm/N_194 ), .A0(S_1),
|
|
.DI1(N_372_i), .DI0(N_361_i), .CLK(C14M_c), .F0(N_361_i), .Q0(\S[2] ),
|
|
.F1(N_372_i), .Q1(\S[3] ));
|
|
SLICE_35 SLICE_35( .D1(N_551), .C1(\S[1] ), .B1(\S[0] ), .A1(\FS[4] ),
|
|
.B0(\S[3] ), .A0(\S[2] ), .DI0(N_551), .LSR(N_1078_0), .CLK(C14M_c),
|
|
.F0(N_551), .Q0(VOEEN), .F1(BA_0_sqmuxa));
|
|
SLICE_36 SLICE_36( .D1(\ram2e_ufm/N_285_i ), .C1(\S[0] ), .B1(\S[1] ),
|
|
.A1(\ram2e_ufm/N_804 ), .D0(nWE_c), .C0(\ram2e_ufm/N_872 ),
|
|
.B0(\ram2e_ufm/N_641 ), .A0(\ram2e_ufm/N_640 ), .DI0(N_370_i),
|
|
.CLK(C14M_c), .F0(N_370_i), .Q0(nCAS), .F1(\ram2e_ufm/N_872 ));
|
|
SLICE_37 SLICE_37( .D1(\S[0] ), .C1(\S[1] ), .B1(\ram2e_ufm/N_285_i ),
|
|
.A1(\ram2e_ufm/N_804 ), .D0(\ram2e_ufm/nRAS_s_i_0_0 ),
|
|
.C0(\ram2e_ufm/N_617 ), .B0(\ram2e_ufm/N_616 ), .A0(\ram2e_ufm/N_615 ),
|
|
.DI0(N_358_i), .CLK(C14M_c), .F0(N_358_i), .Q0(nRAS),
|
|
.F1(\ram2e_ufm/N_617 ));
|
|
SLICE_38 SLICE_38( .D1(\S[2] ), .C1(\ram2e_ufm/S_r_i_0_o2[1] ),
|
|
.B1(\ram2e_ufm/N_226 ), .A1(\ram2e_ufm/N_285_i ), .D0(\ram2e_ufm/N_804 ),
|
|
.C0(\ram2e_ufm/N_866 ), .B0(\ram2e_ufm/S_r_i_0_o2_RNI62C53[1] ),
|
|
.A0(\ram2e_ufm/N_615 ), .DI0(N_359_i), .CLK(C14M_c), .F0(N_359_i),
|
|
.Q0(nRWE), .F1(\ram2e_ufm/N_615 ));
|
|
ram2e_ufm_SLICE_39 \ram2e_ufm/SLICE_39 ( .D1(\Din_c[3] ), .C1(\Din_c[5] ),
|
|
.B1(\Din_c[0] ), .A1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ),
|
|
.D0(\ram2e_ufm/CmdBitbangMXO2_3_0_a3_1 ), .C0(\ram2e_ufm/N_800 ),
|
|
.B0(\Din_c[2] ), .A0(\Din_c[1] ), .DI0(\ram2e_ufm/CmdBitbangMXO2_3 ),
|
|
.CE(N_187_i), .CLK(C14M_c), .F0(\ram2e_ufm/CmdBitbangMXO2_3 ),
|
|
.Q0(\ram2e_ufm/CmdBitbangMXO2 ), .F1(\ram2e_ufm/CmdBitbangMXO2_3_0_a3_1 ));
|
|
ram2e_ufm_SLICE_40 \ram2e_ufm/SLICE_40 ( .D1(\CS[1] ), .C1(\CS[2] ),
|
|
.B1(\CS[0] ), .A1(\Din_c[6] ), .B0(\ram2e_ufm/N_851 ),
|
|
.A0(\ram2e_ufm/N_800 ), .DI0(\ram2e_ufm/CmdExecMXO2_3 ), .CE(N_187_i),
|
|
.CLK(C14M_c), .F0(\ram2e_ufm/CmdExecMXO2_3 ), .Q0(\ram2e_ufm/CmdExecMXO2 ),
|
|
.F1(\ram2e_ufm/N_800 ));
|
|
ram2e_ufm_SLICE_41 \ram2e_ufm/SLICE_41 ( .D1(\Din_c[0] ), .C1(\Din_c[1] ),
|
|
.B1(\Din_c[2] ), .A1(\Din_c[4] ),
|
|
.D0(\ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3_0 ), .C0(\ram2e_ufm/N_800 ),
|
|
.B0(\ram2e_ufm/N_190 ), .A0(\Din_c[7] ),
|
|
.DI0(\ram2e_ufm/CmdSetRWBankFFChip_3 ), .CE(N_187_i), .CLK(C14M_c),
|
|
.F0(\ram2e_ufm/CmdSetRWBankFFChip_3 ), .Q0(\ram2e_ufm/CmdSetRWBankFFChip ),
|
|
.F1(\ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3_0 ));
|
|
ram2e_ufm_SLICE_42 \ram2e_ufm/SLICE_42 ( .C1(\Din_c[6] ), .B1(\Din_c[2] ),
|
|
.A1(\Din_c[0] ), .C0(\ram2e_ufm/wb_dato[0] ), .B0(\S[3] ), .A0(\Din_c[0] ),
|
|
.DI0(\ram2e_ufm/N_295 ), .CE(\ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0] ),
|
|
.CLK(C14M_c), .F0(\ram2e_ufm/N_295 ), .Q0(\ram2e_ufm/LEDEN ),
|
|
.F1(\ram2e_ufm/N_212 ));
|
|
ram2e_ufm_SLICE_43 \ram2e_ufm/SLICE_43 ( .C1(\ram2e_ufm/wb_dato[1] ),
|
|
.B1(\S[3] ), .A1(\Din_c[1] ), .C0(\ram2e_ufm/wb_dato[0] ), .B0(\S[3] ),
|
|
.A0(\Din_c[0] ), .DI1(\ram2e_ufm/N_307_i ), .DI0(\ram2e_ufm/N_309_i ),
|
|
.CE(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ), .CLK(C14M_c),
|
|
.F0(\ram2e_ufm/N_309_i ), .Q0(\ram2e_ufm/RWMask[0] ),
|
|
.F1(\ram2e_ufm/N_307_i ), .Q1(\ram2e_ufm/RWMask[1] ));
|
|
ram2e_ufm_SLICE_44 \ram2e_ufm/SLICE_44 ( .C1(\ram2e_ufm/wb_dato[3] ),
|
|
.B1(\S[3] ), .A1(\Din_c[3] ), .C0(\ram2e_ufm/wb_dato[2] ), .B0(\S[3] ),
|
|
.A0(\Din_c[2] ), .DI1(\ram2e_ufm/N_302_i ), .DI0(\ram2e_ufm/N_304_i ),
|
|
.CE(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ), .CLK(C14M_c),
|
|
.F0(\ram2e_ufm/N_304_i ), .Q0(\ram2e_ufm/RWMask[2] ),
|
|
.F1(\ram2e_ufm/N_302_i ), .Q1(\ram2e_ufm/RWMask[3] ));
|
|
ram2e_ufm_SLICE_45 \ram2e_ufm/SLICE_45 ( .C1(\ram2e_ufm/wb_dato[5] ),
|
|
.B1(\S[3] ), .A1(\Din_c[5] ), .C0(\ram2e_ufm/wb_dato[4] ), .B0(\S[3] ),
|
|
.A0(\Din_c[4] ), .DI1(\ram2e_ufm/N_301_i ), .DI0(\ram2e_ufm/N_310_i ),
|
|
.CE(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ), .CLK(C14M_c),
|
|
.F0(\ram2e_ufm/N_310_i ), .Q0(\ram2e_ufm/RWMask[4] ),
|
|
.F1(\ram2e_ufm/N_301_i ), .Q1(\ram2e_ufm/RWMask[5] ));
|
|
ram2e_ufm_SLICE_46 \ram2e_ufm/SLICE_46 ( .C1(\ram2e_ufm/wb_dato[7] ),
|
|
.B1(\S[3] ), .A1(\Din_c[7] ), .C0(\ram2e_ufm/wb_dato[6] ), .B0(\S[3] ),
|
|
.A0(\Din_c[6] ), .DI1(\ram2e_ufm/N_296 ), .DI0(\ram2e_ufm/N_300_i ),
|
|
.CE(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ), .CLK(C14M_c),
|
|
.F0(\ram2e_ufm/N_300_i ), .Q0(\ram2e_ufm/RWMask[6] ),
|
|
.F1(\ram2e_ufm/N_296 ), .Q1(\ram2e_ufm/RWMask[7] ));
|
|
ram2e_ufm_SLICE_47 \ram2e_ufm/SLICE_47 ( .D1(\ram2e_ufm/wb_adr_7_5_41_0_1 ),
|
|
.C1(\S[2] ), .B1(\ram2e_ufm/N_768 ), .A1(\Din_c[1] ),
|
|
.D0(\ram2e_ufm/wb_adr_7_i_i_5[0] ), .C0(\ram2e_ufm/wb_adr_7_i_i_4[0] ),
|
|
.B0(\ram2e_ufm/N_793 ), .A0(\FS[10] ), .DI1(\ram2e_ufm/wb_adr_RNO[1] ),
|
|
.DI0(\ram2e_ufm/wb_adr_7_i_i[0] ),
|
|
.CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), .CLK(C14M_c),
|
|
.F0(\ram2e_ufm/wb_adr_7_i_i[0] ), .Q0(\ram2e_ufm/wb_adr[0] ),
|
|
.F1(\ram2e_ufm/wb_adr_RNO[1] ), .Q1(\ram2e_ufm/wb_adr[1] ));
|
|
ram2e_ufm_SLICE_48 \ram2e_ufm/SLICE_48 ( .B1(\S[2] ), .A1(\Din_c[3] ),
|
|
.B0(\S[2] ), .A0(\Din_c[2] ), .DI1(\ram2e_ufm/N_268_i ),
|
|
.DI0(\ram2e_ufm/N_80_i ), .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ),
|
|
.CLK(C14M_c), .F0(\ram2e_ufm/N_80_i ), .Q0(\ram2e_ufm/wb_adr[2] ),
|
|
.F1(\ram2e_ufm/N_268_i ), .Q1(\ram2e_ufm/wb_adr[3] ));
|
|
ram2e_ufm_SLICE_49 \ram2e_ufm/SLICE_49 ( .C1(\S[2] ), .B1(\FS[14] ),
|
|
.A1(\Din_c[5] ), .C0(\S[2] ), .B0(\FS[14] ), .A0(\Din_c[4] ),
|
|
.DI1(\ram2e_ufm/N_290 ), .DI0(\ram2e_ufm/N_294 ),
|
|
.CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), .CLK(C14M_c),
|
|
.F0(\ram2e_ufm/N_294 ), .Q0(\ram2e_ufm/wb_adr[4] ), .F1(\ram2e_ufm/N_290 ),
|
|
.Q1(\ram2e_ufm/wb_adr[5] ));
|
|
ram2e_ufm_SLICE_50 \ram2e_ufm/SLICE_50 ( .B1(\S[2] ), .A1(\Din_c[7] ),
|
|
.C0(\S[2] ), .B0(\FS[14] ), .A0(\Din_c[6] ), .DI1(\ram2e_ufm/N_267_i ),
|
|
.DI0(\ram2e_ufm/N_284 ), .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ),
|
|
.CLK(C14M_c), .F0(\ram2e_ufm/N_284 ), .Q0(\ram2e_ufm/wb_adr[6] ),
|
|
.F1(\ram2e_ufm/N_267_i ), .Q1(\ram2e_ufm/wb_adr[7] ));
|
|
ram2e_ufm_SLICE_51 \ram2e_ufm/SLICE_51 ( .D1(\ram2e_ufm/wb_ack ),
|
|
.C1(\ram2e_ufm/N_336 ), .B1(\FS[14] ), .A1(\FS[0] ),
|
|
.C0(\ram2e_ufm/CmdExecMXO2 ), .B0(\S[3] ), .A0(\ram2e_ufm/N_687 ),
|
|
.DI0(\ram2e_ufm/wb_cyc_stb_RNO ),
|
|
.CE(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0] ), .CLK(C14M_c),
|
|
.F0(\ram2e_ufm/wb_cyc_stb_RNO ), .Q0(\ram2e_ufm/wb_cyc_stb ),
|
|
.F1(\ram2e_ufm/N_687 ));
|
|
ram2e_ufm_SLICE_52 \ram2e_ufm/SLICE_52 ( .D1(\ram2e_ufm/wb_dati_7_0_0_0[1] ),
|
|
.C1(\ram2e_ufm/N_849 ), .B1(\ram2e_ufm/N_793 ), .A1(\ram2e_ufm/N_611 ),
|
|
.D0(\ram2e_ufm/wb_dati_7_0_0_0_a3_0[0] ), .C0(\ram2e_ufm/wb_adr[0] ),
|
|
.B0(\S[2] ), .A0(\ram2e_ufm/N_856 ), .DI1(\ram2e_ufm/wb_dati_7[1] ),
|
|
.DI0(\ram2e_ufm/wb_dati_7[0] ), .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ),
|
|
.CLK(C14M_c), .F0(\ram2e_ufm/wb_dati_7[0] ), .Q0(\ram2e_ufm/wb_dati[0] ),
|
|
.F1(\ram2e_ufm/wb_dati_7[1] ), .Q1(\ram2e_ufm/wb_dati[1] ));
|
|
ram2e_ufm_SLICE_53 \ram2e_ufm/SLICE_53 (
|
|
.D1(\ram2e_ufm/wb_dati_7_0_0_0_0[3] ), .C1(\ram2e_ufm/N_849 ),
|
|
.B1(\ram2e_ufm/N_783 ), .A1(\ram2e_ufm/N_611 ),
|
|
.D0(\ram2e_ufm/wb_dati_7_0_0_o3_0[2] ), .C0(\ram2e_ufm/wb_adr[2] ),
|
|
.B0(\S[2] ), .A0(\ram2e_ufm/N_760 ), .DI1(\ram2e_ufm/wb_dati_7[3] ),
|
|
.DI0(\ram2e_ufm/wb_dati_7[2] ), .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ),
|
|
.CLK(C14M_c), .F0(\ram2e_ufm/wb_dati_7[2] ), .Q0(\ram2e_ufm/wb_dati[2] ),
|
|
.F1(\ram2e_ufm/wb_dati_7[3] ), .Q1(\ram2e_ufm/wb_dati[3] ));
|
|
ram2e_ufm_SLICE_54 \ram2e_ufm/SLICE_54 (
|
|
.D1(\ram2e_ufm/wb_dati_7_0_0_o3_0[2] ), .C1(\ram2e_ufm/wb_adr[5] ),
|
|
.B1(\S[2] ), .A1(\ram2e_ufm/N_760 ), .D0(\ram2e_ufm/wb_dati_7_0_0_0[4] ),
|
|
.C0(\ram2e_ufm/N_763 ), .B0(\ram2e_ufm/N_760 ), .A0(\ram2e_ufm/N_757 ),
|
|
.DI1(\ram2e_ufm/wb_dati_7[5] ), .DI0(\ram2e_ufm/wb_dati_7[4] ),
|
|
.CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), .CLK(C14M_c),
|
|
.F0(\ram2e_ufm/wb_dati_7[4] ), .Q0(\ram2e_ufm/wb_dati[4] ),
|
|
.F1(\ram2e_ufm/wb_dati_7[5] ), .Q1(\ram2e_ufm/wb_dati[5] ));
|
|
ram2e_ufm_SLICE_55 \ram2e_ufm/SLICE_55 (
|
|
.D1(\ram2e_ufm/wb_dati_7_0_0_0_0[7] ),
|
|
.C1(\ram2e_ufm/wb_dati_7_0_0_RNO_0[7] ), .B1(\ram2e_ufm/N_604 ),
|
|
.A1(\ram2e_ufm/N_602 ), .D0(\ram2e_ufm/wb_dati_7_0_0_0[6] ),
|
|
.C0(\ram2e_ufm/N_849 ), .B0(\ram2e_ufm/N_793 ), .A0(\ram2e_ufm/N_757 ),
|
|
.DI1(\ram2e_ufm/wb_dati_7[7] ), .DI0(\ram2e_ufm/wb_dati_7[6] ),
|
|
.CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), .CLK(C14M_c),
|
|
.F0(\ram2e_ufm/wb_dati_7[6] ), .Q0(\ram2e_ufm/wb_dati[6] ),
|
|
.F1(\ram2e_ufm/wb_dati_7[7] ), .Q1(\ram2e_ufm/wb_dati[7] ));
|
|
ram2e_ufm_SLICE_56 \ram2e_ufm/SLICE_56 ( .D1(\S[3] ), .C1(\S[1] ),
|
|
.B1(\S[0] ), .A1(\FS[14] ), .D0(\ram2e_ufm/wb_reqc_1 ), .C0(\FS[13] ),
|
|
.B0(\FS[12] ), .A0(\FS[11] ), .DI0(\ram2e_ufm/wb_reqc_i ),
|
|
.CE(\ram2e_ufm/wb_adr_0_sqmuxa_1_i ), .LSR(\S[2] ), .CLK(C14M_c),
|
|
.F0(\ram2e_ufm/wb_reqc_i ), .Q0(\ram2e_ufm/wb_req ),
|
|
.F1(\ram2e_ufm/wb_reqc_1 ));
|
|
ram2e_ufm_SLICE_57 \ram2e_ufm/SLICE_57 ( .D1(\FS[15] ), .C1(\FS[14] ),
|
|
.B1(\FS[4] ), .A1(\FS[2] ), .B0(\FS[15] ), .A0(\FS[14] ),
|
|
.DI0(\ram2e_ufm/wb_rst8 ), .LSR(\ram2e_ufm/wb_rst16_i ), .CLK(C14M_c),
|
|
.F0(\ram2e_ufm/wb_rst8 ), .Q0(\ram2e_ufm/wb_rst ),
|
|
.F1(\ram2e_ufm/Ready3_0_a3_4 ));
|
|
ram2e_ufm_SLICE_58 \ram2e_ufm/SLICE_58 (
|
|
.D1(\ram2e_ufm/wb_we_7_iv_0_0_3_0_0 ), .C1(\ram2e_ufm/N_885 ),
|
|
.B1(\ram2e_ufm/N_799 ), .A1(\FS[12] ),
|
|
.D0(\ram2e_ufm/wb_we_7_iv_0_0_3_0_1 ), .C0(\ram2e_ufm/N_799 ),
|
|
.B0(\ram2e_ufm/N_208 ), .A0(\FS[13] ), .DI0(\ram2e_ufm/wb_we_RNO ),
|
|
.CE(\ram2e_ufm/wb_we_RNO_0 ), .CLK(C14M_c), .F0(\ram2e_ufm/wb_we_RNO ),
|
|
.Q0(\ram2e_ufm/wb_we ), .F1(\ram2e_ufm/wb_we_7_iv_0_0_3_0_1 ));
|
|
ram2e_ufm_SUM0_i_m3_0_SLICE_59 \ram2e_ufm/SUM0_i_m3_0/SLICE_59 (
|
|
.C1(\CS[1] ), .B1(\Din_c[5] ), .A1(\Din_c[3] ), .C0(\Din_c[7] ),
|
|
.B0(\Din_c[5] ), .A0(\Din_c[3] ), .M0(\Din_c[1] ),
|
|
.OFX0(\ram2e_ufm/N_338 ));
|
|
ram2e_ufm_un1_CS_0_sqmuxa_0_0_0_SLICE_60
|
|
\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60 ( .D1(\CS[0] ), .C1(\Din_c[6] ),
|
|
.B1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_2_2 ), .A1(\ram2e_ufm/N_193 ),
|
|
.C0(CO0_0), .B0(\CmdTout[1] ), .A0(\CmdTout[2] ), .M0(RWSel),
|
|
.OFX0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0 ));
|
|
ram2e_ufm_CKE_7_SLICE_61 \ram2e_ufm/CKE_7/SLICE_61 ( .C1(\RC[1] ),
|
|
.B1(\ram2e_ufm/N_821 ), .A1(\ram2e_ufm/N_817 ), .C0(nWE_c), .B0(\S[1] ),
|
|
.A0(\ram2e_ufm/N_804 ), .M0(\ram2e_ufm/CKE_7_sm0 ),
|
|
.OFX0(\ram2e_ufm/CKE_7 ));
|
|
ram2e_ufm_SLICE_62 \ram2e_ufm/SLICE_62 ( .D1(\ram2e_ufm/N_851 ),
|
|
.C1(\Din_c[6] ), .B1(\CS[2] ), .A1(\CS[1] ),
|
|
.D0(\ram2e_ufm/SUM0_i_a3_4_0 ), .C0(\ram2e_ufm/N_234 ), .B0(\CS[2] ),
|
|
.A0(\CS[1] ), .F0(\ram2e_ufm/N_720_tz ), .F1(\ram2e_ufm/SUM0_i_a3_4_0 ));
|
|
ram2e_ufm_SLICE_63 \ram2e_ufm/SLICE_63 ( .D1(\ram2e_ufm/SUM0_i_0 ),
|
|
.C1(\ram2e_ufm/N_350 ), .B1(\CS[2] ), .A1(\CS[0] ),
|
|
.D0(\ram2e_ufm/SUM0_i_3 ), .C0(\ram2e_ufm/SUM0_i_1 ),
|
|
.B0(\ram2e_ufm/N_187 ), .A0(\CS[0] ), .F0(\ram2e_ufm/SUM0_i_4 ),
|
|
.F1(\ram2e_ufm/SUM0_i_1 ));
|
|
ram2e_ufm_SLICE_64 \ram2e_ufm/SLICE_64 ( .C1(\ram2e_ufm/N_793 ),
|
|
.B1(\FS[11] ), .A1(\FS[9] ), .D0(\ram2e_ufm/N_856 ),
|
|
.C0(\ram2e_ufm/N_755 ), .B0(\FS[13] ), .A0(\FS[11] ),
|
|
.F0(\ram2e_ufm/wb_adr_7_i_i_5[0] ), .F1(\ram2e_ufm/N_755 ));
|
|
ram2e_ufm_SLICE_65 \ram2e_ufm/SLICE_65 ( .D1(\ram2e_ufm/N_193 ),
|
|
.C1(\Din_c[6] ), .B1(\Din_c[0] ), .A1(\CS[0] ), .D0(\ram2e_ufm/N_735 ),
|
|
.C0(\ram2e_ufm/N_345 ), .B0(\CS[1] ), .A0(\CS[0] ),
|
|
.F0(\ram2e_ufm/SUM0_i_0 ), .F1(\ram2e_ufm/N_735 ));
|
|
ram2e_ufm_SLICE_66 \ram2e_ufm/SLICE_66 ( .D1(\ram2e_ufm/wb_ack ),
|
|
.C1(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0[0] ),
|
|
.B1(\ram2e_ufm/N_777 ), .A1(\FS[14] ), .D0(\ram2e_ufm/wb_ack ),
|
|
.C0(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_0[0] ),
|
|
.B0(\ram2e_ufm/CmdExecMXO2 ), .A0(\ram2e_ufm/N_187 ),
|
|
.F0(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0] ),
|
|
.F1(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_0[0] ));
|
|
ram2e_ufm_SLICE_67 \ram2e_ufm/SLICE_67 ( .C1(\FS[3] ), .B1(\FS[2] ),
|
|
.A1(\FS[1] ), .D0(\S[1] ), .C0(\ram2e_ufm/N_250 ), .B0(\FS[4] ),
|
|
.A0(\FS[3] ), .F0(\ram2e_ufm/N_256 ), .F1(\ram2e_ufm/N_250 ));
|
|
ram2e_ufm_SLICE_68 \ram2e_ufm/SLICE_68 (
|
|
.D1(\ram2e_ufm/wb_adr_7_i_i_3_1[0] ), .C1(\ram2e_ufm/N_783 ), .B1(\FS[9] ),
|
|
.A1(\FS[8] ), .D0(\FS[12] ), .C0(\FS[11] ), .B0(\FS[10] ), .A0(\FS[8] ),
|
|
.F0(\ram2e_ufm/wb_adr_7_i_i_3_1[0] ), .F1(\ram2e_ufm/wb_adr_7_i_i_3[0] ));
|
|
ram2e_ufm_SLICE_69 \ram2e_ufm/SLICE_69 ( .D1(\ram2e_ufm/N_254 ),
|
|
.C1(\ram2e_ufm/wb_rst16_i ), .B1(\FS[15] ), .A1(\FS[0] ), .D0(\S[2] ),
|
|
.C0(\S[3] ), .B0(\S[1] ), .A0(\S[0] ), .F0(\ram2e_ufm/wb_rst16_i ),
|
|
.F1(\ram2e_ufm/N_641 ));
|
|
ram2e_ufm_SLICE_70 \ram2e_ufm/SLICE_70 ( .C1(\FS[14] ),
|
|
.B1(\ram2e_ufm/N_777 ), .A1(\FS[8] ), .D0(\FS[12] ), .C0(\FS[13] ),
|
|
.B0(\ram2e_ufm/N_807 ), .A0(\ram2e_ufm/N_876 ), .F0(\ram2e_ufm/N_604 ),
|
|
.F1(\ram2e_ufm/N_807 ));
|
|
ram2e_ufm_SLICE_71 \ram2e_ufm/SLICE_71 ( .C1(\FS[4] ),
|
|
.B1(\ram2e_ufm/N_784 ), .A1(\FS[3] ), .C0(\S[2] ), .B0(\S[3] ),
|
|
.A0(\S[0] ), .F0(\ram2e_ufm/N_784 ), .F1(\ram2e_ufm/N_801 ));
|
|
ram2e_ufm_SLICE_72 \ram2e_ufm/SLICE_72 ( .D1(\S[0] ), .C1(\RWBank[5] ),
|
|
.B1(\ram2e_ufm/N_560 ), .A1(\FS[4] ), .C0(\S[2] ), .B0(\S[3] ),
|
|
.A0(\S[1] ), .F0(\ram2e_ufm/N_560 ), .F1(\BA_4[0] ));
|
|
ram2e_ufm_SLICE_73 \ram2e_ufm/SLICE_73 ( .D1(\ram2e_ufm/N_873 ),
|
|
.C1(\ram2e_ufm/N_781 ), .B1(\ram2e_ufm/N_611 ), .A1(\ram2e_ufm/N_184 ),
|
|
.D0(\FS[8] ), .C0(\FS[9] ), .B0(\FS[10] ), .A0(\FS[11] ),
|
|
.F0(\ram2e_ufm/N_873 ), .F1(\ram2e_ufm/wb_dati_7_0_0_o3_0[2] ));
|
|
ram2e_ufm_SLICE_74 \ram2e_ufm/SLICE_74 ( .C1(\RWBank[3] ),
|
|
.B1(\ram2e_ufm/N_845 ), .A1(\ram2e_ufm/N_625 ), .D0(\S[0] ), .C0(\S[1] ),
|
|
.B0(\S[2] ), .A0(\S[3] ), .F0(\ram2e_ufm/N_845 ),
|
|
.F1(\ram2e_ufm/RA_35_2_0_0[10] ));
|
|
ram2e_ufm_SLICE_75 \ram2e_ufm/SLICE_75 ( .C1(\FS[11] ), .B1(\FS[10] ),
|
|
.A1(\FS[9] ), .D0(\FS[12] ), .C0(\FS[13] ), .B0(\ram2e_ufm/N_876 ),
|
|
.A0(\ram2e_ufm/wb_ack ),
|
|
.F0(\ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_a3_0_1[0] ),
|
|
.F1(\ram2e_ufm/N_876 ));
|
|
ram2e_ufm_SLICE_76 \ram2e_ufm/SLICE_76 ( .B1(\FS[11] ), .A1(\FS[10] ),
|
|
.D0(\FS[12] ), .C0(\FS[13] ), .B0(\ram2e_ufm/N_811 ),
|
|
.A0(\ram2e_ufm/N_206 ), .F0(\ram2e_ufm/wb_dati_7_0_0_a3_8_0[7] ),
|
|
.F1(\ram2e_ufm/N_811 ));
|
|
ram2e_ufm_SLICE_77 \ram2e_ufm/SLICE_77 ( .C1(\ram2e_ufm/N_185 ), .B1(RWSel),
|
|
.A1(\CS[0] ), .D0(\S[0] ), .C0(\S[1] ), .B0(\S[2] ), .A0(\S[3] ),
|
|
.F0(\ram2e_ufm/N_185 ), .F1(\ram2e_ufm/N_215 ));
|
|
ram2e_ufm_SLICE_78 \ram2e_ufm/SLICE_78 ( .B1(\S[1] ), .A1(\S[0] ),
|
|
.D0(\ram2e_ufm/S_r_i_0_o2[1] ), .C0(\S[2] ), .B0(\S[3] ), .A0(\RWBank[1] ),
|
|
.F0(\ram2e_ufm/N_699 ), .F1(\ram2e_ufm/S_r_i_0_o2[1] ));
|
|
ram2e_ufm_SLICE_79 \ram2e_ufm/SLICE_79 (
|
|
.D1(\ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_a3_0_1[0] ),
|
|
.C1(\ram2e_ufm/N_807 ), .B1(\ram2e_ufm/N_187 ), .A1(CmdLEDSet),
|
|
.D0(\ram2e_ufm/S_r_i_0_o2[1] ), .C0(\S[2] ), .B0(\S[3] ), .A0(RWSel),
|
|
.F0(\ram2e_ufm/N_187 ), .F1(\ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0] ));
|
|
ram2e_ufm_SLICE_80 \ram2e_ufm/SLICE_80 ( .D1(N_551), .C1(\S[1] ),
|
|
.B1(\S[0] ), .A1(\FS[15] ), .D0(\ram2e_ufm/N_185 ), .C0(RWSel),
|
|
.B0(\ram2e_ufm/N_777 ), .A0(\ram2e_ufm/CmdBitbangMXO2 ),
|
|
.F0(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), .F1(\ram2e_ufm/N_777 ));
|
|
ram2e_ufm_SLICE_81 \ram2e_ufm/SLICE_81 ( .D1(\FS[8] ),
|
|
.C1(\ram2e_ufm/N_777 ), .B1(\FS[14] ), .A1(\FS[9] ), .D0(\FS[12] ),
|
|
.C0(\FS[13] ), .B0(\ram2e_ufm/N_811 ), .A0(\ram2e_ufm/N_856 ),
|
|
.F0(\ram2e_ufm/N_757 ), .F1(\ram2e_ufm/N_856 ));
|
|
ram2e_ufm_SLICE_82 \ram2e_ufm/SLICE_82 (
|
|
.D1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_0_1 ),
|
|
.C1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o2 ), .B1(\Din_c[6] ), .A1(\CS[0] ),
|
|
.D0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0 ),
|
|
.C0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S ),
|
|
.B0(\ram2e_ufm/N_637 ), .A0(\ram2e_ufm/N_185 ), .F0(un1_CS_0_sqmuxa_i),
|
|
.F1(\ram2e_ufm/N_637 ));
|
|
ram2e_ufm_SLICE_83 \ram2e_ufm/SLICE_83 ( .C1(\ram2e_ufm/N_851 ),
|
|
.B1(\Din_c[6] ), .A1(\CS[2] ), .D0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0 ),
|
|
.C0(RWSel), .B0(\ram2e_ufm/N_592 ), .A0(\CS[0] ),
|
|
.F0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S ),
|
|
.F1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0 ));
|
|
ram2e_ufm_SLICE_84 \ram2e_ufm/SLICE_84 ( .D1(\ram2e_ufm/N_850 ),
|
|
.C1(\ram2e_ufm/N_212 ), .B1(\Din_c[4] ), .A1(\CS[2] ),
|
|
.D0(\ram2e_ufm/N_886 ), .C0(\ram2e_ufm/N_720_tz ), .B0(\ram2e_ufm/N_187 ),
|
|
.A0(\CS[1] ), .F0(\ram2e_ufm/SUM0_i_3 ), .F1(\ram2e_ufm/N_886 ));
|
|
ram2e_ufm_SLICE_85 \ram2e_ufm/SLICE_85 ( .D1(\FS[13] ),
|
|
.C1(\ram2e_ufm/N_777 ), .B1(\FS[14] ), .A1(\FS[12] ),
|
|
.D0(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] ),
|
|
.C0(\ram2e_ufm/N_793 ), .B0(\ram2e_ufm/N_187 ), .A0(CmdRWMaskSet),
|
|
.F0(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ), .F1(\ram2e_ufm/N_793 ));
|
|
ram2e_ufm_SLICE_86 \ram2e_ufm/SLICE_86 ( .B1(\S[2] ), .A1(\Din_c[0] ),
|
|
.D0(\ram2e_ufm/wb_adr_7_i_i_3[0] ), .C0(\ram2e_ufm/wb_adr_7_i_i_1[0] ),
|
|
.B0(\ram2e_ufm/N_753 ), .A0(\ram2e_ufm/N_634 ),
|
|
.F0(\ram2e_ufm/wb_adr_7_i_i_4[0] ), .F1(\ram2e_ufm/N_634 ));
|
|
ram2e_ufm_SLICE_87 \ram2e_ufm/SLICE_87 (
|
|
.D1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ), .C1(\ram2e_ufm/N_212 ),
|
|
.B1(\ram2e_ufm/N_190 ), .A1(\Din_c[1] ), .C0(\ram2e_ufm/N_886 ),
|
|
.B0(\ram2e_ufm/N_234 ), .A0(\CS[1] ), .F0(\ram2e_ufm/N_592 ),
|
|
.F1(\ram2e_ufm/N_234 ));
|
|
ram2e_ufm_SLICE_88 \ram2e_ufm/SLICE_88 ( .B1(\FS[11] ), .A1(\FS[10] ),
|
|
.D0(\ram2e_ufm/wb_dati_7_0_0_a3_6_1[3] ), .C0(\ram2e_ufm/N_876 ),
|
|
.B0(\ram2e_ufm/N_793 ), .A0(\ram2e_ufm/N_206 ),
|
|
.F0(\ram2e_ufm/wb_dati_7_0_0_RNO_0[7] ),
|
|
.F1(\ram2e_ufm/wb_dati_7_0_0_a3_6_1[3] ));
|
|
ram2e_ufm_SLICE_89 \ram2e_ufm/SLICE_89 ( .C1(\FS[14] ),
|
|
.B1(\ram2e_ufm/N_777 ), .A1(\FS[13] ),
|
|
.D0(\ram2e_ufm/wb_dati_7_0_0_0_a3_0[3] ), .C0(\ram2e_ufm/wb_adr[3] ),
|
|
.B0(\S[2] ), .A0(\ram2e_ufm/N_783 ), .F0(\ram2e_ufm/wb_dati_7_0_0_0_0[3] ),
|
|
.F1(\ram2e_ufm/N_783 ));
|
|
ram2e_ufm_SLICE_90 \ram2e_ufm/SLICE_90 ( .D1(\ram2e_ufm/N_206 ),
|
|
.C1(\FS[12] ), .B1(\FS[11] ), .A1(\FS[10] ),
|
|
.D0(\ram2e_ufm/wb_dati_7_0_0_a3_1[6] ), .C0(\ram2e_ufm/wb_adr[6] ),
|
|
.B0(\S[2] ), .A0(\ram2e_ufm/N_783 ), .F0(\ram2e_ufm/wb_dati_7_0_0_0[6] ),
|
|
.F1(\ram2e_ufm/wb_dati_7_0_0_a3_1[6] ));
|
|
ram2e_ufm_SLICE_91 \ram2e_ufm/SLICE_91 ( .D1(CO0_1), .C1(\RC[2] ),
|
|
.B1(\ram2e_ufm/N_817 ), .A1(\RC[1] ), .D0(\ram2e_ufm/N_890 ),
|
|
.C0(\ram2e_ufm/N_784 ), .B0(\ram2e_ufm/N_256 ), .A0(\ram2e_ufm/N_285_i ),
|
|
.F0(\ram2e_ufm/nRAS_s_i_0_0 ), .F1(\ram2e_ufm/N_890 ));
|
|
ram2e_ufm_SLICE_92 \ram2e_ufm/SLICE_92 ( .D1(nWE_c), .C1(\S[1] ),
|
|
.B1(\ram2e_ufm/N_804 ), .A1(N_551), .D0(\S[0] ), .C0(\ram2e_ufm/N_890 ),
|
|
.B0(\ram2e_ufm/N_220 ), .A0(\ram2e_ufm/N_285_i ), .F0(\ram2e_ufm/N_640 ),
|
|
.F1(\ram2e_ufm/N_220 ));
|
|
ram2e_ufm_SLICE_93 \ram2e_ufm/SLICE_93 ( .D1(\FS[11] ), .C1(\FS[10] ),
|
|
.B1(\FS[9] ), .A1(\FS[8] ), .C0(\ram2e_ufm/N_783 ), .B0(\ram2e_ufm/N_196 ),
|
|
.A0(\FS[12] ), .F0(\ram2e_ufm/N_760 ), .F1(\ram2e_ufm/N_196 ));
|
|
ram2e_ufm_SLICE_94 \ram2e_ufm/SLICE_94 ( .B1(\Din_c[7] ), .A1(\Din_c[4] ),
|
|
.D0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ), .C0(\ram2e_ufm/N_243 ),
|
|
.B0(\Din_c[0] ), .A0(\CS[2] ), .F0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_2_2 ),
|
|
.F1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ));
|
|
ram2e_ufm_SLICE_95 \ram2e_ufm/SLICE_95 ( .D1(\S[3] ), .C1(\S[2] ),
|
|
.B1(\S[1] ), .A1(\S[0] ), .D0(\RA[4] ), .C0(\ram2e_ufm/N_186 ),
|
|
.B0(\ram2e_ufm/N_182 ), .A0(\Ain_c[4] ), .F0(\ram2e_ufm/RA_35_0_0_0[4] ),
|
|
.F1(\ram2e_ufm/N_182 ));
|
|
ram2e_ufm_SLICE_96 \ram2e_ufm/SLICE_96 ( .D1(\S[3] ), .C1(\S[2] ),
|
|
.B1(\S[1] ), .A1(\S[0] ), .D0(\RA[6] ), .C0(\ram2e_ufm/N_186 ),
|
|
.B0(\ram2e_ufm/N_182 ), .A0(\Ain_c[6] ), .F0(\ram2e_ufm/RA_35_0_0_0_0[6] ),
|
|
.F1(\ram2e_ufm/N_186 ));
|
|
ram2e_ufm_SLICE_97 \ram2e_ufm/SLICE_97 ( .C1(\ram2e_ufm/N_873 ),
|
|
.B1(\FS[13] ), .A1(\FS[12] ), .D0(\ram2e_ufm/wb_dati_7_0_0_a3_0_0[1] ),
|
|
.C0(\ram2e_ufm/wb_adr[1] ), .B0(\S[2] ), .A0(\ram2e_ufm/N_781 ),
|
|
.F0(\ram2e_ufm/wb_dati_7_0_0_0[1] ),
|
|
.F1(\ram2e_ufm/wb_dati_7_0_0_a3_0_0[1] ));
|
|
ram2e_ufm_SLICE_98 \ram2e_ufm/SLICE_98 ( .B1(\ram2e_ufm/N_777 ),
|
|
.A1(\FS[14] ), .D0(\ram2e_ufm/wb_dati_7_0_0_a3_8_0[7] ),
|
|
.C0(\ram2e_ufm/wb_adr[7] ), .B0(\S[2] ), .A0(\ram2e_ufm/N_781 ),
|
|
.F0(\ram2e_ufm/wb_dati_7_0_0_0_0[7] ), .F1(\ram2e_ufm/N_781 ));
|
|
ram2e_ufm_SLICE_99 \ram2e_ufm/SLICE_99 ( .C1(\FS[11] ), .B1(\FS[10] ),
|
|
.A1(\FS[8] ), .D0(\ram2e_ufm/wb_adr_7_i_i_a3_2_0[0] ),
|
|
.C0(\ram2e_ufm/N_781 ), .B0(\ram2e_ufm/N_565 ), .A0(\FS[12] ),
|
|
.F0(\ram2e_ufm/wb_adr_7_i_i_1[0] ),
|
|
.F1(\ram2e_ufm/wb_adr_7_i_i_a3_2_0[0] ));
|
|
ram2e_ufm_SLICE_100 \ram2e_ufm/SLICE_100 ( .D1(\Din_c[5] ), .C1(\Din_c[3] ),
|
|
.B1(\Din_c[2] ), .A1(\Din_c[1] ), .D0(\ram2e_ufm/N_243 ), .C0(\Din_c[7] ),
|
|
.B0(\Din_c[4] ), .A0(\CS[2] ), .F0(\ram2e_ufm/N_345 ),
|
|
.F1(\ram2e_ufm/N_243 ));
|
|
ram2e_ufm_SLICE_101 \ram2e_ufm/SLICE_101 ( .B1(\Din_c[5] ), .A1(\Din_c[3] ),
|
|
.D0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_5_1 ), .C0(\ram2e_ufm/N_850 ),
|
|
.B0(\ram2e_ufm/N_190 ), .A0(\CS[1] ),
|
|
.F0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o2 ), .F1(\ram2e_ufm/N_190 ));
|
|
ram2e_ufm_SLICE_102 \ram2e_ufm/SLICE_102 ( .C1(\S[3] ), .B1(\S[2] ),
|
|
.A1(\S[1] ), .C0(\ram2e_ufm/CKE_7s2_0_0_0 ), .B0(\ram2e_ufm/N_817 ),
|
|
.A0(\ram2e_ufm/N_220 ), .F0(\ram2e_ufm/CKE_7_sm0 ), .F1(\ram2e_ufm/N_817 ));
|
|
ram2e_ufm_SLICE_103 \ram2e_ufm/SLICE_103 ( .B1(\FS[13] ), .A1(\FS[12] ),
|
|
.D0(\ram2e_ufm/wb_adr_7_5_41_a3_3_0 ), .C0(\ram2e_ufm/N_799 ),
|
|
.B0(\ram2e_ufm/N_204 ), .A0(\ram2e_ufm/N_184 ),
|
|
.F0(\ram2e_ufm/wb_adr_7_5_41_0_1 ), .F1(\ram2e_ufm/N_184 ));
|
|
ram2e_ufm_SLICE_104 \ram2e_ufm/SLICE_104 ( .D1(\FS[11] ), .C1(\FS[10] ),
|
|
.B1(\FS[9] ), .A1(\FS[8] ), .B0(\ram2e_ufm/N_595 ), .A0(\FS[12] ),
|
|
.F0(\ram2e_ufm/wb_dati_7_0_0_0_a3_0[3] ), .F1(\ram2e_ufm/N_595 ));
|
|
ram2e_ufm_SLICE_105 \ram2e_ufm/SLICE_105 ( .D1(\ram2e_ufm/nRWE_s_i_0_63_1 ),
|
|
.C1(\S[3] ), .B1(\ram2e_ufm/S_r_i_0_o2[1] ), .A1(\ram2e_ufm/N_285_i ),
|
|
.C0(\ram2e_ufm/wb_rst16_i ), .B0(\FS[15] ), .A0(\FS[0] ),
|
|
.F0(\ram2e_ufm/N_285_i ), .F1(\ram2e_ufm/S_r_i_0_o2_RNI62C53[1] ));
|
|
ram2e_ufm_SLICE_106 \ram2e_ufm/SLICE_106 ( .B1(\S[1] ), .A1(\S[0] ),
|
|
.D0(\S[2] ), .C0(\RA[10] ), .B0(\ram2e_ufm/S_r_i_0_o2[1] ),
|
|
.A0(\ram2e_ufm/N_194 ), .F0(\ram2e_ufm/N_624 ), .F1(\ram2e_ufm/N_194 ));
|
|
ram2e_ufm_SLICE_107 \ram2e_ufm/SLICE_107 ( .D1(\S[0] ), .C1(\FS[4] ),
|
|
.B1(\S[3] ), .A1(\S[2] ), .D0(\ram2e_ufm/N_792 ), .C0(\FS[8] ),
|
|
.B0(\FS[5] ), .A0(\FS[3] ), .F0(\ram2e_ufm/N_659 ), .F1(\ram2e_ufm/N_792 ));
|
|
ram2e_ufm_SLICE_108 \ram2e_ufm/SLICE_108 (
|
|
.D1(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3[0] ), .C1(\FS[7] ),
|
|
.B1(\FS[5] ), .A1(\FS[4] ), .C0(\ram2e_ufm/wb_req ),
|
|
.B0(\ram2e_ufm/N_336 ), .A0(\FS[0] ),
|
|
.F0(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0[0] ),
|
|
.F1(\ram2e_ufm/N_336 ));
|
|
ram2e_ufm_SLICE_109 \ram2e_ufm/SLICE_109 ( .B1(\S[2] ), .A1(\FS[14] ),
|
|
.D0(\ram2e_ufm/N_799 ), .C0(\ram2e_ufm/N_634 ), .B0(\ram2e_ufm/N_184 ),
|
|
.A0(\FS[11] ), .F0(\ram2e_ufm/wb_we_7_iv_0_0_3_0_0 ),
|
|
.F1(\ram2e_ufm/N_799 ));
|
|
ram2e_ufm_SLICE_110 \ram2e_ufm/SLICE_110 ( .D1(\FS[8] ), .C1(\FS[9] ),
|
|
.B1(\FS[11] ), .A1(\FS[10] ), .B0(\ram2e_ufm/wb_ack ),
|
|
.A0(\ram2e_ufm/N_885 ),
|
|
.F0(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] ),
|
|
.F1(\ram2e_ufm/N_885 ));
|
|
ram2e_ufm_SLICE_111 \ram2e_ufm/SLICE_111 ( .C1(\ram2e_ufm/N_807 ),
|
|
.B1(\ram2e_ufm/N_553 ), .A1(\FS[12] ),
|
|
.D0(\ram2e_ufm/wb_dati_7_0_0_a3_6_1[3] ), .C0(\ram2e_ufm/N_811 ),
|
|
.B0(\FS[13] ), .A0(\FS[9] ), .F0(\ram2e_ufm/N_553 ),
|
|
.F1(\ram2e_ufm/N_611 ));
|
|
ram2e_ufm_SLICE_112 \ram2e_ufm/SLICE_112 ( .C1(\S[1] ), .B1(\S[0] ),
|
|
.A1(\ram2e_ufm/N_285_i ), .D0(nWE_c), .C0(nEN80_c), .B0(\S[2] ),
|
|
.A0(\ram2e_ufm/N_866 ), .F0(\ram2e_ufm/N_616 ), .F1(\ram2e_ufm/N_866 ));
|
|
ram2e_ufm_SLICE_113 \ram2e_ufm/SLICE_113 ( .C1(nEN80_c), .B1(\S[3] ),
|
|
.A1(\S[2] ), .D0(nWE_c), .C0(\S[1] ), .B0(\S[0] ), .A0(\ram2e_ufm/N_804 ),
|
|
.F0(\ram2e_ufm/N_628 ), .F1(\ram2e_ufm/N_804 ));
|
|
ram2e_ufm_SLICE_114 \ram2e_ufm/SLICE_114 ( .C1(\FS[10] ), .B1(\FS[9] ),
|
|
.A1(\FS[8] ), .D0(\ram2e_ufm/N_799 ), .C0(\ram2e_ufm/N_241_i ),
|
|
.B0(\FS[12] ), .A0(\FS[11] ), .F0(\ram2e_ufm/N_768 ),
|
|
.F1(\ram2e_ufm/N_241_i ));
|
|
ram2e_ufm_SLICE_115 \ram2e_ufm/SLICE_115 ( .B1(\S[2] ), .A1(\S[1] ),
|
|
.D0(nEN80_c), .C0(\S[3] ), .B0(\S[0] ), .A0(\ram2e_ufm/N_221 ),
|
|
.F0(\ram2e_ufm/CKE_7s2_0_0_0 ), .F1(\ram2e_ufm/N_221 ));
|
|
ram2e_ufm_SLICE_116 \ram2e_ufm/SLICE_116 ( .D1(\Din_c[3] ), .C1(\Din_c[5] ),
|
|
.B1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ), .A1(\ram2e_ufm/N_814 ),
|
|
.C0(\Din_c[2] ), .B0(\Din_c[1] ), .A0(\Din_c[0] ), .F0(\ram2e_ufm/N_814 ),
|
|
.F1(\ram2e_ufm/N_851 ));
|
|
ram2e_ufm_SLICE_117 \ram2e_ufm/SLICE_117 ( .D1(\S[1] ), .C1(\S[0] ),
|
|
.B1(\S[3] ), .A1(\S[2] ), .D0(\S[1] ), .C0(\S[2] ), .B0(\S[0] ),
|
|
.A0(\S[3] ), .F0(N_225_i), .F1(\ram2e_ufm/N_643 ));
|
|
ram2e_ufm_SLICE_118 \ram2e_ufm/SLICE_118 ( .D1(\S[1] ), .C1(\S[0] ),
|
|
.B1(\S[3] ), .A1(\S[2] ), .D0(\S[1] ), .C0(\S[2] ), .B0(\S[0] ),
|
|
.A0(\S[3] ), .F0(N_201_i), .F1(RC12));
|
|
ram2e_ufm_SLICE_119 \ram2e_ufm/SLICE_119 ( .D1(\S[2] ), .C1(\S[3] ),
|
|
.B1(\S[1] ), .A1(\S[0] ), .D0(\S[3] ), .C0(\S[2] ), .B0(\S[1] ),
|
|
.A0(\S[0] ), .F0(N_126), .F1(N_185_i));
|
|
ram2e_ufm_SLICE_120 \ram2e_ufm/SLICE_120 ( .D1(\S[3] ), .C1(\S[0] ),
|
|
.B1(\RWBank[0] ), .A1(\FS[15] ), .D0(\S[3] ), .C0(\S[0] ),
|
|
.B0(\RWBank[0] ), .A0(\FS[15] ), .F0(N_507_i), .F1(N_508));
|
|
ram2e_ufm_SLICE_121 \ram2e_ufm/SLICE_121 ( .D1(\S[3] ), .C1(\S[2] ),
|
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.B1(\S[1] ), .A1(\S[0] ), .D0(\S[3] ), .C0(\S[2] ), .B0(\S[1] ),
|
|
.A0(\S[0] ), .F0(\ram2e_ufm/N_242 ), .F1(Vout3));
|
|
ram2e_ufm_SLICE_122 \ram2e_ufm/SLICE_122 ( .D1(\FS[4] ), .C1(\FS[3] ),
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.B1(\FS[2] ), .A1(\FS[1] ), .D0(\FS[4] ), .C0(\FS[3] ), .B0(\FS[2] ),
|
|
.A0(\FS[1] ), .F0(\ram2e_ufm/N_254 ), .F1(\ram2e_ufm/nRWE_s_i_0_63_1 ));
|
|
ram2e_ufm_SLICE_123 \ram2e_ufm/SLICE_123 ( .C1(\FS[11] ), .B1(\FS[9] ),
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.A1(\FS[8] ), .D0(\FS[8] ), .C0(\FS[9] ), .B0(\FS[11] ), .A0(\FS[10] ),
|
|
.F0(\ram2e_ufm/N_849 ), .F1(\ram2e_ufm/N_204 ));
|
|
ram2e_ufm_SLICE_124 \ram2e_ufm/SLICE_124 ( .D1(\ram2e_ufm/N_784 ),
|
|
.C1(\FS[12] ), .B1(\FS[4] ), .A1(\FS[3] ), .D0(\FS[4] ),
|
|
.C0(\ram2e_ufm/N_784 ), .B0(\FS[1] ), .A0(\FS[3] ), .F0(\ram2e_ufm/N_684 ),
|
|
.F1(\ram2e_ufm/RA_35_0_0_0[5] ));
|
|
ram2e_ufm_SLICE_125 \ram2e_ufm/SLICE_125 ( .D1(\FS[13] ), .C1(\FS[11] ),
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|
.B1(\FS[9] ), .A1(\FS[8] ), .D0(\ram2e_ufm/N_793 ), .C0(\FS[11] ),
|
|
.B0(\FS[9] ), .A0(\FS[8] ), .F0(\ram2e_ufm/N_763 ), .F1(\ram2e_ufm/N_565 ));
|
|
ram2e_ufm_SLICE_126 \ram2e_ufm/SLICE_126 ( .D1(\FS[12] ), .C1(\FS[10] ),
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|
.B1(\FS[9] ), .A1(\FS[8] ), .D0(\ram2e_ufm/N_781 ), .C0(\FS[12] ),
|
|
.B0(\FS[10] ), .A0(\FS[9] ), .F0(\ram2e_ufm/N_753 ),
|
|
.F1(\ram2e_ufm/N_208 ));
|
|
ram2e_ufm_SLICE_127 \ram2e_ufm/SLICE_127 ( .D1(\S[3] ), .C1(\S[2] ),
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|
.B1(\S[1] ), .A1(\S[0] ), .D0(\S[3] ), .C0(\S[2] ), .B0(\S[0] ),
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|
.A0(\RWBank[7] ), .F0(\ram2e_ufm/N_698 ), .F1(un9_VOEEN_0_a2_0_a3_0_a3));
|
|
ram2e_ufm_SLICE_128 \ram2e_ufm/SLICE_128 ( .D1(\FS[13] ), .C1(\FS[12] ),
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|
.B1(\FS[11] ), .A1(\FS[10] ), .C0(\FS[13] ), .B0(\FS[12] ), .A0(\FS[10] ),
|
|
.F0(\ram2e_ufm/wb_adr_7_5_41_a3_3_0 ),
|
|
.F1(\ram2e_ufm/wb_dati_7_0_0_0_a3_0[0] ));
|
|
ram2e_ufm_SLICE_129 \ram2e_ufm/SLICE_129 ( .D1(\S[0] ), .C1(\RWBank[6] ),
|
|
.B1(\ram2e_ufm/N_560 ), .A1(\FS[4] ), .D0(N_551), .C0(\S[0] ),
|
|
.B0(\FS[1] ), .A0(\FS[4] ), .F0(\ram2e_ufm/N_627 ), .F1(\BA_4[1] ));
|
|
ram2e_ufm_SLICE_130 \ram2e_ufm/SLICE_130 ( .B1(\ram2e_ufm/N_185 ),
|
|
.A1(RWSel), .D0(\ram2e_ufm/N_185 ), .C0(RWSel), .B0(\ram2e_ufm/N_777 ),
|
|
.A0(\ram2e_ufm/CmdExecMXO2 ), .F0(\ram2e_ufm/wb_we_RNO_0 ), .F1(N_187_i));
|
|
ram2e_ufm_SLICE_131 \ram2e_ufm/SLICE_131 ( .D1(\FS[13] ), .C1(\FS[12] ),
|
|
.B1(\FS[3] ), .A1(\FS[1] ), .D0(\ram2e_ufm/N_856 ), .C0(\ram2e_ufm/N_811 ),
|
|
.B0(\FS[13] ), .A0(\FS[12] ), .F0(\ram2e_ufm/N_602 ),
|
|
.F1(\ram2e_ufm/Ready3_0_a3_5 ));
|
|
ram2e_ufm_SLICE_132 \ram2e_ufm/SLICE_132 ( .D1(\RA[0] ),
|
|
.C1(\ram2e_ufm/N_186 ), .B1(\ram2e_ufm/N_182 ), .A1(\Ain_c[0] ),
|
|
.D0(\RA[7] ), .C0(\ram2e_ufm/N_186 ), .B0(\ram2e_ufm/N_182 ),
|
|
.A0(\Ain_c[7] ), .F0(\ram2e_ufm/RA_35_0_0_0_0[7] ),
|
|
.F1(\ram2e_ufm/RA_35_0_0_1[0] ));
|
|
ram2e_ufm_SLICE_133 \ram2e_ufm/SLICE_133 ( .D1(RWSel), .C1(\Din_c[4] ),
|
|
.B1(\Din_c[2] ), .A1(\Din_c[0] ), .C0(\ram2e_ufm/N_338 ), .B0(\Din_c[4] ),
|
|
.A0(\Din_c[2] ), .F0(\ram2e_ufm/N_350 ),
|
|
.F1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_0_1 ));
|
|
ram2e_ufm_SLICE_134 \ram2e_ufm/SLICE_134 ( .D1(\FS[6] ), .C1(\FS[3] ),
|
|
.B1(\FS[2] ), .A1(\FS[1] ), .D0(\ram2e_ufm/N_792 ), .C0(\FS[9] ),
|
|
.B0(\FS[6] ), .A0(\FS[3] ), .F0(\ram2e_ufm/N_679 ),
|
|
.F1(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3[0] ));
|
|
ram2e_ufm_SLICE_135 \ram2e_ufm/SLICE_135 ( .B1(\S[3] ), .A1(\S[2] ),
|
|
.D0(nEN80_c), .C0(\S[3] ), .B0(\S[2] ), .A0(\ram2e_ufm/S_r_i_0_o2[1] ),
|
|
.F0(\ram2e_ufm/N_625 ), .F1(\ram2e_ufm/N_271 ));
|
|
ram2e_ufm_SLICE_136 \ram2e_ufm/SLICE_136 ( .C1(nWE_c), .B1(nEN80_c),
|
|
.A1(\S[3] ), .C0(nWE_c), .B0(nEN80_c), .A0(DOEEN), .F0(nDOE_c),
|
|
.F1(\ram2e_ufm/N_226 ));
|
|
ram2e_ufm_SLICE_137 \ram2e_ufm/SLICE_137 ( .C1(nWE_c), .B1(nEN80_c),
|
|
.A1(Ready), .C0(nEN80_c), .B0(Ready), .A0(\ram2e_ufm/LEDEN ), .F0(LED_c),
|
|
.F1(RDOE_i));
|
|
SLICE_138 SLICE_138( .C1(\S[0] ), .B1(\S[1] ), .A1(\S[3] ), .C0(\S[0] ),
|
|
.B0(\S[1] ), .A0(\S[2] ), .F0(N_1080_0), .F1(N_1078_0));
|
|
SLICE_139 SLICE_139( .B1(VOEEN), .A1(PHI1_c), .C0(Ready), .B0(PHI1r),
|
|
.A0(PHI1_c), .F0(S_1), .F1(nVOE_c));
|
|
ram2e_ufm_SLICE_140 \ram2e_ufm/SLICE_140 ( .B1(\RA[2] ),
|
|
.A1(\ram2e_ufm/N_186 ), .B0(\RA[5] ), .A0(\ram2e_ufm/N_186 ),
|
|
.F0(\ram2e_ufm/N_621 ), .F1(\ram2e_ufm/N_680 ));
|
|
ram2e_ufm_SLICE_141 \ram2e_ufm/SLICE_141 ( .B1(Ready), .A1(\Din_c[0] ),
|
|
.B0(Ready), .A0(\Din_c[3] ), .F0(N_263_i), .F1(N_667));
|
|
ram2e_ufm_SLICE_142 \ram2e_ufm/SLICE_142 ( .C1(\Din_c[4] ), .B1(\Din_c[7] ),
|
|
.A1(\Din_c[0] ), .B0(Ready), .A0(\Din_c[4] ), .F0(N_648),
|
|
.F1(\ram2e_ufm/CmdLEDGet_3_0_a3_1 ));
|
|
ram2e_ufm_SLICE_143 \ram2e_ufm/SLICE_143 ( .B1(Ready), .A1(\Din_c[1] ),
|
|
.B0(Ready), .A0(\Din_c[7] ), .F0(N_662), .F1(N_666));
|
|
ram2e_ufm_SLICE_144 \ram2e_ufm/SLICE_144 ( .B1(Ready), .A1(\Din_c[2] ),
|
|
.B0(Ready), .A0(\Din_c[6] ), .F0(N_663), .F1(N_665));
|
|
ram2e_ufm_SLICE_145 \ram2e_ufm/SLICE_145 ( .D1(\ram2e_ufm/wb_adr[4] ),
|
|
.C1(\S[2] ), .B1(\ram2e_ufm/N_873 ), .A1(\ram2e_ufm/N_783 ), .B0(\FS[9] ),
|
|
.A0(\FS[8] ), .F0(\ram2e_ufm/N_206 ), .F1(\ram2e_ufm/wb_dati_7_0_0_0[4] ));
|
|
ram2e_ufm_SLICE_146 \ram2e_ufm/SLICE_146 ( .D1(\RWBank[2] ),
|
|
.C1(\ram2e_ufm/N_845 ), .B1(\ram2e_ufm/N_784 ), .A1(\FS[4] ), .D0(\FS[7] ),
|
|
.C0(\FS[6] ), .B0(\FS[5] ), .A0(\FS[0] ), .F0(\ram2e_ufm/Ready3_0_a3_3 ),
|
|
.F1(\ram2e_ufm/RA_35_0_0_0[9] ));
|
|
ram2e_ufm_SLICE_147 \ram2e_ufm/SLICE_147 ( .D1(\ram2e_ufm/LEDEN ),
|
|
.C1(CmdSetRWBankFFLED), .B1(\ram2e_ufm/CmdSetRWBankFFChip ),
|
|
.A1(CmdLEDGet), .B0(Ready), .A0(\Din_c[5] ), .F0(N_664),
|
|
.F1(\ram2e_ufm/N_188 ));
|
|
RD_0_ \RD[0]_I ( .PADDI(\RD_in[0] ), .PADDT(RDOE_i), .PADDO(N_667),
|
|
.RD0(RD[0]));
|
|
LED LED_I( .PADDO(LED_c), .LED(LED));
|
|
C14M C14M_I( .PADDI(C14M_c), .C14M(C14M));
|
|
RD_7_ \RD[7]_I ( .PADDI(\RD_in[7] ), .PADDT(RDOE_i), .PADDO(N_662),
|
|
.RD7(RD[7]));
|
|
RD_6_ \RD[6]_I ( .PADDI(\RD_in[6] ), .PADDT(RDOE_i), .PADDO(N_663),
|
|
.RD6(RD[6]));
|
|
RD_5_ \RD[5]_I ( .PADDI(\RD_in[5] ), .PADDT(RDOE_i), .PADDO(N_664),
|
|
.RD5(RD[5]));
|
|
RD_4_ \RD[4]_I ( .PADDI(\RD_in[4] ), .PADDT(RDOE_i), .PADDO(N_648),
|
|
.RD4(RD[4]));
|
|
RD_3_ \RD[3]_I ( .PADDI(\RD_in[3] ), .PADDT(RDOE_i), .PADDO(N_263_i),
|
|
.RD3(RD[3]));
|
|
RD_2_ \RD[2]_I ( .PADDI(\RD_in[2] ), .PADDT(RDOE_i), .PADDO(N_665),
|
|
.RD2(RD[2]));
|
|
RD_1_ \RD[1]_I ( .PADDI(\RD_in[1] ), .PADDT(RDOE_i), .PADDO(N_666),
|
|
.RD1(RD[1]));
|
|
DQMH DQMH_I( .IOLDO(DQMH_c), .DQMH(DQMH));
|
|
DQMH_MGIOL DQMH_MGIOL( .IOLDO(DQMH_c), .OPOS(N_508), .CE(N_201_i),
|
|
.CLK(C14M_c));
|
|
DQML DQML_I( .IOLDO(DQML_c), .DQML(DQML));
|
|
DQML_MGIOL DQML_MGIOL( .IOLDO(DQML_c), .OPOS(N_507_i), .CE(N_201_i),
|
|
.CLK(C14M_c));
|
|
RAout_11_ \RAout[11]_I ( .IOLDO(\RAout_c[11] ), .RAout11(RAout[11]));
|
|
RAout_11__MGIOL \RAout[11]_MGIOL ( .IOLDO(\RAout_c[11] ), .OPOS(\RA[11] ),
|
|
.CLK(C14M_c));
|
|
RAout_10_ \RAout[10]_I ( .IOLDO(\RAout_c[10] ), .RAout10(RAout[10]));
|
|
RAout_10__MGIOL \RAout[10]_MGIOL ( .IOLDO(\RAout_c[10] ), .OPOS(\RA[10] ),
|
|
.CLK(C14M_c));
|
|
RAout_9_ \RAout[9]_I ( .IOLDO(\RAout_c[9] ), .RAout9(RAout[9]));
|
|
RAout_9__MGIOL \RAout[9]_MGIOL ( .IOLDO(\RAout_c[9] ), .OPOS(\RA[9] ),
|
|
.CLK(C14M_c));
|
|
RAout_8_ \RAout[8]_I ( .IOLDO(\RAout_c[8] ), .RAout8(RAout[8]));
|
|
RAout_8__MGIOL \RAout[8]_MGIOL ( .IOLDO(\RAout_c[8] ), .OPOS(\RA[8] ),
|
|
.CLK(C14M_c));
|
|
RAout_7_ \RAout[7]_I ( .IOLDO(\RAout_c[7] ), .RAout7(RAout[7]));
|
|
RAout_7__MGIOL \RAout[7]_MGIOL ( .IOLDO(\RAout_c[7] ), .OPOS(\RA[7] ),
|
|
.CLK(C14M_c));
|
|
RAout_6_ \RAout[6]_I ( .IOLDO(\RAout_c[6] ), .RAout6(RAout[6]));
|
|
RAout_6__MGIOL \RAout[6]_MGIOL ( .IOLDO(\RAout_c[6] ), .OPOS(\RA[6] ),
|
|
.CLK(C14M_c));
|
|
RAout_5_ \RAout[5]_I ( .IOLDO(\RAout_c[5] ), .RAout5(RAout[5]));
|
|
RAout_5__MGIOL \RAout[5]_MGIOL ( .IOLDO(\RAout_c[5] ), .OPOS(\RA[5] ),
|
|
.CLK(C14M_c));
|
|
RAout_4_ \RAout[4]_I ( .IOLDO(\RAout_c[4] ), .RAout4(RAout[4]));
|
|
RAout_4__MGIOL \RAout[4]_MGIOL ( .IOLDO(\RAout_c[4] ), .OPOS(\RA[4] ),
|
|
.CLK(C14M_c));
|
|
RAout_3_ \RAout[3]_I ( .IOLDO(\RAout_c[3] ), .RAout3(RAout[3]));
|
|
RAout_3__MGIOL \RAout[3]_MGIOL ( .IOLDO(\RAout_c[3] ), .OPOS(\RA[3] ),
|
|
.CLK(C14M_c));
|
|
RAout_2_ \RAout[2]_I ( .IOLDO(\RAout_c[2] ), .RAout2(RAout[2]));
|
|
RAout_2__MGIOL \RAout[2]_MGIOL ( .IOLDO(\RAout_c[2] ), .OPOS(\RA[2] ),
|
|
.CLK(C14M_c));
|
|
RAout_1_ \RAout[1]_I ( .IOLDO(\RAout_c[1] ), .RAout1(RAout[1]));
|
|
RAout_1__MGIOL \RAout[1]_MGIOL ( .IOLDO(\RAout_c[1] ), .OPOS(\RA[1] ),
|
|
.CLK(C14M_c));
|
|
RAout_0_ \RAout[0]_I ( .IOLDO(\RAout_c[0] ), .RAout0(RAout[0]));
|
|
RAout_0__MGIOL \RAout[0]_MGIOL ( .IOLDO(\RAout_c[0] ), .OPOS(\RA[0] ),
|
|
.CLK(C14M_c));
|
|
BA_1_ \BA[1]_I ( .IOLDO(\BA_c[1] ), .BA1(BA[1]));
|
|
BA_1__MGIOL \BA[1]_MGIOL ( .IOLDO(\BA_c[1] ), .OPOS(\BA_4[1] ), .CE(N_225_i),
|
|
.LSR(BA_0_sqmuxa), .CLK(C14M_c));
|
|
BA_0_ \BA[0]_I ( .IOLDO(\BA_c[0] ), .BA0(BA[0]));
|
|
BA_0__MGIOL \BA[0]_MGIOL ( .IOLDO(\BA_c[0] ), .OPOS(\BA_4[0] ), .CE(N_225_i),
|
|
.LSR(BA_0_sqmuxa), .CLK(C14M_c));
|
|
nRWEout nRWEout_I( .IOLDO(nRWEout_c), .nRWEout(nRWEout));
|
|
nRWEout_MGIOL nRWEout_MGIOL( .IOLDO(nRWEout_c), .OPOS(nRWE), .CLK(C14M_c));
|
|
nCASout nCASout_I( .IOLDO(nCASout_c), .nCASout(nCASout));
|
|
nCASout_MGIOL nCASout_MGIOL( .IOLDO(nCASout_c), .OPOS(nCAS), .CLK(C14M_c));
|
|
nRASout nRASout_I( .IOLDO(nRASout_c), .nRASout(nRASout));
|
|
nRASout_MGIOL nRASout_MGIOL( .IOLDO(nRASout_c), .OPOS(nRAS), .CLK(C14M_c));
|
|
nCSout nCSout_I( .PADDO(GND), .nCSout(nCSout));
|
|
CKEout CKEout_I( .IOLDO(CKEout_c), .CKEout(CKEout));
|
|
CKEout_MGIOL CKEout_MGIOL( .IOLDO(CKEout_c), .OPOS(CKE), .CLK(C14M_c));
|
|
nVOE nVOE_I( .PADDO(nVOE_c), .nVOE(nVOE));
|
|
Vout_7_ \Vout[7]_I ( .IOLDO(\Vout_c[7] ), .Vout7(Vout[7]));
|
|
Vout_7__MGIOL \Vout[7]_MGIOL ( .IOLDO(\Vout_c[7] ), .OPOS(\RD_in[7] ),
|
|
.CE(Vout3), .CLK(C14M_c));
|
|
Vout_6_ \Vout[6]_I ( .IOLDO(\Vout_c[6] ), .Vout6(Vout[6]));
|
|
Vout_6__MGIOL \Vout[6]_MGIOL ( .IOLDO(\Vout_c[6] ), .OPOS(\RD_in[6] ),
|
|
.CE(Vout3), .CLK(C14M_c));
|
|
Vout_5_ \Vout[5]_I ( .IOLDO(\Vout_c[5] ), .Vout5(Vout[5]));
|
|
Vout_5__MGIOL \Vout[5]_MGIOL ( .IOLDO(\Vout_c[5] ), .OPOS(\RD_in[5] ),
|
|
.CE(Vout3), .CLK(C14M_c));
|
|
Vout_4_ \Vout[4]_I ( .IOLDO(\Vout_c[4] ), .Vout4(Vout[4]));
|
|
Vout_4__MGIOL \Vout[4]_MGIOL ( .IOLDO(\Vout_c[4] ), .OPOS(\RD_in[4] ),
|
|
.CE(Vout3), .CLK(C14M_c));
|
|
Vout_3_ \Vout[3]_I ( .IOLDO(\Vout_c[3] ), .Vout3(Vout[3]));
|
|
Vout_3__MGIOL \Vout[3]_MGIOL ( .IOLDO(\Vout_c[3] ), .OPOS(\RD_in[3] ),
|
|
.CE(Vout3), .CLK(C14M_c));
|
|
Vout_2_ \Vout[2]_I ( .IOLDO(\Vout_c[2] ), .Vout2(Vout[2]));
|
|
Vout_2__MGIOL \Vout[2]_MGIOL ( .IOLDO(\Vout_c[2] ), .OPOS(\RD_in[2] ),
|
|
.CE(Vout3), .CLK(C14M_c));
|
|
Vout_1_ \Vout[1]_I ( .IOLDO(\Vout_c[1] ), .Vout1(Vout[1]));
|
|
Vout_1__MGIOL \Vout[1]_MGIOL ( .IOLDO(\Vout_c[1] ), .OPOS(\RD_in[1] ),
|
|
.CE(Vout3), .CLK(C14M_c));
|
|
Vout_0_ \Vout[0]_I ( .IOLDO(\Vout_c[0] ), .Vout0(Vout[0]));
|
|
Vout_0__MGIOL \Vout[0]_MGIOL ( .IOLDO(\Vout_c[0] ), .OPOS(\RD_in[0] ),
|
|
.CE(Vout3), .CLK(C14M_c));
|
|
nDOE nDOE_I( .PADDO(nDOE_c), .nDOE(nDOE));
|
|
Dout_7_ \Dout[7]_I ( .PADDO(\RD_in[7] ), .Dout7(Dout[7]));
|
|
Dout_6_ \Dout[6]_I ( .PADDO(\RD_in[6] ), .Dout6(Dout[6]));
|
|
Dout_5_ \Dout[5]_I ( .PADDO(\RD_in[5] ), .Dout5(Dout[5]));
|
|
Dout_4_ \Dout[4]_I ( .PADDO(\RD_in[4] ), .Dout4(Dout[4]));
|
|
Dout_3_ \Dout[3]_I ( .PADDO(\RD_in[3] ), .Dout3(Dout[3]));
|
|
Dout_2_ \Dout[2]_I ( .PADDO(\RD_in[2] ), .Dout2(Dout[2]));
|
|
Dout_1_ \Dout[1]_I ( .PADDO(\RD_in[1] ), .Dout1(Dout[1]));
|
|
Dout_0_ \Dout[0]_I ( .PADDO(\RD_in[0] ), .Dout0(Dout[0]));
|
|
Din_7_ \Din[7]_I ( .PADDI(\Din_c[7] ), .Din7(Din[7]));
|
|
Din_6_ \Din[6]_I ( .PADDI(\Din_c[6] ), .Din6(Din[6]));
|
|
Din_5_ \Din[5]_I ( .PADDI(\Din_c[5] ), .Din5(Din[5]));
|
|
Din_4_ \Din[4]_I ( .PADDI(\Din_c[4] ), .Din4(Din[4]));
|
|
Din_3_ \Din[3]_I ( .PADDI(\Din_c[3] ), .Din3(Din[3]));
|
|
Din_2_ \Din[2]_I ( .PADDI(\Din_c[2] ), .Din2(Din[2]));
|
|
Din_1_ \Din[1]_I ( .PADDI(\Din_c[1] ), .Din1(Din[1]));
|
|
Din_0_ \Din[0]_I ( .PADDI(\Din_c[0] ), .Din0(Din[0]));
|
|
Ain_7_ \Ain[7]_I ( .PADDI(\Ain_c[7] ), .Ain7(Ain[7]));
|
|
Ain_6_ \Ain[6]_I ( .PADDI(\Ain_c[6] ), .Ain6(Ain[6]));
|
|
Ain_5_ \Ain[5]_I ( .PADDI(\Ain_c[5] ), .Ain5(Ain[5]));
|
|
Ain_4_ \Ain[4]_I ( .PADDI(\Ain_c[4] ), .Ain4(Ain[4]));
|
|
Ain_3_ \Ain[3]_I ( .PADDI(\Ain_c[3] ), .Ain3(Ain[3]));
|
|
Ain_2_ \Ain[2]_I ( .PADDI(\Ain_c[2] ), .Ain2(Ain[2]));
|
|
Ain_1_ \Ain[1]_I ( .PADDI(\Ain_c[1] ), .Ain1(Ain[1]));
|
|
Ain_0_ \Ain[0]_I ( .PADDI(\Ain_c[0] ), .Ain0(Ain[0]));
|
|
nC07X nC07X_I( .PADDI(nC07X_c), .nC07X(nC07X));
|
|
nEN80 nEN80_I( .PADDI(nEN80_c), .nEN80(nEN80));
|
|
nWE nWE_I( .PADDI(nWE_c), .nWE(nWE));
|
|
PHI1 PHI1_I( .PADDI(PHI1_c), .PHI1(PHI1));
|
|
PHI1_MGIOL PHI1_MGIOL( .DI(PHI1_c), .CLK(C14M_c), .IN(PHI1r));
|
|
ram2e_ufm_ufmefb_EFBInst_0 \ram2e_ufm/ufmefb/EFBInst_0 ( .WBCLKI(C14M_c),
|
|
.WBRSTI(\ram2e_ufm/wb_rst ), .WBCYCI(\ram2e_ufm/wb_cyc_stb ),
|
|
.WBSTBI(\ram2e_ufm/wb_cyc_stb ), .WBWEI(\ram2e_ufm/wb_we ),
|
|
.WBADRI0(\ram2e_ufm/wb_adr[0] ), .WBADRI1(\ram2e_ufm/wb_adr[1] ),
|
|
.WBADRI2(\ram2e_ufm/wb_adr[2] ), .WBADRI3(\ram2e_ufm/wb_adr[3] ),
|
|
.WBADRI4(\ram2e_ufm/wb_adr[4] ), .WBADRI5(\ram2e_ufm/wb_adr[5] ),
|
|
.WBADRI6(\ram2e_ufm/wb_adr[6] ), .WBADRI7(\ram2e_ufm/wb_adr[7] ),
|
|
.WBDATI0(\ram2e_ufm/wb_dati[0] ), .WBDATI1(\ram2e_ufm/wb_dati[1] ),
|
|
.WBDATI2(\ram2e_ufm/wb_dati[2] ), .WBDATI3(\ram2e_ufm/wb_dati[3] ),
|
|
.WBDATI4(\ram2e_ufm/wb_dati[4] ), .WBDATI5(\ram2e_ufm/wb_dati[5] ),
|
|
.WBDATI6(\ram2e_ufm/wb_dati[6] ), .WBDATI7(\ram2e_ufm/wb_dati[7] ),
|
|
.WBDATO0(\ram2e_ufm/wb_dato[0] ), .WBDATO1(\ram2e_ufm/wb_dato[1] ),
|
|
.WBDATO2(\ram2e_ufm/wb_dato[2] ), .WBDATO3(\ram2e_ufm/wb_dato[3] ),
|
|
.WBDATO4(\ram2e_ufm/wb_dato[4] ), .WBDATO5(\ram2e_ufm/wb_dato[5] ),
|
|
.WBDATO6(\ram2e_ufm/wb_dato[6] ), .WBDATO7(\ram2e_ufm/wb_dato[7] ),
|
|
.WBACKO(\ram2e_ufm/wb_ack ));
|
|
VHI VHI_INST( .Z(VCCI));
|
|
PUR PUR_INST( .PUR(VCCI));
|
|
GSR GSR_INST( .GSR(VCCI));
|
|
endmodule
|
|
|
|
module SLICE_0 ( input A1, DI1, CLK, output F1, Q1, FCO );
|
|
wire VCCI, GNDI, DI1_dly, CLK_dly;
|
|
|
|
vmuxregsre \FS[0] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
ccu2 \FS_cry_0[0] ( .A0(GNDI), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1),
|
|
.B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(GNDI), .S0(), .S1(F1), .CO1(FCO));
|
|
|
|
specify
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => FCO) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module vmuxregsre ( input D0, D1, SD, SP, CK, LSR, output Q );
|
|
|
|
FL1P3DX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q));
|
|
defparam INST01.GSR = "DISABLED";
|
|
endmodule
|
|
|
|
module vcc ( output PWR1 );
|
|
|
|
VHI INST1( .Z(PWR1));
|
|
endmodule
|
|
|
|
module gnd ( output PWR0 );
|
|
|
|
VLO INST1( .Z(PWR0));
|
|
endmodule
|
|
|
|
module ccu2 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 );
|
|
|
|
CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1),
|
|
.C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1));
|
|
defparam inst1.INIT0 = 16'h000A;
|
|
defparam inst1.INIT1 = 16'h300A;
|
|
defparam inst1.INJECT1_0 = "NO";
|
|
defparam inst1.INJECT1_1 = "NO";
|
|
endmodule
|
|
|
|
module SLICE_1 ( input A0, DI0, CLK, FCI, output F0, Q0 );
|
|
wire VCCI, GNDI, DI0_dly, CLK_dly;
|
|
|
|
vmuxregsre \FS[15] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
ccu20001 \FS_s_0[15] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(GNDI),
|
|
.B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(), .CO1());
|
|
|
|
specify
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(FCI => F0) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module ccu20001 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 );
|
|
|
|
CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1),
|
|
.C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1));
|
|
defparam inst1.INIT0 = 16'h5002;
|
|
defparam inst1.INIT1 = 16'h300A;
|
|
defparam inst1.INJECT1_0 = "NO";
|
|
defparam inst1.INJECT1_1 = "NO";
|
|
endmodule
|
|
|
|
module SLICE_2 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
|
|
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
|
|
|
|
vmuxregsre \FS[14] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
vmuxregsre \FS[13] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
ccu20002 \FS_cry_0[13] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1),
|
|
.B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));
|
|
|
|
specify
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => FCO) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F1) = (0:0:0,0:0:0);
|
|
(A0 => FCO) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
(FCI => F0) = (0:0:0,0:0:0);
|
|
(FCI => F1) = (0:0:0,0:0:0);
|
|
(FCI => FCO) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module ccu20002 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 );
|
|
|
|
CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1),
|
|
.C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1));
|
|
defparam inst1.INIT0 = 16'h300A;
|
|
defparam inst1.INIT1 = 16'h300A;
|
|
defparam inst1.INJECT1_0 = "NO";
|
|
defparam inst1.INJECT1_1 = "NO";
|
|
endmodule
|
|
|
|
module SLICE_3 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
|
|
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
|
|
|
|
vmuxregsre \FS[12] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
vmuxregsre \FS[11] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
ccu20002 \FS_cry_0[11] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1),
|
|
.B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));
|
|
|
|
specify
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => FCO) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F1) = (0:0:0,0:0:0);
|
|
(A0 => FCO) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
(FCI => F0) = (0:0:0,0:0:0);
|
|
(FCI => F1) = (0:0:0,0:0:0);
|
|
(FCI => FCO) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module SLICE_4 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
|
|
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
|
|
|
|
vmuxregsre \FS[10] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
vmuxregsre \FS[9] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
ccu20002 \FS_cry_0[9] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1),
|
|
.B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));
|
|
|
|
specify
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => FCO) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F1) = (0:0:0,0:0:0);
|
|
(A0 => FCO) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
(FCI => F0) = (0:0:0,0:0:0);
|
|
(FCI => F1) = (0:0:0,0:0:0);
|
|
(FCI => FCO) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module SLICE_5 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
|
|
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
|
|
|
|
vmuxregsre \FS[8] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
vmuxregsre \FS[7] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
ccu20002 \FS_cry_0[7] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1),
|
|
.B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));
|
|
|
|
specify
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => FCO) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F1) = (0:0:0,0:0:0);
|
|
(A0 => FCO) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
(FCI => F0) = (0:0:0,0:0:0);
|
|
(FCI => F1) = (0:0:0,0:0:0);
|
|
(FCI => FCO) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module SLICE_6 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
|
|
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
|
|
|
|
vmuxregsre \FS[6] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
vmuxregsre \FS[5] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
ccu20002 \FS_cry_0[5] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1),
|
|
.B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));
|
|
|
|
specify
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => FCO) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F1) = (0:0:0,0:0:0);
|
|
(A0 => FCO) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
(FCI => F0) = (0:0:0,0:0:0);
|
|
(FCI => F1) = (0:0:0,0:0:0);
|
|
(FCI => FCO) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module SLICE_7 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
|
|
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
|
|
|
|
vmuxregsre \FS[4] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
vmuxregsre \FS[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
ccu20002 \FS_cry_0[3] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1),
|
|
.B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));
|
|
|
|
specify
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => FCO) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F1) = (0:0:0,0:0:0);
|
|
(A0 => FCO) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
(FCI => F0) = (0:0:0,0:0:0);
|
|
(FCI => F1) = (0:0:0,0:0:0);
|
|
(FCI => FCO) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module SLICE_8 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO );
|
|
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
|
|
|
|
vmuxregsre \FS[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
vmuxregsre \FS[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
ccu20002 \FS_cry_0[1] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1),
|
|
.B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO));
|
|
|
|
specify
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => FCO) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F1) = (0:0:0,0:0:0);
|
|
(A0 => FCO) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
(FCI => F0) = (0:0:0,0:0:0);
|
|
(FCI => F1) = (0:0:0,0:0:0);
|
|
(FCI => FCO) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module SLICE_9 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0,
|
|
F1 );
|
|
wire VCCI, GNDI, DI0_dly, CLK_dly;
|
|
|
|
lut4 \ram2e_ufm/wb_req_RNO_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40003 \ram2e_ufm/CKE_7_RNIS77M1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
vmuxregsre0004 CKE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut4 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40003 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hAAAB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module vmuxregsre0004 ( input D0, D1, SD, SP, CK, LSR, output Q );
|
|
|
|
FL1P3BX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q));
|
|
defparam INST01.GSR = "DISABLED";
|
|
endmodule
|
|
|
|
module SLICE_10 ( input B0, A0, DI0, CE, CLK, output F0, Q0, F1 );
|
|
wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
|
|
|
|
lut40005 GND( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40006 \ram2e_ufm/CmdTout_3_0_a3_0_a3[0] ( .A(A0), .B(B0), .C(GNDI),
|
|
.D(GNDI), .Z(F0));
|
|
vmuxregsre \CmdTout[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
|
|
specify
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40005 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h0000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40006 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_11 ( input B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 );
|
|
wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
|
|
|
|
lut40006 \ram2e_ufm/RC_3_0_0_a3_1[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI),
|
|
.Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40007 \ram2e_ufm/N_360_i ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
|
|
vmuxregsre \RC[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
|
|
specify
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40007 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h1515) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_12 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, LSR, CLK,
|
|
output F0, Q0, F1, Q1 );
|
|
wire VCCI, DI1_dly, CLK_dly, DI0_dly, LSR_dly;
|
|
|
|
lut40008 \ram2e_ufm/CmdExecMXO2_3_0_a3_0_RNI6S1P8 ( .A(A1), .B(B1), .C(C1),
|
|
.D(D1), .Z(F1));
|
|
lut40009 \ram2e_ufm/S_r_i_0_o2_RNIVM0LF[1] ( .A(A0), .B(B0), .C(C0), .D(D0),
|
|
.Z(F0));
|
|
vmuxregsre0010 \CS[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(LSR_dly), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
vmuxregsre0010 \CS[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
|
|
$width (posedge LSR, 0:0:0);
|
|
$width (negedge LSR, 0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40008 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hFF54) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40009 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h00F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module vmuxregsre0010 ( input D0, D1, SD, SP, CK, LSR, output Q );
|
|
|
|
FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q));
|
|
defparam INST01.GSR = "DISABLED";
|
|
endmodule
|
|
|
|
module SLICE_13 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output
|
|
F0, Q0, F1 );
|
|
wire VCCI, DI0_dly, CLK_dly, LSR_dly;
|
|
|
|
lut40011 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514_0 ( .A(A1),
|
|
.B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40012 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514 ( .A(A0), .B(B0),
|
|
.C(C0), .D(D0), .Z(F0));
|
|
vmuxregsre0010 \CS[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
|
|
$width (posedge LSR, 0:0:0);
|
|
$width (negedge LSR, 0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40011 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hA2A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40012 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hC4C6) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_14 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0,
|
|
Q0, F1 );
|
|
wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
|
|
|
|
lut40013 \ram2e_ufm/CmdLEDGet_3_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(GNDI),
|
|
.Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40014 \ram2e_ufm/CmdLEDGet_3_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0),
|
|
.Z(F0));
|
|
vmuxregsre CmdLEDGet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40013 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40014 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_15 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0,
|
|
Q0, F1 );
|
|
wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
|
|
|
|
lut40013 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_5_1 ( .A(A1), .B(B1), .C(C1),
|
|
.D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40015 \ram2e_ufm/CmdLEDSet_3_0_a8_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0),
|
|
.Z(F0));
|
|
vmuxregsre CmdLEDSet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40015 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_16 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output
|
|
F0, Q0, F1 );
|
|
wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;
|
|
|
|
lut40016 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_9 ( .A(A1), .B(B1), .C(C1),
|
|
.D(D1), .Z(F1));
|
|
lut40017 \ram2e_ufm/CmdRWMaskSet_3_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0),
|
|
.Z(F0));
|
|
vmuxregsre CmdRWMaskSet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40016 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40017 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_17 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0,
|
|
Q0, F1 );
|
|
wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
|
|
|
|
lut40018 \ram2e_ufm/CmdRWMaskSet_3_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(GNDI),
|
|
.Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40019 \ram2e_ufm/CmdSetRWBankFFLED_4_0_a8_0_a3 ( .A(A0), .B(B0), .C(C0),
|
|
.D(D0), .Z(F0));
|
|
vmuxregsre CmdSetRWBankFFLED( .D0(VCCI), .D1(DI0_dly), .SD(VCCI),
|
|
.SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40018 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h1010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40019 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_18 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output
|
|
F0, Q0, F1, Q1 );
|
|
wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
|
|
|
|
lut40020 \ram2e_ufm/N_369_i ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40021 \ram2e_ufm/N_368_i ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
vmuxregsre \CmdTout[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
vmuxregsre \CmdTout[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40020 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h0078) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40021 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h0606) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_19 ( input B1, A1, B0, A0, M0, LSR, CLK, output F0, Q0, F1 );
|
|
wire GNDI, VCCI, M0_dly, CLK_dly, LSR_dly;
|
|
|
|
lut40022 \ram2e_ufm/SUM0_i_o2 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40023 \ram2e_ufm/RA_35_i_i_0_a3_0[1] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI),
|
|
.Z(F0));
|
|
vmuxregsre0010 DOEEN( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
|
|
specify
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly);
|
|
$setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
|
|
$width (posedge LSR, 0:0:0);
|
|
$width (negedge LSR, 0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40022 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40023 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_20 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK,
|
|
output F0, Q0, F1, Q1 );
|
|
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
|
|
|
|
lut40024 \ram2e_ufm/RA_35_i_i_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40025 \ram2e_ufm/RA_35_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
vmuxregsre \RA[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
vmuxregsre \RA[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40024 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40025 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hECFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_21 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output
|
|
F0, Q0, F1, Q1 );
|
|
wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
|
|
|
|
lut40026 \ram2e_ufm/RA_35_0_0[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40024 \ram2e_ufm/RA_35_0_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
vmuxregsre \RA[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
vmuxregsre \RA[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40026 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hF8F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_22 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output
|
|
F0, Q0, F1, Q1 );
|
|
wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
|
|
|
|
lut40024 \ram2e_ufm/RA_35_0_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40026 \ram2e_ufm/RA_35_0_0[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
vmuxregsre \RA[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
vmuxregsre \RA[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module SLICE_23 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0,
|
|
Q0, F1, Q1 );
|
|
wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
|
|
|
|
lut40026 \ram2e_ufm/RA_35_0_0_0[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI),
|
|
.Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40026 \ram2e_ufm/RA_35_0_0_0[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI),
|
|
.Z(F0));
|
|
vmuxregsre \RA[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
vmuxregsre \RA[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module SLICE_24 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output
|
|
F0, Q0, F1, Q1 );
|
|
wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
|
|
|
|
lut40026 \ram2e_ufm/RA_35_0_0[9] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40027 \ram2e_ufm/un2_S_2_i_0_0_o3_RNIHFHN3 ( .A(A0), .B(B0), .C(C0),
|
|
.D(D0), .Z(F0));
|
|
vmuxregsre \RA[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
vmuxregsre \RA[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40027 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hFEFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_25 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK,
|
|
output F0, Q0, F1, Q1 );
|
|
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
|
|
|
|
lut40028 \ram2e_ufm/RA_35_0_0[11] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut4 \ram2e_ufm/RA_35_2_0[10] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
vmuxregsre \RA[11] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
vmuxregsre \RA[10] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40028 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_26 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0,
|
|
Q0, F1, Q1 );
|
|
wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
|
|
|
|
lut40029 \ram2e_ufm/RC_3_0_0[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40030 \ram2e_ufm/RC_3_0_0[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
|
|
vmuxregsre \RC[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
vmuxregsre \RC[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40029 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h3838) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40030 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h4646) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_27 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0,
|
|
Q0, F1, Q1 );
|
|
wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
|
|
|
|
lut40031 \ram2e_ufm/RWBank_3_0[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40031 \ram2e_ufm/RWBank_3_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI),
|
|
.Z(F0));
|
|
vmuxregsre \RWBank[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
vmuxregsre \RWBank[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40031 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hCECE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_28 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0,
|
|
Q0, F1, Q1 );
|
|
wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
|
|
|
|
lut40031 \ram2e_ufm/RWBank_3_0[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40031 \ram2e_ufm/RWBank_3_0[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
|
|
vmuxregsre \RWBank[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
vmuxregsre \RWBank[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module SLICE_29 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0,
|
|
Q0, F1, Q1 );
|
|
wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
|
|
|
|
lut40031 \ram2e_ufm/RWBank_3_0[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40031 \ram2e_ufm/RWBank_3_0_0[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI),
|
|
.Z(F0));
|
|
vmuxregsre \RWBank[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
vmuxregsre \RWBank[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module SLICE_30 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0,
|
|
Q0, F1, Q1 );
|
|
wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
|
|
|
|
lut40032 \ram2e_ufm/RWBank_3_0[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40031 \ram2e_ufm/RWBank_3_0[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
|
|
vmuxregsre \RWBank[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
vmuxregsre \RWBank[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40032 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hECEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_31 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output
|
|
F0, Q0, F1 );
|
|
wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;
|
|
|
|
lut40033 \ram2e_ufm/RA_35_0_0_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40034 \ram2e_ufm/RWSel_2_0_a3_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0),
|
|
.Z(F0));
|
|
vmuxregsre RWSel( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40033 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40034 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_32 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 );
|
|
wire GNDI, VCCI, DI0_dly, CLK_dly;
|
|
|
|
lut40035 \ram2e_ufm/Ready3_0_a3 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40036 Ready_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
vmuxregsre Ready( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40035 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40036 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_33 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CLK, output
|
|
F0, Q0, F1, Q1 );
|
|
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
|
|
|
|
lut40037 \ram2e_ufm/S_r_i_0_o2_0_RNI36E21[1] ( .A(A1), .B(B1), .C(C1),
|
|
.D(D1), .Z(F1));
|
|
lut40038 \ram2e_ufm/S_s_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
vmuxregsre \S[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
vmuxregsre \S[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40037 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h4500) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40038 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hFBFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_34 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CLK, output
|
|
F0, Q0, F1, Q1 );
|
|
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly;
|
|
|
|
lut40039 \ram2e_ufm/S_r_i_0_o2_RNIFNP81_0[2] ( .A(A1), .B(B1), .C(C1),
|
|
.D(D1), .Z(F1));
|
|
lut40040 \ram2e_ufm/S_r_i_0_o2_RNIFNP81[2] ( .A(A0), .B(B0), .C(C0), .D(D0),
|
|
.Z(F0));
|
|
vmuxregsre \S[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
vmuxregsre \S[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40039 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h0B0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40040 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h5141) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_35 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0,
|
|
F1 );
|
|
wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly;
|
|
|
|
lut40016 \ram2e_ufm/CKE_7_m1_0_0_o2_RNICM8E1 ( .A(A1), .B(B1), .C(C1),
|
|
.D(D1), .Z(F1));
|
|
lut40036 \ram2e_ufm/CKE_7_m1_0_0_o2 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI),
|
|
.Z(F0));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
vmuxregsre0010 VOEEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
|
|
$width (posedge LSR, 0:0:0);
|
|
$width (negedge LSR, 0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module SLICE_36 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0,
|
|
Q0, F1 );
|
|
wire VCCI, GNDI, DI0_dly, CLK_dly;
|
|
|
|
lut40041 \ram2e_ufm/nRAS_s_i_0_a3_5_RNIH7J73 ( .A(A1), .B(B1), .C(C1),
|
|
.D(D1), .Z(F1));
|
|
lut40042 \ram2e_ufm/nCAS_s_i_0_a3_RNIO1UQ3 ( .A(A0), .B(B0), .C(C0), .D(D0),
|
|
.Z(F0));
|
|
vmuxregsre0004 nCAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40041 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40042 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h1101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_37 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0,
|
|
Q0, F1 );
|
|
wire VCCI, GNDI, DI0_dly, CLK_dly;
|
|
|
|
lut40034 \ram2e_ufm/nRAS_s_i_0_a3_5_RNIH7J73_0 ( .A(A1), .B(B1), .C(C1),
|
|
.D(D1), .Z(F1));
|
|
lut40016 \ram2e_ufm/nRAS_s_i_0_0_RNI0PC64 ( .A(A0), .B(B0), .C(C0), .D(D0),
|
|
.Z(F0));
|
|
vmuxregsre0004 nRAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module SLICE_38 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0,
|
|
Q0, F1 );
|
|
wire VCCI, GNDI, DI0_dly, CLK_dly;
|
|
|
|
lut40043 \ram2e_ufm/nRAS_s_i_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40044 \ram2e_ufm/nRAS_s_i_0_a3_0_RNIIR094 ( .A(A0), .B(B0), .C(C0),
|
|
.D(D0), .Z(F0));
|
|
vmuxregsre0004 nRWE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI),
|
|
.CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40043 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40044 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h0111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_39 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK,
|
|
output F0, Q0, F1 );
|
|
wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;
|
|
|
|
lut40045 \ram2e_ufm/CmdBitbangMXO2_3_0_a3_1 ( .A(A1), .B(B1), .C(C1), .D(D1),
|
|
.Z(F1));
|
|
lut40019 \ram2e_ufm/CmdBitbangMXO2_3_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0),
|
|
.Z(F0));
|
|
vmuxregsre \ram2e_ufm/CmdBitbangMXO2 ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI),
|
|
.SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40045 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_40 ( input D1, C1, B1, A1, B0, A0, DI0, CE, CLK,
|
|
output F0, Q0, F1 );
|
|
wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
|
|
|
|
lut40014 \ram2e_ufm/CmdBitbangMXO2_3_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(D1),
|
|
.Z(F1));
|
|
lut40023 \ram2e_ufm/CmdExecMXO2_3_0_a3 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI),
|
|
.Z(F0));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
vmuxregsre \ram2e_ufm/CmdExecMXO2 ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI),
|
|
.SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_41 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK,
|
|
output F0, Q0, F1 );
|
|
wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;
|
|
|
|
lut40046 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3_0_0 ( .A(A1), .B(B1),
|
|
.C(C1), .D(D1), .Z(F1));
|
|
lut40014 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3 ( .A(A0), .B(B0), .C(C0),
|
|
.D(D0), .Z(F0));
|
|
vmuxregsre \ram2e_ufm/CmdSetRWBankFFChip ( .D0(VCCI), .D1(DI0_dly),
|
|
.SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40046 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_42 ( input C1, B1, A1, C0, B0, A0, DI0, CE, CLK,
|
|
output F0, Q0, F1 );
|
|
wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
|
|
|
|
lut40047 \ram2e_ufm/SUM1_0_o3_0 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40048 \ram2e_ufm/LEDEN_RNO ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
|
|
vmuxregsre \ram2e_ufm/LEDEN ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI),
|
|
.SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40047 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40048 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hB8B8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_43 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK,
|
|
output F0, Q0, F1, Q1 );
|
|
wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
|
|
|
|
lut40049 \ram2e_ufm/RWMask_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40049 \ram2e_ufm/RWMask_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
|
|
vmuxregsre \ram2e_ufm/RWMask[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI),
|
|
.SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
vmuxregsre \ram2e_ufm/RWMask[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI),
|
|
.SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40049 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h7474) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_44 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK,
|
|
output F0, Q0, F1, Q1 );
|
|
wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
|
|
|
|
lut40049 \ram2e_ufm/RWMask_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40049 \ram2e_ufm/RWMask_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
|
|
vmuxregsre \ram2e_ufm/RWMask[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI),
|
|
.SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
vmuxregsre \ram2e_ufm/RWMask[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI),
|
|
.SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_45 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK,
|
|
output F0, Q0, F1, Q1 );
|
|
wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
|
|
|
|
lut40049 \ram2e_ufm/RWMask_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40049 \ram2e_ufm/RWMask_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
|
|
vmuxregsre \ram2e_ufm/RWMask[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI),
|
|
.SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
vmuxregsre \ram2e_ufm/RWMask[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI),
|
|
.SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_46 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK,
|
|
output F0, Q0, F1, Q1 );
|
|
wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
|
|
|
|
lut40048 \ram2e_ufm/RWMask_RNO[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40049 \ram2e_ufm/RWMask_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
|
|
vmuxregsre \ram2e_ufm/RWMask[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI),
|
|
.SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
vmuxregsre \ram2e_ufm/RWMask[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI),
|
|
.SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_47 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE,
|
|
CLK, output F0, Q0, F1, Q1 );
|
|
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
|
|
|
|
lut40050 \ram2e_ufm/wb_adr_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40024 \ram2e_ufm/wb_adr_7_i_i[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
vmuxregsre \ram2e_ufm/wb_adr[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI),
|
|
.SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
vmuxregsre \ram2e_ufm/wb_adr[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI),
|
|
.SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40050 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hFFEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_48 ( input B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0,
|
|
Q0, F1, Q1 );
|
|
wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
|
|
|
|
lut40023 \ram2e_ufm/wb_adr_RNO[3] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI),
|
|
.Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40023 \ram2e_ufm/wb_adr_RNO[2] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI),
|
|
.Z(F0));
|
|
vmuxregsre \ram2e_ufm/wb_adr[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI),
|
|
.SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
vmuxregsre \ram2e_ufm/wb_adr[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI),
|
|
.SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
|
|
specify
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_49 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK,
|
|
output F0, Q0, F1, Q1 );
|
|
wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
|
|
|
|
lut40051 \ram2e_ufm/wb_adr_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40051 \ram2e_ufm/wb_adr_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
|
|
vmuxregsre \ram2e_ufm/wb_adr[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI),
|
|
.SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
vmuxregsre \ram2e_ufm/wb_adr[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI),
|
|
.SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40051 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hA3A3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_50 ( input B1, A1, C0, B0, A0, DI1, DI0, CE, CLK,
|
|
output F0, Q0, F1, Q1 );
|
|
wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
|
|
|
|
lut40023 \ram2e_ufm/wb_adr_RNO[7] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI),
|
|
.Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40051 \ram2e_ufm/wb_adr_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
|
|
vmuxregsre \ram2e_ufm/wb_adr[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI),
|
|
.SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
vmuxregsre \ram2e_ufm/wb_adr[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI),
|
|
.SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
|
|
specify
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_51 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK,
|
|
output F0, Q0, F1 );
|
|
wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly;
|
|
|
|
lut40052 \ram2e_ufm/wb_cyc_stb_RNO_0 ( .A(A1), .B(B1), .C(C1), .D(D1),
|
|
.Z(F1));
|
|
lut40053 \ram2e_ufm/wb_cyc_stb_RNO ( .A(A0), .B(B0), .C(C0), .D(GNDI),
|
|
.Z(F0));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
vmuxregsre \ram2e_ufm/wb_cyc_stb ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI),
|
|
.SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40052 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h0032) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40053 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hEAEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE,
|
|
CLK, output F0, Q0, F1, Q1 );
|
|
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
|
|
|
|
lut40054 \ram2e_ufm/wb_dati_7_0_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1),
|
|
.Z(F1));
|
|
lut40055 \ram2e_ufm/wb_dati_7_0_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0),
|
|
.Z(F0));
|
|
vmuxregsre \ram2e_ufm/wb_dati[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI),
|
|
.SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
vmuxregsre \ram2e_ufm/wb_dati[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI),
|
|
.SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40054 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hFFEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40055 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_53 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE,
|
|
CLK, output F0, Q0, F1, Q1 );
|
|
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
|
|
|
|
lut40054 \ram2e_ufm/wb_dati_7_0_0_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1),
|
|
.Z(F1));
|
|
lut40054 \ram2e_ufm/wb_dati_7_0_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0),
|
|
.Z(F0));
|
|
vmuxregsre \ram2e_ufm/wb_dati[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI),
|
|
.SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
vmuxregsre \ram2e_ufm/wb_dati[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI),
|
|
.SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_54 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE,
|
|
CLK, output F0, Q0, F1, Q1 );
|
|
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
|
|
|
|
lut40054 \ram2e_ufm/wb_dati_7_0_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1),
|
|
.Z(F1));
|
|
lut4 \ram2e_ufm/wb_dati_7_0_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
vmuxregsre \ram2e_ufm/wb_dati[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI),
|
|
.SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
vmuxregsre \ram2e_ufm/wb_dati[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI),
|
|
.SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_55 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE,
|
|
CLK, output F0, Q0, F1, Q1 );
|
|
wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly;
|
|
|
|
lut4 \ram2e_ufm/wb_dati_7_0_0_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40054 \ram2e_ufm/wb_dati_7_0_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0),
|
|
.Z(F0));
|
|
vmuxregsre \ram2e_ufm/wb_dati[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI),
|
|
.SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
vmuxregsre \ram2e_ufm/wb_dati[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI),
|
|
.SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
(CLK => Q1) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_56 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR,
|
|
CLK, output F0, Q0, F1 );
|
|
wire VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly;
|
|
|
|
lut4 \ram2e_ufm/wb_reqc_1_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40056 \ram2e_ufm/wb_req_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
vmuxregsre0010 \ram2e_ufm/wb_req ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI),
|
|
.SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
|
|
$width (posedge LSR, 0:0:0);
|
|
$width (negedge LSR, 0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40056 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h007F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_57 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK,
|
|
output F0, Q0, F1 );
|
|
wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly;
|
|
|
|
lut40035 \ram2e_ufm/Ready3_0_a3_4 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40006 \ram2e_ufm/wb_rst8_0_a3_0_a3 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI),
|
|
.Z(F0));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
vmuxregsre0010 \ram2e_ufm/wb_rst ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI),
|
|
.SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
|
|
$width (posedge LSR, 0:0:0);
|
|
$width (negedge LSR, 0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_58 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK,
|
|
output F0, Q0, F1 );
|
|
wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly;
|
|
|
|
lut40057 \ram2e_ufm/wb_we_RNO_2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40057 \ram2e_ufm/wb_we_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
vmuxregsre \ram2e_ufm/wb_we ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI),
|
|
.SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
(CLK => Q0) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40057 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hFF40) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SUM0_i_m3_0_SLICE_59 ( input C1, B1, A1, C0, B0, A0, M0,
|
|
output OFX0 );
|
|
wire GNDI,
|
|
\ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/SLICE_59_K1_H1 ,
|
|
\ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/GATE_H0 ;
|
|
|
|
lut40058 \ram2e_ufm/SUM0_i_m3_0/SLICE_59_K1 ( .A(A1), .B(B1), .C(C1),
|
|
.D(GNDI),
|
|
.Z(\ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/SLICE_59_K1_H1 ));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40059 \ram2e_ufm/SUM0_i_m3_0/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI),
|
|
.Z(\ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/GATE_H0 ));
|
|
selmux2 \ram2e_ufm/SUM0_i_m3_0/SLICE_59_K0K1MUX (
|
|
.D0(\ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/GATE_H0 ),
|
|
.D1(\ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/SLICE_59_K1_H1 ),
|
|
.SD(M0), .Z(OFX0));
|
|
|
|
specify
|
|
(C1 => OFX0) = (0:0:0,0:0:0);
|
|
(B1 => OFX0) = (0:0:0,0:0:0);
|
|
(A1 => OFX0) = (0:0:0,0:0:0);
|
|
(C0 => OFX0) = (0:0:0,0:0:0);
|
|
(B0 => OFX0) = (0:0:0,0:0:0);
|
|
(A0 => OFX0) = (0:0:0,0:0:0);
|
|
(M0 => OFX0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40058 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hF7F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40059 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module selmux2 ( input D0, D1, SD, output Z );
|
|
|
|
MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_un1_CS_0_sqmuxa_0_0_0_SLICE_60 ( input D1, C1, B1, A1, C0, B0,
|
|
A0, M0, output OFX0 );
|
|
wire
|
|
\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60_K1_H1
|
|
, GNDI,
|
|
\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/GATE_H0
|
|
;
|
|
|
|
lut40060 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60_K1 ( .A(A1), .B(B1),
|
|
.C(C1), .D(D1),
|
|
.Z(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60_K1_H1 )
|
|
);
|
|
lut40061 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/GATE ( .A(A0), .B(B0), .C(C0),
|
|
.D(GNDI),
|
|
.Z(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/GATE_H0 )
|
|
);
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
selmux2 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60_K0K1MUX (
|
|
.D0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/GATE_H0 )
|
|
,
|
|
.D1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60_K1_H1 )
|
|
, .SD(M0), .Z(OFX0));
|
|
|
|
specify
|
|
(D1 => OFX0) = (0:0:0,0:0:0);
|
|
(C1 => OFX0) = (0:0:0,0:0:0);
|
|
(B1 => OFX0) = (0:0:0,0:0:0);
|
|
(A1 => OFX0) = (0:0:0,0:0:0);
|
|
(C0 => OFX0) = (0:0:0,0:0:0);
|
|
(B0 => OFX0) = (0:0:0,0:0:0);
|
|
(A0 => OFX0) = (0:0:0,0:0:0);
|
|
(M0 => OFX0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40060 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h55D5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40061 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_CKE_7_SLICE_61 ( input C1, B1, A1, C0, B0, A0, M0, output
|
|
OFX0 );
|
|
wire GNDI, \ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/SLICE_61_K1_H1 ,
|
|
\ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/GATE_H0 ;
|
|
|
|
lut40062 \ram2e_ufm/CKE_7/SLICE_61_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI),
|
|
.Z(\ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/SLICE_61_K1_H1 ));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40063 \ram2e_ufm/CKE_7/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI),
|
|
.Z(\ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/GATE_H0 ));
|
|
selmux2 \ram2e_ufm/CKE_7/SLICE_61_K0K1MUX (
|
|
.D0(\ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/GATE_H0 ),
|
|
.D1(\ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/SLICE_61_K1_H1 ), .SD(M0),
|
|
.Z(OFX0));
|
|
|
|
specify
|
|
(C1 => OFX0) = (0:0:0,0:0:0);
|
|
(B1 => OFX0) = (0:0:0,0:0:0);
|
|
(A1 => OFX0) = (0:0:0,0:0:0);
|
|
(C0 => OFX0) = (0:0:0,0:0:0);
|
|
(B0 => OFX0) = (0:0:0,0:0:0);
|
|
(A0 => OFX0) = (0:0:0,0:0:0);
|
|
(M0 => OFX0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40062 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h5D5D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40063 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_62 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0,
|
|
F1 );
|
|
|
|
lut40043 \ram2e_ufm/CmdExecMXO2_3_0_a3_0_RNIAJ811 ( .A(A1), .B(B1), .C(C1),
|
|
.D(D1), .Z(F1));
|
|
lut40064 \ram2e_ufm/CmdExecMXO2_3_0_a3_0_RNIPG3P2 ( .A(A0), .B(B0), .C(C0),
|
|
.D(D0), .Z(F0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40064 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hFF02) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_63 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0,
|
|
F1 );
|
|
|
|
lut40065 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3_0_RNIA0N95 ( .A(A1), .B(B1),
|
|
.C(C1), .D(D1), .Z(F1));
|
|
lut40066 \ram2e_ufm/S_r_i_0_o2_RNI3VQTC[1] ( .A(A0), .B(B0), .C(C0), .D(D0),
|
|
.Z(F0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40065 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hFF10) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40066 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hFFF4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_64 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40067 \ram2e_ufm/wb_adr_7_i_i_a3_6[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI),
|
|
.Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40068 \ram2e_ufm/wb_adr_7_i_i_5[0] ( .A(A0), .B(B0), .C(C0), .D(D0),
|
|
.Z(F0));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40067 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40068 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hF4F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_65 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0,
|
|
F1 );
|
|
|
|
lut40069 \ram2e_ufm/SUM0_i_a3_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40065 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3_0_RNIN3AF2 ( .A(A0), .B(B0),
|
|
.C(C0), .D(D0), .Z(F0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40069 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h1500) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_66 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0,
|
|
F1 );
|
|
|
|
lut40070 \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_0[0] ( .A(A1), .B(B1),
|
|
.C(C1), .D(D1), .Z(F1));
|
|
lut40071 \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0] ( .A(A0), .B(B0),
|
|
.C(C0), .D(D0), .Z(F0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40070 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hCCC8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40071 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hF5F4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_67 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40072 \ram2e_ufm/nRAS_s_i_0_m3 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40073 \ram2e_ufm/nRAS_s_i_0_o2_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40072 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h8B8B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40073 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hFFF6) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_68 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0,
|
|
F1 );
|
|
|
|
lut40074 \ram2e_ufm/wb_adr_7_i_i_3[0] ( .A(A1), .B(B1), .C(C1), .D(D1),
|
|
.Z(F1));
|
|
lut40075 \ram2e_ufm/wb_adr_7_i_i_3_1[0] ( .A(A0), .B(B0), .C(C0), .D(D0),
|
|
.Z(F0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40074 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h0090) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40075 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h01A1) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_69 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0,
|
|
F1 );
|
|
|
|
lut40076 \ram2e_ufm/nCAS_s_i_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut4 \ram2e_ufm/wb_rst16_i_i_i_o3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40076 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_70 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40077 \ram2e_ufm/wb_dati_7_0_0_a3_12[7] ( .A(A1), .B(B1), .C(C1),
|
|
.D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40078 \ram2e_ufm/wb_dati_7_0_0_0_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(D0),
|
|
.Z(F0));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40077 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h0404) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40078 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h8808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_71 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40013 \ram2e_ufm/RA_35_0_0_a3_4[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI),
|
|
.Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40079 \ram2e_ufm/nRAS_s_i_0_a3_4 ( .A(A0), .B(B0), .C(C0), .D(GNDI),
|
|
.Z(F0));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40079 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h0101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_72 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40080 \ram2e_ufm/BA_4[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40047 \ram2e_ufm/un1_RC12_i_0_o3 ( .A(A0), .B(B0), .C(C0), .D(GNDI),
|
|
.Z(F0));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40080 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hC0D0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0,
|
|
F1 );
|
|
|
|
lut40081 \ram2e_ufm/wb_dati_7_0_0_o3_0[2] ( .A(A1), .B(B1), .C(C1), .D(D1),
|
|
.Z(F1));
|
|
lut40082 \ram2e_ufm/wb_dati_7_0_0_a3_3[4] ( .A(A0), .B(B0), .C(C0), .D(D0),
|
|
.Z(F0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40081 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hECCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40082 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_74 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40053 \ram2e_ufm/RA_35_2_0_0[10] ( .A(A1), .B(B1), .C(C1), .D(GNDI),
|
|
.Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40034 \ram2e_ufm/RA_35_2_0_a3_5[10] ( .A(A0), .B(B0), .C(C0), .D(D0),
|
|
.Z(F0));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_75 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40079 \ram2e_ufm/wb_dati_7_0_0_a3_15[7] ( .A(A1), .B(B1), .C(C1),
|
|
.D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40015 \ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0_RNO[0] ( .A(A0), .B(B0),
|
|
.C(C0), .D(D0), .Z(F0));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_76 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40083 \ram2e_ufm/wb_dati_7_0_0_a3_13[7] ( .A(A1), .B(B1), .C(GNDI),
|
|
.D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40019 \ram2e_ufm/wb_dati_7_0_0_0_0_RNO[7] ( .A(A0), .B(B0), .C(C0),
|
|
.D(D0), .Z(F0));
|
|
|
|
specify
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40083 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h2222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_77 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40084 \ram2e_ufm/SUM2_0_o2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40085 \ram2e_ufm/N_314_i_i_o3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40084 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hF7F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40085 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hFFF7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_78 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40036 \ram2e_ufm/S_r_i_0_o2[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI),
|
|
.Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40041 \ram2e_ufm/S_r_i_0_o2_RNIP4KI1[1] ( .A(A0), .B(B0), .C(C0), .D(D0),
|
|
.Z(F0));
|
|
|
|
specify
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_79 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0,
|
|
F1 );
|
|
|
|
lut40086 \ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0] ( .A(A1), .B(B1), .C(C1),
|
|
.D(D1), .Z(F1));
|
|
lut40087 \ram2e_ufm/S_r_i_0_o2_RNIOGTF1[1] ( .A(A0), .B(B0), .C(C0), .D(D0),
|
|
.Z(F0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40086 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hF222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40087 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hFF7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_80 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0,
|
|
F1 );
|
|
|
|
lut40034 \ram2e_ufm/un1_wb_cyc_stb_0_sqmuxa_1_i_0_0_a2[0] ( .A(A1), .B(B1),
|
|
.C(C1), .D(D1), .Z(F1));
|
|
lut40088 \ram2e_ufm/CmdBitbangMXO2_RNINSM62 ( .A(A0), .B(B0), .C(C0), .D(D0),
|
|
.Z(F0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40088 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hCCEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0,
|
|
F1 );
|
|
|
|
lut40017 \ram2e_ufm/wb_dati_7_0_0_a3_14[7] ( .A(A1), .B(B1), .C(C1), .D(D1),
|
|
.Z(F1));
|
|
lut40035 \ram2e_ufm/wb_dati_7_0_0_a3_13_RNI81UL[7] ( .A(A0), .B(B0), .C(C0),
|
|
.D(D0), .Z(F0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_82 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0,
|
|
F1 );
|
|
|
|
lut40019 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_0 ( .A(A1), .B(B1), .C(C1),
|
|
.D(D1), .Z(F1));
|
|
lut40016 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0_RNIVQNQ2 ( .A(A0), .B(B0), .C(C0),
|
|
.D(D0), .Z(F0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_83 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40067 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0 ( .A(A1), .B(B1), .C(C1),
|
|
.D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40089 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S ( .A(A0), .B(B0),
|
|
.C(C0), .D(D0), .Z(F0));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40089 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hA020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_84 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0,
|
|
F1 );
|
|
|
|
lut40082 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_9_RNIJT9D1 ( .A(A1), .B(B1),
|
|
.C(C1), .D(D1), .Z(F1));
|
|
lut40090 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_9_RNI3N8T5 ( .A(A0), .B(B0),
|
|
.C(C0), .D(D0), .Z(F0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40090 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h3130) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0,
|
|
F1 );
|
|
|
|
lut40017 \ram2e_ufm/wb_dati_7_0_0_a3_10[7] ( .A(A1), .B(B1), .C(C1), .D(D1),
|
|
.Z(F1));
|
|
lut40086 \ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ( .A(A0), .B(B0), .C(C0),
|
|
.D(D0), .Z(F0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_86 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40023 \ram2e_ufm/wb_we_7_iv_0_0_0_a3_1 ( .A(A1), .B(B1), .C(GNDI),
|
|
.D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut4 \ram2e_ufm/wb_adr_7_i_i_4[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
|
|
specify
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_87 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40091 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_o3_RNIGCV91 ( .A(A1), .B(B1),
|
|
.C(C1), .D(D1), .Z(F1));
|
|
lut40092 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_m3 ( .A(A0), .B(B0), .C(C0),
|
|
.D(GNDI), .Z(F0));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40091 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hFFFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40092 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h8D8D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_88 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40093 \ram2e_ufm/wb_dati_7_0_0_a3_4_1_0[7] ( .A(A1), .B(B1), .C(GNDI),
|
|
.D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40094 \ram2e_ufm/wb_dati_7_0_0_RNO_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0),
|
|
.Z(F0));
|
|
|
|
specify
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40093 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h4444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40094 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hC8C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_89 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40077 \ram2e_ufm/wb_dati_7_0_0_a3_7[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI),
|
|
.Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40055 \ram2e_ufm/wb_dati_7_0_0_0_0[3] ( .A(A0), .B(B0), .C(C0), .D(D0),
|
|
.Z(F0));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_90 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0,
|
|
F1 );
|
|
|
|
lut40095 \ram2e_ufm/wb_dati_7_0_0_a3_1_0[6] ( .A(A1), .B(B1), .C(C1), .D(D1),
|
|
.Z(F1));
|
|
lut40055 \ram2e_ufm/wb_dati_7_0_0_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0),
|
|
.Z(F0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40095 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h0021) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_91 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0,
|
|
F1 );
|
|
|
|
lut40096 \ram2e_ufm/nRAS_s_i_0_a3_8 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40097 \ram2e_ufm/nRAS_s_i_0_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40096 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40097 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h5540) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_92 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0,
|
|
F1 );
|
|
|
|
lut40098 \ram2e_ufm/CKE_7s2_0_0_o3 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40099 \ram2e_ufm/nCAS_s_i_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40098 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h5C50) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40099 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h5400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_93 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40100 \ram2e_ufm/wb_dati_7_0_0_o2[4] ( .A(A1), .B(B1), .C(C1), .D(D1),
|
|
.Z(F1));
|
|
lut40013 \ram2e_ufm/wb_dati_7_0_0_a3[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI),
|
|
.Z(F0));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40100 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h7880) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_94 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40101 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ( .A(A1), .B(B1), .C(GNDI),
|
|
.D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40041 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_2_2 ( .A(A0), .B(B0), .C(C0),
|
|
.D(D0), .Z(F0));
|
|
|
|
specify
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40101 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hBBBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_95 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0,
|
|
F1 );
|
|
|
|
lut40102 \ram2e_ufm/RA_35_0_0_o2[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40033 \ram2e_ufm/RA_35_0_0_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40102 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hEAE8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_96 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0,
|
|
F1 );
|
|
|
|
lut40103 \ram2e_ufm/RA_35_0_0_o2_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1),
|
|
.Z(F1));
|
|
lut40033 \ram2e_ufm/RA_35_0_0_0_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0),
|
|
.Z(F0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40103 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h1512) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_97 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40104 \ram2e_ufm/wb_dati_7_0_0_a3_0_0[1] ( .A(A1), .B(B1), .C(C1),
|
|
.D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40055 \ram2e_ufm/wb_dati_7_0_0_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0),
|
|
.Z(F0));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40104 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_98 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40093 \ram2e_ufm/wb_dati_7_0_0_a3_9[7] ( .A(A1), .B(B1), .C(GNDI),
|
|
.D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40055 \ram2e_ufm/wb_dati_7_0_0_0_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0),
|
|
.Z(F0));
|
|
|
|
specify
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_99 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40105 \ram2e_ufm/wb_adr_7_i_i_a3_2_0[0] ( .A(A1), .B(B1), .C(C1),
|
|
.D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40106 \ram2e_ufm/wb_adr_7_i_i_1[0] ( .A(A0), .B(B0), .C(C0), .D(D0),
|
|
.Z(F0));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40105 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40106 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hF040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_100 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0,
|
|
F1 );
|
|
|
|
lut4 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3_0 ( .A(A1), .B(B1), .C(C1), .D(D1),
|
|
.Z(F1));
|
|
lut40107 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3_0_RNI9H8R ( .A(A0), .B(B0),
|
|
.C(C0), .D(D0), .Z(F0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40107 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hBF8F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_101 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40022 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_o3 ( .A(A1), .B(B1),
|
|
.C(GNDI), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40108 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o2 ( .A(A0), .B(B0), .C(C0), .D(D0),
|
|
.Z(F0));
|
|
|
|
specify
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40108 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hB1A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_102 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40077 \ram2e_ufm/CKE_7s2_0_0_a2_1 ( .A(A1), .B(B1), .C(C1), .D(GNDI),
|
|
.Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40047 \ram2e_ufm/CKE_7s2_0_0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_103 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40101 \ram2e_ufm/wb_dati_7_0_0_0_o2[7] ( .A(A1), .B(B1), .C(GNDI),
|
|
.D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40109 \ram2e_ufm/wb_adr_RNO_1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
|
|
specify
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40109 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h7040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_104 ( input D1, C1, B1, A1, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40110 \ram2e_ufm/wb_dati_7_0_0_o2_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1),
|
|
.Z(F1));
|
|
lut40093 \ram2e_ufm/wb_dati_7_0_0_0_a3_0[3] ( .A(A0), .B(B0), .C(GNDI),
|
|
.D(GNDI), .Z(F0));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40110 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h7084) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_105 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40016 \ram2e_ufm/S_r_i_0_o2_RNI62C53[1] ( .A(A1), .B(B1), .C(C1), .D(D1),
|
|
.Z(F1));
|
|
lut40111 \ram2e_ufm/N_285_i ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40111 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h0B0B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_106 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40022 \ram2e_ufm/S_r_i_0_o2[2] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI),
|
|
.Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40112 \ram2e_ufm/RA_35_2_0_a3[10] ( .A(A0), .B(B0), .C(C0), .D(D0),
|
|
.Z(F0));
|
|
|
|
specify
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40112 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hD050) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_107 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0,
|
|
F1 );
|
|
|
|
lut40113 \ram2e_ufm/CKE_7_m1_0_0_o2_RNIGC501 ( .A(A1), .B(B1), .C(C1),
|
|
.D(D1), .Z(F1));
|
|
lut40114 \ram2e_ufm/RA_35_i_i_0_a3[1] ( .A(A0), .B(B0), .C(C0), .D(D0),
|
|
.Z(F0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40113 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40114 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hD800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_108 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut4 \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_o3[0] ( .A(A1), .B(B1),
|
|
.C(C1), .D(D1), .Z(F1));
|
|
lut40115 \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0[0] ( .A(A0),
|
|
.B(B0), .C(C0), .D(GNDI), .Z(F0));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40115 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h3131) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_109 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40006 \ram2e_ufm/wb_we_7_iv_0_0_0_a3_6 ( .A(A1), .B(B1), .C(GNDI),
|
|
.D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40068 \ram2e_ufm/wb_we_RNO_3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
|
|
specify
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_110 ( input D1, C1, B1, A1, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40035 \ram2e_ufm/wb_we_7_iv_0_0_0_a3_7 ( .A(A1), .B(B1), .C(C1), .D(D1),
|
|
.Z(F1));
|
|
lut40023 \ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] ( .A(A0), .B(B0),
|
|
.C(GNDI), .D(GNDI), .Z(F0));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_111 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40104 \ram2e_ufm/wb_dati_7_0_0_a3_2[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI),
|
|
.Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40116 \ram2e_ufm/wb_dati_7_0_0_0_o2[3] ( .A(A0), .B(B0), .C(C0), .D(D0),
|
|
.Z(F0));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40116 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h9180) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_112 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40018 \ram2e_ufm/nRAS_s_i_0_a3_6 ( .A(A1), .B(B1), .C(C1), .D(GNDI),
|
|
.Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40117 \ram2e_ufm/nRAS_s_i_0_a3_1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40117 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_113 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40077 \ram2e_ufm/nRAS_s_i_0_a3_5 ( .A(A1), .B(B1), .C(C1), .D(GNDI),
|
|
.Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40014 \ram2e_ufm/RA_35_2_0_a3_3[10] ( .A(A0), .B(B0), .C(C0), .D(D0),
|
|
.Z(F0));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_114 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40118 \ram2e_ufm/wb_adr_RNO_2[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI),
|
|
.Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40117 \ram2e_ufm/wb_adr_RNO_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40118 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h8787) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_115 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40036 \ram2e_ufm/un2_S_2_i_0_0_o3 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI),
|
|
.Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40119 \ram2e_ufm/CKE_7s2_0_0_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
|
|
specify
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40119 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h0C4C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_116 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40014 \ram2e_ufm/CmdExecMXO2_3_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(D1),
|
|
.Z(F1));
|
|
lut40067 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3_0 ( .A(A0), .B(B0),
|
|
.C(C0), .D(GNDI), .Z(F0));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_117 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0,
|
|
F1 );
|
|
|
|
lut40120 \ram2e_ufm/S_s_0_0_RNO[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40121 \ram2e_ufm/N_225_i ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40120 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h0F0E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40121 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h0007) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_118 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0,
|
|
F1 );
|
|
|
|
lut40113 \ram2e_ufm/CKE_7_m1_0_0_o2_RNI7FOA1 ( .A(A1), .B(B1), .C(C1),
|
|
.D(D1), .Z(F1));
|
|
lut40122 \ram2e_ufm/N_201_i ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40122 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h000D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_119 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0,
|
|
F1 );
|
|
|
|
lut40123 \ram2e_ufm/S_r_i_0_o2_RNIBAU51[1] ( .A(A1), .B(B1), .C(C1), .D(D1),
|
|
.Z(F1));
|
|
lut40124 \ram2e_ufm/un1_CKE75_0_i_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40123 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40124 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hD79B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_120 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0,
|
|
F1 );
|
|
|
|
lut40125 \ram2e_ufm/DQMH_4_iv_0_0_i_i_a3_0_a3 ( .A(A1), .B(B1), .C(C1),
|
|
.D(D1), .Z(F1));
|
|
lut40126 \ram2e_ufm/N_507_i ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40125 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h31F5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40126 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hCD05) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_121 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0,
|
|
F1 );
|
|
|
|
lut40127 \ram2e_ufm/Vout3_0_a3_0_a3_0_a3 ( .A(A1), .B(B1), .C(C1), .D(D1),
|
|
.Z(F1));
|
|
lut40128 \ram2e_ufm/RA_35_0_0_o2[11] ( .A(A0), .B(B0), .C(C0), .D(D0),
|
|
.Z(F0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40127 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40128 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hFCF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_122 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0,
|
|
F1 );
|
|
|
|
lut40129 \ram2e_ufm/nRWE_s_i_0_63_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40130 \ram2e_ufm/nCAS_s_i_0_m2 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40129 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h4FFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40130 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h37FA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_123 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40131 \ram2e_ufm/wb_adr_RNO_3[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI),
|
|
.Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40019 \ram2e_ufm/wb_dati_7_0_0_a3_8[3] ( .A(A0), .B(B0), .C(C0), .D(D0),
|
|
.Z(F0));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40131 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_124 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0,
|
|
F1 );
|
|
|
|
lut40132 \ram2e_ufm/RA_35_0_0_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40035 \ram2e_ufm/RA_35_0_0_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0),
|
|
.Z(F0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40132 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h7300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_125 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0,
|
|
F1 );
|
|
|
|
lut40133 \ram2e_ufm/wb_adr_7_i_i_o2_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1),
|
|
.Z(F1));
|
|
lut40045 \ram2e_ufm/wb_dati_7_0_0_a3_2[4] ( .A(A0), .B(B0), .C(C0), .D(D0),
|
|
.Z(F0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40133 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h7F70) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_126 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0,
|
|
F1 );
|
|
|
|
lut40134 \ram2e_ufm/wb_we_RNO_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40117 \ram2e_ufm/wb_adr_7_i_i_a3_4[0] ( .A(A0), .B(B0), .C(C0), .D(D0),
|
|
.Z(F0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40134 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h7F07) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_127 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0,
|
|
F1 );
|
|
|
|
lut40117 \ram2e_ufm/un9_VOEEN_0_a2_0_a3_0_a3 ( .A(A1), .B(B1), .C(C1),
|
|
.D(D1), .Z(F1));
|
|
lut40046 \ram2e_ufm/RA_35_2_30_a3_2 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_128 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40135 \ram2e_ufm/wb_dati_7_0_0_0_a3_0[0] ( .A(A1), .B(B1), .C(C1), .D(D1),
|
|
.Z(F1));
|
|
lut40136 \ram2e_ufm/wb_adr_RNO_4[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI),
|
|
.Z(F0));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40135 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h2080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40136 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_129 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0,
|
|
F1 );
|
|
|
|
lut40080 \ram2e_ufm/BA_4[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40016 \ram2e_ufm/RA_35_2_0_RNO[10] ( .A(A0), .B(B0), .C(C0), .D(D0),
|
|
.Z(F0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_130 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40083 \ram2e_ufm/N_187_i ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40088 \ram2e_ufm/wb_we_RNO_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
|
|
specify
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_131 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0,
|
|
F1 );
|
|
|
|
lut40035 \ram2e_ufm/Ready3_0_a3_5 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40137 \ram2e_ufm/wb_dati_7_0_0_0_a3[7] ( .A(A0), .B(B0), .C(C0), .D(D0),
|
|
.Z(F0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40137 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h9000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_132 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0,
|
|
F1 );
|
|
|
|
lut40138 \ram2e_ufm/RA_35_0_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40033 \ram2e_ufm/RA_35_0_0_0_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0),
|
|
.Z(F0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40138 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h0777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_133 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40035 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_0_1 ( .A(A1), .B(B1), .C(C1),
|
|
.D(D1), .Z(F1));
|
|
lut40084 \ram2e_ufm/SUM0_i_o2_2 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_134 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0,
|
|
F1 );
|
|
|
|
lut4 \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3[0] ( .A(A1), .B(B1),
|
|
.C(C1), .D(D1), .Z(F1));
|
|
lut40114 \ram2e_ufm/RA_35_0_0_a3[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_135 ( input B1, A1, D0, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40022 \ram2e_ufm/S_r_i_0_o2_0[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI),
|
|
.Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40139 \ram2e_ufm/RA_35_2_0_a3_0[10] ( .A(A0), .B(B0), .C(C0), .D(D0),
|
|
.Z(F0));
|
|
|
|
specify
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40139 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h0444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_136 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40140 \ram2e_ufm/nRAS_s_i_0_o2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40141 \ram2e_ufm/un1_nDOE_i ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40140 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'h5757) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module lut40141 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hDFDF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_137 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40142 \ram2e_ufm/RDOE_i ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40084 \ram2e_ufm/LEDEN_RNI6G6M ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40142 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hA8A8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module SLICE_138 ( input C1, B1, A1, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40007 VOEEN_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40007 DOEEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module SLICE_139 ( input B1, A1, C0, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40101 nVOE_pad_RNO( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40067 S_1( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0));
|
|
|
|
specify
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_140 ( input B1, A1, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40023 \ram2e_ufm/RA_35_0_0_a3_0[2] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI),
|
|
.Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40023 \ram2e_ufm/RA_35_0_0_a3[5] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI),
|
|
.Z(F0));
|
|
|
|
specify
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_141 ( input B1, A1, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40023 \ram2e_ufm/RDout_i_0_i_a3[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI),
|
|
.Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40023 \ram2e_ufm/N_263_i ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0));
|
|
|
|
specify
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_142 ( input C1, B1, A1, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40136 \ram2e_ufm/CmdLEDGet_3_0_a3_1 ( .A(A1), .B(B1), .C(C1), .D(GNDI),
|
|
.Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40023 \ram2e_ufm/RDout_i_i_a3[4] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI),
|
|
.Z(F0));
|
|
|
|
specify
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_143 ( input B1, A1, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40023 \ram2e_ufm/RDout_i_0_i_a3[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI),
|
|
.Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40023 \ram2e_ufm/RDout_i_0_i_a3[7] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI),
|
|
.Z(F0));
|
|
|
|
specify
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_144 ( input B1, A1, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40023 \ram2e_ufm/RDout_i_0_i_a3[2] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI),
|
|
.Z(F1));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
lut40023 \ram2e_ufm/RDout_i_0_i_a3[6] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI),
|
|
.Z(F0));
|
|
|
|
specify
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_145 ( input D1, C1, B1, A1, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40033 \ram2e_ufm/wb_dati_7_0_0_0[4] ( .A(A1), .B(B1), .C(C1), .D(D1),
|
|
.Z(F1));
|
|
lut40143 \ram2e_ufm/wb_dati_7_0_0_o2_0[7] ( .A(A0), .B(B0), .C(GNDI),
|
|
.D(GNDI), .Z(F0));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40143 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hDDDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_146 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0,
|
|
F1 );
|
|
|
|
lut40144 \ram2e_ufm/RA_35_0_0_0[9] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1));
|
|
lut40035 \ram2e_ufm/Ready3_0_a3_3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(D0 => F0) = (0:0:0,0:0:0);
|
|
(C0 => F0) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module lut40144 ( input A, B, C, D, output Z );
|
|
|
|
ROM16X1A #(16'hF444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z));
|
|
endmodule
|
|
|
|
module ram2e_ufm_SLICE_147 ( input D1, C1, B1, A1, B0, A0, output F0, F1 );
|
|
wire GNDI;
|
|
|
|
lut40027 \ram2e_ufm/RWBank_3_0_0_o3[0] ( .A(A1), .B(B1), .C(C1), .D(D1),
|
|
.Z(F1));
|
|
lut40023 \ram2e_ufm/RDout_i_0_i_a3[5] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI),
|
|
.Z(F0));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(D1 => F1) = (0:0:0,0:0:0);
|
|
(C1 => F1) = (0:0:0,0:0:0);
|
|
(B1 => F1) = (0:0:0,0:0:0);
|
|
(A1 => F1) = (0:0:0,0:0:0);
|
|
(B0 => F0) = (0:0:0,0:0:0);
|
|
(A0 => F0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RD_0_ ( output PADDI, input PADDT, PADDO, inout RD0 );
|
|
|
|
xo2iobuf \RD_pad[0] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD0), .PADI(RD0));
|
|
|
|
specify
|
|
(PADDT => RD0) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
|
|
(PADDO => RD0) = (0:0:0,0:0:0);
|
|
(RD0 => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge RD0, 0:0:0);
|
|
$width (negedge RD0, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module xo2iobuf ( input I, T, output Z, PAD, input PADI );
|
|
|
|
IB INST1( .I(PADI), .O(Z));
|
|
OBW INST2( .I(I), .T(T), .O(PAD));
|
|
endmodule
|
|
|
|
module LED ( input PADDO, output LED );
|
|
|
|
xo2iobuf0145 LED_pad( .I(PADDO), .PAD(LED));
|
|
|
|
specify
|
|
(PADDO => LED) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module xo2iobuf0145 ( input I, output PAD );
|
|
|
|
OB INST5( .I(I), .O(PAD));
|
|
endmodule
|
|
|
|
module C14M ( output PADDI, input C14M );
|
|
|
|
xo2iobuf0146 C14M_pad( .Z(PADDI), .PAD(C14M));
|
|
|
|
specify
|
|
(C14M => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge C14M, 0:0:0);
|
|
$width (negedge C14M, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module xo2iobuf0146 ( output Z, input PAD );
|
|
|
|
IB INST1( .I(PAD), .O(Z));
|
|
endmodule
|
|
|
|
module RD_7_ ( output PADDI, input PADDT, PADDO, inout RD7 );
|
|
|
|
xo2iobuf \RD_pad[7] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD7), .PADI(RD7));
|
|
|
|
specify
|
|
(PADDT => RD7) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
|
|
(PADDO => RD7) = (0:0:0,0:0:0);
|
|
(RD7 => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge RD7, 0:0:0);
|
|
$width (negedge RD7, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RD_6_ ( output PADDI, input PADDT, PADDO, inout RD6 );
|
|
|
|
xo2iobuf \RD_pad[6] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD6), .PADI(RD6));
|
|
|
|
specify
|
|
(PADDT => RD6) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
|
|
(PADDO => RD6) = (0:0:0,0:0:0);
|
|
(RD6 => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge RD6, 0:0:0);
|
|
$width (negedge RD6, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RD_5_ ( output PADDI, input PADDT, PADDO, inout RD5 );
|
|
|
|
xo2iobuf \RD_pad[5] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD5), .PADI(RD5));
|
|
|
|
specify
|
|
(PADDT => RD5) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
|
|
(PADDO => RD5) = (0:0:0,0:0:0);
|
|
(RD5 => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge RD5, 0:0:0);
|
|
$width (negedge RD5, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RD_4_ ( output PADDI, input PADDT, PADDO, inout RD4 );
|
|
|
|
xo2iobuf \RD_pad[4] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD4), .PADI(RD4));
|
|
|
|
specify
|
|
(PADDT => RD4) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
|
|
(PADDO => RD4) = (0:0:0,0:0:0);
|
|
(RD4 => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge RD4, 0:0:0);
|
|
$width (negedge RD4, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RD_3_ ( output PADDI, input PADDT, PADDO, inout RD3 );
|
|
|
|
xo2iobuf \RD_pad[3] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD3), .PADI(RD3));
|
|
|
|
specify
|
|
(PADDT => RD3) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
|
|
(PADDO => RD3) = (0:0:0,0:0:0);
|
|
(RD3 => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge RD3, 0:0:0);
|
|
$width (negedge RD3, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RD_2_ ( output PADDI, input PADDT, PADDO, inout RD2 );
|
|
|
|
xo2iobuf \RD_pad[2] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD2), .PADI(RD2));
|
|
|
|
specify
|
|
(PADDT => RD2) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
|
|
(PADDO => RD2) = (0:0:0,0:0:0);
|
|
(RD2 => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge RD2, 0:0:0);
|
|
$width (negedge RD2, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RD_1_ ( output PADDI, input PADDT, PADDO, inout RD1 );
|
|
|
|
xo2iobuf \RD_pad[1] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD1), .PADI(RD1));
|
|
|
|
specify
|
|
(PADDT => RD1) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0);
|
|
(PADDO => RD1) = (0:0:0,0:0:0);
|
|
(RD1 => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge RD1, 0:0:0);
|
|
$width (negedge RD1, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module DQMH ( input IOLDO, output DQMH );
|
|
|
|
xo2iobuf0145 DQMH_pad( .I(IOLDO), .PAD(DQMH));
|
|
|
|
specify
|
|
(IOLDO => DQMH) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module DQMH_MGIOL ( output IOLDO, input OPOS, CE, CLK );
|
|
wire GNDI, OPOS_dly, CLK_dly, CE_dly;
|
|
|
|
mfflsre DQMH_0io( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI),
|
|
.Q(IOLDO));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module mfflsre ( input D0, SP, CK, LSR, output Q );
|
|
|
|
FD1P3BX INST01( .D(D0), .SP(SP), .CK(CK), .PD(LSR), .Q(Q));
|
|
defparam INST01.GSR = "DISABLED";
|
|
endmodule
|
|
|
|
module DQML ( input IOLDO, output DQML );
|
|
|
|
xo2iobuf0145 DQML_pad( .I(IOLDO), .PAD(DQML));
|
|
|
|
specify
|
|
(IOLDO => DQML) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module DQML_MGIOL ( output IOLDO, input OPOS, CE, CLK );
|
|
wire GNDI, OPOS_dly, CLK_dly, CE_dly;
|
|
|
|
mfflsre DQML_0io( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI),
|
|
.Q(IOLDO));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RAout_11_ ( input IOLDO, output RAout11 );
|
|
|
|
xo2iobuf0145 \RAout_pad[11] ( .I(IOLDO), .PAD(RAout11));
|
|
|
|
specify
|
|
(IOLDO => RAout11) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RAout_11__MGIOL ( output IOLDO, input OPOS, CLK );
|
|
wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
|
|
|
|
mfflsre0147 \RAout_0io[11] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN),
|
|
.LSR(GNDI), .Q(IOLDO));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
$setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module mfflsre0147 ( input D0, SP, CK, LSR, output Q );
|
|
|
|
FD1P3DX INST01( .D(D0), .SP(SP), .CK(CK), .CD(LSR), .Q(Q));
|
|
defparam INST01.GSR = "DISABLED";
|
|
endmodule
|
|
|
|
module inverter ( input I, output Z );
|
|
|
|
INV INST1( .A(I), .Z(Z));
|
|
endmodule
|
|
|
|
module RAout_10_ ( input IOLDO, output RAout10 );
|
|
|
|
xo2iobuf0145 \RAout_pad[10] ( .I(IOLDO), .PAD(RAout10));
|
|
|
|
specify
|
|
(IOLDO => RAout10) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RAout_10__MGIOL ( output IOLDO, input OPOS, CLK );
|
|
wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
|
|
|
|
mfflsre0147 \RAout_0io[10] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN),
|
|
.LSR(GNDI), .Q(IOLDO));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
$setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RAout_9_ ( input IOLDO, output RAout9 );
|
|
|
|
xo2iobuf0145 \RAout_pad[9] ( .I(IOLDO), .PAD(RAout9));
|
|
|
|
specify
|
|
(IOLDO => RAout9) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RAout_9__MGIOL ( output IOLDO, input OPOS, CLK );
|
|
wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
|
|
|
|
mfflsre0147 \RAout_0io[9] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN),
|
|
.LSR(GNDI), .Q(IOLDO));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
$setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RAout_8_ ( input IOLDO, output RAout8 );
|
|
|
|
xo2iobuf0145 \RAout_pad[8] ( .I(IOLDO), .PAD(RAout8));
|
|
|
|
specify
|
|
(IOLDO => RAout8) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RAout_8__MGIOL ( output IOLDO, input OPOS, CLK );
|
|
wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
|
|
|
|
mfflsre0147 \RAout_0io[8] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN),
|
|
.LSR(GNDI), .Q(IOLDO));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
$setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RAout_7_ ( input IOLDO, output RAout7 );
|
|
|
|
xo2iobuf0145 \RAout_pad[7] ( .I(IOLDO), .PAD(RAout7));
|
|
|
|
specify
|
|
(IOLDO => RAout7) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RAout_7__MGIOL ( output IOLDO, input OPOS, CLK );
|
|
wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
|
|
|
|
mfflsre0147 \RAout_0io[7] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN),
|
|
.LSR(GNDI), .Q(IOLDO));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
$setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RAout_6_ ( input IOLDO, output RAout6 );
|
|
|
|
xo2iobuf0145 \RAout_pad[6] ( .I(IOLDO), .PAD(RAout6));
|
|
|
|
specify
|
|
(IOLDO => RAout6) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RAout_6__MGIOL ( output IOLDO, input OPOS, CLK );
|
|
wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
|
|
|
|
mfflsre0147 \RAout_0io[6] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN),
|
|
.LSR(GNDI), .Q(IOLDO));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
$setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RAout_5_ ( input IOLDO, output RAout5 );
|
|
|
|
xo2iobuf0145 \RAout_pad[5] ( .I(IOLDO), .PAD(RAout5));
|
|
|
|
specify
|
|
(IOLDO => RAout5) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RAout_5__MGIOL ( output IOLDO, input OPOS, CLK );
|
|
wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
|
|
|
|
mfflsre0147 \RAout_0io[5] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN),
|
|
.LSR(GNDI), .Q(IOLDO));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
$setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RAout_4_ ( input IOLDO, output RAout4 );
|
|
|
|
xo2iobuf0145 \RAout_pad[4] ( .I(IOLDO), .PAD(RAout4));
|
|
|
|
specify
|
|
(IOLDO => RAout4) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RAout_4__MGIOL ( output IOLDO, input OPOS, CLK );
|
|
wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
|
|
|
|
mfflsre0147 \RAout_0io[4] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN),
|
|
.LSR(GNDI), .Q(IOLDO));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
$setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RAout_3_ ( input IOLDO, output RAout3 );
|
|
|
|
xo2iobuf0145 \RAout_pad[3] ( .I(IOLDO), .PAD(RAout3));
|
|
|
|
specify
|
|
(IOLDO => RAout3) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RAout_3__MGIOL ( output IOLDO, input OPOS, CLK );
|
|
wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
|
|
|
|
mfflsre0147 \RAout_0io[3] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN),
|
|
.LSR(GNDI), .Q(IOLDO));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
$setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RAout_2_ ( input IOLDO, output RAout2 );
|
|
|
|
xo2iobuf0145 \RAout_pad[2] ( .I(IOLDO), .PAD(RAout2));
|
|
|
|
specify
|
|
(IOLDO => RAout2) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RAout_2__MGIOL ( output IOLDO, input OPOS, CLK );
|
|
wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
|
|
|
|
mfflsre0147 \RAout_0io[2] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN),
|
|
.LSR(GNDI), .Q(IOLDO));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
$setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RAout_1_ ( input IOLDO, output RAout1 );
|
|
|
|
xo2iobuf0145 \RAout_pad[1] ( .I(IOLDO), .PAD(RAout1));
|
|
|
|
specify
|
|
(IOLDO => RAout1) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RAout_1__MGIOL ( output IOLDO, input OPOS, CLK );
|
|
wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
|
|
|
|
mfflsre0147 \RAout_0io[1] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN),
|
|
.LSR(GNDI), .Q(IOLDO));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
$setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RAout_0_ ( input IOLDO, output RAout0 );
|
|
|
|
xo2iobuf0145 \RAout_pad[0] ( .I(IOLDO), .PAD(RAout0));
|
|
|
|
specify
|
|
(IOLDO => RAout0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module RAout_0__MGIOL ( output IOLDO, input OPOS, CLK );
|
|
wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
|
|
|
|
mfflsre0147 \RAout_0io[0] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN),
|
|
.LSR(GNDI), .Q(IOLDO));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
$setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module BA_1_ ( input IOLDO, output BA1 );
|
|
|
|
xo2iobuf0145 \BA_pad[1] ( .I(IOLDO), .PAD(BA1));
|
|
|
|
specify
|
|
(IOLDO => BA1) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module BA_1__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK );
|
|
wire OPOS_dly, CLK_dly, CE_dly, LSR_dly;
|
|
|
|
mfflsre0148 \BA_0io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly),
|
|
.LSR(LSR_dly), .Q(IOLDO));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module mfflsre0148 ( input D0, SP, CK, LSR, output Q );
|
|
|
|
FD1P3IX INST01( .D(D0), .SP(SP), .CK(CK), .CD(LSR), .Q(Q));
|
|
defparam INST01.GSR = "DISABLED";
|
|
endmodule
|
|
|
|
module BA_0_ ( input IOLDO, output BA0 );
|
|
|
|
xo2iobuf0145 \BA_pad[0] ( .I(IOLDO), .PAD(BA0));
|
|
|
|
specify
|
|
(IOLDO => BA0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module BA_0__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK );
|
|
wire OPOS_dly, CLK_dly, CE_dly, LSR_dly;
|
|
|
|
mfflsre0148 \BA_0io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly),
|
|
.LSR(LSR_dly), .Q(IOLDO));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module nRWEout ( input IOLDO, output nRWEout );
|
|
|
|
xo2iobuf0145 nRWEout_pad( .I(IOLDO), .PAD(nRWEout));
|
|
|
|
specify
|
|
(IOLDO => nRWEout) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module nRWEout_MGIOL ( output IOLDO, input OPOS, CLK );
|
|
wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
|
|
|
|
mfflsre nRWEout_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI),
|
|
.Q(IOLDO));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
$setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module nCASout ( input IOLDO, output nCASout );
|
|
|
|
xo2iobuf0145 nCASout_pad( .I(IOLDO), .PAD(nCASout));
|
|
|
|
specify
|
|
(IOLDO => nCASout) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module nCASout_MGIOL ( output IOLDO, input OPOS, CLK );
|
|
wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
|
|
|
|
mfflsre nCASout_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI),
|
|
.Q(IOLDO));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
$setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module nRASout ( input IOLDO, output nRASout );
|
|
|
|
xo2iobuf0145 nRASout_pad( .I(IOLDO), .PAD(nRASout));
|
|
|
|
specify
|
|
(IOLDO => nRASout) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module nRASout_MGIOL ( output IOLDO, input OPOS, CLK );
|
|
wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
|
|
|
|
mfflsre nRASout_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI),
|
|
.Q(IOLDO));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
$setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module nCSout ( input PADDO, output nCSout );
|
|
|
|
xo2iobuf0145 nCSout_pad( .I(PADDO), .PAD(nCSout));
|
|
|
|
specify
|
|
(PADDO => nCSout) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module CKEout ( input IOLDO, output CKEout );
|
|
|
|
xo2iobuf0145 CKEout_pad( .I(IOLDO), .PAD(CKEout));
|
|
|
|
specify
|
|
(IOLDO => CKEout) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module CKEout_MGIOL ( output IOLDO, input OPOS, CLK );
|
|
wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly;
|
|
|
|
mfflsre0147 CKEout_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI),
|
|
.Q(IOLDO));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
$setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module nVOE ( input PADDO, output nVOE );
|
|
|
|
xo2iobuf0145 nVOE_pad( .I(PADDO), .PAD(nVOE));
|
|
|
|
specify
|
|
(PADDO => nVOE) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Vout_7_ ( input IOLDO, output Vout7 );
|
|
|
|
xo2iobuf0145 \Vout_pad[7] ( .I(IOLDO), .PAD(Vout7));
|
|
|
|
specify
|
|
(IOLDO => Vout7) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Vout_7__MGIOL ( output IOLDO, input OPOS, CE, CLK );
|
|
wire GNDI, OPOS_dly, CLK_dly, CE_dly;
|
|
|
|
mfflsre0147 \Vout_0io[7] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly),
|
|
.LSR(GNDI), .Q(IOLDO));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Vout_6_ ( input IOLDO, output Vout6 );
|
|
|
|
xo2iobuf0145 \Vout_pad[6] ( .I(IOLDO), .PAD(Vout6));
|
|
|
|
specify
|
|
(IOLDO => Vout6) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Vout_6__MGIOL ( output IOLDO, input OPOS, CE, CLK );
|
|
wire GNDI, OPOS_dly, CLK_dly, CE_dly;
|
|
|
|
mfflsre0147 \Vout_0io[6] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly),
|
|
.LSR(GNDI), .Q(IOLDO));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Vout_5_ ( input IOLDO, output Vout5 );
|
|
|
|
xo2iobuf0145 \Vout_pad[5] ( .I(IOLDO), .PAD(Vout5));
|
|
|
|
specify
|
|
(IOLDO => Vout5) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Vout_5__MGIOL ( output IOLDO, input OPOS, CE, CLK );
|
|
wire GNDI, OPOS_dly, CLK_dly, CE_dly;
|
|
|
|
mfflsre0147 \Vout_0io[5] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly),
|
|
.LSR(GNDI), .Q(IOLDO));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Vout_4_ ( input IOLDO, output Vout4 );
|
|
|
|
xo2iobuf0145 \Vout_pad[4] ( .I(IOLDO), .PAD(Vout4));
|
|
|
|
specify
|
|
(IOLDO => Vout4) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Vout_4__MGIOL ( output IOLDO, input OPOS, CE, CLK );
|
|
wire GNDI, OPOS_dly, CLK_dly, CE_dly;
|
|
|
|
mfflsre0147 \Vout_0io[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly),
|
|
.LSR(GNDI), .Q(IOLDO));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Vout_3_ ( input IOLDO, output Vout3 );
|
|
|
|
xo2iobuf0145 \Vout_pad[3] ( .I(IOLDO), .PAD(Vout3));
|
|
|
|
specify
|
|
(IOLDO => Vout3) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Vout_3__MGIOL ( output IOLDO, input OPOS, CE, CLK );
|
|
wire GNDI, OPOS_dly, CLK_dly, CE_dly;
|
|
|
|
mfflsre0147 \Vout_0io[3] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly),
|
|
.LSR(GNDI), .Q(IOLDO));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Vout_2_ ( input IOLDO, output Vout2 );
|
|
|
|
xo2iobuf0145 \Vout_pad[2] ( .I(IOLDO), .PAD(Vout2));
|
|
|
|
specify
|
|
(IOLDO => Vout2) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Vout_2__MGIOL ( output IOLDO, input OPOS, CE, CLK );
|
|
wire GNDI, OPOS_dly, CLK_dly, CE_dly;
|
|
|
|
mfflsre0147 \Vout_0io[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly),
|
|
.LSR(GNDI), .Q(IOLDO));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Vout_1_ ( input IOLDO, output Vout1 );
|
|
|
|
xo2iobuf0145 \Vout_pad[1] ( .I(IOLDO), .PAD(Vout1));
|
|
|
|
specify
|
|
(IOLDO => Vout1) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Vout_1__MGIOL ( output IOLDO, input OPOS, CE, CLK );
|
|
wire GNDI, OPOS_dly, CLK_dly, CE_dly;
|
|
|
|
mfflsre0147 \Vout_0io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly),
|
|
.LSR(GNDI), .Q(IOLDO));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Vout_0_ ( input IOLDO, output Vout0 );
|
|
|
|
xo2iobuf0145 \Vout_pad[0] ( .I(IOLDO), .PAD(Vout0));
|
|
|
|
specify
|
|
(IOLDO => Vout0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Vout_0__MGIOL ( output IOLDO, input OPOS, CE, CLK );
|
|
wire GNDI, OPOS_dly, CLK_dly, CE_dly;
|
|
|
|
mfflsre0147 \Vout_0io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly),
|
|
.LSR(GNDI), .Q(IOLDO));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IOLDO) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly);
|
|
$setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module nDOE ( input PADDO, output nDOE );
|
|
|
|
xo2iobuf0145 nDOE_pad( .I(PADDO), .PAD(nDOE));
|
|
|
|
specify
|
|
(PADDO => nDOE) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Dout_7_ ( input PADDO, output Dout7 );
|
|
|
|
xo2iobuf0145 \Dout_pad[7] ( .I(PADDO), .PAD(Dout7));
|
|
|
|
specify
|
|
(PADDO => Dout7) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Dout_6_ ( input PADDO, output Dout6 );
|
|
|
|
xo2iobuf0145 \Dout_pad[6] ( .I(PADDO), .PAD(Dout6));
|
|
|
|
specify
|
|
(PADDO => Dout6) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Dout_5_ ( input PADDO, output Dout5 );
|
|
|
|
xo2iobuf0145 \Dout_pad[5] ( .I(PADDO), .PAD(Dout5));
|
|
|
|
specify
|
|
(PADDO => Dout5) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Dout_4_ ( input PADDO, output Dout4 );
|
|
|
|
xo2iobuf0145 \Dout_pad[4] ( .I(PADDO), .PAD(Dout4));
|
|
|
|
specify
|
|
(PADDO => Dout4) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Dout_3_ ( input PADDO, output Dout3 );
|
|
|
|
xo2iobuf0145 \Dout_pad[3] ( .I(PADDO), .PAD(Dout3));
|
|
|
|
specify
|
|
(PADDO => Dout3) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Dout_2_ ( input PADDO, output Dout2 );
|
|
|
|
xo2iobuf0145 \Dout_pad[2] ( .I(PADDO), .PAD(Dout2));
|
|
|
|
specify
|
|
(PADDO => Dout2) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Dout_1_ ( input PADDO, output Dout1 );
|
|
|
|
xo2iobuf0145 \Dout_pad[1] ( .I(PADDO), .PAD(Dout1));
|
|
|
|
specify
|
|
(PADDO => Dout1) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Dout_0_ ( input PADDO, output Dout0 );
|
|
|
|
xo2iobuf0145 \Dout_pad[0] ( .I(PADDO), .PAD(Dout0));
|
|
|
|
specify
|
|
(PADDO => Dout0) = (0:0:0,0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Din_7_ ( output PADDI, input Din7 );
|
|
|
|
xo2iobuf0146 \Din_pad[7] ( .Z(PADDI), .PAD(Din7));
|
|
|
|
specify
|
|
(Din7 => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge Din7, 0:0:0);
|
|
$width (negedge Din7, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Din_6_ ( output PADDI, input Din6 );
|
|
|
|
xo2iobuf0146 \Din_pad[6] ( .Z(PADDI), .PAD(Din6));
|
|
|
|
specify
|
|
(Din6 => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge Din6, 0:0:0);
|
|
$width (negedge Din6, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Din_5_ ( output PADDI, input Din5 );
|
|
|
|
xo2iobuf0146 \Din_pad[5] ( .Z(PADDI), .PAD(Din5));
|
|
|
|
specify
|
|
(Din5 => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge Din5, 0:0:0);
|
|
$width (negedge Din5, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Din_4_ ( output PADDI, input Din4 );
|
|
|
|
xo2iobuf0146 \Din_pad[4] ( .Z(PADDI), .PAD(Din4));
|
|
|
|
specify
|
|
(Din4 => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge Din4, 0:0:0);
|
|
$width (negedge Din4, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Din_3_ ( output PADDI, input Din3 );
|
|
|
|
xo2iobuf0146 \Din_pad[3] ( .Z(PADDI), .PAD(Din3));
|
|
|
|
specify
|
|
(Din3 => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge Din3, 0:0:0);
|
|
$width (negedge Din3, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Din_2_ ( output PADDI, input Din2 );
|
|
|
|
xo2iobuf0146 \Din_pad[2] ( .Z(PADDI), .PAD(Din2));
|
|
|
|
specify
|
|
(Din2 => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge Din2, 0:0:0);
|
|
$width (negedge Din2, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Din_1_ ( output PADDI, input Din1 );
|
|
|
|
xo2iobuf0146 \Din_pad[1] ( .Z(PADDI), .PAD(Din1));
|
|
|
|
specify
|
|
(Din1 => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge Din1, 0:0:0);
|
|
$width (negedge Din1, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Din_0_ ( output PADDI, input Din0 );
|
|
|
|
xo2iobuf0146 \Din_pad[0] ( .Z(PADDI), .PAD(Din0));
|
|
|
|
specify
|
|
(Din0 => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge Din0, 0:0:0);
|
|
$width (negedge Din0, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Ain_7_ ( output PADDI, input Ain7 );
|
|
|
|
xo2iobuf0146 \Ain_pad[7] ( .Z(PADDI), .PAD(Ain7));
|
|
|
|
specify
|
|
(Ain7 => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge Ain7, 0:0:0);
|
|
$width (negedge Ain7, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Ain_6_ ( output PADDI, input Ain6 );
|
|
|
|
xo2iobuf0146 \Ain_pad[6] ( .Z(PADDI), .PAD(Ain6));
|
|
|
|
specify
|
|
(Ain6 => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge Ain6, 0:0:0);
|
|
$width (negedge Ain6, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Ain_5_ ( output PADDI, input Ain5 );
|
|
|
|
xo2iobuf0146 \Ain_pad[5] ( .Z(PADDI), .PAD(Ain5));
|
|
|
|
specify
|
|
(Ain5 => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge Ain5, 0:0:0);
|
|
$width (negedge Ain5, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Ain_4_ ( output PADDI, input Ain4 );
|
|
|
|
xo2iobuf0146 \Ain_pad[4] ( .Z(PADDI), .PAD(Ain4));
|
|
|
|
specify
|
|
(Ain4 => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge Ain4, 0:0:0);
|
|
$width (negedge Ain4, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Ain_3_ ( output PADDI, input Ain3 );
|
|
|
|
xo2iobuf0146 \Ain_pad[3] ( .Z(PADDI), .PAD(Ain3));
|
|
|
|
specify
|
|
(Ain3 => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge Ain3, 0:0:0);
|
|
$width (negedge Ain3, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Ain_2_ ( output PADDI, input Ain2 );
|
|
|
|
xo2iobuf0146 \Ain_pad[2] ( .Z(PADDI), .PAD(Ain2));
|
|
|
|
specify
|
|
(Ain2 => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge Ain2, 0:0:0);
|
|
$width (negedge Ain2, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Ain_1_ ( output PADDI, input Ain1 );
|
|
|
|
xo2iobuf0146 \Ain_pad[1] ( .Z(PADDI), .PAD(Ain1));
|
|
|
|
specify
|
|
(Ain1 => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge Ain1, 0:0:0);
|
|
$width (negedge Ain1, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module Ain_0_ ( output PADDI, input Ain0 );
|
|
|
|
xo2iobuf0146 \Ain_pad[0] ( .Z(PADDI), .PAD(Ain0));
|
|
|
|
specify
|
|
(Ain0 => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge Ain0, 0:0:0);
|
|
$width (negedge Ain0, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module nC07X ( output PADDI, input nC07X );
|
|
|
|
xo2iobuf0146 nC07X_pad( .Z(PADDI), .PAD(nC07X));
|
|
|
|
specify
|
|
(nC07X => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge nC07X, 0:0:0);
|
|
$width (negedge nC07X, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module nEN80 ( output PADDI, input nEN80 );
|
|
|
|
xo2iobuf0146 nEN80_pad( .Z(PADDI), .PAD(nEN80));
|
|
|
|
specify
|
|
(nEN80 => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge nEN80, 0:0:0);
|
|
$width (negedge nEN80, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module nWE ( output PADDI, input nWE );
|
|
|
|
xo2iobuf0146 nWE_pad( .Z(PADDI), .PAD(nWE));
|
|
|
|
specify
|
|
(nWE => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge nWE, 0:0:0);
|
|
$width (negedge nWE, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module PHI1 ( output PADDI, input PHI1 );
|
|
|
|
xo2iobuf0146 PHI1_pad( .Z(PADDI), .PAD(PHI1));
|
|
|
|
specify
|
|
(PHI1 => PADDI) = (0:0:0,0:0:0);
|
|
$width (posedge PHI1, 0:0:0);
|
|
$width (negedge PHI1, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module PHI1_MGIOL ( input DI, CLK, output IN );
|
|
wire VCCI, GNDI, DI_dly, CLK_dly;
|
|
|
|
smuxlregsre PHI1r_0io( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI),
|
|
.Q(IN));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
|
|
specify
|
|
(CLK => IN) = (0:0:0,0:0:0);
|
|
$setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly);
|
|
$width (posedge CLK, 0:0:0);
|
|
$width (negedge CLK, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|
|
|
|
module smuxlregsre ( input D0, SP, CK, LSR, output Q );
|
|
|
|
IFS1P3DX INST01( .D(D0), .SP(SP), .SCLK(CK), .CD(LSR), .Q(Q));
|
|
defparam INST01.GSR = "DISABLED";
|
|
endmodule
|
|
|
|
module ram2e_ufm_ufmefb_EFBInst_0 ( input WBCLKI, WBRSTI, WBCYCI, WBSTBI,
|
|
WBWEI, WBADRI0, WBADRI1, WBADRI2, WBADRI3, WBADRI4, WBADRI5, WBADRI6,
|
|
WBADRI7, WBDATI0, WBDATI1, WBDATI2, WBDATI3, WBDATI4, WBDATI5, WBDATI6,
|
|
WBDATI7, output WBDATO0, WBDATO1, WBDATO2, WBDATO3, WBDATO4, WBDATO5,
|
|
WBDATO6, WBDATO7, WBACKO );
|
|
wire VCCI, GNDI;
|
|
|
|
EFB_B \ram2e_ufm/ufmefb/EFBInst_0_EFB ( .WBCLKI(WBCLKI), .WBRSTI(WBRSTI),
|
|
.WBCYCI(WBCYCI), .WBSTBI(WBSTBI), .WBWEI(WBWEI), .WBADRI0(WBADRI0),
|
|
.WBADRI1(WBADRI1), .WBADRI2(WBADRI2), .WBADRI3(WBADRI3), .WBADRI4(WBADRI4),
|
|
.WBADRI5(WBADRI5), .WBADRI6(WBADRI6), .WBADRI7(WBADRI7), .WBDATI0(WBDATI0),
|
|
.WBDATI1(WBDATI1), .WBDATI2(WBDATI2), .WBDATI3(WBDATI3), .WBDATI4(WBDATI4),
|
|
.WBDATI5(WBDATI5), .WBDATI6(WBDATI6), .WBDATI7(WBDATI7), .WBDATO0(WBDATO0),
|
|
.WBDATO1(WBDATO1), .WBDATO2(WBDATO2), .WBDATO3(WBDATO3), .WBDATO4(WBDATO4),
|
|
.WBDATO5(WBDATO5), .WBDATO6(WBDATO6), .WBDATO7(WBDATO7), .WBACKO(WBACKO),
|
|
.WBCUFMIRQ(), .UFMSN(VCCI), .CFGWAKE(), .CFGSTDBY(), .I2C1SCLI(GNDI),
|
|
.I2C1SCLO(), .I2C1SCLOEN(), .I2C1SDAI(GNDI), .I2C1SDAO(), .I2C1SDAOEN(),
|
|
.I2C2SCLI(GNDI), .I2C2SCLO(), .I2C2SCLOEN(), .I2C2SDAI(GNDI), .I2C2SDAO(),
|
|
.I2C2SDAOEN(), .I2C1IRQO(), .I2C2IRQO(), .SPISCKI(GNDI), .SPISCKO(),
|
|
.SPISCKEN(), .SPIMISOI(GNDI), .SPIMISOO(), .SPIMISOEN(), .SPIMOSII(GNDI),
|
|
.SPIMOSIO(), .SPIMOSIEN(), .SPIMCSN0(), .SPIMCSN1(), .SPIMCSN2(),
|
|
.SPIMCSN3(), .SPIMCSN4(), .SPIMCSN5(), .SPIMCSN6(), .SPIMCSN7(),
|
|
.SPICSNEN(), .SPISCSN(GNDI), .SPIIRQO(), .TCCLKI(GNDI), .TCRSTN(GNDI),
|
|
.TCIC(GNDI), .TCINT(), .TCOC(), .PLLCLKO(), .PLLRSTO(), .PLL0STBO(),
|
|
.PLL1STBO(), .PLLWEO(), .PLLADRO0(), .PLLADRO1(), .PLLADRO2(), .PLLADRO3(),
|
|
.PLLADRO4(), .PLLDATO0(), .PLLDATO1(), .PLLDATO2(), .PLLDATO3(),
|
|
.PLLDATO4(), .PLLDATO5(), .PLLDATO6(), .PLLDATO7(), .PLL0DATI0(GNDI),
|
|
.PLL0DATI1(GNDI), .PLL0DATI2(GNDI), .PLL0DATI3(GNDI), .PLL0DATI4(GNDI),
|
|
.PLL0DATI5(GNDI), .PLL0DATI6(GNDI), .PLL0DATI7(GNDI), .PLL0ACKI(GNDI),
|
|
.PLL1DATI0(GNDI), .PLL1DATI1(GNDI), .PLL1DATI2(GNDI), .PLL1DATI3(GNDI),
|
|
.PLL1DATI4(GNDI), .PLL1DATI5(GNDI), .PLL1DATI6(GNDI), .PLL1DATI7(GNDI),
|
|
.PLL1ACKI(GNDI));
|
|
vcc DRIVEVCC( .PWR1(VCCI));
|
|
gnd DRIVEGND( .PWR0(GNDI));
|
|
endmodule
|
|
|
|
module EFB_B ( input WBCLKI, WBRSTI, WBCYCI, WBSTBI, WBWEI, WBADRI0, WBADRI1,
|
|
WBADRI2, WBADRI3, WBADRI4, WBADRI5, WBADRI6, WBADRI7, WBDATI0, WBDATI1,
|
|
WBDATI2, WBDATI3, WBDATI4, WBDATI5, WBDATI6, WBDATI7, output WBDATO0,
|
|
WBDATO1, WBDATO2, WBDATO3, WBDATO4, WBDATO5, WBDATO6, WBDATO7, WBACKO,
|
|
WBCUFMIRQ, input UFMSN, output CFGWAKE, CFGSTDBY, input I2C1SCLI, output
|
|
I2C1SCLO, I2C1SCLOEN, input I2C1SDAI, output I2C1SDAO, I2C1SDAOEN, input
|
|
I2C2SCLI, output I2C2SCLO, I2C2SCLOEN, input I2C2SDAI, output I2C2SDAO,
|
|
I2C2SDAOEN, I2C1IRQO, I2C2IRQO, input SPISCKI, output SPISCKO, SPISCKEN,
|
|
input SPIMISOI, output SPIMISOO, SPIMISOEN, input SPIMOSII, output
|
|
SPIMOSIO, SPIMOSIEN, SPIMCSN0, SPIMCSN1, SPIMCSN2, SPIMCSN3, SPIMCSN4,
|
|
SPIMCSN5, SPIMCSN6, SPIMCSN7, SPICSNEN, input SPISCSN, output SPIIRQO,
|
|
input TCCLKI, TCRSTN, TCIC, output TCINT, TCOC, PLLCLKO, PLLRSTO, PLL0STBO,
|
|
PLL1STBO, PLLWEO, PLLADRO0, PLLADRO1, PLLADRO2, PLLADRO3, PLLADRO4,
|
|
PLLDATO0, PLLDATO1, PLLDATO2, PLLDATO3, PLLDATO4, PLLDATO5, PLLDATO6,
|
|
PLLDATO7, input PLL0DATI0, PLL0DATI1, PLL0DATI2, PLL0DATI3, PLL0DATI4,
|
|
PLL0DATI5, PLL0DATI6, PLL0DATI7, PLL0ACKI, PLL1DATI0, PLL1DATI1, PLL1DATI2,
|
|
PLL1DATI3, PLL1DATI4, PLL1DATI5, PLL1DATI6, PLL1DATI7, PLL1ACKI );
|
|
wire WBCLKI_buf, WBRSTI_buf, WBCYCI_buf, WBSTBI_buf, WBWEI_buf,
|
|
WBADRI7_buf, WBADRI6_buf, WBADRI5_buf, WBADRI4_buf, WBADRI3_buf,
|
|
WBADRI2_buf, WBADRI1_buf, WBADRI0_buf, WBDATI7_buf, WBDATI6_buf,
|
|
WBDATI5_buf, WBDATI4_buf, WBDATI3_buf, WBDATI2_buf, WBDATI1_buf,
|
|
WBDATI0_buf, PLL0DATI7_buf, PLL0DATI6_buf, PLL0DATI5_buf,
|
|
PLL0DATI4_buf, PLL0DATI3_buf, PLL0DATI2_buf, PLL0DATI1_buf,
|
|
PLL0DATI0_buf, PLL0ACKI_buf, PLL1DATI7_buf, PLL1DATI6_buf,
|
|
PLL1DATI5_buf, PLL1DATI4_buf, PLL1DATI3_buf, PLL1DATI2_buf,
|
|
PLL1DATI1_buf, PLL1DATI0_buf, PLL1ACKI_buf, I2C1SCLI_buf,
|
|
I2C1SDAI_buf, I2C2SCLI_buf, I2C2SDAI_buf, SPISCKI_buf, SPIMISOI_buf,
|
|
SPIMOSII_buf, SPISCSN_buf, TCCLKI_buf, TCRSTN_buf, TCIC_buf,
|
|
UFMSN_buf, WBDATO7_buf, WBDATO6_buf, WBDATO5_buf, WBDATO4_buf,
|
|
WBDATO3_buf, WBDATO2_buf, WBDATO1_buf, WBDATO0_buf, WBACKO_buf,
|
|
PLLCLKO_buf, PLLRSTO_buf, PLL0STBO_buf, PLL1STBO_buf, PLLWEO_buf,
|
|
PLLADRO4_buf, PLLADRO3_buf, PLLADRO2_buf, PLLADRO1_buf, PLLADRO0_buf,
|
|
PLLDATO7_buf, PLLDATO6_buf, PLLDATO5_buf, PLLDATO4_buf, PLLDATO3_buf,
|
|
PLLDATO2_buf, PLLDATO1_buf, PLLDATO0_buf, I2C1SCLO_buf,
|
|
I2C1SCLOEN_buf, I2C1SDAO_buf, I2C1SDAOEN_buf, I2C2SCLO_buf,
|
|
I2C2SCLOEN_buf, I2C2SDAO_buf, I2C2SDAOEN_buf, I2C1IRQO_buf,
|
|
I2C2IRQO_buf, SPISCKO_buf, SPISCKEN_buf, SPIMISOO_buf, SPIMISOEN_buf,
|
|
SPIMOSIO_buf, SPIMOSIEN_buf, SPIMCSN0_buf, SPIMCSN1_buf, SPIMCSN2_buf,
|
|
SPIMCSN3_buf, SPIMCSN4_buf, SPIMCSN5_buf, SPIMCSN6_buf, SPIMCSN7_buf,
|
|
SPICSNEN_buf, SPIIRQO_buf, TCINT_buf, TCOC_buf, WBCUFMIRQ_buf,
|
|
CFGWAKE_buf, CFGSTDBY_buf;
|
|
|
|
EFB INST10( .WBCLKI(WBCLKI_buf), .WBRSTI(WBRSTI_buf), .WBCYCI(WBCYCI_buf),
|
|
.WBSTBI(WBSTBI_buf), .WBWEI(WBWEI_buf), .WBADRI7(WBADRI7_buf),
|
|
.WBADRI6(WBADRI6_buf), .WBADRI5(WBADRI5_buf), .WBADRI4(WBADRI4_buf),
|
|
.WBADRI3(WBADRI3_buf), .WBADRI2(WBADRI2_buf), .WBADRI1(WBADRI1_buf),
|
|
.WBADRI0(WBADRI0_buf), .WBDATI7(WBDATI7_buf), .WBDATI6(WBDATI6_buf),
|
|
.WBDATI5(WBDATI5_buf), .WBDATI4(WBDATI4_buf), .WBDATI3(WBDATI3_buf),
|
|
.WBDATI2(WBDATI2_buf), .WBDATI1(WBDATI1_buf), .WBDATI0(WBDATI0_buf),
|
|
.PLL0DATI7(PLL0DATI7_buf), .PLL0DATI6(PLL0DATI6_buf),
|
|
.PLL0DATI5(PLL0DATI5_buf), .PLL0DATI4(PLL0DATI4_buf),
|
|
.PLL0DATI3(PLL0DATI3_buf), .PLL0DATI2(PLL0DATI2_buf),
|
|
.PLL0DATI1(PLL0DATI1_buf), .PLL0DATI0(PLL0DATI0_buf),
|
|
.PLL0ACKI(PLL0ACKI_buf), .PLL1DATI7(PLL1DATI7_buf),
|
|
.PLL1DATI6(PLL1DATI6_buf), .PLL1DATI5(PLL1DATI5_buf),
|
|
.PLL1DATI4(PLL1DATI4_buf), .PLL1DATI3(PLL1DATI3_buf),
|
|
.PLL1DATI2(PLL1DATI2_buf), .PLL1DATI1(PLL1DATI1_buf),
|
|
.PLL1DATI0(PLL1DATI0_buf), .PLL1ACKI(PLL1ACKI_buf),
|
|
.I2C1SCLI(I2C1SCLI_buf), .I2C1SDAI(I2C1SDAI_buf), .I2C2SCLI(I2C2SCLI_buf),
|
|
.I2C2SDAI(I2C2SDAI_buf), .SPISCKI(SPISCKI_buf), .SPIMISOI(SPIMISOI_buf),
|
|
.SPIMOSII(SPIMOSII_buf), .SPISCSN(SPISCSN_buf), .TCCLKI(TCCLKI_buf),
|
|
.TCRSTN(TCRSTN_buf), .TCIC(TCIC_buf), .UFMSN(UFMSN_buf),
|
|
.WBDATO7(WBDATO7_buf), .WBDATO6(WBDATO6_buf), .WBDATO5(WBDATO5_buf),
|
|
.WBDATO4(WBDATO4_buf), .WBDATO3(WBDATO3_buf), .WBDATO2(WBDATO2_buf),
|
|
.WBDATO1(WBDATO1_buf), .WBDATO0(WBDATO0_buf), .WBACKO(WBACKO_buf),
|
|
.PLLCLKO(PLLCLKO_buf), .PLLRSTO(PLLRSTO_buf), .PLL0STBO(PLL0STBO_buf),
|
|
.PLL1STBO(PLL1STBO_buf), .PLLWEO(PLLWEO_buf), .PLLADRO4(PLLADRO4_buf),
|
|
.PLLADRO3(PLLADRO3_buf), .PLLADRO2(PLLADRO2_buf), .PLLADRO1(PLLADRO1_buf),
|
|
.PLLADRO0(PLLADRO0_buf), .PLLDATO7(PLLDATO7_buf), .PLLDATO6(PLLDATO6_buf),
|
|
.PLLDATO5(PLLDATO5_buf), .PLLDATO4(PLLDATO4_buf), .PLLDATO3(PLLDATO3_buf),
|
|
.PLLDATO2(PLLDATO2_buf), .PLLDATO1(PLLDATO1_buf), .PLLDATO0(PLLDATO0_buf),
|
|
.I2C1SCLO(I2C1SCLO_buf), .I2C1SCLOEN(I2C1SCLOEN_buf),
|
|
.I2C1SDAO(I2C1SDAO_buf), .I2C1SDAOEN(I2C1SDAOEN_buf),
|
|
.I2C2SCLO(I2C2SCLO_buf), .I2C2SCLOEN(I2C2SCLOEN_buf),
|
|
.I2C2SDAO(I2C2SDAO_buf), .I2C2SDAOEN(I2C2SDAOEN_buf),
|
|
.I2C1IRQO(I2C1IRQO_buf), .I2C2IRQO(I2C2IRQO_buf), .SPISCKO(SPISCKO_buf),
|
|
.SPISCKEN(SPISCKEN_buf), .SPIMISOO(SPIMISOO_buf),
|
|
.SPIMISOEN(SPIMISOEN_buf), .SPIMOSIO(SPIMOSIO_buf),
|
|
.SPIMOSIEN(SPIMOSIEN_buf), .SPIMCSN0(SPIMCSN0_buf),
|
|
.SPIMCSN1(SPIMCSN1_buf), .SPIMCSN2(SPIMCSN2_buf), .SPIMCSN3(SPIMCSN3_buf),
|
|
.SPIMCSN4(SPIMCSN4_buf), .SPIMCSN5(SPIMCSN5_buf), .SPIMCSN6(SPIMCSN6_buf),
|
|
.SPIMCSN7(SPIMCSN7_buf), .SPICSNEN(SPICSNEN_buf), .SPIIRQO(SPIIRQO_buf),
|
|
.TCINT(TCINT_buf), .TCOC(TCOC_buf), .WBCUFMIRQ(WBCUFMIRQ_buf),
|
|
.CFGWAKE(CFGWAKE_buf), .CFGSTDBY(CFGSTDBY_buf));
|
|
defparam INST10.DEV_DENSITY = "640L";
|
|
defparam INST10.EFB_I2C1 = "DISABLED";
|
|
defparam INST10.EFB_I2C2 = "DISABLED";
|
|
defparam INST10.EFB_SPI = "DISABLED";
|
|
defparam INST10.EFB_TC = "DISABLED";
|
|
defparam INST10.EFB_TC_PORTMODE = "WB";
|
|
defparam INST10.EFB_UFM = "ENABLED";
|
|
defparam INST10.EFB_WB_CLK_FREQ = "14.4";
|
|
defparam INST10.GSR = "ENABLED";
|
|
defparam INST10.I2C1_ADDRESSING = "7BIT";
|
|
defparam INST10.I2C1_BUS_PERF = "100kHz";
|
|
defparam INST10.I2C1_CLK_DIVIDER = 1;
|
|
defparam INST10.I2C1_GEN_CALL = "DISABLED";
|
|
defparam INST10.I2C1_SLAVE_ADDR = "0b1000001";
|
|
defparam INST10.I2C1_WAKEUP = "DISABLED";
|
|
defparam INST10.I2C2_ADDRESSING = "7BIT";
|
|
defparam INST10.I2C2_BUS_PERF = "100kHz";
|
|
defparam INST10.I2C2_CLK_DIVIDER = 1;
|
|
defparam INST10.I2C2_GEN_CALL = "DISABLED";
|
|
defparam INST10.I2C2_SLAVE_ADDR = "0b1000010";
|
|
defparam INST10.I2C2_WAKEUP = "DISABLED";
|
|
defparam INST10.SPI_CLK_DIVIDER = 1;
|
|
defparam INST10.SPI_CLK_INV = "DISABLED";
|
|
defparam INST10.SPI_INTR_RXOVR = "DISABLED";
|
|
defparam INST10.SPI_INTR_RXRDY = "DISABLED";
|
|
defparam INST10.SPI_INTR_TXOVR = "DISABLED";
|
|
defparam INST10.SPI_INTR_TXRDY = "DISABLED";
|
|
defparam INST10.SPI_LSB_FIRST = "DISABLED";
|
|
defparam INST10.SPI_MODE = "MASTER";
|
|
defparam INST10.SPI_PHASE_ADJ = "DISABLED";
|
|
defparam INST10.SPI_SLAVE_HANDSHAKE = "DISABLED";
|
|
defparam INST10.SPI_WAKEUP = "DISABLED";
|
|
defparam INST10.TC_CCLK_SEL = 1;
|
|
defparam INST10.TC_ICAPTURE = "DISABLED";
|
|
defparam INST10.TC_ICR_INT = "OFF";
|
|
defparam INST10.TC_MODE = "CTCM";
|
|
defparam INST10.TC_OCR_INT = "OFF";
|
|
defparam INST10.TC_OCR_SET = 32767;
|
|
defparam INST10.TC_OC_MODE = "TOGGLE";
|
|
defparam INST10.TC_OVERFLOW = "DISABLED";
|
|
defparam INST10.TC_OV_INT = "OFF";
|
|
defparam INST10.TC_RESETN = "ENABLED";
|
|
defparam INST10.TC_SCLK_SEL = "PCLOCK";
|
|
defparam INST10.TC_TOP_SEL = "OFF";
|
|
defparam INST10.TC_TOP_SET = 65535;
|
|
defparam INST10.UFM_INIT_ALL_ZEROS = "DISABLED";
|
|
defparam INST10.UFM_INIT_FILE_FORMAT = "HEX";
|
|
defparam INST10.UFM_INIT_FILE_NAME = "../RAM2E-LCMXO2.mem";
|
|
defparam INST10.UFM_INIT_PAGES = 1;
|
|
defparam INST10.UFM_INIT_START_PAGE = 190;
|
|
EFB_Buffer_Block INST20( .WBCLKIin(WBCLKI), .WBCLKIout(WBCLKI_buf),
|
|
.WBRSTIin(WBRSTI), .WBRSTIout(WBRSTI_buf), .WBCYCIin(WBCYCI),
|
|
.WBCYCIout(WBCYCI_buf), .WBSTBIin(WBSTBI), .WBSTBIout(WBSTBI_buf),
|
|
.WBWEIin(WBWEI), .WBWEIout(WBWEI_buf), .WBADRI7in(WBADRI7),
|
|
.WBADRI7out(WBADRI7_buf), .WBADRI6in(WBADRI6), .WBADRI6out(WBADRI6_buf),
|
|
.WBADRI5in(WBADRI5), .WBADRI5out(WBADRI5_buf), .WBADRI4in(WBADRI4),
|
|
.WBADRI4out(WBADRI4_buf), .WBADRI3in(WBADRI3), .WBADRI3out(WBADRI3_buf),
|
|
.WBADRI2in(WBADRI2), .WBADRI2out(WBADRI2_buf), .WBADRI1in(WBADRI1),
|
|
.WBADRI1out(WBADRI1_buf), .WBADRI0in(WBADRI0), .WBADRI0out(WBADRI0_buf),
|
|
.WBDATI7in(WBDATI7), .WBDATI7out(WBDATI7_buf), .WBDATI6in(WBDATI6),
|
|
.WBDATI6out(WBDATI6_buf), .WBDATI5in(WBDATI5), .WBDATI5out(WBDATI5_buf),
|
|
.WBDATI4in(WBDATI4), .WBDATI4out(WBDATI4_buf), .WBDATI3in(WBDATI3),
|
|
.WBDATI3out(WBDATI3_buf), .WBDATI2in(WBDATI2), .WBDATI2out(WBDATI2_buf),
|
|
.WBDATI1in(WBDATI1), .WBDATI1out(WBDATI1_buf), .WBDATI0in(WBDATI0),
|
|
.WBDATI0out(WBDATI0_buf), .PLL0DATI7in(PLL0DATI7),
|
|
.PLL0DATI7out(PLL0DATI7_buf), .PLL0DATI6in(PLL0DATI6),
|
|
.PLL0DATI6out(PLL0DATI6_buf), .PLL0DATI5in(PLL0DATI5),
|
|
.PLL0DATI5out(PLL0DATI5_buf), .PLL0DATI4in(PLL0DATI4),
|
|
.PLL0DATI4out(PLL0DATI4_buf), .PLL0DATI3in(PLL0DATI3),
|
|
.PLL0DATI3out(PLL0DATI3_buf), .PLL0DATI2in(PLL0DATI2),
|
|
.PLL0DATI2out(PLL0DATI2_buf), .PLL0DATI1in(PLL0DATI1),
|
|
.PLL0DATI1out(PLL0DATI1_buf), .PLL0DATI0in(PLL0DATI0),
|
|
.PLL0DATI0out(PLL0DATI0_buf), .PLL0ACKIin(PLL0ACKI),
|
|
.PLL0ACKIout(PLL0ACKI_buf), .PLL1DATI7in(PLL1DATI7),
|
|
.PLL1DATI7out(PLL1DATI7_buf), .PLL1DATI6in(PLL1DATI6),
|
|
.PLL1DATI6out(PLL1DATI6_buf), .PLL1DATI5in(PLL1DATI5),
|
|
.PLL1DATI5out(PLL1DATI5_buf), .PLL1DATI4in(PLL1DATI4),
|
|
.PLL1DATI4out(PLL1DATI4_buf), .PLL1DATI3in(PLL1DATI3),
|
|
.PLL1DATI3out(PLL1DATI3_buf), .PLL1DATI2in(PLL1DATI2),
|
|
.PLL1DATI2out(PLL1DATI2_buf), .PLL1DATI1in(PLL1DATI1),
|
|
.PLL1DATI1out(PLL1DATI1_buf), .PLL1DATI0in(PLL1DATI0),
|
|
.PLL1DATI0out(PLL1DATI0_buf), .PLL1ACKIin(PLL1ACKI),
|
|
.PLL1ACKIout(PLL1ACKI_buf), .I2C1SCLIin(I2C1SCLI),
|
|
.I2C1SCLIout(I2C1SCLI_buf), .I2C1SDAIin(I2C1SDAI),
|
|
.I2C1SDAIout(I2C1SDAI_buf), .I2C2SCLIin(I2C2SCLI),
|
|
.I2C2SCLIout(I2C2SCLI_buf), .I2C2SDAIin(I2C2SDAI),
|
|
.I2C2SDAIout(I2C2SDAI_buf), .SPISCKIin(SPISCKI), .SPISCKIout(SPISCKI_buf),
|
|
.SPIMISOIin(SPIMISOI), .SPIMISOIout(SPIMISOI_buf), .SPIMOSIIin(SPIMOSII),
|
|
.SPIMOSIIout(SPIMOSII_buf), .SPISCSNin(SPISCSN), .SPISCSNout(SPISCSN_buf),
|
|
.TCCLKIin(TCCLKI), .TCCLKIout(TCCLKI_buf), .TCRSTNin(TCRSTN),
|
|
.TCRSTNout(TCRSTN_buf), .TCICin(TCIC), .TCICout(TCIC_buf), .UFMSNin(UFMSN),
|
|
.UFMSNout(UFMSN_buf), .WBDATO7out(WBDATO7), .WBDATO7in(WBDATO7_buf),
|
|
.WBDATO6out(WBDATO6), .WBDATO6in(WBDATO6_buf), .WBDATO5out(WBDATO5),
|
|
.WBDATO5in(WBDATO5_buf), .WBDATO4out(WBDATO4), .WBDATO4in(WBDATO4_buf),
|
|
.WBDATO3out(WBDATO3), .WBDATO3in(WBDATO3_buf), .WBDATO2out(WBDATO2),
|
|
.WBDATO2in(WBDATO2_buf), .WBDATO1out(WBDATO1), .WBDATO1in(WBDATO1_buf),
|
|
.WBDATO0out(WBDATO0), .WBDATO0in(WBDATO0_buf), .WBACKOout(WBACKO),
|
|
.WBACKOin(WBACKO_buf), .PLLCLKOout(PLLCLKO), .PLLCLKOin(PLLCLKO_buf),
|
|
.PLLRSTOout(PLLRSTO), .PLLRSTOin(PLLRSTO_buf), .PLL0STBOout(PLL0STBO),
|
|
.PLL0STBOin(PLL0STBO_buf), .PLL1STBOout(PLL1STBO),
|
|
.PLL1STBOin(PLL1STBO_buf), .PLLWEOout(PLLWEO), .PLLWEOin(PLLWEO_buf),
|
|
.PLLADRO4out(PLLADRO4), .PLLADRO4in(PLLADRO4_buf), .PLLADRO3out(PLLADRO3),
|
|
.PLLADRO3in(PLLADRO3_buf), .PLLADRO2out(PLLADRO2),
|
|
.PLLADRO2in(PLLADRO2_buf), .PLLADRO1out(PLLADRO1),
|
|
.PLLADRO1in(PLLADRO1_buf), .PLLADRO0out(PLLADRO0),
|
|
.PLLADRO0in(PLLADRO0_buf), .PLLDATO7out(PLLDATO7),
|
|
.PLLDATO7in(PLLDATO7_buf), .PLLDATO6out(PLLDATO6),
|
|
.PLLDATO6in(PLLDATO6_buf), .PLLDATO5out(PLLDATO5),
|
|
.PLLDATO5in(PLLDATO5_buf), .PLLDATO4out(PLLDATO4),
|
|
.PLLDATO4in(PLLDATO4_buf), .PLLDATO3out(PLLDATO3),
|
|
.PLLDATO3in(PLLDATO3_buf), .PLLDATO2out(PLLDATO2),
|
|
.PLLDATO2in(PLLDATO2_buf), .PLLDATO1out(PLLDATO1),
|
|
.PLLDATO1in(PLLDATO1_buf), .PLLDATO0out(PLLDATO0),
|
|
.PLLDATO0in(PLLDATO0_buf), .I2C1SCLOout(I2C1SCLO),
|
|
.I2C1SCLOin(I2C1SCLO_buf), .I2C1SCLOENout(I2C1SCLOEN),
|
|
.I2C1SCLOENin(I2C1SCLOEN_buf), .I2C1SDAOout(I2C1SDAO),
|
|
.I2C1SDAOin(I2C1SDAO_buf), .I2C1SDAOENout(I2C1SDAOEN),
|
|
.I2C1SDAOENin(I2C1SDAOEN_buf), .I2C2SCLOout(I2C2SCLO),
|
|
.I2C2SCLOin(I2C2SCLO_buf), .I2C2SCLOENout(I2C2SCLOEN),
|
|
.I2C2SCLOENin(I2C2SCLOEN_buf), .I2C2SDAOout(I2C2SDAO),
|
|
.I2C2SDAOin(I2C2SDAO_buf), .I2C2SDAOENout(I2C2SDAOEN),
|
|
.I2C2SDAOENin(I2C2SDAOEN_buf), .I2C1IRQOout(I2C1IRQO),
|
|
.I2C1IRQOin(I2C1IRQO_buf), .I2C2IRQOout(I2C2IRQO),
|
|
.I2C2IRQOin(I2C2IRQO_buf), .SPISCKOout(SPISCKO), .SPISCKOin(SPISCKO_buf),
|
|
.SPISCKENout(SPISCKEN), .SPISCKENin(SPISCKEN_buf), .SPIMISOOout(SPIMISOO),
|
|
.SPIMISOOin(SPIMISOO_buf), .SPIMISOENout(SPIMISOEN),
|
|
.SPIMISOENin(SPIMISOEN_buf), .SPIMOSIOout(SPIMOSIO),
|
|
.SPIMOSIOin(SPIMOSIO_buf), .SPIMOSIENout(SPIMOSIEN),
|
|
.SPIMOSIENin(SPIMOSIEN_buf), .SPIMCSN0out(SPIMCSN0),
|
|
.SPIMCSN0in(SPIMCSN0_buf), .SPIMCSN1out(SPIMCSN1),
|
|
.SPIMCSN1in(SPIMCSN1_buf), .SPIMCSN2out(SPIMCSN2),
|
|
.SPIMCSN2in(SPIMCSN2_buf), .SPIMCSN3out(SPIMCSN3),
|
|
.SPIMCSN3in(SPIMCSN3_buf), .SPIMCSN4out(SPIMCSN4),
|
|
.SPIMCSN4in(SPIMCSN4_buf), .SPIMCSN5out(SPIMCSN5),
|
|
.SPIMCSN5in(SPIMCSN5_buf), .SPIMCSN6out(SPIMCSN6),
|
|
.SPIMCSN6in(SPIMCSN6_buf), .SPIMCSN7out(SPIMCSN7),
|
|
.SPIMCSN7in(SPIMCSN7_buf), .SPICSNENout(SPICSNEN),
|
|
.SPICSNENin(SPICSNEN_buf), .SPIIRQOout(SPIIRQO), .SPIIRQOin(SPIIRQO_buf),
|
|
.TCINTout(TCINT), .TCINTin(TCINT_buf), .TCOCout(TCOC), .TCOCin(TCOC_buf),
|
|
.WBCUFMIRQout(WBCUFMIRQ), .WBCUFMIRQin(WBCUFMIRQ_buf),
|
|
.CFGWAKEout(CFGWAKE), .CFGWAKEin(CFGWAKE_buf), .CFGSTDBYout(CFGSTDBY),
|
|
.CFGSTDBYin(CFGSTDBY_buf));
|
|
endmodule
|
|
|
|
module EFB_Buffer_Block ( input WBCLKIin, output WBCLKIout, input WBRSTIin,
|
|
output WBRSTIout, input WBCYCIin, output WBCYCIout, input WBSTBIin,
|
|
output WBSTBIout, input WBWEIin, output WBWEIout, input WBADRI7in, output
|
|
WBADRI7out, input WBADRI6in, output WBADRI6out, input WBADRI5in, output
|
|
WBADRI5out, input WBADRI4in, output WBADRI4out, input WBADRI3in, output
|
|
WBADRI3out, input WBADRI2in, output WBADRI2out, input WBADRI1in, output
|
|
WBADRI1out, input WBADRI0in, output WBADRI0out, input WBDATI7in, output
|
|
WBDATI7out, input WBDATI6in, output WBDATI6out, input WBDATI5in, output
|
|
WBDATI5out, input WBDATI4in, output WBDATI4out, input WBDATI3in, output
|
|
WBDATI3out, input WBDATI2in, output WBDATI2out, input WBDATI1in, output
|
|
WBDATI1out, input WBDATI0in, output WBDATI0out, input PLL0DATI7in, output
|
|
PLL0DATI7out, input PLL0DATI6in, output PLL0DATI6out, input PLL0DATI5in,
|
|
output PLL0DATI5out, input PLL0DATI4in, output PLL0DATI4out, input
|
|
PLL0DATI3in, output PLL0DATI3out, input PLL0DATI2in, output PLL0DATI2out,
|
|
input PLL0DATI1in, output PLL0DATI1out, input PLL0DATI0in, output
|
|
PLL0DATI0out, input PLL0ACKIin, output PLL0ACKIout, input PLL1DATI7in,
|
|
output PLL1DATI7out, input PLL1DATI6in, output PLL1DATI6out, input
|
|
PLL1DATI5in, output PLL1DATI5out, input PLL1DATI4in, output PLL1DATI4out,
|
|
input PLL1DATI3in, output PLL1DATI3out, input PLL1DATI2in, output
|
|
PLL1DATI2out, input PLL1DATI1in, output PLL1DATI1out, input PLL1DATI0in,
|
|
output PLL1DATI0out, input PLL1ACKIin, output PLL1ACKIout, input
|
|
I2C1SCLIin, output I2C1SCLIout, input I2C1SDAIin, output I2C1SDAIout,
|
|
input I2C2SCLIin, output I2C2SCLIout, input I2C2SDAIin, output I2C2SDAIout,
|
|
input SPISCKIin, output SPISCKIout, input SPIMISOIin, output SPIMISOIout,
|
|
input SPIMOSIIin, output SPIMOSIIout, input SPISCSNin, output SPISCSNout,
|
|
input TCCLKIin, output TCCLKIout, input TCRSTNin, output TCRSTNout, input
|
|
TCICin, output TCICout, input UFMSNin, output UFMSNout, WBDATO7out, input
|
|
WBDATO7in, output WBDATO6out, input WBDATO6in, output WBDATO5out, input
|
|
WBDATO5in, output WBDATO4out, input WBDATO4in, output WBDATO3out, input
|
|
WBDATO3in, output WBDATO2out, input WBDATO2in, output WBDATO1out, input
|
|
WBDATO1in, output WBDATO0out, input WBDATO0in, output WBACKOout, input
|
|
WBACKOin, output PLLCLKOout, input PLLCLKOin, output PLLRSTOout, input
|
|
PLLRSTOin, output PLL0STBOout, input PLL0STBOin, output PLL1STBOout,
|
|
input PLL1STBOin, output PLLWEOout, input PLLWEOin, output PLLADRO4out,
|
|
input PLLADRO4in, output PLLADRO3out, input PLLADRO3in, output PLLADRO2out,
|
|
input PLLADRO2in, output PLLADRO1out, input PLLADRO1in, output PLLADRO0out,
|
|
input PLLADRO0in, output PLLDATO7out, input PLLDATO7in, output PLLDATO6out,
|
|
input PLLDATO6in, output PLLDATO5out, input PLLDATO5in, output PLLDATO4out,
|
|
input PLLDATO4in, output PLLDATO3out, input PLLDATO3in, output PLLDATO2out,
|
|
input PLLDATO2in, output PLLDATO1out, input PLLDATO1in, output PLLDATO0out,
|
|
input PLLDATO0in, output I2C1SCLOout, input I2C1SCLOin, output
|
|
I2C1SCLOENout, input I2C1SCLOENin, output I2C1SDAOout, input I2C1SDAOin,
|
|
output I2C1SDAOENout, input I2C1SDAOENin, output I2C2SCLOout, input
|
|
I2C2SCLOin, output I2C2SCLOENout, input I2C2SCLOENin, output I2C2SDAOout,
|
|
input I2C2SDAOin, output I2C2SDAOENout, input I2C2SDAOENin, output
|
|
I2C1IRQOout, input I2C1IRQOin, output I2C2IRQOout, input I2C2IRQOin,
|
|
output SPISCKOout, input SPISCKOin, output SPISCKENout, input SPISCKENin,
|
|
output SPIMISOOout, input SPIMISOOin, output SPIMISOENout, input
|
|
SPIMISOENin, output SPIMOSIOout, input SPIMOSIOin, output SPIMOSIENout,
|
|
input SPIMOSIENin, output SPIMCSN0out, input SPIMCSN0in, output
|
|
SPIMCSN1out, input SPIMCSN1in, output SPIMCSN2out, input SPIMCSN2in,
|
|
output SPIMCSN3out, input SPIMCSN3in, output SPIMCSN4out, input SPIMCSN4in,
|
|
output SPIMCSN5out, input SPIMCSN5in, output SPIMCSN6out, input SPIMCSN6in,
|
|
output SPIMCSN7out, input SPIMCSN7in, output SPICSNENout, input SPICSNENin,
|
|
output SPIIRQOout, input SPIIRQOin, output TCINTout, input TCINTin,
|
|
output TCOCout, input TCOCin, output WBCUFMIRQout, input WBCUFMIRQin,
|
|
output CFGWAKEout, input CFGWAKEin, output CFGSTDBYout, input CFGSTDBYin );
|
|
wire WBRSTIin_dly, WBCLKIin_dly, WBCYCIin_dly, WBSTBIin_dly, WBWEIin_dly,
|
|
WBADRI0in_dly, WBADRI1in_dly, WBADRI2in_dly, WBADRI3in_dly,
|
|
WBADRI4in_dly, WBADRI5in_dly, WBADRI6in_dly, WBADRI7in_dly,
|
|
WBDATI0in_dly, WBDATI1in_dly, WBDATI2in_dly, WBDATI3in_dly,
|
|
WBDATI4in_dly, WBDATI5in_dly, WBDATI6in_dly, WBDATI7in_dly;
|
|
|
|
BUFBA WBCLKI_buf( .A(WBCLKIin_dly), .Z(WBCLKIout));
|
|
BUFBA WBRSTI_buf( .A(WBRSTIin_dly), .Z(WBRSTIout));
|
|
BUFBA WBCYCI_buf( .A(WBCYCIin_dly), .Z(WBCYCIout));
|
|
BUFBA WBSTBI_buf( .A(WBSTBIin_dly), .Z(WBSTBIout));
|
|
BUFBA WBWEI_buf( .A(WBWEIin_dly), .Z(WBWEIout));
|
|
BUFBA WBADRI7_buf( .A(WBADRI7in_dly), .Z(WBADRI7out));
|
|
BUFBA WBADRI6_buf( .A(WBADRI6in_dly), .Z(WBADRI6out));
|
|
BUFBA WBADRI5_buf( .A(WBADRI5in_dly), .Z(WBADRI5out));
|
|
BUFBA WBADRI4_buf( .A(WBADRI4in_dly), .Z(WBADRI4out));
|
|
BUFBA WBADRI3_buf( .A(WBADRI3in_dly), .Z(WBADRI3out));
|
|
BUFBA WBADRI2_buf( .A(WBADRI2in_dly), .Z(WBADRI2out));
|
|
BUFBA WBADRI1_buf( .A(WBADRI1in_dly), .Z(WBADRI1out));
|
|
BUFBA WBADRI0_buf( .A(WBADRI0in_dly), .Z(WBADRI0out));
|
|
BUFBA WBDATI7_buf( .A(WBDATI7in_dly), .Z(WBDATI7out));
|
|
BUFBA WBDATI6_buf( .A(WBDATI6in_dly), .Z(WBDATI6out));
|
|
BUFBA WBDATI5_buf( .A(WBDATI5in_dly), .Z(WBDATI5out));
|
|
BUFBA WBDATI4_buf( .A(WBDATI4in_dly), .Z(WBDATI4out));
|
|
BUFBA WBDATI3_buf( .A(WBDATI3in_dly), .Z(WBDATI3out));
|
|
BUFBA WBDATI2_buf( .A(WBDATI2in_dly), .Z(WBDATI2out));
|
|
BUFBA WBDATI1_buf( .A(WBDATI1in_dly), .Z(WBDATI1out));
|
|
BUFBA WBDATI0_buf( .A(WBDATI0in_dly), .Z(WBDATI0out));
|
|
BUFBA PLL0DATI7_buf( .A(PLL0DATI7in), .Z(PLL0DATI7out));
|
|
BUFBA PLL0DATI6_buf( .A(PLL0DATI6in), .Z(PLL0DATI6out));
|
|
BUFBA PLL0DATI5_buf( .A(PLL0DATI5in), .Z(PLL0DATI5out));
|
|
BUFBA PLL0DATI4_buf( .A(PLL0DATI4in), .Z(PLL0DATI4out));
|
|
BUFBA PLL0DATI3_buf( .A(PLL0DATI3in), .Z(PLL0DATI3out));
|
|
BUFBA PLL0DATI2_buf( .A(PLL0DATI2in), .Z(PLL0DATI2out));
|
|
BUFBA PLL0DATI1_buf( .A(PLL0DATI1in), .Z(PLL0DATI1out));
|
|
BUFBA PLL0DATI0_buf( .A(PLL0DATI0in), .Z(PLL0DATI0out));
|
|
BUFBA PLL0ACKI_buf( .A(PLL0ACKIin), .Z(PLL0ACKIout));
|
|
BUFBA PLL1DATI7_buf( .A(PLL1DATI7in), .Z(PLL1DATI7out));
|
|
BUFBA PLL1DATI6_buf( .A(PLL1DATI6in), .Z(PLL1DATI6out));
|
|
BUFBA PLL1DATI5_buf( .A(PLL1DATI5in), .Z(PLL1DATI5out));
|
|
BUFBA PLL1DATI4_buf( .A(PLL1DATI4in), .Z(PLL1DATI4out));
|
|
BUFBA PLL1DATI3_buf( .A(PLL1DATI3in), .Z(PLL1DATI3out));
|
|
BUFBA PLL1DATI2_buf( .A(PLL1DATI2in), .Z(PLL1DATI2out));
|
|
BUFBA PLL1DATI1_buf( .A(PLL1DATI1in), .Z(PLL1DATI1out));
|
|
BUFBA PLL1DATI0_buf( .A(PLL1DATI0in), .Z(PLL1DATI0out));
|
|
BUFBA PLL1ACKI_buf( .A(PLL1ACKIin), .Z(PLL1ACKIout));
|
|
BUFBA I2C1SCLI_buf( .A(I2C1SCLIin), .Z(I2C1SCLIout));
|
|
BUFBA I2C1SDAI_buf( .A(I2C1SDAIin), .Z(I2C1SDAIout));
|
|
BUFBA I2C2SCLI_buf( .A(I2C2SCLIin), .Z(I2C2SCLIout));
|
|
BUFBA I2C2SDAI_buf( .A(I2C2SDAIin), .Z(I2C2SDAIout));
|
|
BUFBA SPISCKI_buf( .A(SPISCKIin), .Z(SPISCKIout));
|
|
BUFBA SPIMISOI_buf( .A(SPIMISOIin), .Z(SPIMISOIout));
|
|
BUFBA SPIMOSII_buf( .A(SPIMOSIIin), .Z(SPIMOSIIout));
|
|
BUFBA SPISCSN_buf( .A(SPISCSNin), .Z(SPISCSNout));
|
|
BUFBA TCCLKI_buf( .A(TCCLKIin), .Z(TCCLKIout));
|
|
BUFBA TCRSTN_buf( .A(TCRSTNin), .Z(TCRSTNout));
|
|
BUFBA TCIC_buf( .A(TCICin), .Z(TCICout));
|
|
BUFBA UFMSN_buf( .A(UFMSNin), .Z(UFMSNout));
|
|
BUFBA WBDATO7_buf( .A(WBDATO7in), .Z(WBDATO7out));
|
|
BUFBA WBDATO6_buf( .A(WBDATO6in), .Z(WBDATO6out));
|
|
BUFBA WBDATO5_buf( .A(WBDATO5in), .Z(WBDATO5out));
|
|
BUFBA WBDATO4_buf( .A(WBDATO4in), .Z(WBDATO4out));
|
|
BUFBA WBDATO3_buf( .A(WBDATO3in), .Z(WBDATO3out));
|
|
BUFBA WBDATO2_buf( .A(WBDATO2in), .Z(WBDATO2out));
|
|
BUFBA WBDATO1_buf( .A(WBDATO1in), .Z(WBDATO1out));
|
|
BUFBA WBDATO0_buf( .A(WBDATO0in), .Z(WBDATO0out));
|
|
BUFBA WBACKO_buf( .A(WBACKOin), .Z(WBACKOout));
|
|
BUFBA PLLCLKO_buf( .A(PLLCLKOin), .Z(PLLCLKOout));
|
|
BUFBA PLLRSTO_buf( .A(PLLRSTOin), .Z(PLLRSTOout));
|
|
BUFBA PLL0STBO_buf( .A(PLL0STBOin), .Z(PLL0STBOout));
|
|
BUFBA PLL1STBO_buf( .A(PLL1STBOin), .Z(PLL1STBOout));
|
|
BUFBA PLLWEO_buf( .A(PLLWEOin), .Z(PLLWEOout));
|
|
BUFBA PLLADRO4_buf( .A(PLLADRO4in), .Z(PLLADRO4out));
|
|
BUFBA PLLADRO3_buf( .A(PLLADRO3in), .Z(PLLADRO3out));
|
|
BUFBA PLLADRO2_buf( .A(PLLADRO2in), .Z(PLLADRO2out));
|
|
BUFBA PLLADRO1_buf( .A(PLLADRO1in), .Z(PLLADRO1out));
|
|
BUFBA PLLADRO0_buf( .A(PLLADRO0in), .Z(PLLADRO0out));
|
|
BUFBA PLLDATO7_buf( .A(PLLDATO7in), .Z(PLLDATO7out));
|
|
BUFBA PLLDATO6_buf( .A(PLLDATO6in), .Z(PLLDATO6out));
|
|
BUFBA PLLDATO5_buf( .A(PLLDATO5in), .Z(PLLDATO5out));
|
|
BUFBA PLLDATO4_buf( .A(PLLDATO4in), .Z(PLLDATO4out));
|
|
BUFBA PLLDATO3_buf( .A(PLLDATO3in), .Z(PLLDATO3out));
|
|
BUFBA PLLDATO2_buf( .A(PLLDATO2in), .Z(PLLDATO2out));
|
|
BUFBA PLLDATO1_buf( .A(PLLDATO1in), .Z(PLLDATO1out));
|
|
BUFBA PLLDATO0_buf( .A(PLLDATO0in), .Z(PLLDATO0out));
|
|
BUFBA I2C1SCLO_buf( .A(I2C1SCLOin), .Z(I2C1SCLOout));
|
|
BUFBA I2C1SCLOEN_buf( .A(I2C1SCLOENin), .Z(I2C1SCLOENout));
|
|
BUFBA I2C1SDAO_buf( .A(I2C1SDAOin), .Z(I2C1SDAOout));
|
|
BUFBA I2C1SDAOEN_buf( .A(I2C1SDAOENin), .Z(I2C1SDAOENout));
|
|
BUFBA I2C2SCLO_buf( .A(I2C2SCLOin), .Z(I2C2SCLOout));
|
|
BUFBA I2C2SCLOEN_buf( .A(I2C2SCLOENin), .Z(I2C2SCLOENout));
|
|
BUFBA I2C2SDAO_buf( .A(I2C2SDAOin), .Z(I2C2SDAOout));
|
|
BUFBA I2C2SDAOEN_buf( .A(I2C2SDAOENin), .Z(I2C2SDAOENout));
|
|
BUFBA I2C1IRQO_buf( .A(I2C1IRQOin), .Z(I2C1IRQOout));
|
|
BUFBA I2C2IRQO_buf( .A(I2C2IRQOin), .Z(I2C2IRQOout));
|
|
BUFBA SPISCKO_buf( .A(SPISCKOin), .Z(SPISCKOout));
|
|
BUFBA SPISCKEN_buf( .A(SPISCKENin), .Z(SPISCKENout));
|
|
BUFBA SPIMISOO_buf( .A(SPIMISOOin), .Z(SPIMISOOout));
|
|
BUFBA SPIMISOEN_buf( .A(SPIMISOENin), .Z(SPIMISOENout));
|
|
BUFBA SPIMOSIO_buf( .A(SPIMOSIOin), .Z(SPIMOSIOout));
|
|
BUFBA SPIMOSIEN_buf( .A(SPIMOSIENin), .Z(SPIMOSIENout));
|
|
BUFBA SPIMCSN0_buf( .A(SPIMCSN0in), .Z(SPIMCSN0out));
|
|
BUFBA SPIMCSN1_buf( .A(SPIMCSN1in), .Z(SPIMCSN1out));
|
|
BUFBA SPIMCSN2_buf( .A(SPIMCSN2in), .Z(SPIMCSN2out));
|
|
BUFBA SPIMCSN3_buf( .A(SPIMCSN3in), .Z(SPIMCSN3out));
|
|
BUFBA SPIMCSN4_buf( .A(SPIMCSN4in), .Z(SPIMCSN4out));
|
|
BUFBA SPIMCSN5_buf( .A(SPIMCSN5in), .Z(SPIMCSN5out));
|
|
BUFBA SPIMCSN6_buf( .A(SPIMCSN6in), .Z(SPIMCSN6out));
|
|
BUFBA SPIMCSN7_buf( .A(SPIMCSN7in), .Z(SPIMCSN7out));
|
|
BUFBA SPICSNEN_buf( .A(SPICSNENin), .Z(SPICSNENout));
|
|
BUFBA SPIIRQO_buf( .A(SPIIRQOin), .Z(SPIIRQOout));
|
|
BUFBA TCINT_buf( .A(TCINTin), .Z(TCINTout));
|
|
BUFBA TCOC_buf( .A(TCOCin), .Z(TCOCout));
|
|
BUFBA WBCUFMIRQ_buf( .A(WBCUFMIRQin), .Z(WBCUFMIRQout));
|
|
BUFBA CFGWAKE_buf( .A(CFGWAKEin), .Z(CFGWAKEout));
|
|
BUFBA CFGSTDBY_buf( .A(CFGSTDBYin), .Z(CFGSTDBYout));
|
|
|
|
specify
|
|
(WBCLKIin => WBDATO0out) = (0:0:0,0:0:0);
|
|
(WBCLKIin => WBDATO1out) = (0:0:0,0:0:0);
|
|
(WBCLKIin => WBDATO2out) = (0:0:0,0:0:0);
|
|
(WBCLKIin => WBDATO3out) = (0:0:0,0:0:0);
|
|
(WBCLKIin => WBDATO4out) = (0:0:0,0:0:0);
|
|
(WBCLKIin => WBDATO5out) = (0:0:0,0:0:0);
|
|
(WBCLKIin => WBDATO6out) = (0:0:0,0:0:0);
|
|
(WBCLKIin => WBDATO7out) = (0:0:0,0:0:0);
|
|
(WBCLKIin => WBACKOout) = (0:0:0,0:0:0);
|
|
$setuphold
|
|
(posedge WBCLKIin, WBRSTIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBRSTIin_dly);
|
|
$setuphold
|
|
(posedge WBCLKIin, WBCYCIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBCYCIin_dly);
|
|
$setuphold
|
|
(posedge WBCLKIin, WBSTBIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBSTBIin_dly);
|
|
$setuphold
|
|
(posedge WBCLKIin, WBWEIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBWEIin_dly);
|
|
$setuphold
|
|
(posedge WBCLKIin, WBADRI0in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI0in_dly);
|
|
$setuphold
|
|
(posedge WBCLKIin, WBADRI1in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI1in_dly);
|
|
$setuphold
|
|
(posedge WBCLKIin, WBADRI2in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI2in_dly);
|
|
$setuphold
|
|
(posedge WBCLKIin, WBADRI3in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI3in_dly);
|
|
$setuphold
|
|
(posedge WBCLKIin, WBADRI4in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI4in_dly);
|
|
$setuphold
|
|
(posedge WBCLKIin, WBADRI5in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI5in_dly);
|
|
$setuphold
|
|
(posedge WBCLKIin, WBADRI6in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI6in_dly);
|
|
$setuphold
|
|
(posedge WBCLKIin, WBADRI7in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI7in_dly);
|
|
$setuphold
|
|
(posedge WBCLKIin, WBDATI0in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI0in_dly);
|
|
$setuphold
|
|
(posedge WBCLKIin, WBDATI1in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI1in_dly);
|
|
$setuphold
|
|
(posedge WBCLKIin, WBDATI2in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI2in_dly);
|
|
$setuphold
|
|
(posedge WBCLKIin, WBDATI3in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI3in_dly);
|
|
$setuphold
|
|
(posedge WBCLKIin, WBDATI4in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI4in_dly);
|
|
$setuphold
|
|
(posedge WBCLKIin, WBDATI5in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI5in_dly);
|
|
$setuphold
|
|
(posedge WBCLKIin, WBDATI6in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI6in_dly);
|
|
$setuphold
|
|
(posedge WBCLKIin, WBDATI7in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI7in_dly);
|
|
$width (posedge WBCLKIin, 0:0:0);
|
|
$width (negedge WBCLKIin, 0:0:0);
|
|
endspecify
|
|
|
|
endmodule
|