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8eb7ead8ee
Gated RAM access during PHI0, squeezed video access and MPU access together, gated data bus output buffer OE to only output at end of PHI0
7 lines
298 B
Plaintext
7 lines
298 B
Plaintext
start_full_compilation:s:00:00:07
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start_analysis_synthesis:s:00:00:02-start_full_compilation
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start_analysis_elaboration:s-start_full_compilation
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start_fitter:s:00:00:03-start_full_compilation
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start_assembler:s:00:00:01-start_full_compilation
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start_timing_analyzer:s:00:00:01-start_full_compilation
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