Improve power consumption

Gated RAM access during PHI0, squeezed video access and MPU access together, gated data bus output buffer OE to only output at end of PHI0
This commit is contained in:
Zane Kaminski 2020-09-16 19:49:18 -04:00
parent e8dee0f319
commit 8eb7ead8ee
101 changed files with 962 additions and 1625 deletions

View File

@ -56,7 +56,6 @@ set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name QIP_FILE UFM.qip
set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE BALANCED
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
@ -76,26 +75,32 @@ set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"
set_location_assignment PIN_12 -to C14M
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to C14M
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to C14M
set_location_assignment PIN_37 -to PHI1
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PHI1
set_instance_assignment -name PAD_TO_CORE_DELAY 1 -to PHI1
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to PHI1
set_location_assignment PIN_51 -to nWE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nWE
set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nWE
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nWE
set_location_assignment PIN_28 -to nEN80
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nEN80
set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nEN80
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nEN80
set_location_assignment PIN_33 -to nWE80
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nWE80
set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nWE80
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nWE80
set_location_assignment PIN_52 -to nC07X
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nC07X
set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nC07X
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nC07X
set_location_assignment PIN_56 -to Ain[0]
set_location_assignment PIN_54 -to Ain[1]
@ -107,6 +112,7 @@ set_location_assignment PIN_39 -to Ain[6]
set_location_assignment PIN_53 -to Ain[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Ain
set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to Ain
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Ain
set_location_assignment PIN_38 -to Din[0]
set_location_assignment PIN_40 -to Din[1]
@ -118,11 +124,13 @@ set_location_assignment PIN_36 -to Din[6]
set_location_assignment PIN_35 -to Din[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Din
set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to Din
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Din
set_location_assignment PIN_55 -to nDOE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nDOE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nDOE
set_instance_assignment -name SLOW_SLEW_RATE ON -to nDOE
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nDOE
set_location_assignment PIN_77 -to Dout[0]
set_location_assignment PIN_76 -to Dout[1]
@ -134,13 +142,15 @@ set_location_assignment PIN_84 -to Dout[6]
set_location_assignment PIN_85 -to Dout[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Dout
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to Dout
set_instance_assignment -name SLOW_SLEW_RATE OFF -to Dout
set_instance_assignment -name SLOW_SLEW_RATE ON -to Dout
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to Dout
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Dout
set_location_assignment PIN_50 -to nVOE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nVOE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nVOE
set_instance_assignment -name SLOW_SLEW_RATE OFF -to nVOE
set_instance_assignment -name SLOW_SLEW_RATE ON -to nVOE
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nVOE
set_location_assignment PIN_70 -to Vout[0]
set_location_assignment PIN_67 -to Vout[1]
@ -152,38 +162,44 @@ set_location_assignment PIN_58 -to Vout[6]
set_location_assignment PIN_57 -to Vout[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Vout
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to Vout
set_instance_assignment -name SLOW_SLEW_RATE OFF -to Vout
set_instance_assignment -name SLOW_SLEW_RATE ON -to Vout
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to Vout
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Vout
set_location_assignment PIN_4 -to CKE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CKE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to CKE
set_instance_assignment -name SLOW_SLEW_RATE ON -to CKE
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CKE
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to CKE
set_location_assignment PIN_8 -to nCS
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nCS
set_instance_assignment -name SLOW_SLEW_RATE ON -to nCS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nCS
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nCS
set_location_assignment PIN_2 -to nRWE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRWE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRWE
set_instance_assignment -name SLOW_SLEW_RATE ON -to nRWE
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRWE
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRWE
set_location_assignment PIN_5 -to nRAS
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRAS
set_instance_assignment -name SLOW_SLEW_RATE ON -to nRAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRAS
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRAS
set_location_assignment PIN_3 -to nCAS
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nCAS
set_instance_assignment -name SLOW_SLEW_RATE ON -to nCAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nCAS
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nCAS
set_location_assignment PIN_6 -to BA[0]
set_location_assignment PIN_14 -to BA[1]
@ -191,6 +207,7 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to BA
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to BA
set_instance_assignment -name SLOW_SLEW_RATE ON -to BA
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to BA
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to BA
set_location_assignment PIN_18 -to RA[0]
set_location_assignment PIN_20 -to RA[1]
@ -208,18 +225,21 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RA
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RA
set_instance_assignment -name SLOW_SLEW_RATE ON -to RA
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to RA
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA
set_location_assignment PIN_100 -to DQMH
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DQMH
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to DQMH
set_instance_assignment -name SLOW_SLEW_RATE ON -to DQMH
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DQMH
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to DQMH
set_location_assignment PIN_98 -to DQML
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DQML
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to DQML
set_instance_assignment -name SLOW_SLEW_RATE ON -to DQML
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DQML
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to DQML
set_location_assignment PIN_97 -to RD[0]
set_location_assignment PIN_90 -to RD[1]
@ -230,6 +250,10 @@ set_location_assignment PIN_92 -to RD[5]
set_location_assignment PIN_95 -to RD[6]
set_location_assignment PIN_96 -to RD[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RD
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RD
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RD
set_instance_assignment -name SLOW_SLEW_RATE ON -to RD
set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to RD
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to RD
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RD
set_global_assignment -name QIP_FILE UFM.qip

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View File

@ -17,10 +17,12 @@ module RAM2E(C14M, PHI1,
/* Address Bus */
input [7:0] Ain; // Multiplexed DRAM address input
reg [7:0] Areg; // Address saved for later
/* 6502 Data Bus */
input [7:0] Din; // 6502 data bus inputs
output nDOE = ~(EN80 & nWE); // 6502 data bus output enable
reg DOEEN = 0; // 6502 data bus output enable from state machine
output nDOE = ~(EN80 & nWE & DOEEN); // 6502 data bus output enable
output reg [7:0] Dout; // 6502 data Bus output
/* Video Data Bus */
@ -255,12 +257,15 @@ module RAM2E(C14M, PHI1,
// Mask everything
DQML <= 1'b1;
DQMH <= 1'b1;
// Inhibit data bus output
DOEEN <= 1'b0;
// Begin normal operation after 128k init cycles (~9.15ms)
if (FS == 16'hFFFF) Ready <= 1'b1;
end else if (S==4'h1) begin
// Enable clock
CKE <= 1'b1;
// Disable clock
CKE <= 1'b0;
// NOP
nCS <= 1'b1;
@ -275,7 +280,52 @@ module RAM2E(C14M, PHI1,
// Mask everything
DQML <= 1'b1;
DQMH <= 1'b1;
// Inhibit data bus output
DOEEN <= 1'b0;
end else if (S==4'h2) begin
// Disable clock
CKE <= 1'b0;
// NOP
nCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nRWE <= 1'b1;
// SDRAM bank 0, high-order row address is 0
BA <= 2'b00;
RA[11:8] <= 4'b0000;
// Mask everything
DQML <= 1'b1;
DQMH <= 1'b1;
// Inhibit data bus output
DOEEN <= 1'b0;
end else if (S==4'h3) begin
// Enable clock
CKE <= 1'b1;
// NOP
nCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nRWE <= 1'b1;
// Don't care bank, RA[11:8]
BA <= 2'b00;
RA[11:8] <= 4'b0000;
// Latch column address for read command
Areg[7:0] <= Ain[7:0];
// Mask everything
DQML <= 1'b1;
DQMH <= 1'b1;
// Inhibit data bus output
DOEEN <= 1'b0;
end else if (S==4'h4) begin
// Enable clock
CKE <= 1'b1;
@ -285,7 +335,7 @@ module RAM2E(C14M, PHI1,
nCAS <= 1'b1;
nRWE <= 1'b1;
// SDRAM bank 0, high-order row address is 0
// Don't care bank, RA[11:8]
BA <= 2'b00;
RA[11:8] <= 4'b0000;
// Row address is as previously latched
@ -293,7 +343,10 @@ module RAM2E(C14M, PHI1,
// Mask everything
DQML <= 1'b1;
DQMH <= 1'b1;
end else if (S==4'h3) begin
// Inhibit data bus output
DOEEN <= 1'b0;
end else if (S==4'h5) begin
// Enable clock
CKE <= 1'b1;
@ -309,50 +362,43 @@ module RAM2E(C14M, PHI1,
RA[10] <= 1'b1; // (A10 set to auto-precharge)
RA[9] <= 1'b0;
RA[8] <= 1'b0;
// Latch column address for read command
RA[7:0] <= Ain[7:0];
// Output previously latched column address
RA[7:0] <= Areg[7:0];
// Mask everything
DQML <= 1'b1;
DQMH <= 1'b1;
// Read low byte (high byte is +4MB in ramworks)
DQML <= 1'b0;
DQMH <= 1'b1;
end else if (S==4'h4) begin
// Enable clock
CKE <= 1'b1;
// NOP
nCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nRWE <= 1'b1;
// Don't care bank, RA[11:8]
BA <= 2'b00;
RA[11:8] <= 4'b0000;
// Mask everything
DQML <= 1'b1;
DQMH <= 1'b1;
end else if (S==4'h5) begin
// Enable clock
CKE <= 1'b1;
// NOP
nCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nRWE <= 1'b1;
// Don't care bank, RA[11:8]
BA <= 2'b00;
RA[11:8] <= 4'b0000;
// Mask everything
DQML <= 1'b1;
DQMH <= 1'b1;
// Inhibit data bus output
DOEEN <= 1'b0;
end else if (S==4'h6) begin
// Enable clock
CKE <= 1'b1;
// NOP
nCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nRWE <= 1'b1;
// Don't care bank, RA[11:8]
BA <= 2'b00;
RA[11:8] <= 4'b0000;
// Mask everything
DQML <= 1'b1;
DQMH <= 1'b1;
// Inhibit data bus output
DOEEN <= 1'b0;
end else if (S==4'h7) begin
// Enable clock
CKE <= 1'b1;
if (FS[6:4]==0) begin
// Auto-refresh
nCS <= 1'b0;
@ -367,23 +413,6 @@ module RAM2E(C14M, PHI1,
nRWE <= 1'b1;
end
// Don't care bank, RA[11:8]
BA <= 2'b00;
RA[11:8] <= 4'b0000;
// Mask everything
DQML <= 1'b1;
DQMH <= 1'b1;
end else if (S==4'h7) begin
// Enable clock
CKE <= 1'b1;
// NOP
nCS <= 1'b1;
nRAS <= 1'b1;
nCAS <= 1'b1;
nRWE <= 1'b1;
// Don't care bank, RA[11:8]
BA <= 2'b00;
RA[11:8] <= 4'b0000;
@ -393,12 +422,15 @@ module RAM2E(C14M, PHI1,
// Mask everything
DQML <= 1'b1;
DQMH <= 1'b1;
end else if (S==4'h8) begin
// Enable clock
CKE <= 1'b1;
// Activate
nCS <= 1'b0;
// Inhibit data bus output
DOEEN <= 1'b0;
end else if (S==4'h8) begin
// Enable clock if '245 output enabled
CKE <= EN80;
// Activate if '245 output enabled
nCS <= nEN80;
nRAS <= 1'b0;
nCAS <= 1'b1;
nRWE <= 1'b1;
@ -411,12 +443,15 @@ module RAM2E(C14M, PHI1,
// Mask everything
DQML <= 1'b1;
DQMH <= 1'b1;
end else if (S==4'h9) begin
// Enable clock
CKE <= 1'b1;
// Read/Write
nCS <= 1'b0;
// Inhibit data bus output
DOEEN <= 1'b0;
end else if (S==4'h9) begin
// Enable clock if '245 output enabled
CKE <= EN80;
// Read/Write if '245 output enabled
nCS <= nEN80;
nRAS <= 1'b1;
nCAS <= 1'b0;
nRWE <= nWE80;
@ -436,9 +471,12 @@ module RAM2E(C14M, PHI1,
// Mask according to RAMWorks bank (high byte is +4MB)
DQML <= RWBank[6];
DQMH <= ~RWBank[6];
// Inhibit data bus output
DOEEN <= 1'b0;
end else if (S==4'hA) begin
// Enable clock
CKE <= 1'b1;
// Enable clock if '245 output enabled
CKE <= EN80;
// NOP
nCS <= 1'b1;
@ -453,6 +491,9 @@ module RAM2E(C14M, PHI1,
// Mask everything
DQML <= 1'b1;
DQMH <= 1'b1;
// Inhibit data bus output
DOEEN <= 1'b0;
end else if (S==4'hB) begin
// Disable clock
CKE <= 1'b0;
@ -470,6 +511,9 @@ module RAM2E(C14M, PHI1,
// Mask everything
DQML <= 1'b1;
DQMH <= 1'b1;
// Enable data bus output
DOEEN <= 1'b1;
end else if (S==4'hC) begin
// Disable clock
CKE <= 1'b0;
@ -487,6 +531,9 @@ module RAM2E(C14M, PHI1,
// Mask everything
DQML <= 1'b1;
DQMH <= 1'b1;
// Enable data bus output
DOEEN <= 1'b1;
// RAMWorks Bank Register Select
if (RWSel) begin
@ -539,6 +586,9 @@ module RAM2E(C14M, PHI1,
// Mask everything
DQML <= 1'b1;
DQMH <= 1'b1;
// Enable data bus output
DOEEN <= 1'b1;
end else if (S==4'hE) begin
// Disable clock
CKE <= 1'b0;
@ -558,6 +608,9 @@ module RAM2E(C14M, PHI1,
// Mask everything
DQML <= 1'b1;
DQMH <= 1'b1;
// Enable data bus output
DOEEN <= 1'b1;
end else if (S==4'hF) begin
// Disable clock
CKE <= 1'b0;
@ -577,11 +630,14 @@ module RAM2E(C14M, PHI1,
// Mask everything
DQML <= 1'b1;
DQMH <= 1'b1;
// Enable data bus output
DOEEN <= 1'b1;
end
end
always @(negedge C14M) begin
// Latch video and read data outputs
if (S==4'h6) Vout[7:0] <= RD[7:0];
if (S==4'h8) Vout[7:0] <= RD[7:0];
if (S==4'hC) Dout[7:0] <= RD[7:0];
end
endmodule

View File

@ -1,127 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
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(line (pt 48 192)(pt 112 192))
(line (pt 48 32)(pt 48 192))
(line (pt 0 0)(pt 160 0))
(line (pt 160 0)(pt 160 208))
(line (pt 0 208)(pt 160 208))
(line (pt 0 0)(pt 0 208))
)
)

View File

@ -1,5 +1,3 @@
set_global_assignment -name IP_TOOL_NAME "ALTUFM_NONE"
set_global_assignment -name IP_TOOL_VERSION "13.0"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "UFM.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "UFM.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "UFM_bb.v"]

View File

@ -9,7 +9,7 @@
// ALTUFM_NONE
//
// Simulation Library Files(s):
// maxii
// maxv
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
@ -33,17 +33,17 @@
//applicable agreement for further details.
//altufm_none CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="MAX II" ERASE_TIME=500000000 LPM_FILE="RAM2E.mif" OSC_FREQUENCY=180000 PORT_ARCLKENA="PORT_UNUSED" PORT_DRCLKENA="PORT_UNUSED" PROGRAM_TIME=1600000 WIDTH_UFM_ADDRESS=9 arclk ardin arshft busy drclk drdin drdout drshft erase osc oscena program rtpbusy
//altufm_none CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="MAX V" ERASE_TIME=500000000 LPM_FILE="RAM2E.mif" OSC_FREQUENCY=180000 PORT_ARCLKENA="PORT_UNUSED" PORT_DRCLKENA="PORT_UNUSED" PROGRAM_TIME=1600000 WIDTH_UFM_ADDRESS=9 arclk ardin arshft busy drclk drdin drdout drshft erase osc oscena program rtpbusy
//VERSION_BEGIN 13.0 cbx_a_gray2bin 2013:06:12:18:03:43:SJ cbx_a_graycounter 2013:06:12:18:03:43:SJ cbx_altufm_none 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_maxii 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = maxii_ufm 1
//synthesis_resources = maxv_ufm 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module UFM_altufm_none_a7r
module UFM_altufm_none_e4r
(
arclk,
ardin,
@ -90,7 +90,7 @@ module UFM_altufm_none_a7r
wire ufm_oscena;
wire ufm_program;
maxii_ufm maxii_ufm_block1
maxv_ufm maxii_ufm_block1
(
.arclk(ufm_arclk),
.ardin(ufm_ardin),
@ -136,7 +136,7 @@ module UFM_altufm_none_a7r
maxii_ufm_block1.mem9 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.osc_sim_setting = 180000,
maxii_ufm_block1.program_time = 1600000,
maxii_ufm_block1.lpm_type = "maxii_ufm";
maxii_ufm_block1.lpm_type = "maxv_ufm";
assign
busy = ufm_busy,
drdout = ufm_drdout,
@ -155,7 +155,7 @@ module UFM_altufm_none_a7r
ufm_osc = wire_maxii_ufm_block1_osc,
ufm_oscena = oscena,
ufm_program = program;
endmodule //UFM_altufm_none_a7r
endmodule //UFM_altufm_none_e4r
//VALID FILE
@ -200,7 +200,7 @@ module UFM (
wire drdout = sub_wire2;
wire busy = sub_wire3;
UFM_altufm_none_a7r UFM_altufm_none_a7r_component (
UFM_altufm_none_e4r UFM_altufm_none_e4r_component (
.arshft (arshft),
.drclk (drclk),
.erase (erase),
@ -221,9 +221,9 @@ endmodule
// CNX file retrieval info
// ============================================================
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX II"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX V"
// Retrieval info: CONSTANT: ERASE_TIME NUMERIC "500000000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX II"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX V"
// Retrieval info: CONSTANT: LPM_FILE STRING "RAM2E.mif"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altufm_none"
@ -260,9 +260,9 @@ endmodule
// Retrieval info: CONNECT: rtpbusy 0 0 0 0 @rtpbusy 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.qip TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.bsf TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.bsf FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM_inst.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM_bb.v TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM_bb.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.inc FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.cmp FALSE TRUE
// Retrieval info: LIB_FILE: maxii
// Retrieval info: LIB_FILE: maxv

View File

@ -1,113 +0,0 @@
// megafunction wizard: %ALTUFM_NONE%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTUFM_NONE
// ============================================================
// File Name: UFM.v
// Megafunction Name(s):
// ALTUFM_NONE
//
// Simulation Library Files(s):
// maxii
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module UFM (
arclk,
ardin,
arshft,
drclk,
drdin,
drshft,
erase,
oscena,
program,
busy,
drdout,
osc,
rtpbusy)/* synthesis synthesis_clearbox = 1 */;
input arclk;
input ardin;
input arshft;
input drclk;
input drdin;
input drshft;
input erase;
input oscena;
input program;
output busy;
output drdout;
output osc;
output rtpbusy;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX II"
// Retrieval info: CONSTANT: ERASE_TIME NUMERIC "500000000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX II"
// Retrieval info: CONSTANT: LPM_FILE STRING "RAM2E.mif"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altufm_none"
// Retrieval info: CONSTANT: OSC_FREQUENCY NUMERIC "180000"
// Retrieval info: CONSTANT: PORT_ARCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_DRCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PROGRAM_TIME NUMERIC "1600000"
// Retrieval info: CONSTANT: WIDTH_UFM_ADDRESS NUMERIC "9"
// Retrieval info: USED_PORT: arclk 0 0 0 0 INPUT NODEFVAL "arclk"
// Retrieval info: CONNECT: @arclk 0 0 0 0 arclk 0 0 0 0
// Retrieval info: USED_PORT: ardin 0 0 0 0 INPUT NODEFVAL "ardin"
// Retrieval info: CONNECT: @ardin 0 0 0 0 ardin 0 0 0 0
// Retrieval info: USED_PORT: arshft 0 0 0 0 INPUT NODEFVAL "arshft"
// Retrieval info: CONNECT: @arshft 0 0 0 0 arshft 0 0 0 0
// Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy"
// Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
// Retrieval info: USED_PORT: drclk 0 0 0 0 INPUT NODEFVAL "drclk"
// Retrieval info: CONNECT: @drclk 0 0 0 0 drclk 0 0 0 0
// Retrieval info: USED_PORT: drdin 0 0 0 0 INPUT NODEFVAL "drdin"
// Retrieval info: CONNECT: @drdin 0 0 0 0 drdin 0 0 0 0
// Retrieval info: USED_PORT: drdout 0 0 0 0 OUTPUT NODEFVAL "drdout"
// Retrieval info: CONNECT: drdout 0 0 0 0 @drdout 0 0 0 0
// Retrieval info: USED_PORT: drshft 0 0 0 0 INPUT NODEFVAL "drshft"
// Retrieval info: CONNECT: @drshft 0 0 0 0 drshft 0 0 0 0
// Retrieval info: USED_PORT: erase 0 0 0 0 INPUT NODEFVAL "erase"
// Retrieval info: CONNECT: @erase 0 0 0 0 erase 0 0 0 0
// Retrieval info: USED_PORT: osc 0 0 0 0 OUTPUT NODEFVAL "osc"
// Retrieval info: CONNECT: osc 0 0 0 0 @osc 0 0 0 0
// Retrieval info: USED_PORT: oscena 0 0 0 0 INPUT NODEFVAL "oscena"
// Retrieval info: CONNECT: @oscena 0 0 0 0 oscena 0 0 0 0
// Retrieval info: USED_PORT: program 0 0 0 0 INPUT NODEFVAL "program"
// Retrieval info: CONNECT: @program 0 0 0 0 program 0 0 0 0
// Retrieval info: USED_PORT: rtpbusy 0 0 0 0 OUTPUT NODEFVAL "rtpbusy"
// Retrieval info: CONNECT: rtpbusy 0 0 0 0 @rtpbusy 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.qip TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.bsf TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM_inst.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM_bb.v TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.inc FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.cmp FALSE TRUE
// Retrieval info: LIB_FILE: maxii

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@ -1,6 +1,6 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1599607698989 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1599607698989 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 08 19:28:18 2020 " "Processing started: Tue Sep 08 19:28:18 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1599607698989 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1599607698989 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1599607698989 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1599607699289 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1599607699299 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4524 " "Peak virtual memory: 4524 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1599607699479 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 08 19:28:19 2020 " "Processing ended: Tue Sep 08 19:28:19 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1599607699479 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1599607699479 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1599607699479 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1599607699479 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1600299289286 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1600299289286 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 16 19:34:49 2020 " "Processing started: Wed Sep 16 19:34:49 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1600299289286 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1600299289286 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1600299289286 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1600299289446 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1600299289456 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4524 " "Peak virtual memory: 4524 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1600299289606 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 16 19:34:49 2020 " "Processing ended: Wed Sep 16 19:34:49 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1600299289606 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1600299289606 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1600299289606 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1600299289606 ""}

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@ -1,3 +1,3 @@
Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Version_Index = 302049280
Creation_Time = Tue Sep 08 19:25:14 2020
Creation_Time = Wed Sep 16 19:33:27 2020

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@ -1,39 +0,0 @@
{ "Info" "IQCU_PARALLEL_AUTODETECT_ONE_PROCESSOR" "" "Only one processor detected - disabling parallel compilation" { } { } 0 20029 "Only one processor detected - disabling parallel compilation" 0 0 "Fitter" 0 -1 1590186805031 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2E EPM240T100C5 " "Selected device EPM240T100C5 for design \"RAM2E\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1590186805156 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1590186805922 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1590186805922 ""}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1590186806281 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1590186806422 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1590186806640 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1590186806640 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1590186806640 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1590186806640 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1590186806640 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1590186806640 ""}
{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1590186806953 ""}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DRCLK " "Node: DRCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1590186807015 "|RAM2E|DRCLK"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ARCLK " "Node: ARCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1590186807015 "|RAM2E|ARCLK"}
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1590186807031 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1590186807031 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1590186807031 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 69.841 C14M " " 69.841 C14M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1590186807031 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1590186807031 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1590186807047 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1590186807062 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1590186807078 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C14M Global clock in PIN 12 " "Automatically promoted signal \"C14M\" to use Global clock in PIN 12" { } { { "RAM2E.v" "" { Text "Z:/Repos/RAM2E/cpld/RAM2E.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1590186807156 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1590186807172 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1590186807187 ""}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1590186807344 ""}
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1590186807344 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1590186807515 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1590186807578 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1590186807594 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1590186807609 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1590186807672 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1590186808625 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1590186809125 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1590186809156 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1590186810219 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1590186810234 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1590186810406 ""}
{ "Info" "IFITAPI_FITAPI_VPR_STATUS_DELAY_ADDED_FOR_HOLD" "4e+01 ns 2.7% " "4e+01 ns of routing delay (approximately 2.7% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report." { } { } 0 170089 "%1!s! of routing delay (approximately %2!s! of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report." 0 0 "Fitter" 0 -1 1590186810875 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "20 " "Router estimated average interconnect usage is 20% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "20 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Z:/Repos/RAM2E/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1590186810984 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1590186810984 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1590186811359 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.41 " "Total time spent on timing analysis during the Fitter is 0.41 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1590186811500 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1590186811531 ""}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1590186811625 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/RAM2E/cpld/output_files/RAM2E.fit.smsg " "Generated suppressed messages file Z:/Repos/RAM2E/cpld/output_files/RAM2E.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1590186812422 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "363 " "Peak virtual memory: 363 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1590186813875 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri May 22 18:33:32 2020 " "Processing ended: Fri May 22 18:33:32 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1590186813875 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:18 " "Elapsed time: 00:00:18" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1590186813875 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:10 " "Total CPU time (on all processors): 00:00:10" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1590186813875 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1590186813875 ""}

View File

@ -1,39 +0,0 @@
{ "Info" "IQCU_PARALLEL_AUTODETECT_ONE_PROCESSOR" "" "Only one processor detected - disabling parallel compilation" { } { } 0 20029 "Only one processor detected - disabling parallel compilation" 0 0 "Fitter" 0 -1 1590186869219 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2E EPM240T100C5 " "Selected device EPM240T100C5 for design \"RAM2E\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1590186869251 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1590186870126 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1590186870126 ""}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1590186870391 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1590186870438 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1590186870673 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1590186870673 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1590186870673 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1590186870673 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1590186870673 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1590186870673 ""}
{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1590186870954 ""}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DRCLK " "Node: DRCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1590186871032 "|RAM2E|DRCLK"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ARCLK " "Node: ARCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1590186871032 "|RAM2E|ARCLK"}
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1590186871048 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1590186871063 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1590186871063 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 69.841 C14M " " 69.841 C14M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1590186871063 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1590186871063 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1590186871079 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1590186871079 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1590186871110 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C14M Global clock in PIN 12 " "Automatically promoted signal \"C14M\" to use Global clock in PIN 12" { } { { "RAM2E.v" "" { Text "Z:/Repos/RAM2E/cpld/RAM2E.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1590186871126 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1590186871141 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1590186871141 ""}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1590186871235 ""}
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1590186871235 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1590186871329 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1590186871344 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1590186871344 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1590186871344 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1590186871376 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1590186872032 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1590186872610 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1590186872673 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1590186874345 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Fitter placement operations ending: elapsed time is 00:00:02" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1590186874391 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1590186874657 ""}
{ "Info" "IFITAPI_FITAPI_VPR_STATUS_DELAY_ADDED_FOR_HOLD" "4e+01 ns 2.7% " "4e+01 ns of routing delay (approximately 2.7% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report." { } { } 0 170089 "%1!s! of routing delay (approximately %2!s! of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report." 0 0 "Fitter" 0 -1 1590186875282 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "20 " "Router estimated average interconnect usage is 20% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "20 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "Z:/Repos/RAM2E/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1590186875423 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1590186875423 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1590186875642 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.55 " "Total time spent on timing analysis during the Fitter is 0.55 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1590186875688 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1590186875688 ""}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1590186875829 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "Z:/Repos/RAM2E/cpld/output_files/RAM2E.fit.smsg " "Generated suppressed messages file Z:/Repos/RAM2E/cpld/output_files/RAM2E.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1590186876126 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "363 " "Peak virtual memory: 363 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1590186877782 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri May 22 18:34:36 2020 " "Processing ended: Fri May 22 18:34:36 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1590186877782 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1590186877782 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Total CPU time (on all processors): 00:00:09" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1590186877782 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1590186877782 ""}

View File

@ -1,40 +0,0 @@
{ "Info" "IQCU_PARALLEL_AUTODETECT_ONE_PROCESSOR" "" "Only one processor detected - disabling parallel compilation" { } { } 0 20029 "Only one processor detected - disabling parallel compilation" 0 0 "Fitter" 0 -1 1590959452243 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2E EPM240T100C5 " "Selected device EPM240T100C5 for design \"RAM2E\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1590959452274 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1590959452540 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1590959452540 ""}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1590959452837 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1590959452868 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1590959453087 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1590959453087 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1590959453087 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1590959453087 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1590959453087 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1590959453087 ""}
{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1590959453353 ""}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DRCLK " "Node: DRCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1590959453399 "|RAM2E|DRCLK"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ARCLK " "Node: ARCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1590959453399 "|RAM2E|ARCLK"}
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1590959453415 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1590959453415 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1590959453415 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 69.841 C14M " " 69.841 C14M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1590959453415 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1590959453415 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1590959453415 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1590959453431 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1590959453446 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C14M Global clock in PIN 12 " "Automatically promoted signal \"C14M\" to use Global clock in PIN 12" { } { { "RAM2E.v" "" { Text "//vmware-host/Shared Folders/Repos/RAM2E/cpld/RAM2E.v" 9 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1590959453462 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1590959453462 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1590959453462 ""}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1590959453540 ""}
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1590959453556 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1590959453634 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1590959453649 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1590959453649 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1590959453649 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1590959453728 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1590959454024 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1590959454290 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1590959454306 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1590959454837 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1590959454837 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1590959454946 ""}
{ "Info" "IFITAPI_FITAPI_VPR_STATUS_DELAY_ADDED_FOR_HOLD" "4e+01 ns 2.8% " "4e+01 ns of routing delay (approximately 2.8% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report." { } { } 0 170089 "%1!s! of routing delay (approximately %2!s! of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report." 0 0 "Fitter" 0 -1 1590959455321 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "18 " "Router estimated average interconnect usage is 18% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "18 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "//vmware-host/Shared Folders/Repos/RAM2E/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1590959455415 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1590959455415 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1590959455665 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.28 " "Total time spent on timing analysis during the Fitter is 0.28 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1590959455696 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1590959455712 ""}
{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1590959455728 ""}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1590959455743 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/Repos/RAM2E/cpld/output_files/RAM2E.fit.smsg " "Generated suppressed messages file /Repos/RAM2E/cpld/output_files/RAM2E.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1590959455946 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus II 32-bit " "Quartus II 32-bit Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "366 " "Peak virtual memory: 366 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1590959457103 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 31 17:10:56 2020 " "Processing ended: Sun May 31 17:10:56 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1590959457103 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1590959457103 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1590959457103 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1590959457103 ""}

View File

@ -1,38 +1,39 @@
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1599607695785 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2E 5M240ZT100C5 " "Selected device 5M240ZT100C5 for design \"RAM2E\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1599607695785 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1599607695835 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1599607695835 ""}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1599607696066 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1599607696086 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M80ZT100C5 " "Device 5M80ZT100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1599607696246 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M80ZT100I5 " "Device 5M80ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1599607696246 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M160ZT100C5 " "Device 5M160ZT100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1599607696246 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M160ZT100I5 " "Device 5M160ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1599607696246 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M240ZT100I5 " "Device 5M240ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1599607696246 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M570ZT100C5 " "Device 5M570ZT100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1599607696246 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M570ZT100I5 " "Device 5M570ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1599607696246 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1599607696246 ""}
{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1599607696496 ""}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DRCLK " "Node: DRCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1599607696506 "|RAM2E|DRCLK"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ARCLK " "Node: ARCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1599607696506 "|RAM2E|ARCLK"}
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1599607696516 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1599607696516 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1599607696516 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 69.841 C14M " " 69.841 C14M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1599607696516 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1599607696516 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1599607696526 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1599607696526 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1599607696526 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C14M Global clock in PIN 12 " "Automatically promoted signal \"C14M\" to use Global clock in PIN 12" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 8 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1599607696536 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1599607696536 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1599607696546 ""}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1599607696566 ""}
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1599607696566 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1599607696606 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1599607696606 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1599607696606 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1599607696606 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1599607696666 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1599607697106 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1599607697246 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1599607697256 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1599607697511 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1599607697511 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1599607697541 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "17 " "Router estimated average interconnect usage is 17% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "17 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 17% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 17% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 17% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1599607697709 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1599607697709 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1599607697869 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.13 " "Total time spent on timing analysis during the Fitter is 0.13 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1599607697879 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1599607697879 ""}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1599607697909 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.fit.smsg " "Generated suppressed messages file C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1599607697979 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4771 " "Peak virtual memory: 4771 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1599607698049 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 08 19:28:18 2020 " "Processing ended: Tue Sep 08 19:28:18 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1599607698049 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1599607698049 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1599607698049 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1599607698049 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1600299287061 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2E 5M240ZT100C5 " "Selected device 5M240ZT100C5 for design \"RAM2E\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1600299287063 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1600299287091 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1600299287091 ""}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1600299287121 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1600299287126 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M80ZT100C5 " "Device 5M80ZT100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1600299287188 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M80ZT100I5 " "Device 5M80ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1600299287188 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M160ZT100C5 " "Device 5M160ZT100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1600299287188 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M160ZT100I5 " "Device 5M160ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1600299287188 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M240ZT100I5 " "Device 5M240ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1600299287188 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M570ZT100C5 " "Device 5M570ZT100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1600299287188 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M570ZT100I5 " "Device 5M570ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1600299287188 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1600299287188 ""}
{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1600299287248 ""}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DRCLK " "Node: DRCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1600299287250 "|RAM2E|DRCLK"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ARCLK " "Node: ARCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1600299287250 "|RAM2E|ARCLK"}
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1600299287251 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1600299287252 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1600299287252 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 69.841 C14M " " 69.841 C14M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1600299287252 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1600299287252 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1600299287254 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1600299287254 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1600299287256 ""}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C14M Global clock in PIN 12 " "Automatically promoted signal \"C14M\" to use Global clock in PIN 12" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 8 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1600299287261 ""}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1600299287261 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1600299287262 ""}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1600299287275 ""}
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1600299287275 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1600299287290 ""}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1600299287290 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1600299287290 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1600299287290 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1600299287310 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1600299287380 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1600299287510 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1600299287520 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1600299287742 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1600299287742 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1600299287762 ""}
{ "Info" "IFITAPI_FITAPI_VPR_STATUS_DELAY_ADDED_FOR_HOLD" "2e+01 ns 1.2% " "2e+01 ns of routing delay (approximately 1.2% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report." { } { } 0 170089 "%1!s! of routing delay (approximately %2!s! of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report." 0 0 "Fitter" 0 -1 1600299287883 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "19 " "Router estimated average interconnect usage is 19% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "19 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1600299287903 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1600299287903 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1600299288022 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.13 " "Total time spent on timing analysis during the Fitter is 0.13 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1600299288022 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1600299288022 ""}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1600299288047 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.fit.smsg " "Generated suppressed messages file C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1600299288095 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4767 " "Peak virtual memory: 4767 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1600299288155 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 16 19:34:48 2020 " "Processing ended: Wed Sep 16 19:34:48 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1600299288155 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1600299288155 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1600299288155 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1600299288155 ""}

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@ -19,7 +19,16 @@ C14M => RWBank[5].CLK
C14M => RWBank[6].CLK
C14M => RWBank[7].CLK
C14M => RWSel.CLK
C14M => Areg[0].CLK
C14M => Areg[1].CLK
C14M => Areg[2].CLK
C14M => Areg[3].CLK
C14M => Areg[4].CLK
C14M => Areg[5].CLK
C14M => Areg[6].CLK
C14M => Areg[7].CLK
C14M => Ready.CLK
C14M => DOEEN.CLK
C14M => DQMH~reg0.CLK
C14M => DQML~reg0.CLK
C14M => BA[0]~reg0.CLK
@ -112,49 +121,54 @@ nWE => comb.IN0
nWE => RWSel.IN1
nWE80 => nRWE.DATAB
nWE80 => RDOE.IN0
nEN80 => nCS.DATAB
nEN80 => nCS.DATAB
nEN80 => comb.IN1
nEN80 => RDOE.IN1
nEN80 => CKE.DATAB
nEN80 => CKE.DATAB
nEN80 => CKE.DATAB
nC07X => RWSel.IN1
Ain[0] => RA.DATAB
Ain[0] => RA.DATAB
Ain[0] => RA.DATAB
Ain[0] => RA.DATAB
Ain[0] => RA.DATAB
Ain[1] => RA.DATAB
Ain[0] => Areg.DATAB
Ain[1] => RA.DATAB
Ain[1] => RA.DATAB
Ain[1] => RA.DATAB
Ain[1] => RA.DATAB
Ain[1] => Areg.DATAB
Ain[2] => RA.DATAB
Ain[2] => RA.DATAB
Ain[2] => RA.DATAB
Ain[2] => RA.DATAB
Ain[2] => RA.DATAB
Ain[3] => RA.DATAB
Ain[2] => Areg.DATAB
Ain[3] => RA.DATAB
Ain[3] => RA.DATAB
Ain[3] => RA.DATAB
Ain[3] => RA.DATAB
Ain[3] => Areg.DATAB
Ain[4] => RA.DATAB
Ain[4] => RA.DATAB
Ain[4] => RA.DATAB
Ain[4] => RA.DATAB
Ain[4] => RA.DATAB
Ain[5] => RA.DATAB
Ain[4] => Areg.DATAB
Ain[5] => RA.DATAB
Ain[5] => RA.DATAB
Ain[5] => RA.DATAB
Ain[5] => RA.DATAB
Ain[5] => Areg.DATAB
Ain[6] => RA.DATAB
Ain[6] => RA.DATAB
Ain[6] => RA.DATAB
Ain[6] => RA.DATAB
Ain[6] => RA.DATAB
Ain[7] => RA.DATAB
Ain[6] => Areg.DATAB
Ain[7] => RA.DATAB
Ain[7] => RA.DATAB
Ain[7] => RA.DATAB
Ain[7] => RA.DATAB
Ain[7] => Areg.DATAB
Din[0] => RWBank.IN1
Din[0] => RD[0].DATAIN
Din[0] => RWMask.DATAB
@ -320,13 +334,13 @@ drshft => drshft.IN1
erase => erase.IN1
oscena => oscena.IN1
program => program.IN1
busy <= UFM_altufm_none_a7r:UFM_altufm_none_a7r_component.busy
drdout <= UFM_altufm_none_a7r:UFM_altufm_none_a7r_component.drdout
osc <= UFM_altufm_none_a7r:UFM_altufm_none_a7r_component.osc
rtpbusy <= UFM_altufm_none_a7r:UFM_altufm_none_a7r_component.rtpbusy
busy <= UFM_altufm_none_e4r:UFM_altufm_none_e4r_component.busy
drdout <= UFM_altufm_none_e4r:UFM_altufm_none_e4r_component.drdout
osc <= UFM_altufm_none_e4r:UFM_altufm_none_e4r_component.osc
rtpbusy <= UFM_altufm_none_e4r:UFM_altufm_none_e4r_component.rtpbusy
|RAM2E|UFM:UFM_inst|UFM_altufm_none_a7r:UFM_altufm_none_a7r_component
|RAM2E|UFM:UFM_inst|UFM_altufm_none_e4r:UFM_altufm_none_e4r_component
arclk => maxii_ufm_block1.ARCLK
ardin => maxii_ufm_block1.ARDIN
arshft => maxii_ufm_block1.ARSHFT

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@ -16,7 +16,7 @@
<TH>Output only Bidir</TH>
</TR>
<TR >
<TD >UFM_inst|UFM_altufm_none_a7r_component</TD>
<TD >UFM_inst|UFM_altufm_none_e4r_component</TD>
<TD >9</TD>
<TD >0</TD>
<TD >0</TD>

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@ -3,6 +3,6 @@
+----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; UFM_inst|UFM_altufm_none_a7r_component ; 9 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; UFM_inst|UFM_altufm_none_e4r_component ; 9 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; UFM_inst ; 9 ; 2 ; 0 ; 2 ; 4 ; 2 ; 2 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

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@ -1,20 +1,19 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1599607693606 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1599607693606 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 08 19:28:13 2020 " "Processing started: Tue Sep 08 19:28:13 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1599607693606 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1599607693606 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1599607693606 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1599607693837 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2E.v(37) " "Verilog HDL warning at RAM2E.v(37): extended using \"x\" or \"z\"" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 37 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1599607693867 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram2e.v 1 1 " "Found 1 design units, including 1 entities, in source file ram2e.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2E " "Found entity 1: RAM2E" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1599607693867 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1599607693867 ""}
{ "Warning" "WSGN_OUTDATED_CLEARBOX" "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v C:/Users/Zane/Documents/GitHub/RAM2E/cpld/db/UFM.v " "Clear box output file C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v is not compatible with the current compile. Used regenerated output file C:/Users/Zane/Documents/GitHub/RAM2E/cpld/db/UFM.v for elaboration" { } { } 0 12136 "Clear box output file %1!s! is not compatible with the current compile. Used regenerated output file %2!s! for elaboration" 0 0 "Quartus II" 0 -1 1599607693927 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "db/UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/db/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1599607693927 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "db/UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/db/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1599607693935 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file db/ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_a7r " "Found entity 1: UFM_altufm_none_a7r" { } { { "db/UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/db/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1599607693935 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "db/UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/db/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1599607693935 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1599607693935 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2E " "Elaborating entity \"RAM2E\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1599607693955 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 RAM2E.v(99) " "Verilog HDL assignment warning at RAM2E.v(99): truncated value with size 32 to match size of target (16)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 99 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1599607693963 "|RAM2E"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2E.v(102) " "Verilog HDL assignment warning at RAM2E.v(102): truncated value with size 32 to match size of target (4)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 102 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1599607693963 "|RAM2E"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 RAM2E.v(504) " "Verilog HDL assignment warning at RAM2E.v(504): truncated value with size 32 to match size of target (3)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 504 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1599607693963 "|RAM2E"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 RAM2E.v(521) " "Verilog HDL assignment warning at RAM2E.v(521): truncated value with size 32 to match size of target (3)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 521 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1599607693963 "|RAM2E"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "RAM2E.v" "UFM_inst" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 78 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1599607693965 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_a7r UFM:UFM_inst\|UFM_altufm_none_a7r:UFM_altufm_none_a7r_component " "Elaborating entity \"UFM_altufm_none_a7r\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_a7r:UFM_altufm_none_a7r_component\"" { } { { "db/UFM.v" "UFM_altufm_none_a7r_component" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/db/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1599607693965 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "263 " "Implemented 263 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "22 " "Implemented 22 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1599607694566 ""} { "Info" "ICUT_CUT_TM_OPINS" "39 " "Implemented 39 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1599607694566 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1599607694566 ""} { "Info" "ICUT_CUT_TM_LCELLS" "193 " "Implemented 193 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1599607694566 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1599607694566 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1599607694566 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.map.smsg " "Generated suppressed messages file C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1599607694614 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 6 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4577 " "Peak virtual memory: 4577 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1599607694716 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 08 19:28:14 2020 " "Processing ended: Tue Sep 08 19:28:14 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1599607694716 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1599607694716 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1599607694716 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1599607694716 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1600299285139 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1600299285139 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 16 19:34:45 2020 " "Processing started: Wed Sep 16 19:34:45 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1600299285139 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1600299285139 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1600299285139 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1600299285319 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2E.v(39) " "Verilog HDL warning at RAM2E.v(39): extended using \"x\" or \"z\"" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 39 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1600299285349 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram2e.v 1 1 " "Found 1 design units, including 1 entities, in source file ram2e.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2E " "Found entity 1: RAM2E" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1600299285349 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1600299285349 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1600299285389 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1600299285389 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_e4r " "Found entity 1: UFM_altufm_none_e4r" { } { { "UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1600299285389 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1600299285389 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1600299285389 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2E " "Elaborating entity \"RAM2E\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1600299285419 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 RAM2E.v(101) " "Verilog HDL assignment warning at RAM2E.v(101): truncated value with size 32 to match size of target (16)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 101 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1600299285419 "|RAM2E"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2E.v(104) " "Verilog HDL assignment warning at RAM2E.v(104): truncated value with size 32 to match size of target (4)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 104 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1600299285419 "|RAM2E"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 RAM2E.v(551) " "Verilog HDL assignment warning at RAM2E.v(551): truncated value with size 32 to match size of target (3)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 551 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1600299285419 "|RAM2E"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 RAM2E.v(568) " "Verilog HDL assignment warning at RAM2E.v(568): truncated value with size 32 to match size of target (3)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 568 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1600299285419 "|RAM2E"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "RAM2E.v" "UFM_inst" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 80 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1600299285429 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_e4r UFM:UFM_inst\|UFM_altufm_none_e4r:UFM_altufm_none_e4r_component " "Elaborating entity \"UFM_altufm_none_e4r\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_e4r:UFM_altufm_none_e4r_component\"" { } { { "UFM.v" "UFM_altufm_none_e4r_component" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1600299285439 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "278 " "Implemented 278 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "22 " "Implemented 22 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1600299285969 ""} { "Info" "ICUT_CUT_TM_OPINS" "39 " "Implemented 39 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1600299285969 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1600299285969 ""} { "Info" "ICUT_CUT_TM_LCELLS" "208 " "Implemented 208 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1600299285969 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1600299285969 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1600299285969 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.map.smsg " "Generated suppressed messages file C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1600299286009 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4575 " "Peak virtual memory: 4575 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1600299286049 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 16 19:34:46 2020 " "Processing ended: Wed Sep 16 19:34:46 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1600299286049 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1600299286049 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1600299286049 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1600299286049 ""}

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1590186927656 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "PowerPlay Power Analyzer Quartus II 32-bit " "Running Quartus II 32-bit PowerPlay Power Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1590186927656 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri May 22 18:35:27 2020 " "Processing started: Fri May 22 18:35:27 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1590186927656 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1590186927656 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_pow --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E " "Command: quartus_pow --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1590186927656 ""}
{ "Error" "EPAN_QSTA_NOT_AVAILABLE" "" "PowerPlay Power Analyzer (quartus_pow) cannot be run. The required timing data is not available. Run TimeQuest Timing Analyzer (quartus_sta)." { } { } 0 215048 "PowerPlay Power Analyzer (quartus_pow) cannot be run. The required timing data is not available. Run TimeQuest Timing Analyzer (quartus_sta)." 0 0 "Quartus II" 0 -1 1590186929219 ""}
{ "Error" "EQEXE_ERROR_COUNT" "PowerPlay Power Analyzer 1 0 s Quartus II 32-bit " "Quartus II 32-bit PowerPlay Power Analyzer was unsuccessful. 1 error, 0 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "267 " "Peak virtual memory: 267 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1590186929578 ""} { "Error" "EQEXE_END_BANNER_TIME" "Fri May 22 18:35:29 2020 " "Processing ended: Fri May 22 18:35:29 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1590186929578 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1590186929578 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1590186929578 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1590186929578 ""}

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@ -1,22 +1,22 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1599607700619 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1599607700619 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 08 19:28:20 2020 " "Processing started: Tue Sep 08 19:28:20 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1599607700619 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1599607700619 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2E -c RAM2E " "Command: quartus_sta RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1599607700620 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1599607700695 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1599607700791 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1599607700831 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1599607700831 ""}
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1599607700861 ""}
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1599607701084 ""}
{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1599607701152 ""}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DRCLK " "Node: DRCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1599607701162 "|RAM2E|DRCLK"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ARCLK " "Node: ARCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1599607701162 "|RAM2E|ARCLK"}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1599607701162 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 22.276 " "Worst-case setup slack is 22.276" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1599607701200 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1599607701200 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 22.276 0.000 C14M " " 22.276 0.000 C14M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1599607701200 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1599607701200 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 3.130 " "Worst-case hold slack is 3.130" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1599607701210 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1599607701210 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.130 0.000 C14M " " 3.130 0.000 C14M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1599607701210 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1599607701210 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1599607701220 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1599607701220 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 34.581 " "Worst-case minimum pulse width slack is 34.581" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1599607701230 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1599607701230 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 34.581 0.000 C14M " " 34.581 0.000 C14M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1599607701230 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1599607701230 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1599607701290 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1599607701310 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1599607701310 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4528 " "Peak virtual memory: 4528 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1599607701390 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 08 19:28:21 2020 " "Processing ended: Tue Sep 08 19:28:21 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1599607701390 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1599607701390 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1599607701390 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1599607701390 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1600299290603 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1600299290603 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 16 19:34:50 2020 " "Processing started: Wed Sep 16 19:34:50 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1600299290603 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1600299290603 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2E -c RAM2E " "Command: quartus_sta RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1600299290603 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1600299290654 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1600299290732 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1600299290762 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1600299290762 ""}
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1600299290792 ""}
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1600299291033 ""}
{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1600299291181 ""}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DRCLK " "Node: DRCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1600299291191 "|RAM2E|DRCLK"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ARCLK " "Node: ARCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1600299291191 "|RAM2E|ARCLK"}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1600299291191 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 22.294 " "Worst-case setup slack is 22.294" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600299291221 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600299291221 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 22.294 0.000 C14M " " 22.294 0.000 C14M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600299291221 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1600299291221 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 3.117 " "Worst-case hold slack is 3.117" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600299291231 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600299291231 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.117 0.000 C14M " " 3.117 0.000 C14M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600299291231 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1600299291231 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1600299291241 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1600299291241 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 34.581 " "Worst-case minimum pulse width slack is 34.581" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600299291251 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600299291251 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 34.581 0.000 C14M " " 34.581 0.000 C14M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600299291251 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1600299291251 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1600299291301 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1600299291321 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1600299291321 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4522 " "Peak virtual memory: 4522 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1600299291391 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 16 19:34:51 2020 " "Processing ended: Wed Sep 16 19:34:51 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1600299291391 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1600299291391 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1600299291391 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1600299291391 ""}

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@ -1,6 +1,6 @@
start_full_compilation:s:00:00:08
start_full_compilation:s:00:00:07
start_analysis_synthesis:s:00:00:02-start_full_compilation
start_analysis_elaboration:s-start_full_compilation
start_fitter:s:00:00:03-start_full_compilation
start_assembler:s:00:00:02-start_full_compilation
start_assembler:s:00:00:01-start_full_compilation
start_timing_analyzer:s:00:00:01-start_full_compilation

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@ -1,269 +0,0 @@
// megafunction wizard: %ALTUFM_NONE%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTUFM_NONE
// ============================================================
// File Name: UFM.v
// Megafunction Name(s):
// ALTUFM_NONE
//
// Simulation Library Files(s):
// maxii
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altufm_none CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="MAX V" ERASE_TIME=500000000 LPM_FILE="RAM2E.mif" OSC_FREQUENCY=180000 PORT_ARCLKENA="PORT_UNUSED" PORT_DRCLKENA="PORT_UNUSED" PROGRAM_TIME=1600000 WIDTH_UFM_ADDRESS=9 arclk ardin arshft busy drclk drdin drdout drshft erase osc oscena program rtpbusy
//VERSION_BEGIN 13.0 cbx_a_gray2bin 2013:06:12:18:03:43:SJ cbx_a_graycounter 2013:06:12:18:03:43:SJ cbx_altufm_none 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_maxii 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = maxv_ufm 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module UFM_altufm_none_a7r
(
arclk,
ardin,
arshft,
busy,
drclk,
drdin,
drdout,
drshft,
erase,
osc,
oscena,
program,
rtpbusy) ;
input arclk;
input ardin;
input arshft;
output busy;
input drclk;
input drdin;
output drdout;
input drshft;
input erase;
output osc;
input oscena;
input program;
output rtpbusy;
wire wire_maxii_ufm_block1_bgpbusy;
wire wire_maxii_ufm_block1_busy;
wire wire_maxii_ufm_block1_drdout;
wire wire_maxii_ufm_block1_osc;
wire ufm_arclk;
wire ufm_ardin;
wire ufm_arshft;
wire ufm_bgpbusy;
wire ufm_busy;
wire ufm_drclk;
wire ufm_drdin;
wire ufm_drdout;
wire ufm_drshft;
wire ufm_erase;
wire ufm_osc;
wire ufm_oscena;
wire ufm_program;
maxv_ufm maxii_ufm_block1
(
.arclk(ufm_arclk),
.ardin(ufm_ardin),
.arshft(ufm_arshft),
.bgpbusy(wire_maxii_ufm_block1_bgpbusy),
.busy(wire_maxii_ufm_block1_busy),
.drclk(ufm_drclk),
.drdin(ufm_drdin),
.drdout(wire_maxii_ufm_block1_drdout),
.drshft(ufm_drshft),
.erase(ufm_erase),
.osc(wire_maxii_ufm_block1_osc),
.oscena(ufm_oscena),
.program(ufm_program)
// synopsys translate_off
,
.ctrl_bgpbusy(1'b0),
.devclrn(1'b1),
.devpor(1'b1),
.sbdin(1'b0),
.sbdout()
// synopsys translate_on
);
defparam
maxii_ufm_block1.address_width = 9,
maxii_ufm_block1.erase_time = 500000000,
maxii_ufm_block1.init_file = "RAM2E.mif",
maxii_ufm_block1.mem1 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem10 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem11 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem12 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem13 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem14 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem15 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem16 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem2 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem3 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem4 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem5 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem6 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem7 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem8 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.mem9 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.osc_sim_setting = 180000,
maxii_ufm_block1.program_time = 1600000,
maxii_ufm_block1.lpm_type = "maxv_ufm";
assign
busy = ufm_busy,
drdout = ufm_drdout,
osc = ufm_osc,
rtpbusy = ufm_bgpbusy,
ufm_arclk = arclk,
ufm_ardin = ardin,
ufm_arshft = arshft,
ufm_bgpbusy = wire_maxii_ufm_block1_bgpbusy,
ufm_busy = wire_maxii_ufm_block1_busy,
ufm_drclk = drclk,
ufm_drdin = drdin,
ufm_drdout = wire_maxii_ufm_block1_drdout,
ufm_drshft = drshft,
ufm_erase = erase,
ufm_osc = wire_maxii_ufm_block1_osc,
ufm_oscena = oscena,
ufm_program = program;
endmodule //UFM_altufm_none_a7r
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module UFM (
arclk,
ardin,
arshft,
drclk,
drdin,
drshft,
erase,
oscena,
program,
busy,
drdout,
osc,
rtpbusy);
input arclk;
input ardin;
input arshft;
input drclk;
input drdin;
input drshft;
input erase;
input oscena;
input program;
output busy;
output drdout;
output osc;
output rtpbusy;
wire sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire sub_wire3;
wire osc = sub_wire0;
wire rtpbusy = sub_wire1;
wire drdout = sub_wire2;
wire busy = sub_wire3;
UFM_altufm_none_a7r UFM_altufm_none_a7r_component (
.arshft (arshft),
.drclk (drclk),
.erase (erase),
.program (program),
.arclk (arclk),
.drdin (drdin),
.oscena (oscena),
.ardin (ardin),
.drshft (drshft),
.osc (sub_wire0),
.rtpbusy (sub_wire1),
.drdout (sub_wire2),
.busy (sub_wire3));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX II"
// Retrieval info: CONSTANT: ERASE_TIME NUMERIC "500000000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX II"
// Retrieval info: CONSTANT: LPM_FILE STRING "RAM2E.mif"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altufm_none"
// Retrieval info: CONSTANT: OSC_FREQUENCY NUMERIC "180000"
// Retrieval info: CONSTANT: PORT_ARCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_DRCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PROGRAM_TIME NUMERIC "1600000"
// Retrieval info: CONSTANT: WIDTH_UFM_ADDRESS NUMERIC "9"
// Retrieval info: USED_PORT: arclk 0 0 0 0 INPUT NODEFVAL "arclk"
// Retrieval info: CONNECT: @arclk 0 0 0 0 arclk 0 0 0 0
// Retrieval info: USED_PORT: ardin 0 0 0 0 INPUT NODEFVAL "ardin"
// Retrieval info: CONNECT: @ardin 0 0 0 0 ardin 0 0 0 0
// Retrieval info: USED_PORT: arshft 0 0 0 0 INPUT NODEFVAL "arshft"
// Retrieval info: CONNECT: @arshft 0 0 0 0 arshft 0 0 0 0
// Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy"
// Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
// Retrieval info: USED_PORT: drclk 0 0 0 0 INPUT NODEFVAL "drclk"
// Retrieval info: CONNECT: @drclk 0 0 0 0 drclk 0 0 0 0
// Retrieval info: USED_PORT: drdin 0 0 0 0 INPUT NODEFVAL "drdin"
// Retrieval info: CONNECT: @drdin 0 0 0 0 drdin 0 0 0 0
// Retrieval info: USED_PORT: drdout 0 0 0 0 OUTPUT NODEFVAL "drdout"
// Retrieval info: CONNECT: drdout 0 0 0 0 @drdout 0 0 0 0
// Retrieval info: USED_PORT: drshft 0 0 0 0 INPUT NODEFVAL "drshft"
// Retrieval info: CONNECT: @drshft 0 0 0 0 drshft 0 0 0 0
// Retrieval info: USED_PORT: erase 0 0 0 0 INPUT NODEFVAL "erase"
// Retrieval info: CONNECT: @erase 0 0 0 0 erase 0 0 0 0
// Retrieval info: USED_PORT: osc 0 0 0 0 OUTPUT NODEFVAL "osc"
// Retrieval info: CONNECT: osc 0 0 0 0 @osc 0 0 0 0
// Retrieval info: USED_PORT: oscena 0 0 0 0 INPUT NODEFVAL "oscena"
// Retrieval info: CONNECT: @oscena 0 0 0 0 oscena 0 0 0 0
// Retrieval info: USED_PORT: program 0 0 0 0 INPUT NODEFVAL "program"
// Retrieval info: CONNECT: @program 0 0 0 0 program 0 0 0 0
// Retrieval info: USED_PORT: rtpbusy 0 0 0 0 OUTPUT NODEFVAL "rtpbusy"
// Retrieval info: CONNECT: rtpbusy 0 0 0 0 @rtpbusy 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.qip TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.bsf TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM_inst.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM_bb.v TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.inc FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.cmp FALSE TRUE
// Retrieval info: LIB_FILE: maxii

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@ -1,31 +1,15 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1599607628183 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1599607628185 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 08 19:27:08 2020 " "Processing started: Tue Sep 08 19:27:08 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1599607628185 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1599607628185 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1599607628185 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1599607628412 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2E.v(37) " "Verilog HDL warning at RAM2E.v(37): extended using \"x\" or \"z\"" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 37 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1599607628450 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram2e.v 1 1 " "Found 1 design units, including 1 entities, in source file ram2e.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2E " "Found entity 1: RAM2E" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1599607628450 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1599607628450 ""}
{ "Warning" "WSGN_OUTDATED_CLEARBOX" "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v C:/Users/Zane/Documents/GitHub/RAM2E/cpld/db/UFM.v " "Clear box output file C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v is not compatible with the current compile. Used regenerated output file C:/Users/Zane/Documents/GitHub/RAM2E/cpld/db/UFM.v for elaboration" { } { } 0 12136 "Clear box output file %1!s! is not compatible with the current compile. Used regenerated output file %2!s! for elaboration" 0 0 "Quartus II" 0 -1 1599607628500 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "db/UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/db/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1599607628500 ""}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "db/UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/db/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1599607628500 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file db/ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_a7r " "Found entity 1: UFM_altufm_none_a7r" { } { { "db/UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/db/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1599607628500 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "db/UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/db/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1599607628500 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1599607628500 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2E " "Elaborating entity \"RAM2E\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1599607628530 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 RAM2E.v(99) " "Verilog HDL assignment warning at RAM2E.v(99): truncated value with size 32 to match size of target (16)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 99 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1599607628530 "|RAM2E"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2E.v(102) " "Verilog HDL assignment warning at RAM2E.v(102): truncated value with size 32 to match size of target (4)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 102 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1599607628530 "|RAM2E"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 RAM2E.v(504) " "Verilog HDL assignment warning at RAM2E.v(504): truncated value with size 32 to match size of target (3)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 504 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1599607628530 "|RAM2E"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 RAM2E.v(521) " "Verilog HDL assignment warning at RAM2E.v(521): truncated value with size 32 to match size of target (3)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 521 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1599607628530 "|RAM2E"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "RAM2E.v" "UFM_inst" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 78 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1599607628530 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_a7r UFM:UFM_inst\|UFM_altufm_none_a7r:UFM_altufm_none_a7r_component " "Elaborating entity \"UFM_altufm_none_a7r\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_a7r:UFM_altufm_none_a7r_component\"" { } { { "db/UFM.v" "UFM_altufm_none_a7r_component" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/db/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1599607628540 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "263 " "Implemented 263 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "22 " "Implemented 22 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1599607629190 ""} { "Info" "ICUT_CUT_TM_OPINS" "39 " "Implemented 39 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1599607629190 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1599607629190 ""} { "Info" "ICUT_CUT_TM_LCELLS" "193 " "Implemented 193 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1599607629190 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1599607629190 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1599607629190 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.map.smsg " "Generated suppressed messages file C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1599607629240 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 6 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4577 " "Peak virtual memory: 4577 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1599607629280 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Sep 08 19:27:09 2020 " "Processing ended: Tue Sep 08 19:27:09 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1599607629280 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1599607629280 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1599607629280 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1599607629280 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1599607630188 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1599607630189 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Sep 08 19:27:09 2020 " "Processing started: Tue Sep 08 19:27:09 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1599607630189 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1599607630189 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E " "Command: quartus_fit --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1599607630189 ""}
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1599607630242 ""}
{ "Info" "0" "" "Project = RAM2E" { } { } 0 0 "Project = RAM2E" 0 0 "Fitter" 0 0 1599607630242 ""}
{ "Info" "0" "" "Revision = RAM2E" { } { } 0 0 "Revision = RAM2E" 0 0 "Fitter" 0 0 1599607630242 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1599607630292 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2E 5M240ZT100C5 " "Selected device 5M240ZT100C5 for design \"RAM2E\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1599607630292 ""}
{ "Error" "ECUT_CUT_INVALID_SUPPLY_VOLTAGE_VALUE" "3.3V VCCINT " "Supply voltage value 3.3V set to the 'VCCINT' power rail is illegal for the selected device." { } { } 0 21191 "Supply voltage value %1!s! set to the '%2!s!' power rail is illegal for the selected device." 0 0 "Fitter" 0 -1 1599607630326 ""}
{ "Error" "EQEXE_ERROR_COUNT" "Fitter 1 1 Quartus II 64-Bit " "Quartus II 64-Bit Fitter was unsuccessful. 1 error, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "4685 " "Peak virtual memory: 4685 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1599607630446 ""} { "Error" "EQEXE_END_BANNER_TIME" "Tue Sep 08 19:27:10 2020 " "Processing ended: Tue Sep 08 19:27:10 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1599607630446 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1599607630446 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1599607630446 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1599607630446 ""}
{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 3 s 7 s " "Quartus II Full Compilation was unsuccessful. 3 errors, 7 warnings" { } { } 0 293001 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1599607631016 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1600299211916 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1600299211916 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 16 19:33:31 2020 " "Processing started: Wed Sep 16 19:33:31 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1600299211916 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1600299211916 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1600299211916 ""}
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1600299212097 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2E.v(39) " "Verilog HDL warning at RAM2E.v(39): extended using \"x\" or \"z\"" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 39 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1600299212130 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram2e.v 1 1 " "Found 1 design units, including 1 entities, in source file ram2e.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2E " "Found entity 1: RAM2E" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1600299212132 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1600299212132 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2E " "Elaborating entity \"RAM2E\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1600299212161 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 RAM2E.v(101) " "Verilog HDL assignment warning at RAM2E.v(101): truncated value with size 32 to match size of target (16)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 101 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1600299212163 "|RAM2E"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2E.v(104) " "Verilog HDL assignment warning at RAM2E.v(104): truncated value with size 32 to match size of target (4)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 104 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1600299212163 "|RAM2E"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 RAM2E.v(551) " "Verilog HDL assignment warning at RAM2E.v(551): truncated value with size 32 to match size of target (3)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 551 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1600299212165 "|RAM2E"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 RAM2E.v(568) " "Verilog HDL assignment warning at RAM2E.v(568): truncated value with size 32 to match size of target (3)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 568 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1600299212165 "|RAM2E"}
{ "Error" "ESGN_ENTITY_IS_MISSING" "UFM_inst UFM " "Node instance \"UFM_inst\" instantiates undefined entity \"UFM\"" { } { { "RAM2E.v" "UFM_inst" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 80 0 0 } } } 0 12006 "Node instance \"%1!s!\" instantiates undefined entity \"%2!s!\"" 0 0 "Quartus II" 0 -1 1600299212209 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.map.smsg " "Generated suppressed messages file C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1600299212248 ""}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1 5 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 1 error, 5 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "4566 " "Peak virtual memory: 4566 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1600299212288 ""} { "Error" "EQEXE_END_BANNER_TIME" "Wed Sep 16 19:33:32 2020 " "Processing ended: Wed Sep 16 19:33:32 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1600299212288 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1600299212288 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1600299212288 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1600299212288 ""}
{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 3 s 5 s " "Quartus II Full Compilation was unsuccessful. 3 errors, 5 warnings" { } { } 0 293001 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1600299212889 ""}

View File

@ -1,5 +1,5 @@
ERASE_TIME=500000000
INTENDED_DEVICE_FAMILY="MAX II"
INTENDED_DEVICE_FAMILY="MAX V"
LPM_FILE=RAM2E.mif
LPM_HINT=UNUSED
LPM_TYPE=altufm_none
@ -8,8 +8,7 @@ PORT_ARCLKENA=PORT_UNUSED
PORT_DRCLKENA=PORT_UNUSED
PROGRAM_TIME=1600000
WIDTH_UFM_ADDRESS=9
DEVICE_FAMILY="MAX II"
CBX_AUTO_BLACKBOX=ALL
DEVICE_FAMILY="MAX V"
CBX_AUTO_BLACKBOX=ALL
arclk
ardin

View File

@ -1,3 +0,0 @@
Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Version_Index = 302049280
Creation_Time = Wed May 20 18:25:28 2020

View File

@ -1,5 +1,5 @@
Assembler report for RAM2E
Tue Sep 08 19:28:19 2020
Wed Sep 16 19:34:49 2020
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -37,7 +37,7 @@ applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Tue Sep 08 19:28:19 2020 ;
; Assembler Status ; Successful - Wed Sep 16 19:34:49 2020 ;
; Revision Name ; RAM2E ;
; Top-level Entity Name ; RAM2E ;
; Family ; MAX V ;
@ -90,8 +90,8 @@ applicable agreement for further details.
; Option ; Setting ;
+----------------+---------------------------------------------------------------------------+
; Device ; 5M240ZT100C5 ;
; JTAG usercode ; 0x0016F835 ;
; Checksum ; 0x0016FC1D ;
; JTAG usercode ; 0x0016E4E9 ;
; Checksum ; 0x0016E859 ;
+----------------+---------------------------------------------------------------------------+
@ -101,14 +101,14 @@ applicable agreement for further details.
Info: *******************************************************************
Info: Running Quartus II 64-Bit Assembler
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Tue Sep 08 19:28:18 2020
Info: Processing started: Wed Sep 16 19:34:49 2020
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 4524 megabytes
Info: Processing ended: Tue Sep 08 19:28:19 2020
Info: Elapsed time: 00:00:01
Info: Processing ended: Wed Sep 16 19:34:49 2020
Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:00

View File

@ -1 +1 @@
Tue Sep 08 19:28:22 2020
Wed Sep 16 19:34:52 2020

View File

@ -1,5 +1,5 @@
Fitter report for RAM2E
Tue Sep 08 19:28:17 2020
Wed Sep 16 19:34:48 2020
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -57,14 +57,14 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------+
; Fitter Summary ;
+---------------------------+-------------------------------------------------+
; Fitter Status ; Successful - Tue Sep 08 19:28:17 2020 ;
; Fitter Status ; Successful - Wed Sep 16 19:34:48 2020 ;
; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; RAM2E ;
; Top-level Entity Name ; RAM2E ;
; Family ; MAX V ;
; Device ; 5M240ZT100C5 ;
; Timing Models ; Final ;
; Total logic elements ; 184 / 240 ( 77 % ) ;
; Total logic elements ; 199 / 240 ( 83 % ) ;
; Total pins ; 69 / 79 ( 87 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
@ -142,28 +142,28 @@ The pin-out file can be found in C:/Users/Zane/Documents/GitHub/RAM2E/cpld/outpu
+---------------------------------------------+--------------------+
; Resource ; Usage ;
+---------------------------------------------+--------------------+
; Total logic elements ; 184 / 240 ( 77 % ) ;
; -- Combinational with no register ; 78 ;
; -- Register only ; 17 ;
; -- Combinational with a register ; 89 ;
; Total logic elements ; 199 / 240 ( 83 % ) ;
; -- Combinational with no register ; 84 ;
; -- Register only ; 25 ;
; -- Combinational with a register ; 90 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 87 ;
; -- 3 input functions ; 42 ;
; -- 2 input functions ; 34 ;
; -- 4 input functions ; 99 ;
; -- 3 input functions ; 36 ;
; -- 2 input functions ; 35 ;
; -- 1 input functions ; 3 ;
; -- 0 input functions ; 1 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 170 ;
; -- normal mode ; 185 ;
; -- arithmetic mode ; 14 ;
; -- qfbk mode ; 9 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 13 ;
; -- synchronous clear/load mode ; 14 ;
; -- asynchronous clear/load mode ; 0 ;
; ; ;
; Total registers ; 106 / 240 ( 44 % ) ;
; Total LABs ; 22 / 24 ( 92 % ) ;
; Total registers ; 115 / 240 ( 48 % ) ;
; Total LABs ; 24 / 24 ( 100 % ) ;
; Logic elements in carry chains ; 15 ;
; Virtual pins ; 0 ;
; I/O pins ; 69 / 79 ( 87 % ) ;
@ -173,12 +173,12 @@ The pin-out file can be found in C:/Users/Zane/Documents/GitHub/RAM2E/cpld/outpu
; UFM blocks ; 1 / 1 ( 100 % ) ;
; Global clocks ; 1 / 4 ( 25 % ) ;
; JTAGs ; 0 / 1 ( 0 % ) ;
; Average interconnect usage (total/H/V) ; 23% / 23% / 22% ;
; Peak interconnect usage (total/H/V) ; 23% / 23% / 22% ;
; Maximum fan-out ; 106 ;
; Highest non-global fan-out ; 33 ;
; Total fan-out ; 793 ;
; Average fan-out ; 3.12 ;
; Average interconnect usage (total/H/V) ; 23% / 22% / 23% ;
; Peak interconnect usage (total/H/V) ; 23% / 22% / 23% ;
; Maximum fan-out ; 115 ;
; Highest non-global fan-out ; 25 ;
; Total fan-out ; 850 ;
; Average fan-out ; 3.16 ;
+---------------------------------------------+--------------------+
@ -187,26 +187,26 @@ The pin-out file can be found in C:/Users/Zane/Documents/GitHub/RAM2E/cpld/outpu
+--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Location assigned by ;
+--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+
; Ain[0] ; 56 ; 2 ; 8 ; 1 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ;
; Ain[1] ; 54 ; 2 ; 8 ; 1 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ;
; Ain[2] ; 43 ; 1 ; 6 ; 0 ; 3 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ;
; Ain[3] ; 47 ; 1 ; 6 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ;
; Ain[4] ; 44 ; 1 ; 6 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ;
; Ain[5] ; 34 ; 1 ; 3 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ;
; Ain[6] ; 39 ; 1 ; 5 ; 0 ; 3 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ;
; Ain[7] ; 53 ; 2 ; 8 ; 1 ; 3 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ;
; C14M ; 12 ; 1 ; 1 ; 3 ; 3 ; 106 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ;
; Din[0] ; 38 ; 1 ; 4 ; 0 ; 0 ; 11 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ;
; Din[1] ; 40 ; 1 ; 5 ; 0 ; 2 ; 10 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ;
; Din[2] ; 42 ; 1 ; 5 ; 0 ; 0 ; 11 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ;
; Ain[0] ; 56 ; 2 ; 8 ; 1 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ;
; Ain[1] ; 54 ; 2 ; 8 ; 1 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ;
; Ain[2] ; 43 ; 1 ; 6 ; 0 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ;
; Ain[3] ; 47 ; 1 ; 6 ; 0 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ;
; Ain[4] ; 44 ; 1 ; 6 ; 0 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ;
; Ain[5] ; 34 ; 1 ; 3 ; 0 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ;
; Ain[6] ; 39 ; 1 ; 5 ; 0 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ;
; Ain[7] ; 53 ; 2 ; 8 ; 1 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ;
; C14M ; 12 ; 1 ; 1 ; 3 ; 3 ; 115 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ;
; Din[0] ; 38 ; 1 ; 4 ; 0 ; 0 ; 9 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ;
; Din[1] ; 40 ; 1 ; 5 ; 0 ; 2 ; 11 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ;
; Din[2] ; 42 ; 1 ; 5 ; 0 ; 0 ; 9 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ;
; Din[3] ; 41 ; 1 ; 5 ; 0 ; 1 ; 9 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ;
; Din[4] ; 48 ; 1 ; 6 ; 0 ; 0 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ;
; Din[5] ; 49 ; 1 ; 7 ; 0 ; 2 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ;
; Din[5] ; 49 ; 1 ; 7 ; 0 ; 2 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ;
; Din[6] ; 36 ; 1 ; 4 ; 0 ; 2 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ;
; Din[7] ; 35 ; 1 ; 3 ; 0 ; 0 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ;
; Din[7] ; 35 ; 1 ; 3 ; 0 ; 0 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ;
; PHI1 ; 37 ; 1 ; 4 ; 0 ; 1 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ;
; nC07X ; 52 ; 2 ; 8 ; 1 ; 4 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ;
; nEN80 ; 28 ; 1 ; 2 ; 0 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ;
; nEN80 ; 28 ; 1 ; 2 ; 0 ; 1 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ;
; nWE ; 51 ; 1 ; 7 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ;
; nWE80 ; 33 ; 1 ; 3 ; 0 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ;
+--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+
@ -218,22 +218,22 @@ The pin-out file can be found in C:/Users/Zane/Documents/GitHub/RAM2E/cpld/outpu
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
; BA[0] ; 6 ; 1 ; 1 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; BA[1] ; 14 ; 1 ; 1 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; BA[1] ; 14 ; 1 ; 1 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; CKE ; 4 ; 1 ; 1 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; DQMH ; 100 ; 2 ; 2 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; DQML ; 98 ; 2 ; 2 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Dout[0] ; 77 ; 2 ; 7 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Dout[1] ; 76 ; 2 ; 7 ; 5 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Dout[2] ; 74 ; 2 ; 8 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; Dout[3] ; 75 ; 2 ; 7 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Dout[4] ; 73 ; 2 ; 8 ; 4 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; Dout[5] ; 72 ; 2 ; 8 ; 4 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Dout[6] ; 84 ; 2 ; 6 ; 5 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Dout[7] ; 85 ; 2 ; 5 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Dout[0] ; 77 ; 2 ; 7 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Dout[1] ; 76 ; 2 ; 7 ; 5 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Dout[2] ; 74 ; 2 ; 8 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; Dout[3] ; 75 ; 2 ; 7 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Dout[4] ; 73 ; 2 ; 8 ; 4 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; Dout[5] ; 72 ; 2 ; 8 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Dout[6] ; 84 ; 2 ; 6 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Dout[7] ; 85 ; 2 ; 5 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; RA[0] ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; RA[10] ; 16 ; 1 ; 1 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; RA[11] ; 7 ; 1 ; 1 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; RA[1] ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; RA[1] ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RA[2] ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; RA[3] ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; RA[4] ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
@ -242,20 +242,20 @@ The pin-out file can be found in C:/Users/Zane/Documents/GitHub/RAM2E/cpld/outpu
; RA[7] ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; RA[8] ; 17 ; 1 ; 1 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; RA[9] ; 15 ; 1 ; 1 ; 2 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[0] ; 70 ; 2 ; 8 ; 4 ; 4 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[1] ; 67 ; 2 ; 8 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[2] ; 69 ; 2 ; 8 ; 3 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[3] ; 62 ; 2 ; 8 ; 2 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[4] ; 71 ; 2 ; 8 ; 4 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[5] ; 68 ; 2 ; 8 ; 3 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[6] ; 58 ; 2 ; 8 ; 2 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[7] ; 57 ; 2 ; 8 ; 2 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[0] ; 70 ; 2 ; 8 ; 4 ; 4 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[1] ; 67 ; 2 ; 8 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[2] ; 69 ; 2 ; 8 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[3] ; 62 ; 2 ; 8 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[4] ; 71 ; 2 ; 8 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[5] ; 68 ; 2 ; 8 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[6] ; 58 ; 2 ; 8 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[7] ; 57 ; 2 ; 8 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; nCAS ; 3 ; 1 ; 1 ; 4 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; nCS ; 8 ; 1 ; 1 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; nDOE ; 55 ; 2 ; 8 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; nDOE ; 55 ; 2 ; 8 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; nRAS ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; nRWE ; 2 ; 1 ; 1 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; nVOE ; 50 ; 1 ; 7 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; nVOE ; 50 ; 1 ; 7 ; 0 ; 1 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
@ -264,14 +264,14 @@ The pin-out file can be found in C:/Users/Zane/Documents/GitHub/RAM2E/cpld/outpu
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
; RD[0] ; 97 ; 2 ; 3 ; 5 ; 3 ; 2 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; RDOE ; - ;
; RD[1] ; 90 ; 2 ; 4 ; 5 ; 1 ; 2 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; RDOE ; - ;
; RD[2] ; 99 ; 2 ; 2 ; 5 ; 1 ; 2 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; RDOE ; - ;
; RD[3] ; 89 ; 2 ; 4 ; 5 ; 0 ; 2 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; RDOE ; - ;
; RD[4] ; 91 ; 2 ; 4 ; 5 ; 2 ; 2 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; RDOE ; - ;
; RD[5] ; 92 ; 2 ; 3 ; 5 ; 0 ; 2 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; RDOE ; - ;
; RD[6] ; 95 ; 2 ; 3 ; 5 ; 1 ; 2 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; RDOE ; - ;
; RD[7] ; 96 ; 2 ; 3 ; 5 ; 2 ; 2 ; 0 ; no ; no ; yes ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; RDOE ; - ;
; RD[0] ; 97 ; 2 ; 3 ; 5 ; 3 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ;
; RD[1] ; 90 ; 2 ; 4 ; 5 ; 1 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ;
; RD[2] ; 99 ; 2 ; 2 ; 5 ; 1 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ;
; RD[3] ; 89 ; 2 ; 4 ; 5 ; 0 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ;
; RD[4] ; 91 ; 2 ; 4 ; 5 ; 2 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ;
; RD[5] ; 92 ; 2 ; 3 ; 5 ; 0 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ;
; RD[6] ; 95 ; 2 ; 3 ; 5 ; 1 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ;
; RD[7] ; 96 ; 2 ; 3 ; 5 ; 2 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
@ -339,12 +339,12 @@ The pin-out file can be found in C:/Users/Zane/Documents/GitHub/RAM2E/cpld/outpu
; 47 ; 37 ; 1 ; Ain[3] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 48 ; 38 ; 1 ; Din[4] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 49 ; 39 ; 1 ; Din[5] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 50 ; 40 ; 1 ; nVOE ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 50 ; 40 ; 1 ; nVOE ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; On ;
; 51 ; 41 ; 1 ; nWE ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 52 ; 42 ; 2 ; nC07X ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 53 ; 43 ; 2 ; Ain[7] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 54 ; 44 ; 2 ; Ain[1] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 55 ; 45 ; 2 ; nDOE ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 55 ; 45 ; 2 ; nDOE ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; On ;
; 56 ; 46 ; 2 ; Ain[0] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 57 ; 47 ; 2 ; Vout[7] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 58 ; 48 ; 2 ; Vout[6] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
@ -378,17 +378,17 @@ The pin-out file can be found in C:/Users/Zane/Documents/GitHub/RAM2E/cpld/outpu
; 86 ; 70 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 87 ; 71 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 88 ; 72 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
; 89 ; 73 ; 2 ; RD[3] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 90 ; 74 ; 2 ; RD[1] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 91 ; 75 ; 2 ; RD[4] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 92 ; 76 ; 2 ; RD[5] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 89 ; 73 ; 2 ; RD[3] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
; 90 ; 74 ; 2 ; RD[1] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
; 91 ; 75 ; 2 ; RD[4] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
; 92 ; 76 ; 2 ; RD[5] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
; 93 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 94 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 95 ; 77 ; 2 ; RD[6] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 96 ; 78 ; 2 ; RD[7] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 97 ; 79 ; 2 ; RD[0] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 95 ; 77 ; 2 ; RD[6] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
; 96 ; 78 ; 2 ; RD[7] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
; 97 ; 79 ; 2 ; RD[0] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
; 98 ; 80 ; 2 ; DQML ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 99 ; 81 ; 2 ; RD[2] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
; 99 ; 81 ; 2 ; RD[2] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
; 100 ; 82 ; 2 ; DQMH ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
+----------+------------+----------+----------------+--------+--------------+---------+------------+-----------------+----------+--------------+
Note: Pin directions (input, output or bidir) are based on device operating in user mode.
@ -418,9 +418,9 @@ Note: User assignments will override these defaults. The user specified values a
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+--------------+
; |RAM2E ; 184 (184) ; 106 ; 1 ; 69 ; 0 ; 78 (78) ; 17 (17) ; 89 (89) ; 15 (15) ; 9 (9) ; |RAM2E ; work ;
; |RAM2E ; 199 (199) ; 115 ; 1 ; 69 ; 0 ; 84 (84) ; 25 (25) ; 90 (90) ; 15 (15) ; 9 (9) ; |RAM2E ; work ;
; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|UFM:UFM_inst ; work ;
; |UFM_altufm_none_a7r:UFM_altufm_none_a7r_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|UFM:UFM_inst|UFM_altufm_none_a7r:UFM_altufm_none_a7r_component ; work ;
; |UFM_altufm_none_e4r:UFM_altufm_none_e4r_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|UFM:UFM_inst|UFM_altufm_none_e4r:UFM_altufm_none_e4r_component ; work ;
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
@ -507,16 +507,17 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+-------------+-------------+---------+---------------+--------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
+-------------+-------------+---------+---------------+--------+----------------------+------------------+
; C14M ; PIN_12 ; 106 ; Clock ; yes ; Global Clock ; GCLK0 ;
; CS[0]~2 ; LC_X7_Y3_N9 ; 3 ; Clock enable ; no ; -- ; -- ;
; C14M ; PIN_12 ; 115 ; Clock ; yes ; Global Clock ; GCLK0 ;
; CS[0]~2 ; LC_X6_Y1_N4 ; 3 ; Clock enable ; no ; -- ; -- ;
; Equal9~0 ; LC_X6_Y3_N7 ; 14 ; Clock enable ; no ; -- ; -- ;
; Equal9~1 ; LC_X6_Y3_N5 ; 8 ; Clock enable ; no ; -- ; -- ;
; RA[4]~1 ; LC_X2_Y2_N7 ; 8 ; Clock enable ; no ; -- ; -- ;
; RDOE ; LC_X2_Y2_N1 ; 8 ; Output enable ; no ; -- ; -- ;
; RWBank[4]~1 ; LC_X5_Y3_N1 ; 13 ; Clock enable ; no ; -- ; -- ;
; RWMask[4]~2 ; LC_X4_Y2_N8 ; 8 ; Clock enable ; no ; -- ; -- ;
; S[2] ; LC_X6_Y3_N0 ; 19 ; Sync. clear ; no ; -- ; -- ;
; UFMD[8]~5 ; LC_X4_Y4_N3 ; 7 ; Clock enable ; no ; -- ; -- ;
; Equal9~7 ; LC_X2_Y2_N7 ; 8 ; Clock enable ; no ; -- ; -- ;
; RA[4]~2 ; LC_X2_Y2_N5 ; 8 ; Clock enable ; no ; -- ; -- ;
; RDOE ; LC_X2_Y4_N6 ; 8 ; Output enable ; no ; -- ; -- ;
; RWBank[4]~1 ; LC_X7_Y2_N1 ; 13 ; Clock enable ; no ; -- ; -- ;
; RWMask[4]~2 ; LC_X5_Y2_N9 ; 8 ; Clock enable ; no ; -- ; -- ;
; S[1] ; LC_X6_Y3_N6 ; 23 ; Sync. clear ; no ; -- ; -- ;
; UFMD[8]~5 ; LC_X4_Y2_N7 ; 7 ; Clock enable ; no ; -- ; -- ;
+-------------+-------------+---------+---------------+--------+----------------------+------------------+
@ -525,7 +526,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+------+----------+---------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
+------+----------+---------+----------------------+------------------+
; C14M ; PIN_12 ; 106 ; Global Clock ; GCLK0 ;
; C14M ; PIN_12 ; 115 ; Global Clock ; GCLK0 ;
+------+----------+---------+----------------------+------------------+
@ -534,70 +535,73 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+----------------------------------------------------------------------------------------------+---------+
; Name ; Fan-Out ;
+----------------------------------------------------------------------------------------------+---------+
; S[0] ; 33 ;
; S[1] ; 27 ;
; Equal9~4 ; 22 ;
; S[2] ; 19 ;
; S[3] ; 18 ;
; S[0] ; 25 ;
; S[3] ; 24 ;
; Equal9~6 ; 23 ;
; S[1] ; 23 ;
; S[2] ; 23 ;
; Equal9~0 ; 14 ;
; RWBank[4]~1 ; 13 ;
; Din[2] ; 11 ;
; Din[0] ; 11 ;
; Din[1] ; 10 ;
; Din[1] ; 11 ;
; CS[1] ; 10 ;
; Din[3] ; 9 ;
; Din[2] ; 9 ;
; Din[0] ; 9 ;
; CS[0] ; 9 ;
; Din[7] ; 8 ;
; Din[6] ; 8 ;
; RWMask[4]~2 ; 8 ;
; RDOE ; 8 ;
; Equal9~7 ; 8 ;
; SetRWBankFF ; 8 ;
; CS[2] ; 8 ;
; RWSel ; 8 ;
; RA[4]~1 ; 8 ;
; RA[4]~2 ; 8 ;
; RA[4]~0 ; 8 ;
; Equal9~4 ; 8 ;
; FS[4] ; 8 ;
; Equal9~1 ; 8 ;
; Din[7] ; 7 ;
; Din[5] ; 7 ;
; Din[4] ; 7 ;
; UFMD[8]~5 ; 7 ;
; always1~9 ; 7 ;
; Din[5] ; 6 ;
; UFMReqErase ; 6 ;
; FS[5] ; 7 ;
; UFMInitDone ; 6 ;
; FS[5] ; 6 ;
; FS[3] ; 6 ;
; FS[0] ; 6 ;
; Equal4~0 ; 5 ;
; UFMReqErase ; 5 ;
; always1~1 ; 5 ;
; FS[3] ; 5 ;
; FS[2]~25 ; 5 ;
; FS[0] ; 5 ;
; FS[7]~19 ; 5 ;
; FS[15] ; 5 ;
; FS[14] ; 5 ;
; FS[13] ; 5 ;
; PHI1 ; 4 ;
; nEN80 ; 4 ;
; always1~6 ; 4 ;
; UFMD[13] ; 4 ;
; CmdTout[0] ; 4 ;
; UFMBitbang~0 ; 4 ;
; UFMEraseEN ; 4 ;
; UFMPrgmEN ; 4 ;
; Equal4~0 ; 4 ;
; Equal9~3 ; 4 ;
; always1~2 ; 4 ;
; Equal9~5 ; 4 ;
; DRCLK~0 ; 4 ;
; UFM:UFM_inst|UFM_altufm_none_a7r:UFM_altufm_none_a7r_component|wire_maxii_ufm_block1_drdout ; 4 ;
; UFM:UFM_inst|UFM_altufm_none_e4r:UFM_altufm_none_e4r_component|wire_maxii_ufm_block1_drdout ; 4 ;
; S[3]~9 ; 3 ;
; UFMD[11] ; 3 ;
; UFMD[9] ; 3 ;
; UFMD[10] ; 3 ;
; always1~6 ; 3 ;
; UFMD[12] ; 3 ;
; UFMD[8] ; 3 ;
; CS[0]~2 ; 3 ;
; CmdTout[1] ; 3 ;
; CS~0 ; 3 ;
; RWMaskSet~0 ; 3 ;
; always2~1 ; 3 ;
; RWMaskSet~1 ; 3 ;
; S~4 ; 3 ;
; Ready ; 3 ;
; S[3]~2 ; 3 ;
; always1~2 ; 3 ;
; UFMD[8]~4 ; 3 ;
; always1~0 ; 3 ;
; Equal10~4 ; 3 ;
; FS[2] ; 3 ;
@ -605,6 +609,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; always2~0 ; 3 ;
; Ready~0 ; 3 ;
; FS[6] ; 3 ;
; Equal9~2 ; 3 ;
; Equal10~1 ; 3 ;
; FS[12]~1 ; 3 ;
; RD[7]~7 ; 2 ;
@ -615,27 +620,32 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; RD[2]~2 ; 2 ;
; RD[1]~1 ; 2 ;
; RD[0]~0 ; 2 ;
; Ain[7] ; 2 ;
; Ain[6] ; 2 ;
; Ain[5] ; 2 ;
; Ain[4] ; 2 ;
; Ain[3] ; 2 ;
; Ain[2] ; 2 ;
; Ain[1] ; 2 ;
; Ain[0] ; 2 ;
; nWE80 ; 2 ;
; nEN80 ; 2 ;
; nWE ; 2 ;
; UFMD[14] ; 2 ;
; UFMEraseEN~0 ; 2 ;
; RWMask[4]~0 ; 2 ;
; UFMReqErase~3 ; 2 ;
; UFMBusyReg ; 2 ;
; UFMInitDone~0 ; 2 ;
; CmdTout[2] ; 2 ;
; Equal39~1 ; 2 ;
; RWMaskSet~1 ; 2 ;
; always2~10 ; 2 ;
; S~3 ; 2 ;
; UFMBusyReg ; 2 ;
; always1~3 ; 2 ;
; UFMD[8]~4 ; 2 ;
; RWBank[6] ; 2 ;
; Equal9~2 ; 2 ;
; DQML~0 ; 2 ;
; nRAS~2 ; 2 ;
; nRAS~1 ; 2 ;
; nCS~3 ; 2 ;
; nCS~2 ; 2 ;
; nCS~1 ; 2 ;
; nCS~0 ; 2 ;
; Equal12~0 ; 2 ;
; FS[7] ; 2 ;
; CKE~1 ; 2 ;
; Equal10~2 ; 2 ;
@ -652,20 +662,13 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; UFMProgram~_wirecell ; 1 ;
; UFMErase~_wirecell ; 1 ;
; nC07X ; 1 ;
; Ain[7] ; 1 ;
; Ain[6] ; 1 ;
; Ain[5] ; 1 ;
; Ain[4] ; 1 ;
; Ain[3] ; 1 ;
; Ain[2] ; 1 ;
; Ain[1] ; 1 ;
; Ain[0] ; 1 ;
; ~GND ; 1 ;
; UFMReqErase~4 ; 1 ;
; RWMaskSet ; 1 ;
; RWMask[4]~1 ; 1 ;
; always1~8 ; 1 ;
; always1~7 ; 1 ;
; Ready~1 ; 1 ;
; UFMReqErase~3 ; 1 ;
; UFMReqErase~2 ; 1 ;
; UFMReqErase~1 ; 1 ;
; UFMReqErase~0 ; 1 ;
@ -675,7 +678,6 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; always2~12 ; 1 ;
; Equal39~0 ; 1 ;
; always2~11 ; 1 ;
; always2~10 ; 1 ;
; always2~9 ; 1 ;
; always2~8 ; 1 ;
; always2~7 ; 1 ;
@ -684,8 +686,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; always2~4 ; 1 ;
; always2~3 ; 1 ;
; always2~2 ; 1 ;
; Equal27~1 ; 1 ;
; UFMBitbang~0 ; 1 ;
; always2~1 ; 1 ;
; RWMaskSet~0 ; 1 ;
; RWSel~0 ; 1 ;
; RWMask[6] ; 1 ;
; RWMask[3] ; 1 ;
@ -700,27 +702,37 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; UFMErase~0 ; 1 ;
; RTPBusyReg ; 1 ;
; UFMProgram~0 ; 1 ;
; DRCLKPulse ; 1 ;
; DRCLK~2 ; 1 ;
; DRCLK~1 ; 1 ;
; DRCLKPulse ; 1 ;
; Equal27~0 ; 1 ;
; UFMBitbang ; 1 ;
; RWBank[3] ; 1 ;
; RA~11 ; 1 ;
; RA~12 ; 1 ;
; RWBank[2] ; 1 ;
; RWBank[1] ; 1 ;
; RWBank[0] ; 1 ;
; RWBank[7] ; 1 ;
; Areg[7] ; 1 ;
; Areg[6] ; 1 ;
; Areg[5] ; 1 ;
; Areg[4] ; 1 ;
; Areg[3] ; 1 ;
; Areg[2] ; 1 ;
; Areg[1] ; 1 ;
; Areg[0] ; 1 ;
; RWBank[5] ; 1 ;
; RWBank[4] ; 1 ;
; nRWE~1 ; 1 ;
; Equal12~1 ; 1 ;
; nRWE~0 ; 1 ;
; nCAS~1 ; 1 ;
; nCAS~0 ; 1 ;
; FS[5]~29COUT1_50 ; 1 ;
; FS[5]~29 ; 1 ;
; FS[3]~27COUT1_46 ; 1 ;
; FS[3]~27 ; 1 ;
; nCS~2 ; 1 ;
; nRAS~0 ; 1 ;
; Equal12~0 ; 1 ;
; FS[3]~29COUT1_46 ; 1 ;
; FS[3]~29 ; 1 ;
; FS[5]~27COUT1_50 ; 1 ;
; FS[5]~27 ; 1 ;
; FS[1]~23COUT1_44 ; 1 ;
; FS[1]~23 ; 1 ;
; FS[4]~21COUT1_48 ; 1 ;
@ -728,6 +740,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; FS[6]~17COUT1_52 ; 1 ;
; FS[6]~17 ; 1 ;
; Equal10~3 ; 1 ;
; Equal9~3 ; 1 ;
; nCS~0 ; 1 ;
; CKE~2 ; 1 ;
; CKE~0 ; 1 ;
; FS[14]~13COUT1_64 ; 1 ;
; FS[14]~13 ; 1 ;
@ -774,6 +789,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Vout[1]~reg0 ; 1 ;
; Vout[0]~reg0 ; 1 ;
; comb~0 ; 1 ;
; DOEEN ; 1 ;
; Dout[7]~reg0 ; 1 ;
; Dout[6]~reg0 ; 1 ;
; Dout[5]~reg0 ; 1 ;
@ -782,8 +798,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Dout[2]~reg0 ; 1 ;
; Dout[1]~reg0 ; 1 ;
; Dout[0]~reg0 ; 1 ;
; UFM:UFM_inst|UFM_altufm_none_a7r:UFM_altufm_none_a7r_component|wire_maxii_ufm_block1_bgpbusy ; 1 ;
; UFM:UFM_inst|UFM_altufm_none_a7r:UFM_altufm_none_a7r_component|wire_maxii_ufm_block1_busy ; 1 ;
; UFM:UFM_inst|UFM_altufm_none_e4r:UFM_altufm_none_e4r_component|wire_maxii_ufm_block1_bgpbusy ; 1 ;
; UFM:UFM_inst|UFM_altufm_none_e4r:UFM_altufm_none_e4r_component|wire_maxii_ufm_block1_busy ; 1 ;
+----------------------------------------------------------------------------------------------+---------+
@ -792,30 +808,30 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+-----------------------------+--------------------+
; Other Routing Resource Type ; Usage ;
+-----------------------------+--------------------+
; C4s ; 146 / 784 ( 19 % ) ;
; Direct links ; 53 / 888 ( 6 % ) ;
; C4s ; 151 / 784 ( 19 % ) ;
; Direct links ; 54 / 888 ( 6 % ) ;
; Global clocks ; 1 / 4 ( 25 % ) ;
; LAB clocks ; 6 / 32 ( 19 % ) ;
; LUT chains ; 16 / 216 ( 7 % ) ;
; Local interconnects ; 281 / 888 ( 32 % ) ;
; R4s ; 132 / 704 ( 19 % ) ;
; LUT chains ; 14 / 216 ( 6 % ) ;
; Local interconnects ; 299 / 888 ( 34 % ) ;
; R4s ; 125 / 704 ( 18 % ) ;
+-----------------------------+--------------------+
+---------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+------------------------------+
; Number of Logic Elements (Average = 8.36) ; Number of LABs (Total = 22) ;
; Number of Logic Elements (Average = 8.29) ; Number of LABs (Total = 24) ;
+--------------------------------------------+------------------------------+
; 1 ; 2 ;
; 1 ; 3 ;
; 2 ; 0 ;
; 3 ; 1 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 1 ;
; 6 ; 0 ;
; 6 ; 1 ;
; 7 ; 0 ;
; 8 ; 3 ;
; 9 ; 0 ;
; 8 ; 1 ;
; 9 ; 3 ;
; 10 ; 15 ;
+--------------------------------------------+------------------------------+
@ -823,9 +839,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+-------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+------------------------------+
; LAB-wide Signals (Average = 1.45) ; Number of LABs (Total = 22) ;
; LAB-wide Signals (Average = 1.38) ; Number of LABs (Total = 24) ;
+------------------------------------+------------------------------+
; 1 Clock ; 21 ;
; 1 Clock ; 22 ;
; 1 Clock enable ; 7 ;
; 2 Clock enables ; 4 ;
+------------------------------------+------------------------------+
@ -834,20 +850,20 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+------------------------------+
; Number of Signals Sourced (Average = 8.77) ; Number of LABs (Total = 22) ;
; Number of Signals Sourced (Average = 8.67) ; Number of LABs (Total = 24) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 2 ;
; 1 ; 3 ;
; 2 ; 0 ;
; 3 ; 1 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 5 ; 1 ;
; 6 ; 1 ;
; 7 ; 0 ;
; 8 ; 3 ;
; 9 ; 0 ;
; 10 ; 13 ;
; 11 ; 0 ;
; 8 ; 1 ;
; 9 ; 3 ;
; 10 ; 12 ;
; 11 ; 1 ;
; 12 ; 1 ;
; 13 ; 0 ;
; 14 ; 0 ;
@ -859,19 +875,19 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out (Average = 6.50) ; Number of LABs (Total = 22) ;
; Number of Signals Sourced Out (Average = 6.13) ; Number of LABs (Total = 24) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 2 ;
; 1 ; 3 ;
; 2 ; 0 ;
; 3 ; 1 ;
; 4 ; 2 ;
; 3 ; 0 ;
; 4 ; 4 ;
; 5 ; 1 ;
; 6 ; 3 ;
; 7 ; 4 ;
; 8 ; 6 ;
; 9 ; 0 ;
; 10 ; 2 ;
; 9 ; 2 ;
; 10 ; 0 ;
; 11 ; 1 ;
+-------------------------------------------------+------------------------------+
@ -879,29 +895,29 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+-----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+----------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 11.05) ; Number of LABs (Total = 22) ;
; Number of Distinct Inputs (Average = 11.25) ; Number of LABs (Total = 24) ;
+----------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 1 ; 1 ;
; 2 ; 2 ;
; 3 ; 2 ;
; 4 ; 1 ;
; 5 ; 1 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 1 ;
; 8 ; 0 ;
; 9 ; 1 ;
; 10 ; 1 ;
; 11 ; 2 ;
; 12 ; 3 ;
; 9 ; 2 ;
; 10 ; 2 ;
; 11 ; 1 ;
; 12 ; 2 ;
; 13 ; 1 ;
; 14 ; 1 ;
; 15 ; 0 ;
; 14 ; 0 ;
; 15 ; 1 ;
; 16 ; 1 ;
; 17 ; 0 ;
; 18 ; 2 ;
; 19 ; 1 ;
; 20 ; 0 ;
; 17 ; 3 ;
; 18 ; 1 ;
; 19 ; 0 ;
; 20 ; 1 ;
; 21 ; 2 ;
+----------------------------------------------+------------------------------+
@ -961,18 +977,19 @@ Info (170191): Fitter placement operations beginning
Info (170137): Fitter placement was successful
Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
Info (170193): Fitter routing operations beginning
Info (170195): Router estimated average interconnect usage is 17% of the available device resources
Info (170196): Router estimated peak interconnect usage is 17% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
Info (170089): 2e+01 ns of routing delay (approximately 1.2% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report.
Info (170195): Router estimated average interconnect usage is 19% of the available device resources
Info (170196): Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
Info (11888): Total time spent on timing analysis during the Fitter is 0.13 seconds.
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info (144001): Generated suppressed messages file C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.fit.smsg
Info: Quartus II 64-Bit Fitter was successful. 0 errors, 5 warnings
Info: Peak virtual memory: 4771 megabytes
Info: Processing ended: Tue Sep 08 19:28:18 2020
Info: Elapsed time: 00:00:03
Info: Total CPU time (on all processors): 00:00:02
Info: Peak virtual memory: 4767 megabytes
Info: Processing ended: Wed Sep 16 19:34:48 2020
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:01
+----------------------------+

View File

@ -1,11 +1,11 @@
Fitter Status : Successful - Tue Sep 08 19:28:17 2020
Fitter Status : Successful - Wed Sep 16 19:34:48 2020
Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name : RAM2E
Top-level Entity Name : RAM2E
Family : MAX V
Device : 5M240ZT100C5
Timing Models : Final
Total logic elements : 184 / 240 ( 77 % )
Total logic elements : 199 / 240 ( 83 % )
Total pins : 69 / 79 ( 87 % )
Total virtual pins : 0
UFM blocks : 1 / 1 ( 100 % )

View File

@ -1,5 +1,5 @@
Flow report for RAM2E
Tue Sep 08 19:28:21 2020
Wed Sep 16 19:34:51 2020
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -40,14 +40,14 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------+
; Flow Summary ;
+---------------------------+-------------------------------------------------+
; Flow Status ; Successful - Tue Sep 08 19:28:19 2020 ;
; Flow Status ; Successful - Wed Sep 16 19:34:49 2020 ;
; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; RAM2E ;
; Top-level Entity Name ; RAM2E ;
; Family ; MAX V ;
; Device ; 5M240ZT100C5 ;
; Timing Models ; Final ;
; Total logic elements ; 184 / 240 ( 77 % ) ;
; Total logic elements ; 199 / 240 ( 83 % ) ;
; Total pins ; 69 / 79 ( 87 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
@ -59,7 +59,7 @@ applicable agreement for further details.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 09/08/2020 19:28:13 ;
; Start date & time ; 09/16/2020 19:34:45 ;
; Main task ; Compilation ;
; Revision Name ; RAM2E ;
+-------------------+---------------------+
@ -71,14 +71,12 @@ applicable agreement for further details.
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+------------------------------------+---------------------------------+---------------+-------------+------------+
; ALLOW_POWER_UP_DONT_CARE ; Off ; On ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 207120313862967.159960769334468 ; -- ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 207120313862967.160029928511600 ; -- ; -- ; -- ;
; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ;
; IP_TOOL_NAME ; ALTUFM_NONE ; -- ; -- ; -- ;
; IP_TOOL_VERSION ; 13.0 ; -- ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; MISC_FILE ; UFM.bsf ; -- ; -- ; -- ;
; MISC_FILE ; UFM_bb.v ; -- ; -- ; -- ;
; OPTIMIZE_MULTI_CORNER_TIMING ; On ; Off ; -- ; -- ;
; PARALLEL_SYNTHESIS ; Off ; On ; -- ; -- ;
; POWER_DEFAULT_INPUT_IO_TOGGLE_RATE ; 12.5 % ; 12.5% ; -- ; -- ;
@ -95,11 +93,11 @@ applicable agreement for further details.
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:01 ; 1.0 ; 4577 MB ; 00:00:01 ;
; Fitter ; 00:00:02 ; 1.0 ; 4771 MB ; 00:00:02 ;
; Assembler ; 00:00:01 ; 1.0 ; 4524 MB ; 00:00:00 ;
; TimeQuest Timing Analyzer ; 00:00:01 ; 1.0 ; 4528 MB ; 00:00:01 ;
; Total ; 00:00:05 ; -- ; -- ; 00:00:04 ;
; Analysis & Synthesis ; 00:00:00 ; 1.0 ; 4575 MB ; 00:00:01 ;
; Fitter ; 00:00:02 ; 1.0 ; 4767 MB ; 00:00:01 ;
; Assembler ; 00:00:00 ; 1.0 ; 4524 MB ; 00:00:00 ;
; TimeQuest Timing Analyzer ; 00:00:01 ; 1.0 ; 4522 MB ; 00:00:01 ;
; Total ; 00:00:03 ; -- ; -- ; 00:00:03 ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+

View File

@ -1,6 +1,6 @@
<sld_project_info>
<project>
<hash md5_digest_80b="56678bba3097e929c412"/>
<hash md5_digest_80b="652565839ecfc53317c4"/>
</project>
<file_info>
<file device="5M240ZT100C5" path="RAM2E.sof" usercode="0xFFFFFFFF"/>

View File

@ -1,5 +1,5 @@
Analysis & Synthesis report for RAM2E
Tue Sep 08 19:28:14 2020
Wed Sep 16 19:34:46 2020
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -45,12 +45,12 @@ applicable agreement for further details.
+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+-------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Tue Sep 08 19:28:14 2020 ;
; Analysis & Synthesis Status ; Successful - Wed Sep 16 19:34:45 2020 ;
; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; RAM2E ;
; Top-level Entity Name ; RAM2E ;
; Family ; MAX V ;
; Total logic elements ; 193 ;
; Total logic elements ; 208 ;
; Total pins ; 69 ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
@ -147,8 +147,8 @@ Parallel compilation was disabled, but you have multiple processors available. E
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+----------------------------------+-----------------------------------------------------+---------+
; RAM2E.v ; yes ; User Verilog HDL File ; C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v ; ;
; db/UFM.v ; yes ; Auto-Generated Megafunction ; C:/Users/Zane/Documents/GitHub/RAM2E/cpld/db/UFM.v ; ;
; RAM2E.mif ; yes ; User Memory Initialization File ; C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.mif ; ;
; UFM.v ; yes ; User Wizard-Generated File ; C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v ; ;
+----------------------------------+-----------------+----------------------------------+-----------------------------------------------------+---------+
@ -157,34 +157,34 @@ Parallel compilation was disabled, but you have multiple processors available. E
+---------------------------------------------+-------+
; Resource ; Usage ;
+---------------------------------------------+-------+
; Total logic elements ; 193 ;
; -- Combinational with no register ; 87 ;
; -- Register only ; 26 ;
; -- Combinational with a register ; 80 ;
; Total logic elements ; 208 ;
; -- Combinational with no register ; 93 ;
; -- Register only ; 34 ;
; -- Combinational with a register ; 81 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 87 ;
; -- 3 input functions ; 42 ;
; -- 2 input functions ; 34 ;
; -- 4 input functions ; 99 ;
; -- 3 input functions ; 36 ;
; -- 2 input functions ; 35 ;
; -- 1 input functions ; 3 ;
; -- 0 input functions ; 1 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 179 ;
; -- normal mode ; 194 ;
; -- arithmetic mode ; 14 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 1 ;
; -- asynchronous clear/load mode ; 0 ;
; ; ;
; Total registers ; 106 ;
; Total registers ; 115 ;
; Total logic cells in carry chains ; 15 ;
; I/O pins ; 69 ;
; UFM blocks ; 1 ;
; Maximum fan-out node ; C14M ;
; Maximum fan-out ; 106 ;
; Total fan-out ; 797 ;
; Average fan-out ; 3.03 ;
; Maximum fan-out ; 115 ;
; Total fan-out ; 854 ;
; Average fan-out ; 3.07 ;
+---------------------------------------------+-------+
@ -193,20 +193,20 @@ Parallel compilation was disabled, but you have multiple processors available. E
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+--------------+
; |RAM2E ; 193 (193) ; 106 ; 1 ; 69 ; 0 ; 87 (87) ; 26 (26) ; 80 (80) ; 15 (15) ; 0 (0) ; |RAM2E ; work ;
; |RAM2E ; 208 (208) ; 115 ; 1 ; 69 ; 0 ; 93 (93) ; 34 (34) ; 81 (81) ; 15 (15) ; 0 (0) ; |RAM2E ; work ;
; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|UFM:UFM_inst ; work ;
; |UFM_altufm_none_a7r:UFM_altufm_none_a7r_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|UFM:UFM_inst|UFM_altufm_none_a7r:UFM_altufm_none_a7r_component ; work ;
; |UFM_altufm_none_e4r:UFM_altufm_none_e4r_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|UFM:UFM_inst|UFM_altufm_none_e4r:UFM_altufm_none_e4r_component ; work ;
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary ;
+--------+--------------+---------+--------------+--------------+---------------------+----------------------------------------------------+
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ;
+--------+--------------+---------+--------------+--------------+---------------------+----------------------------------------------------+
; Altera ; ALTUFM_NONE ; 13.0 ; N/A ; N/A ; |RAM2E|UFM:UFM_inst ; C:/Users/Zane/Documents/GitHub/RAM2E/cpld/db/UFM.v ;
+--------+--------------+---------+--------------+--------------+---------------------+----------------------------------------------------+
+---------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary ;
+--------+--------------+---------+--------------+--------------+---------------------+-------------------------------------------------+
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ;
+--------+--------------+---------+--------------+--------------+---------------------+-------------------------------------------------+
; Altera ; ALTUFM_NONE ; 13.0 ; N/A ; N/A ; |RAM2E|UFM:UFM_inst ; C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v ;
+--------+--------------+---------+--------------+--------------+---------------------+-------------------------------------------------+
+------------------------------------------------------+
@ -214,12 +214,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 106 ;
; Total registers ; 115 ;
; Number of registers using Synchronous Clear ; 1 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 56 ;
; Number of registers using Clock Enable ; 64 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
@ -246,7 +246,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |RAM2E|S[3] ;
; 4:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |RAM2E|CS[2] ;
; 16:1 ; 8 bits ; 80 LEs ; 8 LEs ; 72 LEs ; Yes ; |RAM2E|RA[4]~reg0 ;
; 16:1 ; 8 bits ; 80 LEs ; 16 LEs ; 64 LEs ; Yes ; |RAM2E|RA[4]~reg0 ;
; 9:1 ; 8 bits ; 48 LEs ; 16 LEs ; 32 LEs ; Yes ; |RAM2E|RWMask[4] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
@ -268,32 +268,31 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Tue Sep 08 19:28:13 2020
Info: Processing started: Wed Sep 16 19:34:45 2020
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (12021): Found 1 design units, including 1 entities, in source file ram2e.v
Info (12023): Found entity 1: RAM2E
Warning (12136): Clear box output file C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v is not compatible with the current compile. Used regenerated output file C:/Users/Zane/Documents/GitHub/RAM2E/cpld/db/UFM.v for elaboration
Info (12021): Found 2 design units, including 2 entities, in source file db/ufm.v
Info (12023): Found entity 1: UFM_altufm_none_a7r
Info (12021): Found 2 design units, including 2 entities, in source file ufm.v
Info (12023): Found entity 1: UFM_altufm_none_e4r
Info (12023): Found entity 2: UFM
Info (12127): Elaborating entity "RAM2E" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at RAM2E.v(99): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at RAM2E.v(102): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at RAM2E.v(504): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at RAM2E.v(521): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at RAM2E.v(101): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at RAM2E.v(104): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at RAM2E.v(551): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at RAM2E.v(568): truncated value with size 32 to match size of target (3)
Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst"
Info (12128): Elaborating entity "UFM_altufm_none_a7r" for hierarchy "UFM:UFM_inst|UFM_altufm_none_a7r:UFM_altufm_none_a7r_component"
Info (21057): Implemented 263 device resources after synthesis - the final resource count might be different
Info (12128): Elaborating entity "UFM_altufm_none_e4r" for hierarchy "UFM:UFM_inst|UFM_altufm_none_e4r:UFM_altufm_none_e4r_component"
Info (21057): Implemented 278 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 22 input pins
Info (21059): Implemented 39 output pins
Info (21060): Implemented 8 bidirectional pins
Info (21061): Implemented 193 logic cells
Info (21061): Implemented 208 logic cells
Info (21070): Implemented 1 User Flash Memory blocks
Info (144001): Generated suppressed messages file C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.map.smsg
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 6 warnings
Info: Peak virtual memory: 4577 megabytes
Info: Processing ended: Tue Sep 08 19:28:14 2020
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 5 warnings
Info: Peak virtual memory: 4575 megabytes
Info: Processing ended: Wed Sep 16 19:34:46 2020
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01

View File

@ -1,3 +1,3 @@
Warning (10273): Verilog HDL warning at RAM2E.v(37): extended using "x" or "z"
Warning (10273): Verilog HDL warning at RAM2E.v(39): extended using "x" or "z"
Warning (10463): Verilog HDL Declaration warning at UFM.v(72): "program" is SystemVerilog-2005 keyword
Warning (10463): Verilog HDL Declaration warning at UFM.v(188): "program" is SystemVerilog-2005 keyword

View File

@ -1,9 +1,9 @@
Analysis & Synthesis Status : Successful - Tue Sep 08 19:28:14 2020
Analysis & Synthesis Status : Successful - Wed Sep 16 19:34:45 2020
Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name : RAM2E
Top-level Entity Name : RAM2E
Family : MAX V
Total logic elements : 193
Total logic elements : 208
Total pins : 69
Total virtual pins : 0
UFM blocks : 1 / 1 ( 100 % )

Binary file not shown.

View File

@ -1,89 +0,0 @@
PowerPlay Power Analyzer report for RAM2E
Fri May 22 18:35:29 2020
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. PowerPlay Power Analyzer Summary
3. PowerPlay Power Analyzer Settings
4. PowerPlay Power Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------------+
; PowerPlay Power Analyzer Summary ;
+---------------------------------+-------------------------------------------------+
; PowerPlay Power Analyzer Status ; Failed - Fri May 22 18:35:29 2020 ;
; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; RAM2E ;
; Top-level Entity Name ; RAM2E ;
; Family ; MAX II ;
; Device ; EPM240T100C5 ;
+---------------------------------+-------------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------+
; PowerPlay Power Analyzer Settings ;
+----------------------------------------------------------------------------+-----------------------------+---------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------------+-----------------------------+---------------+
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Default Power Input I/O Toggle Rate ; 12.5% ; 12.5% ;
; External Supply Voltage Applied to Voltage Regulator ; 3.3V ; ;
; Preset Cooling Solution ; No Heat Sink With Still Air ; ;
; Default Power Toggle Rate ; 12.5% ; 12.5% ;
; Use vectorless estimation ; On ; On ;
; Use Input Files ; Off ; Off ;
; Filter Glitches in VCD File Reader ; On ; On ;
; Power Analyzer Report Signal Activity ; Off ; Off ;
; Power Analyzer Report Power Dissipation ; Off ; Off ;
; Device Power Characteristics ; TYPICAL ; TYPICAL ;
; Automatically Compute Junction Temperature ; On ; On ;
; Specified Junction Temperature ; 25 ; 25 ;
; Ambient Temperature ; 25 ; 25 ;
; Use Custom Cooling Solution ; Off ; Off ;
; Enable HPS ; Off ; Off ;
; Processor Frequency ; 0.0 ; 0.0 ;
+----------------------------------------------------------------------------+-----------------------------+---------------+
+-----------------------------------+
; PowerPlay Power Analyzer Messages ;
+-----------------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit PowerPlay Power Analyzer
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Fri May 22 18:35:27 2020
Info: Command: quartus_pow --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E
Error (215048): PowerPlay Power Analyzer (quartus_pow) cannot be run. The required timing data is not available. Run TimeQuest Timing Analyzer (quartus_sta).
Error: Quartus II 32-bit PowerPlay Power Analyzer was unsuccessful. 1 error, 0 warnings
Error: Peak virtual memory: 267 megabytes
Error: Processing ended: Fri May 22 18:35:29 2020
Error: Elapsed time: 00:00:02
Error: Total CPU time (on all processors): 00:00:02

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@ -1,6 +0,0 @@
PowerPlay Power Analyzer Status : Failed - Fri May 22 18:35:29 2020
Quartus II 32-bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name : RAM2E
Top-level Entity Name : RAM2E
Family : MAX II
Device : EPM240T100C5

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@ -1,5 +1,5 @@
TimeQuest Timing Analyzer report for RAM2E
Tue Sep 08 19:28:21 2020
Wed Sep 16 19:34:51 2020
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@ -83,7 +83,7 @@ Parallel compilation was disabled, but you have multiple processors available. E
+-----------------+--------+--------------------------+
; SDC File Path ; Status ; Read at ;
+-----------------+--------+--------------------------+
; constraints.sdc ; OK ; Tue Sep 08 19:28:21 2020 ;
; constraints.sdc ; OK ; Wed Sep 16 19:34:51 2020 ;
+-----------------+--------+--------------------------+
@ -96,13 +96,13 @@ Parallel compilation was disabled, but you have multiple processors available. E
+------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+
+------------------------------------------------+
; Fmax Summary ;
+----------+-----------------+------------+------+
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
+----------+-----------------+------------+------+
; 38.2 MHz ; 38.2 MHz ; C14M ; ;
+----------+-----------------+------------+------+
+-------------------------------------------------+
; Fmax Summary ;
+-----------+-----------------+------------+------+
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
+-----------+-----------------+------------+------+
; 34.54 MHz ; 34.54 MHz ; C14M ; ;
+-----------+-----------------+------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
@ -111,7 +111,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+-------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+-------+--------+---------------+
; C14M ; 22.276 ; 0.000 ;
; C14M ; 22.294 ; 0.000 ;
+-------+--------+---------------+
@ -120,7 +120,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+-------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+-------+-------+---------------+
; C14M ; 3.130 ; 0.000 ;
; C14M ; 3.117 ; 0.000 ;
+-------+-------+---------------+
@ -150,106 +150,106 @@ No paths to report.
+--------+-----------+--------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------+--------------+--------------+-------------+--------------+------------+------------+
; 22.276 ; S[1] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.323 ;
; 22.276 ; S[1] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.323 ;
; 22.276 ; S[1] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.323 ;
; 22.276 ; S[1] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.323 ;
; 22.276 ; S[1] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.323 ;
; 22.276 ; S[1] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.323 ;
; 22.426 ; S[0] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.173 ;
; 22.426 ; S[0] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.173 ;
; 22.426 ; S[0] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.173 ;
; 22.460 ; S[2] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.139 ;
; 22.460 ; S[2] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.139 ;
; 22.460 ; S[2] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.139 ;
; 22.460 ; S[2] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.139 ;
; 22.460 ; S[2] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.139 ;
; 22.460 ; S[2] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.139 ;
; 22.542 ; S[3] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.057 ;
; 22.542 ; S[3] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.057 ;
; 22.542 ; S[3] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.057 ;
; 22.733 ; S[1] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.866 ;
; 22.735 ; S[1] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.864 ;
; 22.870 ; S[0] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.729 ;
; 22.870 ; S[0] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.729 ;
; 22.917 ; S[2] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.682 ;
; 22.919 ; S[2] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.680 ;
; 22.986 ; S[3] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.613 ;
; 22.986 ; S[3] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.613 ;
; 23.378 ; S[2] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.221 ;
; 23.378 ; S[2] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.221 ;
; 23.378 ; S[2] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.221 ;
; 23.395 ; S[0] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.204 ;
; 23.395 ; S[0] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.204 ;
; 23.395 ; S[0] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.204 ;
; 23.395 ; S[0] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.204 ;
; 23.395 ; S[0] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.204 ;
; 23.395 ; S[0] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.204 ;
; 23.822 ; S[2] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.777 ;
; 23.822 ; S[2] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.777 ;
; 23.852 ; S[0] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.747 ;
; 23.854 ; S[0] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.745 ;
; 23.953 ; S[3] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.646 ;
; 23.953 ; S[3] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.646 ;
; 23.953 ; S[3] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.646 ;
; 23.953 ; S[3] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.646 ;
; 23.953 ; S[3] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.646 ;
; 23.953 ; S[3] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.646 ;
; 24.064 ; S[1] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.535 ;
; 24.064 ; S[1] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.535 ;
; 24.064 ; S[1] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.535 ;
; 24.410 ; S[3] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.189 ;
; 24.412 ; S[3] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.187 ;
; 24.508 ; S[1] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.091 ;
; 24.508 ; S[1] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.091 ;
; 24.602 ; S[0] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 9.997 ;
; 24.602 ; S[0] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 9.997 ;
; 24.602 ; S[0] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 9.997 ;
; 24.718 ; S[3] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 9.881 ;
; 24.718 ; S[3] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 9.881 ;
; 24.718 ; S[3] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 9.881 ;
; 25.554 ; S[2] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 9.045 ;
; 25.554 ; S[2] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 9.045 ;
; 25.554 ; S[2] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 9.045 ;
; 26.240 ; S[1] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 8.359 ;
; 26.240 ; S[1] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 8.359 ;
; 26.240 ; S[1] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 8.359 ;
; 43.660 ; FS[11] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 25.860 ;
; 43.812 ; UFMD[13] ; RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 25.708 ;
; 43.847 ; FS[10] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 25.673 ;
; 43.869 ; FS[8] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 25.651 ;
; 43.924 ; FS[7] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 25.596 ;
; 44.239 ; UFMD[14] ; RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 25.281 ;
; 44.508 ; FS[9] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 25.012 ;
; 44.688 ; FS[12] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 24.832 ;
; 44.939 ; UFMD[13] ; RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.581 ;
; 44.939 ; UFMD[13] ; RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.581 ;
; 44.939 ; UFMD[13] ; RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.581 ;
; 44.939 ; UFMD[13] ; RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.581 ;
; 44.939 ; UFMD[13] ; RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.581 ;
; 44.939 ; UFMD[13] ; RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.581 ;
; 44.939 ; UFMD[13] ; RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.581 ;
; 45.366 ; UFMD[14] ; RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.154 ;
; 45.366 ; UFMD[14] ; RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.154 ;
; 45.366 ; UFMD[14] ; RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.154 ;
; 45.366 ; UFMD[14] ; RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.154 ;
; 45.366 ; UFMD[14] ; RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.154 ;
; 45.366 ; UFMD[14] ; RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.154 ;
; 45.366 ; UFMD[14] ; RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.154 ;
; 45.570 ; FS[6] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 23.950 ;
; 45.725 ; S[1] ; DRCLK ; C14M ; C14M ; 69.841 ; 0.000 ; 23.795 ;
; 45.909 ; S[2] ; DRCLK ; C14M ; C14M ; 69.841 ; 0.000 ; 23.611 ;
; 45.989 ; S[1] ; S[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 23.531 ;
; 45.990 ; S[1] ; S[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 23.530 ;
; 45.991 ; S[1] ; S[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 23.529 ;
; 46.221 ; FS[4] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 23.299 ;
; 46.324 ; FS[4] ; RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 23.196 ;
; 46.503 ; FS[11] ; RA[10]~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 23.017 ;
; 46.641 ; FS[4] ; DRCLK ; C14M ; C14M ; 69.841 ; 0.000 ; 22.879 ;
; 46.690 ; FS[10] ; RA[10]~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 22.830 ;
; 46.712 ; FS[8] ; RA[10]~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 22.808 ;
; 46.753 ; FS[15] ; DRCLK ; C14M ; C14M ; 69.841 ; 0.000 ; 22.767 ;
; 46.767 ; FS[7] ; RA[10]~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 22.753 ;
; 22.294 ; S[0] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.305 ;
; 22.294 ; S[0] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.305 ;
; 22.294 ; S[0] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.305 ;
; 22.294 ; S[0] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.305 ;
; 22.294 ; S[0] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.305 ;
; 22.294 ; S[0] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.305 ;
; 22.365 ; S[0] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.234 ;
; 22.365 ; S[0] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.234 ;
; 22.365 ; S[0] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.234 ;
; 22.488 ; S[2] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.111 ;
; 22.488 ; S[2] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.111 ;
; 22.488 ; S[2] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.111 ;
; 22.488 ; S[2] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.111 ;
; 22.488 ; S[2] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.111 ;
; 22.488 ; S[2] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.111 ;
; 22.559 ; S[2] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.040 ;
; 22.559 ; S[2] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.040 ;
; 22.559 ; S[2] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.040 ;
; 22.805 ; S[0] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.794 ;
; 22.807 ; S[0] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.792 ;
; 22.825 ; S[0] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.774 ;
; 22.825 ; S[0] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.774 ;
; 22.999 ; S[2] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.600 ;
; 23.001 ; S[2] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.598 ;
; 23.019 ; S[2] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.580 ;
; 23.019 ; S[2] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.580 ;
; 23.370 ; S[1] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.229 ;
; 23.370 ; S[1] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.229 ;
; 23.370 ; S[1] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.229 ;
; 23.370 ; S[1] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.229 ;
; 23.370 ; S[1] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.229 ;
; 23.370 ; S[1] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.229 ;
; 23.443 ; S[1] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.156 ;
; 23.443 ; S[1] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.156 ;
; 23.443 ; S[1] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.156 ;
; 23.881 ; S[1] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.718 ;
; 23.883 ; S[1] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.716 ;
; 23.903 ; S[1] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.696 ;
; 23.903 ; S[1] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.696 ;
; 24.036 ; S[3] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.563 ;
; 24.036 ; S[3] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.563 ;
; 24.036 ; S[3] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.563 ;
; 24.036 ; S[3] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.563 ;
; 24.036 ; S[3] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.563 ;
; 24.036 ; S[3] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.563 ;
; 24.108 ; S[3] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.491 ;
; 24.108 ; S[3] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.491 ;
; 24.108 ; S[3] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.491 ;
; 24.541 ; S[0] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.058 ;
; 24.541 ; S[0] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.058 ;
; 24.541 ; S[0] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.058 ;
; 24.547 ; S[3] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.052 ;
; 24.549 ; S[3] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.050 ;
; 24.568 ; S[3] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.031 ;
; 24.568 ; S[3] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.031 ;
; 24.735 ; S[2] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 9.864 ;
; 24.735 ; S[2] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 9.864 ;
; 24.735 ; S[2] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 9.864 ;
; 25.619 ; S[1] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 8.980 ;
; 25.619 ; S[1] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 8.980 ;
; 25.619 ; S[1] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 8.980 ;
; 26.284 ; S[3] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 8.315 ;
; 26.284 ; S[3] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 8.315 ;
; 26.284 ; S[3] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 8.315 ;
; 40.888 ; UFMD[14] ; RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 28.632 ;
; 41.955 ; UFMD[14] ; RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 27.565 ;
; 41.955 ; UFMD[14] ; RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 27.565 ;
; 41.955 ; UFMD[14] ; RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 27.565 ;
; 41.955 ; UFMD[14] ; RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 27.565 ;
; 41.955 ; UFMD[14] ; RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 27.565 ;
; 41.955 ; UFMD[14] ; RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 27.565 ;
; 41.955 ; UFMD[14] ; RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 27.565 ;
; 42.894 ; FS[15] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 26.626 ;
; 43.480 ; UFMD[13] ; RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.040 ;
; 43.730 ; S[0] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 25.790 ;
; 43.787 ; FS[14] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 25.733 ;
; 43.865 ; UFMD[9] ; RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 25.655 ;
; 44.355 ; FS[7] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 25.165 ;
; 44.387 ; FS[13] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 25.133 ;
; 44.473 ; FS[4] ; RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 25.047 ;
; 44.547 ; UFMD[13] ; RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.973 ;
; 44.547 ; UFMD[13] ; RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.973 ;
; 44.547 ; UFMD[13] ; RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.973 ;
; 44.547 ; UFMD[13] ; RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.973 ;
; 44.547 ; UFMD[13] ; RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.973 ;
; 44.547 ; UFMD[13] ; RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.973 ;
; 44.547 ; UFMD[13] ; RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.973 ;
; 44.844 ; FS[15] ; RA[10]~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 24.676 ;
; 44.932 ; UFMD[9] ; RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.588 ;
; 44.932 ; UFMD[9] ; RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.588 ;
; 44.932 ; UFMD[9] ; RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.588 ;
; 44.932 ; UFMD[9] ; RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.588 ;
; 44.932 ; UFMD[9] ; RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.588 ;
; 44.932 ; UFMD[9] ; RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.588 ;
; 44.932 ; UFMD[9] ; RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.588 ;
; 45.011 ; FS[8] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 24.509 ;
; 45.082 ; S[3] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 24.438 ;
; 45.186 ; FS[7] ; UFMReqErase ; C14M ; C14M ; 69.841 ; 0.000 ; 24.334 ;
; 45.257 ; UFMD[12] ; RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.263 ;
; 45.419 ; FS[4] ; UFMReqErase ; C14M ; C14M ; 69.841 ; 0.000 ; 24.101 ;
+--------+-----------+--------------+--------------+-------------+--------------+------------+------------+
@ -258,106 +258,106 @@ No paths to report.
+-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
; 3.130 ; UFMD[8] ; UFMD[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.169 ;
; 3.143 ; UFMD[12] ; UFMD[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.182 ;
; 3.147 ; UFMD[11] ; UFMD[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.186 ;
; 3.377 ; DRDIn ; DRDIn ; C14M ; C14M ; 0.000 ; 0.000 ; 3.416 ;
; 3.448 ; CmdTout[0] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.487 ;
; 3.565 ; CS[0] ; SetRWBankFF ; C14M ; C14M ; 0.000 ; 0.000 ; 3.604 ;
; 3.741 ; CmdTout[2] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.780 ;
; 3.751 ; UFMPrgmEN ; UFMPrgmEN ; C14M ; C14M ; 0.000 ; 0.000 ; 3.790 ;
; 3.779 ; UFMProgram ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 3.818 ;
; 3.802 ; CmdTout[1] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.841 ;
; 3.811 ; FS[0] ; FS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.850 ;
; 3.952 ; CS[1] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.991 ;
; 3.956 ; CS[1] ; SetRWBankFF ; C14M ; C14M ; 0.000 ; 0.000 ; 3.995 ;
; 3.964 ; CS[1] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.003 ;
; 4.013 ; RTPBusyReg ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 4.052 ;
; 4.201 ; UFMD[9] ; UFMD[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.240 ;
; 4.292 ; UFMD[10] ; UFMD[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.331 ;
; 4.387 ; UFMBusyReg ; UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 4.426 ;
; 4.833 ; RWMask[5] ; RWBank[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.872 ;
; 4.839 ; RWMask[6] ; RWBank[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.878 ;
; 4.904 ; RWBank[5] ; BA[1]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 4.943 ;
; 5.216 ; RWSel ; RWSel ; C14M ; C14M ; 0.000 ; 0.000 ; 5.255 ;
; 3.117 ; UFMD[8] ; UFMD[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.156 ;
; 3.158 ; UFMD[12] ; UFMD[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.197 ;
; 3.742 ; RWMask[4] ; RWBank[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.781 ;
; 3.766 ; FS[0] ; FS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.805 ;
; 3.801 ; CmdTout[2] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.840 ;
; 3.810 ; CmdTout[1] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.849 ;
; 3.814 ; UFMProgram ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 3.853 ;
; 3.854 ; CS[0] ; CS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.893 ;
; 3.856 ; CS[0] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.895 ;
; 3.863 ; CS[0] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.902 ;
; 3.971 ; RTPBusyReg ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 4.010 ;
; 4.268 ; UFMD[11] ; UFMD[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.307 ;
; 4.271 ; UFMD[10] ; UFMD[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.310 ;
; 4.398 ; RWMask[6] ; RWBank[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.437 ;
; 4.447 ; Areg[3] ; RA[3]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 4.486 ;
; 4.475 ; RWMask[3] ; RWBank[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.514 ;
; 5.029 ; CS[2] ; SetRWBankFF ; C14M ; C14M ; 0.000 ; 0.000 ; 5.068 ;
; 5.217 ; FS[5] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.256 ;
; 5.242 ; FS[15] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.281 ;
; 5.244 ; UFMEraseEN ; UFMEraseEN ; C14M ; C14M ; 0.000 ; 0.000 ; 5.283 ;
; 5.249 ; UFMErase ; UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 5.288 ;
; 5.218 ; Areg[1] ; RA[1]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 5.257 ;
; 5.228 ; Ready ; Ready ; C14M ; C14M ; 0.000 ; 0.000 ; 5.267 ;
; 5.231 ; RWMask[7] ; RWBank[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.270 ;
; 5.241 ; FS[15] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.280 ;
; 5.243 ; FS[7] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.282 ;
; 5.252 ; FS[8] ; FS[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.291 ;
; 5.267 ; FS[10] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.306 ;
; 5.270 ; FS[9] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.309 ;
; 5.308 ; CmdTout[0] ; CmdTout[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.347 ;
; 5.319 ; CmdTout[0] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.358 ;
; 5.419 ; RWMask[0] ; RWBank[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.458 ;
; 5.432 ; RWMask[4] ; RWBank[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.471 ;
; 5.434 ; RWMask[1] ; RWBank[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.473 ;
; 5.442 ; FS[11] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.481 ;
; 5.268 ; DRDIn ; DRDIn ; C14M ; C14M ; 0.000 ; 0.000 ; 5.307 ;
; 5.280 ; FS[10] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.319 ;
; 5.283 ; FS[9] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.322 ;
; 5.305 ; CmdTout[1] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.344 ;
; 5.315 ; UFMInitDone ; UFMInitDone ; C14M ; C14M ; 0.000 ; 0.000 ; 5.354 ;
; 5.317 ; CS[1] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.356 ;
; 5.317 ; UFMEraseEN ; UFMEraseEN ; C14M ; C14M ; 0.000 ; 0.000 ; 5.356 ;
; 5.326 ; CS[1] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.365 ;
; 5.328 ; UFMPrgmEN ; UFMPrgmEN ; C14M ; C14M ; 0.000 ; 0.000 ; 5.367 ;
; 5.397 ; UFMD[11] ; RWMask[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.436 ;
; 5.419 ; Areg[2] ; RA[2]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 5.458 ;
; 5.429 ; UFMErase ; UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 5.468 ;
; 5.429 ; RWMask[5] ; RWBank[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.468 ;
; 5.430 ; Areg[7] ; RA[7]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 5.469 ;
; 5.433 ; Areg[0] ; RA[0]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 5.472 ;
; 5.442 ; DRCLKPulse ; DRCLK ; C14M ; C14M ; 0.000 ; 0.000 ; 5.481 ;
; 5.452 ; FS[13] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.491 ;
; 5.453 ; FS[14] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.492 ;
; 5.452 ; FS[14] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.491 ;
; 5.456 ; S[3] ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.495 ;
; 5.465 ; RWSel ; RWSel ; C14M ; C14M ; 0.000 ; 0.000 ; 5.504 ;
; 5.466 ; FS[12] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.505 ;
; 5.473 ; FS[3] ; FS[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.512 ;
; 5.480 ; CmdTout[1] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.519 ;
; 5.485 ; FS[6] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.524 ;
; 5.490 ; UFMInitDone ; UFMInitDone ; C14M ; C14M ; 0.000 ; 0.000 ; 5.529 ;
; 5.483 ; FS[6] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.522 ;
; 5.490 ; FS[2] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.529 ;
; 5.514 ; FS[1] ; FS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.553 ;
; 5.616 ; CS[2] ; SetRWBankFF ; C14M ; C14M ; 0.000 ; 0.000 ; 5.655 ;
; 5.626 ; CS[0] ; CS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.665 ;
; 5.628 ; CS[0] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.667 ;
; 5.632 ; CS[0] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.671 ;
; 5.727 ; UFMReqErase ; UFMReqErase ; C14M ; C14M ; 0.000 ; 0.000 ; 5.766 ;
; 5.850 ; CS[2] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.889 ;
; 5.505 ; CmdTout[0] ; CmdTout[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.544 ;
; 5.507 ; FS[1] ; FS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.546 ;
; 5.507 ; CmdTout[0] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.546 ;
; 5.509 ; CS[2] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.548 ;
; 5.510 ; CmdTout[0] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.549 ;
; 5.676 ; UFMReqErase ; UFMReqErase ; C14M ; C14M ; 0.000 ; 0.000 ; 5.715 ;
; 5.815 ; UFMPrgmEN ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 5.854 ;
; 5.952 ; FS[5] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.991 ;
; 5.962 ; UFMInitDone ; UFMReqErase ; C14M ; C14M ; 0.000 ; 0.000 ; 6.001 ;
; 5.987 ; FS[8] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.026 ;
; 6.002 ; FS[10] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.041 ;
; 6.005 ; FS[9] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.044 ;
; 6.015 ; FS[10] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.054 ;
; 6.018 ; FS[9] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.057 ;
; 6.095 ; S[2] ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.134 ;
; 6.096 ; FS[5] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.135 ;
; 6.131 ; FS[8] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.170 ;
; 6.146 ; FS[10] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.185 ;
; 6.149 ; FS[9] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.188 ;
; 6.159 ; FS[10] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.198 ;
; 6.162 ; FS[9] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.201 ;
; 6.242 ; RWMask[2] ; RWBank[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.281 ;
; 6.275 ; FS[8] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.314 ;
; 6.287 ; FS[7] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.326 ;
; 6.293 ; FS[9] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.332 ;
; 6.278 ; RWMask[1] ; RWBank[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.317 ;
; 6.286 ; Areg[5] ; RA[5]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 6.325 ;
; 6.292 ; Areg[6] ; RA[6]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 6.331 ;
; 6.306 ; FS[9] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.345 ;
; 6.396 ; UFMReqErase ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 6.435 ;
; 6.416 ; RWSel ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.455 ;
; 6.419 ; FS[8] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.458 ;
; 6.444 ; FS[11] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.483 ;
; 6.429 ; RWSel ; CmdTout[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.468 ;
; 6.433 ; RWSel ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.472 ;
; 6.444 ; FS[4] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.483 ;
; 6.454 ; FS[13] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.493 ;
; 6.455 ; FS[14] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.494 ;
; 6.463 ; RWBank[7] ; RA[8]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 6.502 ;
; 6.466 ; FS[4] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.505 ;
; 6.454 ; FS[14] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.493 ;
; 6.475 ; FS[3] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.514 ;
; 6.487 ; FS[6] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.526 ;
; 6.489 ; RWBank[0] ; RA[8]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 6.528 ;
; 6.516 ; FS[1] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.555 ;
; 6.521 ; S[0] ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.560 ;
; 6.529 ; RWMask[7] ; RWBank[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.568 ;
; 6.564 ; RWBank[1] ; RA[9]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 6.603 ;
; 6.566 ; RWMask[2] ; RWBank[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.605 ;
; 6.578 ; S[2] ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.617 ;
; 6.583 ; S[3] ; S[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.622 ;
; 6.484 ; S[2] ; S[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.523 ;
; 6.485 ; FS[6] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.524 ;
; 6.493 ; CS[1] ; SetRWBankFF ; C14M ; C14M ; 0.000 ; 0.000 ; 6.532 ;
; 6.509 ; FS[1] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.548 ;
; 6.515 ; FS[11] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.554 ;
; 6.538 ; S[1] ; S[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.577 ;
; 6.595 ; S[2] ; BA[0]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 6.634 ;
; 6.598 ; FS[13] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.637 ;
; 6.619 ; FS[3] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.658 ;
; 6.623 ; UFMD[9] ; UFMD[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.662 ;
; 6.658 ; CS[0] ; SetRWBankFF ; C14M ; C14M ; 0.000 ; 0.000 ; 6.697 ;
; 6.682 ; Areg[4] ; RA[4]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 6.721 ;
; 6.692 ; UFMD[13] ; RWMask[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.731 ;
; 6.708 ; UFMD[12] ; RWMask[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.747 ;
; 6.720 ; RWMask[0] ; RWBank[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.759 ;
; 6.759 ; RWBank[7] ; RA[8]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 6.798 ;
; 6.763 ; FS[3] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.802 ;
; 6.782 ; FS[10] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.821 ;
; 6.782 ; FS[10] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.821 ;
; 6.782 ; FS[10] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.821 ;
; 6.880 ; SetRWBankFF ; RWBank[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.919 ;
; 6.886 ; SetRWBankFF ; RWBank[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.925 ;
; 6.907 ; FS[3] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.946 ;
; 6.929 ; FS[9] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.968 ;
; 6.929 ; FS[9] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.968 ;
; 6.929 ; FS[9] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.968 ;
; 7.023 ; FS[12] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 7.062 ;
; 7.023 ; FS[12] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 7.062 ;
; 7.023 ; FS[12] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 7.062 ;
; 7.047 ; FS[2] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 7.086 ;
; 7.047 ; FS[2] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 7.086 ;
; 7.047 ; FS[2] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 7.086 ;
; 7.047 ; FS[2] ; FS[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 7.086 ;
; 7.047 ; FS[2] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 7.086 ;
; 7.055 ; FS[8] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 7.094 ;
; 7.055 ; FS[8] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 7.094 ;
; 6.791 ; FS[0] ; Ready ; C14M ; C14M ; 0.000 ; 0.000 ; 6.830 ;
; 6.795 ; FS[10] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.834 ;
; 6.795 ; FS[10] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.834 ;
; 6.795 ; FS[10] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.834 ;
+-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
@ -368,6 +368,14 @@ No paths to report.
+--------+--------------+----------------+------------------+-------+------------+--------------+
; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; ARCLK ;
; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; ARShift ;
; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; Areg[0] ;
; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; Areg[1] ;
; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; Areg[2] ;
; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; Areg[3] ;
; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; Areg[4] ;
; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; Areg[5] ;
; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; Areg[6] ;
; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; Areg[7] ;
; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; BA[0]~reg0 ;
; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; BA[1]~reg0 ;
; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; CKE~reg0 ;
@ -377,6 +385,7 @@ No paths to report.
; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; CmdTout[0] ;
; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; CmdTout[1] ;
; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; CmdTout[2] ;
; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; DOEEN ;
; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; DQMH~reg0 ;
; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; DQML~reg0 ;
; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; DRCLK ;
@ -457,15 +466,6 @@ No paths to report.
; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; UFMErase ;
; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; UFMEraseEN ;
; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; UFMInitDone ;
; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; UFMPrgmEN ;
; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; UFMProgram ;
; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; UFMReqErase ;
; 34.581 ; 34.920 ; 0.339 ; Low Pulse Width ; C14M ; Fall ; Vout[0]~reg0 ;
; 34.581 ; 34.920 ; 0.339 ; Low Pulse Width ; C14M ; Fall ; Vout[1]~reg0 ;
; 34.581 ; 34.920 ; 0.339 ; Low Pulse Width ; C14M ; Fall ; Vout[2]~reg0 ;
; 34.581 ; 34.920 ; 0.339 ; Low Pulse Width ; C14M ; Fall ; Vout[3]~reg0 ;
; 34.581 ; 34.920 ; 0.339 ; Low Pulse Width ; C14M ; Fall ; Vout[4]~reg0 ;
; 34.581 ; 34.920 ; 0.339 ; Low Pulse Width ; C14M ; Fall ; Vout[5]~reg0 ;
+--------+--------------+----------------+------------------+-------+------------+--------------+
@ -474,37 +474,38 @@ No paths to report.
+-----------+------------+--------+--------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+--------+--------+------------+-----------------+
; Ain[*] ; C14M ; 6.638 ; 6.638 ; Rise ; C14M ;
; Ain[0] ; C14M ; 6.238 ; 6.238 ; Rise ; C14M ;
; Ain[1] ; C14M ; 6.346 ; 6.346 ; Rise ; C14M ;
; Ain[2] ; C14M ; 6.638 ; 6.638 ; Rise ; C14M ;
; Ain[3] ; C14M ; 5.468 ; 5.468 ; Rise ; C14M ;
; Ain[4] ; C14M ; 5.467 ; 5.467 ; Rise ; C14M ;
; Ain[5] ; C14M ; 5.452 ; 5.452 ; Rise ; C14M ;
; Ain[6] ; C14M ; 5.335 ; 5.335 ; Rise ; C14M ;
; Ain[7] ; C14M ; 6.291 ; 6.291 ; Rise ; C14M ;
; Din[*] ; C14M ; 27.902 ; 27.902 ; Rise ; C14M ;
; Din[0] ; C14M ; 21.596 ; 21.596 ; Rise ; C14M ;
; Din[1] ; C14M ; 23.617 ; 23.617 ; Rise ; C14M ;
; Din[2] ; C14M ; 22.540 ; 22.540 ; Rise ; C14M ;
; Din[3] ; C14M ; 20.056 ; 20.056 ; Rise ; C14M ;
; Din[4] ; C14M ; 23.422 ; 23.422 ; Rise ; C14M ;
; Din[5] ; C14M ; 27.902 ; 27.902 ; Rise ; C14M ;
; Din[6] ; C14M ; 20.352 ; 20.352 ; Rise ; C14M ;
; Din[7] ; C14M ; 26.876 ; 26.876 ; Rise ; C14M ;
; PHI1 ; C14M ; 17.415 ; 17.415 ; Rise ; C14M ;
; nC07X ; C14M ; 13.673 ; 13.673 ; Rise ; C14M ;
; nWE ; C14M ; 16.647 ; 16.647 ; Rise ; C14M ;
; nWE80 ; C14M ; 13.238 ; 13.238 ; Rise ; C14M ;
; RD[*] ; C14M ; 8.566 ; 8.566 ; Fall ; C14M ;
; RD[0] ; C14M ; 6.580 ; 6.580 ; Fall ; C14M ;
; RD[1] ; C14M ; 5.064 ; 5.064 ; Fall ; C14M ;
; RD[2] ; C14M ; 8.566 ; 8.566 ; Fall ; C14M ;
; RD[3] ; C14M ; 5.071 ; 5.071 ; Fall ; C14M ;
; RD[4] ; C14M ; 5.077 ; 5.077 ; Fall ; C14M ;
; RD[5] ; C14M ; 6.634 ; 6.634 ; Fall ; C14M ;
; RD[6] ; C14M ; 7.173 ; 7.173 ; Fall ; C14M ;
; RD[7] ; C14M ; 5.048 ; 5.048 ; Fall ; C14M ;
; Ain[*] ; C14M ; 7.377 ; 7.377 ; Rise ; C14M ;
; Ain[0] ; C14M ; 6.262 ; 6.262 ; Rise ; C14M ;
; Ain[1] ; C14M ; 6.408 ; 6.408 ; Rise ; C14M ;
; Ain[2] ; C14M ; 7.028 ; 7.028 ; Rise ; C14M ;
; Ain[3] ; C14M ; 7.145 ; 7.145 ; Rise ; C14M ;
; Ain[4] ; C14M ; 6.972 ; 6.972 ; Rise ; C14M ;
; Ain[5] ; C14M ; 5.239 ; 5.239 ; Rise ; C14M ;
; Ain[6] ; C14M ; 7.377 ; 7.377 ; Rise ; C14M ;
; Ain[7] ; C14M ; 6.200 ; 6.200 ; Rise ; C14M ;
; Din[*] ; C14M ; 28.839 ; 28.839 ; Rise ; C14M ;
; Din[0] ; C14M ; 28.839 ; 28.839 ; Rise ; C14M ;
; Din[1] ; C14M ; 19.557 ; 19.557 ; Rise ; C14M ;
; Din[2] ; C14M ; 26.970 ; 26.970 ; Rise ; C14M ;
; Din[3] ; C14M ; 24.844 ; 24.844 ; Rise ; C14M ;
; Din[4] ; C14M ; 21.873 ; 21.873 ; Rise ; C14M ;
; Din[5] ; C14M ; 21.507 ; 21.507 ; Rise ; C14M ;
; Din[6] ; C14M ; 24.111 ; 24.111 ; Rise ; C14M ;
; Din[7] ; C14M ; 27.444 ; 27.444 ; Rise ; C14M ;
; PHI1 ; C14M ; 19.269 ; 19.269 ; Rise ; C14M ;
; nC07X ; C14M ; 8.188 ; 8.188 ; Rise ; C14M ;
; nEN80 ; C14M ; 10.690 ; 10.690 ; Rise ; C14M ;
; nWE ; C14M ; 11.021 ; 11.021 ; Rise ; C14M ;
; nWE80 ; C14M ; 7.374 ; 7.374 ; Rise ; C14M ;
; RD[*] ; C14M ; 8.565 ; 8.565 ; Fall ; C14M ;
; RD[0] ; C14M ; 6.593 ; 6.593 ; Fall ; C14M ;
; RD[1] ; C14M ; 7.115 ; 7.115 ; Fall ; C14M ;
; RD[2] ; C14M ; 8.565 ; 8.565 ; Fall ; C14M ;
; RD[3] ; C14M ; 6.929 ; 6.929 ; Fall ; C14M ;
; RD[4] ; C14M ; 5.109 ; 5.109 ; Fall ; C14M ;
; RD[5] ; C14M ; 7.262 ; 7.262 ; Fall ; C14M ;
; RD[6] ; C14M ; 6.928 ; 6.928 ; Fall ; C14M ;
; RD[7] ; C14M ; 7.016 ; 7.016 ; Fall ; C14M ;
+-----------+------------+--------+--------+------------+-----------------+
@ -513,37 +514,38 @@ No paths to report.
+-----------+------------+---------+---------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+---------+---------+------------+-----------------+
; Ain[*] ; C14M ; -4.975 ; -4.975 ; Rise ; C14M ;
; Ain[0] ; C14M ; -5.878 ; -5.878 ; Rise ; C14M ;
; Ain[1] ; C14M ; -5.986 ; -5.986 ; Rise ; C14M ;
; Ain[2] ; C14M ; -6.278 ; -6.278 ; Rise ; C14M ;
; Ain[3] ; C14M ; -5.108 ; -5.108 ; Rise ; C14M ;
; Ain[4] ; C14M ; -5.107 ; -5.107 ; Rise ; C14M ;
; Ain[5] ; C14M ; -5.092 ; -5.092 ; Rise ; C14M ;
; Ain[6] ; C14M ; -4.975 ; -4.975 ; Rise ; C14M ;
; Ain[7] ; C14M ; -5.931 ; -5.931 ; Rise ; C14M ;
; Din[*] ; C14M ; -4.891 ; -4.891 ; Rise ; C14M ;
; Din[0] ; C14M ; -4.891 ; -4.891 ; Rise ; C14M ;
; Din[1] ; C14M ; -6.727 ; -6.727 ; Rise ; C14M ;
; Din[2] ; C14M ; -5.052 ; -5.052 ; Rise ; C14M ;
; Din[3] ; C14M ; -5.127 ; -5.127 ; Rise ; C14M ;
; Din[4] ; C14M ; -6.998 ; -6.998 ; Rise ; C14M ;
; Din[5] ; C14M ; -5.193 ; -5.193 ; Rise ; C14M ;
; Din[6] ; C14M ; -4.925 ; -4.925 ; Rise ; C14M ;
; Din[7] ; C14M ; -6.270 ; -6.270 ; Rise ; C14M ;
; PHI1 ; C14M ; -4.606 ; -4.606 ; Rise ; C14M ;
; nC07X ; C14M ; -13.313 ; -13.313 ; Rise ; C14M ;
; nWE ; C14M ; -16.287 ; -16.287 ; Rise ; C14M ;
; nWE80 ; C14M ; -12.878 ; -12.878 ; Rise ; C14M ;
; RD[*] ; C14M ; -4.678 ; -4.678 ; Fall ; C14M ;
; RD[0] ; C14M ; -6.219 ; -6.219 ; Fall ; C14M ;
; RD[1] ; C14M ; -4.695 ; -4.695 ; Fall ; C14M ;
; RD[2] ; C14M ; -6.152 ; -6.152 ; Fall ; C14M ;
; RD[3] ; C14M ; -4.686 ; -4.686 ; Fall ; C14M ;
; RD[4] ; C14M ; -4.714 ; -4.714 ; Fall ; C14M ;
; RD[5] ; C14M ; -4.770 ; -4.770 ; Fall ; C14M ;
; RD[6] ; C14M ; -6.781 ; -6.781 ; Fall ; C14M ;
; RD[7] ; C14M ; -4.678 ; -4.678 ; Fall ; C14M ;
; Ain[*] ; C14M ; -4.775 ; -4.775 ; Rise ; C14M ;
; Ain[0] ; C14M ; -5.895 ; -5.895 ; Rise ; C14M ;
; Ain[1] ; C14M ; -6.047 ; -6.047 ; Rise ; C14M ;
; Ain[2] ; C14M ; -4.801 ; -4.801 ; Rise ; C14M ;
; Ain[3] ; C14M ; -6.614 ; -6.614 ; Rise ; C14M ;
; Ain[4] ; C14M ; -6.610 ; -6.610 ; Rise ; C14M ;
; Ain[5] ; C14M ; -4.777 ; -4.777 ; Rise ; C14M ;
; Ain[6] ; C14M ; -4.775 ; -4.775 ; Rise ; C14M ;
; Ain[7] ; C14M ; -5.839 ; -5.839 ; Rise ; C14M ;
; Din[*] ; C14M ; -3.466 ; -3.466 ; Rise ; C14M ;
; Din[0] ; C14M ; -4.971 ; -4.971 ; Rise ; C14M ;
; Din[1] ; C14M ; -5.127 ; -5.127 ; Rise ; C14M ;
; Din[2] ; C14M ; -3.470 ; -3.470 ; Rise ; C14M ;
; Din[3] ; C14M ; -3.466 ; -3.466 ; Rise ; C14M ;
; Din[4] ; C14M ; -5.273 ; -5.273 ; Rise ; C14M ;
; Din[5] ; C14M ; -7.331 ; -7.331 ; Rise ; C14M ;
; Din[6] ; C14M ; -5.028 ; -5.028 ; Rise ; C14M ;
; Din[7] ; C14M ; -5.011 ; -5.011 ; Rise ; C14M ;
; PHI1 ; C14M ; -4.691 ; -4.691 ; Rise ; C14M ;
; nC07X ; C14M ; -7.828 ; -7.828 ; Rise ; C14M ;
; nEN80 ; C14M ; -7.050 ; -7.050 ; Rise ; C14M ;
; nWE ; C14M ; -10.661 ; -10.661 ; Rise ; C14M ;
; nWE80 ; C14M ; -7.014 ; -7.014 ; Rise ; C14M ;
; RD[*] ; C14M ; -4.677 ; -4.677 ; Fall ; C14M ;
; RD[0] ; C14M ; -6.232 ; -6.232 ; Fall ; C14M ;
; RD[1] ; C14M ; -4.677 ; -4.677 ; Fall ; C14M ;
; RD[2] ; C14M ; -6.203 ; -6.203 ; Fall ; C14M ;
; RD[3] ; C14M ; -4.885 ; -4.885 ; Fall ; C14M ;
; RD[4] ; C14M ; -4.749 ; -4.749 ; Fall ; C14M ;
; RD[5] ; C14M ; -6.858 ; -6.858 ; Fall ; C14M ;
; RD[6] ; C14M ; -4.728 ; -4.728 ; Fall ; C14M ;
; RD[7] ; C14M ; -6.238 ; -6.238 ; Fall ; C14M ;
+-----------+------------+---------+---------+------------+-----------------+
@ -552,47 +554,48 @@ No paths to report.
+-----------+------------+--------+--------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+--------+--------+------------+-----------------+
; BA[*] ; C14M ; 19.354 ; 19.354 ; Rise ; C14M ;
; BA[*] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ;
; BA[0] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ;
; BA[1] ; C14M ; 19.354 ; 19.354 ; Rise ; C14M ;
; BA[1] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ;
; CKE ; C14M ; 17.378 ; 17.378 ; Rise ; C14M ;
; DQMH ; C14M ; 20.741 ; 20.741 ; Rise ; C14M ;
; DQML ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ;
; RA[*] ; C14M ; 17.399 ; 17.399 ; Rise ; C14M ;
; RA[0] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ;
; RA[1] ; C14M ; 17.378 ; 17.378 ; Rise ; C14M ;
; RA[2] ; C14M ; 17.332 ; 17.332 ; Rise ; C14M ;
; DQMH ; C14M ; 20.694 ; 20.694 ; Rise ; C14M ;
; DQML ; C14M ; 17.368 ; 17.368 ; Rise ; C14M ;
; RA[*] ; C14M ; 19.354 ; 19.354 ; Rise ; C14M ;
; RA[0] ; C14M ; 17.421 ; 17.421 ; Rise ; C14M ;
; RA[1] ; C14M ; 19.354 ; 19.354 ; Rise ; C14M ;
; RA[2] ; C14M ; 17.350 ; 17.350 ; Rise ; C14M ;
; RA[3] ; C14M ; 17.368 ; 17.368 ; Rise ; C14M ;
; RA[4] ; C14M ; 17.368 ; 17.368 ; Rise ; C14M ;
; RA[5] ; C14M ; 17.392 ; 17.392 ; Rise ; C14M ;
; RA[4] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ;
; RA[5] ; C14M ; 17.375 ; 17.375 ; Rise ; C14M ;
; RA[6] ; C14M ; 17.378 ; 17.378 ; Rise ; C14M ;
; RA[7] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ;
; RA[8] ; C14M ; 17.376 ; 17.376 ; Rise ; C14M ;
; RA[9] ; C14M ; 17.399 ; 17.399 ; Rise ; C14M ;
; RA[9] ; C14M ; 17.382 ; 17.382 ; Rise ; C14M ;
; RA[10] ; C14M ; 17.376 ; 17.376 ; Rise ; C14M ;
; RA[11] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ;
; nCAS ; C14M ; 19.354 ; 19.354 ; Rise ; C14M ;
; nCS ; C14M ; 17.378 ; 17.378 ; Rise ; C14M ;
; nDOE ; C14M ; 23.226 ; 23.226 ; Rise ; C14M ;
; nRAS ; C14M ; 17.378 ; 17.378 ; Rise ; C14M ;
; nRWE ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ;
; Dout[*] ; C14M ; 10.924 ; 10.924 ; Fall ; C14M ;
; Dout[0] ; C14M ; 8.945 ; 8.945 ; Fall ; C14M ;
; Dout[1] ; C14M ; 8.977 ; 8.977 ; Fall ; C14M ;
; Dout[2] ; C14M ; 10.917 ; 10.917 ; Fall ; C14M ;
; Dout[3] ; C14M ; 8.971 ; 8.971 ; Fall ; C14M ;
; Dout[4] ; C14M ; 10.924 ; 10.924 ; Fall ; C14M ;
; Dout[5] ; C14M ; 8.941 ; 8.941 ; Fall ; C14M ;
; Dout[6] ; C14M ; 8.946 ; 8.946 ; Fall ; C14M ;
; Dout[7] ; C14M ; 8.941 ; 8.941 ; Fall ; C14M ;
; Vout[*] ; C14M ; 8.950 ; 8.950 ; Fall ; C14M ;
; Vout[0] ; C14M ; 8.950 ; 8.950 ; Fall ; C14M ;
; Vout[1] ; C14M ; 8.941 ; 8.941 ; Fall ; C14M ;
; Vout[2] ; C14M ; 8.946 ; 8.946 ; Fall ; C14M ;
; Vout[3] ; C14M ; 8.946 ; 8.946 ; Fall ; C14M ;
; Vout[4] ; C14M ; 8.941 ; 8.941 ; Fall ; C14M ;
; Vout[5] ; C14M ; 8.947 ; 8.947 ; Fall ; C14M ;
; Vout[6] ; C14M ; 8.941 ; 8.941 ; Fall ; C14M ;
; Vout[7] ; C14M ; 8.941 ; 8.941 ; Fall ; C14M ;
; Dout[*] ; C14M ; 19.315 ; 19.315 ; Fall ; C14M ;
; Dout[0] ; C14M ; 17.336 ; 17.336 ; Fall ; C14M ;
; Dout[1] ; C14M ; 17.368 ; 17.368 ; Fall ; C14M ;
; Dout[2] ; C14M ; 19.308 ; 19.308 ; Fall ; C14M ;
; Dout[3] ; C14M ; 17.362 ; 17.362 ; Fall ; C14M ;
; Dout[4] ; C14M ; 19.315 ; 19.315 ; Fall ; C14M ;
; Dout[5] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ;
; Dout[6] ; C14M ; 17.337 ; 17.337 ; Fall ; C14M ;
; Dout[7] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ;
; Vout[*] ; C14M ; 17.350 ; 17.350 ; Fall ; C14M ;
; Vout[0] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ;
; Vout[1] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ;
; Vout[2] ; C14M ; 17.337 ; 17.337 ; Fall ; C14M ;
; Vout[3] ; C14M ; 17.337 ; 17.337 ; Fall ; C14M ;
; Vout[4] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ;
; Vout[5] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ;
; Vout[6] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ;
; Vout[7] ; C14M ; 17.350 ; 17.350 ; Fall ; C14M ;
+-----------+------------+--------+--------+------------+-----------------+
@ -603,45 +606,46 @@ No paths to report.
+-----------+------------+--------+--------+------------+-----------------+
; BA[*] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ;
; BA[0] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ;
; BA[1] ; C14M ; 19.354 ; 19.354 ; Rise ; C14M ;
; BA[1] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ;
; CKE ; C14M ; 17.378 ; 17.378 ; Rise ; C14M ;
; DQMH ; C14M ; 20.741 ; 20.741 ; Rise ; C14M ;
; DQML ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ;
; RA[*] ; C14M ; 17.332 ; 17.332 ; Rise ; C14M ;
; RA[0] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ;
; RA[1] ; C14M ; 17.378 ; 17.378 ; Rise ; C14M ;
; RA[2] ; C14M ; 17.332 ; 17.332 ; Rise ; C14M ;
; DQMH ; C14M ; 20.694 ; 20.694 ; Rise ; C14M ;
; DQML ; C14M ; 17.368 ; 17.368 ; Rise ; C14M ;
; RA[*] ; C14M ; 17.350 ; 17.350 ; Rise ; C14M ;
; RA[0] ; C14M ; 17.421 ; 17.421 ; Rise ; C14M ;
; RA[1] ; C14M ; 19.354 ; 19.354 ; Rise ; C14M ;
; RA[2] ; C14M ; 17.350 ; 17.350 ; Rise ; C14M ;
; RA[3] ; C14M ; 17.368 ; 17.368 ; Rise ; C14M ;
; RA[4] ; C14M ; 17.368 ; 17.368 ; Rise ; C14M ;
; RA[5] ; C14M ; 17.392 ; 17.392 ; Rise ; C14M ;
; RA[4] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ;
; RA[5] ; C14M ; 17.375 ; 17.375 ; Rise ; C14M ;
; RA[6] ; C14M ; 17.378 ; 17.378 ; Rise ; C14M ;
; RA[7] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ;
; RA[8] ; C14M ; 17.376 ; 17.376 ; Rise ; C14M ;
; RA[9] ; C14M ; 17.399 ; 17.399 ; Rise ; C14M ;
; RA[9] ; C14M ; 17.382 ; 17.382 ; Rise ; C14M ;
; RA[10] ; C14M ; 17.376 ; 17.376 ; Rise ; C14M ;
; RA[11] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ;
; nCAS ; C14M ; 19.354 ; 19.354 ; Rise ; C14M ;
; nCS ; C14M ; 17.378 ; 17.378 ; Rise ; C14M ;
; nDOE ; C14M ; 23.226 ; 23.226 ; Rise ; C14M ;
; nRAS ; C14M ; 17.378 ; 17.378 ; Rise ; C14M ;
; nRWE ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ;
; Dout[*] ; C14M ; 8.941 ; 8.941 ; Fall ; C14M ;
; Dout[0] ; C14M ; 8.945 ; 8.945 ; Fall ; C14M ;
; Dout[1] ; C14M ; 8.977 ; 8.977 ; Fall ; C14M ;
; Dout[2] ; C14M ; 10.917 ; 10.917 ; Fall ; C14M ;
; Dout[3] ; C14M ; 8.971 ; 8.971 ; Fall ; C14M ;
; Dout[4] ; C14M ; 10.924 ; 10.924 ; Fall ; C14M ;
; Dout[5] ; C14M ; 8.941 ; 8.941 ; Fall ; C14M ;
; Dout[6] ; C14M ; 8.946 ; 8.946 ; Fall ; C14M ;
; Dout[7] ; C14M ; 8.941 ; 8.941 ; Fall ; C14M ;
; Vout[*] ; C14M ; 8.941 ; 8.941 ; Fall ; C14M ;
; Vout[0] ; C14M ; 8.950 ; 8.950 ; Fall ; C14M ;
; Vout[1] ; C14M ; 8.941 ; 8.941 ; Fall ; C14M ;
; Vout[2] ; C14M ; 8.946 ; 8.946 ; Fall ; C14M ;
; Vout[3] ; C14M ; 8.946 ; 8.946 ; Fall ; C14M ;
; Vout[4] ; C14M ; 8.941 ; 8.941 ; Fall ; C14M ;
; Vout[5] ; C14M ; 8.947 ; 8.947 ; Fall ; C14M ;
; Vout[6] ; C14M ; 8.941 ; 8.941 ; Fall ; C14M ;
; Vout[7] ; C14M ; 8.941 ; 8.941 ; Fall ; C14M ;
; Dout[*] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ;
; Dout[0] ; C14M ; 17.336 ; 17.336 ; Fall ; C14M ;
; Dout[1] ; C14M ; 17.368 ; 17.368 ; Fall ; C14M ;
; Dout[2] ; C14M ; 19.308 ; 19.308 ; Fall ; C14M ;
; Dout[3] ; C14M ; 17.362 ; 17.362 ; Fall ; C14M ;
; Dout[4] ; C14M ; 19.315 ; 19.315 ; Fall ; C14M ;
; Dout[5] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ;
; Dout[6] ; C14M ; 17.337 ; 17.337 ; Fall ; C14M ;
; Dout[7] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ;
; Vout[*] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ;
; Vout[0] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ;
; Vout[1] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ;
; Vout[2] ; C14M ; 17.337 ; 17.337 ; Fall ; C14M ;
; Vout[3] ; C14M ; 17.337 ; 17.337 ; Fall ; C14M ;
; Vout[4] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ;
; Vout[5] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ;
; Vout[6] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ;
; Vout[7] ; C14M ; 17.350 ; 17.350 ; Fall ; C14M ;
+-----------+------------+--------+--------+------------+-----------------+
@ -650,33 +654,33 @@ No paths to report.
+------------+-------------+--------+----+----+--------+
; Input Port ; Output Port ; RR ; RF ; FR ; FF ;
+------------+-------------+--------+----+----+--------+
; Din[0] ; RD[0] ; 17.981 ; ; ; 17.981 ;
; Din[1] ; RD[1] ; 17.927 ; ; ; 17.927 ;
; Din[2] ; RD[2] ; 20.142 ; ; ; 20.142 ;
; Din[3] ; RD[3] ; 17.941 ; ; ; 17.941 ;
; Din[4] ; RD[4] ; 19.866 ; ; ; 19.866 ;
; Din[5] ; RD[5] ; 19.798 ; ; ; 19.798 ;
; Din[6] ; RD[6] ; 18.337 ; ; ; 18.337 ;
; Din[7] ; RD[7] ; 17.921 ; ; ; 17.921 ;
; PHI1 ; nVOE ; 14.089 ; ; ; 14.089 ;
; nEN80 ; RD[0] ; 20.841 ; ; ; 20.841 ;
; nEN80 ; RD[1] ; 22.027 ; ; ; 22.027 ;
; nEN80 ; RD[2] ; 20.841 ; ; ; 20.841 ;
; nEN80 ; RD[3] ; 22.027 ; ; ; 22.027 ;
; nEN80 ; RD[4] ; 22.027 ; ; ; 22.027 ;
; nEN80 ; RD[5] ; 20.841 ; ; ; 20.841 ;
; nEN80 ; RD[6] ; 20.841 ; ; ; 20.841 ;
; nEN80 ; RD[7] ; 20.841 ; ; ; 20.841 ;
; nEN80 ; nDOE ; 22.901 ; ; ; 22.901 ;
; nWE ; nDOE ; 27.259 ; ; ; 27.259 ;
; nWE80 ; RD[0] ; 19.386 ; ; ; 19.386 ;
; nWE80 ; RD[1] ; 20.572 ; ; ; 20.572 ;
; nWE80 ; RD[2] ; 19.386 ; ; ; 19.386 ;
; nWE80 ; RD[3] ; 20.572 ; ; ; 20.572 ;
; nWE80 ; RD[4] ; 20.572 ; ; ; 20.572 ;
; nWE80 ; RD[5] ; 19.386 ; ; ; 19.386 ;
; nWE80 ; RD[6] ; 19.386 ; ; ; 19.386 ;
; nWE80 ; RD[7] ; 19.386 ; ; ; 19.386 ;
; Din[0] ; RD[0] ; 19.349 ; ; ; 19.349 ;
; Din[1] ; RD[1] ; 19.378 ; ; ; 19.378 ;
; Din[2] ; RD[2] ; 21.534 ; ; ; 21.534 ;
; Din[3] ; RD[3] ; 19.335 ; ; ; 19.335 ;
; Din[4] ; RD[4] ; 21.330 ; ; ; 21.330 ;
; Din[5] ; RD[5] ; 21.614 ; ; ; 21.614 ;
; Din[6] ; RD[6] ; 19.625 ; ; ; 19.625 ;
; Din[7] ; RD[7] ; 19.254 ; ; ; 19.254 ;
; PHI1 ; nVOE ; 22.494 ; ; ; 22.494 ;
; nEN80 ; RD[0] ; 19.829 ; ; ; 19.829 ;
; nEN80 ; RD[1] ; 21.564 ; ; ; 21.564 ;
; nEN80 ; RD[2] ; 19.829 ; ; ; 19.829 ;
; nEN80 ; RD[3] ; 21.564 ; ; ; 21.564 ;
; nEN80 ; RD[4] ; 21.564 ; ; ; 21.564 ;
; nEN80 ; RD[5] ; 19.829 ; ; ; 19.829 ;
; nEN80 ; RD[6] ; 19.829 ; ; ; 19.829 ;
; nEN80 ; RD[7] ; 19.829 ; ; ; 19.829 ;
; nEN80 ; nDOE ; 27.166 ; ; ; 27.166 ;
; nWE ; nDOE ; 24.346 ; ; ; 24.346 ;
; nWE80 ; RD[0] ; 22.991 ; ; ; 22.991 ;
; nWE80 ; RD[1] ; 24.726 ; ; ; 24.726 ;
; nWE80 ; RD[2] ; 22.991 ; ; ; 22.991 ;
; nWE80 ; RD[3] ; 24.726 ; ; ; 24.726 ;
; nWE80 ; RD[4] ; 24.726 ; ; ; 24.726 ;
; nWE80 ; RD[5] ; 22.991 ; ; ; 22.991 ;
; nWE80 ; RD[6] ; 22.991 ; ; ; 22.991 ;
; nWE80 ; RD[7] ; 22.991 ; ; ; 22.991 ;
+------------+-------------+--------+----+----+--------+
@ -685,33 +689,33 @@ No paths to report.
+------------+-------------+--------+----+----+--------+
; Input Port ; Output Port ; RR ; RF ; FR ; FF ;
+------------+-------------+--------+----+----+--------+
; Din[0] ; RD[0] ; 17.981 ; ; ; 17.981 ;
; Din[1] ; RD[1] ; 17.927 ; ; ; 17.927 ;
; Din[2] ; RD[2] ; 20.142 ; ; ; 20.142 ;
; Din[3] ; RD[3] ; 17.941 ; ; ; 17.941 ;
; Din[4] ; RD[4] ; 19.866 ; ; ; 19.866 ;
; Din[5] ; RD[5] ; 19.798 ; ; ; 19.798 ;
; Din[6] ; RD[6] ; 18.337 ; ; ; 18.337 ;
; Din[7] ; RD[7] ; 17.921 ; ; ; 17.921 ;
; PHI1 ; nVOE ; 14.089 ; ; ; 14.089 ;
; nEN80 ; RD[0] ; 20.841 ; ; ; 20.841 ;
; nEN80 ; RD[1] ; 22.027 ; ; ; 22.027 ;
; nEN80 ; RD[2] ; 20.841 ; ; ; 20.841 ;
; nEN80 ; RD[3] ; 22.027 ; ; ; 22.027 ;
; nEN80 ; RD[4] ; 22.027 ; ; ; 22.027 ;
; nEN80 ; RD[5] ; 20.841 ; ; ; 20.841 ;
; nEN80 ; RD[6] ; 20.841 ; ; ; 20.841 ;
; nEN80 ; RD[7] ; 20.841 ; ; ; 20.841 ;
; nEN80 ; nDOE ; 22.901 ; ; ; 22.901 ;
; nWE ; nDOE ; 27.259 ; ; ; 27.259 ;
; nWE80 ; RD[0] ; 19.386 ; ; ; 19.386 ;
; nWE80 ; RD[1] ; 20.572 ; ; ; 20.572 ;
; nWE80 ; RD[2] ; 19.386 ; ; ; 19.386 ;
; nWE80 ; RD[3] ; 20.572 ; ; ; 20.572 ;
; nWE80 ; RD[4] ; 20.572 ; ; ; 20.572 ;
; nWE80 ; RD[5] ; 19.386 ; ; ; 19.386 ;
; nWE80 ; RD[6] ; 19.386 ; ; ; 19.386 ;
; nWE80 ; RD[7] ; 19.386 ; ; ; 19.386 ;
; Din[0] ; RD[0] ; 19.349 ; ; ; 19.349 ;
; Din[1] ; RD[1] ; 19.378 ; ; ; 19.378 ;
; Din[2] ; RD[2] ; 21.534 ; ; ; 21.534 ;
; Din[3] ; RD[3] ; 19.335 ; ; ; 19.335 ;
; Din[4] ; RD[4] ; 21.330 ; ; ; 21.330 ;
; Din[5] ; RD[5] ; 21.614 ; ; ; 21.614 ;
; Din[6] ; RD[6] ; 19.625 ; ; ; 19.625 ;
; Din[7] ; RD[7] ; 19.254 ; ; ; 19.254 ;
; PHI1 ; nVOE ; 22.494 ; ; ; 22.494 ;
; nEN80 ; RD[0] ; 19.829 ; ; ; 19.829 ;
; nEN80 ; RD[1] ; 21.564 ; ; ; 21.564 ;
; nEN80 ; RD[2] ; 19.829 ; ; ; 19.829 ;
; nEN80 ; RD[3] ; 21.564 ; ; ; 21.564 ;
; nEN80 ; RD[4] ; 21.564 ; ; ; 21.564 ;
; nEN80 ; RD[5] ; 19.829 ; ; ; 19.829 ;
; nEN80 ; RD[6] ; 19.829 ; ; ; 19.829 ;
; nEN80 ; RD[7] ; 19.829 ; ; ; 19.829 ;
; nEN80 ; nDOE ; 27.166 ; ; ; 27.166 ;
; nWE ; nDOE ; 24.346 ; ; ; 24.346 ;
; nWE80 ; RD[0] ; 22.991 ; ; ; 22.991 ;
; nWE80 ; RD[1] ; 24.726 ; ; ; 24.726 ;
; nWE80 ; RD[2] ; 22.991 ; ; ; 22.991 ;
; nWE80 ; RD[3] ; 24.726 ; ; ; 24.726 ;
; nWE80 ; RD[4] ; 24.726 ; ; ; 24.726 ;
; nWE80 ; RD[5] ; 22.991 ; ; ; 22.991 ;
; nWE80 ; RD[6] ; 22.991 ; ; ; 22.991 ;
; nWE80 ; RD[7] ; 22.991 ; ; ; 22.991 ;
+------------+-------------+--------+----+----+--------+
@ -720,7 +724,7 @@ No paths to report.
+------------+----------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+----------+----------+----------+----------+
; C14M ; C14M ; 1346 ; 0 ; 64 ; 0 ;
; C14M ; C14M ; 1432 ; 0 ; 64 ; 0 ;
+------------+----------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
@ -730,7 +734,7 @@ Entries labeled "false path" only account for clock-to-clock false paths and not
+------------+----------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+----------+----------+----------+----------+
; C14M ; C14M ; 1346 ; 0 ; 64 ; 0 ;
; C14M ; C14M ; 1432 ; 0 ; 64 ; 0 ;
+------------+----------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
@ -755,9 +759,9 @@ No dedicated SERDES Receiver circuitry present in device or used in design
; Illegal Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 2 ; 2 ;
; Unconstrained Input Ports ; 29 ; 29 ;
; Unconstrained Input Port Paths ; 141 ; 141 ;
; Unconstrained Input Port Paths ; 151 ; 151 ;
; Unconstrained Output Ports ; 47 ; 47 ;
; Unconstrained Output Port Paths ; 64 ; 64 ;
; Unconstrained Output Port Paths ; 65 ; 65 ;
+---------------------------------+-------+------+
@ -767,7 +771,7 @@ No dedicated SERDES Receiver circuitry present in device or used in design
Info: *******************************************************************
Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Tue Sep 08 19:28:20 2020
Info: Processing started: Wed Sep 16 19:34:50 2020
Info: Command: quartus_sta RAM2E -c RAM2E
Info: qsta_default_script.tcl version: #1
Warning (20028): Parallel compilation is not licensed and has been disabled
@ -779,14 +783,14 @@ Info (332104): Reading SDC File: 'constraints.sdc'
Warning (332060): Node: DRCLK was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: ARCLK was determined to be a clock but was found without an associated clock assignment.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info (332146): Worst-case setup slack is 22.276
Info (332146): Worst-case setup slack is 22.294
Info (332119): Slack End Point TNS Clock
Info (332119): ========= ============= =====================
Info (332119): 22.276 0.000 C14M
Info (332146): Worst-case hold slack is 3.130
Info (332119): 22.294 0.000 C14M
Info (332146): Worst-case hold slack is 3.117
Info (332119): Slack End Point TNS Clock
Info (332119): ========= ============= =====================
Info (332119): 3.130 0.000 C14M
Info (332119): 3.117 0.000 C14M
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is 34.581
@ -797,8 +801,8 @@ Info (332001): The selected device family is not supported by the report_metasta
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings
Info: Peak virtual memory: 4528 megabytes
Info: Processing ended: Tue Sep 08 19:28:21 2020
Info: Peak virtual memory: 4522 megabytes
Info: Processing ended: Wed Sep 16 19:34:51 2020
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01

View File

@ -3,11 +3,11 @@ TimeQuest Timing Analyzer Summary
------------------------------------------------------------
Type : Setup 'C14M'
Slack : 22.276
Slack : 22.294
TNS : 0.000
Type : Hold 'C14M'
Slack : 3.130
Slack : 3.117
TNS : 0.000
Type : Minimum Pulse Width 'C14M'

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