mirror of
https://github.com/garrettsworkshop/RAM2E.git
synced 2024-06-04 14:29:32 +00:00
8eb7ead8ee
Gated RAM access during PHI0, squeezed video access and MPU access together, gated data bus output buffer OE to only output at end of PHI0
26 lines
349 B
Plaintext
26 lines
349 B
Plaintext
ERASE_TIME=500000000
|
|
INTENDED_DEVICE_FAMILY="MAX V"
|
|
LPM_FILE=RAM2E.mif
|
|
LPM_HINT=UNUSED
|
|
LPM_TYPE=altufm_none
|
|
OSC_FREQUENCY=180000
|
|
PORT_ARCLKENA=PORT_UNUSED
|
|
PORT_DRCLKENA=PORT_UNUSED
|
|
PROGRAM_TIME=1600000
|
|
WIDTH_UFM_ADDRESS=9
|
|
DEVICE_FAMILY="MAX V"
|
|
CBX_AUTO_BLACKBOX=ALL
|
|
arclk
|
|
ardin
|
|
arshft
|
|
busy
|
|
drclk
|
|
drdin
|
|
drdout
|
|
drshft
|
|
erase
|
|
osc
|
|
oscena
|
|
program
|
|
rtpbusy
|