mirror of
https://github.com/garrettsworkshop/RAM2E.git
synced 2024-06-04 14:29:32 +00:00
8eb7ead8ee
Gated RAM access during PHI0, squeezed video access and MPU access together, gated data bus output buffer OE to only output at end of PHI0
12 lines
365 B
Plaintext
Executable File
12 lines
365 B
Plaintext
Executable File
Fitter Status : Successful - Wed Sep 16 19:34:48 2020
|
|
Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
|
|
Revision Name : RAM2E
|
|
Top-level Entity Name : RAM2E
|
|
Family : MAX V
|
|
Device : 5M240ZT100C5
|
|
Timing Models : Final
|
|
Total logic elements : 199 / 240 ( 83 % )
|
|
Total pins : 69 / 79 ( 87 % )
|
|
Total virtual pins : 0
|
|
UFM blocks : 1 / 1 ( 100 % )
|