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8eb7ead8ee
Gated RAM access during PHI0, squeezed video access and MPU access together, gated data bus output buffer OE to only output at end of PHI0
10 lines
306 B
Plaintext
Executable File
10 lines
306 B
Plaintext
Executable File
Analysis & Synthesis Status : Successful - Wed Sep 16 19:34:45 2020
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Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
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Revision Name : RAM2E
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Top-level Entity Name : RAM2E
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Family : MAX V
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Total logic elements : 208
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Total pins : 69
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Total virtual pins : 0
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UFM blocks : 1 / 1 ( 100 % )
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