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759 lines
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759 lines
36 KiB
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<HEAD><TITLE>Synthesis Report</TITLE>
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<PRE><A name="Syn"></A><B><U><big>Synthesis Report</big></U></B>
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#Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021
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#install: C:\lscc\diamond\3.12\synpbase
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#OS: Windows 8 6.2
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#Hostname: ZANEMACWIN11
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# Thu Dec 28 23:09:45 2023
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#Implementation: impl1
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Copyright (C) 1994-2021 Synopsys, Inc.
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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
|
and may only be used pursuant to the terms and conditions of a written license agreement
|
|
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
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Synopsys software or the associated documentation is strictly prohibited.
|
|
Tool: Synplify Pro (R)
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Build: R-2021.03L-SP1
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Install: C:\lscc\diamond\3.12\synpbase
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OS: Windows 6.2
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Hostname: ZANEMACWIN11
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Implementation : impl1
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Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
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@N|Running in 64-bit mode
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###########################################################[
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Copyright (C) 1994-2021 Synopsys, Inc.
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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
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|
and may only be used pursuant to the terms and conditions of a written license agreement
|
|
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
|
Synopsys software or the associated documentation is strictly prohibited.
|
|
Tool: Synplify Pro (R)
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Build: R-2021.03L-SP1
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Install: C:\lscc\diamond\3.12\synpbase
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OS: Windows 6.2
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Hostname: ZANEMACWIN11
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Implementation : impl1
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Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
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@N|Running in 64-bit mode
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@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v" (library work)
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@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
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@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
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@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
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@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
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@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
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@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v" (library work)
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@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v" (library work)
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@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\REFB.v" (library work)
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Verilog syntax check successful!
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Selecting top level module RAM2E
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@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
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Running optimization stage 1 on VHI .......
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Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
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@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
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Running optimization stage 1 on VLO .......
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Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
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@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
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Running optimization stage 1 on EFB .......
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Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
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@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
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Running optimization stage 1 on REFB .......
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Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
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@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v":1:7:1:15|Synthesizing module RAM2E_UFM in library work.
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Running optimization stage 1 on RAM2E_UFM .......
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Finished optimization stage 1 on RAM2E_UFM (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB)
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@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v":1:7:1:11|Synthesizing module RAM2E in library work.
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Running optimization stage 1 on RAM2E .......
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Finished optimization stage 1 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB)
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Running optimization stage 2 on RAM2E .......
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@N: CL159 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v":11:15:11:19|Input nWE80 is unused.
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Finished optimization stage 2 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
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Running optimization stage 2 on RAM2E_UFM .......
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@N: CL159 :"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v":10:7:10:11|Input Ready is unused.
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Finished optimization stage 2 on RAM2E_UFM (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
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Running optimization stage 2 on REFB .......
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Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
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Running optimization stage 2 on EFB .......
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Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
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Running optimization stage 2 on VLO .......
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Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
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Running optimization stage 2 on VHI .......
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Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
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At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 102MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Thu Dec 28 23:09:45 2023
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###########################################################]
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###########################################################[
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Copyright (C) 1994-2021 Synopsys, Inc.
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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
|
and may only be used pursuant to the terms and conditions of a written license agreement
|
|
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
|
Synopsys software or the associated documentation is strictly prohibited.
|
|
Tool: Synplify Pro (R)
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Build: R-2021.03L-SP1
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Install: C:\lscc\diamond\3.12\synpbase
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OS: Windows 6.2
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Hostname: ZANEMACWIN11
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Implementation : impl1
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Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
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@N|Running in 64-bit mode
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At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Thu Dec 28 23:09:46 2023
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###########################################################]
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For a summary of runtime and memory usage for all design units, please see file:
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==========================================================
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@L: A:\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_comp.rt.csv
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@END
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At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Thu Dec 28 23:09:46 2023
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###########################################################]
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###########################################################[
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Copyright (C) 1994-2021 Synopsys, Inc.
|
|
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
|
and may only be used pursuant to the terms and conditions of a written license agreement
|
|
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
|
Synopsys software or the associated documentation is strictly prohibited.
|
|
Tool: Synplify Pro (R)
|
|
Build: R-2021.03L-SP1
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Install: C:\lscc\diamond\3.12\synpbase
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OS: Windows 6.2
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Hostname: ZANEMACWIN11
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Implementation : impl1
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Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
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@N|Running in 64-bit mode
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File \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_comp.srs changed - recompiling
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At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Thu Dec 28 23:09:47 2023
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###########################################################]
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# Thu Dec 28 23:09:47 2023
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Copyright (C) 1994-2021 Synopsys, Inc.
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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
|
and may only be used pursuant to the terms and conditions of a written license agreement
|
|
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
|
Synopsys software or the associated documentation is strictly prohibited.
|
|
Tool: Synplify Pro (R)
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Build: R-2021.03L-SP1
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Install: C:\lscc\diamond\3.12\synpbase
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OS: Windows 6.2
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Hostname: ZANEMACWIN11
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Implementation : impl1
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Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @
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Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
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Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 140MB)
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Reading constraint file: \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
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@L: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1_scck.rpt
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See clock summary report "\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1_scck.rpt"
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@N: MF916 |Option synthesis_strategy=base is enabled.
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@N: MF248 |Running in 64-bit mode.
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@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
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Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 140MB)
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Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 140MB)
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Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 149MB)
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Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 151MB)
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@N: FX493 |Applying initial value "0" on instance CmdBitbangMXO2.
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@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
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@N: FX493 |Applying initial value "0" on instance CmdExecMXO2.
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@N: FX493 |Applying initial value "0" on instance PHI1r.
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@N: FX493 |Applying initial value "0" on instance RWSel.
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@N: FX493 |Applying initial value "0" on instance Ready.
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@N: FX493 |Applying initial value "00000000" on instance RWBank[7:0].
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@N: FX493 |Applying initial value "0" on instance CmdLEDGet.
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@N: FX493 |Applying initial value "0" on instance CmdLEDSet.
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@N: FX493 |Applying initial value "0" on instance CmdRWMaskSet.
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@N: FX493 |Applying initial value "0" on instance CmdSetRWBankFFLED.
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@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Initial value on register DQMH is non-zero which can prevent the register from being packed into a block RAM or DSP.
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@N: FX493 |Applying initial value "1" on instance DQMH.
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@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Initial value on register DQML is non-zero which can prevent the register from being packed into a block RAM or DSP.
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@N: FX493 |Applying initial value "1" on instance DQML.
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@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":21:4:21:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
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@N: FX493 |Applying initial value "0000" on instance S[3:0].
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@N: FX493 |Applying initial value "1" on instance CKE.
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@N: FX493 |Applying initial value "1" on instance nRWE.
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@N: FX493 |Applying initial value "1" on instance nRWEout.
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@N: FX493 |Applying initial value "1" on instance nCAS.
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@N: FX493 |Applying initial value "1" on instance nCASout.
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@N: FX493 |Applying initial value "1" on instance nRAS.
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@N: FX493 |Applying initial value "1" on instance nRASout.
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Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
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Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
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Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
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Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
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@N: FX1184 |Applying syn_allowed_resources blockrams=7 on top level netlist RAM2E
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Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
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Clock Summary
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******************
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Start Requested Requested Clock Clock Clock
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Level Clock Frequency Period Type Group Load
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----------------------------------------------------------------------------------------
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0 - C14M 14.3 MHz 69.841 declared default_clkgroup 122
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0 - System 100.0 MHz 10.000 system system_clkgroup 0
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========================================================================================
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Clock Load Summary
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***********************
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Clock Source Clock Pin Non-clock Pin Non-clock Pin
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Clock Load Pin Seq Example Seq Example Comb Example
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----------------------------------------------------------------------------------------
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C14M 122 C14M(port) DOEEN.C - un1_C14M.I[0](inv)
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System 0 - - - -
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========================================================================================
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ICG Latch Removal Summary:
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Number of ICG latches removed: 0
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Number of ICG latches not removed: 0
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For details review file gcc_ICG_report.rpt
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@S |Clock Optimization Summary
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#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
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1 non-gated/non-generated clock tree(s) driving 122 clock pin(s) of sequential element(s)
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0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
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0 instances converted, 0 sequential instances remain driven by gated/generated clocks
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=========================== Non-Gated/Non-Generated Clocks ============================
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Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
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---------------------------------------------------------------------------------------
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@KP:ckid0_0 C14M port 122 nRAS
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=======================================================================================
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##### END OF CLOCK OPTIMIZATION REPORT ######
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@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
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Finished Pre Mapping Phase.
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Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
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Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
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Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
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Pre-mapping successful!
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At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 99MB peak: 185MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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# Thu Dec 28 23:09:49 2023
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###########################################################]
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# Thu Dec 28 23:09:49 2023
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Copyright (C) 1994-2021 Synopsys, Inc.
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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
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and may only be used pursuant to the terms and conditions of a written license agreement
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with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
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Synopsys software or the associated documentation is strictly prohibited.
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Tool: Synplify Pro (R)
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Build: R-2021.03L-SP1
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Install: C:\lscc\diamond\3.12\synpbase
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OS: Windows 6.2
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Hostname: ZANEMACWIN11
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Implementation : impl1
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Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @
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Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
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@N: MF916 |Option synthesis_strategy=base is enabled.
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@N: MF248 |Running in 64-bit mode.
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@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
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Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 139MB)
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Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 139MB)
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Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
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Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 146MB)
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Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 178MB peak: 178MB)
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Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB)
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@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":14:23:14:28|Found counter in view:work.RAM2E(verilog) instance FS[15:0]
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@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
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Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB)
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Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
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Available hyper_sources - for debug and ip models
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None Found
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Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
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Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
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Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 191MB)
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Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 191MB)
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Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 191MB)
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Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 211MB peak: 211MB)
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Pass CPU time Worst Slack Luts / Registers
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------------------------------------------------------------
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1 0h:00m:02s 33.71ns 284 / 122
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Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 211MB peak: 211MB)
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@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
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@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Boundary register BA_1_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
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@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Boundary register BA_0_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
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Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 212MB peak: 212MB)
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Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 174MB peak: 212MB)
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Writing Analyst data base \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_m.srm
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Finished Writing Netlist Databases (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 212MB peak: 212MB)
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Writing EDIF Netlist and constraint files
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@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1.edi
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@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
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Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB)
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Finished Writing Netlists (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB)
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Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 215MB peak: 217MB)
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@W: MT246 :"\\mac\icloud\repos\ram2e\cpld\lcmxo2-1200hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
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@N: MT615 |Found clock C14M with period 69.84ns
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##### START OF TIMING REPORT #####[
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# Timing report written on Thu Dec 28 23:09:54 2023
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#
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Top view: RAM2E
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Requested Frequency: 14.3 MHz
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Wire load mode: top
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Paths requested: 5
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Constraint File(s): \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
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@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
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@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
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Performance Summary
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*******************
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Worst slack in design: 33.707
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Requested Estimated Requested Estimated Clock Clock
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Starting Clock Frequency Frequency Period Period Slack Type Group
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-------------------------------------------------------------------------------------------------------------------
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C14M 14.3 MHz 128.0 MHz 69.841 7.813 33.707 declared default_clkgroup
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System 100.0 MHz NA 10.000 NA 67.088 system system_clkgroup
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===================================================================================================================
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Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
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Clock Relationships
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*******************
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Clocks | rise to rise | fall to fall | rise to fall | fall to rise
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----------------------------------------------------------------------------------------------------------
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Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
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----------------------------------------------------------------------------------------------------------
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System C14M | 69.841 67.088 | No paths - | No paths - | No paths -
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C14M System | 69.841 68.797 | No paths - | No paths - | No paths -
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C14M C14M | 69.841 62.028 | No paths - | 34.920 33.707 | No paths -
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==========================================================================================================
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Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
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'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
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Interface Information
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*********************
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No IO constraint found
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====================================
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Detailed Report for Clock: C14M
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====================================
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Starting Points with Worst Slack
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********************************
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Starting Arrival
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Instance Reference Type Pin Net Time Slack
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Clock
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---------------------------------------------------------------------------
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RA[0] C14M FD1P3AX Q RA[0] 1.108 33.707
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RA[3] C14M FD1P3AX Q RA[3] 1.108 33.707
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RA[1] C14M FD1P3AX Q RA[1] 1.044 33.771
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RA[2] C14M FD1P3AX Q RA[2] 1.044 33.771
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RA[4] C14M FD1P3AX Q RA[4] 1.044 33.771
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RA[5] C14M FD1P3AX Q RA[5] 1.044 33.771
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RA[6] C14M FD1P3AX Q RA[6] 1.044 33.771
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RA[7] C14M FD1P3AX Q RA[7] 1.044 33.771
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RA[8] C14M FD1P3AX Q RA[8] 1.044 33.771
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RA[9] C14M FD1P3AX Q RA[9] 1.044 33.771
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===========================================================================
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Ending Points with Worst Slack
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******************************
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Starting Required
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Instance Reference Type Pin Net Time Slack
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Clock
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---------------------------------------------------------------------------------
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RAout_0io[0] C14M OFS1P3DX D RA[0] 34.815 33.707
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RAout_0io[3] C14M OFS1P3DX D RA[3] 34.815 33.707
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RAout_0io[1] C14M OFS1P3DX D RA[1] 34.815 33.771
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RAout_0io[2] C14M OFS1P3DX D RA[2] 34.815 33.771
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RAout_0io[4] C14M OFS1P3DX D RA[4] 34.815 33.771
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RAout_0io[5] C14M OFS1P3DX D RA[5] 34.815 33.771
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RAout_0io[6] C14M OFS1P3DX D RA[6] 34.815 33.771
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RAout_0io[7] C14M OFS1P3DX D RA[7] 34.815 33.771
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RAout_0io[8] C14M OFS1P3DX D RA[8] 34.815 33.771
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RAout_0io[9] C14M OFS1P3DX D RA[9] 34.815 33.771
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=================================================================================
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Worst Path Information
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***********************
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Path information for path number 1:
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Requested Period: 34.920
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- Setup time: 0.106
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+ Clock delay at ending point: 0.000 (ideal)
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= Required time: 34.815
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- Propagation time: 1.108
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- Clock delay at starting point: 0.000 (ideal)
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= Slack (critical) : 33.707
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Number of logic level(s): 0
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Starting point: RA[0] / Q
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Ending point: RAout_0io[0] / D
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The start point is clocked by C14M [rising] (rise=0.000 fall=34.920 period=69.841) on pin CK
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The end point is clocked by C14M [falling] (rise=0.000 fall=34.920 period=69.841) on pin SCLK
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Instance / Net Pin Pin Arrival No. of
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Name Type Name Dir Delay Time Fan Out(s)
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---------------------------------------------------------------------------------
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RA[0] FD1P3AX Q Out 1.108 1.108 r -
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RA[0] Net - - - - 3
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RAout_0io[0] OFS1P3DX D In 0.000 1.108 r -
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=================================================================================
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====================================
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Detailed Report for Clock: System
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====================================
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Starting Points with Worst Slack
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********************************
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Starting Arrival
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Instance Reference Type Pin Net Time Slack
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Clock
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---------------------------------------------------------------------------------------------------
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ram2e_ufm.ufmefb.EFBInst_0 System EFB WBACKO wb_ack 0.000 67.088
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ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO0 wb_dato[0] 0.000 69.313
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ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000 69.313
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ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO2 wb_dato[2] 0.000 69.313
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ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO3 wb_dato[3] 0.000 69.313
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ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO4 wb_dato[4] 0.000 69.313
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ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO5 wb_dato[5] 0.000 69.313
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ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO6 wb_dato[6] 0.000 69.313
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ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO7 wb_dato[7] 0.000 69.313
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===================================================================================================
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Ending Points with Worst Slack
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******************************
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Starting Required
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Instance Reference Type Pin Net Time Slack
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Clock
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----------------------------------------------------------------------------------------------------------------------
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ram2e_ufm.RWMask[0] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088
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ram2e_ufm.RWMask[1] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088
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ram2e_ufm.RWMask[2] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088
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ram2e_ufm.RWMask[3] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088
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ram2e_ufm.RWMask[4] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088
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ram2e_ufm.RWMask[5] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088
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ram2e_ufm.RWMask[6] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088
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ram2e_ufm.RWMask[7] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088
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ram2e_ufm.LEDEN System FD1P3AX SP un1_LEDEN_0_sqmuxa_1_i_0_0[0] 69.369 67.736
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ram2e_ufm.wb_cyc_stb System FD1P3AX SP un1_CmdSetRWBankFFChip13_1_i_0_0[0] 69.369 67.736
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======================================================================================================================
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Worst Path Information
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***********************
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Path information for path number 1:
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Requested Period: 69.841
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- Setup time: 0.472
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+ Clock delay at ending point: 0.000 (ideal)
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= Required time: 69.369
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- Propagation time: 2.282
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- Clock delay at starting point: 0.000 (ideal)
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- Estimated clock delay at start point: -0.000
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= Slack (non-critical) : 67.088
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Number of logic level(s): 2
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Starting point: ram2e_ufm.ufmefb.EFBInst_0 / WBACKO
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Ending point: ram2e_ufm.RWMask[0] / SP
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The start point is clocked by System [rising]
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The end point is clocked by C14M [rising] (rise=0.000 fall=34.920 period=69.841) on pin CK
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Instance / Net Pin Pin Arrival No. of
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Name Type Name Dir Delay Time Fan Out(s)
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------------------------------------------------------------------------------------------------------------------
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ram2e_ufm.ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 r -
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wb_ack Net - - - - 5
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ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] ORCALUT4 B In 0.000 0.000 r -
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ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] ORCALUT4 Z Out 1.017 1.017 r -
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un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] Net - - - - 1
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ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_0[0] ORCALUT4 D In 0.000 1.017 r -
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ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_0[0] ORCALUT4 Z Out 1.265 2.282 r -
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un1_RWMask_0_sqmuxa_1_i_0_0[0] Net - - - - 8
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ram2e_ufm.RWMask[0] FD1P3AX SP In 0.000 2.282 r -
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==================================================================================================================
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##### END OF TIMING REPORT #####]
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Timing exceptions that could not be applied
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Finished final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 216MB peak: 217MB)
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Finished timing report (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 216MB peak: 217MB)
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---------------------------------------
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Resource Usage Report
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Part: lcmxo2_1200hc-4
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Register bits: 122 of 1280 (10%)
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PIC Latch: 0
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I/O cells: 69
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Details:
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BB: 8
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CCU2D: 9
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EFB: 1
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FD1P3AX: 61
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FD1P3IX: 1
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FD1S3AX: 21
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FD1S3AY: 4
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FD1S3IX: 6
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GSR: 1
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IB: 21
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IFS1P3DX: 1
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INV: 1
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OB: 40
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OFS1P3BX: 5
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OFS1P3DX: 21
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OFS1P3IX: 2
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ORCALUT4: 277
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PFUMX: 3
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PUR: 1
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VHI: 3
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VLO: 3
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Mapper successful!
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At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 79MB peak: 217MB)
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Process took 0h:00m:04s realtime, 0h:00m:04s cputime
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# Thu Dec 28 23:09:54 2023
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###########################################################]
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