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https://github.com/garrettsworkshop/RAM2GS.git
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30 lines
1.1 KiB
Plaintext
30 lines
1.1 KiB
Plaintext
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SCUBA, Version Diamond (64-bit) 3.11.3.469
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Sun Jul 14 22:23:22 2024
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
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BEGIN SCUBA Module Synthesis
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Issued command : C:\lscc\diamond\3.11_x64\ispfpga\bin\nt64\scuba.exe -w -n RPLL -lang verilog -synth synplify -arch xo2c00 -type pll -fin 133.0 -fclkop 61 -fclkop_tol 1.0 -trimp 0 -phasep 0 -trimp_r -phase_cntl STATIC -fb_mode 1
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Circuit name : RPLL
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Module type : pll
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Module Version : 5.7
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Ports :
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Inputs : CLKI
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Outputs : CLKOP
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I/O buffer : not inserted
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EDIF output : RPLL.edn
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Verilog output : RPLL.v
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Verilog template : RPLL_tmpl.v
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Verilog purpose : for synthesis and simulation
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Bus notation : big endian
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Report output : RPLL.srp
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Estimated Resource Usage:
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END SCUBA Module Synthesis
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