mirror of
https://github.com/garrettsworkshop/RAM2GS.git
synced 2025-02-20 09:29:07 +00:00
Add LCMXO2 internal oscillator firmware build
This commit is contained in:
Zane Kaminski
parent
9449460535
commit
51d7ed8056
2574
CPLD/LCMXO2-1200HC-IntOsc/._Real_._Math_.vhd
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2574
CPLD/LCMXO2-1200HC-IntOsc/._Real_._Math_.vhd
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File diff suppressed because it is too large
Load Diff
4
CPLD/LCMXO2-1200HC-IntOsc/.setting.ini
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4
CPLD/LCMXO2-1200HC-IntOsc/.setting.ini
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[General]
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Map.auto_tasks=@@empty()
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PAR.auto_tasks=@@empty()
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Export.auto_tasks=Jedecgen
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1
CPLD/LCMXO2-1200HC-IntOsc/RAM2GS-LCMXO2.ccl
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1
CPLD/LCMXO2-1200HC-IntOsc/RAM2GS-LCMXO2.ccl
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VERSION=20110520
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26
CPLD/LCMXO2-1200HC-IntOsc/RAM2GS_LCMXO2_1200HC.ldf
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26
CPLD/LCMXO2-1200HC-IntOsc/RAM2GS_LCMXO2_1200HC.ldf
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<?xml version="1.0" encoding="UTF-8"?>
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<BaliProject version="3.2" title="RAM2GS_LCMXO2_1200HC" device="LCMXO2-1200HC-4TG100C" default_implementation="impl1">
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<Options/>
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<Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
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<Options def_top="RAM2GS"/>
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<Source name="REFB.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="../RAM2GS-LCMXO2-IntOsc.v" type="Verilog" type_short="Verilog">
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<Options top_module="RAM2GS"/>
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</Source>
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<Source name="RPLL.ipx" type="IPX_Module" type_short="IPX">
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<Options/>
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</Source>
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<Source name="impl1/impl1.xcf" type="Programming Project File" type_short="Programming">
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<Options/>
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</Source>
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<Source name="../RAM2GS-LCMXO2.lpf" type="Logic Preference" type_short="LPF">
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<Options/>
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</Source>
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<Source name="../RAM2GS.sdc" type="Synplify Design Constraints File" type_short="SDC">
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<Options/>
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</Source>
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</Implementation>
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<Strategy name="Strategy1" file="RAM2GS_LCMXO2_1200HC1.sty"/>
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</BaliProject>
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203
CPLD/LCMXO2-1200HC-IntOsc/RAM2GS_LCMXO2_1200HC1.sty
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203
CPLD/LCMXO2-1200HC-IntOsc/RAM2GS_LCMXO2_1200HC1.sty
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<?xml version="1.0" encoding="UTF-8"?>
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<!DOCTYPE strategy>
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<Strategy version="1.0" predefined="0" description="" label="Strategy1">
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<Property name="PROP_BD_CmdLineArgs" value="" time="0"/>
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<Property name="PROP_BD_EdfHardtimer" value="Enable" time="0"/>
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<Property name="PROP_BD_EdfInBusNameConv" value="None" time="0"/>
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<Property name="PROP_BD_EdfInLibPath" value="" time="0"/>
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<Property name="PROP_BD_EdfInRemLoc" value="Off" time="0"/>
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<Property name="PROP_BD_EdfMemPath" value="" time="0"/>
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<Property name="PROP_BD_ParSearchPath" value="" time="0"/>
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<Property name="PROP_BIT_AddressBitGen" value="Increment" time="0"/>
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<Property name="PROP_BIT_AllowReadBitGen" value="Disable" time="0"/>
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<Property name="PROP_BIT_ByteWideBitMirror" value="Disable" time="0"/>
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||||
<Property name="PROP_BIT_CapReadBitGen" value="Disable" time="0"/>
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||||
<Property name="PROP_BIT_ConModBitGen" value="Disable" time="0"/>
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<Property name="PROP_BIT_CreateBitFile" value="True" time="0"/>
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<Property name="PROP_BIT_DisRAMResBitGen" value="True" time="0"/>
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<Property name="PROP_BIT_DisableUESBitgen" value="False" time="0"/>
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<Property name="PROP_BIT_DonePinBitGen" value="Pullup" time="0"/>
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<Property name="PROP_BIT_DoneSigBitGen" value="4" time="0"/>
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<Property name="PROP_BIT_EnIOBitGen" value="TriStateDuringReConfig" time="0"/>
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<Property name="PROP_BIT_EnIntOscBitGen" value="Disable" time="0"/>
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<Property name="PROP_BIT_ExtClockBitGen" value="False" time="0"/>
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<Property name="PROP_BIT_GSREnableBitGen" value="True" time="0"/>
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<Property name="PROP_BIT_GSRRelOnBitGen" value="DoneIn" time="0"/>
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<Property name="PROP_BIT_GranTimBitGen" value="0" time="0"/>
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<Property name="PROP_BIT_IOTriRelBitGen" value="Cycle 2" time="0"/>
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<Property name="PROP_BIT_JTAGEnableBitGen" value="False" time="0"/>
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<Property name="PROP_BIT_LenBitsBitGen" value="24" time="0"/>
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<Property name="PROP_BIT_MIFFileBitGen" value="" time="0"/>
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<Property name="PROP_BIT_NoHeader" value="False" time="0"/>
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<Property name="PROP_BIT_OutFormatBitGen" value="Bit File (Binary)" time="0"/>
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<Property name="PROP_BIT_OutFormatBitGen_REF" value="" time="0"/>
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<Property name="PROP_BIT_OutFormatPromGen" value="Intel Hex 32-bit" time="0"/>
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<Property name="PROP_BIT_ParityCheckBitGen" value="True" time="0"/>
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<Property name="PROP_BIT_ReadBackBitGen" value="Flash" time="0"/>
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<Property name="PROP_BIT_ReadCaptureBitGen" value="Disable" time="0"/>
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<Property name="PROP_BIT_RemZeroFramesBitGen" value="False" time="0"/>
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<Property name="PROP_BIT_RunDRCBitGen" value="True" time="0"/>
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<Property name="PROP_BIT_SearchPthBitGen" value="" time="0"/>
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<Property name="PROP_BIT_StartUpClkBitGen" value="Cclk" time="0"/>
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<Property name="PROP_BIT_SynchIOBitGen" value="True" time="0"/>
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<Property name="PROP_BIT_SysClockConBitGen" value="Reset" time="0"/>
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<Property name="PROP_BIT_SysConBitGen" value="Reset" time="0"/>
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<Property name="PROP_BIT_WaitStTimBitGen" value="5" time="0"/>
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<Property name="PROP_IOTIMING_AllSpeed" value="False" time="0"/>
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<Property name="PROP_LST_AllowDUPMod" value="False" time="0"/>
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<Property name="PROP_LST_CarryChain" value="True" time="0"/>
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<Property name="PROP_LST_CarryChainLength" value="0" time="0"/>
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<Property name="PROP_LST_CmdLineArgs" value="" time="0"/>
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<Property name="PROP_LST_DSPStyle" value="DSP" time="0"/>
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<Property name="PROP_LST_DSPUtil" value="100" time="0"/>
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<Property name="PROP_LST_DecodeUnreachableStates" value="False" time="0"/>
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<Property name="PROP_LST_DisableDistRam" value="False" time="0"/>
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<Property name="PROP_LST_EBRUtil" value="100" time="0"/>
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<Property name="PROP_LST_EdfFrequency" value="200" time="0"/>
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<Property name="PROP_LST_EdfHardtimer" value="Enable" time="0"/>
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<Property name="PROP_LST_EdfInLibPath" value="" time="0"/>
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<Property name="PROP_LST_EdfInRemLoc" value="Off" time="0"/>
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||||
<Property name="PROP_LST_EdfMemPath" value="" time="0"/>
|
||||
<Property name="PROP_LST_FIXGATEDCLKS" value="True" time="0"/>
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<Property name="PROP_LST_FSMEncodeStyle" value="Auto" time="0"/>
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<Property name="PROP_LST_ForceGSRInfer" value="Auto" time="0"/>
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<Property name="PROP_LST_IOInsertion" value="True" time="0"/>
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<Property name="PROP_LST_InterFileDump" value="False" time="0"/>
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<Property name="PROP_LST_LoopLimit" value="1950" time="0"/>
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||||
<Property name="PROP_LST_MaxFanout" value="1000" time="0"/>
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||||
<Property name="PROP_LST_MuxStyle" value="Auto" time="0"/>
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<Property name="PROP_LST_NumCriticalPaths" value="3" time="0"/>
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<Property name="PROP_LST_OptimizeGoal" value="Balanced" time="0"/>
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<Property name="PROP_LST_PropagatConst" value="True" time="0"/>
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<Property name="PROP_LST_RAMStyle" value="Auto" time="0"/>
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<Property name="PROP_LST_ROMStyle" value="Auto" time="0"/>
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<Property name="PROP_LST_RemoveDupRegs" value="True" time="0"/>
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<Property name="PROP_LST_ResolvedMixedDrivers" value="False" time="0"/>
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||||
<Property name="PROP_LST_ResourceShare" value="True" time="0"/>
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<Property name="PROP_LST_UseIOReg" value="Auto" time="0"/>
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<Property name="PROP_LST_UseLPF" value="True" time="0"/>
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<Property name="PROP_LST_VHDL2008" value="False" time="0"/>
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<Property name="PROP_MAPSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
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<Property name="PROP_MAPSTA_AutoTiming" value="True" time="0"/>
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<Property name="PROP_MAPSTA_CheckUnconstrainedConns" value="False" time="0"/>
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<Property name="PROP_MAPSTA_CheckUnconstrainedPaths" value="False" time="0"/>
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||||
<Property name="PROP_MAPSTA_FullName" value="False" time="0"/>
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<Property name="PROP_MAPSTA_NumUnconstrainedPaths" value="0" time="0"/>
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<Property name="PROP_MAPSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
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||||
<Property name="PROP_MAPSTA_RouteEstAlogtithm" value="0" time="0"/>
|
||||
<Property name="PROP_MAPSTA_RptAsynTimLoop" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_WordCasePaths" value="1" time="0"/>
|
||||
<Property name="PROP_MAP_IgnorePreErr" value="True" time="0"/>
|
||||
<Property name="PROP_MAP_MAPIORegister" value="Auto" time="0"/>
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<Property name="PROP_MAP_MAPInferGSR" value="True" time="0"/>
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<Property name="PROP_MAP_MapModArgs" value="" time="0"/>
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||||
<Property name="PROP_MAP_OvermapDevice" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_PackLogMapDes" value="0" time="0"/>
|
||||
<Property name="PROP_MAP_RegRetiming" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_SigCrossRef" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_SymCrossRef" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_TimingDriven" value="False" time="0"/>
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<Property name="PROP_MAP_TimingDrivenNodeRep" value="False" time="0"/>
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<Property name="PROP_MAP_TimingDrivenPack" value="False" time="0"/>
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<Property name="PROP_PARSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
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<Property name="PROP_PARSTA_AutoTiming" value="True" time="0"/>
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<Property name="PROP_PARSTA_CheckUnconstrainedConns" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_CheckUnconstrainedPaths" value="False" time="0"/>
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<Property name="PROP_PARSTA_FullName" value="False" time="0"/>
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||||
<Property name="PROP_PARSTA_NumUnconstrainedPaths" value="0" time="0"/>
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||||
<Property name="PROP_PARSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
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||||
<Property name="PROP_PARSTA_RptAsynTimLoop" value="False" time="0"/>
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<Property name="PROP_PARSTA_SpeedForHoldAnalysis" value="m" time="0"/>
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||||
<Property name="PROP_PARSTA_SpeedForSetupAnalysis" value="default" time="0"/>
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||||
<Property name="PROP_PARSTA_WordCasePaths" value="10" time="0"/>
|
||||
<Property name="PROP_PAR_CrDlyStFileParDes" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_DisableTDParDes" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_EffortParDes" value="5" time="0"/>
|
||||
<Property name="PROP_PAR_MultiSeedSortMode" value="Worst Slack" time="0"/>
|
||||
<Property name="PROP_PAR_NewRouteParDes" value="NBR" time="0"/>
|
||||
<Property name="PROP_PAR_PARClockSkew" value="Off" time="0"/>
|
||||
<Property name="PROP_PAR_PARModArgs" value="" time="0"/>
|
||||
<Property name="PROP_PAR_ParMultiNodeList" value="" time="0"/>
|
||||
<Property name="PROP_PAR_ParRunPlaceOnly" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_PlcIterParDes" value="1" time="0"/>
|
||||
<Property name="PROP_PAR_PlcStCostTblParDes" value="1" time="0"/>
|
||||
<Property name="PROP_PAR_PrefErrorOut" value="True" time="0"/>
|
||||
<Property name="PROP_PAR_RemoveDir" value="True" time="0"/>
|
||||
<Property name="PROP_PAR_RouteDlyRedParDes" value="0" time="0"/>
|
||||
<Property name="PROP_PAR_RoutePassParDes" value="6" time="0"/>
|
||||
<Property name="PROP_PAR_RouteResOptParDes" value="0" time="0"/>
|
||||
<Property name="PROP_PAR_RoutingCDP" value="0" time="0"/>
|
||||
<Property name="PROP_PAR_RoutingCDR" value="0" time="0"/>
|
||||
<Property name="PROP_PAR_RunParWithTrce" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_SaveBestRsltParDes" value="1" time="0"/>
|
||||
<Property name="PROP_PAR_StopZero" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_parHold" value="On" time="0"/>
|
||||
<Property name="PROP_PAR_parPathBased" value="Off" time="0"/>
|
||||
<Property name="PROP_PRE_CmdLineArgs" value="" time="0"/>
|
||||
<Property name="PROP_PRE_EdfArrayBoundsCase" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfAutoResOfRam" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfClockDomainCross" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfDSPAcrossHie" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfFullCase" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfIgnoreRamRWCol" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfMissConstraint" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfNetFanout" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfParaCase" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfReencodeFSM" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfResSharing" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfTimingViolation" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfUseSafeFSM" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfVlog2001" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynComArea" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynCritcal" value="3" time="0"/>
|
||||
<Property name="PROP_PRE_VSynFSM" value="Auto" time="0"/>
|
||||
<Property name="PROP_PRE_VSynFreq" value="200" time="0"/>
|
||||
<Property name="PROP_PRE_VSynGSR" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_VSynGatedClk" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_VSynIOPad" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_VSynOutNetForm" value="None" time="0"/>
|
||||
<Property name="PROP_PRE_VSynOutPref" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynRepClkFreq" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynRetime" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynTimSum" value="10" time="0"/>
|
||||
<Property name="PROP_PRE_VSynTransform" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSyninpd" value="0" time="0"/>
|
||||
<Property name="PROP_PRE_VSynoutd" value="0" time="0"/>
|
||||
<Property name="PROP_SYN_ClockConversion" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_CmdLineArgs" value="" time="0"/>
|
||||
<Property name="PROP_SYN_EdfAllowDUPMod" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfArea" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfArrangeVHDLFiles" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfDefEnumEncode" value="Default" time="0"/>
|
||||
<Property name="PROP_SYN_EdfFanout" value="1000" time="0"/>
|
||||
<Property name="PROP_SYN_EdfFrequency" value="100" time="0"/>
|
||||
<Property name="PROP_SYN_EdfGSR" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfInsertIO" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfNumCritPath" value="" time="0"/>
|
||||
<Property name="PROP_SYN_EdfNumStartEnd" value="" time="0"/>
|
||||
<Property name="PROP_SYN_EdfOutNetForm" value="None" time="0"/>
|
||||
<Property name="PROP_SYN_EdfPushTirstates" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfResSharing" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfRunRetiming" value="Pipelining Only" time="0"/>
|
||||
<Property name="PROP_SYN_EdfSymFSM" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfUnconsClk" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfVerilogInput" value="Verilog 2001" time="0"/>
|
||||
<Property name="PROP_SYN_ExportSetting" value="No" time="0"/>
|
||||
<Property name="PROP_SYN_LibPath" value="" time="0"/>
|
||||
<Property name="PROP_SYN_ResolvedMixedDrivers" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_UpdateCompilePtTimData" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_UseLPF" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_VHDL2008" value="False" time="0"/>
|
||||
<Property name="PROP_THERMAL_DefaultFreq" value="0" time="0"/>
|
||||
<Property name="PROP_TIM_MaxDelSimDes" value="" time="0"/>
|
||||
<Property name="PROP_TIM_MinSpeedGrade" value="False" time="0"/>
|
||||
<Property name="PROP_TIM_ModPreSimDes" value="" time="0"/>
|
||||
<Property name="PROP_TIM_NegStupHldTim" value="True" time="0"/>
|
||||
<Property name="PROP_TIM_TimSimGenPUR" value="True" time="0"/>
|
||||
<Property name="PROP_TIM_TimSimGenX" value="False" time="0"/>
|
||||
<Property name="PROP_TIM_TimSimHierSep" value="" time="0"/>
|
||||
<Property name="PROP_TIM_TransportModeOfPathDelay" value="False" time="0"/>
|
||||
<Property name="PROP_TIM_TrgtSpeedGrade" value="" time="0"/>
|
||||
<Property name="PROP_TIM_WriteVerboseNetlist" value="False" time="0"/>
|
||||
<Property name="PROP_TMCHK_EnableCheck" value="True" time="0"/>
|
||||
</Strategy>
|
||||
72
CPLD/LCMXO2-1200HC-IntOsc/RAM2GS_LCMXO2_1200HC_tcl.html
Normal file
72
CPLD/LCMXO2-1200HC-IntOsc/RAM2GS_LCMXO2_1200HC_tcl.html
Normal file
@ -0,0 +1,72 @@
|
||||
<HTML>
|
||||
<HEAD><TITLE>Lattice TCL Log</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="pn240714185505"></A><B><U><big>pn240714185505</big></U></B>
|
||||
#Start recording tcl command: 7/14/2024 18:47:20
|
||||
#Project Location: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC-IntOsc; Project name: RAM2GS_LCMXO2_1200HC
|
||||
prj_project open "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC-IntOsc/RAM2GS_LCMXO2_1200HC.ldf"
|
||||
prj_src add "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC-IntOsc/RPLL.v"
|
||||
prj_run Export -impl impl1 -task IBIS
|
||||
prj_run Export -impl impl1
|
||||
#Stop recording: 7/14/2024 18:55:05
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
550
CPLD/LCMXO2-1200HC-IntOsc/REFB.edn
Normal file
550
CPLD/LCMXO2-1200HC-IntOsc/REFB.edn
Normal file
@ -0,0 +1,550 @@
|
||||
(edif REFB
|
||||
(edifVersion 2 0 0)
|
||||
(edifLevel 0)
|
||||
(keywordMap (keywordLevel 0))
|
||||
(status
|
||||
(written
|
||||
(timestamp 2023 9 21 4 34 49)
|
||||
(program "SCUBA" (version "Diamond (64-bit) 3.12.1.454"))))
|
||||
(comment "C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 66.7 -ufm -ufm_ebr 190 -mem_size 321 -memfile ../RAM2GS-LCMXO2.mem -memformat hex -wb -dev 1200 ")
|
||||
(library ORCLIB
|
||||
(edifLevel 0)
|
||||
(technology
|
||||
(numberDefinition))
|
||||
(cell VHI
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port Z
|
||||
(direction OUTPUT)))))
|
||||
(cell VLO
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port Z
|
||||
(direction OUTPUT)))))
|
||||
(cell EFB
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port WBCLKI
|
||||
(direction INPUT))
|
||||
(port WBRSTI
|
||||
(direction INPUT))
|
||||
(port WBCYCI
|
||||
(direction INPUT))
|
||||
(port WBSTBI
|
||||
(direction INPUT))
|
||||
(port WBWEI
|
||||
(direction INPUT))
|
||||
(port WBADRI7
|
||||
(direction INPUT))
|
||||
(port WBADRI6
|
||||
(direction INPUT))
|
||||
(port WBADRI5
|
||||
(direction INPUT))
|
||||
(port WBADRI4
|
||||
(direction INPUT))
|
||||
(port WBADRI3
|
||||
(direction INPUT))
|
||||
(port WBADRI2
|
||||
(direction INPUT))
|
||||
(port WBADRI1
|
||||
(direction INPUT))
|
||||
(port WBADRI0
|
||||
(direction INPUT))
|
||||
(port WBDATI7
|
||||
(direction INPUT))
|
||||
(port WBDATI6
|
||||
(direction INPUT))
|
||||
(port WBDATI5
|
||||
(direction INPUT))
|
||||
(port WBDATI4
|
||||
(direction INPUT))
|
||||
(port WBDATI3
|
||||
(direction INPUT))
|
||||
(port WBDATI2
|
||||
(direction INPUT))
|
||||
(port WBDATI1
|
||||
(direction INPUT))
|
||||
(port WBDATI0
|
||||
(direction INPUT))
|
||||
(port PLL0DATI7
|
||||
(direction INPUT))
|
||||
(port PLL0DATI6
|
||||
(direction INPUT))
|
||||
(port PLL0DATI5
|
||||
(direction INPUT))
|
||||
(port PLL0DATI4
|
||||
(direction INPUT))
|
||||
(port PLL0DATI3
|
||||
(direction INPUT))
|
||||
(port PLL0DATI2
|
||||
(direction INPUT))
|
||||
(port PLL0DATI1
|
||||
(direction INPUT))
|
||||
(port PLL0DATI0
|
||||
(direction INPUT))
|
||||
(port PLL0ACKI
|
||||
(direction INPUT))
|
||||
(port PLL1DATI7
|
||||
(direction INPUT))
|
||||
(port PLL1DATI6
|
||||
(direction INPUT))
|
||||
(port PLL1DATI5
|
||||
(direction INPUT))
|
||||
(port PLL1DATI4
|
||||
(direction INPUT))
|
||||
(port PLL1DATI3
|
||||
(direction INPUT))
|
||||
(port PLL1DATI2
|
||||
(direction INPUT))
|
||||
(port PLL1DATI1
|
||||
(direction INPUT))
|
||||
(port PLL1DATI0
|
||||
(direction INPUT))
|
||||
(port PLL1ACKI
|
||||
(direction INPUT))
|
||||
(port I2C1SCLI
|
||||
(direction INPUT))
|
||||
(port I2C1SDAI
|
||||
(direction INPUT))
|
||||
(port I2C2SCLI
|
||||
(direction INPUT))
|
||||
(port I2C2SDAI
|
||||
(direction INPUT))
|
||||
(port SPISCKI
|
||||
(direction INPUT))
|
||||
(port SPIMISOI
|
||||
(direction INPUT))
|
||||
(port SPIMOSII
|
||||
(direction INPUT))
|
||||
(port SPISCSN
|
||||
(direction INPUT))
|
||||
(port TCCLKI
|
||||
(direction INPUT))
|
||||
(port TCRSTN
|
||||
(direction INPUT))
|
||||
(port TCIC
|
||||
(direction INPUT))
|
||||
(port UFMSN
|
||||
(direction INPUT))
|
||||
(port WBDATO7
|
||||
(direction OUTPUT))
|
||||
(port WBDATO6
|
||||
(direction OUTPUT))
|
||||
(port WBDATO5
|
||||
(direction OUTPUT))
|
||||
(port WBDATO4
|
||||
(direction OUTPUT))
|
||||
(port WBDATO3
|
||||
(direction OUTPUT))
|
||||
(port WBDATO2
|
||||
(direction OUTPUT))
|
||||
(port WBDATO1
|
||||
(direction OUTPUT))
|
||||
(port WBDATO0
|
||||
(direction OUTPUT))
|
||||
(port WBACKO
|
||||
(direction OUTPUT))
|
||||
(port PLLCLKO
|
||||
(direction OUTPUT))
|
||||
(port PLLRSTO
|
||||
(direction OUTPUT))
|
||||
(port PLL0STBO
|
||||
(direction OUTPUT))
|
||||
(port PLL1STBO
|
||||
(direction OUTPUT))
|
||||
(port PLLWEO
|
||||
(direction OUTPUT))
|
||||
(port PLLADRO4
|
||||
(direction OUTPUT))
|
||||
(port PLLADRO3
|
||||
(direction OUTPUT))
|
||||
(port PLLADRO2
|
||||
(direction OUTPUT))
|
||||
(port PLLADRO1
|
||||
(direction OUTPUT))
|
||||
(port PLLADRO0
|
||||
(direction OUTPUT))
|
||||
(port PLLDATO7
|
||||
(direction OUTPUT))
|
||||
(port PLLDATO6
|
||||
(direction OUTPUT))
|
||||
(port PLLDATO5
|
||||
(direction OUTPUT))
|
||||
(port PLLDATO4
|
||||
(direction OUTPUT))
|
||||
(port PLLDATO3
|
||||
(direction OUTPUT))
|
||||
(port PLLDATO2
|
||||
(direction OUTPUT))
|
||||
(port PLLDATO1
|
||||
(direction OUTPUT))
|
||||
(port PLLDATO0
|
||||
(direction OUTPUT))
|
||||
(port I2C1SCLO
|
||||
(direction OUTPUT))
|
||||
(port I2C1SCLOEN
|
||||
(direction OUTPUT))
|
||||
(port I2C1SDAO
|
||||
(direction OUTPUT))
|
||||
(port I2C1SDAOEN
|
||||
(direction OUTPUT))
|
||||
(port I2C2SCLO
|
||||
(direction OUTPUT))
|
||||
(port I2C2SCLOEN
|
||||
(direction OUTPUT))
|
||||
(port I2C2SDAO
|
||||
(direction OUTPUT))
|
||||
(port I2C2SDAOEN
|
||||
(direction OUTPUT))
|
||||
(port I2C1IRQO
|
||||
(direction OUTPUT))
|
||||
(port I2C2IRQO
|
||||
(direction OUTPUT))
|
||||
(port SPISCKO
|
||||
(direction OUTPUT))
|
||||
(port SPISCKEN
|
||||
(direction OUTPUT))
|
||||
(port SPIMISOO
|
||||
(direction OUTPUT))
|
||||
(port SPIMISOEN
|
||||
(direction OUTPUT))
|
||||
(port SPIMOSIO
|
||||
(direction OUTPUT))
|
||||
(port SPIMOSIEN
|
||||
(direction OUTPUT))
|
||||
(port SPIMCSN7
|
||||
(direction OUTPUT))
|
||||
(port SPIMCSN6
|
||||
(direction OUTPUT))
|
||||
(port SPIMCSN5
|
||||
(direction OUTPUT))
|
||||
(port SPIMCSN4
|
||||
(direction OUTPUT))
|
||||
(port SPIMCSN3
|
||||
(direction OUTPUT))
|
||||
(port SPIMCSN2
|
||||
(direction OUTPUT))
|
||||
(port SPIMCSN1
|
||||
(direction OUTPUT))
|
||||
(port SPIMCSN0
|
||||
(direction OUTPUT))
|
||||
(port SPICSNEN
|
||||
(direction OUTPUT))
|
||||
(port SPIIRQO
|
||||
(direction OUTPUT))
|
||||
(port TCINT
|
||||
(direction OUTPUT))
|
||||
(port TCOC
|
||||
(direction OUTPUT))
|
||||
(port WBCUFMIRQ
|
||||
(direction OUTPUT))
|
||||
(port CFGWAKE
|
||||
(direction OUTPUT))
|
||||
(port CFGSTDBY
|
||||
(direction OUTPUT)))))
|
||||
(cell REFB
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port wb_clk_i
|
||||
(direction INPUT))
|
||||
(port wb_rst_i
|
||||
(direction INPUT))
|
||||
(port wb_cyc_i
|
||||
(direction INPUT))
|
||||
(port wb_stb_i
|
||||
(direction INPUT))
|
||||
(port wb_we_i
|
||||
(direction INPUT))
|
||||
(port (array (rename wb_adr_i "wb_adr_i(7:0)") 8)
|
||||
(direction INPUT))
|
||||
(port (array (rename wb_dat_i "wb_dat_i(7:0)") 8)
|
||||
(direction INPUT))
|
||||
(port (array (rename wb_dat_o "wb_dat_o(7:0)") 8)
|
||||
(direction OUTPUT))
|
||||
(port wb_ack_o
|
||||
(direction OUTPUT))
|
||||
(port wbc_ufm_irq
|
||||
(direction OUTPUT)))
|
||||
(property NGD_DRC_MASK (integer 1))
|
||||
(contents
|
||||
(instance scuba_vhi_inst
|
||||
(viewRef view1
|
||||
(cellRef VHI)))
|
||||
(instance scuba_vlo_inst
|
||||
(viewRef view1
|
||||
(cellRef VLO)))
|
||||
(instance EFBInst_0
|
||||
(viewRef view1
|
||||
(cellRef EFB))
|
||||
(property UFM_INIT_FILE_FORMAT
|
||||
(string "HEX"))
|
||||
(property UFM_INIT_FILE_NAME
|
||||
(string "../RAM2GS-LCMXO2.mem"))
|
||||
(property UFM_INIT_ALL_ZEROS
|
||||
(string "DISABLED"))
|
||||
(property UFM_INIT_START_PAGE
|
||||
(string "190"))
|
||||
(property UFM_INIT_PAGES
|
||||
(string "321"))
|
||||
(property DEV_DENSITY
|
||||
(string "1200L"))
|
||||
(property EFB_UFM
|
||||
(string "ENABLED"))
|
||||
(property TC_ICAPTURE
|
||||
(string "DISABLED"))
|
||||
(property TC_OVERFLOW
|
||||
(string "DISABLED"))
|
||||
(property TC_ICR_INT
|
||||
(string "OFF"))
|
||||
(property TC_OCR_INT
|
||||
(string "OFF"))
|
||||
(property TC_OV_INT
|
||||
(string "OFF"))
|
||||
(property TC_TOP_SEL
|
||||
(string "OFF"))
|
||||
(property TC_RESETN
|
||||
(string "ENABLED"))
|
||||
(property TC_OC_MODE
|
||||
(string "TOGGLE"))
|
||||
(property TC_OCR_SET
|
||||
(string "32767"))
|
||||
(property TC_TOP_SET
|
||||
(string "65535"))
|
||||
(property GSR
|
||||
(string "ENABLED"))
|
||||
(property TC_CCLK_SEL
|
||||
(string "1"))
|
||||
(property TC_MODE
|
||||
(string "CTCM"))
|
||||
(property TC_SCLK_SEL
|
||||
(string "PCLOCK"))
|
||||
(property EFB_TC_PORTMODE
|
||||
(string "WB"))
|
||||
(property EFB_TC
|
||||
(string "DISABLED"))
|
||||
(property SPI_WAKEUP
|
||||
(string "DISABLED"))
|
||||
(property SPI_INTR_RXOVR
|
||||
(string "DISABLED"))
|
||||
(property SPI_INTR_TXOVR
|
||||
(string "DISABLED"))
|
||||
(property SPI_INTR_RXRDY
|
||||
(string "DISABLED"))
|
||||
(property SPI_INTR_TXRDY
|
||||
(string "DISABLED"))
|
||||
(property SPI_SLAVE_HANDSHAKE
|
||||
(string "DISABLED"))
|
||||
(property SPI_PHASE_ADJ
|
||||
(string "DISABLED"))
|
||||
(property SPI_CLK_INV
|
||||
(string "DISABLED"))
|
||||
(property SPI_LSB_FIRST
|
||||
(string "DISABLED"))
|
||||
(property SPI_CLK_DIVIDER
|
||||
(string "1"))
|
||||
(property SPI_MODE
|
||||
(string "MASTER"))
|
||||
(property EFB_SPI
|
||||
(string "DISABLED"))
|
||||
(property I2C2_WAKEUP
|
||||
(string "DISABLED"))
|
||||
(property I2C2_GEN_CALL
|
||||
(string "DISABLED"))
|
||||
(property I2C2_CLK_DIVIDER
|
||||
(string "1"))
|
||||
(property I2C2_BUS_PERF
|
||||
(string "100kHz"))
|
||||
(property I2C2_SLAVE_ADDR
|
||||
(string "0b1000010"))
|
||||
(property I2C2_ADDRESSING
|
||||
(string "7BIT"))
|
||||
(property EFB_I2C2
|
||||
(string "DISABLED"))
|
||||
(property I2C1_WAKEUP
|
||||
(string "DISABLED"))
|
||||
(property I2C1_GEN_CALL
|
||||
(string "DISABLED"))
|
||||
(property I2C1_CLK_DIVIDER
|
||||
(string "1"))
|
||||
(property I2C1_BUS_PERF
|
||||
(string "100kHz"))
|
||||
(property I2C1_SLAVE_ADDR
|
||||
(string "0b1000001"))
|
||||
(property I2C1_ADDRESSING
|
||||
(string "7BIT"))
|
||||
(property EFB_I2C1
|
||||
(string "DISABLED"))
|
||||
(property EFB_WB_CLK_FREQ
|
||||
(string "66.7")))
|
||||
(net scuba_vhi
|
||||
(joined
|
||||
(portRef Z (instanceRef scuba_vhi_inst))
|
||||
(portRef UFMSN (instanceRef EFBInst_0))))
|
||||
(net scuba_vlo
|
||||
(joined
|
||||
(portRef Z (instanceRef scuba_vlo_inst))
|
||||
(portRef PLL1DATI7 (instanceRef EFBInst_0))
|
||||
(portRef PLL1DATI6 (instanceRef EFBInst_0))
|
||||
(portRef PLL1DATI5 (instanceRef EFBInst_0))
|
||||
(portRef PLL1DATI4 (instanceRef EFBInst_0))
|
||||
(portRef PLL1DATI3 (instanceRef EFBInst_0))
|
||||
(portRef PLL1DATI2 (instanceRef EFBInst_0))
|
||||
(portRef PLL1DATI1 (instanceRef EFBInst_0))
|
||||
(portRef PLL1DATI0 (instanceRef EFBInst_0))
|
||||
(portRef PLL1ACKI (instanceRef EFBInst_0))
|
||||
(portRef PLL0DATI7 (instanceRef EFBInst_0))
|
||||
(portRef PLL0DATI6 (instanceRef EFBInst_0))
|
||||
(portRef PLL0DATI5 (instanceRef EFBInst_0))
|
||||
(portRef PLL0DATI4 (instanceRef EFBInst_0))
|
||||
(portRef PLL0DATI3 (instanceRef EFBInst_0))
|
||||
(portRef PLL0DATI2 (instanceRef EFBInst_0))
|
||||
(portRef PLL0DATI1 (instanceRef EFBInst_0))
|
||||
(portRef PLL0DATI0 (instanceRef EFBInst_0))
|
||||
(portRef PLL0ACKI (instanceRef EFBInst_0))
|
||||
(portRef TCIC (instanceRef EFBInst_0))
|
||||
(portRef TCRSTN (instanceRef EFBInst_0))
|
||||
(portRef TCCLKI (instanceRef EFBInst_0))
|
||||
(portRef SPISCSN (instanceRef EFBInst_0))
|
||||
(portRef SPIMOSII (instanceRef EFBInst_0))
|
||||
(portRef SPIMISOI (instanceRef EFBInst_0))
|
||||
(portRef SPISCKI (instanceRef EFBInst_0))
|
||||
(portRef I2C2SDAI (instanceRef EFBInst_0))
|
||||
(portRef I2C2SCLI (instanceRef EFBInst_0))
|
||||
(portRef I2C1SDAI (instanceRef EFBInst_0))
|
||||
(portRef I2C1SCLI (instanceRef EFBInst_0))))
|
||||
(net wbc_ufm_irq
|
||||
(joined
|
||||
(portRef wbc_ufm_irq)
|
||||
(portRef WBCUFMIRQ (instanceRef EFBInst_0))))
|
||||
(net wb_ack_o
|
||||
(joined
|
||||
(portRef wb_ack_o)
|
||||
(portRef WBACKO (instanceRef EFBInst_0))))
|
||||
(net wb_dat_o7
|
||||
(joined
|
||||
(portRef (member wb_dat_o 0))
|
||||
(portRef WBDATO7 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_o6
|
||||
(joined
|
||||
(portRef (member wb_dat_o 1))
|
||||
(portRef WBDATO6 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_o5
|
||||
(joined
|
||||
(portRef (member wb_dat_o 2))
|
||||
(portRef WBDATO5 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_o4
|
||||
(joined
|
||||
(portRef (member wb_dat_o 3))
|
||||
(portRef WBDATO4 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_o3
|
||||
(joined
|
||||
(portRef (member wb_dat_o 4))
|
||||
(portRef WBDATO3 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_o2
|
||||
(joined
|
||||
(portRef (member wb_dat_o 5))
|
||||
(portRef WBDATO2 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_o1
|
||||
(joined
|
||||
(portRef (member wb_dat_o 6))
|
||||
(portRef WBDATO1 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_o0
|
||||
(joined
|
||||
(portRef (member wb_dat_o 7))
|
||||
(portRef WBDATO0 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_i7
|
||||
(joined
|
||||
(portRef (member wb_dat_i 0))
|
||||
(portRef WBDATI7 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_i6
|
||||
(joined
|
||||
(portRef (member wb_dat_i 1))
|
||||
(portRef WBDATI6 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_i5
|
||||
(joined
|
||||
(portRef (member wb_dat_i 2))
|
||||
(portRef WBDATI5 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_i4
|
||||
(joined
|
||||
(portRef (member wb_dat_i 3))
|
||||
(portRef WBDATI4 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_i3
|
||||
(joined
|
||||
(portRef (member wb_dat_i 4))
|
||||
(portRef WBDATI3 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_i2
|
||||
(joined
|
||||
(portRef (member wb_dat_i 5))
|
||||
(portRef WBDATI2 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_i1
|
||||
(joined
|
||||
(portRef (member wb_dat_i 6))
|
||||
(portRef WBDATI1 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_i0
|
||||
(joined
|
||||
(portRef (member wb_dat_i 7))
|
||||
(portRef WBDATI0 (instanceRef EFBInst_0))))
|
||||
(net wb_adr_i7
|
||||
(joined
|
||||
(portRef (member wb_adr_i 0))
|
||||
(portRef WBADRI7 (instanceRef EFBInst_0))))
|
||||
(net wb_adr_i6
|
||||
(joined
|
||||
(portRef (member wb_adr_i 1))
|
||||
(portRef WBADRI6 (instanceRef EFBInst_0))))
|
||||
(net wb_adr_i5
|
||||
(joined
|
||||
(portRef (member wb_adr_i 2))
|
||||
(portRef WBADRI5 (instanceRef EFBInst_0))))
|
||||
(net wb_adr_i4
|
||||
(joined
|
||||
(portRef (member wb_adr_i 3))
|
||||
(portRef WBADRI4 (instanceRef EFBInst_0))))
|
||||
(net wb_adr_i3
|
||||
(joined
|
||||
(portRef (member wb_adr_i 4))
|
||||
(portRef WBADRI3 (instanceRef EFBInst_0))))
|
||||
(net wb_adr_i2
|
||||
(joined
|
||||
(portRef (member wb_adr_i 5))
|
||||
(portRef WBADRI2 (instanceRef EFBInst_0))))
|
||||
(net wb_adr_i1
|
||||
(joined
|
||||
(portRef (member wb_adr_i 6))
|
||||
(portRef WBADRI1 (instanceRef EFBInst_0))))
|
||||
(net wb_adr_i0
|
||||
(joined
|
||||
(portRef (member wb_adr_i 7))
|
||||
(portRef WBADRI0 (instanceRef EFBInst_0))))
|
||||
(net wb_we_i
|
||||
(joined
|
||||
(portRef wb_we_i)
|
||||
(portRef WBWEI (instanceRef EFBInst_0))))
|
||||
(net wb_stb_i
|
||||
(joined
|
||||
(portRef wb_stb_i)
|
||||
(portRef WBSTBI (instanceRef EFBInst_0))))
|
||||
(net wb_cyc_i
|
||||
(joined
|
||||
(portRef wb_cyc_i)
|
||||
(portRef WBCYCI (instanceRef EFBInst_0))))
|
||||
(net wb_rst_i
|
||||
(joined
|
||||
(portRef wb_rst_i)
|
||||
(portRef WBRSTI (instanceRef EFBInst_0))))
|
||||
(net wb_clk_i
|
||||
(joined
|
||||
(portRef wb_clk_i)
|
||||
(portRef WBCLKI (instanceRef EFBInst_0))))))))
|
||||
(design REFB
|
||||
(cellRef REFB
|
||||
(libraryRef ORCLIB)))
|
||||
)
|
||||
8
CPLD/LCMXO2-1200HC-IntOsc/REFB.ipx
Normal file
8
CPLD/LCMXO2-1200HC-IntOsc/REFB.ipx
Normal file
@ -0,0 +1,8 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<DiamondModule name="REFB" module="EFB" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2023 09 21 04:34:51.977" version="1.2" type="Module" synthesis="synplify" source_format="Verilog">
|
||||
<Package>
|
||||
<File name="REFB.lpc" type="lpc" modified="2023 09 21 04:34:49.038"/>
|
||||
<File name="REFB.v" type="top_level_verilog" modified="2023 09 21 04:34:49.107"/>
|
||||
<File name="REFB_tmpl.v" type="template_verilog" modified="2023 09 21 04:34:49.108"/>
|
||||
</Package>
|
||||
</DiamondModule>
|
||||
141
CPLD/LCMXO2-1200HC-IntOsc/REFB.lpc
Normal file
141
CPLD/LCMXO2-1200HC-IntOsc/REFB.lpc
Normal file
@ -0,0 +1,141 @@
|
||||
[Device]
|
||||
Family=machxo2
|
||||
PartType=LCMXO2-1200HC
|
||||
PartName=LCMXO2-1200HC-4TG100C
|
||||
SpeedGrade=4
|
||||
Package=TQFP100
|
||||
OperatingCondition=COM
|
||||
Status=S
|
||||
|
||||
[IP]
|
||||
VendorName=Lattice Semiconductor Corporation
|
||||
CoreType=LPM
|
||||
CoreStatus=Demo
|
||||
CoreName=EFB
|
||||
CoreRevision=1.2
|
||||
ModuleName=REFB
|
||||
SourceFormat=Verilog HDL
|
||||
ParameterFileVersion=1.0
|
||||
Date=09/21/2023
|
||||
Time=04:34:49
|
||||
|
||||
[Parameters]
|
||||
Verilog=1
|
||||
VHDL=0
|
||||
EDIF=1
|
||||
Destination=Synplicity
|
||||
Expression=BusA(0 to 7)
|
||||
Order=Big Endian [MSB:LSB]
|
||||
IO=0
|
||||
freq=
|
||||
i2c1=0
|
||||
i2c1config=0
|
||||
i2c1_addr=7-Bit Addressing
|
||||
i2c1_ce=0
|
||||
i2c1_freq=100
|
||||
i2c1_sa=10000
|
||||
i2c1_we=0
|
||||
i2c2=0
|
||||
i2c2_addr=7-Bit Addressing
|
||||
i2c2_ce=0
|
||||
i2c2_freq=100
|
||||
i2c2_sa=10000
|
||||
i2c2_we=0
|
||||
ufm_addr=7-Bit Addressing
|
||||
ufm_sa=10000
|
||||
pll=0
|
||||
pll_cnt=1
|
||||
spi=0
|
||||
spi_clkinv=0
|
||||
spi_cs=1
|
||||
spi_en=0
|
||||
spi_freq=1
|
||||
spi_lsb=0
|
||||
spi_mode=Slave
|
||||
spi_ib=0
|
||||
spi_ph=0
|
||||
spi_hs=0
|
||||
spi_rxo=0
|
||||
spi_rxr=0
|
||||
spi_txo=0
|
||||
spi_txr=0
|
||||
spi_we=0
|
||||
static_tc=Static
|
||||
tc=0
|
||||
tc_clkinv=Positive
|
||||
tc_ctr=1
|
||||
tc_div=1
|
||||
tc_ipcap=0
|
||||
tc_mode=CTCM
|
||||
tc_ocr=32767
|
||||
tc_oflow=1
|
||||
tc_o=TOGGLE
|
||||
tc_opcomp=0
|
||||
tc_osc=0
|
||||
tc_sa_oflow=0
|
||||
tc_top=65535
|
||||
ufm=1
|
||||
ufm0=0
|
||||
ufm1=0
|
||||
ufm2=0
|
||||
ufm3=0
|
||||
ufm_cfg0=0
|
||||
ufm_cfg1=0
|
||||
wb_clk_freq=66.7
|
||||
ufm_usage=SHARED_EBR_TAG
|
||||
ufm_ebr=190
|
||||
ufm_remain=
|
||||
mem_size=321
|
||||
ufm_start=
|
||||
ufm_init=mem
|
||||
memfile=../RAM2GS-LCMXO2.mem
|
||||
ufm_dt=hex
|
||||
ufm0_ebr=
|
||||
mem_size0=1
|
||||
ufm0_init=0
|
||||
memfile0=
|
||||
ufm0_dt=hex
|
||||
ufm1_ebr=
|
||||
mem_size1=1
|
||||
ufm1_init=0
|
||||
memfile1=
|
||||
ufm1_dt=hex
|
||||
ufm2_ebr=
|
||||
mem_size2=1
|
||||
ufm2_init=0
|
||||
memfile2=
|
||||
ufm2_dt=hex
|
||||
ufm3_ebr=
|
||||
mem_size3=1
|
||||
ufm3_init=0
|
||||
memfile3=
|
||||
ufm3_dt=hex
|
||||
ufm_cfg0_ebr=
|
||||
mem_size_cfg0=1
|
||||
ufm_cfg0_init=0
|
||||
memfile_cfg0=
|
||||
ufm_cfg0_dt=hex
|
||||
ufm_cfg1_ebr=
|
||||
mem_size_cfg1=1
|
||||
ufm_cfg1_init=0
|
||||
memfile_cfg1=
|
||||
ufm_cfg1_dt=hex
|
||||
wb=1
|
||||
boot_option=Internal
|
||||
efb_ufm=0
|
||||
boot_option_internal=Single Boot
|
||||
internal_ufm0=0
|
||||
internal_ufm1=0
|
||||
efb_ufm_boot=
|
||||
tamperdr=0
|
||||
t_pwd=0
|
||||
t_lockflash=0
|
||||
t_manmode=0
|
||||
t_jtagport=0
|
||||
t_sspiport=0
|
||||
t_sic2port=0
|
||||
t_wbport=0
|
||||
t_portlock=0
|
||||
|
||||
[Command]
|
||||
cmd_line= -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 66.7 -ufm -ufm_ebr 190 -mem_size 321 -memfile ../RAM2GS-LCMXO2.mem -memformat hex -wb -dev 1200
|
||||
31
CPLD/LCMXO2-1200HC-IntOsc/REFB.naf
Normal file
31
CPLD/LCMXO2-1200HC-IntOsc/REFB.naf
Normal file
@ -0,0 +1,31 @@
|
||||
wb_clk_i i
|
||||
wb_rst_i i
|
||||
wb_cyc_i i
|
||||
wb_stb_i i
|
||||
wb_we_i i
|
||||
wb_adr_i[7] i
|
||||
wb_adr_i[6] i
|
||||
wb_adr_i[5] i
|
||||
wb_adr_i[4] i
|
||||
wb_adr_i[3] i
|
||||
wb_adr_i[2] i
|
||||
wb_adr_i[1] i
|
||||
wb_adr_i[0] i
|
||||
wb_dat_i[7] i
|
||||
wb_dat_i[6] i
|
||||
wb_dat_i[5] i
|
||||
wb_dat_i[4] i
|
||||
wb_dat_i[3] i
|
||||
wb_dat_i[2] i
|
||||
wb_dat_i[1] i
|
||||
wb_dat_i[0] i
|
||||
wb_dat_o[7] o
|
||||
wb_dat_o[6] o
|
||||
wb_dat_o[5] o
|
||||
wb_dat_o[4] o
|
||||
wb_dat_o[3] o
|
||||
wb_dat_o[2] o
|
||||
wb_dat_o[1] o
|
||||
wb_dat_o[0] o
|
||||
wb_ack_o o
|
||||
wbc_ufm_irq o
|
||||
1
CPLD/LCMXO2-1200HC-IntOsc/REFB.sort
Normal file
1
CPLD/LCMXO2-1200HC-IntOsc/REFB.sort
Normal file
@ -0,0 +1 @@
|
||||
REFB.v
|
||||
26
CPLD/LCMXO2-1200HC-IntOsc/REFB.srp
Normal file
26
CPLD/LCMXO2-1200HC-IntOsc/REFB.srp
Normal file
@ -0,0 +1,26 @@
|
||||
SCUBA, Version Diamond (64-bit) 3.12.1.454
|
||||
Thu Sep 21 04:34:49 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 66.7 -ufm -ufm_ebr 190 -mem_size 321 -memfile ../RAM2GS-LCMXO2.mem -memformat hex -wb -dev 1200
|
||||
Circuit name : REFB
|
||||
Module type : efb
|
||||
Module Version : 1.2
|
||||
Ports :
|
||||
Inputs : wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i[7:0], wb_dat_i[7:0]
|
||||
Outputs : wb_dat_o[7:0], wb_ack_o, wbc_ufm_irq
|
||||
I/O buffer : not inserted
|
||||
EDIF output : REFB.edn
|
||||
Verilog output : REFB.v
|
||||
Verilog template : REFB_tmpl.v
|
||||
Verilog purpose : for synthesis and simulation
|
||||
Bus notation : big endian
|
||||
Report output : REFB.srp
|
||||
Element Usage :
|
||||
EFB : 1
|
||||
Estimated Resource Usage:
|
||||
BIN
CPLD/LCMXO2-1200HC-IntOsc/REFB.sym
Normal file
BIN
CPLD/LCMXO2-1200HC-IntOsc/REFB.sym
Normal file
Binary file not shown.
113
CPLD/LCMXO2-1200HC-IntOsc/REFB.v
Normal file
113
CPLD/LCMXO2-1200HC-IntOsc/REFB.v
Normal file
@ -0,0 +1,113 @@
|
||||
/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 */
|
||||
/* Module Version: 1.2 */
|
||||
/* C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 66.7 -ufm -ufm_ebr 190 -mem_size 321 -memfile ../RAM2GS-LCMXO2.mem -memformat hex -wb -dev 1200 */
|
||||
/* Thu Sep 21 04:34:49 2023 */
|
||||
|
||||
|
||||
`timescale 1 ns / 1 ps
|
||||
module REFB (wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i,
|
||||
wb_dat_i, wb_dat_o, wb_ack_o, wbc_ufm_irq)/* synthesis NGD_DRC_MASK=1 */;
|
||||
input wire wb_clk_i;
|
||||
input wire wb_rst_i;
|
||||
input wire wb_cyc_i;
|
||||
input wire wb_stb_i;
|
||||
input wire wb_we_i;
|
||||
input wire [7:0] wb_adr_i;
|
||||
input wire [7:0] wb_dat_i;
|
||||
output wire [7:0] wb_dat_o;
|
||||
output wire wb_ack_o;
|
||||
output wire wbc_ufm_irq;
|
||||
|
||||
wire scuba_vhi;
|
||||
wire scuba_vlo;
|
||||
|
||||
VHI scuba_vhi_inst (.Z(scuba_vhi));
|
||||
|
||||
VLO scuba_vlo_inst (.Z(scuba_vlo));
|
||||
|
||||
defparam EFBInst_0.UFM_INIT_FILE_FORMAT = "HEX" ;
|
||||
defparam EFBInst_0.UFM_INIT_FILE_NAME = "../RAM2GS-LCMXO2.mem" ;
|
||||
defparam EFBInst_0.UFM_INIT_ALL_ZEROS = "DISABLED" ;
|
||||
defparam EFBInst_0.UFM_INIT_START_PAGE = 190 ;
|
||||
defparam EFBInst_0.UFM_INIT_PAGES = 321 ;
|
||||
defparam EFBInst_0.DEV_DENSITY = "1200L" ;
|
||||
defparam EFBInst_0.EFB_UFM = "ENABLED" ;
|
||||
defparam EFBInst_0.TC_ICAPTURE = "DISABLED" ;
|
||||
defparam EFBInst_0.TC_OVERFLOW = "DISABLED" ;
|
||||
defparam EFBInst_0.TC_ICR_INT = "OFF" ;
|
||||
defparam EFBInst_0.TC_OCR_INT = "OFF" ;
|
||||
defparam EFBInst_0.TC_OV_INT = "OFF" ;
|
||||
defparam EFBInst_0.TC_TOP_SEL = "OFF" ;
|
||||
defparam EFBInst_0.TC_RESETN = "ENABLED" ;
|
||||
defparam EFBInst_0.TC_OC_MODE = "TOGGLE" ;
|
||||
defparam EFBInst_0.TC_OCR_SET = 32767 ;
|
||||
defparam EFBInst_0.TC_TOP_SET = 65535 ;
|
||||
defparam EFBInst_0.GSR = "ENABLED" ;
|
||||
defparam EFBInst_0.TC_CCLK_SEL = 1 ;
|
||||
defparam EFBInst_0.TC_MODE = "CTCM" ;
|
||||
defparam EFBInst_0.TC_SCLK_SEL = "PCLOCK" ;
|
||||
defparam EFBInst_0.EFB_TC_PORTMODE = "WB" ;
|
||||
defparam EFBInst_0.EFB_TC = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_WAKEUP = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_INTR_RXOVR = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_INTR_TXOVR = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_INTR_RXRDY = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_INTR_TXRDY = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_SLAVE_HANDSHAKE = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_PHASE_ADJ = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_CLK_INV = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_LSB_FIRST = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_CLK_DIVIDER = 1 ;
|
||||
defparam EFBInst_0.SPI_MODE = "MASTER" ;
|
||||
defparam EFBInst_0.EFB_SPI = "DISABLED" ;
|
||||
defparam EFBInst_0.I2C2_WAKEUP = "DISABLED" ;
|
||||
defparam EFBInst_0.I2C2_GEN_CALL = "DISABLED" ;
|
||||
defparam EFBInst_0.I2C2_CLK_DIVIDER = 1 ;
|
||||
defparam EFBInst_0.I2C2_BUS_PERF = "100kHz" ;
|
||||
defparam EFBInst_0.I2C2_SLAVE_ADDR = "0b1000010" ;
|
||||
defparam EFBInst_0.I2C2_ADDRESSING = "7BIT" ;
|
||||
defparam EFBInst_0.EFB_I2C2 = "DISABLED" ;
|
||||
defparam EFBInst_0.I2C1_WAKEUP = "DISABLED" ;
|
||||
defparam EFBInst_0.I2C1_GEN_CALL = "DISABLED" ;
|
||||
defparam EFBInst_0.I2C1_CLK_DIVIDER = 1 ;
|
||||
defparam EFBInst_0.I2C1_BUS_PERF = "100kHz" ;
|
||||
defparam EFBInst_0.I2C1_SLAVE_ADDR = "0b1000001" ;
|
||||
defparam EFBInst_0.I2C1_ADDRESSING = "7BIT" ;
|
||||
defparam EFBInst_0.EFB_I2C1 = "DISABLED" ;
|
||||
defparam EFBInst_0.EFB_WB_CLK_FREQ = "66.7" ;
|
||||
EFB EFBInst_0 (.WBCLKI(wb_clk_i), .WBRSTI(wb_rst_i), .WBCYCI(wb_cyc_i),
|
||||
.WBSTBI(wb_stb_i), .WBWEI(wb_we_i), .WBADRI7(wb_adr_i[7]), .WBADRI6(wb_adr_i[6]),
|
||||
.WBADRI5(wb_adr_i[5]), .WBADRI4(wb_adr_i[4]), .WBADRI3(wb_adr_i[3]),
|
||||
.WBADRI2(wb_adr_i[2]), .WBADRI1(wb_adr_i[1]), .WBADRI0(wb_adr_i[0]),
|
||||
.WBDATI7(wb_dat_i[7]), .WBDATI6(wb_dat_i[6]), .WBDATI5(wb_dat_i[5]),
|
||||
.WBDATI4(wb_dat_i[4]), .WBDATI3(wb_dat_i[3]), .WBDATI2(wb_dat_i[2]),
|
||||
.WBDATI1(wb_dat_i[1]), .WBDATI0(wb_dat_i[0]), .PLL0DATI7(scuba_vlo),
|
||||
.PLL0DATI6(scuba_vlo), .PLL0DATI5(scuba_vlo), .PLL0DATI4(scuba_vlo),
|
||||
.PLL0DATI3(scuba_vlo), .PLL0DATI2(scuba_vlo), .PLL0DATI1(scuba_vlo),
|
||||
.PLL0DATI0(scuba_vlo), .PLL0ACKI(scuba_vlo), .PLL1DATI7(scuba_vlo),
|
||||
.PLL1DATI6(scuba_vlo), .PLL1DATI5(scuba_vlo), .PLL1DATI4(scuba_vlo),
|
||||
.PLL1DATI3(scuba_vlo), .PLL1DATI2(scuba_vlo), .PLL1DATI1(scuba_vlo),
|
||||
.PLL1DATI0(scuba_vlo), .PLL1ACKI(scuba_vlo), .I2C1SCLI(scuba_vlo),
|
||||
.I2C1SDAI(scuba_vlo), .I2C2SCLI(scuba_vlo), .I2C2SDAI(scuba_vlo),
|
||||
.SPISCKI(scuba_vlo), .SPIMISOI(scuba_vlo), .SPIMOSII(scuba_vlo),
|
||||
.SPISCSN(scuba_vlo), .TCCLKI(scuba_vlo), .TCRSTN(scuba_vlo), .TCIC(scuba_vlo),
|
||||
.UFMSN(scuba_vhi), .WBDATO7(wb_dat_o[7]), .WBDATO6(wb_dat_o[6]),
|
||||
.WBDATO5(wb_dat_o[5]), .WBDATO4(wb_dat_o[4]), .WBDATO3(wb_dat_o[3]),
|
||||
.WBDATO2(wb_dat_o[2]), .WBDATO1(wb_dat_o[1]), .WBDATO0(wb_dat_o[0]),
|
||||
.WBACKO(wb_ack_o), .PLLCLKO(), .PLLRSTO(), .PLL0STBO(), .PLL1STBO(),
|
||||
.PLLWEO(), .PLLADRO4(), .PLLADRO3(), .PLLADRO2(), .PLLADRO1(), .PLLADRO0(),
|
||||
.PLLDATO7(), .PLLDATO6(), .PLLDATO5(), .PLLDATO4(), .PLLDATO3(),
|
||||
.PLLDATO2(), .PLLDATO1(), .PLLDATO0(), .I2C1SCLO(), .I2C1SCLOEN(),
|
||||
.I2C1SDAO(), .I2C1SDAOEN(), .I2C2SCLO(), .I2C2SCLOEN(), .I2C2SDAO(),
|
||||
.I2C2SDAOEN(), .I2C1IRQO(), .I2C2IRQO(), .SPISCKO(), .SPISCKEN(),
|
||||
.SPIMISOO(), .SPIMISOEN(), .SPIMOSIO(), .SPIMOSIEN(), .SPIMCSN7(),
|
||||
.SPIMCSN6(), .SPIMCSN5(), .SPIMCSN4(), .SPIMCSN3(), .SPIMCSN2(),
|
||||
.SPIMCSN1(), .SPIMCSN0(), .SPICSNEN(), .SPIIRQO(), .TCINT(), .TCOC(),
|
||||
.WBCUFMIRQ(wbc_ufm_irq), .CFGWAKE(), .CFGSTDBY());
|
||||
|
||||
|
||||
|
||||
// exemplar begin
|
||||
// exemplar end
|
||||
|
||||
endmodule
|
||||
8
CPLD/LCMXO2-1200HC-IntOsc/REFB_tmpl.v
Normal file
8
CPLD/LCMXO2-1200HC-IntOsc/REFB_tmpl.v
Normal file
@ -0,0 +1,8 @@
|
||||
/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.12.1.454 */
|
||||
/* Module Version: 1.2 */
|
||||
/* Thu Sep 21 04:34:49 2023 */
|
||||
|
||||
/* parameterized module instance */
|
||||
REFB __ (.wb_clk_i( ), .wb_rst_i( ), .wb_cyc_i( ), .wb_stb_i( ),
|
||||
.wb_we_i( ), .wb_adr_i( ), .wb_dat_i( ), .wb_dat_o( ), .wb_ack_o( ),
|
||||
.wbc_ufm_irq( ));
|
||||
297
CPLD/LCMXO2-1200HC-IntOsc/RPLL.edn
Normal file
297
CPLD/LCMXO2-1200HC-IntOsc/RPLL.edn
Normal file
@ -0,0 +1,297 @@
|
||||
(edif RPLL
|
||||
(edifVersion 2 0 0)
|
||||
(edifLevel 0)
|
||||
(keywordMap (keywordLevel 0))
|
||||
(status
|
||||
(written
|
||||
(timestamp 2024 7 14 22 23 22)
|
||||
(program "SCUBA" (version "Diamond (64-bit) 3.11.3.469"))))
|
||||
(comment "C:\lscc\diamond\3.11_x64\ispfpga\bin\nt64\scuba.exe -w -n RPLL -lang verilog -synth synplify -arch xo2c00 -type pll -fin 133.0 -fclkop 61 -fclkop_tol 1.0 -trimp 0 -phasep 0 -trimp_r -phase_cntl STATIC -fb_mode 1 ")
|
||||
(library ORCLIB
|
||||
(edifLevel 0)
|
||||
(technology
|
||||
(numberDefinition))
|
||||
(cell VLO
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port Z
|
||||
(direction OUTPUT)))))
|
||||
(cell EHXPLLJ
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port CLKI
|
||||
(direction INPUT))
|
||||
(port CLKFB
|
||||
(direction INPUT))
|
||||
(port PHASESEL1
|
||||
(direction INPUT))
|
||||
(port PHASESEL0
|
||||
(direction INPUT))
|
||||
(port PHASEDIR
|
||||
(direction INPUT))
|
||||
(port PHASESTEP
|
||||
(direction INPUT))
|
||||
(port LOADREG
|
||||
(direction INPUT))
|
||||
(port STDBY
|
||||
(direction INPUT))
|
||||
(port PLLWAKESYNC
|
||||
(direction INPUT))
|
||||
(port RST
|
||||
(direction INPUT))
|
||||
(port RESETM
|
||||
(direction INPUT))
|
||||
(port RESETC
|
||||
(direction INPUT))
|
||||
(port RESETD
|
||||
(direction INPUT))
|
||||
(port ENCLKOP
|
||||
(direction INPUT))
|
||||
(port ENCLKOS
|
||||
(direction INPUT))
|
||||
(port ENCLKOS2
|
||||
(direction INPUT))
|
||||
(port ENCLKOS3
|
||||
(direction INPUT))
|
||||
(port PLLCLK
|
||||
(direction INPUT))
|
||||
(port PLLRST
|
||||
(direction INPUT))
|
||||
(port PLLSTB
|
||||
(direction INPUT))
|
||||
(port PLLWE
|
||||
(direction INPUT))
|
||||
(port PLLADDR4
|
||||
(direction INPUT))
|
||||
(port PLLADDR3
|
||||
(direction INPUT))
|
||||
(port PLLADDR2
|
||||
(direction INPUT))
|
||||
(port PLLADDR1
|
||||
(direction INPUT))
|
||||
(port PLLADDR0
|
||||
(direction INPUT))
|
||||
(port PLLDATI7
|
||||
(direction INPUT))
|
||||
(port PLLDATI6
|
||||
(direction INPUT))
|
||||
(port PLLDATI5
|
||||
(direction INPUT))
|
||||
(port PLLDATI4
|
||||
(direction INPUT))
|
||||
(port PLLDATI3
|
||||
(direction INPUT))
|
||||
(port PLLDATI2
|
||||
(direction INPUT))
|
||||
(port PLLDATI1
|
||||
(direction INPUT))
|
||||
(port PLLDATI0
|
||||
(direction INPUT))
|
||||
(port CLKOP
|
||||
(direction OUTPUT))
|
||||
(port CLKOS
|
||||
(direction OUTPUT))
|
||||
(port CLKOS2
|
||||
(direction OUTPUT))
|
||||
(port CLKOS3
|
||||
(direction OUTPUT))
|
||||
(port LOCK
|
||||
(direction OUTPUT))
|
||||
(port INTLOCK
|
||||
(direction OUTPUT))
|
||||
(port REFCLK
|
||||
(direction OUTPUT))
|
||||
(port CLKINTFB
|
||||
(direction OUTPUT))
|
||||
(port DPHSRC
|
||||
(direction OUTPUT))
|
||||
(port PLLACK
|
||||
(direction OUTPUT))
|
||||
(port PLLDATO7
|
||||
(direction OUTPUT))
|
||||
(port PLLDATO6
|
||||
(direction OUTPUT))
|
||||
(port PLLDATO5
|
||||
(direction OUTPUT))
|
||||
(port PLLDATO4
|
||||
(direction OUTPUT))
|
||||
(port PLLDATO3
|
||||
(direction OUTPUT))
|
||||
(port PLLDATO2
|
||||
(direction OUTPUT))
|
||||
(port PLLDATO1
|
||||
(direction OUTPUT))
|
||||
(port PLLDATO0
|
||||
(direction OUTPUT)))))
|
||||
(cell RPLL
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port CLKI
|
||||
(direction INPUT))
|
||||
(port CLKOP
|
||||
(direction OUTPUT)))
|
||||
(property NGD_DRC_MASK (integer 1))
|
||||
(contents
|
||||
(instance scuba_vlo_inst
|
||||
(viewRef view1
|
||||
(cellRef VLO)))
|
||||
(instance PLLInst_0
|
||||
(viewRef view1
|
||||
(cellRef EHXPLLJ))
|
||||
(property DDRST_ENA
|
||||
(string "DISABLED"))
|
||||
(property DCRST_ENA
|
||||
(string "DISABLED"))
|
||||
(property MRST_ENA
|
||||
(string "DISABLED"))
|
||||
(property PLLRST_ENA
|
||||
(string "DISABLED"))
|
||||
(property INTFB_WAKE
|
||||
(string "DISABLED"))
|
||||
(property STDBY_ENABLE
|
||||
(string "DISABLED"))
|
||||
(property DPHASE_SOURCE
|
||||
(string "DISABLED"))
|
||||
(property PLL_USE_WB
|
||||
(string "DISABLED"))
|
||||
(property CLKOS3_FPHASE
|
||||
(string "0"))
|
||||
(property CLKOS3_CPHASE
|
||||
(string "0"))
|
||||
(property CLKOS2_FPHASE
|
||||
(string "0"))
|
||||
(property CLKOS2_CPHASE
|
||||
(string "0"))
|
||||
(property CLKOS_FPHASE
|
||||
(string "0"))
|
||||
(property CLKOS_CPHASE
|
||||
(string "0"))
|
||||
(property CLKOP_FPHASE
|
||||
(string "0"))
|
||||
(property CLKOP_CPHASE
|
||||
(string "7"))
|
||||
(property PLL_LOCK_MODE
|
||||
(string "0"))
|
||||
(property CLKOS_TRIM_DELAY
|
||||
(string "0"))
|
||||
(property CLKOS_TRIM_POL
|
||||
(string "FALLING"))
|
||||
(property CLKOP_TRIM_DELAY
|
||||
(string "0"))
|
||||
(property CLKOP_TRIM_POL
|
||||
(string "RISING"))
|
||||
(property FRACN_DIV
|
||||
(string "0"))
|
||||
(property FRACN_ENABLE
|
||||
(string "DISABLED"))
|
||||
(property OUTDIVIDER_MUXD2
|
||||
(string "DIVD"))
|
||||
(property PREDIVIDER_MUXD1
|
||||
(string "0"))
|
||||
(property VCO_BYPASS_D0
|
||||
(string "DISABLED"))
|
||||
(property CLKOS3_ENABLE
|
||||
(string "DISABLED"))
|
||||
(property OUTDIVIDER_MUXC2
|
||||
(string "DIVC"))
|
||||
(property PREDIVIDER_MUXC1
|
||||
(string "0"))
|
||||
(property VCO_BYPASS_C0
|
||||
(string "DISABLED"))
|
||||
(property CLKOS2_ENABLE
|
||||
(string "DISABLED"))
|
||||
(property OUTDIVIDER_MUXB2
|
||||
(string "DIVB"))
|
||||
(property PREDIVIDER_MUXB1
|
||||
(string "0"))
|
||||
(property VCO_BYPASS_B0
|
||||
(string "DISABLED"))
|
||||
(property CLKOS_ENABLE
|
||||
(string "DISABLED"))
|
||||
(property FREQUENCY_PIN_CLKOP
|
||||
(string "61.384615"))
|
||||
(property OUTDIVIDER_MUXA2
|
||||
(string "DIVA"))
|
||||
(property PREDIVIDER_MUXA1
|
||||
(string "0"))
|
||||
(property VCO_BYPASS_A0
|
||||
(string "DISABLED"))
|
||||
(property CLKOP_ENABLE
|
||||
(string "ENABLED"))
|
||||
(property FREQUENCY_PIN_CLKI
|
||||
(string "133.000000"))
|
||||
(property ICP_CURRENT
|
||||
(string "7"))
|
||||
(property LPF_RESISTOR
|
||||
(string "8"))
|
||||
(property CLKOS3_DIV
|
||||
(string "1"))
|
||||
(property CLKOS2_DIV
|
||||
(string "1"))
|
||||
(property CLKOS_DIV
|
||||
(string "1"))
|
||||
(property CLKOP_DIV
|
||||
(string "8"))
|
||||
(property CLKFB_DIV
|
||||
(string "6"))
|
||||
(property CLKI_DIV
|
||||
(string "13"))
|
||||
(property FEEDBK_PATH
|
||||
(string "CLKOP")))
|
||||
(net LOCK
|
||||
(joined
|
||||
(portRef LOCK (instanceRef PLLInst_0))))
|
||||
(net scuba_vlo
|
||||
(joined
|
||||
(portRef Z (instanceRef scuba_vlo_inst))
|
||||
(portRef PLLADDR4 (instanceRef PLLInst_0))
|
||||
(portRef PLLADDR3 (instanceRef PLLInst_0))
|
||||
(portRef PLLADDR2 (instanceRef PLLInst_0))
|
||||
(portRef PLLADDR1 (instanceRef PLLInst_0))
|
||||
(portRef PLLADDR0 (instanceRef PLLInst_0))
|
||||
(portRef PLLDATI7 (instanceRef PLLInst_0))
|
||||
(portRef PLLDATI6 (instanceRef PLLInst_0))
|
||||
(portRef PLLDATI5 (instanceRef PLLInst_0))
|
||||
(portRef PLLDATI4 (instanceRef PLLInst_0))
|
||||
(portRef PLLDATI3 (instanceRef PLLInst_0))
|
||||
(portRef PLLDATI2 (instanceRef PLLInst_0))
|
||||
(portRef PLLDATI1 (instanceRef PLLInst_0))
|
||||
(portRef PLLDATI0 (instanceRef PLLInst_0))
|
||||
(portRef PLLWE (instanceRef PLLInst_0))
|
||||
(portRef PLLSTB (instanceRef PLLInst_0))
|
||||
(portRef PLLRST (instanceRef PLLInst_0))
|
||||
(portRef PLLCLK (instanceRef PLLInst_0))
|
||||
(portRef ENCLKOS3 (instanceRef PLLInst_0))
|
||||
(portRef ENCLKOS2 (instanceRef PLLInst_0))
|
||||
(portRef ENCLKOS (instanceRef PLLInst_0))
|
||||
(portRef ENCLKOP (instanceRef PLLInst_0))
|
||||
(portRef RESETD (instanceRef PLLInst_0))
|
||||
(portRef RESETC (instanceRef PLLInst_0))
|
||||
(portRef RESETM (instanceRef PLLInst_0))
|
||||
(portRef RST (instanceRef PLLInst_0))
|
||||
(portRef PLLWAKESYNC (instanceRef PLLInst_0))
|
||||
(portRef STDBY (instanceRef PLLInst_0))
|
||||
(portRef LOADREG (instanceRef PLLInst_0))
|
||||
(portRef PHASESTEP (instanceRef PLLInst_0))
|
||||
(portRef PHASEDIR (instanceRef PLLInst_0))
|
||||
(portRef PHASESEL1 (instanceRef PLLInst_0))
|
||||
(portRef PHASESEL0 (instanceRef PLLInst_0))))
|
||||
(net CLKOP
|
||||
(joined
|
||||
(portRef CLKOP)
|
||||
(portRef CLKFB (instanceRef PLLInst_0))
|
||||
(portRef CLKOP (instanceRef PLLInst_0))))
|
||||
(net CLKI
|
||||
(joined
|
||||
(portRef CLKI)
|
||||
(portRef CLKI (instanceRef PLLInst_0))))))))
|
||||
(design RPLL
|
||||
(cellRef RPLL
|
||||
(libraryRef ORCLIB)))
|
||||
)
|
||||
8
CPLD/LCMXO2-1200HC-IntOsc/RPLL.ipx
Normal file
8
CPLD/LCMXO2-1200HC-IntOsc/RPLL.ipx
Normal file
@ -0,0 +1,8 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<DiamondModule name="RPLL" module="RPLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2024 07 14 22:23:23.515" version="5.8" type="Module" synthesis="synplify" source_format="Verilog HDL">
|
||||
<Package>
|
||||
<File name="RPLL.lpc" type="lpc" modified="2024 07 14 22:23:22.367"/>
|
||||
<File name="RPLL.v" type="top_level_verilog" modified="2024 07 14 22:23:22.464"/>
|
||||
<File name="RPLL_tmpl.v" type="template_verilog" modified="2024 07 14 22:23:22.465"/>
|
||||
</Package>
|
||||
</DiamondModule>
|
||||
87
CPLD/LCMXO2-1200HC-IntOsc/RPLL.lpc
Normal file
87
CPLD/LCMXO2-1200HC-IntOsc/RPLL.lpc
Normal file
@ -0,0 +1,87 @@
|
||||
[Device]
|
||||
Family=machxo2
|
||||
PartType=LCMXO2-1200HC
|
||||
PartName=LCMXO2-1200HC-4TG100C
|
||||
SpeedGrade=4
|
||||
Package=TQFP100
|
||||
OperatingCondition=COM
|
||||
Status=S
|
||||
|
||||
[IP]
|
||||
VendorName=Lattice Semiconductor Corporation
|
||||
CoreType=LPM
|
||||
CoreStatus=Demo
|
||||
CoreName=PLL
|
||||
CoreRevision=5.8
|
||||
ModuleName=RPLL
|
||||
SourceFormat=Verilog HDL
|
||||
ParameterFileVersion=1.0
|
||||
Date=07/14/2024
|
||||
Time=22:23:22
|
||||
|
||||
[Parameters]
|
||||
Verilog=1
|
||||
VHDL=0
|
||||
EDIF=1
|
||||
Destination=Synplicity
|
||||
Expression=None
|
||||
Order=None
|
||||
IO=0
|
||||
mode=Frequency
|
||||
CLKI=133.0
|
||||
CLKI_DIV=13
|
||||
BW=0.955
|
||||
VCO=491.077
|
||||
fb_mode=CLKOP
|
||||
CLKFB_DIV=6
|
||||
FRACN_ENABLE=0
|
||||
FRACN_DIV=0
|
||||
DynamicPhase=STATIC
|
||||
ClkEnable=0
|
||||
Standby=0
|
||||
Enable_sel=0
|
||||
PLLRst=0
|
||||
PLLMRst=0
|
||||
ClkOS2Rst=0
|
||||
ClkOS3Rst=0
|
||||
LockSig=0
|
||||
LockStk=0
|
||||
WBProt=0
|
||||
OPBypass=0
|
||||
OPUseDiv=0
|
||||
CLKOP_DIV=8
|
||||
FREQ_PIN_CLKOP=61
|
||||
OP_Tol=1.0
|
||||
CLKOP_AFREQ=61.384615
|
||||
CLKOP_PHASEADJ=0
|
||||
CLKOP_TRIM_POL=Rising
|
||||
CLKOP_TRIM_DELAY=0
|
||||
EnCLKOS=0
|
||||
OSBypass=0
|
||||
OSUseDiv=0
|
||||
CLKOS_DIV=1
|
||||
FREQ_PIN_CLKOS=100
|
||||
OS_Tol=0.0
|
||||
CLKOS_AFREQ=
|
||||
CLKOS_PHASEADJ=0
|
||||
CLKOS_TRIM_POL=Rising
|
||||
CLKOS_TRIM_DELAY=0
|
||||
EnCLKOS2=0
|
||||
OS2Bypass=0
|
||||
OS2UseDiv=0
|
||||
CLKOS2_DIV=1
|
||||
FREQ_PIN_CLKOS2=100
|
||||
OS2_Tol=0.0
|
||||
CLKOS2_AFREQ=
|
||||
CLKOS2_PHASEADJ=0
|
||||
EnCLKOS3=0
|
||||
OS3Bypass=0
|
||||
OS3UseDiv=0
|
||||
CLKOS3_DIV=1
|
||||
FREQ_PIN_CLKOS3=100
|
||||
OS3_Tol=0.0
|
||||
CLKOS3_AFREQ=
|
||||
CLKOS3_PHASEADJ=0
|
||||
|
||||
[Command]
|
||||
cmd_line= -w -n RPLL -lang verilog -synth synplify -arch xo2c00 -type pll -fin 133.0 -fclkop 61 -fclkop_tol 1.0 -trimp 0 -phasep 0 -trimp_r -phase_cntl STATIC -fb_mode 1
|
||||
2
CPLD/LCMXO2-1200HC-IntOsc/RPLL.naf
Normal file
2
CPLD/LCMXO2-1200HC-IntOsc/RPLL.naf
Normal file
@ -0,0 +1,2 @@
|
||||
CLKI i
|
||||
CLKOP o
|
||||
1
CPLD/LCMXO2-1200HC-IntOsc/RPLL.sort
Normal file
1
CPLD/LCMXO2-1200HC-IntOsc/RPLL.sort
Normal file
@ -0,0 +1 @@
|
||||
RPLL.v
|
||||
26
CPLD/LCMXO2-1200HC-IntOsc/RPLL.srp
Normal file
26
CPLD/LCMXO2-1200HC-IntOsc/RPLL.srp
Normal file
@ -0,0 +1,26 @@
|
||||
SCUBA, Version Diamond (64-bit) 3.11.3.469
|
||||
Sun Jul 14 22:23:22 2024
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
Issued command : C:\lscc\diamond\3.11_x64\ispfpga\bin\nt64\scuba.exe -w -n RPLL -lang verilog -synth synplify -arch xo2c00 -type pll -fin 133.0 -fclkop 61 -fclkop_tol 1.0 -trimp 0 -phasep 0 -trimp_r -phase_cntl STATIC -fb_mode 1
|
||||
Circuit name : RPLL
|
||||
Module type : pll
|
||||
Module Version : 5.7
|
||||
Ports :
|
||||
Inputs : CLKI
|
||||
Outputs : CLKOP
|
||||
I/O buffer : not inserted
|
||||
EDIF output : RPLL.edn
|
||||
Verilog output : RPLL.v
|
||||
Verilog template : RPLL_tmpl.v
|
||||
Verilog purpose : for synthesis and simulation
|
||||
Bus notation : big endian
|
||||
Report output : RPLL.srp
|
||||
Element Usage :
|
||||
EHXPLLJ : 1
|
||||
Estimated Resource Usage:
|
||||
BIN
CPLD/LCMXO2-1200HC-IntOsc/RPLL.sym
Normal file
BIN
CPLD/LCMXO2-1200HC-IntOsc/RPLL.sym
Normal file
Binary file not shown.
93
CPLD/LCMXO2-1200HC-IntOsc/RPLL.v
Normal file
93
CPLD/LCMXO2-1200HC-IntOsc/RPLL.v
Normal file
@ -0,0 +1,93 @@
|
||||
/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.11.3.469 */
|
||||
/* Module Version: 5.7 */
|
||||
/* C:\lscc\diamond\3.11_x64\ispfpga\bin\nt64\scuba.exe -w -n RPLL -lang verilog -synth synplify -arch xo2c00 -type pll -fin 133.0 -fclkop 61 -fclkop_tol 1.0 -trimp 0 -phasep 0 -trimp_r -phase_cntl STATIC -fb_mode 1 */
|
||||
/* Sun Jul 14 22:23:22 2024 */
|
||||
|
||||
|
||||
`timescale 1 ns / 1 ps
|
||||
module RPLL (CLKI, CLKOP)/* synthesis NGD_DRC_MASK=1 */;
|
||||
input wire CLKI;
|
||||
output wire CLKOP;
|
||||
|
||||
wire LOCK;
|
||||
wire CLKOP_t;
|
||||
wire scuba_vlo;
|
||||
|
||||
VLO scuba_vlo_inst (.Z(scuba_vlo));
|
||||
|
||||
defparam PLLInst_0.DDRST_ENA = "DISABLED" ;
|
||||
defparam PLLInst_0.DCRST_ENA = "DISABLED" ;
|
||||
defparam PLLInst_0.MRST_ENA = "DISABLED" ;
|
||||
defparam PLLInst_0.PLLRST_ENA = "DISABLED" ;
|
||||
defparam PLLInst_0.INTFB_WAKE = "DISABLED" ;
|
||||
defparam PLLInst_0.STDBY_ENABLE = "DISABLED" ;
|
||||
defparam PLLInst_0.DPHASE_SOURCE = "DISABLED" ;
|
||||
defparam PLLInst_0.PLL_USE_WB = "DISABLED" ;
|
||||
defparam PLLInst_0.CLKOS3_FPHASE = 0 ;
|
||||
defparam PLLInst_0.CLKOS3_CPHASE = 0 ;
|
||||
defparam PLLInst_0.CLKOS2_FPHASE = 0 ;
|
||||
defparam PLLInst_0.CLKOS2_CPHASE = 0 ;
|
||||
defparam PLLInst_0.CLKOS_FPHASE = 0 ;
|
||||
defparam PLLInst_0.CLKOS_CPHASE = 0 ;
|
||||
defparam PLLInst_0.CLKOP_FPHASE = 0 ;
|
||||
defparam PLLInst_0.CLKOP_CPHASE = 7 ;
|
||||
defparam PLLInst_0.PLL_LOCK_MODE = 0 ;
|
||||
defparam PLLInst_0.CLKOS_TRIM_DELAY = 0 ;
|
||||
defparam PLLInst_0.CLKOS_TRIM_POL = "FALLING" ;
|
||||
defparam PLLInst_0.CLKOP_TRIM_DELAY = 0 ;
|
||||
defparam PLLInst_0.CLKOP_TRIM_POL = "RISING" ;
|
||||
defparam PLLInst_0.FRACN_DIV = 0 ;
|
||||
defparam PLLInst_0.FRACN_ENABLE = "DISABLED" ;
|
||||
defparam PLLInst_0.OUTDIVIDER_MUXD2 = "DIVD" ;
|
||||
defparam PLLInst_0.PREDIVIDER_MUXD1 = 0 ;
|
||||
defparam PLLInst_0.VCO_BYPASS_D0 = "DISABLED" ;
|
||||
defparam PLLInst_0.CLKOS3_ENABLE = "DISABLED" ;
|
||||
defparam PLLInst_0.OUTDIVIDER_MUXC2 = "DIVC" ;
|
||||
defparam PLLInst_0.PREDIVIDER_MUXC1 = 0 ;
|
||||
defparam PLLInst_0.VCO_BYPASS_C0 = "DISABLED" ;
|
||||
defparam PLLInst_0.CLKOS2_ENABLE = "DISABLED" ;
|
||||
defparam PLLInst_0.OUTDIVIDER_MUXB2 = "DIVB" ;
|
||||
defparam PLLInst_0.PREDIVIDER_MUXB1 = 0 ;
|
||||
defparam PLLInst_0.VCO_BYPASS_B0 = "DISABLED" ;
|
||||
defparam PLLInst_0.CLKOS_ENABLE = "DISABLED" ;
|
||||
defparam PLLInst_0.OUTDIVIDER_MUXA2 = "DIVA" ;
|
||||
defparam PLLInst_0.PREDIVIDER_MUXA1 = 0 ;
|
||||
defparam PLLInst_0.VCO_BYPASS_A0 = "DISABLED" ;
|
||||
defparam PLLInst_0.CLKOP_ENABLE = "ENABLED" ;
|
||||
defparam PLLInst_0.CLKOS3_DIV = 1 ;
|
||||
defparam PLLInst_0.CLKOS2_DIV = 1 ;
|
||||
defparam PLLInst_0.CLKOS_DIV = 1 ;
|
||||
defparam PLLInst_0.CLKOP_DIV = 8 ;
|
||||
defparam PLLInst_0.CLKFB_DIV = 6 ;
|
||||
defparam PLLInst_0.CLKI_DIV = 13 ;
|
||||
defparam PLLInst_0.FEEDBK_PATH = "CLKOP" ;
|
||||
EHXPLLJ PLLInst_0 (.CLKI(CLKI), .CLKFB(CLKOP_t), .PHASESEL1(scuba_vlo),
|
||||
.PHASESEL0(scuba_vlo), .PHASEDIR(scuba_vlo), .PHASESTEP(scuba_vlo),
|
||||
.LOADREG(scuba_vlo), .STDBY(scuba_vlo), .PLLWAKESYNC(scuba_vlo),
|
||||
.RST(scuba_vlo), .RESETM(scuba_vlo), .RESETC(scuba_vlo), .RESETD(scuba_vlo),
|
||||
.ENCLKOP(scuba_vlo), .ENCLKOS(scuba_vlo), .ENCLKOS2(scuba_vlo),
|
||||
.ENCLKOS3(scuba_vlo), .PLLCLK(scuba_vlo), .PLLRST(scuba_vlo), .PLLSTB(scuba_vlo),
|
||||
.PLLWE(scuba_vlo), .PLLADDR4(scuba_vlo), .PLLADDR3(scuba_vlo), .PLLADDR2(scuba_vlo),
|
||||
.PLLADDR1(scuba_vlo), .PLLADDR0(scuba_vlo), .PLLDATI7(scuba_vlo),
|
||||
.PLLDATI6(scuba_vlo), .PLLDATI5(scuba_vlo), .PLLDATI4(scuba_vlo),
|
||||
.PLLDATI3(scuba_vlo), .PLLDATI2(scuba_vlo), .PLLDATI1(scuba_vlo),
|
||||
.PLLDATI0(scuba_vlo), .CLKOP(CLKOP_t), .CLKOS(), .CLKOS2(), .CLKOS3(),
|
||||
.LOCK(LOCK), .INTLOCK(), .REFCLK(), .CLKINTFB(), .DPHSRC(), .PLLACK(),
|
||||
.PLLDATO7(), .PLLDATO6(), .PLLDATO5(), .PLLDATO4(), .PLLDATO3(),
|
||||
.PLLDATO2(), .PLLDATO1(), .PLLDATO0())
|
||||
/* synthesis FREQUENCY_PIN_CLKOP="61.384615" */
|
||||
/* synthesis FREQUENCY_PIN_CLKI="133.000000" */
|
||||
/* synthesis ICP_CURRENT="7" */
|
||||
/* synthesis LPF_RESISTOR="8" */;
|
||||
|
||||
assign CLKOP = CLKOP_t;
|
||||
|
||||
|
||||
// exemplar begin
|
||||
// exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKOP 61.384615
|
||||
// exemplar attribute PLLInst_0 FREQUENCY_PIN_CLKI 133.000000
|
||||
// exemplar attribute PLLInst_0 ICP_CURRENT 7
|
||||
// exemplar attribute PLLInst_0 LPF_RESISTOR 8
|
||||
// exemplar end
|
||||
|
||||
endmodule
|
||||
44
CPLD/LCMXO2-1200HC-IntOsc/RPLL_generate.log
Normal file
44
CPLD/LCMXO2-1200HC-IntOsc/RPLL_generate.log
Normal file
@ -0,0 +1,44 @@
|
||||
Starting process: Module
|
||||
|
||||
Starting process:
|
||||
|
||||
SCUBA, Version Diamond (64-bit) 3.11.3.469
|
||||
Sun Jul 14 22:23:22 2024
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
BEGIN SCUBA Module Synthesis
|
||||
|
||||
Issued command : C:\lscc\diamond\3.11_x64\ispfpga\bin\nt64\scuba.exe -w -n RPLL -lang verilog -synth synplify -arch xo2c00 -type pll -fin 133.0 -fclkop 61 -fclkop_tol 1.0 -trimp 0 -phasep 0 -trimp_r -phase_cntl STATIC -fb_mode 1
|
||||
Circuit name : RPLL
|
||||
Module type : pll
|
||||
Module Version : 5.7
|
||||
Ports :
|
||||
Inputs : CLKI
|
||||
Outputs : CLKOP
|
||||
I/O buffer : not inserted
|
||||
EDIF output : RPLL.edn
|
||||
Verilog output : RPLL.v
|
||||
Verilog template : RPLL_tmpl.v
|
||||
Verilog purpose : for synthesis and simulation
|
||||
Bus notation : big endian
|
||||
Report output : RPLL.srp
|
||||
Estimated Resource Usage:
|
||||
|
||||
END SCUBA Module Synthesis
|
||||
|
||||
File: RPLL.lpc created.
|
||||
|
||||
|
||||
End process: completed successfully.
|
||||
|
||||
|
||||
Total Warnings: 0
|
||||
|
||||
Total Errors: 0
|
||||
|
||||
|
||||
6
CPLD/LCMXO2-1200HC-IntOsc/RPLL_tmpl.v
Normal file
6
CPLD/LCMXO2-1200HC-IntOsc/RPLL_tmpl.v
Normal file
@ -0,0 +1,6 @@
|
||||
/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.11.3.469 */
|
||||
/* Module Version: 5.7 */
|
||||
/* Sun Jul 14 22:23:22 2024 */
|
||||
|
||||
/* parameterized module instance */
|
||||
RPLL __ (.CLKI( ), .CLKOP( ));
|
||||
2574
CPLD/LCMXO2-1200HC-IntOsc/_math_real.vhd
Normal file
2574
CPLD/LCMXO2-1200HC-IntOsc/_math_real.vhd
Normal file
File diff suppressed because it is too large
Load Diff
100
CPLD/LCMXO2-1200HC-IntOsc/generate_core.tcl
Normal file
100
CPLD/LCMXO2-1200HC-IntOsc/generate_core.tcl
Normal file
@ -0,0 +1,100 @@
|
||||
#!/usr/local/bin/wish
|
||||
|
||||
proc GetPlatform {} {
|
||||
global tcl_platform
|
||||
|
||||
set cpu $tcl_platform(machine)
|
||||
|
||||
switch $cpu {
|
||||
intel -
|
||||
i*86* {
|
||||
set cpu ix86
|
||||
}
|
||||
x86_64 {
|
||||
if {$tcl_platform(wordSize) == 4} {
|
||||
set cpu ix86
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
switch $tcl_platform(platform) {
|
||||
windows {
|
||||
if {$cpu == "amd64"} {
|
||||
# Do not check wordSize, win32-x64 is an IL32P64 platform.
|
||||
set cpu x86_64
|
||||
}
|
||||
if {$cpu == "x86_64"} {
|
||||
return "nt64"
|
||||
} else {
|
||||
return "nt"
|
||||
}
|
||||
}
|
||||
unix {
|
||||
if {$tcl_platform(os) == "Linux"} {
|
||||
if {$cpu == "x86_64"} {
|
||||
return "lin64"
|
||||
} else {
|
||||
return "lin"
|
||||
}
|
||||
} else {
|
||||
return "sol"
|
||||
}
|
||||
}
|
||||
}
|
||||
return "nt"
|
||||
}
|
||||
|
||||
proc GetCmdLine {lpcfile} {
|
||||
global Para
|
||||
|
||||
if [catch {open $lpcfile r} fileid] {
|
||||
puts "Cannot open $para_file file!"
|
||||
exit -1
|
||||
}
|
||||
|
||||
seek $fileid 0 start
|
||||
set default_match 0
|
||||
while {[gets $fileid line] >= 0} {
|
||||
if {[string first "\[Command\]" $line] == 0} {
|
||||
set default_match 1
|
||||
continue
|
||||
}
|
||||
if {[string first "\[" $line] == 0} {
|
||||
set default_match 0
|
||||
}
|
||||
if {$default_match == 1} {
|
||||
if [regexp {([^=]*)=(.*)} $line match parameter value] {
|
||||
if [regexp {([ |\t]*;)} $parameter match] {continue}
|
||||
if [regexp {(.*)[ |\t]*;} $value match temp] {
|
||||
set Para($parameter) $temp
|
||||
} else {
|
||||
set Para($parameter) $value
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
set default_match 0
|
||||
close $fileid
|
||||
|
||||
return $Para(cmd_line)
|
||||
}
|
||||
|
||||
set platformpath [GetPlatform]
|
||||
set Para(sbp_path) [file dirname [info script]]
|
||||
set Para(install_dir) $env(TOOLRTF)
|
||||
set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
|
||||
|
||||
set scuba "$Para(FPGAPath)/scuba"
|
||||
set modulename "RPLL"
|
||||
set lang "verilog"
|
||||
set lpcfile "$Para(sbp_path)/$modulename.lpc"
|
||||
set arch "xo2c00"
|
||||
set cmd_line [GetCmdLine $lpcfile]
|
||||
set fdcfile "$Para(sbp_path)/$modulename.fdc"
|
||||
if {[file exists $fdcfile] == 0} {
|
||||
append scuba " " $cmd_line
|
||||
} else {
|
||||
append scuba " " $cmd_line " " -fdc " " \"$fdcfile\"
|
||||
}
|
||||
set Para(result) [catch {eval exec "$scuba"} msg]
|
||||
#puts $msg
|
||||
115
CPLD/LCMXO2-1200HC-IntOsc/generate_ngd.tcl
Normal file
115
CPLD/LCMXO2-1200HC-IntOsc/generate_ngd.tcl
Normal file
@ -0,0 +1,115 @@
|
||||
#!/usr/local/bin/wish
|
||||
|
||||
proc GetPlatform {} {
|
||||
global tcl_platform
|
||||
|
||||
set cpu $tcl_platform(machine)
|
||||
|
||||
switch $cpu {
|
||||
intel -
|
||||
i*86* {
|
||||
set cpu ix86
|
||||
}
|
||||
x86_64 {
|
||||
if {$tcl_platform(wordSize) == 4} {
|
||||
set cpu ix86
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
switch $tcl_platform(platform) {
|
||||
windows {
|
||||
if {$cpu == "amd64"} {
|
||||
# Do not check wordSize, win32-x64 is an IL32P64 platform.
|
||||
set cpu x86_64
|
||||
}
|
||||
if {$cpu == "x86_64"} {
|
||||
return "nt64"
|
||||
} else {
|
||||
return "nt"
|
||||
}
|
||||
}
|
||||
unix {
|
||||
if {$tcl_platform(os) == "Linux"} {
|
||||
if {$cpu == "x86_64"} {
|
||||
return "lin64"
|
||||
} else {
|
||||
return "lin"
|
||||
}
|
||||
} else {
|
||||
return "sol"
|
||||
}
|
||||
}
|
||||
}
|
||||
return "nt"
|
||||
}
|
||||
|
||||
set platformpath [GetPlatform]
|
||||
set Para(sbp_path) [file dirname [info script]]
|
||||
set Para(install_dir) $env(TOOLRTF)
|
||||
set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
|
||||
set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]"
|
||||
|
||||
set Para(ModuleName) "RPLL"
|
||||
set Para(Module) "PLL"
|
||||
set Para(libname) machxo2
|
||||
set Para(arch_name) xo2c00
|
||||
set Para(PartType) "LCMXO2-1200HC"
|
||||
|
||||
set Para(tech_syn) machxo2
|
||||
set Para(tech_cae) machxo2
|
||||
set Para(Package) "TQFP100"
|
||||
set Para(SpeedGrade) "4"
|
||||
set Para(FMax) "100"
|
||||
set fdcfile "$Para(sbp_path)/$Para(ModuleName).fdc"
|
||||
|
||||
#create response file(*.cmd) for Synpwrap
|
||||
proc CreateCmdFile {} {
|
||||
global Para
|
||||
|
||||
file mkdir "$Para(sbp_path)/syn_results"
|
||||
if [catch {open $Para(ModuleName).cmd w} rspFile] {
|
||||
puts "Cannot create response file $Para(ModuleName).cmd."
|
||||
exit -1
|
||||
} else {
|
||||
puts $rspFile "PROJECT: $Para(ModuleName)
|
||||
working_path: \"$Para(sbp_path)/syn_results\"
|
||||
module: $Para(ModuleName)
|
||||
verilog_file_list: \"$Para(install_dir)/cae_library/synthesis/verilog/$Para(tech_cae).v\" \"$Para(install_dir)/cae_library/synthesis/verilog/pmi_def.v\" \"$Para(sbp_path)/$Para(ModuleName).v\"
|
||||
vlog_std_v2001: true
|
||||
constraint_file_name: \"$Para(sbp_path)/$Para(ModuleName).fdc\"
|
||||
suffix_name: edn
|
||||
output_file_name: $Para(ModuleName)
|
||||
write_prf: true
|
||||
disable_io_insertion: true
|
||||
force_gsr: false
|
||||
frequency: $Para(FMax)
|
||||
fanout_limit: 50
|
||||
retiming: false
|
||||
pipe: false
|
||||
part: $Para(PartType)
|
||||
speed_grade: $Para(SpeedGrade)
|
||||
"
|
||||
close $rspFile
|
||||
}
|
||||
}
|
||||
|
||||
#synpwrap
|
||||
CreateCmdFile
|
||||
set synpwrap "$Para(bin_dir)/synpwrap"
|
||||
if {[file exists $fdcfile] == 0} {
|
||||
set Para(result) [catch {eval exec $synpwrap -rem -e $Para(ModuleName) -target $Para(tech_syn)} msg]
|
||||
} else {
|
||||
set Para(result) [catch {eval exec $synpwrap -rem -e $Para(ModuleName) -target $Para(tech_syn) -fdc $fdcfile} msg]
|
||||
}
|
||||
#puts $msg
|
||||
|
||||
#edif2ngd
|
||||
set edif2ngd "$Para(FPGAPath)/edif2ngd"
|
||||
set Para(result) [catch {eval exec $edif2ngd -l $Para(libname) -d $Para(PartType) -nopropwarn \"syn_results/$Para(ModuleName).edn\" $Para(ModuleName).ngo} msg]
|
||||
#puts $msg
|
||||
|
||||
#ngdbuild
|
||||
set ngdbuild "$Para(FPGAPath)/ngdbuild"
|
||||
set Para(result) [catch {eval exec $ngdbuild -addiobuf -dt -a $Para(arch_name) $Para(ModuleName).ngo $Para(ModuleName).ngd} msg]
|
||||
#puts $msg
|
||||
@ -0,0 +1,71 @@
|
||||
NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
|
||||
NOTE All Rights Reserved *
|
||||
NOTE DATE CREATED: Sun Jul 14 22:31:30 2024 *
|
||||
NOTE DESIGN NAME: RAM2GS *
|
||||
NOTE DEVICE NAME: LCMXO2-1200HC-4TQFP100 *
|
||||
NOTE PIN ASSIGNMENTS *
|
||||
NOTE PINS RD[0] : 36 : inout *
|
||||
NOTE PINS Dout[0] : 76 : out *
|
||||
NOTE PINS PHI2 : 8 : in *
|
||||
NOTE PINS RDQML : 48 : out *
|
||||
NOTE PINS RDQMH : 51 : out *
|
||||
NOTE PINS nRCAS : 52 : out *
|
||||
NOTE PINS nRRAS : 54 : out *
|
||||
NOTE PINS nRWE : 49 : out *
|
||||
NOTE PINS RCKE : 53 : out *
|
||||
NOTE PINS RCLKout : 60 : out *
|
||||
NOTE PINS nRCS : 57 : out *
|
||||
NOTE PINS RD[7] : 43 : inout *
|
||||
NOTE PINS RD[6] : 42 : inout *
|
||||
NOTE PINS RD[5] : 41 : inout *
|
||||
NOTE PINS RD[4] : 40 : inout *
|
||||
NOTE PINS RD[3] : 39 : inout *
|
||||
NOTE PINS RD[2] : 38 : inout *
|
||||
NOTE PINS RD[1] : 37 : inout *
|
||||
NOTE PINS RA[11] : 59 : out *
|
||||
NOTE PINS RA[10] : 64 : out *
|
||||
NOTE PINS RA[9] : 62 : out *
|
||||
NOTE PINS RA[8] : 65 : out *
|
||||
NOTE PINS RA[7] : 75 : out *
|
||||
NOTE PINS RA[6] : 68 : out *
|
||||
NOTE PINS RA[5] : 70 : out *
|
||||
NOTE PINS RA[4] : 74 : out *
|
||||
NOTE PINS RA[3] : 71 : out *
|
||||
NOTE PINS RA[2] : 69 : out *
|
||||
NOTE PINS RA[1] : 67 : out *
|
||||
NOTE PINS RA[0] : 66 : out *
|
||||
NOTE PINS RBA[1] : 47 : out *
|
||||
NOTE PINS RBA[0] : 58 : out *
|
||||
NOTE PINS LED : 34 : out *
|
||||
NOTE PINS nFWE : 15 : in *
|
||||
NOTE PINS nCRAS : 17 : in *
|
||||
NOTE PINS nCCAS : 9 : in *
|
||||
NOTE PINS Dout[7] : 82 : out *
|
||||
NOTE PINS Dout[6] : 78 : out *
|
||||
NOTE PINS Dout[5] : 84 : out *
|
||||
NOTE PINS Dout[4] : 83 : out *
|
||||
NOTE PINS Dout[3] : 85 : out *
|
||||
NOTE PINS Dout[2] : 87 : out *
|
||||
NOTE PINS Dout[1] : 86 : out *
|
||||
NOTE PINS Din[7] : 1 : in *
|
||||
NOTE PINS Din[6] : 2 : in *
|
||||
NOTE PINS Din[5] : 98 : in *
|
||||
NOTE PINS Din[4] : 99 : in *
|
||||
NOTE PINS Din[3] : 97 : in *
|
||||
NOTE PINS Din[2] : 88 : in *
|
||||
NOTE PINS Din[1] : 96 : in *
|
||||
NOTE PINS Din[0] : 3 : in *
|
||||
NOTE PINS CROW[1] : 16 : in *
|
||||
NOTE PINS CROW[0] : 10 : in *
|
||||
NOTE PINS MAin[9] : 32 : in *
|
||||
NOTE PINS MAin[8] : 25 : in *
|
||||
NOTE PINS MAin[7] : 18 : in *
|
||||
NOTE PINS MAin[6] : 24 : in *
|
||||
NOTE PINS MAin[5] : 19 : in *
|
||||
NOTE PINS MAin[4] : 20 : in *
|
||||
NOTE PINS MAin[3] : 21 : in *
|
||||
NOTE PINS MAin[2] : 13 : in *
|
||||
NOTE PINS MAin[1] : 12 : in *
|
||||
NOTE PINS MAin[0] : 14 : in *
|
||||
NOTE CONFIGURATION MODE: NONE *
|
||||
NOTE COMPRESSION: on *
|
||||
@ -0,0 +1,58 @@
|
||||
----------------------------------------------------------------------
|
||||
Report for cell RAM2GS.verilog
|
||||
|
||||
Register bits: 106 of 1280 (8%)
|
||||
PIC Latch: 0
|
||||
I/O cells: 63
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
BB 8 100.0
|
||||
CCU2D 10 100.0
|
||||
EFB 1 100.0
|
||||
EHXPLLJ 1 100.0
|
||||
FD1P3AX 28 100.0
|
||||
FD1P3IX 3 100.0
|
||||
FD1S3AX 37 100.0
|
||||
FD1S3IX 3 100.0
|
||||
GSR 1 100.0
|
||||
IB 24 100.0
|
||||
IFS1P3DX 9 100.0
|
||||
IFS1P3IX 10 100.0
|
||||
IFS1P3JX 2 100.0
|
||||
INV 7 100.0
|
||||
OB 31 100.0
|
||||
ODDRXE 1 100.0
|
||||
OFS1P3BX 4 100.0
|
||||
OFS1P3DX 8 100.0
|
||||
OFS1P3IX 1 100.0
|
||||
OFS1P3JX 1 100.0
|
||||
ORCALUT4 186 100.0
|
||||
OSCH 1 100.0
|
||||
PFUMX 2 100.0
|
||||
PUR 1 100.0
|
||||
VHI 2 100.0
|
||||
VLO 3 100.0
|
||||
SUB MODULES
|
||||
REFB 1 100.0
|
||||
RPLL 1 100.0
|
||||
|
||||
TOTAL 387
|
||||
----------------------------------------------------------------------
|
||||
Report for cell REFB.netlist
|
||||
Instance path: ufmefb
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
EFB 1 100.0
|
||||
VHI 1 50.0
|
||||
VLO 1 33.3
|
||||
|
||||
TOTAL 3
|
||||
----------------------------------------------------------------------
|
||||
Report for cell RPLL.netlist
|
||||
Instance path: rpll
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
EHXPLLJ 1 100.0
|
||||
VLO 1 33.3
|
||||
|
||||
TOTAL 2
|
||||
@ -0,0 +1,86 @@
|
||||
BITGEN: Bitstream Generator Diamond (64-bit) 3.11.3.469
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Sun Jul 14 22:31:27 2024
|
||||
|
||||
|
||||
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC-IntOsc -w -jedec -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC-IntOsc/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
|
||||
|
||||
Loading design for application Bitgen from file RAM2GS_LCMXO2_1200HC_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-1200HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application Bitgen from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.11_x64/ispfpga.
|
||||
Package Status: Final Version 1.42.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
|
||||
Running DRC.
|
||||
DRC detected 0 errors and 0 warnings.
|
||||
Reading Preference File from RAM2GS_LCMXO2_1200HC_impl1.prf.
|
||||
|
||||
Preference Summary:
|
||||
+---------------------------------+---------------------------------+
|
||||
| Preference | Current Setting |
|
||||
+---------------------------------+---------------------------------+
|
||||
| RamCfg | Reset** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MCCLK_FREQ | 2.08** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| CONFIG_SECURE | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| INBUF | ON** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| JTAG_PORT | ENABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SDM_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SLAVE_SPI_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MASTER_SPI_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| I2C_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MUX_CONFIGURATION_PORTS | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| CONFIGURATION | CFG** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| COMPRESS_CONFIG | ON** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MY_ASSP | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| ONE_TIME_PROGRAM | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| ENABLE_TRANSFR | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SHAREDEBRINIT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| BACKGROUND_RECONFIG | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
* Default setting.
|
||||
** The specified setting matches the default setting.
|
||||
|
||||
|
||||
Creating bit map...
|
||||
|
||||
Bitstream Status: Final Version 1.95.
|
||||
|
||||
Saving bit stream in "RAM2GS_LCMXO2_1200HC_impl1.jed".
|
||||
|
||||
===========
|
||||
UFM Summary.
|
||||
===========
|
||||
UFM Size: 511 Pages (128*511 Bits).
|
||||
UFM Utilization: General Purpose Flash Memory.
|
||||
|
||||
Available General Purpose Flash Memory: 511 Pages (Page 0 to Page 510).
|
||||
Initialized UFM Pages: 321 Pages (Page 190 to Page 510).
|
||||
|
||||
Total CPU Time: 3 secs
|
||||
Total REAL Time: 3 secs
|
||||
Peak Memory Usage: 275 MB
|
||||
4572
CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1.edi
Normal file
4572
CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1.edi
Normal file
File diff suppressed because it is too large
Load Diff
2778
CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1.jed
Normal file
2778
CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1.jed
Normal file
File diff suppressed because it is too large
Load Diff
600
CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1.mrp
Normal file
600
CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1.mrp
Normal file
@ -0,0 +1,600 @@
|
||||
|
||||
Lattice Mapping Report File for Design Module 'RAM2GS'
|
||||
|
||||
|
||||
Design Information
|
||||
------------------
|
||||
|
||||
Command line: map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 4 -oc Commercial
|
||||
RAM2GS_LCMXO2_1200HC_impl1.ngd -o RAM2GS_LCMXO2_1200HC_impl1_map.ncd -pr
|
||||
RAM2GS_LCMXO2_1200HC_impl1.prf -mp RAM2GS_LCMXO2_1200HC_impl1.mrp -lpf //Ma
|
||||
c/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_
|
||||
impl1_synplify.lpf -lpf //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.lpf -c
|
||||
0 -gui -msgset
|
||||
//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC-IntOsc/promote.xml
|
||||
Target Vendor: LATTICE
|
||||
Target Device: LCMXO2-1200HCTQFP100
|
||||
Target Performance: 4
|
||||
Mapper: xo2c00, version: Diamond (64-bit) 3.11.3.469
|
||||
Mapped on: 07/14/24 22:31:15
|
||||
|
||||
Design Summary
|
||||
--------------
|
||||
|
||||
Number of registers: 106 out of 1520 (7%)
|
||||
PFU registers: 71 out of 1280 (6%)
|
||||
PIO registers: 35 out of 240 (15%)
|
||||
Number of SLICEs: 106 out of 640 (17%)
|
||||
SLICEs as Logic/ROM: 106 out of 640 (17%)
|
||||
SLICEs as RAM: 0 out of 480 (0%)
|
||||
SLICEs as Carry: 10 out of 640 (2%)
|
||||
Number of LUT4s: 210 out of 1280 (16%)
|
||||
Number used as logic LUTs: 190
|
||||
Number used as distributed RAM: 0
|
||||
Number used as ripple logic: 20
|
||||
Number used as shift registers: 0
|
||||
Number of PIO sites used: 63 + 4(JTAG) out of 80 (84%)
|
||||
Number of IDDR/ODDR/TDDR cells used: 1 out of 240 (0%)
|
||||
Number of IDDR cells: 0
|
||||
Number of ODDR cells: 1
|
||||
Number of TDDR cells: 0
|
||||
Number of PIO using at least one IDDR/ODDR/TDDR: 1 (0 differential)
|
||||
Number of PIO using IDDR only: 0 (0 differential)
|
||||
Number of PIO using ODDR only: 1 (0 differential)
|
||||
Number of PIO using TDDR only: 0 (0 differential)
|
||||
Number of PIO using IDDR/ODDR: 0 (0 differential)
|
||||
Number of PIO using IDDR/TDDR: 0 (0 differential)
|
||||
Number of PIO using ODDR/TDDR: 0 (0 differential)
|
||||
Number of PIO using IDDR/ODDR/TDDR: 0 (0 differential)
|
||||
Number of block RAMs: 0 out of 7 (0%)
|
||||
Number of GSRs: 0 out of 1 (0%)
|
||||
EFB used : Yes
|
||||
JTAG used : No
|
||||
Readback used : No
|
||||
Oscillator used : Yes
|
||||
Startup used : No
|
||||
POR : On
|
||||
Bandgap : On
|
||||
Number of Power Controller: 0 out of 1 (0%)
|
||||
Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
|
||||
Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%)
|
||||
Number of DCCA: 0 out of 8 (0%)
|
||||
Number of DCMA: 0 out of 2 (0%)
|
||||
|
||||
Page 1
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 07/14/24 22:31:15
|
||||
|
||||
Design Summary (cont)
|
||||
---------------------
|
||||
Number of PLLs: 1 out of 1 (100%)
|
||||
Number of DQSDLLs: 0 out of 2 (0%)
|
||||
Number of CLKDIVC: 0 out of 4 (0%)
|
||||
Number of ECLKSYNCA: 0 out of 4 (0%)
|
||||
Number of ECLKBRIDGECS: 0 out of 2 (0%)
|
||||
Notes:-
|
||||
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
|
||||
distributed RAMs) + 2*(Number of ripple logic)
|
||||
2. Number of logic LUT4s does not include count of distributed RAM and
|
||||
ripple logic.
|
||||
Number of clocks: 5
|
||||
Net ICLK: 1 loads, 1 rising, 0 falling (Driver: OSCH_inst )
|
||||
Net PHI2_c: 19 loads, 9 rising, 10 falling (Driver: PIO PHI2 )
|
||||
Net PCLK: 48 loads, 48 rising, 0 falling (Driver: rpll/PLLInst_0 )
|
||||
Net nCRAS_c: 14 loads, 0 rising, 14 falling (Driver: PIO nCRAS )
|
||||
Net nCCAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCCAS )
|
||||
Number of Clock Enables: 7
|
||||
Net N_51: 1 loads, 1 LSLICEs
|
||||
Net XOR8MEG17: 5 loads, 5 LSLICEs
|
||||
Net N_94_i: 2 loads, 2 LSLICEs
|
||||
Net CmdUFMData_1_sqmuxa: 1 loads, 1 LSLICEs
|
||||
Net N_239_i: 10 loads, 10 LSLICEs
|
||||
Net N_63: 2 loads, 2 LSLICEs
|
||||
Net N_258_i: 2 loads, 2 LSLICEs
|
||||
Number of LSRs: 6
|
||||
Net RA10s_i: 1 loads, 0 LSLICEs
|
||||
Net wb_rst7: 3 loads, 3 LSLICEs
|
||||
Net wb_rst: 1 loads, 0 LSLICEs
|
||||
Net Ready: 13 loads, 0 LSLICEs
|
||||
Net nRRAS_0_sqmuxa: 1 loads, 1 LSLICEs
|
||||
Net RASr2: 1 loads, 1 LSLICEs
|
||||
Number of nets driven by tri-state buffers: 0
|
||||
Top 10 highest fanout non-clock nets:
|
||||
Net InitReady: 35 loads
|
||||
Net Ready: 27 loads
|
||||
Net FS[12]: 21 loads
|
||||
Net FS[13]: 19 loads
|
||||
Net FS[11]: 18 loads
|
||||
Net N_242: 18 loads
|
||||
Net FS[10]: 17 loads
|
||||
Net FS[14]: 17 loads
|
||||
Net FS[9]: 17 loads
|
||||
Net S[0]: 12 loads
|
||||
|
||||
|
||||
|
||||
|
||||
Number of warnings: 4
|
||||
Number of errors: 0
|
||||
|
||||
|
||||
Design Errors/Warnings
|
||||
----------------------
|
||||
|
||||
WARNING - map: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_
|
||||
LCMXO2_1200HC_impl1_synplify.lpf(9): Semantic error in "FREQUENCY PORT
|
||||
|
||||
Page 2
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 07/14/24 22:31:15
|
||||
|
||||
Design Errors/Warnings (cont)
|
||||
-----------------------------
|
||||
"RCLK" 62.500000 MHz ;": "RCLK" matches no ports in the design. This
|
||||
preference has been disabled.
|
||||
WARNING - map: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.lpf(68): Semantic
|
||||
error in "IOBUF PORT "RCLK" IO_TYPE=LVCMOS33 PULLMODE=NONE ;": Port "RCLK"
|
||||
does not exist in the design. This preference has been disabled.
|
||||
WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
||||
temporarily disable certain features of the device including Power
|
||||
Controller, GSR, Hardened User SPI Port, Hardened Primary User I2C Port.
|
||||
Functionality is restored after the Flash Memory (UFM/Configuration)
|
||||
Interface is disabled using Disable Configuration Interface command 0x26
|
||||
followed by Bypass command 0xFF.
|
||||
WARNING - map: IO buffer missing for top level port RCLK...logic will be
|
||||
discarded.
|
||||
|
||||
IO (PIO) Attributes
|
||||
-------------------
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| IO Name | Direction | Levelmode | IO |
|
||||
| | | IO_TYPE | Register |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[0] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[0] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| PHI2 | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RDQML | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RDQMH | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRCAS | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRRAS | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRWE | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RCKE | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RCLKout | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRCS | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[7] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[6] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[5] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[4] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[3] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[2] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[1] | BIDIR | LVCMOS33 | OUT |
|
||||
|
||||
Page 3
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 07/14/24 22:31:15
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[11] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[10] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[9] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[8] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[7] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[6] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[5] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[4] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[3] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[2] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[1] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[0] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RBA[1] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RBA[0] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| LED | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nFWE | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nCRAS | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nCCAS | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[7] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[6] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[5] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[4] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[3] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[2] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[1] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[7] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[6] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[5] | INPUT | LVCMOS33 | IN |
|
||||
|
||||
Page 4
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 07/14/24 22:31:15
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[4] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[3] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[2] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[1] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[0] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| CROW[1] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| CROW[0] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[9] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[8] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[7] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[6] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[5] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[4] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[3] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[2] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[1] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[0] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
Removed logic
|
||||
-------------
|
||||
|
||||
Block GSR_INST undriven or does not drive anything - clipped.
|
||||
Signal nCRAS_c_i was merged into signal nCRAS_c
|
||||
Signal RASr2_i was merged into signal RASr2
|
||||
Signal Ready_i was merged into signal Ready
|
||||
Signal XOR8MEG.CN was merged into signal PHI2_c
|
||||
Signal rpll/GND undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/VCC undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/GND undriven or does not drive anything - clipped.
|
||||
Signal FS_s_0_S1[17] undriven or does not drive anything - clipped.
|
||||
Signal FS_s_0_COUT[17] undriven or does not drive anything - clipped.
|
||||
Signal rpll/CLKINTFB undriven or does not drive anything - clipped.
|
||||
Signal rpll/DPHSRC undriven or does not drive anything - clipped.
|
||||
Signal rpll/PLLACK undriven or does not drive anything - clipped.
|
||||
Signal rpll/PLLDATO0 undriven or does not drive anything - clipped.
|
||||
Signal rpll/PLLDATO1 undriven or does not drive anything - clipped.
|
||||
Signal rpll/PLLDATO2 undriven or does not drive anything - clipped.
|
||||
Signal rpll/PLLDATO3 undriven or does not drive anything - clipped.
|
||||
|
||||
Page 5
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 07/14/24 22:31:15
|
||||
|
||||
Removed logic (cont)
|
||||
--------------------
|
||||
Signal rpll/PLLDATO4 undriven or does not drive anything - clipped.
|
||||
Signal rpll/PLLDATO5 undriven or does not drive anything - clipped.
|
||||
Signal rpll/PLLDATO6 undriven or does not drive anything - clipped.
|
||||
Signal rpll/PLLDATO7 undriven or does not drive anything - clipped.
|
||||
Signal rpll/REFCLK undriven or does not drive anything - clipped.
|
||||
Signal rpll/INTLOCK undriven or does not drive anything - clipped.
|
||||
Signal rpll/LOCK undriven or does not drive anything - clipped.
|
||||
Signal rpll/CLKOS3 undriven or does not drive anything - clipped.
|
||||
Signal rpll/CLKOS2 undriven or does not drive anything - clipped.
|
||||
Signal rpll/CLKOS undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/CFGWAKE undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wbc_ufm_irq undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/TCOC undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/TCINT undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIIRQO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPICSNEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMOSIEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMOSIO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMISOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMISOO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPISCKEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPISCKO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SDAOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SCLOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SDAOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SCLOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO0_0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO1_0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO2_0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO3_0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO4_0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO5_0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO6_0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO7_0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO4 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLWEO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLL1STBO undriven or does not drive anything - clipped.
|
||||
|
||||
Page 6
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 07/14/24 22:31:15
|
||||
|
||||
Removed logic (cont)
|
||||
--------------------
|
||||
Signal ufmefb/PLL0STBO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLRSTO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLCLKO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wb_dat_o_1[2] undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wb_dat_o_1[3] undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wb_dat_o_1[4] undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wb_dat_o_1[5] undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wb_dat_o_1[6] undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wb_dat_o_1[7] undriven or does not drive anything - clipped.
|
||||
Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped.
|
||||
Signal N_1 undriven or does not drive anything - clipped.
|
||||
Signal OSCH_inst_SEDSTDBY undriven or does not drive anything - clipped.
|
||||
Block nCRAS_pad_RNIBPVB was optimized away.
|
||||
Block RASr2_RNIAFR1 was optimized away.
|
||||
Block Ready_RNILCP9 was optimized away.
|
||||
Block C1Submitted.CN was optimized away.
|
||||
Block rpll/GND was optimized away.
|
||||
Block ufmefb/VCC was optimized away.
|
||||
Block ufmefb/GND was optimized away.
|
||||
|
||||
|
||||
|
||||
PLL/DLL Summary
|
||||
---------------
|
||||
|
||||
PLL 1: Pin/Node Value
|
||||
PLL Instance Name: rpll/PLLInst_0
|
||||
PLL Type: EHXPLLJ
|
||||
Input Clock: NODE ICLK
|
||||
Output Clock(P): NODE PCLK
|
||||
Output Clock(S): NONE
|
||||
Output Clock(S2): NONE
|
||||
Output Clock(S3): NONE
|
||||
Feedback Signal: NODE PCLK
|
||||
Reset Signal: NONE
|
||||
M Divider Reset Signal: NONE
|
||||
C Divider Reset Signal: NONE
|
||||
D Divider Reset Signal: NONE
|
||||
Standby Signal: NONE
|
||||
PLL LOCK signal: NONE
|
||||
PLL Data bus CLK Signal: NONE
|
||||
PLL Data bus Strobe Signal: NONE
|
||||
PLL Data bus Reset Signal: NONE
|
||||
PLL Data bus Write Enable Signal: NONE
|
||||
PLL Data bus Address0: NONE
|
||||
PLL Data bus Address1: NONE
|
||||
PLL Data bus Address2: NONE
|
||||
PLL Data bus Address3: NONE
|
||||
PLL Data bus Address4: NONE
|
||||
PLL Data In bus Data0: NONE
|
||||
PLL Data In bus Data1: NONE
|
||||
PLL Data In bus Data2: NONE
|
||||
PLL Data In bus Data3: NONE
|
||||
PLL Data In bus Data4: NONE
|
||||
PLL Data In bus Data5: NONE
|
||||
PLL Data In bus Data6: NONE
|
||||
|
||||
Page 7
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 07/14/24 22:31:15
|
||||
|
||||
PLL/DLL Summary (cont)
|
||||
----------------------
|
||||
PLL Data In bus Data7: NONE
|
||||
PLL Data bus Acknowledge: NONE
|
||||
PLL Data Out bus Data0: NONE
|
||||
PLL Data Out bus Data1: NONE
|
||||
PLL Data Out bus Data2: NONE
|
||||
PLL Data Out bus Data3: NONE
|
||||
PLL Data Out bus Data4: NONE
|
||||
PLL Data Out bus Data5: NONE
|
||||
PLL Data Out bus Data6: NONE
|
||||
PLL Data Out bus Data7: NONE
|
||||
Input Clock Frequency (MHz): 133.0000
|
||||
Output Clock(P) Frequency (MHz): 61.3846
|
||||
Output Clock(S) Frequency (MHz): NA
|
||||
Output Clock(S2) Frequency (MHz): NA
|
||||
Output Clock(S3) Frequency (MHz): NA
|
||||
CLKOP Post Divider A Input: DIVA
|
||||
CLKOS Post Divider B Input: DIVB
|
||||
CLKOS2 Post Divider C Input: DIVC
|
||||
CLKOS3 Post Divider D Input: DIVD
|
||||
Pre Divider A Input: VCO_PHASE
|
||||
Pre Divider B Input: VCO_PHASE
|
||||
Pre Divider C Input: VCO_PHASE
|
||||
Pre Divider D Input: VCO_PHASE
|
||||
VCO Bypass A Input: VCO_PHASE
|
||||
VCO Bypass B Input: VCO_PHASE
|
||||
VCO Bypass C Input: VCO_PHASE
|
||||
VCO Bypass D Input: VCO_PHASE
|
||||
FB_MODE: CLKOP
|
||||
CLKI Divider: 13
|
||||
CLKFB Divider: 6
|
||||
CLKOP Divider: 8
|
||||
CLKOS Divider: 1
|
||||
CLKOS2 Divider: 1
|
||||
CLKOS3 Divider: 1
|
||||
Fractional N Divider: 0
|
||||
CLKOP Desired Phase Shift(degree): 0
|
||||
CLKOP Trim Option Rising/Falling: RISING
|
||||
CLKOP Trim Option Delay: 0
|
||||
CLKOS Desired Phase Shift(degree): 0
|
||||
CLKOS Trim Option Rising/Falling: FALLING
|
||||
CLKOS Trim Option Delay: 0
|
||||
CLKOS2 Desired Phase Shift(degree): 0
|
||||
CLKOS3 Desired Phase Shift(degree): 0
|
||||
|
||||
OSC Summary
|
||||
-----------
|
||||
|
||||
OSC 1: Pin/Node Value
|
||||
OSC Instance Name: OSCH_inst
|
||||
OSC Type: OSCH
|
||||
STDBY Input: NONE
|
||||
OSC Output: NODE ICLK
|
||||
OSC Nominal Frequency (MHz): 133.00
|
||||
|
||||
|
||||
|
||||
|
||||
Page 8
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 07/14/24 22:31:15
|
||||
|
||||
Embedded Functional Block Connection Summary
|
||||
--------------------------------------------
|
||||
|
||||
Desired WISHBONE clock frequency: 66.7 MHz
|
||||
Clock source: PCLK
|
||||
Reset source: wb_rst
|
||||
Functions mode:
|
||||
I2C #1 (Primary) Function: DISABLED
|
||||
I2C #2 (Secondary) Function: DISABLED
|
||||
SPI Function: DISABLED
|
||||
Timer/Counter Function: DISABLED
|
||||
Timer/Counter Mode: WB
|
||||
UFM Connection: ENABLED
|
||||
PLL0 Connection: DISABLED
|
||||
PLL1 Connection: DISABLED
|
||||
I2C Function Summary:
|
||||
--------------------
|
||||
None
|
||||
SPI Function Summary:
|
||||
--------------------
|
||||
None
|
||||
Timer/Counter Function Summary:
|
||||
------------------------------
|
||||
None
|
||||
UFM Function Summary:
|
||||
--------------------
|
||||
UFM Utilization: General Purpose Flash Memory
|
||||
Initialized UFM Pages: 321 Pages (321*128 Bits)
|
||||
Available General
|
||||
Purpose Flash Memory: 511 Pages (511*128 Bits)
|
||||
|
||||
EBR Blocks with Unique
|
||||
Initialization Data: 0
|
||||
|
||||
WID EBR Instance
|
||||
--- ------------
|
||||
|
||||
|
||||
ASIC Components
|
||||
---------------
|
||||
|
||||
Instance Name: OSCH_inst
|
||||
Type: OSCH
|
||||
Instance Name: ufmefb/EFBInst_0
|
||||
Type: EFB
|
||||
Instance Name: rpll/PLLInst_0
|
||||
Type: EHXPLLJ
|
||||
|
||||
Run Time and Memory Usage
|
||||
-------------------------
|
||||
|
||||
Total CPU Time: 0 secs
|
||||
Total REAL Time: 0 secs
|
||||
Peak Memory Usage: 64 MB
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Page 9
|
||||
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights
|
||||
reserved.
|
||||
303
CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1.pad
Normal file
303
CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1.pad
Normal file
@ -0,0 +1,303 @@
|
||||
PAD Specification File
|
||||
***************************
|
||||
|
||||
PART TYPE: LCMXO2-1200HC
|
||||
Performance Grade: 4
|
||||
PACKAGE: TQFP100
|
||||
Package Status: Final Version 1.42
|
||||
|
||||
Sun Jul 14 22:31:22 2024
|
||||
|
||||
Pinout by Port Name:
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties |
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
| CROW[0] | 10/3 | LVCMOS33_IN | PL4B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| CROW[1] | 16/3 | LVCMOS33_IN | PL8A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[0] | 3/3 | LVCMOS33_IN | PL3A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[1] | 96/0 | LVCMOS33_IN | PT10B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[2] | 88/0 | LVCMOS33_IN | PT12A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[3] | 97/0 | LVCMOS33_IN | PT10A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[4] | 99/0 | LVCMOS33_IN | PT9A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[5] | 98/0 | LVCMOS33_IN | PT9B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[6] | 2/3 | LVCMOS33_IN | PL2D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[7] | 1/3 | LVCMOS33_IN | PL2C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Dout[0] | 76/0 | LVCMOS33_OUT | PT17D | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[1] | 86/0 | LVCMOS33_OUT | PT12C | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[2] | 87/0 | LVCMOS33_OUT | PT12B | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[3] | 85/0 | LVCMOS33_OUT | PT12D | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[4] | 83/0 | LVCMOS33_OUT | PT15B | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[5] | 84/0 | LVCMOS33_OUT | PT15A | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[6] | 78/0 | LVCMOS33_OUT | PT16C | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[7] | 82/0 | LVCMOS33_OUT | PT15C | | | DRIVE:4mA SLEW:FAST |
|
||||
| LED | 34/2 | LVCMOS33_OUT | PB9A | | | DRIVE:24mA SLEW:SLOW |
|
||||
| MAin[0] | 14/3 | LVCMOS33_IN | PL5C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[1] | 12/3 | LVCMOS33_IN | PL5A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[2] | 13/3 | LVCMOS33_IN | PL5B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[3] | 21/3 | LVCMOS33_IN | PL9B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[4] | 20/3 | LVCMOS33_IN | PL9A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[5] | 19/3 | LVCMOS33_IN | PL8D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[6] | 24/3 | LVCMOS33_IN | PL10C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[7] | 18/3 | LVCMOS33_IN | PL8C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[8] | 25/3 | LVCMOS33_IN | PL10D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[9] | 32/2 | LVCMOS33_IN | PB6D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| PHI2 | 8/3 | LVCMOS33_IN | PL3D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| RA[0] | 66/1 | LVCMOS33_OUT | PR4D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[10] | 64/1 | LVCMOS33_OUT | PR5B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[11] | 59/1 | LVCMOS33_OUT | PR8D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[1] | 67/1 | LVCMOS33_OUT | PR4C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[2] | 69/1 | LVCMOS33_OUT | PR4A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[3] | 71/1 | LVCMOS33_OUT | PR3A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[4] | 74/1 | LVCMOS33_OUT | PR2B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[5] | 70/1 | LVCMOS33_OUT | PR3B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[6] | 68/1 | LVCMOS33_OUT | PR4B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[7] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[9] | 62/1 | LVCMOS33_OUT | PR5D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RBA[0] | 58/1 | LVCMOS33_OUT | PR9A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RBA[1] | 47/2 | LVCMOS33_OUT | PB18D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RCKE | 53/1 | LVCMOS33_OUT | PR9D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RCLKout | 60/1 | LVCMOS33_OUT | PR8C | | | DRIVE:24mA SLEW:FAST |
|
||||
| RDQMH | 51/1 | LVCMOS33_OUT | PR10D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RDQML | 48/2 | LVCMOS33_OUT | PB20C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RD[0] | 36/2 | LVCMOS33_BIDI | PB11C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[1] | 37/2 | LVCMOS33_BIDI | PB11D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[2] | 38/2 | LVCMOS33_BIDI | PB11A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[3] | 39/2 | LVCMOS33_BIDI | PB11B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[4] | 40/2 | LVCMOS33_BIDI | PB15A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[5] | 41/2 | LVCMOS33_BIDI | PB15B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[6] | 42/2 | LVCMOS33_BIDI | PB18A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[7] | 43/2 | LVCMOS33_BIDI | PB18B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| nCCAS | 9/3 | LVCMOS33_IN | PL4A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nCRAS | 17/3 | LVCMOS33_IN | PL8B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nFWE | 15/3 | LVCMOS33_IN | PL5D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nRCAS | 52/1 | LVCMOS33_OUT | PR10C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nRCS | 57/1 | LVCMOS33_OUT | PR9B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nRRAS | 54/1 | LVCMOS33_OUT | PR9C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nRWE | 49/2 | LVCMOS33_OUT | PB20D | | | DRIVE:4mA SLEW:SLOW |
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
|
||||
Vccio by Bank:
|
||||
+------+-------+
|
||||
| Bank | Vccio |
|
||||
+------+-------+
|
||||
| 0 | 3.3V |
|
||||
| 1 | 3.3V |
|
||||
| 2 | 3.3V |
|
||||
| 3 | 3.3V |
|
||||
+------+-------+
|
||||
|
||||
Vref by Bank:
|
||||
+------+-----+-----------------+---------+
|
||||
| Vref | Pin | Bank # / Vref # | Load(s) |
|
||||
+------+-----+-----------------+---------+
|
||||
+------+-----+-----------------+---------+
|
||||
|
||||
Pinout by Pin Number:
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable |
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
| 1/3 | Din[7] | LOCATED | LVCMOS33_IN | PL2C | L_GPLLT_IN | | |
|
||||
| 2/3 | Din[6] | LOCATED | LVCMOS33_IN | PL2D | L_GPLLC_IN | | |
|
||||
| 3/3 | Din[0] | LOCATED | LVCMOS33_IN | PL3A | PCLKT3_2 | | |
|
||||
| 4/3 | unused, PULL:DOWN | | | PL3B | PCLKC3_2 | | |
|
||||
| 7/3 | unused, PULL:DOWN | | | PL3C | | | |
|
||||
| 8/3 | PHI2 | LOCATED | LVCMOS33_IN | PL3D | | | |
|
||||
| 9/3 | nCCAS | LOCATED | LVCMOS33_IN | PL4A | | | |
|
||||
| 10/3 | CROW[0] | LOCATED | LVCMOS33_IN | PL4B | | | |
|
||||
| 12/3 | MAin[1] | LOCATED | LVCMOS33_IN | PL5A | PCLKT3_1 | | |
|
||||
| 13/3 | MAin[2] | LOCATED | LVCMOS33_IN | PL5B | PCLKC3_1 | | |
|
||||
| 14/3 | MAin[0] | LOCATED | LVCMOS33_IN | PL5C | | | |
|
||||
| 15/3 | nFWE | LOCATED | LVCMOS33_IN | PL5D | | | |
|
||||
| 16/3 | CROW[1] | LOCATED | LVCMOS33_IN | PL8A | | | |
|
||||
| 17/3 | nCRAS | LOCATED | LVCMOS33_IN | PL8B | | | |
|
||||
| 18/3 | MAin[7] | LOCATED | LVCMOS33_IN | PL8C | | | |
|
||||
| 19/3 | MAin[5] | LOCATED | LVCMOS33_IN | PL8D | | | |
|
||||
| 20/3 | MAin[4] | LOCATED | LVCMOS33_IN | PL9A | PCLKT3_0 | | |
|
||||
| 21/3 | MAin[3] | LOCATED | LVCMOS33_IN | PL9B | PCLKC3_0 | | |
|
||||
| 24/3 | MAin[6] | LOCATED | LVCMOS33_IN | PL10C | | | |
|
||||
| 25/3 | MAin[8] | LOCATED | LVCMOS33_IN | PL10D | | | |
|
||||
| 27/2 | unused, PULL:DOWN | | | PB4C | CSSPIN | | |
|
||||
| 28/2 | unused, PULL:DOWN | | | PB4D | | | |
|
||||
| 29/2 | unused, PULL:DOWN | | | PB6A | | | |
|
||||
| 30/2 | unused, PULL:DOWN | | | PB6B | | | |
|
||||
| 31/2 | unused, PULL:DOWN | | | PB6C | MCLK/CCLK | | |
|
||||
| 32/2 | MAin[9] | LOCATED | LVCMOS33_IN | PB6D | SO/SPISO | | |
|
||||
| 34/2 | LED | LOCATED | LVCMOS33_OUT | PB9A | PCLKT2_0 | | |
|
||||
| 35/2 | unused, PULL:DOWN | | | PB9B | PCLKC2_0 | | |
|
||||
| 36/2 | RD[0] | LOCATED | LVCMOS33_BIDI | PB11C | | | |
|
||||
| 37/2 | RD[1] | LOCATED | LVCMOS33_BIDI | PB11D | | | |
|
||||
| 38/2 | RD[2] | LOCATED | LVCMOS33_BIDI | PB11A | PCLKT2_1 | | |
|
||||
| 39/2 | RD[3] | LOCATED | LVCMOS33_BIDI | PB11B | PCLKC2_1 | | |
|
||||
| 40/2 | RD[4] | LOCATED | LVCMOS33_BIDI | PB15A | | | |
|
||||
| 41/2 | RD[5] | LOCATED | LVCMOS33_BIDI | PB15B | | | |
|
||||
| 42/2 | RD[6] | LOCATED | LVCMOS33_BIDI | PB18A | | | |
|
||||
| 43/2 | RD[7] | LOCATED | LVCMOS33_BIDI | PB18B | | | |
|
||||
| 45/2 | unused, PULL:DOWN | | | PB18C | | | |
|
||||
| 47/2 | RBA[1] | LOCATED | LVCMOS33_OUT | PB18D | | | |
|
||||
| 48/2 | RDQML | LOCATED | LVCMOS33_OUT | PB20C | SN | | |
|
||||
| 49/2 | nRWE | LOCATED | LVCMOS33_OUT | PB20D | SI/SISPI | | |
|
||||
| 51/1 | RDQMH | LOCATED | LVCMOS33_OUT | PR10D | DQ1 | | |
|
||||
| 52/1 | nRCAS | LOCATED | LVCMOS33_OUT | PR10C | DQ1 | | |
|
||||
| 53/1 | RCKE | LOCATED | LVCMOS33_OUT | PR9D | DQ1 | | |
|
||||
| 54/1 | nRRAS | LOCATED | LVCMOS33_OUT | PR9C | DQ1 | | |
|
||||
| 57/1 | nRCS | LOCATED | LVCMOS33_OUT | PR9B | DQ1 | | |
|
||||
| 58/1 | RBA[0] | LOCATED | LVCMOS33_OUT | PR9A | DQ1 | | |
|
||||
| 59/1 | RA[11] | LOCATED | LVCMOS33_OUT | PR8D | DQ1 | | |
|
||||
| 60/1 | RCLKout | LOCATED | LVCMOS33_OUT | PR8C | DQ1 | | |
|
||||
| 61/1 | unused, PULL:DOWN | | | PR8A | DQS1 | | |
|
||||
| 62/1 | RA[9] | LOCATED | LVCMOS33_OUT | PR5D | PCLKC1_0/DQ0 | | |
|
||||
| 63/1 | unused, PULL:DOWN | | | PR5C | PCLKT1_0/DQ0 | | |
|
||||
| 64/1 | RA[10] | LOCATED | LVCMOS33_OUT | PR5B | DQS0N | | |
|
||||
| 65/1 | RA[8] | LOCATED | LVCMOS33_OUT | PR5A | DQS0 | | |
|
||||
| 66/1 | RA[0] | LOCATED | LVCMOS33_OUT | PR4D | DQ0 | | |
|
||||
| 67/1 | RA[1] | LOCATED | LVCMOS33_OUT | PR4C | DQ0 | | |
|
||||
| 68/1 | RA[6] | LOCATED | LVCMOS33_OUT | PR4B | DQ0 | | |
|
||||
| 69/1 | RA[2] | LOCATED | LVCMOS33_OUT | PR4A | DQ0 | | |
|
||||
| 70/1 | RA[5] | LOCATED | LVCMOS33_OUT | PR3B | DQ0 | | |
|
||||
| 71/1 | RA[3] | LOCATED | LVCMOS33_OUT | PR3A | DQ0 | | |
|
||||
| 74/1 | RA[4] | LOCATED | LVCMOS33_OUT | PR2B | DQ0 | | |
|
||||
| 75/1 | RA[7] | LOCATED | LVCMOS33_OUT | PR2A | DQ0 | | |
|
||||
| 76/0 | Dout[0] | LOCATED | LVCMOS33_OUT | PT17D | DONE | | |
|
||||
| 77/0 | unused, PULL:DOWN | | | PT17C | INITN | | |
|
||||
| 78/0 | Dout[6] | LOCATED | LVCMOS33_OUT | PT16C | | | |
|
||||
| 81/0 | unused, PULL:DOWN | | | PT15D | PROGRAMN | | |
|
||||
| 82/0 | Dout[7] | LOCATED | LVCMOS33_OUT | PT15C | JTAGENB | | |
|
||||
| 83/0 | Dout[4] | LOCATED | LVCMOS33_OUT | PT15B | | | |
|
||||
| 84/0 | Dout[5] | LOCATED | LVCMOS33_OUT | PT15A | | | |
|
||||
| 85/0 | Dout[3] | LOCATED | LVCMOS33_OUT | PT12D | SDA/PCLKC0_0 | | |
|
||||
| 86/0 | Dout[1] | LOCATED | LVCMOS33_OUT | PT12C | SCL/PCLKT0_0 | | |
|
||||
| 87/0 | Dout[2] | LOCATED | LVCMOS33_OUT | PT12B | PCLKC0_1 | | |
|
||||
| 88/0 | Din[2] | LOCATED | LVCMOS33_IN | PT12A | PCLKT0_1 | | |
|
||||
| 90/0 | Reserved: sysCONFIG | | | PT11D | TMS | | |
|
||||
| 91/0 | Reserved: sysCONFIG | | | PT11C | TCK | | |
|
||||
| 94/0 | Reserved: sysCONFIG | | | PT10D | TDI | | |
|
||||
| 95/0 | Reserved: sysCONFIG | | | PT10C | TDO | | |
|
||||
| 96/0 | Din[1] | LOCATED | LVCMOS33_IN | PT10B | | | |
|
||||
| 97/0 | Din[3] | LOCATED | LVCMOS33_IN | PT10A | | | |
|
||||
| 98/0 | Din[5] | LOCATED | LVCMOS33_IN | PT9B | | | |
|
||||
| 99/0 | Din[4] | LOCATED | LVCMOS33_IN | PT9A | | | |
|
||||
| PB4A/2 | unused, PULL:DOWN | | | PB4A | | | |
|
||||
| PB4B/2 | unused, PULL:DOWN | | | PB4B | | | |
|
||||
| PB9C/2 | unused, PULL:DOWN | | | PB9C | | | |
|
||||
| PB9D/2 | unused, PULL:DOWN | | | PB9D | | | |
|
||||
| PB15C/2 | unused, PULL:DOWN | | | PB15C | | | |
|
||||
| PB15D/2 | unused, PULL:DOWN | | | PB15D | | | |
|
||||
| PB20A/2 | unused, PULL:DOWN | | | PB20A | | | |
|
||||
| PB20B/2 | unused, PULL:DOWN | | | PB20B | | | |
|
||||
| PL2A/3 | unused, PULL:DOWN | | | PL2A | L_GPLLT_FB | | |
|
||||
| PL2B/3 | unused, PULL:DOWN | | | PL2B | L_GPLLC_FB | | |
|
||||
| PL4C/3 | unused, PULL:DOWN | | | PL4C | | | |
|
||||
| PL4D/3 | unused, PULL:DOWN | | | PL4D | | | |
|
||||
| PL10A/3 | unused, PULL:DOWN | | | PL10A | | | |
|
||||
| PL10B/3 | unused, PULL:DOWN | | | PL10B | | | |
|
||||
| PR2C/1 | unused, PULL:DOWN | | | PR2C | DQ0 | | |
|
||||
| PR2D/1 | unused, PULL:DOWN | | | PR2D | DQ0 | | |
|
||||
| PR8B/1 | unused, PULL:DOWN | | | PR8B | DQS1N | | |
|
||||
| PR10A/1 | unused, PULL:DOWN | | | PR10A | DQ1 | | |
|
||||
| PR10B/1 | unused, PULL:DOWN | | | PR10B | DQ1 | | |
|
||||
| PT9C/0 | unused, PULL:DOWN | | | PT9C | | | |
|
||||
| PT9D/0 | unused, PULL:DOWN | | | PT9D | | | |
|
||||
| PT11A/0 | unused, PULL:DOWN | | | PT11A | | | |
|
||||
| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | |
|
||||
| PT16A/0 | unused, PULL:DOWN | | | PT16A | | | |
|
||||
| PT16B/0 | unused, PULL:DOWN | | | PT16B | | | |
|
||||
| PT16D/0 | unused, PULL:DOWN | | | PT16D | | | |
|
||||
| PT17A/0 | unused, PULL:DOWN | | | PT17A | | | |
|
||||
| PT17B/0 | unused, PULL:DOWN | | | PT17B | | | |
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
|
||||
sysCONFIG Pins:
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode |
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
| PT11D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP |
|
||||
| PT11C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down |
|
||||
| PT10D | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP |
|
||||
| PT10C | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP |
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
|
||||
Dedicated sysCONFIG Pins:
|
||||
|
||||
|
||||
List of All Pins' Locate Preferences Based on Final Placement After PAR
|
||||
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste):
|
||||
|
||||
LOCATE COMP "CROW[0]" SITE "10";
|
||||
LOCATE COMP "CROW[1]" SITE "16";
|
||||
LOCATE COMP "Din[0]" SITE "3";
|
||||
LOCATE COMP "Din[1]" SITE "96";
|
||||
LOCATE COMP "Din[2]" SITE "88";
|
||||
LOCATE COMP "Din[3]" SITE "97";
|
||||
LOCATE COMP "Din[4]" SITE "99";
|
||||
LOCATE COMP "Din[5]" SITE "98";
|
||||
LOCATE COMP "Din[6]" SITE "2";
|
||||
LOCATE COMP "Din[7]" SITE "1";
|
||||
LOCATE COMP "Dout[0]" SITE "76";
|
||||
LOCATE COMP "Dout[1]" SITE "86";
|
||||
LOCATE COMP "Dout[2]" SITE "87";
|
||||
LOCATE COMP "Dout[3]" SITE "85";
|
||||
LOCATE COMP "Dout[4]" SITE "83";
|
||||
LOCATE COMP "Dout[5]" SITE "84";
|
||||
LOCATE COMP "Dout[6]" SITE "78";
|
||||
LOCATE COMP "Dout[7]" SITE "82";
|
||||
LOCATE COMP "LED" SITE "34";
|
||||
LOCATE COMP "MAin[0]" SITE "14";
|
||||
LOCATE COMP "MAin[1]" SITE "12";
|
||||
LOCATE COMP "MAin[2]" SITE "13";
|
||||
LOCATE COMP "MAin[3]" SITE "21";
|
||||
LOCATE COMP "MAin[4]" SITE "20";
|
||||
LOCATE COMP "MAin[5]" SITE "19";
|
||||
LOCATE COMP "MAin[6]" SITE "24";
|
||||
LOCATE COMP "MAin[7]" SITE "18";
|
||||
LOCATE COMP "MAin[8]" SITE "25";
|
||||
LOCATE COMP "MAin[9]" SITE "32";
|
||||
LOCATE COMP "PHI2" SITE "8";
|
||||
LOCATE COMP "RA[0]" SITE "66";
|
||||
LOCATE COMP "RA[10]" SITE "64";
|
||||
LOCATE COMP "RA[11]" SITE "59";
|
||||
LOCATE COMP "RA[1]" SITE "67";
|
||||
LOCATE COMP "RA[2]" SITE "69";
|
||||
LOCATE COMP "RA[3]" SITE "71";
|
||||
LOCATE COMP "RA[4]" SITE "74";
|
||||
LOCATE COMP "RA[5]" SITE "70";
|
||||
LOCATE COMP "RA[6]" SITE "68";
|
||||
LOCATE COMP "RA[7]" SITE "75";
|
||||
LOCATE COMP "RA[8]" SITE "65";
|
||||
LOCATE COMP "RA[9]" SITE "62";
|
||||
LOCATE COMP "RBA[0]" SITE "58";
|
||||
LOCATE COMP "RBA[1]" SITE "47";
|
||||
LOCATE COMP "RCKE" SITE "53";
|
||||
LOCATE COMP "RCLKout" SITE "60";
|
||||
LOCATE COMP "RDQMH" SITE "51";
|
||||
LOCATE COMP "RDQML" SITE "48";
|
||||
LOCATE COMP "RD[0]" SITE "36";
|
||||
LOCATE COMP "RD[1]" SITE "37";
|
||||
LOCATE COMP "RD[2]" SITE "38";
|
||||
LOCATE COMP "RD[3]" SITE "39";
|
||||
LOCATE COMP "RD[4]" SITE "40";
|
||||
LOCATE COMP "RD[5]" SITE "41";
|
||||
LOCATE COMP "RD[6]" SITE "42";
|
||||
LOCATE COMP "RD[7]" SITE "43";
|
||||
LOCATE COMP "nCCAS" SITE "9";
|
||||
LOCATE COMP "nCRAS" SITE "17";
|
||||
LOCATE COMP "nFWE" SITE "15";
|
||||
LOCATE COMP "nRCAS" SITE "52";
|
||||
LOCATE COMP "nRCS" SITE "57";
|
||||
LOCATE COMP "nRRAS" SITE "54";
|
||||
LOCATE COMP "nRWE" SITE "49";
|
||||
|
||||
#PLL
|
||||
LOCATE COMP "rpll/PLLInst_0" SITE "LPLL" ;
|
||||
|
||||
|
||||
|
||||
|
||||
PAR: Place And Route Diamond (64-bit) 3.11.3.469.
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Sun Jul 14 22:31:25 2024
|
||||
|
||||
115
CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1.prf
Normal file
115
CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1.prf
Normal file
@ -0,0 +1,115 @@
|
||||
SCHEMATIC START ;
|
||||
# map: version Diamond (64-bit) 3.11.3.469 -- WARNING: Map write only section -- Sun Jul 14 22:31:16 2024
|
||||
|
||||
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
|
||||
LOCATE COMP "RD[0]" SITE "36" ;
|
||||
LOCATE COMP "Dout[0]" SITE "76" ;
|
||||
LOCATE COMP "PHI2" SITE "8" ;
|
||||
LOCATE COMP "RDQML" SITE "48" ;
|
||||
LOCATE COMP "RDQMH" SITE "51" ;
|
||||
LOCATE COMP "nRCAS" SITE "52" ;
|
||||
LOCATE COMP "nRRAS" SITE "54" ;
|
||||
LOCATE COMP "nRWE" SITE "49" ;
|
||||
LOCATE COMP "RCKE" SITE "53" ;
|
||||
LOCATE COMP "RCLKout" SITE "60" ;
|
||||
LOCATE COMP "nRCS" SITE "57" ;
|
||||
LOCATE COMP "RD[7]" SITE "43" ;
|
||||
LOCATE COMP "RD[6]" SITE "42" ;
|
||||
LOCATE COMP "RD[5]" SITE "41" ;
|
||||
LOCATE COMP "RD[4]" SITE "40" ;
|
||||
LOCATE COMP "RD[3]" SITE "39" ;
|
||||
LOCATE COMP "RD[2]" SITE "38" ;
|
||||
LOCATE COMP "RD[1]" SITE "37" ;
|
||||
LOCATE COMP "RA[11]" SITE "59" ;
|
||||
LOCATE COMP "RA[10]" SITE "64" ;
|
||||
LOCATE COMP "RA[9]" SITE "62" ;
|
||||
LOCATE COMP "RA[8]" SITE "65" ;
|
||||
LOCATE COMP "RA[7]" SITE "75" ;
|
||||
LOCATE COMP "RA[6]" SITE "68" ;
|
||||
LOCATE COMP "RA[5]" SITE "70" ;
|
||||
LOCATE COMP "RA[4]" SITE "74" ;
|
||||
LOCATE COMP "RA[3]" SITE "71" ;
|
||||
LOCATE COMP "RA[2]" SITE "69" ;
|
||||
LOCATE COMP "RA[1]" SITE "67" ;
|
||||
LOCATE COMP "RA[0]" SITE "66" ;
|
||||
LOCATE COMP "RBA[1]" SITE "47" ;
|
||||
LOCATE COMP "RBA[0]" SITE "58" ;
|
||||
LOCATE COMP "LED" SITE "34" ;
|
||||
LOCATE COMP "nFWE" SITE "15" ;
|
||||
LOCATE COMP "nCRAS" SITE "17" ;
|
||||
LOCATE COMP "nCCAS" SITE "9" ;
|
||||
LOCATE COMP "Dout[7]" SITE "82" ;
|
||||
LOCATE COMP "Dout[6]" SITE "78" ;
|
||||
LOCATE COMP "Dout[5]" SITE "84" ;
|
||||
LOCATE COMP "Dout[4]" SITE "83" ;
|
||||
LOCATE COMP "Dout[3]" SITE "85" ;
|
||||
LOCATE COMP "Dout[2]" SITE "87" ;
|
||||
LOCATE COMP "Dout[1]" SITE "86" ;
|
||||
LOCATE COMP "Din[7]" SITE "1" ;
|
||||
LOCATE COMP "Din[6]" SITE "2" ;
|
||||
LOCATE COMP "Din[5]" SITE "98" ;
|
||||
LOCATE COMP "Din[4]" SITE "99" ;
|
||||
LOCATE COMP "Din[3]" SITE "97" ;
|
||||
LOCATE COMP "Din[2]" SITE "88" ;
|
||||
LOCATE COMP "Din[1]" SITE "96" ;
|
||||
LOCATE COMP "Din[0]" SITE "3" ;
|
||||
LOCATE COMP "CROW[1]" SITE "16" ;
|
||||
LOCATE COMP "CROW[0]" SITE "10" ;
|
||||
LOCATE COMP "MAin[9]" SITE "32" ;
|
||||
LOCATE COMP "MAin[8]" SITE "25" ;
|
||||
LOCATE COMP "MAin[7]" SITE "18" ;
|
||||
LOCATE COMP "MAin[6]" SITE "24" ;
|
||||
LOCATE COMP "MAin[5]" SITE "19" ;
|
||||
LOCATE COMP "MAin[4]" SITE "20" ;
|
||||
LOCATE COMP "MAin[3]" SITE "21" ;
|
||||
LOCATE COMP "MAin[2]" SITE "13" ;
|
||||
LOCATE COMP "MAin[1]" SITE "12" ;
|
||||
LOCATE COMP "MAin[0]" SITE "14" ;
|
||||
FREQUENCY NET "ICLK" 133.000000 MHz ;
|
||||
FREQUENCY NET "PCLK" 61.384615 MHz ;
|
||||
FREQUENCY PORT "PHI2" 2.900000 MHz ;
|
||||
FREQUENCY PORT "nCCAS" 2.900000 MHz ;
|
||||
FREQUENCY PORT "nCRAS" 2.900000 MHz ;
|
||||
SCHEMATIC END ;
|
||||
BLOCK RESETPATHS ;
|
||||
BLOCK ASYNCPATHS ;
|
||||
OUTPUT PORT "Dout[0]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Dout[1]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Dout[2]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Dout[3]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Dout[4]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Dout[5]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Dout[6]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Dout[7]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "LED" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[0]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[1]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[2]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[3]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[4]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[5]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[6]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[7]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[8]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[9]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[10]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[11]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RBA[0]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RBA[1]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RCKE" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RDQMH" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RDQML" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "nRCAS" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "nRCS" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "nRRAS" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "nRWE" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RD[0]" LOAD 9.000000 pF ;
|
||||
OUTPUT PORT "RD[1]" LOAD 9.000000 pF ;
|
||||
OUTPUT PORT "RD[2]" LOAD 9.000000 pF ;
|
||||
OUTPUT PORT "RD[3]" LOAD 9.000000 pF ;
|
||||
OUTPUT PORT "RD[4]" LOAD 9.000000 pF ;
|
||||
OUTPUT PORT "RD[5]" LOAD 9.000000 pF ;
|
||||
OUTPUT PORT "RD[6]" LOAD 9.000000 pF ;
|
||||
OUTPUT PORT "RD[7]" LOAD 9.000000 pF ;
|
||||
OUTPUT PORT "RCLKout" LOAD 5.000000 pF ;
|
||||
COMMERCIAL ;
|
||||
808
CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1.srr
Normal file
808
CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_impl1.srr
Normal file
@ -0,0 +1,808 @@
|
||||
#Build: Synplify Pro (R) N-2018.03L-SP1-1, Build 443R, Apr 1 2019
|
||||
#install: C:\lscc\diamond\3.11_x64\synpbase
|
||||
#OS: Windows 8 6.2
|
||||
#Hostname: ZANEMACWIN11
|
||||
|
||||
# Sun Jul 14 22:31:08 2024
|
||||
|
||||
#Implementation: impl1
|
||||
|
||||
|
||||
Copyright (C) 1994-2018 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: N-2018.03L-SP1-1
|
||||
Install: C:\lscc\diamond\3.11_x64\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
Synopsys HDL Compiler, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
|
||||
Copyright (C) 1994-2018 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: N-2018.03L-SP1-1
|
||||
Install: C:\lscc\diamond\3.11_x64\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
Synopsys Verilog Compiler, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v" (library work)
|
||||
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\pmi_def.v" (library work)
|
||||
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
|
||||
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
|
||||
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
|
||||
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
|
||||
@I::"\\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\REFB.v" (library work)
|
||||
@I::"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2-IntOsc.v" (library work)
|
||||
@I::"\\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\RPLL.v" (library work)
|
||||
Verilog syntax check successful!
|
||||
Options changed - recompiling
|
||||
Selecting top level module RAM2GS
|
||||
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1793:7:1793:10|Synthesizing module OSCH in library work.
|
||||
Running optimization stage 1 on OSCH .......
|
||||
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
|
||||
Running optimization stage 1 on VLO .......
|
||||
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1730:7:1730:13|Synthesizing module EHXPLLJ in library work.
|
||||
Running optimization stage 1 on EHXPLLJ .......
|
||||
@N: CG364 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\RPLL.v":8:7:8:10|Synthesizing module RPLL in library work.
|
||||
Running optimization stage 1 on RPLL .......
|
||||
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1601:7:1601:12|Synthesizing module ODDRXE in library work.
|
||||
Running optimization stage 1 on ODDRXE .......
|
||||
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
|
||||
Running optimization stage 1 on VHI .......
|
||||
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
|
||||
Running optimization stage 1 on EFB .......
|
||||
@N: CG364 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
|
||||
Running optimization stage 1 on REFB .......
|
||||
@W: CL318 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\REFB.v":9:14:9:21|*Output wb_dat_o has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output.
|
||||
@N: CG364 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2-IntOsc.v":1:7:1:12|Synthesizing module RAM2GS in library work.
|
||||
Running optimization stage 1 on RAM2GS .......
|
||||
Running optimization stage 2 on RAM2GS .......
|
||||
@N: CL159 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2-IntOsc.v":50:10:50:13|Input RCLK is unused.
|
||||
Running optimization stage 2 on REFB .......
|
||||
Running optimization stage 2 on EFB .......
|
||||
Running optimization stage 2 on VHI .......
|
||||
Running optimization stage 2 on ODDRXE .......
|
||||
Running optimization stage 2 on RPLL .......
|
||||
Running optimization stage 2 on EHXPLLJ .......
|
||||
Running optimization stage 2 on VLO .......
|
||||
Running optimization stage 2 on OSCH .......
|
||||
|
||||
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Sun Jul 14 22:31:08 2024
|
||||
|
||||
###########################################################]
|
||||
|
||||
Copyright (C) 1994-2018 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: N-2018.03L-SP1-1
|
||||
Install: C:\lscc\diamond\3.11_x64\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
File \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\impl1\synwork\layer0.srs changed - recompiling
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Sun Jul 14 22:31:08 2024
|
||||
|
||||
###########################################################]
|
||||
|
||||
For a summary of runtime and memory usage for all design units, please see file:
|
||||
==========================================================
|
||||
@L: A:\\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\impl1\synwork\RAM2GS_LCMXO2_1200HC_impl1_comp.rt.csv
|
||||
|
||||
@END
|
||||
|
||||
At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Sun Jul 14 22:31:08 2024
|
||||
|
||||
###########################################################]
|
||||
|
||||
Copyright (C) 1994-2018 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: N-2018.03L-SP1-1
|
||||
Install: C:\lscc\diamond\3.11_x64\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Database state : \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\impl1\synwork\|impl1
|
||||
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
File \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\impl1\synwork\RAM2GS_LCMXO2_1200HC_impl1_comp.srs changed - recompiling
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 68MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Sun Jul 14 22:31:10 2024
|
||||
|
||||
###########################################################]
|
||||
# Sun Jul 14 22:31:10 2024
|
||||
|
||||
|
||||
Copyright (C) 1994-2018 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: N-2018.03L-SP1-1
|
||||
Install: C:\lscc\diamond\3.11_x64\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
Synopsys Lattice Technology Pre-mapping, Version maplat2018q2p1, Build 055R, Built Apr 3 2019 09:51:54
|
||||
|
||||
|
||||
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
|
||||
|
||||
Reading constraint file: \\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS.sdc
|
||||
@N: MF284 |Setting synthesis effort to medium for the design
|
||||
@L: \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\impl1\RAM2GS_LCMXO2_1200HC_impl1_scck.rpt
|
||||
Printing clock summary report in "\\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\impl1\RAM2GS_LCMXO2_1200HC_impl1_scck.rpt" file
|
||||
@N: MF916 |Option synthesis_strategy=base is enabled.
|
||||
@N: MF248 |Running in 64-bit mode.
|
||||
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
|
||||
|
||||
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
|
||||
|
||||
|
||||
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
|
||||
|
||||
|
||||
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB)
|
||||
|
||||
|
||||
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
|
||||
|
||||
@N: MF284 |Setting synthesis effort to medium for the design
|
||||
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
|
||||
@N: MH105 |UMR3 is only supported for HAPS-80.
|
||||
@N: MH105 |UMR3 is only supported for HAPS-80.
|
||||
syn_allowed_resources : blockrams=7 set on top level netlist RAM2GS
|
||||
|
||||
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
|
||||
|
||||
|
||||
|
||||
Clock Summary
|
||||
******************
|
||||
|
||||
Start Requested Requested Clock Clock Clock
|
||||
Level Clock Frequency Period Type Group Load
|
||||
--------------------------------------------------------------------------------------------------------------
|
||||
0 - PHI2 2.9 MHz 350.000 declared default_clkgroup 20
|
||||
|
||||
0 - nCRAS 2.9 MHz 350.000 declared default_clkgroup 15
|
||||
|
||||
0 - nCCAS 2.9 MHz 350.000 declared default_clkgroup 10
|
||||
|
||||
0 - RCLK 62.5 MHz 16.000 declared default_clkgroup 0
|
||||
|
||||
0 - System 100.0 MHz 10.000 system system_clkgroup 0
|
||||
|
||||
0 - RPLL|CLKOP_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_0 65
|
||||
==============================================================================================================
|
||||
|
||||
|
||||
|
||||
Clock Load Summary
|
||||
***********************
|
||||
|
||||
Clock Source Clock Pin Non-clock Pin Non-clock Pin
|
||||
Clock Load Pin Seq Example Seq Example Comb Example
|
||||
------------------------------------------------------------------------------------------------------------------------------
|
||||
PHI2 20 PHI2(port) Bank[7:0].C PHI2r.D[0] un1_PHI2.I[0](inv)
|
||||
|
||||
nCRAS 15 nCRAS(port) CBR.C RASr.D[0] RASr_2.I[0](inv)
|
||||
|
||||
nCCAS 10 nCCAS(port) WRD[7:0].C CASr.D[0] CASr_2.I[0](inv)
|
||||
|
||||
RCLK 0 RCLK(port) - - -
|
||||
|
||||
System 0 - - - -
|
||||
|
||||
RPLL|CLKOP_inferred_clock 65 rpll.PLLInst_0.CLKOP(EHXPLLJ) CASr2.C - -
|
||||
==============================================================================================================================
|
||||
|
||||
@W: MT529 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2-intosc.v":174:4:174:9|Found inferred clock RPLL|CLKOP_inferred_clock which controls 65 sequential elements including RCKE. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
|
||||
|
||||
ICG Latch Removal Summary:
|
||||
Number of ICG latches removed: 0
|
||||
Number of ICG latches not removed: 0
|
||||
|
||||
|
||||
@S |Clock Optimization Summary
|
||||
|
||||
|
||||
|
||||
#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
|
||||
|
||||
3 non-gated/non-generated clock tree(s) driving 41 clock pin(s) of sequential element(s)
|
||||
1 gated/generated clock tree(s) driving 65 clock pin(s) of sequential element(s)
|
||||
0 instances converted, 65 sequential instances remain driven by gated/generated clocks
|
||||
|
||||
=========================== Non-Gated/Non-Generated Clocks ============================
|
||||
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
|
||||
---------------------------------------------------------------------------------------
|
||||
@KP:ckid0_1 PHI2 port 19 RA11
|
||||
@KP:ckid0_2 nCCAS port 8 WRD[7:0]
|
||||
@KP:ckid0_3 nCRAS port 14 RowA[9:0]
|
||||
=======================================================================================
|
||||
====================================================== Gated/Generated Clocks ======================================================
|
||||
Clock Tree ID Driving Element Drive Element Type Unconverted Fanout Sample Instance Explanation
|
||||
------------------------------------------------------------------------------------------------------------------------------------
|
||||
@KP:ckid0_0 rpll.PLLInst_0.CLKOP EHXPLLJ 65 RCKE Black box on clock path
|
||||
====================================================================================================================================
|
||||
|
||||
|
||||
##### END OF CLOCK OPTIMIZATION REPORT ######
|
||||
|
||||
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
|
||||
Finished Pre Mapping Phase.
|
||||
|
||||
Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
|
||||
|
||||
|
||||
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
|
||||
|
||||
None
|
||||
None
|
||||
|
||||
Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
|
||||
|
||||
Pre-mapping successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Sun Jul 14 22:31:10 2024
|
||||
|
||||
###########################################################]
|
||||
# Sun Jul 14 22:31:11 2024
|
||||
|
||||
|
||||
Copyright (C) 1994-2018 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: N-2018.03L-SP1-1
|
||||
Install: C:\lscc\diamond\3.11_x64\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
Synopsys Lattice Technology Mapper, Version maplat2018q2p1, Build 055R, Built Apr 3 2019 09:51:54
|
||||
|
||||
|
||||
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
|
||||
|
||||
@N: MF284 |Setting synthesis effort to medium for the design
|
||||
@N: MF916 |Option synthesis_strategy=base is enabled.
|
||||
@N: MF248 |Running in 64-bit mode.
|
||||
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
|
||||
|
||||
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
|
||||
|
||||
|
||||
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
|
||||
|
||||
|
||||
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
|
||||
|
||||
|
||||
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
|
||||
|
||||
@N: MF284 |Setting synthesis effort to medium for the design
|
||||
|
||||
|
||||
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
|
||||
|
||||
|
||||
Available hyper_sources - for debug and ip models
|
||||
None Found
|
||||
|
||||
|
||||
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
|
||||
|
||||
@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2-intosc.v":180:4:180:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0]
|
||||
@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2-intosc.v":167:4:167:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0]
|
||||
|
||||
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)
|
||||
|
||||
|
||||
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
|
||||
|
||||
|
||||
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB)
|
||||
|
||||
|
||||
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
|
||||
|
||||
|
||||
Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
|
||||
|
||||
|
||||
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
|
||||
|
||||
|
||||
Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
|
||||
|
||||
|
||||
Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 152MB)
|
||||
|
||||
Pass CPU time Worst Slack Luts / Registers
|
||||
------------------------------------------------------------
|
||||
1 0h:00m:00s 2.24ns 198 / 106
|
||||
|
||||
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 152MB)
|
||||
|
||||
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
|
||||
|
||||
Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 151MB peak: 152MB)
|
||||
|
||||
|
||||
Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 117MB peak: 152MB)
|
||||
|
||||
Writing Analyst data base \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\impl1\synwork\RAM2GS_LCMXO2_1200HC_impl1_m.srm
|
||||
|
||||
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 151MB peak: 153MB)
|
||||
|
||||
Writing EDIF Netlist and constraint files
|
||||
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\impl1\RAM2GS_LCMXO2_1200HC_impl1.edi
|
||||
N-2018.03L-SP1-1
|
||||
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
|
||||
|
||||
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 155MB peak: 157MB)
|
||||
|
||||
|
||||
Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 155MB peak: 157MB)
|
||||
|
||||
@W: MT246 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2-intosc.v":57:11:57:19|Blackbox ODDRXE is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
|
||||
@W: MT246 :"\\mac\icloud\repos\ram2gs\cpld\lcmxo2-1200hc-intosc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
|
||||
@W: MT246 :"\\mac\icloud\repos\ram2gs\cpld\lcmxo2-1200hc-intosc\rpll.v":64:12:64:20|Blackbox EHXPLLJ is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
|
||||
@N: MT615 |Found clock RCLK with period 16.00ns
|
||||
@N: MT615 |Found clock PHI2 with period 350.00ns
|
||||
@N: MT615 |Found clock nCRAS with period 350.00ns
|
||||
@N: MT615 |Found clock nCCAS with period 350.00ns
|
||||
@W: MT420 |Found inferred clock RPLL|CLKOP_inferred_clock with period 10.00ns. Please declare a user-defined clock on net rpll.PCLK.
|
||||
|
||||
|
||||
##### START OF TIMING REPORT #####[
|
||||
# Timing Report written on Sun Jul 14 22:31:13 2024
|
||||
#
|
||||
|
||||
|
||||
Top view: RAM2GS
|
||||
Requested Frequency: 2.9 MHz
|
||||
Wire load mode: top
|
||||
Paths requested: 5
|
||||
Constraint File(s): \\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS.sdc
|
||||
|
||||
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
|
||||
|
||||
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
|
||||
|
||||
|
||||
|
||||
Performance Summary
|
||||
*******************
|
||||
|
||||
|
||||
Worst slack in design: 3.291
|
||||
|
||||
@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching.
|
||||
Requested Estimated Requested Estimated Clock Clock
|
||||
Starting Clock Frequency Frequency Period Period Slack Type Group
|
||||
----------------------------------------------------------------------------------------------------------------------------------
|
||||
PHI2 2.9 MHz 69.1 MHz 350.000 14.481 167.760 declared default_clkgroup
|
||||
RCLK 62.5 MHz NA 16.000 NA NA declared default_clkgroup
|
||||
RPLL|CLKOP_inferred_clock 100.0 MHz 149.0 MHz 10.000 6.709 3.291 inferred Inferred_clkgroup_0
|
||||
nCCAS 2.9 MHz NA 350.000 NA NA declared default_clkgroup
|
||||
nCRAS 2.9 MHz NA 350.000 NA NA declared default_clkgroup
|
||||
System 100.0 MHz 388.0 MHz 10.000 2.577 7.423 system system_clkgroup
|
||||
==================================================================================================================================
|
||||
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Clock Relationships
|
||||
*******************
|
||||
|
||||
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
System System | 10.000 10.000 | No paths - | No paths - | No paths -
|
||||
System RPLL|CLKOP_inferred_clock | 10.000 7.423 | No paths - | No paths - | No paths -
|
||||
PHI2 PHI2 | No paths - | 350.000 347.124 | 175.000 167.760 | 175.000 173.428
|
||||
PHI2 RPLL|CLKOP_inferred_clock | No paths - | No paths - | No paths - | Diff grp -
|
||||
nCRAS RPLL|CLKOP_inferred_clock | No paths - | No paths - | No paths - | Diff grp -
|
||||
RPLL|CLKOP_inferred_clock System | 10.000 8.892 | No paths - | No paths - | No paths -
|
||||
RPLL|CLKOP_inferred_clock PHI2 | Diff grp - | No paths - | Diff grp - | No paths -
|
||||
RPLL|CLKOP_inferred_clock nCRAS | No paths - | No paths - | Diff grp - | No paths -
|
||||
RPLL|CLKOP_inferred_clock RPLL|CLKOP_inferred_clock | 10.000 3.291 | No paths - | No paths - | No paths -
|
||||
===================================================================================================================================================
|
||||
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
|
||||
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
|
||||
|
||||
|
||||
|
||||
Interface Information
|
||||
*********************
|
||||
|
||||
No IO constraint found
|
||||
|
||||
|
||||
|
||||
====================================
|
||||
Detailed Report for Clock: PHI2
|
||||
====================================
|
||||
|
||||
|
||||
|
||||
Starting Points with Worst Slack
|
||||
********************************
|
||||
|
||||
Starting Arrival
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
------------------------------------------------------------------------------------
|
||||
Bank_0io[0] PHI2 IFS1P3DX Q Bank[0] 0.972 167.760
|
||||
Bank_0io[1] PHI2 IFS1P3DX Q Bank[1] 0.972 167.760
|
||||
Bank_0io[2] PHI2 IFS1P3DX Q Bank[2] 0.972 167.760
|
||||
Bank_0io[3] PHI2 IFS1P3DX Q Bank[3] 0.972 167.760
|
||||
Bank_0io[4] PHI2 IFS1P3DX Q Bank[4] 0.972 167.760
|
||||
Bank_0io[5] PHI2 IFS1P3DX Q Bank[5] 0.972 167.760
|
||||
Bank_0io[6] PHI2 IFS1P3DX Q Bank[6] 0.972 167.760
|
||||
Bank_0io[7] PHI2 IFS1P3DX Q Bank[7] 0.972 167.760
|
||||
XOR8MEG PHI2 FD1P3AX Q XOR8MEG 1.044 173.428
|
||||
CmdEnable PHI2 FD1S3AX Q CmdEnable 1.180 347.124
|
||||
====================================================================================
|
||||
|
||||
|
||||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------------------------
|
||||
CmdEnable PHI2 FD1S3AX D CmdEnable_1 175.462 167.760
|
||||
CmdLEDEN PHI2 FD1P3AX SP XOR8MEG17 174.528 168.897
|
||||
CmdUFMShift PHI2 FD1P3AX SP XOR8MEG17 174.528 168.897
|
||||
CmdUFMWrite PHI2 FD1P3AX SP XOR8MEG17 174.528 168.897
|
||||
Cmdn8MEGEN PHI2 FD1P3AX SP XOR8MEG17 174.528 168.897
|
||||
XOR8MEG PHI2 FD1P3AX SP XOR8MEG17 174.528 168.897
|
||||
ADSubmitted PHI2 FD1S3AX D ADSubmitted_2 175.089 169.017
|
||||
C1Submitted PHI2 FD1S3AX D C1Submitted_1 175.089 169.017
|
||||
CmdValid PHI2 FD1S3AX D CmdValid_0 175.089 169.049
|
||||
CmdUFMData PHI2 FD1P3AX SP CmdUFMData_1_sqmuxa 174.528 169.505
|
||||
==============================================================================================
|
||||
|
||||
|
||||
|
||||
Worst Path Information
|
||||
***********************
|
||||
|
||||
|
||||
Path information for path number 1:
|
||||
Requested Period: 175.000
|
||||
- Setup time: -0.462
|
||||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
= Required time: 175.462
|
||||
|
||||
- Propagation time: 7.703
|
||||
- Clock delay at starting point: 0.000 (ideal)
|
||||
= Slack (non-critical) : 167.760
|
||||
|
||||
Number of logic level(s): 7
|
||||
Starting point: Bank_0io[0] / Q
|
||||
Ending point: CmdEnable / D
|
||||
The start point is clocked by PHI2 [rising] on pin SCLK
|
||||
The end point is clocked by PHI2 [falling] on pin CK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
---------------------------------------------------------------------------------
|
||||
Bank_0io[0] IFS1P3DX Q Out 0.972 0.972 -
|
||||
Bank[0] Net - - - - 1
|
||||
un1_Bank_1_4 ORCALUT4 A In 0.000 0.972 -
|
||||
un1_Bank_1_4 ORCALUT4 Z Out 1.153 2.125 -
|
||||
un1_Bank_1_4 Net - - - - 3
|
||||
C1WR_7 ORCALUT4 C In 0.000 2.125 -
|
||||
C1WR_7 ORCALUT4 Z Out 1.089 3.213 -
|
||||
C1WR_7 Net - - - - 2
|
||||
C1WR ORCALUT4 C In 0.000 3.213 -
|
||||
C1WR ORCALUT4 Z Out 1.089 4.302 -
|
||||
C1WR Net - - - - 2
|
||||
un1_ADWR ORCALUT4 B In 0.000 4.302 -
|
||||
un1_ADWR ORCALUT4 Z Out 1.153 5.455 -
|
||||
un1_ADWR Net - - - - 3
|
||||
un1_CMDWR ORCALUT4 B In 0.000 5.455 -
|
||||
un1_CMDWR ORCALUT4 Z Out 1.017 6.472 -
|
||||
un1_CMDWR Net - - - - 1
|
||||
CmdEnable_1_am ORCALUT4 C In 0.000 6.472 -
|
||||
CmdEnable_1_am ORCALUT4 Z Out 1.017 7.489 -
|
||||
CmdEnable_1_am Net - - - - 1
|
||||
CmdEnable_1 PFUMX BLUT In 0.000 7.489 -
|
||||
CmdEnable_1 PFUMX Z Out 0.214 7.703 -
|
||||
CmdEnable_1 Net - - - - 1
|
||||
CmdEnable FD1S3AX D In 0.000 7.703 -
|
||||
=================================================================================
|
||||
|
||||
|
||||
|
||||
|
||||
====================================
|
||||
Detailed Report for Clock: RPLL|CLKOP_inferred_clock
|
||||
====================================
|
||||
|
||||
|
||||
|
||||
Starting Points with Worst Slack
|
||||
********************************
|
||||
|
||||
Starting Arrival
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
-----------------------------------------------------------------------------------------------
|
||||
InitReady RPLL|CLKOP_inferred_clock FD1S3AX Q InitReady 1.326 3.291
|
||||
FS[15] RPLL|CLKOP_inferred_clock FD1S3AX Q FS[15] 1.188 3.429
|
||||
FS[16] RPLL|CLKOP_inferred_clock FD1S3AX Q FS[16] 1.188 3.429
|
||||
FS[17] RPLL|CLKOP_inferred_clock FD1S3AX Q FS[17] 1.188 3.429
|
||||
FS[13] RPLL|CLKOP_inferred_clock FD1S3AX Q FS[13] 1.276 3.777
|
||||
FS[9] RPLL|CLKOP_inferred_clock FD1S3AX Q FS[9] 1.268 3.785
|
||||
FS[10] RPLL|CLKOP_inferred_clock FD1S3AX Q FS[10] 1.268 3.785
|
||||
FS[14] RPLL|CLKOP_inferred_clock FD1S3AX Q FS[14] 1.260 3.793
|
||||
FS[12] RPLL|CLKOP_inferred_clock FD1S3AX Q FS[12] 1.284 4.049
|
||||
FS[11] RPLL|CLKOP_inferred_clock FD1S3AX Q FS[11] 1.272 4.061
|
||||
===============================================================================================
|
||||
|
||||
|
||||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------------------------------
|
||||
wb_dati[2] RPLL|CLKOP_inferred_clock FD1P3AX D wb_dati_5[2] 10.089 3.291
|
||||
wb_dati[4] RPLL|CLKOP_inferred_clock FD1P3AX D wb_dati_5[4] 10.089 3.291
|
||||
wb_dati[5] RPLL|CLKOP_inferred_clock FD1P3AX D wb_dati_5[5] 10.089 3.291
|
||||
wb_dati[7] RPLL|CLKOP_inferred_clock FD1P3AX D wb_dati_5[7] 10.089 3.291
|
||||
wb_dati[3] RPLL|CLKOP_inferred_clock FD1P3AX D wb_dati_5[3] 10.089 3.395
|
||||
wb_dati[6] RPLL|CLKOP_inferred_clock FD1P3AX D wb_dati_5[6] 10.089 3.395
|
||||
wb_dati[1] RPLL|CLKOP_inferred_clock FD1P3AX D wb_dati_5[1] 10.089 4.483
|
||||
FS[17] RPLL|CLKOP_inferred_clock FD1S3AX D FS_s[17] 9.894 4.551
|
||||
LEDEN RPLL|CLKOP_inferred_clock FD1P3AX SP N_63 9.528 4.604
|
||||
n8MEGEN RPLL|CLKOP_inferred_clock FD1P3AX SP N_63 9.528 4.604
|
||||
====================================================================================================
|
||||
|
||||
|
||||
|
||||
Worst Path Information
|
||||
***********************
|
||||
|
||||
|
||||
Path information for path number 1:
|
||||
Requested Period: 10.000
|
||||
- Setup time: -0.089
|
||||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
= Required time: 10.089
|
||||
|
||||
- Propagation time: 6.798
|
||||
- Clock delay at starting point: 0.000 (ideal)
|
||||
= Slack (critical) : 3.291
|
||||
|
||||
Number of logic level(s): 5
|
||||
Starting point: InitReady / Q
|
||||
Ending point: wb_dati[2] / D
|
||||
The start point is clocked by RPLL|CLKOP_inferred_clock [rising] on pin CK
|
||||
The end point is clocked by RPLL|CLKOP_inferred_clock [rising] on pin CK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
--------------------------------------------------------------------------------------------
|
||||
InitReady FD1S3AX Q Out 1.326 1.326 -
|
||||
InitReady Net - - - - 35
|
||||
wb_adr_cnst_sn.m2_i_o3 ORCALUT4 B In 0.000 1.326 -
|
||||
wb_adr_cnst_sn.m2_i_o3 ORCALUT4 Z Out 1.317 2.643 -
|
||||
N_242 Net - - - - 18
|
||||
FS_RNI7U6M[14] ORCALUT4 B In 0.000 2.643 -
|
||||
FS_RNI7U6M[14] ORCALUT4 Z Out 1.193 3.836 -
|
||||
N_134 Net - - - - 4
|
||||
un1_FS_26_1_0_a2_RNI761E1 ORCALUT4 C In 0.000 3.836 -
|
||||
un1_FS_26_1_0_a2_RNI761E1 ORCALUT4 Z Out 1.153 4.989 -
|
||||
wb_adr_21_sqmuxa_s9 Net - - - - 3
|
||||
FS_RNIFUUT2[9] ORCALUT4 C In 0.000 4.989 -
|
||||
FS_RNIFUUT2[9] ORCALUT4 Z Out 1.193 6.181 -
|
||||
N_194 Net - - - - 4
|
||||
wb_dati_5_1_iv[2] ORCALUT4 B In 0.000 6.181 -
|
||||
wb_dati_5_1_iv[2] ORCALUT4 Z Out 0.617 6.798 -
|
||||
wb_dati_5[2] Net - - - - 1
|
||||
wb_dati[2] FD1P3AX D In 0.000 6.798 -
|
||||
============================================================================================
|
||||
|
||||
|
||||
|
||||
|
||||
====================================
|
||||
Detailed Report for Clock: System
|
||||
====================================
|
||||
|
||||
|
||||
|
||||
Starting Points with Worst Slack
|
||||
********************************
|
||||
|
||||
Starting Arrival
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
-----------------------------------------------------------------------------------------
|
||||
ufmefb.EFBInst_0 System EFB WBACKO wb_ack 0.000 7.423
|
||||
ufmefb.EFBInst_0 System EFB WBDATO0 wb_dato[0] 0.000 9.472
|
||||
ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000 9.472
|
||||
OSCH_inst System OSCH OSC ICLK 0.000 10.000
|
||||
=========================================================================================
|
||||
|
||||
|
||||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
---------------------------------------------------------------------------------------
|
||||
LEDEN System FD1P3AX SP N_63 9.528 7.423
|
||||
n8MEGEN System FD1P3AX SP N_63 9.528 7.423
|
||||
wb_cyc_stb System FD1P3IX SP N_51 9.528 8.912
|
||||
LEDEN System FD1P3AX D LEDEN_6 10.089 9.472
|
||||
n8MEGEN System FD1P3AX D n8MEGEN_6 10.089 9.472
|
||||
rpll.PLLInst_0 System EHXPLLJ CLKI ICLK 10.000 10.000
|
||||
=======================================================================================
|
||||
|
||||
|
||||
|
||||
Worst Path Information
|
||||
***********************
|
||||
|
||||
|
||||
Path information for path number 1:
|
||||
Requested Period: 10.000
|
||||
- Setup time: 0.472
|
||||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
= Required time: 9.528
|
||||
|
||||
- Propagation time: 2.106
|
||||
- Clock delay at starting point: 0.000 (ideal)
|
||||
- Estimated clock delay at start point: -0.000
|
||||
= Slack (non-critical) : 7.423
|
||||
|
||||
Number of logic level(s): 2
|
||||
Starting point: ufmefb.EFBInst_0 / WBACKO
|
||||
Ending point: LEDEN / SP
|
||||
The start point is clocked by System [rising]
|
||||
The end point is clocked by RPLL|CLKOP_inferred_clock [rising] on pin CK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
-------------------------------------------------------------------------------------
|
||||
ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 -
|
||||
wb_ack Net - - - - 2
|
||||
un1_FS_38_i_a3_0 ORCALUT4 B In 0.000 0.000 -
|
||||
un1_FS_38_i_a3_0 ORCALUT4 Z Out 1.017 1.017 -
|
||||
un1_FS_38_i_a3_0 Net - - - - 1
|
||||
un1_FS_38_i_0 ORCALUT4 C In 0.000 1.017 -
|
||||
un1_FS_38_i_0 ORCALUT4 Z Out 1.089 2.106 -
|
||||
N_63 Net - - - - 2
|
||||
LEDEN FD1P3AX SP In 0.000 2.106 -
|
||||
=====================================================================================
|
||||
|
||||
|
||||
|
||||
##### END OF TIMING REPORT #####]
|
||||
|
||||
Timing exceptions that could not be applied
|
||||
None
|
||||
|
||||
Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 155MB peak: 157MB)
|
||||
|
||||
|
||||
Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 155MB peak: 157MB)
|
||||
|
||||
---------------------------------------
|
||||
Resource Usage Report
|
||||
Part: lcmxo2_1200hc-4
|
||||
|
||||
Register bits: 106 of 1280 (8%)
|
||||
PIC Latch: 0
|
||||
I/O cells: 63
|
||||
|
||||
|
||||
Details:
|
||||
BB: 8
|
||||
CCU2D: 10
|
||||
EFB: 1
|
||||
EHXPLLJ: 1
|
||||
FD1P3AX: 28
|
||||
FD1P3IX: 3
|
||||
FD1S3AX: 37
|
||||
FD1S3IX: 3
|
||||
GSR: 1
|
||||
IB: 24
|
||||
IFS1P3DX: 9
|
||||
IFS1P3IX: 10
|
||||
IFS1P3JX: 2
|
||||
INV: 7
|
||||
OB: 31
|
||||
ODDRXE: 1
|
||||
OFS1P3BX: 4
|
||||
OFS1P3DX: 8
|
||||
OFS1P3IX: 1
|
||||
OFS1P3JX: 1
|
||||
ORCALUT4: 186
|
||||
OSCH: 1
|
||||
PFUMX: 2
|
||||
PUR: 1
|
||||
VHI: 2
|
||||
VLO: 3
|
||||
true: 1
|
||||
Mapper successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 33MB peak: 157MB)
|
||||
|
||||
Process took 0h:00m:02s realtime, 0h:00m:02s cputime
|
||||
# Sun Jul 14 22:31:13 2024
|
||||
|
||||
###########################################################]
|
||||
@ -0,0 +1,152 @@
|
||||
<HTML>
|
||||
<HEAD><TITLE>Bitgen Report</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
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table
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border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
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font-weight:bold;
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border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
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.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Bgn"></A>BITGEN: Bitstream Generator Diamond (64-bit) 3.11.3.469
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Sun Jul 14 22:29:59 2024
|
||||
|
||||
|
||||
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC-IntOsc -w -jedec -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC-IntOsc/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
|
||||
|
||||
Loading design for application Bitgen from file RAM2GS_LCMXO2_1200HC_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-1200HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application Bitgen from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.11_x64/ispfpga.
|
||||
Package Status: Final Version 1.42.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
|
||||
Running DRC.
|
||||
DRC detected 0 errors and 0 warnings.
|
||||
Reading Preference File from RAM2GS_LCMXO2_1200HC_impl1.prf.
|
||||
|
||||
<A name="bgn_ps"></A>
|
||||
<B><U><big>Preference Summary:</big></U></B>
|
||||
|
||||
+---------------------------------+---------------------------------+
|
||||
| Preference | Current Setting |
|
||||
+---------------------------------+---------------------------------+
|
||||
| RamCfg | Reset** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MCCLK_FREQ | 2.08** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| CONFIG_SECURE | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| INBUF | ON** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| JTAG_PORT | ENABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SDM_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SLAVE_SPI_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MASTER_SPI_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| I2C_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MUX_CONFIGURATION_PORTS | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| CONFIGURATION | CFG** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| COMPRESS_CONFIG | ON** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MY_ASSP | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| ONE_TIME_PROGRAM | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| ENABLE_TRANSFR | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SHAREDEBRINIT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| BACKGROUND_RECONFIG | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
* Default setting.
|
||||
** The specified setting matches the default setting.
|
||||
|
||||
|
||||
Creating bit map...
|
||||
|
||||
Bitstream Status: Final Version 1.95.
|
||||
|
||||
Saving bit stream in "RAM2GS_LCMXO2_1200HC_impl1.jed".
|
||||
|
||||
===========
|
||||
UFM Summary.
|
||||
===========
|
||||
UFM Size: 511 Pages (128*511 Bits).
|
||||
UFM Utilization: General Purpose Flash Memory.
|
||||
|
||||
Available General Purpose Flash Memory: 511 Pages (Page 0 to Page 510).
|
||||
Initialized UFM Pages: 321 Pages (Page 190 to Page 510).
|
||||
|
||||
Total CPU Time: 3 secs
|
||||
Total REAL Time: 3 secs
|
||||
Peak Memory Usage: 275 MB
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
@ -0,0 +1,148 @@
|
||||
|
||||
Copyright (C) 1994-2018 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: N-2018.03L-SP1-1
|
||||
Install: C:\lscc\diamond\3.11_x64\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
|
||||
# Written on Sun Jul 14 22:31:10 2024
|
||||
|
||||
##### DESIGN INFO #######################################################
|
||||
|
||||
Top View: "RAM2GS"
|
||||
Constraint File(s): "\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS.sdc"
|
||||
|
||||
|
||||
|
||||
|
||||
##### SUMMARY ############################################################
|
||||
|
||||
Found 0 issues in 0 out of 4 constraints
|
||||
|
||||
|
||||
##### DETAILS ############################################################
|
||||
|
||||
|
||||
|
||||
Clock Relationships
|
||||
*******************
|
||||
|
||||
Starting Ending | rise to rise | fall to fall | rise to fall | fall to rise
|
||||
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
System System | 10.000 | No paths | No paths | No paths
|
||||
System RPLL|CLKOP_inferred_clock | 10.000 | No paths | No paths | No paths
|
||||
PHI2 PHI2 | No paths | 350.000 | 175.000 | 175.000
|
||||
PHI2 RPLL|CLKOP_inferred_clock | No paths | No paths | No paths | Diff grp
|
||||
nCRAS RPLL|CLKOP_inferred_clock | No paths | No paths | No paths | Diff grp
|
||||
RPLL|CLKOP_inferred_clock System | 10.000 | No paths | No paths | No paths
|
||||
RPLL|CLKOP_inferred_clock PHI2 | Diff grp | No paths | Diff grp | No paths
|
||||
RPLL|CLKOP_inferred_clock nCRAS | No paths | No paths | Diff grp | No paths
|
||||
RPLL|CLKOP_inferred_clock RPLL|CLKOP_inferred_clock | 10.000 | No paths | No paths | No paths
|
||||
=======================================================================================================================================================================
|
||||
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
|
||||
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
|
||||
|
||||
|
||||
Unconstrained Start/End Points
|
||||
******************************
|
||||
|
||||
p:CROW[0]
|
||||
p:CROW[1]
|
||||
p:Din[0]
|
||||
p:Din[1]
|
||||
p:Din[2]
|
||||
p:Din[3]
|
||||
p:Din[4]
|
||||
p:Din[5]
|
||||
p:Din[6]
|
||||
p:Din[7]
|
||||
p:Dout[0]
|
||||
p:Dout[1]
|
||||
p:Dout[2]
|
||||
p:Dout[3]
|
||||
p:Dout[4]
|
||||
p:Dout[5]
|
||||
p:Dout[6]
|
||||
p:Dout[7]
|
||||
p:MAin[0]
|
||||
p:MAin[1]
|
||||
p:MAin[2]
|
||||
p:MAin[3]
|
||||
p:MAin[4]
|
||||
p:MAin[5]
|
||||
p:MAin[6]
|
||||
p:MAin[7]
|
||||
p:MAin[8]
|
||||
p:MAin[9]
|
||||
p:RA[0]
|
||||
p:RA[1]
|
||||
p:RA[2]
|
||||
p:RA[3]
|
||||
p:RA[4]
|
||||
p:RA[5]
|
||||
p:RA[6]
|
||||
p:RA[7]
|
||||
p:RA[8]
|
||||
p:RA[9]
|
||||
p:RA[10]
|
||||
p:RA[11]
|
||||
p:RBA[0]
|
||||
p:RBA[1]
|
||||
p:RCKE
|
||||
p:RCLKout
|
||||
p:RDQMH
|
||||
p:RDQML
|
||||
p:RD[0] (bidir end point)
|
||||
p:RD[0] (bidir start point)
|
||||
p:RD[1] (bidir end point)
|
||||
p:RD[1] (bidir start point)
|
||||
p:RD[2] (bidir end point)
|
||||
p:RD[2] (bidir start point)
|
||||
p:RD[3] (bidir end point)
|
||||
p:RD[3] (bidir start point)
|
||||
p:RD[4] (bidir end point)
|
||||
p:RD[4] (bidir start point)
|
||||
p:RD[5] (bidir end point)
|
||||
p:RD[5] (bidir start point)
|
||||
p:RD[6] (bidir end point)
|
||||
p:RD[6] (bidir start point)
|
||||
p:RD[7] (bidir end point)
|
||||
p:RD[7] (bidir start point)
|
||||
p:nFWE
|
||||
p:nRCAS
|
||||
p:nRCS
|
||||
p:nRRAS
|
||||
p:nRWE
|
||||
|
||||
|
||||
Inapplicable constraints
|
||||
************************
|
||||
|
||||
(none)
|
||||
|
||||
|
||||
Applicable constraints with issues
|
||||
**********************************
|
||||
|
||||
(none)
|
||||
|
||||
|
||||
Constraints with matching wildcard expressions
|
||||
**********************************************
|
||||
|
||||
(none)
|
||||
|
||||
|
||||
Library Report
|
||||
**************
|
||||
|
||||
|
||||
# End of Constraint Checker Report
|
||||
@ -0,0 +1,603 @@
|
||||
<HTML>
|
||||
<HEAD><TITLE>Project Summary</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Mrp"></A>
|
||||
Lattice Mapping Report File for Design Module 'RAM2GS'
|
||||
|
||||
|
||||
|
||||
<A name="mrp_di"></A><B><U><big>Design Information</big></U></B>
|
||||
|
||||
Command line: map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 4 -oc Commercial
|
||||
RAM2GS_LCMXO2_1200HC_impl1.ngd -o RAM2GS_LCMXO2_1200HC_impl1_map.ncd -pr
|
||||
RAM2GS_LCMXO2_1200HC_impl1.prf -mp RAM2GS_LCMXO2_1200HC_impl1.mrp -lpf //Ma
|
||||
c/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_LCMXO2_1200HC_
|
||||
impl1_synplify.lpf -lpf //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.lpf -c
|
||||
0 -gui -msgset
|
||||
//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC-IntOsc/promote.xml
|
||||
Target Vendor: LATTICE
|
||||
Target Device: LCMXO2-1200HCTQFP100
|
||||
Target Performance: 4
|
||||
Mapper: xo2c00, version: Diamond (64-bit) 3.11.3.469
|
||||
Mapped on: 07/14/24 22:31:15
|
||||
|
||||
|
||||
<A name="mrp_ds"></A><B><U><big>Design Summary</big></U></B>
|
||||
Number of registers: 106 out of 1520 (7%)
|
||||
PFU registers: 71 out of 1280 (6%)
|
||||
PIO registers: 35 out of 240 (15%)
|
||||
Number of SLICEs: 106 out of 640 (17%)
|
||||
SLICEs as Logic/ROM: 106 out of 640 (17%)
|
||||
SLICEs as RAM: 0 out of 480 (0%)
|
||||
SLICEs as Carry: 10 out of 640 (2%)
|
||||
Number of LUT4s: 210 out of 1280 (16%)
|
||||
Number used as logic LUTs: 190
|
||||
Number used as distributed RAM: 0
|
||||
Number used as ripple logic: 20
|
||||
Number used as shift registers: 0
|
||||
Number of PIO sites used: 63 + 4(JTAG) out of 80 (84%)
|
||||
Number of IDDR/ODDR/TDDR cells used: 1 out of 240 (0%)
|
||||
Number of IDDR cells: 0
|
||||
Number of ODDR cells: 1
|
||||
Number of TDDR cells: 0
|
||||
Number of PIO using at least one IDDR/ODDR/TDDR: 1 (0 differential)
|
||||
Number of PIO using IDDR only: 0 (0 differential)
|
||||
Number of PIO using ODDR only: 1 (0 differential)
|
||||
Number of PIO using TDDR only: 0 (0 differential)
|
||||
Number of PIO using IDDR/ODDR: 0 (0 differential)
|
||||
Number of PIO using IDDR/TDDR: 0 (0 differential)
|
||||
Number of PIO using ODDR/TDDR: 0 (0 differential)
|
||||
Number of PIO using IDDR/ODDR/TDDR: 0 (0 differential)
|
||||
Number of block RAMs: 0 out of 7 (0%)
|
||||
Number of GSRs: 0 out of 1 (0%)
|
||||
EFB used : Yes
|
||||
JTAG used : No
|
||||
Readback used : No
|
||||
Oscillator used : Yes
|
||||
Startup used : No
|
||||
POR : On
|
||||
Bandgap : On
|
||||
Number of Power Controller: 0 out of 1 (0%)
|
||||
Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
|
||||
Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%)
|
||||
Number of DCCA: 0 out of 8 (0%)
|
||||
Number of DCMA: 0 out of 2 (0%)
|
||||
|
||||
Number of PLLs: 1 out of 1 (100%)
|
||||
Number of DQSDLLs: 0 out of 2 (0%)
|
||||
Number of CLKDIVC: 0 out of 4 (0%)
|
||||
Number of ECLKSYNCA: 0 out of 4 (0%)
|
||||
Number of ECLKBRIDGECS: 0 out of 2 (0%)
|
||||
Notes:-
|
||||
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
|
||||
distributed RAMs) + 2*(Number of ripple logic)
|
||||
2. Number of logic LUT4s does not include count of distributed RAM and
|
||||
ripple logic.
|
||||
Number of clocks: 5
|
||||
Net ICLK: 1 loads, 1 rising, 0 falling (Driver: OSCH_inst )
|
||||
Net PHI2_c: 19 loads, 9 rising, 10 falling (Driver: PIO PHI2 )
|
||||
Net PCLK: 48 loads, 48 rising, 0 falling (Driver: rpll/PLLInst_0 )
|
||||
Net nCRAS_c: 14 loads, 0 rising, 14 falling (Driver: PIO nCRAS )
|
||||
Net nCCAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCCAS )
|
||||
Number of Clock Enables: 7
|
||||
Net N_51: 1 loads, 1 LSLICEs
|
||||
Net XOR8MEG17: 5 loads, 5 LSLICEs
|
||||
Net N_94_i: 2 loads, 2 LSLICEs
|
||||
Net CmdUFMData_1_sqmuxa: 1 loads, 1 LSLICEs
|
||||
Net N_239_i: 10 loads, 10 LSLICEs
|
||||
Net N_63: 2 loads, 2 LSLICEs
|
||||
Net N_258_i: 2 loads, 2 LSLICEs
|
||||
Number of LSRs: 6
|
||||
Net RA10s_i: 1 loads, 0 LSLICEs
|
||||
Net wb_rst7: 3 loads, 3 LSLICEs
|
||||
Net wb_rst: 1 loads, 0 LSLICEs
|
||||
Net Ready: 13 loads, 0 LSLICEs
|
||||
Net nRRAS_0_sqmuxa: 1 loads, 1 LSLICEs
|
||||
Net RASr2: 1 loads, 1 LSLICEs
|
||||
Number of nets driven by tri-state buffers: 0
|
||||
Top 10 highest fanout non-clock nets:
|
||||
Net InitReady: 35 loads
|
||||
Net Ready: 27 loads
|
||||
Net FS[12]: 21 loads
|
||||
Net FS[13]: 19 loads
|
||||
Net FS[11]: 18 loads
|
||||
Net N_242: 18 loads
|
||||
Net FS[10]: 17 loads
|
||||
Net FS[14]: 17 loads
|
||||
Net FS[9]: 17 loads
|
||||
Net S[0]: 12 loads
|
||||
|
||||
|
||||
|
||||
|
||||
Number of warnings: 4
|
||||
Number of errors: 0
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<A name="mrp_dwe"></A><B><U><big>Design Errors/Warnings</big></U></B>
|
||||
|
||||
WARNING - map: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC-IntOsc/impl1/RAM2GS_
|
||||
LCMXO2_1200HC_impl1_synplify.lpf(9): Semantic error in "FREQUENCY PORT
|
||||
|
||||
"RCLK" 62.500000 MHz ;": "RCLK" matches no ports in the design. This
|
||||
preference has been disabled.
|
||||
WARNING - map: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.lpf(68): Semantic
|
||||
error in "IOBUF PORT "RCLK" IO_TYPE=LVCMOS33 PULLMODE=NONE ;": Port "RCLK"
|
||||
does not exist in the design. This preference has been disabled.
|
||||
WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
||||
temporarily disable certain features of the device including Power
|
||||
Controller, GSR, Hardened User SPI Port, Hardened Primary User I2C Port.
|
||||
Functionality is restored after the Flash Memory (UFM/Configuration)
|
||||
Interface is disabled using Disable Configuration Interface command 0x26
|
||||
followed by Bypass command 0xFF.
|
||||
WARNING - map: IO buffer missing for top level port RCLK...logic will be
|
||||
discarded.
|
||||
|
||||
|
||||
|
||||
<A name="mrp_ioa"></A><B><U><big>IO (PIO) Attributes</big></U></B>
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| IO Name | Direction | Levelmode | IO |
|
||||
| | | IO_TYPE | Register |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[0] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[0] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| PHI2 | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RDQML | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RDQMH | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRCAS | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRRAS | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRWE | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RCKE | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RCLKout | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRCS | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[7] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[6] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[5] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[4] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[3] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[2] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[1] | BIDIR | LVCMOS33 | OUT |
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[11] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[10] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[9] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[8] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[7] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[6] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[5] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[4] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[3] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[2] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[1] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[0] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RBA[1] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RBA[0] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| LED | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nFWE | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nCRAS | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nCCAS | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[7] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[6] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[5] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[4] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[3] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[2] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[1] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[7] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[6] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[5] | INPUT | LVCMOS33 | IN |
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[4] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[3] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[2] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[1] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[0] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| CROW[1] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| CROW[0] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[9] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[8] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[7] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[6] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[5] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[4] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[3] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[2] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[1] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[0] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
|
||||
|
||||
<A name="mrp_rm"></A><B><U><big>Removed logic</big></U></B>
|
||||
|
||||
Block GSR_INST undriven or does not drive anything - clipped.
|
||||
Signal nCRAS_c_i was merged into signal nCRAS_c
|
||||
Signal RASr2_i was merged into signal RASr2
|
||||
Signal Ready_i was merged into signal Ready
|
||||
Signal XOR8MEG.CN was merged into signal PHI2_c
|
||||
Signal rpll/GND undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/VCC undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/GND undriven or does not drive anything - clipped.
|
||||
Signal FS_s_0_S1[17] undriven or does not drive anything - clipped.
|
||||
Signal FS_s_0_COUT[17] undriven or does not drive anything - clipped.
|
||||
Signal rpll/CLKINTFB undriven or does not drive anything - clipped.
|
||||
Signal rpll/DPHSRC undriven or does not drive anything - clipped.
|
||||
Signal rpll/PLLACK undriven or does not drive anything - clipped.
|
||||
Signal rpll/PLLDATO0 undriven or does not drive anything - clipped.
|
||||
Signal rpll/PLLDATO1 undriven or does not drive anything - clipped.
|
||||
Signal rpll/PLLDATO2 undriven or does not drive anything - clipped.
|
||||
Signal rpll/PLLDATO3 undriven or does not drive anything - clipped.
|
||||
|
||||
Signal rpll/PLLDATO4 undriven or does not drive anything - clipped.
|
||||
Signal rpll/PLLDATO5 undriven or does not drive anything - clipped.
|
||||
Signal rpll/PLLDATO6 undriven or does not drive anything - clipped.
|
||||
Signal rpll/PLLDATO7 undriven or does not drive anything - clipped.
|
||||
Signal rpll/REFCLK undriven or does not drive anything - clipped.
|
||||
Signal rpll/INTLOCK undriven or does not drive anything - clipped.
|
||||
Signal rpll/LOCK undriven or does not drive anything - clipped.
|
||||
Signal rpll/CLKOS3 undriven or does not drive anything - clipped.
|
||||
Signal rpll/CLKOS2 undriven or does not drive anything - clipped.
|
||||
Signal rpll/CLKOS undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/CFGWAKE undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wbc_ufm_irq undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/TCOC undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/TCINT undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIIRQO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPICSNEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMOSIEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMOSIO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMISOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMISOO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPISCKEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPISCKO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SDAOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SCLOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SDAOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SCLOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO0_0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO1_0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO2_0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO3_0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO4_0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO5_0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO6_0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO7_0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO4 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLWEO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLL1STBO undriven or does not drive anything - clipped.
|
||||
|
||||
Signal ufmefb/PLL0STBO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLRSTO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLCLKO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wb_dat_o_1[2] undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wb_dat_o_1[3] undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wb_dat_o_1[4] undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wb_dat_o_1[5] undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wb_dat_o_1[6] undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wb_dat_o_1[7] undriven or does not drive anything - clipped.
|
||||
Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped.
|
||||
Signal N_1 undriven or does not drive anything - clipped.
|
||||
Signal OSCH_inst_SEDSTDBY undriven or does not drive anything - clipped.
|
||||
Block nCRAS_pad_RNIBPVB was optimized away.
|
||||
Block RASr2_RNIAFR1 was optimized away.
|
||||
Block Ready_RNILCP9 was optimized away.
|
||||
Block C1Submitted.CN was optimized away.
|
||||
Block rpll/GND was optimized away.
|
||||
Block ufmefb/VCC was optimized away.
|
||||
Block ufmefb/GND was optimized away.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<A name="mrp_pll"></A><B><U><big>PLL/DLL Summary</big></U></B>
|
||||
---------------
|
||||
|
||||
PLL 1: Pin/Node Value
|
||||
PLL Instance Name: rpll/PLLInst_0
|
||||
PLL Type: EHXPLLJ
|
||||
Input Clock: NODE ICLK
|
||||
Output Clock(P): NODE PCLK
|
||||
Output Clock(S): NONE
|
||||
Output Clock(S2): NONE
|
||||
Output Clock(S3): NONE
|
||||
Feedback Signal: NODE PCLK
|
||||
Reset Signal: NONE
|
||||
M Divider Reset Signal: NONE
|
||||
C Divider Reset Signal: NONE
|
||||
D Divider Reset Signal: NONE
|
||||
Standby Signal: NONE
|
||||
PLL LOCK signal: NONE
|
||||
PLL Data bus CLK Signal: NONE
|
||||
PLL Data bus Strobe Signal: NONE
|
||||
PLL Data bus Reset Signal: NONE
|
||||
PLL Data bus Write Enable Signal: NONE
|
||||
PLL Data bus Address0: NONE
|
||||
PLL Data bus Address1: NONE
|
||||
PLL Data bus Address2: NONE
|
||||
PLL Data bus Address3: NONE
|
||||
PLL Data bus Address4: NONE
|
||||
PLL Data In bus Data0: NONE
|
||||
PLL Data In bus Data1: NONE
|
||||
PLL Data In bus Data2: NONE
|
||||
PLL Data In bus Data3: NONE
|
||||
PLL Data In bus Data4: NONE
|
||||
PLL Data In bus Data5: NONE
|
||||
PLL Data In bus Data6: NONE
|
||||
|
||||
PLL Data In bus Data7: NONE
|
||||
PLL Data bus Acknowledge: NONE
|
||||
PLL Data Out bus Data0: NONE
|
||||
PLL Data Out bus Data1: NONE
|
||||
PLL Data Out bus Data2: NONE
|
||||
PLL Data Out bus Data3: NONE
|
||||
PLL Data Out bus Data4: NONE
|
||||
PLL Data Out bus Data5: NONE
|
||||
PLL Data Out bus Data6: NONE
|
||||
PLL Data Out bus Data7: NONE
|
||||
Input Clock Frequency (MHz): 133.0000
|
||||
Output Clock(P) Frequency (MHz): 61.3846
|
||||
Output Clock(S) Frequency (MHz): NA
|
||||
Output Clock(S2) Frequency (MHz): NA
|
||||
Output Clock(S3) Frequency (MHz): NA
|
||||
CLKOP Post Divider A Input: DIVA
|
||||
CLKOS Post Divider B Input: DIVB
|
||||
CLKOS2 Post Divider C Input: DIVC
|
||||
CLKOS3 Post Divider D Input: DIVD
|
||||
Pre Divider A Input: VCO_PHASE
|
||||
Pre Divider B Input: VCO_PHASE
|
||||
Pre Divider C Input: VCO_PHASE
|
||||
Pre Divider D Input: VCO_PHASE
|
||||
VCO Bypass A Input: VCO_PHASE
|
||||
VCO Bypass B Input: VCO_PHASE
|
||||
VCO Bypass C Input: VCO_PHASE
|
||||
VCO Bypass D Input: VCO_PHASE
|
||||
FB_MODE: CLKOP
|
||||
CLKI Divider: 13
|
||||
CLKFB Divider: 6
|
||||
CLKOP Divider: 8
|
||||
CLKOS Divider: 1
|
||||
CLKOS2 Divider: 1
|
||||
CLKOS3 Divider: 1
|
||||
Fractional N Divider: 0
|
||||
CLKOP Desired Phase Shift(degree): 0
|
||||
CLKOP Trim Option Rising/Falling: RISING
|
||||
CLKOP Trim Option Delay: 0
|
||||
CLKOS Desired Phase Shift(degree): 0
|
||||
CLKOS Trim Option Rising/Falling: FALLING
|
||||
CLKOS Trim Option Delay: 0
|
||||
CLKOS2 Desired Phase Shift(degree): 0
|
||||
CLKOS3 Desired Phase Shift(degree): 0
|
||||
|
||||
OSC Summary
|
||||
-----------
|
||||
|
||||
OSC 1: Pin/Node Value
|
||||
OSC Instance Name: OSCH_inst
|
||||
OSC Type: OSCH
|
||||
STDBY Input: NONE
|
||||
OSC Output: NODE ICLK
|
||||
OSC Nominal Frequency (MHz): 133.00
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<A name="mrp_efb"></A><B><U><big>Embedded Functional Block Connection Summary</big></U></B>
|
||||
|
||||
Desired WISHBONE clock frequency: 66.7 MHz
|
||||
Clock source: PCLK
|
||||
Reset source: wb_rst
|
||||
Functions mode:
|
||||
I2C #1 (Primary) Function: DISABLED
|
||||
I2C #2 (Secondary) Function: DISABLED
|
||||
SPI Function: DISABLED
|
||||
Timer/Counter Function: DISABLED
|
||||
Timer/Counter Mode: WB
|
||||
UFM Connection: ENABLED
|
||||
PLL0 Connection: DISABLED
|
||||
PLL1 Connection: DISABLED
|
||||
I2C Function Summary:
|
||||
--------------------
|
||||
None
|
||||
SPI Function Summary:
|
||||
--------------------
|
||||
None
|
||||
Timer/Counter Function Summary:
|
||||
------------------------------
|
||||
None
|
||||
UFM Function Summary:
|
||||
--------------------
|
||||
UFM Utilization: General Purpose Flash Memory
|
||||
Initialized UFM Pages: 321 Pages (321*128 Bits)
|
||||
Available General
|
||||
Purpose Flash Memory: 511 Pages (511*128 Bits)
|
||||
|
||||
EBR Blocks with Unique
|
||||
Initialization Data: 0
|
||||
|
||||
WID EBR Instance
|
||||
--- ------------
|
||||
|
||||
|
||||
|
||||
|
||||
<A name="mrp_asic"></A><B><U><big>ASIC Components</big></U></B>
|
||||
---------------
|
||||
|
||||
Instance Name: OSCH_inst
|
||||
Type: OSCH
|
||||
Instance Name: ufmefb/EFBInst_0
|
||||
Type: EFB
|
||||
Instance Name: rpll/PLLInst_0
|
||||
Type: EHXPLLJ
|
||||
|
||||
|
||||
|
||||
<A name="mrp_runtime"></A><B><U><big>Run Time and Memory Usage</big></U></B>
|
||||
-------------------------
|
||||
|
||||
Total CPU Time: 0 secs
|
||||
Total REAL Time: 0 secs
|
||||
Peak Memory Usage: 64 MB
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights
|
||||
reserved.
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
@ -0,0 +1,368 @@
|
||||
<HTML>
|
||||
<HEAD><TITLE>PAD Specification File</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Pad"></A>PAD Specification File
|
||||
***************************
|
||||
|
||||
PART TYPE: LCMXO2-1200HC
|
||||
Performance Grade: 4
|
||||
PACKAGE: TQFP100
|
||||
Package Status: Final Version 1.42
|
||||
|
||||
Sun Jul 14 22:31:22 2024
|
||||
|
||||
Pinout by Port Name:
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties |
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
| CROW[0] | 10/3 | LVCMOS33_IN | PL4B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| CROW[1] | 16/3 | LVCMOS33_IN | PL8A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[0] | 3/3 | LVCMOS33_IN | PL3A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[1] | 96/0 | LVCMOS33_IN | PT10B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[2] | 88/0 | LVCMOS33_IN | PT12A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[3] | 97/0 | LVCMOS33_IN | PT10A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[4] | 99/0 | LVCMOS33_IN | PT9A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[5] | 98/0 | LVCMOS33_IN | PT9B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[6] | 2/3 | LVCMOS33_IN | PL2D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[7] | 1/3 | LVCMOS33_IN | PL2C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Dout[0] | 76/0 | LVCMOS33_OUT | PT17D | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[1] | 86/0 | LVCMOS33_OUT | PT12C | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[2] | 87/0 | LVCMOS33_OUT | PT12B | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[3] | 85/0 | LVCMOS33_OUT | PT12D | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[4] | 83/0 | LVCMOS33_OUT | PT15B | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[5] | 84/0 | LVCMOS33_OUT | PT15A | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[6] | 78/0 | LVCMOS33_OUT | PT16C | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[7] | 82/0 | LVCMOS33_OUT | PT15C | | | DRIVE:4mA SLEW:FAST |
|
||||
| LED | 34/2 | LVCMOS33_OUT | PB9A | | | DRIVE:24mA SLEW:SLOW |
|
||||
| MAin[0] | 14/3 | LVCMOS33_IN | PL5C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[1] | 12/3 | LVCMOS33_IN | PL5A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[2] | 13/3 | LVCMOS33_IN | PL5B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[3] | 21/3 | LVCMOS33_IN | PL9B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[4] | 20/3 | LVCMOS33_IN | PL9A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[5] | 19/3 | LVCMOS33_IN | PL8D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[6] | 24/3 | LVCMOS33_IN | PL10C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[7] | 18/3 | LVCMOS33_IN | PL8C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[8] | 25/3 | LVCMOS33_IN | PL10D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[9] | 32/2 | LVCMOS33_IN | PB6D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| PHI2 | 8/3 | LVCMOS33_IN | PL3D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| RA[0] | 66/1 | LVCMOS33_OUT | PR4D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[10] | 64/1 | LVCMOS33_OUT | PR5B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[11] | 59/1 | LVCMOS33_OUT | PR8D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[1] | 67/1 | LVCMOS33_OUT | PR4C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[2] | 69/1 | LVCMOS33_OUT | PR4A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[3] | 71/1 | LVCMOS33_OUT | PR3A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[4] | 74/1 | LVCMOS33_OUT | PR2B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[5] | 70/1 | LVCMOS33_OUT | PR3B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[6] | 68/1 | LVCMOS33_OUT | PR4B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[7] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[9] | 62/1 | LVCMOS33_OUT | PR5D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RBA[0] | 58/1 | LVCMOS33_OUT | PR9A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RBA[1] | 47/2 | LVCMOS33_OUT | PB18D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RCKE | 53/1 | LVCMOS33_OUT | PR9D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RCLKout | 60/1 | LVCMOS33_OUT | PR8C | | | DRIVE:24mA SLEW:FAST |
|
||||
| RDQMH | 51/1 | LVCMOS33_OUT | PR10D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RDQML | 48/2 | LVCMOS33_OUT | PB20C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RD[0] | 36/2 | LVCMOS33_BIDI | PB11C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[1] | 37/2 | LVCMOS33_BIDI | PB11D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[2] | 38/2 | LVCMOS33_BIDI | PB11A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[3] | 39/2 | LVCMOS33_BIDI | PB11B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[4] | 40/2 | LVCMOS33_BIDI | PB15A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[5] | 41/2 | LVCMOS33_BIDI | PB15B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[6] | 42/2 | LVCMOS33_BIDI | PB18A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[7] | 43/2 | LVCMOS33_BIDI | PB18B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| nCCAS | 9/3 | LVCMOS33_IN | PL4A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nCRAS | 17/3 | LVCMOS33_IN | PL8B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nFWE | 15/3 | LVCMOS33_IN | PL5D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nRCAS | 52/1 | LVCMOS33_OUT | PR10C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nRCS | 57/1 | LVCMOS33_OUT | PR9B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nRRAS | 54/1 | LVCMOS33_OUT | PR9C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nRWE | 49/2 | LVCMOS33_OUT | PB20D | | | DRIVE:4mA SLEW:SLOW |
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
|
||||
Vccio by Bank:
|
||||
+------+-------+
|
||||
| Bank | Vccio |
|
||||
+------+-------+
|
||||
| 0 | 3.3V |
|
||||
| 1 | 3.3V |
|
||||
| 2 | 3.3V |
|
||||
| 3 | 3.3V |
|
||||
+------+-------+
|
||||
|
||||
|
||||
<A name="pad_vref"></A><B><U><big>Vref by Bank:</big></U></B>
|
||||
+------+-----+-----------------+---------+
|
||||
| Vref | Pin | Bank # / Vref # | Load(s) |
|
||||
+------+-----+-----------------+---------+
|
||||
+------+-----+-----------------+---------+
|
||||
|
||||
<A name="pad_pin"></A><B><U><big>Pinout by Pin Number:</big></U></B>
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable |
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
| 1/3 | Din[7] | LOCATED | LVCMOS33_IN | PL2C | L_GPLLT_IN | | |
|
||||
| 2/3 | Din[6] | LOCATED | LVCMOS33_IN | PL2D | L_GPLLC_IN | | |
|
||||
| 3/3 | Din[0] | LOCATED | LVCMOS33_IN | PL3A | PCLKT3_2 | | |
|
||||
| 4/3 | unused, PULL:DOWN | | | PL3B | PCLKC3_2 | | |
|
||||
| 7/3 | unused, PULL:DOWN | | | PL3C | | | |
|
||||
| 8/3 | PHI2 | LOCATED | LVCMOS33_IN | PL3D | | | |
|
||||
| 9/3 | nCCAS | LOCATED | LVCMOS33_IN | PL4A | | | |
|
||||
| 10/3 | CROW[0] | LOCATED | LVCMOS33_IN | PL4B | | | |
|
||||
| 12/3 | MAin[1] | LOCATED | LVCMOS33_IN | PL5A | PCLKT3_1 | | |
|
||||
| 13/3 | MAin[2] | LOCATED | LVCMOS33_IN | PL5B | PCLKC3_1 | | |
|
||||
| 14/3 | MAin[0] | LOCATED | LVCMOS33_IN | PL5C | | | |
|
||||
| 15/3 | nFWE | LOCATED | LVCMOS33_IN | PL5D | | | |
|
||||
| 16/3 | CROW[1] | LOCATED | LVCMOS33_IN | PL8A | | | |
|
||||
| 17/3 | nCRAS | LOCATED | LVCMOS33_IN | PL8B | | | |
|
||||
| 18/3 | MAin[7] | LOCATED | LVCMOS33_IN | PL8C | | | |
|
||||
| 19/3 | MAin[5] | LOCATED | LVCMOS33_IN | PL8D | | | |
|
||||
| 20/3 | MAin[4] | LOCATED | LVCMOS33_IN | PL9A | PCLKT3_0 | | |
|
||||
| 21/3 | MAin[3] | LOCATED | LVCMOS33_IN | PL9B | PCLKC3_0 | | |
|
||||
| 24/3 | MAin[6] | LOCATED | LVCMOS33_IN | PL10C | | | |
|
||||
| 25/3 | MAin[8] | LOCATED | LVCMOS33_IN | PL10D | | | |
|
||||
| 27/2 | unused, PULL:DOWN | | | PB4C | CSSPIN | | |
|
||||
| 28/2 | unused, PULL:DOWN | | | PB4D | | | |
|
||||
| 29/2 | unused, PULL:DOWN | | | PB6A | | | |
|
||||
| 30/2 | unused, PULL:DOWN | | | PB6B | | | |
|
||||
| 31/2 | unused, PULL:DOWN | | | PB6C | MCLK/CCLK | | |
|
||||
| 32/2 | MAin[9] | LOCATED | LVCMOS33_IN | PB6D | SO/SPISO | | |
|
||||
| 34/2 | LED | LOCATED | LVCMOS33_OUT | PB9A | PCLKT2_0 | | |
|
||||
| 35/2 | unused, PULL:DOWN | | | PB9B | PCLKC2_0 | | |
|
||||
| 36/2 | RD[0] | LOCATED | LVCMOS33_BIDI | PB11C | | | |
|
||||
| 37/2 | RD[1] | LOCATED | LVCMOS33_BIDI | PB11D | | | |
|
||||
| 38/2 | RD[2] | LOCATED | LVCMOS33_BIDI | PB11A | PCLKT2_1 | | |
|
||||
| 39/2 | RD[3] | LOCATED | LVCMOS33_BIDI | PB11B | PCLKC2_1 | | |
|
||||
| 40/2 | RD[4] | LOCATED | LVCMOS33_BIDI | PB15A | | | |
|
||||
| 41/2 | RD[5] | LOCATED | LVCMOS33_BIDI | PB15B | | | |
|
||||
| 42/2 | RD[6] | LOCATED | LVCMOS33_BIDI | PB18A | | | |
|
||||
| 43/2 | RD[7] | LOCATED | LVCMOS33_BIDI | PB18B | | | |
|
||||
| 45/2 | unused, PULL:DOWN | | | PB18C | | | |
|
||||
| 47/2 | RBA[1] | LOCATED | LVCMOS33_OUT | PB18D | | | |
|
||||
| 48/2 | RDQML | LOCATED | LVCMOS33_OUT | PB20C | SN | | |
|
||||
| 49/2 | nRWE | LOCATED | LVCMOS33_OUT | PB20D | SI/SISPI | | |
|
||||
| 51/1 | RDQMH | LOCATED | LVCMOS33_OUT | PR10D | DQ1 | | |
|
||||
| 52/1 | nRCAS | LOCATED | LVCMOS33_OUT | PR10C | DQ1 | | |
|
||||
| 53/1 | RCKE | LOCATED | LVCMOS33_OUT | PR9D | DQ1 | | |
|
||||
| 54/1 | nRRAS | LOCATED | LVCMOS33_OUT | PR9C | DQ1 | | |
|
||||
| 57/1 | nRCS | LOCATED | LVCMOS33_OUT | PR9B | DQ1 | | |
|
||||
| 58/1 | RBA[0] | LOCATED | LVCMOS33_OUT | PR9A | DQ1 | | |
|
||||
| 59/1 | RA[11] | LOCATED | LVCMOS33_OUT | PR8D | DQ1 | | |
|
||||
| 60/1 | RCLKout | LOCATED | LVCMOS33_OUT | PR8C | DQ1 | | |
|
||||
| 61/1 | unused, PULL:DOWN | | | PR8A | DQS1 | | |
|
||||
| 62/1 | RA[9] | LOCATED | LVCMOS33_OUT | PR5D | PCLKC1_0/DQ0 | | |
|
||||
| 63/1 | unused, PULL:DOWN | | | PR5C | PCLKT1_0/DQ0 | | |
|
||||
| 64/1 | RA[10] | LOCATED | LVCMOS33_OUT | PR5B | DQS0N | | |
|
||||
| 65/1 | RA[8] | LOCATED | LVCMOS33_OUT | PR5A | DQS0 | | |
|
||||
| 66/1 | RA[0] | LOCATED | LVCMOS33_OUT | PR4D | DQ0 | | |
|
||||
| 67/1 | RA[1] | LOCATED | LVCMOS33_OUT | PR4C | DQ0 | | |
|
||||
| 68/1 | RA[6] | LOCATED | LVCMOS33_OUT | PR4B | DQ0 | | |
|
||||
| 69/1 | RA[2] | LOCATED | LVCMOS33_OUT | PR4A | DQ0 | | |
|
||||
| 70/1 | RA[5] | LOCATED | LVCMOS33_OUT | PR3B | DQ0 | | |
|
||||
| 71/1 | RA[3] | LOCATED | LVCMOS33_OUT | PR3A | DQ0 | | |
|
||||
| 74/1 | RA[4] | LOCATED | LVCMOS33_OUT | PR2B | DQ0 | | |
|
||||
| 75/1 | RA[7] | LOCATED | LVCMOS33_OUT | PR2A | DQ0 | | |
|
||||
| 76/0 | Dout[0] | LOCATED | LVCMOS33_OUT | PT17D | DONE | | |
|
||||
| 77/0 | unused, PULL:DOWN | | | PT17C | INITN | | |
|
||||
| 78/0 | Dout[6] | LOCATED | LVCMOS33_OUT | PT16C | | | |
|
||||
| 81/0 | unused, PULL:DOWN | | | PT15D | PROGRAMN | | |
|
||||
| 82/0 | Dout[7] | LOCATED | LVCMOS33_OUT | PT15C | JTAGENB | | |
|
||||
| 83/0 | Dout[4] | LOCATED | LVCMOS33_OUT | PT15B | | | |
|
||||
| 84/0 | Dout[5] | LOCATED | LVCMOS33_OUT | PT15A | | | |
|
||||
| 85/0 | Dout[3] | LOCATED | LVCMOS33_OUT | PT12D | SDA/PCLKC0_0 | | |
|
||||
| 86/0 | Dout[1] | LOCATED | LVCMOS33_OUT | PT12C | SCL/PCLKT0_0 | | |
|
||||
| 87/0 | Dout[2] | LOCATED | LVCMOS33_OUT | PT12B | PCLKC0_1 | | |
|
||||
| 88/0 | Din[2] | LOCATED | LVCMOS33_IN | PT12A | PCLKT0_1 | | |
|
||||
| 90/0 | Reserved: sysCONFIG | | | PT11D | TMS | | |
|
||||
| 91/0 | Reserved: sysCONFIG | | | PT11C | TCK | | |
|
||||
| 94/0 | Reserved: sysCONFIG | | | PT10D | TDI | | |
|
||||
| 95/0 | Reserved: sysCONFIG | | | PT10C | TDO | | |
|
||||
| 96/0 | Din[1] | LOCATED | LVCMOS33_IN | PT10B | | | |
|
||||
| 97/0 | Din[3] | LOCATED | LVCMOS33_IN | PT10A | | | |
|
||||
| 98/0 | Din[5] | LOCATED | LVCMOS33_IN | PT9B | | | |
|
||||
| 99/0 | Din[4] | LOCATED | LVCMOS33_IN | PT9A | | | |
|
||||
| PB4A/2 | unused, PULL:DOWN | | | PB4A | | | |
|
||||
| PB4B/2 | unused, PULL:DOWN | | | PB4B | | | |
|
||||
| PB9C/2 | unused, PULL:DOWN | | | PB9C | | | |
|
||||
| PB9D/2 | unused, PULL:DOWN | | | PB9D | | | |
|
||||
| PB15C/2 | unused, PULL:DOWN | | | PB15C | | | |
|
||||
| PB15D/2 | unused, PULL:DOWN | | | PB15D | | | |
|
||||
| PB20A/2 | unused, PULL:DOWN | | | PB20A | | | |
|
||||
| PB20B/2 | unused, PULL:DOWN | | | PB20B | | | |
|
||||
| PL2A/3 | unused, PULL:DOWN | | | PL2A | L_GPLLT_FB | | |
|
||||
| PL2B/3 | unused, PULL:DOWN | | | PL2B | L_GPLLC_FB | | |
|
||||
| PL4C/3 | unused, PULL:DOWN | | | PL4C | | | |
|
||||
| PL4D/3 | unused, PULL:DOWN | | | PL4D | | | |
|
||||
| PL10A/3 | unused, PULL:DOWN | | | PL10A | | | |
|
||||
| PL10B/3 | unused, PULL:DOWN | | | PL10B | | | |
|
||||
| PR2C/1 | unused, PULL:DOWN | | | PR2C | DQ0 | | |
|
||||
| PR2D/1 | unused, PULL:DOWN | | | PR2D | DQ0 | | |
|
||||
| PR8B/1 | unused, PULL:DOWN | | | PR8B | DQS1N | | |
|
||||
| PR10A/1 | unused, PULL:DOWN | | | PR10A | DQ1 | | |
|
||||
| PR10B/1 | unused, PULL:DOWN | | | PR10B | DQ1 | | |
|
||||
| PT9C/0 | unused, PULL:DOWN | | | PT9C | | | |
|
||||
| PT9D/0 | unused, PULL:DOWN | | | PT9D | | | |
|
||||
| PT11A/0 | unused, PULL:DOWN | | | PT11A | | | |
|
||||
| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | |
|
||||
| PT16A/0 | unused, PULL:DOWN | | | PT16A | | | |
|
||||
| PT16B/0 | unused, PULL:DOWN | | | PT16B | | | |
|
||||
| PT16D/0 | unused, PULL:DOWN | | | PT16D | | | |
|
||||
| PT17A/0 | unused, PULL:DOWN | | | PT17A | | | |
|
||||
| PT17B/0 | unused, PULL:DOWN | | | PT17B | | | |
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
|
||||
sysCONFIG Pins:
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode |
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
| PT11D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP |
|
||||
| PT11C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down |
|
||||
| PT10D | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP |
|
||||
| PT10C | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP |
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
|
||||
Dedicated sysCONFIG Pins:
|
||||
|
||||
|
||||
List of All Pins' Locate Preferences Based on Final Placement After PAR
|
||||
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste):
|
||||
|
||||
LOCATE COMP "CROW[0]" SITE "10";
|
||||
LOCATE COMP "CROW[1]" SITE "16";
|
||||
LOCATE COMP "Din[0]" SITE "3";
|
||||
LOCATE COMP "Din[1]" SITE "96";
|
||||
LOCATE COMP "Din[2]" SITE "88";
|
||||
LOCATE COMP "Din[3]" SITE "97";
|
||||
LOCATE COMP "Din[4]" SITE "99";
|
||||
LOCATE COMP "Din[5]" SITE "98";
|
||||
LOCATE COMP "Din[6]" SITE "2";
|
||||
LOCATE COMP "Din[7]" SITE "1";
|
||||
LOCATE COMP "Dout[0]" SITE "76";
|
||||
LOCATE COMP "Dout[1]" SITE "86";
|
||||
LOCATE COMP "Dout[2]" SITE "87";
|
||||
LOCATE COMP "Dout[3]" SITE "85";
|
||||
LOCATE COMP "Dout[4]" SITE "83";
|
||||
LOCATE COMP "Dout[5]" SITE "84";
|
||||
LOCATE COMP "Dout[6]" SITE "78";
|
||||
LOCATE COMP "Dout[7]" SITE "82";
|
||||
LOCATE COMP "LED" SITE "34";
|
||||
LOCATE COMP "MAin[0]" SITE "14";
|
||||
LOCATE COMP "MAin[1]" SITE "12";
|
||||
LOCATE COMP "MAin[2]" SITE "13";
|
||||
LOCATE COMP "MAin[3]" SITE "21";
|
||||
LOCATE COMP "MAin[4]" SITE "20";
|
||||
LOCATE COMP "MAin[5]" SITE "19";
|
||||
LOCATE COMP "MAin[6]" SITE "24";
|
||||
LOCATE COMP "MAin[7]" SITE "18";
|
||||
LOCATE COMP "MAin[8]" SITE "25";
|
||||
LOCATE COMP "MAin[9]" SITE "32";
|
||||
LOCATE COMP "PHI2" SITE "8";
|
||||
LOCATE COMP "RA[0]" SITE "66";
|
||||
LOCATE COMP "RA[10]" SITE "64";
|
||||
LOCATE COMP "RA[11]" SITE "59";
|
||||
LOCATE COMP "RA[1]" SITE "67";
|
||||
LOCATE COMP "RA[2]" SITE "69";
|
||||
LOCATE COMP "RA[3]" SITE "71";
|
||||
LOCATE COMP "RA[4]" SITE "74";
|
||||
LOCATE COMP "RA[5]" SITE "70";
|
||||
LOCATE COMP "RA[6]" SITE "68";
|
||||
LOCATE COMP "RA[7]" SITE "75";
|
||||
LOCATE COMP "RA[8]" SITE "65";
|
||||
LOCATE COMP "RA[9]" SITE "62";
|
||||
LOCATE COMP "RBA[0]" SITE "58";
|
||||
LOCATE COMP "RBA[1]" SITE "47";
|
||||
LOCATE COMP "RCKE" SITE "53";
|
||||
LOCATE COMP "RCLKout" SITE "60";
|
||||
LOCATE COMP "RDQMH" SITE "51";
|
||||
LOCATE COMP "RDQML" SITE "48";
|
||||
LOCATE COMP "RD[0]" SITE "36";
|
||||
LOCATE COMP "RD[1]" SITE "37";
|
||||
LOCATE COMP "RD[2]" SITE "38";
|
||||
LOCATE COMP "RD[3]" SITE "39";
|
||||
LOCATE COMP "RD[4]" SITE "40";
|
||||
LOCATE COMP "RD[5]" SITE "41";
|
||||
LOCATE COMP "RD[6]" SITE "42";
|
||||
LOCATE COMP "RD[7]" SITE "43";
|
||||
LOCATE COMP "nCCAS" SITE "9";
|
||||
LOCATE COMP "nCRAS" SITE "17";
|
||||
LOCATE COMP "nFWE" SITE "15";
|
||||
LOCATE COMP "nRCAS" SITE "52";
|
||||
LOCATE COMP "nRCS" SITE "57";
|
||||
LOCATE COMP "nRRAS" SITE "54";
|
||||
LOCATE COMP "nRWE" SITE "49";
|
||||
|
||||
#PLL
|
||||
LOCATE COMP "rpll/PLLInst_0" SITE "LPLL" ;
|
||||
|
||||
|
||||
|
||||
|
||||
PAR: Place And Route Diamond (64-bit) 3.11.3.469.
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Sun Jul 14 22:31:25 2024
|
||||
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
@ -0,0 +1,326 @@
|
||||
<HTML>
|
||||
<HEAD><TITLE>Place & Route Report</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Par"></A>PAR: Place And Route Diamond (64-bit) 3.11.3.469.
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Sun Jul 14 22:31:16 2024
|
||||
|
||||
C:/lscc/diamond/3.11_x64/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_1200HC_impl1.p2t
|
||||
RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.dir
|
||||
RAM2GS_LCMXO2_1200HC_impl1.prf -gui -msgset
|
||||
//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC-IntOsc/promote.xml
|
||||
|
||||
|
||||
Preference file: RAM2GS_LCMXO2_1200HC_impl1.prf.
|
||||
|
||||
<A name="par_cts"></A><B><U><big>Cost Table Summary</big></U></B>
|
||||
Level/ Number Worst Timing Worst Timing Run NCD
|
||||
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
|
||||
---------- -------- ----- ------ ----------- ----------- ---- ------
|
||||
5_1 * 0 6.959 0 0.304 0 11 Completed
|
||||
* : Design saved.
|
||||
|
||||
Total (real) run time for 1-seed: 11 secs
|
||||
|
||||
par done!
|
||||
|
||||
Note: user must run 'Trace' for timing closure signoff.
|
||||
|
||||
Lattice Place and Route Report for Design "RAM2GS_LCMXO2_1200HC_impl1_map.ncd"
|
||||
Sun Jul 14 22:31:16 2024
|
||||
|
||||
|
||||
<A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
|
||||
PAR: Place And Route Diamond (64-bit) 3.11.3.469.
|
||||
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC-IntOsc/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
|
||||
Preference file: RAM2GS_LCMXO2_1200HC_impl1.prf.
|
||||
Placement level-cost: 5-1.
|
||||
Routing Iterations: 6
|
||||
|
||||
Loading design for application par from file RAM2GS_LCMXO2_1200HC_impl1_map.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-1200HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.11_x64/ispfpga.
|
||||
Package Status: Final Version 1.42.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
License checked out.
|
||||
|
||||
|
||||
Ignore Preference Error(s): True
|
||||
|
||||
<A name="par_dus"></A><B><U><big>Device utilization summary:</big></U></B>
|
||||
|
||||
PIO (prelim) 63+4(JTAG)/108 62% used
|
||||
63+4(JTAG)/80 84% bonded
|
||||
IOLOGIC 36/108 33% used
|
||||
|
||||
SLICE 106/640 16% used
|
||||
|
||||
OSC 1/1 100% used
|
||||
PLL 1/1 100% used
|
||||
EFB 1/1 100% used
|
||||
|
||||
|
||||
Number of Signals: 359
|
||||
Number of Connections: 970
|
||||
|
||||
Pin Constraint Summary:
|
||||
63 out of 63 pins locked (100% locked).
|
||||
|
||||
The following 3 signals are selected to use the primary clock routing resources:
|
||||
PCLK (driver: rpll/PLLInst_0, clk load #: 47)
|
||||
PHI2_c (driver: PHI2, clk load #: 19)
|
||||
nCRAS_c (driver: nCRAS, clk load #: 14)
|
||||
|
||||
WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
WARNING - par: Signal "nCRAS_c" is selected to use Primary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
|
||||
The following 3 signals are selected to use the secondary clock routing resources:
|
||||
nCCAS_c (driver: nCCAS, clk load #: 8, sr load #: 0, ce load #: 0)
|
||||
Ready (driver: SLICE_33, clk load #: 0, sr load #: 13, ce load #: 0)
|
||||
N_239_i (driver: SLICE_75, clk load #: 0, sr load #: 0, ce load #: 10)
|
||||
|
||||
WARNING - par: Signal "nCCAS_c" is selected to use Secondary clock resources. However, its driver comp "nCCAS" is located at "9", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
No signal is selected as Global Set/Reset.
|
||||
Starting Placer Phase 0.
|
||||
........
|
||||
Finished Placer Phase 0. REAL time: 2 secs
|
||||
|
||||
Starting Placer Phase 1.
|
||||
...................
|
||||
Placer score = 73583.
|
||||
Finished Placer Phase 1. REAL time: 6 secs
|
||||
|
||||
Starting Placer Phase 2.
|
||||
.
|
||||
Placer score = 73283
|
||||
Finished Placer Phase 2. REAL time: 6 secs
|
||||
|
||||
|
||||
|
||||
<A name="par_clk"></A><B><U><big>Clock Report</big></U></B>
|
||||
|
||||
Global Clock Resources:
|
||||
CLK_PIN : 0 out of 8 (0%)
|
||||
General PIO: 3 out of 108 (2%)
|
||||
PLL : 1 out of 1 (100%)
|
||||
DCM : 0 out of 2 (0%)
|
||||
DCC : 0 out of 8 (0%)
|
||||
|
||||
Global Clocks:
|
||||
PRIMARY "PCLK" from CLKOP on comp "rpll/PLLInst_0" on PLL site "LPLL", clk load = 47
|
||||
PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3D)", clk load = 19
|
||||
PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL8B)", clk load = 14
|
||||
SECONDARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL4A)", clk load = 8, ce load = 0, sr load = 0
|
||||
SECONDARY "Ready" from Q0 on comp "SLICE_33" on site "R7C14A", clk load = 0, ce load = 0, sr load = 13
|
||||
SECONDARY "N_239_i" from F0 on comp "SLICE_75" on site "R7C12D", clk load = 0, ce load = 10, sr load = 0
|
||||
|
||||
PRIMARY : 3 out of 8 (37%)
|
||||
SECONDARY: 3 out of 8 (37%)
|
||||
|
||||
Edge Clocks:
|
||||
No edge clock selected.
|
||||
|
||||
|
||||
|
||||
|
||||
I/O Usage Summary (final):
|
||||
63 + 4(JTAG) out of 108 (62.0%) PIO sites used.
|
||||
63 + 4(JTAG) out of 80 (83.8%) bonded PIO sites used.
|
||||
Number of PIO comps: 63; differential: 0.
|
||||
Number of Vref pins used: 0.
|
||||
|
||||
I/O Bank Usage Summary:
|
||||
+----------+----------------+------------+-----------+
|
||||
| I/O Bank | Usage | Bank Vccio | Bank Vref |
|
||||
+----------+----------------+------------+-----------+
|
||||
| 0 | 13 / 19 ( 68%) | 3.3V | - |
|
||||
| 1 | 19 / 21 ( 90%) | 3.3V | - |
|
||||
| 2 | 13 / 20 ( 65%) | 3.3V | - |
|
||||
| 3 | 18 / 20 ( 90%) | 3.3V | - |
|
||||
+----------+----------------+------------+-----------+
|
||||
|
||||
Total placer CPU time: 5 secs
|
||||
|
||||
Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd.
|
||||
|
||||
0 connections routed; 970 unrouted.
|
||||
Starting router resource preassignment
|
||||
WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
|
||||
|
||||
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
|
||||
Signal=ICLK loads=1 clock_loads=1
|
||||
|
||||
Completed router resource preassignment. Real time: 9 secs
|
||||
|
||||
Start NBR router at 22:31:25 07/14/24
|
||||
|
||||
*****************************************************************
|
||||
Info: NBR allows conflicts(one node used by more than one signal)
|
||||
in the earlier iterations. In each iteration, it tries to
|
||||
solve the conflicts while keeping the critical connections
|
||||
routed as short as possible. The routing process is said to
|
||||
be completed when no conflicts exist and all connections
|
||||
are routed.
|
||||
Note: NBR uses a different method to calculate timing slacks. The
|
||||
worst slack and total negative slack may not be the same as
|
||||
that in TRCE report. You should always run TRCE to verify
|
||||
your design.
|
||||
*****************************************************************
|
||||
|
||||
Start NBR special constraint process at 22:31:25 07/14/24
|
||||
|
||||
Start NBR section for initial routing at 22:31:26 07/14/24
|
||||
Level 1, iteration 1
|
||||
0(0.00%) conflict; 743(76.60%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 7.385ns/0.000ns; real time: 10 secs
|
||||
Level 2, iteration 1
|
||||
0(0.00%) conflict; 735(75.77%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 7.429ns/0.000ns; real time: 10 secs
|
||||
Level 3, iteration 1
|
||||
0(0.00%) conflict; 734(75.67%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 7.556ns/0.000ns; real time: 10 secs
|
||||
Level 4, iteration 1
|
||||
14(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 6.959ns/0.000ns; real time: 10 secs
|
||||
|
||||
Info: Initial congestion level at 75% usage is 0
|
||||
Info: Initial congestion area at 75% usage is 0 (0.00%)
|
||||
|
||||
Start NBR section for normal routing at 22:31:26 07/14/24
|
||||
Level 4, iteration 1
|
||||
4(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 6.959ns/0.000ns; real time: 10 secs
|
||||
Level 4, iteration 2
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 6.959ns/0.000ns; real time: 10 secs
|
||||
|
||||
Start NBR section for setup/hold timing optimization with effort level 3 at 22:31:26 07/14/24
|
||||
|
||||
Start NBR section for re-routing at 22:31:26 07/14/24
|
||||
Level 4, iteration 1
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 6.959ns/0.000ns; real time: 10 secs
|
||||
|
||||
Start NBR section for post-routing at 22:31:26 07/14/24
|
||||
|
||||
End NBR router with 0 unrouted connection
|
||||
|
||||
NBR Summary
|
||||
-----------
|
||||
Number of unrouted connections : 0 (0.00%)
|
||||
Number of connections with timing violations : 0 (0.00%)
|
||||
Estimated worst slack<setup> : 6.959ns
|
||||
Timing score<setup> : 0
|
||||
-----------
|
||||
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
|
||||
|
||||
|
||||
|
||||
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
|
||||
Signal=ICLK loads=1 clock_loads=1
|
||||
|
||||
Total CPU time 10 secs
|
||||
Total REAL time: 11 secs
|
||||
Completely routed.
|
||||
End of route. 970 routed (100.00%); 0 unrouted.
|
||||
|
||||
Hold time timing score: 0, hold timing errors: 0
|
||||
|
||||
Timing score: 0
|
||||
|
||||
Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd.
|
||||
|
||||
|
||||
All signals are completely routed.
|
||||
|
||||
|
||||
PAR_SUMMARY::Run status = Completed
|
||||
PAR_SUMMARY::Number of unrouted conns = 0
|
||||
PAR_SUMMARY::Worst slack<setup/<ns>> = 6.959
|
||||
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
|
||||
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.304
|
||||
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
|
||||
PAR_SUMMARY::Number of errors = 0
|
||||
|
||||
Total CPU time to completion: 10 secs
|
||||
Total REAL time to completion: 11 secs
|
||||
|
||||
par done!
|
||||
|
||||
Note: user must run 'Trace' for timing closure signoff.
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
|
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
@ -0,0 +1,67 @@
|
||||
|
||||
Copyright (C) 1994-2018 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: N-2018.03L-SP1-1
|
||||
Install: C:\lscc\diamond\3.11_x64\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
|
||||
# Written on Sun Jul 14 22:31:10 2024
|
||||
|
||||
##### FILES SYNTAX CHECKED ##############################################
|
||||
Constraint File(s): "\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS.sdc"
|
||||
|
||||
#Run constraint checker to find more issues with constraints.
|
||||
#########################################################################
|
||||
|
||||
|
||||
|
||||
No issues found in constraint syntax.
|
||||
|
||||
|
||||
|
||||
Clock Summary
|
||||
*************
|
||||
|
||||
Start Requested Requested Clock Clock Clock
|
||||
Level Clock Frequency Period Type Group Load
|
||||
--------------------------------------------------------------------------------------------------------------
|
||||
0 - PHI2 2.9 MHz 350.000 declared default_clkgroup 20
|
||||
|
||||
0 - nCRAS 2.9 MHz 350.000 declared default_clkgroup 15
|
||||
|
||||
0 - nCCAS 2.9 MHz 350.000 declared default_clkgroup 10
|
||||
|
||||
0 - RCLK 62.5 MHz 16.000 declared default_clkgroup 0
|
||||
|
||||
0 - System 100.0 MHz 10.000 system system_clkgroup 0
|
||||
|
||||
0 - RPLL|CLKOP_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_0 65
|
||||
==============================================================================================================
|
||||
|
||||
|
||||
Clock Load Summary
|
||||
******************
|
||||
|
||||
Clock Source Clock Pin Non-clock Pin Non-clock Pin
|
||||
Clock Load Pin Seq Example Seq Example Comb Example
|
||||
------------------------------------------------------------------------------------------------------------------------------
|
||||
PHI2 20 PHI2(port) Bank[7:0].C PHI2r.D[0] un1_PHI2.I[0](inv)
|
||||
|
||||
nCRAS 15 nCRAS(port) CBR.C RASr.D[0] RASr_2.I[0](inv)
|
||||
|
||||
nCCAS 10 nCCAS(port) WRD[7:0].C CASr.D[0] CASr_2.I[0](inv)
|
||||
|
||||
RCLK 0 RCLK(port) - - -
|
||||
|
||||
System 0 - - - -
|
||||
|
||||
RPLL|CLKOP_inferred_clock 65 rpll.PLLInst_0.CLKOP(EHXPLLJ) CASr2.C - -
|
||||
==============================================================================================================================
|
||||
@ -0,0 +1,83 @@
|
||||
<HTML>
|
||||
<HEAD><TITLE>Project Summary</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><TABLE border=1 width=100% cellspacing=0 cellpadding=2><small>
|
||||
<TR>
|
||||
<TD align='center' BGCOLOR='#000099' COLSPAN='4'><SPAN style="COLOR: #FFFFFF"><B>RAM2GS_LCMXO2_1200HC project summary</B></SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Module Name:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">RAM2GS_LCMXO2_1200HC</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Synthesis:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">SynplifyPro</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Name:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">impl1</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Strategy Name:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">Strategy1</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Last Process:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">JEDEC File</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">State:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">Passed</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Target Device:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">LCMXO2-1200HC-4TG100C</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Device Family:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">MachXO2</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Device Type:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">LCMXO2-1200HC</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Package Type:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">TQFP100</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Performance grade:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">4</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Operating conditions:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">COM</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Logic preference file:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">RAM2GS-LCMXO2.lpf</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Physical Preference file:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">impl1/RAM2GS_LCMXO2_1200HC_impl1.prf</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Product Version:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">3.11.3.469</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Patch Version:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000"></SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Updated:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2024/07/14 22:31:30</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Location:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC-IntOsc/impl1</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Project File:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC-IntOsc/RAM2GS_LCMXO2_1200HC.ldf</SPAN></TD>
|
||||
</TR>
|
||||
</small></TABLE>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
@ -0,0 +1,873 @@
|
||||
<HTML>
|
||||
<HEAD><TITLE>Synthesis Report</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
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}
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margin-top: 4px;
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margin-right: 4px;
margin-left: 4px;
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{
border-width: 1px 1px 1px 1px;
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border-collapse: collapse;
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border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
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{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Syn"></A><B><U><big>Synthesis Report</big></U></B>
|
||||
#Build: Synplify Pro (R) N-2018.03L-SP1-1, Build 443R, Apr 1 2019
|
||||
#install: C:\lscc\diamond\3.11_x64\synpbase
|
||||
#OS: Windows 8 6.2
|
||||
#Hostname: ZANEMACWIN11
|
||||
|
||||
# Sun Jul 14 22:31:08 2024
|
||||
|
||||
#Implementation: impl1
|
||||
|
||||
|
||||
Copyright (C) 1994-2018 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: N-2018.03L-SP1-1
|
||||
Install: C:\lscc\diamond\3.11_x64\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
Synopsys HDL Compiler, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
|
||||
Copyright (C) 1994-2018 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: N-2018.03L-SP1-1
|
||||
Install: C:\lscc\diamond\3.11_x64\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
Synopsys Verilog Compiler, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v" (library work)
|
||||
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\pmi_def.v" (library work)
|
||||
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
|
||||
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
|
||||
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
|
||||
@I::"C:\lscc\diamond\3.11_x64\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
|
||||
@I::"\\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\REFB.v" (library work)
|
||||
@I::"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2-IntOsc.v" (library work)
|
||||
@I::"\\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\RPLL.v" (library work)
|
||||
Verilog syntax check successful!
|
||||
Options changed - recompiling
|
||||
Selecting top level module RAM2GS
|
||||
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1793:7:1793:10|Synthesizing module OSCH in library work.
|
||||
Running optimization stage 1 on OSCH .......
|
||||
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
|
||||
Running optimization stage 1 on VLO .......
|
||||
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1730:7:1730:13|Synthesizing module EHXPLLJ in library work.
|
||||
Running optimization stage 1 on EHXPLLJ .......
|
||||
@N: CG364 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\RPLL.v":8:7:8:10|Synthesizing module RPLL in library work.
|
||||
Running optimization stage 1 on RPLL .......
|
||||
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1601:7:1601:12|Synthesizing module ODDRXE in library work.
|
||||
Running optimization stage 1 on ODDRXE .......
|
||||
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
|
||||
Running optimization stage 1 on VHI .......
|
||||
@N: CG364 :"C:\lscc\diamond\3.11_x64\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
|
||||
Running optimization stage 1 on EFB .......
|
||||
@N: CG364 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
|
||||
Running optimization stage 1 on REFB .......
|
||||
@W: CL318 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\REFB.v":9:14:9:21|*Output wb_dat_o has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output.
|
||||
@N: CG364 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2-IntOsc.v":1:7:1:12|Synthesizing module RAM2GS in library work.
|
||||
Running optimization stage 1 on RAM2GS .......
|
||||
Running optimization stage 2 on RAM2GS .......
|
||||
@N: CL159 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2-IntOsc.v":50:10:50:13|Input RCLK is unused.
|
||||
Running optimization stage 2 on REFB .......
|
||||
Running optimization stage 2 on EFB .......
|
||||
Running optimization stage 2 on VHI .......
|
||||
Running optimization stage 2 on ODDRXE .......
|
||||
Running optimization stage 2 on RPLL .......
|
||||
Running optimization stage 2 on EHXPLLJ .......
|
||||
Running optimization stage 2 on VLO .......
|
||||
Running optimization stage 2 on OSCH .......
|
||||
|
||||
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Sun Jul 14 22:31:08 2024
|
||||
|
||||
###########################################################]
|
||||
|
||||
Copyright (C) 1994-2018 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: N-2018.03L-SP1-1
|
||||
Install: C:\lscc\diamond\3.11_x64\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
File \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\impl1\synwork\layer0.srs changed - recompiling
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Sun Jul 14 22:31:08 2024
|
||||
|
||||
###########################################################]
|
||||
|
||||
For a summary of runtime and memory usage for all design units, please see file:
|
||||
==========================================================
|
||||
@L: A:\\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\impl1\synwork\RAM2GS_LCMXO2_1200HC_impl1_comp.rt.csv
|
||||
|
||||
@END
|
||||
|
||||
At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Sun Jul 14 22:31:08 2024
|
||||
|
||||
###########################################################]
|
||||
|
||||
Copyright (C) 1994-2018 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: N-2018.03L-SP1-1
|
||||
Install: C:\lscc\diamond\3.11_x64\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Database state : \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\impl1\synwork\|impl1
|
||||
Synopsys Synopsys Netlist Linker, Version comp2018q2p1, Build 461R, Built Apr 1 2019 09:17:43
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
File \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\impl1\synwork\RAM2GS_LCMXO2_1200HC_impl1_comp.srs changed - recompiling
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 68MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Sun Jul 14 22:31:10 2024
|
||||
|
||||
###########################################################]
|
||||
# Sun Jul 14 22:31:10 2024
|
||||
|
||||
|
||||
Copyright (C) 1994-2018 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: N-2018.03L-SP1-1
|
||||
Install: C:\lscc\diamond\3.11_x64\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
Synopsys Lattice Technology Pre-mapping, Version maplat2018q2p1, Build 055R, Built Apr 3 2019 09:51:54
|
||||
|
||||
|
||||
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
|
||||
|
||||
Reading constraint file: \\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS.sdc
|
||||
@N: MF284 |Setting synthesis effort to medium for the design
|
||||
@L: \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\impl1\RAM2GS_LCMXO2_1200HC_impl1_scck.rpt
|
||||
Printing clock summary report in "\\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\impl1\RAM2GS_LCMXO2_1200HC_impl1_scck.rpt" file
|
||||
@N: MF916 |Option synthesis_strategy=base is enabled.
|
||||
@N: MF248 |Running in 64-bit mode.
|
||||
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
|
||||
|
||||
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
|
||||
|
||||
|
||||
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
|
||||
|
||||
|
||||
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB)
|
||||
|
||||
|
||||
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB)
|
||||
|
||||
@N: MF284 |Setting synthesis effort to medium for the design
|
||||
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
|
||||
@N: MH105 |UMR3 is only supported for HAPS-80.
|
||||
@N: MH105 |UMR3 is only supported for HAPS-80.
|
||||
syn_allowed_resources : blockrams=7 set on top level netlist RAM2GS
|
||||
|
||||
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
|
||||
|
||||
|
||||
|
||||
Clock Summary
|
||||
******************
|
||||
|
||||
Start Requested Requested Clock Clock Clock
|
||||
Level Clock Frequency Period Type Group Load
|
||||
--------------------------------------------------------------------------------------------------------------
|
||||
0 - PHI2 2.9 MHz 350.000 declared default_clkgroup 20
|
||||
|
||||
0 - nCRAS 2.9 MHz 350.000 declared default_clkgroup 15
|
||||
|
||||
0 - nCCAS 2.9 MHz 350.000 declared default_clkgroup 10
|
||||
|
||||
0 - RCLK 62.5 MHz 16.000 declared default_clkgroup 0
|
||||
|
||||
0 - System 100.0 MHz 10.000 system system_clkgroup 0
|
||||
|
||||
0 - RPLL|CLKOP_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_0 65
|
||||
==============================================================================================================
|
||||
|
||||
|
||||
|
||||
Clock Load Summary
|
||||
***********************
|
||||
|
||||
Clock Source Clock Pin Non-clock Pin Non-clock Pin
|
||||
Clock Load Pin Seq Example Seq Example Comb Example
|
||||
------------------------------------------------------------------------------------------------------------------------------
|
||||
PHI2 20 PHI2(port) Bank[7:0].C PHI2r.D[0] un1_PHI2.I[0](inv)
|
||||
|
||||
nCRAS 15 nCRAS(port) CBR.C RASr.D[0] RASr_2.I[0](inv)
|
||||
|
||||
nCCAS 10 nCCAS(port) WRD[7:0].C CASr.D[0] CASr_2.I[0](inv)
|
||||
|
||||
RCLK 0 RCLK(port) - - -
|
||||
|
||||
System 0 - - - -
|
||||
|
||||
RPLL|CLKOP_inferred_clock 65 rpll.PLLInst_0.CLKOP(EHXPLLJ) CASr2.C - -
|
||||
==============================================================================================================================
|
||||
|
||||
@W: MT529 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2-intosc.v":174:4:174:9|Found inferred clock RPLL|CLKOP_inferred_clock which controls 65 sequential elements including RCKE. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
|
||||
|
||||
ICG Latch Removal Summary:
|
||||
Number of ICG latches removed: 0
|
||||
Number of ICG latches not removed: 0
|
||||
|
||||
|
||||
@S |Clock Optimization Summary
|
||||
|
||||
|
||||
|
||||
#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
|
||||
|
||||
3 non-gated/non-generated clock tree(s) driving 41 clock pin(s) of sequential element(s)
|
||||
1 gated/generated clock tree(s) driving 65 clock pin(s) of sequential element(s)
|
||||
0 instances converted, 65 sequential instances remain driven by gated/generated clocks
|
||||
|
||||
=========================== Non-Gated/Non-Generated Clocks ============================
|
||||
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
|
||||
---------------------------------------------------------------------------------------
|
||||
@KP:ckid0_1 PHI2 port 19 RA11
|
||||
@KP:ckid0_2 nCCAS port 8 WRD[7:0]
|
||||
@KP:ckid0_3 nCRAS port 14 RowA[9:0]
|
||||
=======================================================================================
|
||||
====================================================== Gated/Generated Clocks ======================================================
|
||||
Clock Tree ID Driving Element Drive Element Type Unconverted Fanout Sample Instance Explanation
|
||||
------------------------------------------------------------------------------------------------------------------------------------
|
||||
@KP:ckid0_0 rpll.PLLInst_0.CLKOP EHXPLLJ 65 RCKE Black box on clock path
|
||||
====================================================================================================================================
|
||||
|
||||
|
||||
##### END OF CLOCK OPTIMIZATION REPORT ######
|
||||
|
||||
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
|
||||
Finished Pre Mapping Phase.
|
||||
|
||||
Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 143MB)
|
||||
|
||||
|
||||
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
|
||||
|
||||
None
|
||||
None
|
||||
|
||||
Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
|
||||
|
||||
Pre-mapping successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 143MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Sun Jul 14 22:31:10 2024
|
||||
|
||||
###########################################################]
|
||||
# Sun Jul 14 22:31:11 2024
|
||||
|
||||
|
||||
Copyright (C) 1994-2018 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: N-2018.03L-SP1-1
|
||||
Install: C:\lscc\diamond\3.11_x64\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
Synopsys Lattice Technology Mapper, Version maplat2018q2p1, Build 055R, Built Apr 3 2019 09:51:54
|
||||
|
||||
|
||||
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
|
||||
|
||||
@N: MF284 |Setting synthesis effort to medium for the design
|
||||
@N: MF916 |Option synthesis_strategy=base is enabled.
|
||||
@N: MF248 |Running in 64-bit mode.
|
||||
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
|
||||
|
||||
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
|
||||
|
||||
|
||||
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
|
||||
|
||||
|
||||
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
|
||||
|
||||
|
||||
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
|
||||
|
||||
@N: MF284 |Setting synthesis effort to medium for the design
|
||||
|
||||
|
||||
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
|
||||
|
||||
|
||||
Available hyper_sources - for debug and ip models
|
||||
None Found
|
||||
|
||||
|
||||
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
|
||||
|
||||
@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2-intosc.v":180:4:180:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0]
|
||||
@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2-intosc.v":167:4:167:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0]
|
||||
|
||||
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB)
|
||||
|
||||
|
||||
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB)
|
||||
|
||||
|
||||
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB)
|
||||
|
||||
|
||||
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
|
||||
|
||||
|
||||
Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
|
||||
|
||||
|
||||
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
|
||||
|
||||
|
||||
Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)
|
||||
|
||||
|
||||
Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 152MB)
|
||||
|
||||
Pass CPU time Worst Slack Luts / Registers
|
||||
------------------------------------------------------------
|
||||
1 0h:00m:00s 2.24ns 198 / 106
|
||||
|
||||
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 152MB)
|
||||
|
||||
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
|
||||
|
||||
Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 151MB peak: 152MB)
|
||||
|
||||
|
||||
Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 117MB peak: 152MB)
|
||||
|
||||
Writing Analyst data base \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\impl1\synwork\RAM2GS_LCMXO2_1200HC_impl1_m.srm
|
||||
|
||||
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 151MB peak: 153MB)
|
||||
|
||||
Writing EDIF Netlist and constraint files
|
||||
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC-IntOsc\impl1\RAM2GS_LCMXO2_1200HC_impl1.edi
|
||||
N-2018.03L-SP1-1
|
||||
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
|
||||
|
||||
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 155MB peak: 157MB)
|
||||
|
||||
|
||||
Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 155MB peak: 157MB)
|
||||
|
||||
@W: MT246 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2-intosc.v":57:11:57:19|Blackbox ODDRXE is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
|
||||
@W: MT246 :"\\mac\icloud\repos\ram2gs\cpld\lcmxo2-1200hc-intosc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
|
||||
@W: MT246 :"\\mac\icloud\repos\ram2gs\cpld\lcmxo2-1200hc-intosc\rpll.v":64:12:64:20|Blackbox EHXPLLJ is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
|
||||
@N: MT615 |Found clock RCLK with period 16.00ns
|
||||
@N: MT615 |Found clock PHI2 with period 350.00ns
|
||||
@N: MT615 |Found clock nCRAS with period 350.00ns
|
||||
@N: MT615 |Found clock nCCAS with period 350.00ns
|
||||
@W: MT420 |Found inferred clock RPLL|CLKOP_inferred_clock with period 10.00ns. Please declare a user-defined clock on net rpll.PCLK.
|
||||
|
||||
|
||||
##### START OF TIMING REPORT #####[
|
||||
# Timing Report written on Sun Jul 14 22:31:13 2024
|
||||
#
|
||||
|
||||
|
||||
Top view: RAM2GS
|
||||
Requested Frequency: 2.9 MHz
|
||||
Wire load mode: top
|
||||
Paths requested: 5
|
||||
Constraint File(s): \\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS.sdc
|
||||
|
||||
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
|
||||
|
||||
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
|
||||
|
||||
|
||||
|
||||
Performance Summary
|
||||
*******************
|
||||
|
||||
|
||||
Worst slack in design: 3.291
|
||||
|
||||
@N: MT286 |System clock period 0.000 stretches to negative invalid value -- ignoring stretching.
|
||||
Requested Estimated Requested Estimated Clock Clock
|
||||
Starting Clock Frequency Frequency Period Period Slack Type Group
|
||||
----------------------------------------------------------------------------------------------------------------------------------
|
||||
PHI2 2.9 MHz 69.1 MHz 350.000 14.481 167.760 declared default_clkgroup
|
||||
RCLK 62.5 MHz NA 16.000 NA NA declared default_clkgroup
|
||||
RPLL|CLKOP_inferred_clock 100.0 MHz 149.0 MHz 10.000 6.709 3.291 inferred Inferred_clkgroup_0
|
||||
nCCAS 2.9 MHz NA 350.000 NA NA declared default_clkgroup
|
||||
nCRAS 2.9 MHz NA 350.000 NA NA declared default_clkgroup
|
||||
System 100.0 MHz 388.0 MHz 10.000 2.577 7.423 system system_clkgroup
|
||||
==================================================================================================================================
|
||||
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Clock Relationships
|
||||
*******************
|
||||
|
||||
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
System System | 10.000 10.000 | No paths - | No paths - | No paths -
|
||||
System RPLL|CLKOP_inferred_clock | 10.000 7.423 | No paths - | No paths - | No paths -
|
||||
PHI2 PHI2 | No paths - | 350.000 347.124 | 175.000 167.760 | 175.000 173.428
|
||||
PHI2 RPLL|CLKOP_inferred_clock | No paths - | No paths - | No paths - | Diff grp -
|
||||
nCRAS RPLL|CLKOP_inferred_clock | No paths - | No paths - | No paths - | Diff grp -
|
||||
RPLL|CLKOP_inferred_clock System | 10.000 8.892 | No paths - | No paths - | No paths -
|
||||
RPLL|CLKOP_inferred_clock PHI2 | Diff grp - | No paths - | Diff grp - | No paths -
|
||||
RPLL|CLKOP_inferred_clock nCRAS | No paths - | No paths - | Diff grp - | No paths -
|
||||
RPLL|CLKOP_inferred_clock RPLL|CLKOP_inferred_clock | 10.000 3.291 | No paths - | No paths - | No paths -
|
||||
===================================================================================================================================================
|
||||
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
|
||||
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
|
||||
|
||||
|
||||
|
||||
Interface Information
|
||||
*********************
|
||||
|
||||
No IO constraint found
|
||||
|
||||
|
||||
|
||||
====================================
|
||||
Detailed Report for Clock: PHI2
|
||||
====================================
|
||||
|
||||
|
||||
|
||||
Starting Points with Worst Slack
|
||||
********************************
|
||||
|
||||
Starting Arrival
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
------------------------------------------------------------------------------------
|
||||
Bank_0io[0] PHI2 IFS1P3DX Q Bank[0] 0.972 167.760
|
||||
Bank_0io[1] PHI2 IFS1P3DX Q Bank[1] 0.972 167.760
|
||||
Bank_0io[2] PHI2 IFS1P3DX Q Bank[2] 0.972 167.760
|
||||
Bank_0io[3] PHI2 IFS1P3DX Q Bank[3] 0.972 167.760
|
||||
Bank_0io[4] PHI2 IFS1P3DX Q Bank[4] 0.972 167.760
|
||||
Bank_0io[5] PHI2 IFS1P3DX Q Bank[5] 0.972 167.760
|
||||
Bank_0io[6] PHI2 IFS1P3DX Q Bank[6] 0.972 167.760
|
||||
Bank_0io[7] PHI2 IFS1P3DX Q Bank[7] 0.972 167.760
|
||||
XOR8MEG PHI2 FD1P3AX Q XOR8MEG 1.044 173.428
|
||||
CmdEnable PHI2 FD1S3AX Q CmdEnable 1.180 347.124
|
||||
====================================================================================
|
||||
|
||||
|
||||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------------------------
|
||||
CmdEnable PHI2 FD1S3AX D CmdEnable_1 175.462 167.760
|
||||
CmdLEDEN PHI2 FD1P3AX SP XOR8MEG17 174.528 168.897
|
||||
CmdUFMShift PHI2 FD1P3AX SP XOR8MEG17 174.528 168.897
|
||||
CmdUFMWrite PHI2 FD1P3AX SP XOR8MEG17 174.528 168.897
|
||||
Cmdn8MEGEN PHI2 FD1P3AX SP XOR8MEG17 174.528 168.897
|
||||
XOR8MEG PHI2 FD1P3AX SP XOR8MEG17 174.528 168.897
|
||||
ADSubmitted PHI2 FD1S3AX D ADSubmitted_2 175.089 169.017
|
||||
C1Submitted PHI2 FD1S3AX D C1Submitted_1 175.089 169.017
|
||||
CmdValid PHI2 FD1S3AX D CmdValid_0 175.089 169.049
|
||||
CmdUFMData PHI2 FD1P3AX SP CmdUFMData_1_sqmuxa 174.528 169.505
|
||||
==============================================================================================
|
||||
|
||||
|
||||
|
||||
Worst Path Information
|
||||
***********************
|
||||
|
||||
|
||||
Path information for path number 1:
|
||||
Requested Period: 175.000
|
||||
- Setup time: -0.462
|
||||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
= Required time: 175.462
|
||||
|
||||
- Propagation time: 7.703
|
||||
- Clock delay at starting point: 0.000 (ideal)
|
||||
= Slack (non-critical) : 167.760
|
||||
|
||||
Number of logic level(s): 7
|
||||
Starting point: Bank_0io[0] / Q
|
||||
Ending point: CmdEnable / D
|
||||
The start point is clocked by PHI2 [rising] on pin SCLK
|
||||
The end point is clocked by PHI2 [falling] on pin CK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
---------------------------------------------------------------------------------
|
||||
Bank_0io[0] IFS1P3DX Q Out 0.972 0.972 -
|
||||
Bank[0] Net - - - - 1
|
||||
un1_Bank_1_4 ORCALUT4 A In 0.000 0.972 -
|
||||
un1_Bank_1_4 ORCALUT4 Z Out 1.153 2.125 -
|
||||
un1_Bank_1_4 Net - - - - 3
|
||||
C1WR_7 ORCALUT4 C In 0.000 2.125 -
|
||||
C1WR_7 ORCALUT4 Z Out 1.089 3.213 -
|
||||
C1WR_7 Net - - - - 2
|
||||
C1WR ORCALUT4 C In 0.000 3.213 -
|
||||
C1WR ORCALUT4 Z Out 1.089 4.302 -
|
||||
C1WR Net - - - - 2
|
||||
un1_ADWR ORCALUT4 B In 0.000 4.302 -
|
||||
un1_ADWR ORCALUT4 Z Out 1.153 5.455 -
|
||||
un1_ADWR Net - - - - 3
|
||||
un1_CMDWR ORCALUT4 B In 0.000 5.455 -
|
||||
un1_CMDWR ORCALUT4 Z Out 1.017 6.472 -
|
||||
un1_CMDWR Net - - - - 1
|
||||
CmdEnable_1_am ORCALUT4 C In 0.000 6.472 -
|
||||
CmdEnable_1_am ORCALUT4 Z Out 1.017 7.489 -
|
||||
CmdEnable_1_am Net - - - - 1
|
||||
CmdEnable_1 PFUMX BLUT In 0.000 7.489 -
|
||||
CmdEnable_1 PFUMX Z Out 0.214 7.703 -
|
||||
CmdEnable_1 Net - - - - 1
|
||||
CmdEnable FD1S3AX D In 0.000 7.703 -
|
||||
=================================================================================
|
||||
|
||||
|
||||
|
||||
|
||||
====================================
|
||||
Detailed Report for Clock: RPLL|CLKOP_inferred_clock
|
||||
====================================
|
||||
|
||||
|
||||
|
||||
Starting Points with Worst Slack
|
||||
********************************
|
||||
|
||||
Starting Arrival
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
-----------------------------------------------------------------------------------------------
|
||||
InitReady RPLL|CLKOP_inferred_clock FD1S3AX Q InitReady 1.326 3.291
|
||||
FS[15] RPLL|CLKOP_inferred_clock FD1S3AX Q FS[15] 1.188 3.429
|
||||
FS[16] RPLL|CLKOP_inferred_clock FD1S3AX Q FS[16] 1.188 3.429
|
||||
FS[17] RPLL|CLKOP_inferred_clock FD1S3AX Q FS[17] 1.188 3.429
|
||||
FS[13] RPLL|CLKOP_inferred_clock FD1S3AX Q FS[13] 1.276 3.777
|
||||
FS[9] RPLL|CLKOP_inferred_clock FD1S3AX Q FS[9] 1.268 3.785
|
||||
FS[10] RPLL|CLKOP_inferred_clock FD1S3AX Q FS[10] 1.268 3.785
|
||||
FS[14] RPLL|CLKOP_inferred_clock FD1S3AX Q FS[14] 1.260 3.793
|
||||
FS[12] RPLL|CLKOP_inferred_clock FD1S3AX Q FS[12] 1.284 4.049
|
||||
FS[11] RPLL|CLKOP_inferred_clock FD1S3AX Q FS[11] 1.272 4.061
|
||||
===============================================================================================
|
||||
|
||||
|
||||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------------------------------
|
||||
wb_dati[2] RPLL|CLKOP_inferred_clock FD1P3AX D wb_dati_5[2] 10.089 3.291
|
||||
wb_dati[4] RPLL|CLKOP_inferred_clock FD1P3AX D wb_dati_5[4] 10.089 3.291
|
||||
wb_dati[5] RPLL|CLKOP_inferred_clock FD1P3AX D wb_dati_5[5] 10.089 3.291
|
||||
wb_dati[7] RPLL|CLKOP_inferred_clock FD1P3AX D wb_dati_5[7] 10.089 3.291
|
||||
wb_dati[3] RPLL|CLKOP_inferred_clock FD1P3AX D wb_dati_5[3] 10.089 3.395
|
||||
wb_dati[6] RPLL|CLKOP_inferred_clock FD1P3AX D wb_dati_5[6] 10.089 3.395
|
||||
wb_dati[1] RPLL|CLKOP_inferred_clock FD1P3AX D wb_dati_5[1] 10.089 4.483
|
||||
FS[17] RPLL|CLKOP_inferred_clock FD1S3AX D FS_s[17] 9.894 4.551
|
||||
LEDEN RPLL|CLKOP_inferred_clock FD1P3AX SP N_63 9.528 4.604
|
||||
n8MEGEN RPLL|CLKOP_inferred_clock FD1P3AX SP N_63 9.528 4.604
|
||||
====================================================================================================
|
||||
|
||||
|
||||
|
||||
Worst Path Information
|
||||
***********************
|
||||
|
||||
|
||||
Path information for path number 1:
|
||||
Requested Period: 10.000
|
||||
- Setup time: -0.089
|
||||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
= Required time: 10.089
|
||||
|
||||
- Propagation time: 6.798
|
||||
- Clock delay at starting point: 0.000 (ideal)
|
||||
= Slack (critical) : 3.291
|
||||
|
||||
Number of logic level(s): 5
|
||||
Starting point: InitReady / Q
|
||||
Ending point: wb_dati[2] / D
|
||||
The start point is clocked by RPLL|CLKOP_inferred_clock [rising] on pin CK
|
||||
The end point is clocked by RPLL|CLKOP_inferred_clock [rising] on pin CK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
--------------------------------------------------------------------------------------------
|
||||
InitReady FD1S3AX Q Out 1.326 1.326 -
|
||||
InitReady Net - - - - 35
|
||||
wb_adr_cnst_sn.m2_i_o3 ORCALUT4 B In 0.000 1.326 -
|
||||
wb_adr_cnst_sn.m2_i_o3 ORCALUT4 Z Out 1.317 2.643 -
|
||||
N_242 Net - - - - 18
|
||||
FS_RNI7U6M[14] ORCALUT4 B In 0.000 2.643 -
|
||||
FS_RNI7U6M[14] ORCALUT4 Z Out 1.193 3.836 -
|
||||
N_134 Net - - - - 4
|
||||
un1_FS_26_1_0_a2_RNI761E1 ORCALUT4 C In 0.000 3.836 -
|
||||
un1_FS_26_1_0_a2_RNI761E1 ORCALUT4 Z Out 1.153 4.989 -
|
||||
wb_adr_21_sqmuxa_s9 Net - - - - 3
|
||||
FS_RNIFUUT2[9] ORCALUT4 C In 0.000 4.989 -
|
||||
FS_RNIFUUT2[9] ORCALUT4 Z Out 1.193 6.181 -
|
||||
N_194 Net - - - - 4
|
||||
wb_dati_5_1_iv[2] ORCALUT4 B In 0.000 6.181 -
|
||||
wb_dati_5_1_iv[2] ORCALUT4 Z Out 0.617 6.798 -
|
||||
wb_dati_5[2] Net - - - - 1
|
||||
wb_dati[2] FD1P3AX D In 0.000 6.798 -
|
||||
============================================================================================
|
||||
|
||||
|
||||
|
||||
|
||||
====================================
|
||||
Detailed Report for Clock: System
|
||||
====================================
|
||||
|
||||
|
||||
|
||||
Starting Points with Worst Slack
|
||||
********************************
|
||||
|
||||
Starting Arrival
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
-----------------------------------------------------------------------------------------
|
||||
ufmefb.EFBInst_0 System EFB WBACKO wb_ack 0.000 7.423
|
||||
ufmefb.EFBInst_0 System EFB WBDATO0 wb_dato[0] 0.000 9.472
|
||||
ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000 9.472
|
||||
OSCH_inst System OSCH OSC ICLK 0.000 10.000
|
||||
=========================================================================================
|
||||
|
||||
|
||||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
---------------------------------------------------------------------------------------
|
||||
LEDEN System FD1P3AX SP N_63 9.528 7.423
|
||||
n8MEGEN System FD1P3AX SP N_63 9.528 7.423
|
||||
wb_cyc_stb System FD1P3IX SP N_51 9.528 8.912
|
||||
LEDEN System FD1P3AX D LEDEN_6 10.089 9.472
|
||||
n8MEGEN System FD1P3AX D n8MEGEN_6 10.089 9.472
|
||||
rpll.PLLInst_0 System EHXPLLJ CLKI ICLK 10.000 10.000
|
||||
=======================================================================================
|
||||
|
||||
|
||||
|
||||
Worst Path Information
|
||||
***********************
|
||||
|
||||
|
||||
Path information for path number 1:
|
||||
Requested Period: 10.000
|
||||
- Setup time: 0.472
|
||||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
= Required time: 9.528
|
||||
|
||||
- Propagation time: 2.106
|
||||
- Clock delay at starting point: 0.000 (ideal)
|
||||
- Estimated clock delay at start point: -0.000
|
||||
= Slack (non-critical) : 7.423
|
||||
|
||||
Number of logic level(s): 2
|
||||
Starting point: ufmefb.EFBInst_0 / WBACKO
|
||||
Ending point: LEDEN / SP
|
||||
The start point is clocked by System [rising]
|
||||
The end point is clocked by RPLL|CLKOP_inferred_clock [rising] on pin CK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
-------------------------------------------------------------------------------------
|
||||
ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 -
|
||||
wb_ack Net - - - - 2
|
||||
un1_FS_38_i_a3_0 ORCALUT4 B In 0.000 0.000 -
|
||||
un1_FS_38_i_a3_0 ORCALUT4 Z Out 1.017 1.017 -
|
||||
un1_FS_38_i_a3_0 Net - - - - 1
|
||||
un1_FS_38_i_0 ORCALUT4 C In 0.000 1.017 -
|
||||
un1_FS_38_i_0 ORCALUT4 Z Out 1.089 2.106 -
|
||||
N_63 Net - - - - 2
|
||||
LEDEN FD1P3AX SP In 0.000 2.106 -
|
||||
=====================================================================================
|
||||
|
||||
|
||||
|
||||
##### END OF TIMING REPORT #####]
|
||||
|
||||
Timing exceptions that could not be applied
|
||||
None
|
||||
|
||||
Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 155MB peak: 157MB)
|
||||
|
||||
|
||||
Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 155MB peak: 157MB)
|
||||
|
||||
---------------------------------------
|
||||
Resource Usage Report
|
||||
Part: lcmxo2_1200hc-4
|
||||
|
||||
Register bits: 106 of 1280 (8%)
|
||||
PIC Latch: 0
|
||||
I/O cells: 63
|
||||
|
||||
|
||||
Details:
|
||||
BB: 8
|
||||
CCU2D: 10
|
||||
EFB: 1
|
||||
EHXPLLJ: 1
|
||||
FD1P3AX: 28
|
||||
FD1P3IX: 3
|
||||
FD1S3AX: 37
|
||||
FD1S3IX: 3
|
||||
GSR: 1
|
||||
IB: 24
|
||||
IFS1P3DX: 9
|
||||
IFS1P3IX: 10
|
||||
IFS1P3JX: 2
|
||||
INV: 7
|
||||
OB: 31
|
||||
ODDRXE: 1
|
||||
OFS1P3BX: 4
|
||||
OFS1P3DX: 8
|
||||
OFS1P3IX: 1
|
||||
OFS1P3JX: 1
|
||||
ORCALUT4: 186
|
||||
OSCH: 1
|
||||
PFUMX: 2
|
||||
PUR: 1
|
||||
VHI: 2
|
||||
VLO: 3
|
||||
true: 1
|
||||
Mapper successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 33MB peak: 157MB)
|
||||
|
||||
Process took 0h:00m:02s realtime, 0h:00m:02s cputime
|
||||
# Sun Jul 14 22:31:13 2024
|
||||
|
||||
###########################################################]
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
21
CPLD/LCMXO2-1200HC-IntOsc/impl1/hdla_gen_hierarchy.html
Normal file
21
CPLD/LCMXO2-1200HC-IntOsc/impl1/hdla_gen_hierarchy.html
Normal file
File diff suppressed because one or more lines are too long
29
CPLD/LCMXO2-1200HC-IntOsc/msg_file.log
Normal file
29
CPLD/LCMXO2-1200HC-IntOsc/msg_file.log
Normal file
@ -0,0 +1,29 @@
|
||||
SCUBA, Version Diamond (64-bit) 3.11.3.469
|
||||
Sun Jul 14 22:23:22 2024
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
BEGIN SCUBA Module Synthesis
|
||||
|
||||
Issued command : C:\lscc\diamond\3.11_x64\ispfpga\bin\nt64\scuba.exe -w -n RPLL -lang verilog -synth synplify -arch xo2c00 -type pll -fin 133.0 -fclkop 61 -fclkop_tol 1.0 -trimp 0 -phasep 0 -trimp_r -phase_cntl STATIC -fb_mode 1
|
||||
Circuit name : RPLL
|
||||
Module type : pll
|
||||
Module Version : 5.7
|
||||
Ports :
|
||||
Inputs : CLKI
|
||||
Outputs : CLKOP
|
||||
I/O buffer : not inserted
|
||||
EDIF output : RPLL.edn
|
||||
Verilog output : RPLL.v
|
||||
Verilog template : RPLL_tmpl.v
|
||||
Verilog purpose : for synthesis and simulation
|
||||
Bus notation : big endian
|
||||
Report output : RPLL.srp
|
||||
Estimated Resource Usage:
|
||||
|
||||
END SCUBA Module Synthesis
|
||||
|
||||
3
CPLD/LCMXO2-1200HC-IntOsc/promote.xml
Normal file
3
CPLD/LCMXO2-1200HC-IntOsc/promote.xml
Normal file
@ -0,0 +1,3 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<userSetting name="//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC-IntOsc/promote.xml" version="Diamond (64-bit) 3.11.3.469" date="Mon Jul 15 05:33:30 2024" vendor="Lattice Semiconductor Corporation" >
|
||||
</userSetting>
|
||||
10
CPLD/LCMXO2-1200HC-IntOsc/reportview.xml
Normal file
10
CPLD/LCMXO2-1200HC-IntOsc/reportview.xml
Normal file
@ -0,0 +1,10 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!DOCTYPE Report>
|
||||
<ReportView version="2.0">
|
||||
<Implement name="impl1">
|
||||
<ToolReport id="tooldec" path="" status="0"/>
|
||||
<ToolReport id="toolhle_genhierarchy" path="//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC-IntOsc/impl1/hdla_gen_hierarchy.html" status="1"/>
|
||||
<ToolReport id="toolpio" path="" status="0"/>
|
||||
<ToolReport id="toolsso" path="" status="0"/>
|
||||
</Implement>
|
||||
</ReportView>
|
||||
632
CPLD/RAM2GS-LCMXO2-IntOsc.v
Normal file
632
CPLD/RAM2GS-LCMXO2-IntOsc.v
Normal file
@ -0,0 +1,632 @@
|
||||
module RAM2GS(PHI2, MAin, CROW, Din, Dout,
|
||||
nCCAS, nCRAS, nFWE, LED,
|
||||
RBA, RA, RD, nRCS, RCLK, RCLKout, RCKE,
|
||||
nRWE, nRRAS, nRCAS, RDQMH, RDQML);
|
||||
|
||||
|
||||
/* 65816 Phase 2 Clock */
|
||||
input PHI2;
|
||||
|
||||
/* Async. DRAM Control Inputs */
|
||||
input nCCAS, nCRAS;
|
||||
|
||||
/* Synchronized PHI2 and DRAM signals */
|
||||
reg PHI2r, PHI2r2, PHI2r3;
|
||||
reg RASr, RASr2, RASr3;
|
||||
reg CASr, CASr2, CASr3;
|
||||
reg FWEr;
|
||||
reg CBR;
|
||||
|
||||
/* Activity LED */
|
||||
reg LEDEN;
|
||||
output LED;
|
||||
assign LED = !(!nCRAS && !CBR && LEDEN && Ready);
|
||||
|
||||
/* 65816 Data */
|
||||
input [7:0] Din;
|
||||
output [7:0] Dout;
|
||||
assign Dout[7:0] = RD[7:0];
|
||||
|
||||
/* Latched 65816 Bank Address */
|
||||
reg [7:0] Bank;
|
||||
|
||||
/* Async. DRAM Address Bus */
|
||||
input [1:0] CROW;
|
||||
input [9:0] MAin;
|
||||
input nFWE;
|
||||
reg n8MEGEN = 0;
|
||||
reg XOR8MEG = 0;
|
||||
|
||||
/* Internal clock */
|
||||
wire ICLK;
|
||||
defparam OSCH_inst.NOM_FREQ = "133.00";
|
||||
OSCH OSCH_inst(.STDBY(1'b0), .OSC(ICLK), .SEDSTDBY());
|
||||
|
||||
/* PLL */
|
||||
wire PCLK;
|
||||
RPLL rpll (.CLKI(ICLK), .CLKOP(PCLK));
|
||||
|
||||
/* SDRAM Clock in */
|
||||
input RCLK;
|
||||
|
||||
/* Clock net tie */
|
||||
wire CLK = PCLK;
|
||||
|
||||
/* SDRAM clock out */
|
||||
output RCLKout;
|
||||
ODDRXE rclk_oddr(.D0(1'b0), .D1(1'b1),
|
||||
.SCLK(CLK), .RST(1'b0), .Q(RCLKout));
|
||||
|
||||
/* SDRAM */
|
||||
reg RCKEEN;
|
||||
output reg RCKE = 0;
|
||||
output reg nRCS = 1, nRRAS = 1, nRCAS = 1, nRWE = 1;
|
||||
output reg [1:0] RBA;
|
||||
reg nRowColSel;
|
||||
reg RA11;
|
||||
reg RA10;
|
||||
reg [9:0] RowA;
|
||||
output [11:0] RA;
|
||||
assign RA[11] = RA11;
|
||||
assign RA[10] = RA10;
|
||||
assign RA[9:0] = !nRowColSel ? RowA[9:0] : MAin[9:0];
|
||||
output RDQML, RDQMH;
|
||||
assign RDQML = !nRowColSel ? 1'b1 : !MAin[9];
|
||||
assign RDQMH = !nRowColSel ? 1'b1 : MAin[9];
|
||||
reg [7:0] WRD;
|
||||
inout [7:0] RD;
|
||||
assign RD[7:0] = (!nCCAS && !nFWE) ? WRD[7:0] : 8'bZ;
|
||||
|
||||
/* UFM Interface */
|
||||
reg wb_rst;
|
||||
reg wb_cyc_stb;
|
||||
reg wb_req;
|
||||
reg wb_we;
|
||||
reg [7:0] wb_adr;
|
||||
reg [7:0] wb_dati;
|
||||
wire wb_ack;
|
||||
wire [7:0] wb_dato;
|
||||
wire ufm_irq;
|
||||
REFB ufmefb (
|
||||
.wb_clk_i(CLK),
|
||||
.wb_rst_i(wb_rst),
|
||||
.wb_cyc_i(wb_cyc_stb),
|
||||
.wb_stb_i(wb_cyc_stb),
|
||||
.wb_we_i(wb_we),
|
||||
.wb_adr_i(wb_adr),
|
||||
.wb_dat_i(wb_dati),
|
||||
.wb_dat_o(wb_dato),
|
||||
.wb_ack_o(wb_ack),
|
||||
.wbc_ufm_irq(ufm_irq));
|
||||
|
||||
/* UFM Command Interface */
|
||||
reg C1Submitted = 0;
|
||||
reg ADSubmitted = 0;
|
||||
reg CmdEnable = 0;
|
||||
reg CmdValid = 0;
|
||||
reg Cmdn8MEGEN = 0;
|
||||
reg CmdLEDEN = 0;
|
||||
reg CmdUFMWrite = 0;
|
||||
reg CmdUFMShift = 0;
|
||||
reg CmdUFMData = 0;
|
||||
wire ADWR = Bank[7:0]==8'hFB && MAin[7:0]==8'hFF && !nFWE;
|
||||
wire C1WR = Bank[7:0]==8'hFB && MAin[7:0]==8'hFE && !nFWE;
|
||||
wire CMDWR = Bank[7:0]==8'hFB && MAin[7:0]==8'hFD && !nFWE;
|
||||
|
||||
/* State Counters */
|
||||
reg InitReady = 0; // 1 if ready for init sequence
|
||||
reg Ready = 0; // 1 if done with init sequence
|
||||
reg [1:0] S = 0; // post-RAS State counter
|
||||
reg [17:0] FS = 0; // Fast init state counter
|
||||
reg [3:0] IS = 0; // Init state counter
|
||||
|
||||
/* Synchronize PHI2, RAS, CAS */
|
||||
always @(posedge CLK) begin
|
||||
PHI2r <= PHI2; PHI2r2 <= PHI2r; PHI2r3 <= PHI2r2;
|
||||
RASr <= !nCRAS; RASr2 <= RASr; RASr3 <= RASr2;
|
||||
CASr <= !nCCAS; CASr2 <= CASr; CASr3 <= CASr2;
|
||||
end
|
||||
|
||||
/* Latch 65816 bank when PHI2 rises */
|
||||
always @(posedge PHI2) begin
|
||||
if (Ready) RA11 <= (Din[6] && !n8MEGEN) ^ XOR8MEG; // Set RA11
|
||||
else RA11 <= 1'b0; // Reserved in mode register
|
||||
Bank[7:0] <= Din[7:0]; // Latch bank
|
||||
end
|
||||
|
||||
/* Latch bank address, row address, WE, and CAS when RAS falls */
|
||||
always @(negedge nCRAS) begin
|
||||
if (Ready) begin
|
||||
RBA[1:0] <= CROW[1:0];
|
||||
RowA[9:0] <= MAin[9:0];
|
||||
end else begin
|
||||
RBA[1:0] <= 2'b00; // Reserved in mode register
|
||||
RowA[9] <= 1'b1; // "1" for single write mode
|
||||
RowA[8] <= 1'b0; // Reserved
|
||||
RowA[7] <= 1'b0; // "0" for not test mode
|
||||
RowA[6:4] <= 3'b010; // "2" for CAS latency 2
|
||||
RowA[3] <= 1'b0; // "0" for sequential burst (not used)
|
||||
RowA[2:0] <= 3'b000; // "0" for burst length 1 (no burst)
|
||||
end
|
||||
FWEr <= !nFWE;
|
||||
CBR <= !nCCAS;
|
||||
end
|
||||
|
||||
/* Latch write data when CAS falls */
|
||||
always @(negedge nCCAS) begin
|
||||
WRD[7:0] <= Din[7:0];
|
||||
end
|
||||
|
||||
/* State counter from RAS */
|
||||
always @(posedge CLK) begin
|
||||
if (!RASr2) S <= 0;
|
||||
else if (S==2'h3) S <= 2'h3;
|
||||
else S <= S+2'h1;
|
||||
end
|
||||
/* Init state counter */
|
||||
always @(posedge CLK) begin
|
||||
// Wait ~4.178ms (at 62.5 MHz) before starting init sequence
|
||||
FS <= FS+18'h1;
|
||||
if (FS[17:10]==8'hFF) InitReady <= 1'b1;
|
||||
end
|
||||
|
||||
/* SDRAM CKE */
|
||||
always @(posedge CLK) begin
|
||||
// Only 1 LUT4 allowed for this function!
|
||||
RCKE <= ((RASr || RASr2) && RCKEEN) || (!RASr2 && RASr3);
|
||||
end
|
||||
|
||||
/* SDRAM command */
|
||||
always @(posedge CLK) begin
|
||||
if (Ready) begin
|
||||
if (S==0) begin
|
||||
if (RASr2) begin
|
||||
if (CBR) begin
|
||||
// AREF
|
||||
nRCS <= 1'b0;
|
||||
nRRAS <= 1'b0;
|
||||
nRCAS <= 1'b0;
|
||||
nRWE <= 1'b1;
|
||||
RA10 <= 1'b1; // RA10 is don't care
|
||||
end else begin
|
||||
// ACT
|
||||
nRCS <= 1'b0;
|
||||
nRRAS <= 1'b0;
|
||||
nRCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
RA10 <= 1'b1; // Bank RA10 consistently "1"
|
||||
end
|
||||
// Enable clock only for reads
|
||||
RCKEEN <= !CBR && !FWEr;
|
||||
end else if (RCKE) begin
|
||||
// PCall
|
||||
nRCS <= 1'b0;
|
||||
nRRAS <= 1'b0;
|
||||
nRCAS <= 1'b1;
|
||||
nRWE <= 1'b0;
|
||||
RA10 <= 1'b1; // "all"
|
||||
RCKEEN <= 1'b1;
|
||||
end else begin
|
||||
// NOP
|
||||
nRCS <= 1'b1;
|
||||
nRRAS <= 1'b1;
|
||||
nRCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
RA10 <= 1'b1; // RA10 is don't care
|
||||
RCKEEN <= 1'b1;
|
||||
end
|
||||
nRowColSel <= 1'b0; // Select registered row addres
|
||||
end else if (S==1) begin
|
||||
// NOP
|
||||
nRCS <= 1'b1;
|
||||
nRRAS <= 1'b1;
|
||||
nRCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
RA10 <= 1'b1; // RA10 is don't care
|
||||
nRowColSel <= 1'b1; // Select asynchronous column address
|
||||
RCKEEN <= !CBR; // Disable clock if refresh cycle
|
||||
end else if (S==2) begin
|
||||
if (!FWEr && !CBR) begin
|
||||
// RD
|
||||
nRCS <= 1'b0;
|
||||
nRRAS <= 1'b1;
|
||||
nRCAS <= 1'b0;
|
||||
nRWE <= 1'b1;
|
||||
RA10 <= 1'b1; // Auto-precharge
|
||||
end else begin
|
||||
// NOP
|
||||
nRCS <= 1'b1;
|
||||
nRRAS <= 1'b1;
|
||||
nRCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
RA10 <= 1'b1; // RA10 is don't care
|
||||
end
|
||||
nRowColSel <= 1'b1; // Select asynchronous column address
|
||||
RCKEEN <= !CBR && FWEr; // Enable clock only for writes
|
||||
end else if (S==3) begin
|
||||
if (CASr2 && !CASr3 && !CBR && FWEr) begin
|
||||
// WR
|
||||
nRCS <= 1'b0;
|
||||
nRRAS <= 1'b1;
|
||||
nRCAS <= 1'b0;
|
||||
nRWE <= 1'b0;
|
||||
RA10 <= 1'b1; // Auto-precharge
|
||||
end else begin
|
||||
// NOP
|
||||
nRCS <= 1'b1;
|
||||
nRRAS <= 1'b1;
|
||||
nRCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
RA10 <= 1'b1; // RA10 is don't care
|
||||
end
|
||||
nRowColSel <= !(!FWEr || CASr3 || CBR);
|
||||
RCKEEN <= !(!FWEr || CASr2 || CBR);
|
||||
end
|
||||
end else if (InitReady) begin
|
||||
if (S==0 && RASr2) begin
|
||||
if (IS==0) begin
|
||||
// NOP
|
||||
nRCS <= 1'b1;
|
||||
nRRAS <= 1'b1;
|
||||
nRCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
RA10 <= 1'b1; // RA10 is don't care
|
||||
end else if (IS==1) begin
|
||||
// PC all
|
||||
nRCS <= 1'b0;
|
||||
nRRAS <= 1'b0;
|
||||
nRCAS <= 1'b1;
|
||||
nRWE <= 1'b0;
|
||||
RA10 <= 1'b1; // "all"
|
||||
end else if (IS==9) begin
|
||||
// Load mode register
|
||||
nRCS <= 1'b0;
|
||||
nRRAS <= 1'b0;
|
||||
nRCAS <= 1'b0;
|
||||
nRWE <= 1'b0;
|
||||
RA10 <= 1'b0; // Reserved in mode register
|
||||
end else begin
|
||||
// AREF
|
||||
nRCS <= 1'b0;
|
||||
nRRAS <= 1'b0;
|
||||
nRCAS <= 1'b0;
|
||||
nRWE <= 1'b1;
|
||||
RA10 <= 1'b1; // RA10 is don't care
|
||||
end
|
||||
IS <= IS+4'h1;
|
||||
end else begin
|
||||
// NOP
|
||||
nRCS <= 1'b1;
|
||||
nRRAS <= 1'b1;
|
||||
nRCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
RA10 <= 1'b1; // RA10 is don't care
|
||||
end
|
||||
if (S==3 && !RASr2 && IS==15) Ready <= 1'b1;
|
||||
nRowColSel <= 1'b0; // Select registered row address
|
||||
RCKEEN <= 1'b1;
|
||||
end else begin
|
||||
// NOP
|
||||
nRCS <= 1'b1;
|
||||
nRRAS <= 1'b1;
|
||||
nRCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
RA10 <= 1'b1; // RA10 is don't care
|
||||
nRowColSel <= 1'b0; // Select registered row address
|
||||
RCKEEN <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
/* Submit command when PHI2 falls */
|
||||
always @(negedge PHI2) begin
|
||||
// Magic number check
|
||||
if (C1WR && Din[7:0]==8'hC1) begin // "C1" magic number
|
||||
if (ADSubmitted) begin
|
||||
CmdEnable <= 1'b1;
|
||||
end
|
||||
C1Submitted <= 1'b1;
|
||||
ADSubmitted <= 1'b0;
|
||||
end else if (ADWR && Din[7:0]==8'hAD) begin // "AD" magic number
|
||||
if (C1Submitted) begin
|
||||
CmdEnable <= 1'b1;
|
||||
end
|
||||
ADSubmitted <= 1'b1;
|
||||
C1Submitted <= 1'b0;
|
||||
end else if (C1WR || ADWR) begin // wrong magic number submitted
|
||||
CmdEnable <= 1'b0;
|
||||
C1Submitted <= 1'b0;
|
||||
ADSubmitted <= 1'b0;
|
||||
end else if (CMDWR) CmdEnable <= 1'b0;
|
||||
|
||||
// Submit command
|
||||
if (CMDWR && CmdEnable) begin
|
||||
// if (Din[7:4]==4'h0 && Din[3:2]==2'b00) begin // MAX w/LED
|
||||
// if (Din[7:4]==4'h0) begin // MAX w/o LED
|
||||
// if (Din[7:4]==4'h0 && Din[3:2]==2'b01) begin // LCMXO / iCE40 / AGM
|
||||
if (Din[7:4]==4'h0 && Din[3:2]==2'b10) begin // LCMXO2
|
||||
XOR8MEG <= Din[0] && !(LEDEN && Din[1]);
|
||||
CmdValid <= 1'b0;
|
||||
end else if (Din[7:4]==4'h0) begin // Unsupported type
|
||||
XOR8MEG <= 0;
|
||||
CmdValid <= 1'b0;
|
||||
end else if (Din[7:4]==4'h1) begin
|
||||
CmdLEDEN <= Din[1];
|
||||
Cmdn8MEGEN <= !Din[0];
|
||||
CmdUFMShift <= 1'b0;
|
||||
CmdUFMWrite <= 1'b0;
|
||||
CmdValid <= 1'b1;
|
||||
end else if (Din[7:4]==4'h2) begin
|
||||
// Reserved for MAX commands
|
||||
CmdValid <= 1'b0;
|
||||
end else if (Din[7:4]==4'h3 && !Din[3]) begin
|
||||
// Reserved for SPI (LCMXO, iCE40) commands
|
||||
// Din[2] - CS
|
||||
// Din[1] - SCK
|
||||
// Din[0] - SDI
|
||||
CmdValid <= 1'b0;
|
||||
end else if (Din[7:4]==4'h3 && Din[3]) begin
|
||||
// LCMXO2 commands
|
||||
// Din[1] - Shift when low, execute when high
|
||||
// Din[0] - Shift data
|
||||
CmdUFMShift <= !Din[1];
|
||||
CmdUFMWrite <= Din[1:0] == 2'b10;
|
||||
CmdUFMData <= Din[0];
|
||||
CmdLEDEN <= LEDEN;
|
||||
Cmdn8MEGEN <= n8MEGEN;
|
||||
CmdValid <= 1'b1;
|
||||
end else CmdValid <= 1'b0;
|
||||
end else CmdValid <= 1'b0;
|
||||
end
|
||||
|
||||
/* UFM Control */
|
||||
always @(posedge CLK) begin
|
||||
if (!InitReady && FS[17:15]==3'h0) begin
|
||||
wb_rst <= !FS[14];
|
||||
wb_we <= 1'b0;
|
||||
wb_cyc_stb <= 1'b0;
|
||||
wb_req <= 1'b0;
|
||||
wb_adr[7:0] <= 8'h00;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
end else if (!InitReady && FS[17:15]==3'h1) begin
|
||||
wb_rst <= 1'b0;
|
||||
|
||||
if (FS[8:0]==0) wb_cyc_stb <= 0;
|
||||
else if (FS[8:0]==1 && wb_req) wb_cyc_stb <= 1;
|
||||
else if (wb_ack) wb_cyc_stb <= 0;
|
||||
case (FS[14:9])
|
||||
0: begin // Open frame
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h70;
|
||||
wb_dati[7:0] <= 8'h80;
|
||||
wb_req <= 1;
|
||||
end 1: begin // Enable configuration interface - command
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h74;
|
||||
wb_req <= 1;
|
||||
end 2: begin // Enable configuration interface - operand 1/3
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h08;
|
||||
wb_req <= 1;
|
||||
end 3: begin // Enable configuration interface - operand 2/3
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_req <= 1;
|
||||
end 4: begin // Enable configuration interface - operand 3/3
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_req <= 1;
|
||||
end 5: begin // Close frame
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h70;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_req <= 1;
|
||||
|
||||
end 6: begin // Open frame
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h70;
|
||||
wb_dati[7:0] <= 8'h80;
|
||||
wb_req <= 1;
|
||||
end 7: begin // Poll status register - command
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h3C;
|
||||
wb_req <= 1;
|
||||
end 8: begin // Poll status register - operand 1/3
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_req <= 1;
|
||||
end 9: begin // Poll status register - operand 2/3
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_req <= 1;
|
||||
end 10: begin // Poll status register - operand 3/3
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_req <= 1;
|
||||
end 11, 12, 13, 14: begin // Read status register 1-4
|
||||
wb_we <= 1'b0;
|
||||
wb_adr[7:0] <= 8'h73;
|
||||
wb_dati[7:0] <= 8'h3C;
|
||||
wb_req <= 1;
|
||||
end 15: begin // Close frame
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h70;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_req <= 1;
|
||||
|
||||
end 16: begin // Open frame
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h70;
|
||||
wb_dati[7:0] <= 8'h80;
|
||||
wb_req <= 1;
|
||||
end 17: begin // Set UFM address - command
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'hB4;
|
||||
wb_req <= 1;
|
||||
end 18: begin // Set UFM address - operand 1/3
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_req <= 1;
|
||||
end 19: begin // Set UFM address - operand 2/3
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_req <= 1;
|
||||
end 20: begin // Set UFM address - operand 3/3
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_req <= 1;
|
||||
end 21: begin // Set UFM address - data 1/4
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h40;
|
||||
wb_req <= 1;
|
||||
end 22: begin // Set UFM address - data 2/4
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_req <= 1;
|
||||
end 23: begin // Set UFM address - data 3/4
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_req <= 1;
|
||||
end 24: begin // Set UFM address - data 4/4
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 190;
|
||||
wb_req <= 1;
|
||||
end 25: begin // Close frame
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h70;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_req <= 1;
|
||||
|
||||
end 26: begin // Open frame
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h70;
|
||||
wb_dati[7:0] <= 8'h80;
|
||||
wb_req <= 1;
|
||||
end 27: begin // Read UFM page - command
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'hCA;
|
||||
wb_req <= 1;
|
||||
end 28: begin // Read UFM page - operand 1/3
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h10;
|
||||
wb_req <= 1;
|
||||
end 29: begin // Read UFM page - operand 2/3
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_req <= 1;
|
||||
end 30: begin // Read UFM page - operand 3/3
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h01;
|
||||
wb_req <= 1;
|
||||
end 31: begin // Read UFM page - data 0
|
||||
wb_we <= 1'b0;
|
||||
wb_adr[7:0] <= 8'h73;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_req <= 1;
|
||||
if (wb_ack) begin
|
||||
LEDEN <= wb_dato[1];
|
||||
n8MEGEN <= wb_dato[0];
|
||||
end
|
||||
end 32, 33, 34,
|
||||
35, 36, 37, 38,
|
||||
39, 40, 41, 42,
|
||||
43, 44, 45, 46: begin // Read UFM page - data 1-15
|
||||
wb_we <= 1'b0;
|
||||
wb_adr[7:0] <= 8'h73;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_req <= 1;
|
||||
end 47: begin // Close frame
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h70;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_req <= 1;
|
||||
|
||||
end 48: begin // Open frame
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h70;
|
||||
wb_dati[7:0] <= 8'h80;
|
||||
wb_req <= 1;
|
||||
end 49: begin // Disable configuration interface - command
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h26;
|
||||
wb_req <= 1;
|
||||
end 50: begin // Disable configuration interface - operand 1/2
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_req <= 1;
|
||||
end 51: begin // Disable configuration interface - operand 2/2
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_req <= 1;
|
||||
end 52: begin // Close frame
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h70;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_req <= 1;
|
||||
|
||||
end 53: begin // Open frame
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h70;
|
||||
wb_dati[7:0] <= 8'h80;
|
||||
wb_req <= 1;
|
||||
end 54: begin // Bypass - command
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h71;
|
||||
wb_dati[7:0] <= 8'hFF;
|
||||
wb_req <= 1;
|
||||
end 55: begin // Close frame
|
||||
wb_we <= 1'b1;
|
||||
wb_adr[7:0] <= 8'h70;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_req <= 1;
|
||||
end default: begin
|
||||
wb_we <= 1'b0;
|
||||
wb_adr[7:0] <= 8'h70;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
wb_req <= 0;
|
||||
end
|
||||
endcase
|
||||
end else if (!InitReady) begin
|
||||
wb_rst <= 1'b0;
|
||||
wb_cyc_stb <= 1'b0;
|
||||
wb_req <= 1'b0;
|
||||
wb_we <= 1'b0;
|
||||
wb_adr[7:0] <= 8'h00;
|
||||
wb_dati[7:0] <= 8'h00;
|
||||
end else if (!PHI2r2 && PHI2r3 && CmdValid) begin
|
||||
wb_rst <= 1'b0;
|
||||
wb_req <= 1'b0;
|
||||
// Set user command signals after PHI2 falls
|
||||
LEDEN <= CmdLEDEN;
|
||||
n8MEGEN <= Cmdn8MEGEN;
|
||||
if (CmdUFMShift) begin
|
||||
wb_adr[7:0] <= { wb_adr[6:0], wb_dati[7] };
|
||||
wb_dati[7:0] <= { wb_dati[6:0], wb_we };
|
||||
wb_we <= CmdUFMData;
|
||||
end
|
||||
wb_cyc_stb <= CmdUFMWrite;
|
||||
end else wb_cyc_stb <= 0;
|
||||
end
|
||||
endmodule
|
||||
Loading…
x
Reference in New Issue
Block a user