mirror of
https://github.com/garrettsworkshop/RAM2GS.git
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47 lines
3.5 KiB
Plaintext
47 lines
3.5 KiB
Plaintext
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<?xml version="1.0" encoding="UTF-8"?>
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<BuildStatus>
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</Milestone>
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<Milestone name="Map" build_result="2" build_time="1629163946">
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<Task name="MapVerilogSimFile" build_result="0" update_result="3" update_time="0"/>
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<Task name="MapVHDLSimFile" build_result="0" update_result="3" update_time="0"/>
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</Milestone>
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<Task name="DEC" build_result="0" update_result="3" update_time="0"/>
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</Milestone>
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<Report name=".vdbs/RAM2GS_LCMXO256C_impl1_map.vdb" last_build_time="1629163946" last_build_size="65077"/>
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<Report name="RAM2GS_LCMXO256C_impl1.lsedata" last_build_time="1629163945" last_build_size="225954"/>
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<Report name="RAM2GS_LCMXO256C_impl1.n2e" last_build_time="1629163946" last_build_size="14598"/>
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<Report name="RAM2GS_LCMXO256C_impl1.ncd" last_build_time="1629163954" last_build_size="154201"/>
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<Report name="RAM2GS_LCMXO256C_impl1.ngd" last_build_time="1629163946" last_build_size="153868"/>
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<Report name="RAM2GS_LCMXO256C_impl1_map.ncd" last_build_time="1629163946" last_build_size="104196"/>
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</Strategy>
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</BuildStatus>
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