This commit is contained in:
Zane Kaminski 2021-10-08 21:29:42 -04:00
parent 00ffa9fa59
commit 3364401289
243 changed files with 117719 additions and 19 deletions

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[Runmanager]
Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1c\0\0\0\xd8\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0)
windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\x2\xc9\0\0\x2i\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)
headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0)
[impl1%3CStrategy1%3E]
isChecked=true
isHidden=false
isExpanded=true

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[General]
Export.auto_tasks=IBIS, Bitgen
Map.auto_tasks=MapEqu, MapTrace
PAR.auto_tasks=PARTrace, IOTiming

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[General]
COLUMN_POS_INFO_NAME_-1_0=Prioritize
COLUMN_POS_INFO_NAME_-1_1=PIO Register

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[General]
pin_sort_type=0
pin_sort_ascending=true
sig_sort_type=0
sig_sort_ascending=true
active_Sheet=Timing Preferences
[Port%20Assignments]
Name="166,0"
Group%20By="84,1"
Pin="63,2"
BANK="62,3"
IO_TYPE="117,4"
PULLMODE="119,5"
DRIVE="67,6"
SLEWRATE="92,7"
OPENDRAIN="97,8"
Outload%20%28pF%29="103,9"
MaxSkew="87,10"
Clock%20Load%20Only="121,11"
sort_columns="Name,Ascending"
[Pin%20Assignments]
Pin="90,0"
Pad%20Name="89,1"
Dual%20Function="109,2"
Polarity="77,3"
BANK="0,4"
IO_TYPE="117,5"
Signal%20Name="123,6"
Signal%20Type="115,7"
sort_columns="Pin,Ascending"
[Clock%20Resource]
Clock%20Type="100,ELLIPSIS"
Clock%20Name="100,ELLIPSIS"
Selection="100,ELLIPSIS"
[Global%20Preferences]
Preference%20Name="222,ELLIPSIS"
Preference%20Value="236,ELLIPSIS"
[Cell%20Mapping]
Type="100,ELLIPSIS"
Name="100,ELLIPSIS"
Din\Dout="100,ELLIPSIS"
PIO%20Register="100,ELLIPSIS"
[Route%20Priority]
Type="100,ELLIPSIS"
Name="100,ELLIPSIS"
Prioritize="100,ELLIPSIS"
[Timing%20Preferences]
Preference%20Name="246,ELLIPSIS"
Preference%20Value="104,ELLIPSIS"
Preference%20Unit="1012,ELLIPSIS"
[Group]
Group%20Type\Name="134,ELLIPSIS"
Value="1245,ELLIPSIS"
[Misc%20Preferences]
Preference%20Name="117,ELLIPSIS"
Preference%20Value="104,ELLIPSIS"

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<?xml version="1.0" encoding="UTF-8"?>
<BaliProject version="3.2" title="RAM2GS_LCMXO256C" device="LCMXO256C-3T100C" default_implementation="impl1">
<Options/>
<Implementation title="impl1" dir="impl1" description="impl1" synthesis="lse" default_strategy="Strategy1">
<Options def_top="RAM2GS"/>
<Source name="../RAM2GS-LCMXO.v" type="Verilog" type_short="Verilog">
<Options top_module="RAM2GS"/>
</Source>
<Source name="RAM2GS_LCMXO256C.lpf" type="Logic Preference" type_short="LPF">
<Options/>
</Source>
</Implementation>
<Strategy name="Strategy1" file="RAM2GS_LCMXO256C1.sty"/>
</BaliProject>

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BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
LOCATE COMP "Dout[0]" SITE "1" ;
LOCATE COMP "Dout[6]" SITE "2" ;
LOCATE COMP "Dout[7]" SITE "3" ;
LOCATE COMP "Dout[4]" SITE "4" ;
LOCATE COMP "Dout[5]" SITE "5" ;
LOCATE COMP "Dout[3]" SITE "6" ;
LOCATE COMP "Dout[1]" SITE "7" ;
LOCATE COMP "Dout[2]" SITE "8" ;
LOCATE COMP "Din[2]" SITE "14" ;
LOCATE COMP "Din[1]" SITE "15" ;
LOCATE COMP "Din[3]" SITE "16" ;
LOCATE COMP "Din[5]" SITE "17" ;
LOCATE COMP "Din[4]" SITE "18" ;
LOCATE COMP "Din[7]" SITE "19" ;
LOCATE COMP "Din[6]" SITE "20" ;
LOCATE COMP "Din[0]" SITE "21" ;
LOCATE COMP "LED" SITE "57" ;
LOCATE COMP "RA[0]" SITE "98" ;
LOCATE COMP "RA[1]" SITE "89" ;
LOCATE COMP "RA[2]" SITE "94" ;
LOCATE COMP "RA[3]" SITE "97" ;
LOCATE COMP "RA[4]" SITE "99" ;
LOCATE COMP "RA[5]" SITE "95" ;
LOCATE COMP "RA[6]" SITE "91" ;
LOCATE COMP "RA[7]" SITE "100" ;
LOCATE COMP "RA[8]" SITE "96" ;
LOCATE COMP "RA[9]" SITE "85" ;
LOCATE COMP "RA[10]" SITE "87" ;
LOCATE COMP "RA[11]" SITE "79" ;
LOCATE COMP "RBA[1]" SITE "83" ;
LOCATE COMP "RBA[0]" SITE "63" ;
LOCATE COMP "RCKE" SITE "82" ;
LOCATE COMP "RDQMH" SITE "76" ;
LOCATE COMP "RDQML" SITE "61" ;
LOCATE COMP "UFMCLK" SITE "58" ;
LOCATE COMP "UFMSDI" SITE "56" ;
LOCATE COMP "nUFMCS" SITE "53" ;
LOCATE COMP "nRCAS" SITE "78" ;
LOCATE COMP "nRCS" SITE "77" ;
LOCATE COMP "nRRAS" SITE "73" ;
LOCATE COMP "nRWE" SITE "72" ;
LOCATE COMP "RD[0]" SITE "64" ;
LOCATE COMP "RD[1]" SITE "65" ;
LOCATE COMP "RD[2]" SITE "66" ;
LOCATE COMP "RD[3]" SITE "67" ;
LOCATE COMP "RD[4]" SITE "68" ;
LOCATE COMP "RD[5]" SITE "69" ;
LOCATE COMP "RD[6]" SITE "70" ;
LOCATE COMP "RD[7]" SITE "71" ;
LOCATE COMP "PHI2" SITE "39" ;
LOCATE COMP "RCLK" SITE "86" ;
LOCATE COMP "nCCAS" SITE "27" ;
LOCATE COMP "nCRAS" SITE "43" ;
LOCATE COMP "CROW[0]" SITE "32" ;
LOCATE COMP "CROW[1]" SITE "34" ;
LOCATE COMP "UFMSDO" SITE "55" ;
LOCATE COMP "nFWE" SITE "22" ;
LOCATE COMP "MAin[0]" SITE "23" ;
LOCATE COMP "MAin[1]" SITE "38" ;
LOCATE COMP "MAin[2]" SITE "37" ;
LOCATE COMP "MAin[3]" SITE "47" ;
LOCATE COMP "MAin[4]" SITE "46" ;
LOCATE COMP "MAin[5]" SITE "45" ;
LOCATE COMP "MAin[6]" SITE "49" ;
LOCATE COMP "MAin[7]" SITE "44" ;
LOCATE COMP "MAin[8]" SITE "50" ;
LOCATE COMP "MAin[9]" SITE "51" ;
IOBUF PORT "CROW[0]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "CROW[1]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "nCRAS" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "nCCAS" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "RCLK" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "PHI2" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "Din[0]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "Din[1]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "Din[2]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "Din[3]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "Din[4]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "Din[5]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "Din[6]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "Din[7]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "MAin[0]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "MAin[1]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "MAin[2]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "MAin[3]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "MAin[4]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "MAin[5]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "MAin[6]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "MAin[7]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "MAin[8]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "MAin[9]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "UFMSDO" PULLMODE=KEEPER IO_TYPE=LVTTL33 ;
IOBUF PORT "nFWE" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "Dout[0]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "Dout[1]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "Dout[2]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "Dout[3]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "Dout[4]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "Dout[5]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "Dout[6]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "Dout[7]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "LED" PULLMODE=NONE IO_TYPE=LVTTL33 DRIVE=16 SLEWRATE=SLOW ;
IOBUF PORT "RA[0]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RA[1]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RA[2]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RA[3]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RA[4]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RA[5]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RA[6]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RA[7]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RA[8]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RA[9]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RA[10]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RA[11]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RBA[0]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RBA[1]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RCKE" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RDQMH" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RDQML" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "UFMCLK" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "UFMSDI" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "nRCAS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "nRCS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "nRRAS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "nRWE" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "nUFMCS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RD[0]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
IOBUF PORT "RD[1]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
IOBUF PORT "RD[2]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
IOBUF PORT "RD[3]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
IOBUF PORT "RD[4]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
IOBUF PORT "RD[5]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
IOBUF PORT "RD[6]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
IOBUF PORT "RD[7]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
OUTPUT PORT "RD[7]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[0]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[1]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[2]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[3]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[4]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[5]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[6]" LOAD 20.000000 pF ;
OUTPUT PORT "nUFMCS" LOAD 15.000000 pF ;
OUTPUT PORT "UFMCLK" LOAD 15.000000 pF ;
OUTPUT PORT "UFMSDI" LOAD 15.000000 pF ;
OUTPUT PORT "nRWE" LOAD 10.000000 pF ;
OUTPUT PORT "nRCAS" LOAD 10.000000 pF ;
OUTPUT PORT "nRCS" LOAD 10.000000 pF ;
OUTPUT PORT "nRRAS" LOAD 10.000000 pF ;
OUTPUT PORT "RDQML" LOAD 10.000000 pF ;
OUTPUT PORT "RDQMH" LOAD 10.000000 pF ;
OUTPUT PORT "RCKE" LOAD 10.000000 pF ;
OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ;
OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[11]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[10]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[9]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[8]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[7]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[6]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[5]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[4]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[3]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[2]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[1]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[0]" LOAD 10.000000 pF ;
OUTPUT PORT "LED" LOAD 25.000000 pF ;
OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ;
USE PRIMARY NET "PHI2_c" ;
USE PRIMARY NET "RCLK_c" ;
VOLTAGE 3.300 V;
VCCIO_DERATE BANK 0 PERCENT -5;
VCCIO_DERATE PERCENT -5;
VCCIO_DERATE BANK 1 PERCENT -5;
PERIOD NET "PHI2_c" 350.000000 ns ;
PERIOD NET "nCCAS_c" 350.000000 ns ;
PERIOD NET "nCRAS_c" 350.000000 ns ;
PERIOD NET "RCLK_c" 16.000000 ns ;
CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
USE PRIMARY NET "nCCAS_c" ;
USE PRIMARY NET "nCRAS_c" ;

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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE strategy>
<Strategy version="1.0" predefined="0" description="" label="Strategy1">
<Property name="PROP_BD_CmdLineArgs" value="" time="0"/>
<Property name="PROP_BD_EdfHardtimer" value="Enable" time="0"/>
<Property name="PROP_BD_EdfInBusNameConv" value="None" time="0"/>
<Property name="PROP_BD_EdfInLibPath" value="" time="0"/>
<Property name="PROP_BD_EdfInRemLoc" value="Off" time="0"/>
<Property name="PROP_BD_EdfMemPath" value="" time="0"/>
<Property name="PROP_BD_ParSearchPath" value="" time="0"/>
<Property name="PROP_BIT_AddressBitGen" value="Increment" time="0"/>
<Property name="PROP_BIT_AllowReadBitGen" value="Disable" time="0"/>
<Property name="PROP_BIT_ByteWideBitMirror" value="Disable" time="0"/>
<Property name="PROP_BIT_CapReadBitGen" value="Disable" time="0"/>
<Property name="PROP_BIT_ConModBitGen" value="Disable" time="0"/>
<Property name="PROP_BIT_CreateBitFile" value="True" time="0"/>
<Property name="PROP_BIT_DisRAMResBitGen" value="True" time="0"/>
<Property name="PROP_BIT_DisableUESBitgen" value="False" time="0"/>
<Property name="PROP_BIT_DonePinBitGen" value="Pullup" time="0"/>
<Property name="PROP_BIT_DoneSigBitGen" value="4" time="0"/>
<Property name="PROP_BIT_EnIOBitGen" value="TriStateDuringReConfig" time="0"/>
<Property name="PROP_BIT_EnIntOscBitGen" value="Disable" time="0"/>
<Property name="PROP_BIT_ExtClockBitGen" value="False" time="0"/>
<Property name="PROP_BIT_GSREnableBitGen" value="True" time="0"/>
<Property name="PROP_BIT_GSRRelOnBitGen" value="DoneIn" time="0"/>
<Property name="PROP_BIT_GranTimBitGen" value="0" time="0"/>
<Property name="PROP_BIT_IOTriRelBitGen" value="Cycle 2" time="0"/>
<Property name="PROP_BIT_JTAGEnableBitGen" value="False" time="0"/>
<Property name="PROP_BIT_LenBitsBitGen" value="24" time="0"/>
<Property name="PROP_BIT_MIFFileBitGen" value="" time="0"/>
<Property name="PROP_BIT_NoHeader" value="False" time="0"/>
<Property name="PROP_BIT_OutFormatBitGen" value="Bit File (Binary)" time="0"/>
<Property name="PROP_BIT_OutFormatBitGen_REF" value="" time="0"/>
<Property name="PROP_BIT_OutFormatPromGen" value="Intel Hex 32-bit" time="0"/>
<Property name="PROP_BIT_ParityCheckBitGen" value="True" time="0"/>
<Property name="PROP_BIT_ReadBackBitGen" value="Flash" time="0"/>
<Property name="PROP_BIT_ReadCaptureBitGen" value="Disable" time="0"/>
<Property name="PROP_BIT_RemZeroFramesBitGen" value="False" time="0"/>
<Property name="PROP_BIT_RunDRCBitGen" value="True" time="0"/>
<Property name="PROP_BIT_SearchPthBitGen" value="" time="0"/>
<Property name="PROP_BIT_StartUpClkBitGen" value="Cclk" time="0"/>
<Property name="PROP_BIT_SynchIOBitGen" value="True" time="0"/>
<Property name="PROP_BIT_SysClockConBitGen" value="Reset" time="0"/>
<Property name="PROP_BIT_SysConBitGen" value="Reset" time="0"/>
<Property name="PROP_BIT_WaitStTimBitGen" value="5" time="0"/>
<Property name="PROP_IOTIMING_AllSpeed" value="False" time="0"/>
<Property name="PROP_LST_AllowDUPMod" value="False" time="0"/>
<Property name="PROP_LST_CarryChain" value="True" time="0"/>
<Property name="PROP_LST_CarryChainLength" value="0" time="0"/>
<Property name="PROP_LST_CmdLineArgs" value="" time="0"/>
<Property name="PROP_LST_DSPStyle" value="DSP" time="0"/>
<Property name="PROP_LST_DSPUtil" value="100" time="0"/>
<Property name="PROP_LST_DecodeUnreachableStates" value="False" time="0"/>
<Property name="PROP_LST_DisableDistRam" value="False" time="0"/>
<Property name="PROP_LST_EBRUtil" value="100" time="0"/>
<Property name="PROP_LST_EdfFrequency" value="200" time="0"/>
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<Property name="PROP_PARSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
<Property name="PROP_PARSTA_RptAsynTimLoop" value="False" time="0"/>
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<Property name="PROP_PAR_EffortParDes" value="5" time="0"/>
<Property name="PROP_PAR_MultiSeedSortMode" value="Worst Slack" time="0"/>
<Property name="PROP_PAR_NewRouteParDes" value="NBR" time="0"/>
<Property name="PROP_PAR_PARClockSkew" value="Off" time="0"/>
<Property name="PROP_PAR_PARModArgs" value="" time="0"/>
<Property name="PROP_PAR_ParMultiNodeList" value="" time="0"/>
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<Property name="PROP_PAR_PlcIterParDes" value="1" time="0"/>
<Property name="PROP_PAR_PlcStCostTblParDes" value="1" time="0"/>
<Property name="PROP_PAR_PrefErrorOut" value="True" time="0"/>
<Property name="PROP_PAR_RemoveDir" value="True" time="0"/>
<Property name="PROP_PAR_RouteDlyRedParDes" value="0" time="0"/>
<Property name="PROP_PAR_RoutePassParDes" value="6" time="0"/>
<Property name="PROP_PAR_RouteResOptParDes" value="0" time="0"/>
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<Property name="PROP_PAR_RoutingCDR" value="0" time="0"/>
<Property name="PROP_PAR_RunParWithTrce" value="False" time="0"/>
<Property name="PROP_PAR_RunTimeReduction" value="True" time="0"/>
<Property name="PROP_PAR_SaveBestRsltParDes" value="1" time="0"/>
<Property name="PROP_PAR_StopZero" value="False" time="0"/>
<Property name="PROP_PAR_parHold" value="On" time="0"/>
<Property name="PROP_PAR_parPathBased" value="Off" time="0"/>
<Property name="PROP_PRE_CmdLineArgs" value="" time="0"/>
<Property name="PROP_PRE_EdfArrayBoundsCase" value="False" time="0"/>
<Property name="PROP_PRE_EdfAutoResOfRam" value="False" time="0"/>
<Property name="PROP_PRE_EdfClockDomainCross" value="False" time="0"/>
<Property name="PROP_PRE_EdfDSPAcrossHie" value="False" time="0"/>
<Property name="PROP_PRE_EdfFullCase" value="False" time="0"/>
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<Property name="PROP_PRE_EdfMissConstraint" value="False" time="0"/>
<Property name="PROP_PRE_EdfNetFanout" value="True" time="0"/>
<Property name="PROP_PRE_EdfParaCase" value="False" time="0"/>
<Property name="PROP_PRE_EdfReencodeFSM" value="True" time="0"/>
<Property name="PROP_PRE_EdfResSharing" value="True" time="0"/>
<Property name="PROP_PRE_EdfTimingViolation" value="True" time="0"/>
<Property name="PROP_PRE_EdfUseSafeFSM" value="False" time="0"/>
<Property name="PROP_PRE_EdfVlog2001" value="True" time="0"/>
<Property name="PROP_PRE_VSynComArea" value="True" time="0"/>
<Property name="PROP_PRE_VSynCritcal" value="3" time="0"/>
<Property name="PROP_PRE_VSynFSM" value="Auto" time="0"/>
<Property name="PROP_PRE_VSynFreq" value="200" time="0"/>
<Property name="PROP_PRE_VSynGSR" value="False" time="0"/>
<Property name="PROP_PRE_VSynGatedClk" value="False" time="0"/>
<Property name="PROP_PRE_VSynIOPad" value="False" time="0"/>
<Property name="PROP_PRE_VSynOutNetForm" value="None" time="0"/>
<Property name="PROP_PRE_VSynOutPref" value="True" time="0"/>
<Property name="PROP_PRE_VSynRepClkFreq" value="True" time="0"/>
<Property name="PROP_PRE_VSynRetime" value="True" time="0"/>
<Property name="PROP_PRE_VSynTimSum" value="10" time="0"/>
<Property name="PROP_PRE_VSynTransform" value="True" time="0"/>
<Property name="PROP_PRE_VSyninpd" value="0" time="0"/>
<Property name="PROP_PRE_VSynoutd" value="0" time="0"/>
<Property name="PROP_SYN_ClockConversion" value="True" time="0"/>
<Property name="PROP_SYN_CmdLineArgs" value="" time="0"/>
<Property name="PROP_SYN_DisableRegisterRep" value="False" time="0"/>
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<Property name="PROP_SYN_EdfFanout" value="1000" time="0"/>
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<Property name="PROP_SYN_EdfPushTirstates" value="True" time="0"/>
<Property name="PROP_SYN_EdfResSharing" value="True" time="0"/>
<Property name="PROP_SYN_EdfRunRetiming" value="Pipelining Only" time="0"/>
<Property name="PROP_SYN_EdfSymFSM" value="True" time="0"/>
<Property name="PROP_SYN_EdfUnconsClk" value="False" time="0"/>
<Property name="PROP_SYN_EdfVerilogInput" value="Verilog 2001" time="0"/>
<Property name="PROP_SYN_ExportSetting" value="No" time="0"/>
<Property name="PROP_SYN_LibPath" value="" time="0"/>
<Property name="PROP_SYN_ResolvedMixedDrivers" value="False" time="0"/>
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<Property name="PROP_THERMAL_DefaultFreq" value="0" time="0"/>
<Property name="PROP_TIM_MaxDelSimDes" value="" time="0"/>
<Property name="PROP_TIM_MinSpeedGrade" value="False" time="0"/>
<Property name="PROP_TIM_ModPreSimDes" value="" time="0"/>
<Property name="PROP_TIM_NegStupHldTim" value="True" time="0"/>
<Property name="PROP_TIM_TimSimGenPUR" value="True" time="0"/>
<Property name="PROP_TIM_TimSimGenX" value="False" time="0"/>
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<Property name="PROP_TIM_WriteVerboseNetlist" value="False" time="0"/>
<Property name="PROP_TMCHK_EnableCheck" value="True" time="0"/>
</Strategy>

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<HTML>
<HEAD><TITLE>Lattice TCL Log</TITLE>
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<PRE><A name="pn210816194012"></A><B><U><big>pn210816194012</big></U></B>
#Start recording tcl command: 8/16/2021 19:02:08
#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C; Project name: RAM2GS_LCMXO256C
prj_project new -name "RAM2GS_LCMXO256C" -impl "impl1" -dev LCMXO256C-3T100C -synthesis "lse"
prj_src add "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM4GS-LCMXO.v"
prj_project save
prj_src remove "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM4GS-LCMXO.v"
prj_src add "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v"
prj_run PAR -impl impl1
prj_run PAR -impl impl1
prj_run Map -impl impl1
prj_run Export -impl impl1
prj_run PAR -impl impl1
prj_run Map -impl impl1
prj_run PAR -impl impl1
prj_run Export -impl impl1 -forceAll
prj_run Export -impl impl1 -forceAll
#Stop recording: 8/16/2021 19:40:12
<A name="pn210816202808"></A><B><U><big>pn210816202808</big></U></B>
#Start recording tcl command: 8/16/2021 20:24:10
#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C; Project name: RAM2GS_LCMXO256C
prj_project open "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.ldf"
prj_run Export -impl impl1 -forceAll
#Stop recording: 8/16/2021 20:28:08
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</BODY>
</HTML>

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#Start recording tcl command: 8/16/2021 19:02:08
#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C; Project name: RAM2GS_LCMXO256C
prj_project new -name "RAM2GS_LCMXO256C" -impl "impl1" -dev LCMXO256C-3T100C -synthesis "lse"
prj_src add "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM4GS-LCMXO.v"
prj_project save
prj_src remove "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM4GS-LCMXO.v"
prj_src add "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v"
prj_run PAR -impl impl1
prj_run PAR -impl impl1
prj_run Map -impl impl1
prj_run Export -impl impl1
prj_run PAR -impl impl1
prj_run Map -impl impl1
prj_run PAR -impl impl1
prj_run Export -impl impl1 -forceAll
prj_run Export -impl impl1 -forceAll
#Stop recording: 8/16/2021 19:40:12

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#Start recording tcl command: 8/16/2021 20:24:10
#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C; Project name: RAM2GS_LCMXO256C
prj_project open "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.ldf"
prj_run Export -impl impl1 -forceAll
#Stop recording: 8/16/2021 20:28:08

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#Start recording tcl command: 8/16/2021 21:33:16
#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C; Project name: RAM2GS_LCMXO256C
prj_project open "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.ldf"
#Stop recording: 8/16/2021 21:33:22

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#Start recording tcl command: 8/16/2021 21:32:14
#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C; Project name: RAM2GS_LCMXO256C
prj_project open "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.ldf"
prj_run Export -impl impl1 -forceAll
prj_run Export -impl impl1 -forceOne
#Stop recording: 8/16/2021 21:41:12

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@ -0,0 +1,46 @@
<?xml version="1.0" encoding="UTF-8"?>
<BuildStatus>
<Strategy name="Strategy1">
<Milestone name="Export" build_result="0" build_time="0">
<Task name="IBIS" build_result="0" update_result="2" update_time="1629164185"/>
<Task name="TimingSimFileVlg" build_result="0" update_result="3" update_time="0"/>
<Task name="TimingSimFileVHD" build_result="0" update_result="3" update_time="0"/>
<Task name="Bitgen" build_result="2" update_result="0" update_time="1629164189"/>
</Milestone>
<Milestone name="Map" build_result="2" build_time="1629163946">
<Task name="Map" build_result="2" update_result="0" update_time="1629163946"/>
<Task name="MapEqu" build_result="2" update_result="0" update_time="1629163946"/>
<Task name="MapTrace" build_result="2" update_result="0" update_time="1629163947"/>
<Task name="MapVerilogSimFile" build_result="0" update_result="3" update_time="0"/>
<Task name="MapVHDLSimFile" build_result="0" update_result="3" update_time="0"/>
</Milestone>
<Milestone name="PAR" build_result="2" build_time="1629163954">
<Task name="PAR" build_result="2" update_result="0" update_time="1629163954"/>
<Task name="PARTrace" build_result="2" update_result="0" update_time="1629163954"/>
<Task name="IOTiming" build_result="2" update_result="0" update_time="1629163954"/>
</Milestone>
<Milestone name="Synthesis" build_result="2" build_time="1629163946">
<Task name="Lattice_Synthesis" build_result="2" update_result="0" update_time="1629163946"/>
<Task name="LSE_Compile" build_result="2" update_result="0" update_time="1629163959"/>
</Milestone>
<Milestone name="TOOL_Report" build_result="0" build_time="0">
<Task name="HDLE" build_result="2" update_result="0" update_time="1629163934"/>
<Task name="BKM" build_result="0" update_result="2" update_time="1629163934"/>
<Task name="SSO" build_result="0" update_result="3" update_time="0"/>
<Task name="PIODRC" build_result="0" update_result="3" update_time="0"/>
<Task name="DEC" build_result="0" update_result="3" update_time="0"/>
</Milestone>
<Report name=".vdbs/RAM2GS_LCMXO256C_impl1_map.vdb" last_build_time="1629163946" last_build_size="65077"/>
<Report name="IBIS/RAM2GS_LCMXO256C_impl1.ibs" last_build_time="0" last_build_size="0"/>
<Report name="RAM2GS_LCMXO256C_impl1.bgn" last_build_time="1629164186" last_build_size="2011"/>
<Report name="RAM2GS_LCMXO256C_impl1.ior" last_build_time="1629163954" last_build_size="6686"/>
<Report name="RAM2GS_LCMXO256C_impl1.jed" last_build_time="1629164189" last_build_size="61054"/>
<Report name="RAM2GS_LCMXO256C_impl1.lsedata" last_build_time="1629163945" last_build_size="225954"/>
<Report name="RAM2GS_LCMXO256C_impl1.n2e" last_build_time="1629163946" last_build_size="14598"/>
<Report name="RAM2GS_LCMXO256C_impl1.ncd" last_build_time="1629163954" last_build_size="154201"/>
<Report name="RAM2GS_LCMXO256C_impl1.ngd" last_build_time="1629163946" last_build_size="153868"/>
<Report name="RAM2GS_LCMXO256C_impl1.tw1" last_build_time="1629163947" last_build_size="111690"/>
<Report name="RAM2GS_LCMXO256C_impl1.twr" last_build_time="1629163954" last_build_size="187578"/>
<Report name="RAM2GS_LCMXO256C_impl1_map.ncd" last_build_time="1629163946" last_build_size="104196"/>
</Strategy>
</BuildStatus>

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RAM2GS_rtl.vdb

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NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
NOTE All Rights Reserved *
NOTE DATE CREATED: Mon Aug 16 21:36:26 2021 *
NOTE DESIGN NAME: RAM2GS *
NOTE DEVICE NAME: LCMXO256C-3TQFP100 *
NOTE PIN ASSIGNMENTS *
NOTE PINS RD[7] : 71 : inout *
NOTE PINS RD[6] : 70 : inout *
NOTE PINS RD[5] : 69 : inout *
NOTE PINS RD[4] : 68 : inout *
NOTE PINS RD[3] : 67 : inout *
NOTE PINS RD[2] : 66 : inout *
NOTE PINS RD[1] : 65 : inout *
NOTE PINS RD[0] : 64 : inout *
NOTE PINS Dout[7] : 3 : out *
NOTE PINS Dout[6] : 2 : out *
NOTE PINS Dout[5] : 5 : out *
NOTE PINS Dout[4] : 4 : out *
NOTE PINS Dout[3] : 6 : out *
NOTE PINS Dout[2] : 8 : out *
NOTE PINS Dout[1] : 7 : out *
NOTE PINS Dout[0] : 1 : out *
NOTE PINS LED : 57 : out *
NOTE PINS RBA[1] : 83 : out *
NOTE PINS RBA[0] : 63 : out *
NOTE PINS RA[11] : 79 : out *
NOTE PINS RA[10] : 87 : out *
NOTE PINS RA[9] : 85 : out *
NOTE PINS RA[8] : 96 : out *
NOTE PINS RA[7] : 100 : out *
NOTE PINS RA[6] : 91 : out *
NOTE PINS RA[5] : 95 : out *
NOTE PINS RA[4] : 99 : out *
NOTE PINS RA[3] : 97 : out *
NOTE PINS RA[2] : 94 : out *
NOTE PINS RA[1] : 89 : out *
NOTE PINS RA[0] : 98 : out *
NOTE PINS nRCS : 77 : out *
NOTE PINS RCKE : 82 : out *
NOTE PINS nRWE : 72 : out *
NOTE PINS nRRAS : 73 : out *
NOTE PINS nRCAS : 78 : out *
NOTE PINS RDQMH : 76 : out *
NOTE PINS RDQML : 61 : out *
NOTE PINS nUFMCS : 53 : out *
NOTE PINS UFMCLK : 58 : out *
NOTE PINS UFMSDI : 56 : out *
NOTE PINS PHI2 : 39 : in *
NOTE PINS MAin[9] : 51 : in *
NOTE PINS MAin[8] : 50 : in *
NOTE PINS MAin[7] : 44 : in *
NOTE PINS MAin[6] : 49 : in *
NOTE PINS MAin[5] : 45 : in *
NOTE PINS MAin[4] : 46 : in *
NOTE PINS MAin[3] : 47 : in *
NOTE PINS MAin[2] : 37 : in *
NOTE PINS MAin[1] : 38 : in *
NOTE PINS MAin[0] : 23 : in *
NOTE PINS CROW[1] : 34 : in *
NOTE PINS CROW[0] : 32 : in *
NOTE PINS Din[7] : 19 : in *
NOTE PINS Din[6] : 20 : in *
NOTE PINS Din[5] : 17 : in *
NOTE PINS Din[4] : 18 : in *
NOTE PINS Din[3] : 16 : in *
NOTE PINS Din[2] : 14 : in *
NOTE PINS Din[1] : 15 : in *
NOTE PINS Din[0] : 21 : in *
NOTE PINS nCCAS : 27 : in *
NOTE PINS nCRAS : 43 : in *
NOTE PINS nFWE : 22 : in *
NOTE PINS RCLK : 86 : in *
NOTE PINS UFMSDO : 55 : in *
NOTE CONFIGURATION MODE: NONE *
NOTE COMPRESSION: off *

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@ -0,0 +1,24 @@
----------------------------------------------------------------------
Report for cell RAM2GS.TECH
Register bits: 102 of 490 (20.816%)
I/O cells: 67
Cell usage:
cell count Res Usage(%)
BB 8 100.0
CCU2 9 100.0
FD1P3AX 28 100.0
FD1P3AY 3 100.0
FD1P3IX 2 100.0
FD1P3JX 1 100.0
FD1S3AX 47 100.0
FD1S3AY 1 100.0
FD1S3IX 16 100.0
FD1S3JX 4 100.0
GSR 1 100.0
IB 26 100.0
INV 3 100.0
LUT4 114 100.0
OB 33 100.0
ORCALUT4 2 100.0
PFUMX 3 100.0
TOTAL 301

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@ -0,0 +1,45 @@
BITGEN: Bitstream Generator Diamond (64-bit) 3.12.0.240.2
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Mon Aug 16 21:36:25 2021
Command: bitgen -w -g ES:No -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf
Loading design for application Bitgen from file RAM2GS_LCMXO256C_impl1.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO256C
Package: TQFP100
Performance: 3
Loading device for application Bitgen from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.19.
Performance Hardware Data Status: Version 1.124.
Running DRC.
DRC detected 0 errors and 0 warnings.
Reading Preference File from RAM2GS_LCMXO256C_impl1.prf.
Preference Summary:
+---------------------------------+---------------------------------+
| Preference | Current Setting |
+---------------------------------+---------------------------------+
| CONFIG_SECURE | OFF** |
+---------------------------------+---------------------------------+
| INBUF | ON** |
+---------------------------------+---------------------------------+
| ES | No** |
+---------------------------------+---------------------------------+
* Default setting.
** The specified setting matches the default setting.
Creating bit map...
Saving bit stream in "RAM2GS_LCMXO256C_impl1.bit".
Total CPU Time: 0 secs
Total REAL Time: 0 secs
Peak Memory Usage: 44 MB

Binary file not shown.

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@ -0,0 +1,271 @@
PAD Specification File
***************************
PART TYPE: LCMXO256C
Performance Grade: 3
PACKAGE: TQFP100
Package Status: Final Version 1.19
Mon Aug 16 21:32:33 2021
Pinout by Port Name:
+-----------+----------+--------------+------+----------------------------------+
| Port Name | Pin/Bank | Buffer Type | Site | Properties |
+-----------+----------+--------------+------+----------------------------------+
| CROW[0] | 32/1 | LVTTL33_IN | PB2C | SLEW:FAST |
| CROW[1] | 34/1 | LVTTL33_IN | PB2D | SLEW:FAST |
| Din[0] | 21/1 | LVTTL33_IN | PL8A | SLEW:FAST |
| Din[1] | 15/1 | LVTTL33_IN | PL6A | SLEW:FAST |
| Din[2] | 14/1 | LVTTL33_IN | PL5D | SLEW:FAST |
| Din[3] | 16/1 | LVTTL33_IN | PL6B | SLEW:FAST |
| Din[4] | 18/1 | LVTTL33_IN | PL7B | SLEW:FAST |
| Din[5] | 17/1 | LVTTL33_IN | PL7A | SLEW:FAST |
| Din[6] | 20/1 | LVTTL33_IN | PL7D | SLEW:FAST |
| Din[7] | 19/1 | LVTTL33_IN | PL7C | SLEW:FAST |
| Dout[0] | 1/1 | LVTTL33_OUT | PL2A | DRIVE:4mA SLEW:SLOW |
| Dout[1] | 7/1 | LVTTL33_OUT | PL4A | DRIVE:4mA SLEW:SLOW |
| Dout[2] | 8/1 | LVTTL33_OUT | PL4B | DRIVE:4mA SLEW:SLOW |
| Dout[3] | 6/1 | LVTTL33_OUT | PL3D | DRIVE:4mA SLEW:SLOW |
| Dout[4] | 4/1 | LVTTL33_OUT | PL3B | DRIVE:4mA SLEW:SLOW |
| Dout[5] | 5/1 | LVTTL33_OUT | PL3C | DRIVE:4mA SLEW:SLOW |
| Dout[6] | 2/1 | LVTTL33_OUT | PL2B | DRIVE:4mA SLEW:SLOW |
| Dout[7] | 3/1 | LVTTL33_OUT | PL3A | DRIVE:4mA SLEW:SLOW |
| LED | 57/0 | LVTTL33_OUT | PR7B | DRIVE:16mA SLEW:SLOW |
| MAin[0] | 23/1 | LVTTL33_IN | PL9A | SLEW:FAST |
| MAin[1] | 38/1 | LVTTL33_IN | PB3C | SLEW:FAST |
| MAin[2] | 37/1 | LVTTL33_IN | PB3B | SLEW:FAST |
| MAin[3] | 47/1 | LVTTL33_IN | PB5A | SLEW:FAST |
| MAin[4] | 46/1 | LVTTL33_IN | PB4D | SLEW:FAST |
| MAin[5] | 45/1 | LVTTL33_IN | PB4C | SLEW:FAST |
| MAin[6] | 49/1 | LVTTL33_IN | PB5C | SLEW:FAST |
| MAin[7] | 44/1 | LVTTL33_IN | PB4B | SLEW:FAST |
| MAin[8] | 50/1 | LVTTL33_IN | PB5D | SLEW:FAST |
| MAin[9] | 51/0 | LVTTL33_IN | PR9B | SLEW:FAST |
| PHI2 | 39/1 | LVTTL33_IN | PB3D | SLEW:FAST |
| RA[0] | 98/0 | LVTTL33_OUT | PT2C | DRIVE:4mA SLEW:SLOW |
| RA[10] | 87/0 | LVTTL33_OUT | PT3D | DRIVE:4mA SLEW:SLOW |
| RA[11] | 79/0 | LVTTL33_OUT | PT5A | DRIVE:4mA SLEW:SLOW |
| RA[1] | 89/0 | LVTTL33_OUT | PT3C | DRIVE:4mA SLEW:SLOW |
| RA[2] | 94/0 | LVTTL33_OUT | PT3A | DRIVE:4mA SLEW:SLOW |
| RA[3] | 97/0 | LVTTL33_OUT | PT2D | DRIVE:4mA SLEW:SLOW |
| RA[4] | 99/0 | LVTTL33_OUT | PT2B | DRIVE:4mA SLEW:SLOW |
| RA[5] | 95/0 | LVTTL33_OUT | PT2F | DRIVE:4mA SLEW:SLOW |
| RA[6] | 91/0 | LVTTL33_OUT | PT3B | DRIVE:4mA SLEW:SLOW |
| RA[7] | 100/0 | LVTTL33_OUT | PT2A | DRIVE:4mA SLEW:SLOW |
| RA[8] | 96/0 | LVTTL33_OUT | PT2E | DRIVE:4mA SLEW:SLOW |
| RA[9] | 85/0 | LVTTL33_OUT | PT4B | DRIVE:4mA SLEW:SLOW |
| RBA[0] | 63/0 | LVTTL33_OUT | PR5D | DRIVE:4mA SLEW:SLOW |
| RBA[1] | 83/0 | LVTTL33_OUT | PT4C | DRIVE:4mA SLEW:SLOW |
| RCKE | 82/0 | LVTTL33_OUT | PT4D | DRIVE:4mA SLEW:SLOW |
| RCLK | 86/0 | LVTTL33_IN | PT4A | SLEW:FAST |
| RDQMH | 76/0 | LVTTL33_OUT | PR2A | DRIVE:4mA SLEW:SLOW |
| RDQML | 61/0 | LVTTL33_OUT | PR6A | DRIVE:4mA SLEW:SLOW |
| RD[0] | 64/0 | LVTTL33_BIDI | PR5C | DRIVE:4mA SLEW:SLOW PULL:KEEPER |
| RD[1] | 65/0 | LVTTL33_BIDI | PR5B | DRIVE:4mA SLEW:SLOW PULL:KEEPER |
| RD[2] | 66/0 | LVTTL33_BIDI | PR5A | DRIVE:4mA SLEW:SLOW PULL:KEEPER |
| RD[3] | 67/0 | LVTTL33_BIDI | PR4B | DRIVE:4mA SLEW:SLOW PULL:KEEPER |
| RD[4] | 68/0 | LVTTL33_BIDI | PR4A | DRIVE:4mA SLEW:SLOW PULL:KEEPER |
| RD[5] | 69/0 | LVTTL33_BIDI | PR3D | DRIVE:4mA SLEW:SLOW PULL:KEEPER |
| RD[6] | 70/0 | LVTTL33_BIDI | PR3C | DRIVE:4mA SLEW:SLOW PULL:KEEPER |
| RD[7] | 71/0 | LVTTL33_BIDI | PR3B | DRIVE:4mA SLEW:SLOW PULL:KEEPER |
| UFMCLK | 58/0 | LVTTL33_OUT | PR7A | DRIVE:4mA SLEW:SLOW |
| UFMSDI | 56/0 | LVTTL33_OUT | PR7C | DRIVE:4mA SLEW:SLOW |
| UFMSDO | 55/0 | LVTTL33_IN | PR7D | SLEW:FAST PULL:KEEPER |
| nCCAS | 27/1 | LVTTL33_IN | PL9B | SLEW:FAST |
| nCRAS | 43/1 | LVTTL33_IN | PB4A | SLEW:FAST |
| nFWE | 22/1 | LVTTL33_IN | PL8B | SLEW:FAST |
| nRCAS | 78/0 | LVTTL33_OUT | PT5B | DRIVE:4mA SLEW:SLOW |
| nRCS | 77/0 | LVTTL33_OUT | PT5C | DRIVE:4mA SLEW:SLOW |
| nRRAS | 73/0 | LVTTL33_OUT | PR2B | DRIVE:4mA SLEW:SLOW |
| nRWE | 72/0 | LVTTL33_OUT | PR3A | DRIVE:4mA SLEW:SLOW |
| nUFMCS | 53/0 | LVTTL33_OUT | PR8B | DRIVE:4mA SLEW:SLOW |
+-----------+----------+--------------+------+----------------------------------+
Vccio by Bank:
+------+-------+
| Bank | Vccio |
+------+-------+
| 0 | 3.3V |
| 1 | 3.3V |
+------+-------+
Vref by Bank:
+------+-----+-----------------+---------+
| Vref | Pin | Bank # / Vref # | Load(s) |
+------+-----+-----------------+---------+
+------+-----+-----------------+---------+
Pinout by Pin Number:
+----------+---------------------+------------+--------------+------+---------------+
| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function |
+----------+---------------------+------------+--------------+------+---------------+
| 1/1 | Dout[0] | LOCATED | LVTTL33_OUT | PL2A | |
| 2/1 | Dout[6] | LOCATED | LVTTL33_OUT | PL2B | |
| 3/1 | Dout[7] | LOCATED | LVTTL33_OUT | PL3A | |
| 4/1 | Dout[4] | LOCATED | LVTTL33_OUT | PL3B | |
| 5/1 | Dout[5] | LOCATED | LVTTL33_OUT | PL3C | |
| 6/1 | Dout[3] | LOCATED | LVTTL33_OUT | PL3D | |
| 7/1 | Dout[1] | LOCATED | LVTTL33_OUT | PL4A | |
| 8/1 | Dout[2] | LOCATED | LVTTL33_OUT | PL4B | |
| 9/1 | unused, PULL:UP | | | PL5A | |
| 11/1 | unused, PULL:UP | | | PL5B | |
| 13/1 | unused, PULL:UP | | | PL5C | |
| 14/1 | Din[2] | LOCATED | LVTTL33_IN | PL5D | GSR_PADN |
| 15/1 | Din[1] | LOCATED | LVTTL33_IN | PL6A | |
| 16/1 | Din[3] | LOCATED | LVTTL33_IN | PL6B | TSALLPAD |
| 17/1 | Din[5] | LOCATED | LVTTL33_IN | PL7A | |
| 18/1 | Din[4] | LOCATED | LVTTL33_IN | PL7B | |
| 19/1 | Din[7] | LOCATED | LVTTL33_IN | PL7C | |
| 20/1 | Din[6] | LOCATED | LVTTL33_IN | PL7D | |
| 21/1 | Din[0] | LOCATED | LVTTL33_IN | PL8A | |
| 22/1 | nFWE | LOCATED | LVTTL33_IN | PL8B | |
| 23/1 | MAin[0] | LOCATED | LVTTL33_IN | PL9A | |
| 27/1 | nCCAS | LOCATED | LVTTL33_IN | PL9B | |
| 29/1 | unused, PULL:UP | | | PB2A | |
| 30/1 | unused, PULL:UP | | | PB2B | |
| 32/1 | CROW[0] | LOCATED | LVTTL33_IN | PB2C | |
| 34/1 | CROW[1] | LOCATED | LVTTL33_IN | PB2D | |
| 36/1 | unused, PULL:UP | | | PB3A | PCLKT1_1 |
| 37/1 | MAin[2] | LOCATED | LVTTL33_IN | PB3B | |
| 38/1 | MAin[1] | LOCATED | LVTTL33_IN | PB3C | PCLKT1_0 |
| 39/1 | PHI2 | LOCATED | LVTTL33_IN | PB3D | |
| 43/1 | nCRAS | LOCATED | LVTTL33_IN | PB4A | |
| 44/1 | MAin[7] | LOCATED | LVTTL33_IN | PB4B | |
| 45/1 | MAin[5] | LOCATED | LVTTL33_IN | PB4C | |
| 46/1 | MAin[4] | LOCATED | LVTTL33_IN | PB4D | |
| 47/1 | MAin[3] | LOCATED | LVTTL33_IN | PB5A | |
| 49/1 | MAin[6] | LOCATED | LVTTL33_IN | PB5C | |
| 50/1 | MAin[8] | LOCATED | LVTTL33_IN | PB5D | |
| 51/0 | MAin[9] | LOCATED | LVTTL33_IN | PR9B | |
| 52/0 | unused, PULL:UP | | | PR9A | |
| 53/0 | nUFMCS | LOCATED | LVTTL33_OUT | PR8B | |
| 54/0 | unused, PULL:UP | | | PR8A | |
| 55/0 | UFMSDO | LOCATED | LVTTL33_IN | PR7D | |
| 56/0 | UFMSDI | LOCATED | LVTTL33_OUT | PR7C | |
| 57/0 | LED | LOCATED | LVTTL33_OUT | PR7B | |
| 58/0 | UFMCLK | LOCATED | LVTTL33_OUT | PR7A | |
| 59/0 | unused, PULL:UP | | | PR6B | |
| 61/0 | RDQML | LOCATED | LVTTL33_OUT | PR6A | |
| 63/0 | RBA[0] | LOCATED | LVTTL33_OUT | PR5D | |
| 64/0 | RD[0] | LOCATED | LVTTL33_BIDI | PR5C | |
| 65/0 | RD[1] | LOCATED | LVTTL33_BIDI | PR5B | |
| 66/0 | RD[2] | LOCATED | LVTTL33_BIDI | PR5A | |
| 67/0 | RD[3] | LOCATED | LVTTL33_BIDI | PR4B | |
| 68/0 | RD[4] | LOCATED | LVTTL33_BIDI | PR4A | |
| 69/0 | RD[5] | LOCATED | LVTTL33_BIDI | PR3D | |
| 70/0 | RD[6] | LOCATED | LVTTL33_BIDI | PR3C | |
| 71/0 | RD[7] | LOCATED | LVTTL33_BIDI | PR3B | |
| 72/0 | nRWE | LOCATED | LVTTL33_OUT | PR3A | |
| 73/0 | nRRAS | LOCATED | LVTTL33_OUT | PR2B | |
| 76/0 | RDQMH | LOCATED | LVTTL33_OUT | PR2A | |
| 77/0 | nRCS | LOCATED | LVTTL33_OUT | PT5C | |
| 78/0 | nRCAS | LOCATED | LVTTL33_OUT | PT5B | |
| 79/0 | RA[11] | LOCATED | LVTTL33_OUT | PT5A | |
| 80/0 | unused, PULL:UP | | | PT4F | |
| 81/0 | unused, PULL:UP | | | PT4E | |
| 82/0 | RCKE | LOCATED | LVTTL33_OUT | PT4D | |
| 83/0 | RBA[1] | LOCATED | LVTTL33_OUT | PT4C | |
| 85/0 | RA[9] | LOCATED | LVTTL33_OUT | PT4B | PCLKT0_1 |
| 86/0 | RCLK | LOCATED | LVTTL33_IN | PT4A | PCLKT0_0 |
| 87/0 | RA[10] | LOCATED | LVTTL33_OUT | PT3D | |
| 89/0 | RA[1] | LOCATED | LVTTL33_OUT | PT3C | |
| 91/0 | RA[6] | LOCATED | LVTTL33_OUT | PT3B | |
| 94/0 | RA[2] | LOCATED | LVTTL33_OUT | PT3A | |
| 95/0 | RA[5] | LOCATED | LVTTL33_OUT | PT2F | |
| 96/0 | RA[8] | LOCATED | LVTTL33_OUT | PT2E | |
| 97/0 | RA[3] | LOCATED | LVTTL33_OUT | PT2D | |
| 98/0 | RA[0] | LOCATED | LVTTL33_OUT | PT2C | |
| 99/0 | RA[4] | LOCATED | LVTTL33_OUT | PT2B | |
| 100/0 | RA[7] | LOCATED | LVTTL33_OUT | PT2A | |
| PB5B/0 | unused, PULL:UP | | | PB5B | |
| PT5D/0 | unused, PULL:UP | | | PT5D | |
| TCK/1 | | | | TCK | TCK |
| TDI/1 | | | | TDI | TDI |
| TDO/1 | | | | TDO | TDO |
| TMS/1 | | | | TMS | TMS |
+----------+---------------------+------------+--------------+------+---------------+
List of All Pins' Locate Preferences Based on Final Placement After PAR
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste):
LOCATE COMP "CROW[0]" SITE "32";
LOCATE COMP "CROW[1]" SITE "34";
LOCATE COMP "Din[0]" SITE "21";
LOCATE COMP "Din[1]" SITE "15";
LOCATE COMP "Din[2]" SITE "14";
LOCATE COMP "Din[3]" SITE "16";
LOCATE COMP "Din[4]" SITE "18";
LOCATE COMP "Din[5]" SITE "17";
LOCATE COMP "Din[6]" SITE "20";
LOCATE COMP "Din[7]" SITE "19";
LOCATE COMP "Dout[0]" SITE "1";
LOCATE COMP "Dout[1]" SITE "7";
LOCATE COMP "Dout[2]" SITE "8";
LOCATE COMP "Dout[3]" SITE "6";
LOCATE COMP "Dout[4]" SITE "4";
LOCATE COMP "Dout[5]" SITE "5";
LOCATE COMP "Dout[6]" SITE "2";
LOCATE COMP "Dout[7]" SITE "3";
LOCATE COMP "LED" SITE "57";
LOCATE COMP "MAin[0]" SITE "23";
LOCATE COMP "MAin[1]" SITE "38";
LOCATE COMP "MAin[2]" SITE "37";
LOCATE COMP "MAin[3]" SITE "47";
LOCATE COMP "MAin[4]" SITE "46";
LOCATE COMP "MAin[5]" SITE "45";
LOCATE COMP "MAin[6]" SITE "49";
LOCATE COMP "MAin[7]" SITE "44";
LOCATE COMP "MAin[8]" SITE "50";
LOCATE COMP "MAin[9]" SITE "51";
LOCATE COMP "PHI2" SITE "39";
LOCATE COMP "RA[0]" SITE "98";
LOCATE COMP "RA[10]" SITE "87";
LOCATE COMP "RA[11]" SITE "79";
LOCATE COMP "RA[1]" SITE "89";
LOCATE COMP "RA[2]" SITE "94";
LOCATE COMP "RA[3]" SITE "97";
LOCATE COMP "RA[4]" SITE "99";
LOCATE COMP "RA[5]" SITE "95";
LOCATE COMP "RA[6]" SITE "91";
LOCATE COMP "RA[7]" SITE "100";
LOCATE COMP "RA[8]" SITE "96";
LOCATE COMP "RA[9]" SITE "85";
LOCATE COMP "RBA[0]" SITE "63";
LOCATE COMP "RBA[1]" SITE "83";
LOCATE COMP "RCKE" SITE "82";
LOCATE COMP "RCLK" SITE "86";
LOCATE COMP "RDQMH" SITE "76";
LOCATE COMP "RDQML" SITE "61";
LOCATE COMP "RD[0]" SITE "64";
LOCATE COMP "RD[1]" SITE "65";
LOCATE COMP "RD[2]" SITE "66";
LOCATE COMP "RD[3]" SITE "67";
LOCATE COMP "RD[4]" SITE "68";
LOCATE COMP "RD[5]" SITE "69";
LOCATE COMP "RD[6]" SITE "70";
LOCATE COMP "RD[7]" SITE "71";
LOCATE COMP "UFMCLK" SITE "58";
LOCATE COMP "UFMSDI" SITE "56";
LOCATE COMP "UFMSDO" SITE "55";
LOCATE COMP "nCCAS" SITE "27";
LOCATE COMP "nCRAS" SITE "43";
LOCATE COMP "nFWE" SITE "22";
LOCATE COMP "nRCAS" SITE "78";
LOCATE COMP "nRCS" SITE "77";
LOCATE COMP "nRRAS" SITE "73";
LOCATE COMP "nRWE" SITE "72";
LOCATE COMP "nUFMCS" SITE "53";
PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Mon Aug 16 21:32:33 2021

View File

@ -0,0 +1,211 @@
Lattice Place and Route Report for Design "RAM2GS_LCMXO256C_impl1_map.ncd"
Mon Aug 16 21:32:27 2021
PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir/5_1.ncd RAM2GS_LCMXO256C_impl1.prf
Preference file: RAM2GS_LCMXO256C_impl1.prf.
Placement level-cost: 5-1.
Routing Iterations: 6
Loading design for application par from file RAM2GS_LCMXO256C_impl1_map.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO256C
Package: TQFP100
Performance: 3
Loading device for application par from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.19.
Performance Hardware Data Status: Version 1.124.
License checked out.
Ignore Preference Error(s): True
Device utilization summary:
PIO (prelim) 67/79 84% used
67/78 85% bonded
SLICE 65/128 50% used
Number of Signals: 252
Number of Connections: 618
Pin Constraint Summary:
67 out of 67 pins locked (100% locked).
The following 4 signals are selected to use the primary clock routing resources:
RCLK_c (driver: RCLK, clk load #: 39)
PHI2_c (driver: PHI2, clk load #: 13)
nCCAS_c (driver: nCCAS, clk load #: 4)
nCRAS_c (driver: nCRAS, clk load #: 7)
No signal is selected as secondary clock.
No signal is selected as Global Set/Reset.
Starting Placer Phase 0.
........
Finished Placer Phase 0. REAL time: 0 secs
Starting Placer Phase 1.
...............
Placer score = 586066.
Finished Placer Phase 1. REAL time: 6 secs
Starting Placer Phase 2.
.
Placer score = 584668
Finished Placer Phase 2. REAL time: 6 secs
------------------ Clock Report ------------------
Global Clock Resources:
CLK_PIN : 1 out of 4 (25%)
General PIO: 3 out of 80 (3%)
Global Clocks:
PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "86 (PT4A)", clk load = 39
PRIMARY "PHI2_c" from comp "PHI2" on PIO site "39 (PB3D)", clk load = 13
PRIMARY "nCCAS_c" from comp "nCCAS" on PIO site "27 (PL9B)", clk load = 4
PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "43 (PB4A)", clk load = 7
PRIMARY : 4 out of 4 (100%)
SECONDARY: 0 out of 4 (0%)
--------------- End of Clock Report ---------------
I/O Usage Summary (final):
67 out of 79 (84.8%) PIO sites used.
67 out of 78 (85.9%) bonded PIO sites used.
Number of PIO comps: 67; differential: 0.
Number of Vref pins used: 0.
I/O Bank Usage Summary:
+----------+----------------+------------+------------+------------+
| I/O Bank | Usage | Bank Vccio | Bank Vref1 | Bank Vref2 |
+----------+----------------+------------+------------+------------+
| 0 | 36 / 41 ( 87%) | 3.3V | - | - |
| 1 | 31 / 37 ( 83%) | 3.3V | - | - |
+----------+----------------+------------+------------+------------+
Total placer CPU time: 6 secs
Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd.
0 connections routed; 618 unrouted.
Starting router resource preassignment
WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
WARNING - par: The driver of primary clock net nCCAS_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
Completed router resource preassignment. Real time: 6 secs
Start NBR router at 21:32:33 08/16/21
*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
in the earlier iterations. In each iteration, it tries to
solve the conflicts while keeping the critical connections
routed as short as possible. The routing process is said to
be completed when no conflicts exist and all connections
are routed.
Note: NBR uses a different method to calculate timing slacks. The
worst slack and total negative slack may not be the same as
that in TRCE report. You should always run TRCE to verify
your design.
*****************************************************************
Start NBR special constraint process at 21:32:33 08/16/21
Start NBR section for initial routing at 21:32:33 08/16/21
Level 1, iteration 1
0(0.00%) conflict; 535(86.57%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 2.084ns/0.000ns; real time: 6 secs
Level 2, iteration 1
0(0.00%) conflict; 535(86.57%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 2.084ns/0.000ns; real time: 6 secs
Level 3, iteration 1
0(0.00%) conflict; 509(82.36%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 2.038ns/0.000ns; real time: 6 secs
Level 4, iteration 1
23(0.19%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs
Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area at 75% usage is 0 (0.00%)
Start NBR section for normal routing at 21:32:33 08/16/21
Level 1, iteration 1
0(0.00%) conflict; 24(3.88%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs
Level 4, iteration 1
8(0.07%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs
Level 4, iteration 2
4(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs
Level 4, iteration 3
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs
Start NBR section for setup/hold timing optimization with effort level 3 at 21:32:33 08/16/21
Start NBR section for re-routing at 21:32:33 08/16/21
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs
Start NBR section for post-routing at 21:32:33 08/16/21
End NBR router with 0 unrouted connection
NBR Summary
-----------
Number of unrouted connections : 0 (0.00%)
Number of connections with timing violations : 0 (0.00%)
Estimated worst slack<setup> : 2.023ns
Timing score<setup> : 0
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
Total CPU time 6 secs
Total REAL time: 7 secs
Completely routed.
End of route. 618 routed (100.00%); 0 unrouted.
Hold time timing score: 0, hold timing errors: 0
Timing score: 0
Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd.
All signals are completely routed.
PAR_SUMMARY::Run status = Completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst slack<setup/<ns>> = 2.023
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.339
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
PAR_SUMMARY::Number of errors = 0
Total CPU time to completion: 6 secs
Total REAL time to completion: 7 secs
par done!
Note: user must run 'Trace' for timing closure signoff.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.

View File

@ -0,0 +1,33 @@
[ActiveSupport PAR]
; Global primary clocks
GLOBAL_PRIMARY_USED = 4;
; Global primary clock #0
GLOBAL_PRIMARY_0_SIGNALNAME = RCLK_c;
GLOBAL_PRIMARY_0_DRIVERTYPE = CLK_PIN;
GLOBAL_PRIMARY_0_LOADNUM = 39;
; Global primary clock #1
GLOBAL_PRIMARY_1_SIGNALNAME = PHI2_c;
GLOBAL_PRIMARY_1_DRIVERTYPE = PIO;
GLOBAL_PRIMARY_1_LOADNUM = 13;
; Global primary clock #2
GLOBAL_PRIMARY_2_SIGNALNAME = nCCAS_c;
GLOBAL_PRIMARY_2_DRIVERTYPE = PIO;
GLOBAL_PRIMARY_2_LOADNUM = 4;
; Global primary clock #3
GLOBAL_PRIMARY_3_SIGNALNAME = nCRAS_c;
GLOBAL_PRIMARY_3_DRIVERTYPE = PIO;
GLOBAL_PRIMARY_3_LOADNUM = 7;
; # of global secondary clocks
GLOBAL_SECONDARY_USED = 0;
; I/O Bank 0 Usage
BANK_0_USED = 36;
BANK_0_AVAIL = 41;
BANK_0_VCCIO = 3.3V;
BANK_0_VREF1 = NA;
BANK_0_VREF2 = NA;
; I/O Bank 1 Usage
BANK_1_USED = 31;
BANK_1_AVAIL = 37;
BANK_1_VCCIO = 3.3V;
BANK_1_VREF1 = NA;
BANK_1_VREF2 = NA;

View File

@ -0,0 +1,28 @@
PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Mon Aug 16 21:32:27 2021
C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO256C_impl1.p2t
RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir
RAM2GS_LCMXO256C_impl1.prf -gui -msgset
C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml
Preference file: RAM2GS_LCMXO256C_impl1.prf.
Level/ Number Worst Timing Worst Timing Run NCD
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
---------- -------- ----- ------ ----------- ----------- ---- ------
5_1 * 0 2.023 0 0.339 0 07 Completed
* : Design saved.
Total (real) run time for 1-seed: 7 secs
par done!
Note: user must run 'Trace' for timing closure signoff.

View File

@ -0,0 +1 @@
DRC detected 0 errors and 0 warnings.

View File

@ -0,0 +1,977 @@

*
NOTE JEDEC CREATED BY: Lattice Semiconductor Diamond Deployment Tool 3.12*
NOTE Version: Diamond (64-bit) 3.12.0.240.2*
NOTE Readback: Off*
NOTE Security: Off*
NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
NOTE All Rights Reserved *
NOTE DATE CREATED: Mon Aug 16 21:36:26 2021 *
NOTE DESIGN NAME: RAM2GS *
NOTE DEVICE NAME: LCMXO256C-3TQFP100 *
NOTE PIN ASSIGNMENTS *
NOTE PINS RD[7] : 71 : inout *
NOTE PINS RD[6] : 70 : inout *
NOTE PINS RD[5] : 69 : inout *
NOTE PINS RD[4] : 68 : inout *
NOTE PINS RD[3] : 67 : inout *
NOTE PINS RD[2] : 66 : inout *
NOTE PINS RD[1] : 65 : inout *
NOTE PINS RD[0] : 64 : inout *
NOTE PINS Dout[7] : 3 : out *
NOTE PINS Dout[6] : 2 : out *
NOTE PINS Dout[5] : 5 : out *
NOTE PINS Dout[4] : 4 : out *
NOTE PINS Dout[3] : 6 : out *
NOTE PINS Dout[2] : 8 : out *
NOTE PINS Dout[1] : 7 : out *
NOTE PINS Dout[0] : 1 : out *
NOTE PINS LED : 57 : out *
NOTE PINS RBA[1] : 83 : out *
NOTE PINS RBA[0] : 63 : out *
NOTE PINS RA[11] : 79 : out *
NOTE PINS RA[10] : 87 : out *
NOTE PINS RA[9] : 85 : out *
NOTE PINS RA[8] : 96 : out *
NOTE PINS RA[7] : 100 : out *
NOTE PINS RA[6] : 91 : out *
NOTE PINS RA[5] : 95 : out *
NOTE PINS RA[4] : 99 : out *
NOTE PINS RA[3] : 97 : out *
NOTE PINS RA[2] : 94 : out *
NOTE PINS RA[1] : 89 : out *
NOTE PINS RA[0] : 98 : out *
NOTE PINS nRCS : 77 : out *
NOTE PINS RCKE : 82 : out *
NOTE PINS nRWE : 72 : out *
NOTE PINS nRRAS : 73 : out *
NOTE PINS nRCAS : 78 : out *
NOTE PINS RDQMH : 76 : out *
NOTE PINS RDQML : 61 : out *
NOTE PINS nUFMCS : 53 : out *
NOTE PINS UFMCLK : 58 : out *
NOTE PINS UFMSDI : 56 : out *
NOTE PINS PHI2 : 39 : in *
NOTE PINS MAin[9] : 51 : in *
NOTE PINS MAin[8] : 50 : in *
NOTE PINS MAin[7] : 44 : in *
NOTE PINS MAin[6] : 49 : in *
NOTE PINS MAin[5] : 45 : in *
NOTE PINS MAin[4] : 46 : in *
NOTE PINS MAin[3] : 47 : in *
NOTE PINS MAin[2] : 37 : in *
NOTE PINS MAin[1] : 38 : in *
NOTE PINS MAin[0] : 23 : in *
NOTE PINS CROW[1] : 34 : in *
NOTE PINS CROW[0] : 32 : in *
NOTE PINS Din[7] : 19 : in *
NOTE PINS Din[6] : 20 : in *
NOTE PINS Din[5] : 17 : in *
NOTE PINS Din[4] : 18 : in *
NOTE PINS Din[3] : 16 : in *
NOTE PINS Din[2] : 14 : in *
NOTE PINS Din[1] : 15 : in *
NOTE PINS Din[0] : 21 : in *
NOTE PINS nCCAS : 27 : in *
NOTE PINS nCRAS : 43 : in *
NOTE PINS nFWE : 22 : in *
NOTE PINS RCLK : 86 : in *
NOTE PINS UFMSDO : 55 : in *
NOTE CONFIGURATION MODE: NONE *
NOTE COMPRESSION: off *
QF56640*
G0*
F0*
L00000
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11111111111111111011111111111111111111111111111111111111111110111111110011111111
11111111111111111111111111111111
11111111111111111111111111111111111111111011111111111111111111101111111111111111
11111111111111111011111111101111111111111111111110111111111111111111111011111111
11001111111100111111111111111111
11111111111111111111111111111111111111111111111111111111111111111111111111111111
11111111111111110111111111111111111111111111111111111111111111111111110111111111
11111111111111111111111111111111
11111111111111111111111111111111111111110111111111111111111111011111111111111110
10111111111111110111101011011110111111111111111101011111111111111111110111111111
11111111111101111111111111111111
11111111111111111111111111111111111111111111111111111111111111111111111111111111
11111111111111111111111111111111111111111111111111111111111111111111111111111111
11111111111111111111111111111111
11111111111111111111111111111111111111111111111111111111111111111111111111111111
01111111111111111111110111111110001111111110011111111001111111111111111111100111
11111111111111111111111111111111
11111111111111111111111111111111111111111111111111111111111111111111111111111111
11111111111111111111111111111111111111111111111111111111111111111001111111100111
11111111111111111111111111111111
11111111111111111111111111111111111111111111111111111111111111111111111111111111
11111111111111111111101111111111111111111111111111111111111111111111111111111111
11111111111111111111111111111111
11111111111111111111111111111111111111111111111111111111111101111111111111111111
11111111111111111111111111110111111111111111111111011111111111111111111001111111
11111111111111111111111111111111
11111111111111111111111111111111111111111111111111111111111111111111111111111110
11111111111111111111111111101111111111111111111110111111111111111111111111111111
11111111111111111111111111111111
11111111111111111111111111111111111111111111111111111111111101111111111111111111
11111111111111111111111111111111111111111111111111111111111111111111111111111111
11111111111111111111111111111111
11111111111111111111111110111111111111111111111011110010100100111100111111001010
01001111011101110011000100111101100111001100010011110010111100101001001111001111
11001010010011110111101111111111
11111111001011111111011110111100101001001111011110110010110011011101111011111111
11111111111011110011000100111101100111001100010011110110101100110001001111011010
11001010010011110111101111111111
11111111111111111111111111111111111111111111111111110010100100111100111111111111
11111111111111110011000100111100100111111111111111111111111100110001001111011010
11111111111111111111111111111111
11111111111111111111111111111111111111111111111111110011011111110111101111111111
11111111111111110010100100111100111111111111111111111111111100110001001111011010
11111111111111111111111111111111
*
CA8D9*
N User Electronic Signature Data*
U00000000000000000000000000000000*
2290

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---- MParTrce Tool Log File ----
==== Par Standard Out ====
==== End of Par Standard Out ====

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#BLOCK ASYNCPATHS;
#BLOCK RESETPATHS;
#FREQUENCY 200.000000 MHz;

File diff suppressed because it is too large Load Diff

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Lattice Mapping Report File for Design Module 'RAM2GS'
Design Information
------------------
Command line: map -a MachXO -p LCMXO256C -t TQFP100 -s 3 -oc Commercial
RAM2GS_LCMXO256C_impl1.ngd -o RAM2GS_LCMXO256C_impl1_map.ncd -pr
RAM2GS_LCMXO256C_impl1.prf -mp RAM2GS_LCMXO256C_impl1.mrp -lpf C:/Users/Dog
/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.
lpf -lpf C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/RAM2GS_L
CMXO256C.lpf -c 0 -gui -msgset
C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml
Target Vendor: LATTICE
Target Device: LCMXO256CTQFP100
Target Performance: 3
Mapper: mj5g00, version: Diamond (64-bit) 3.12.0.240.2
Mapped on: 08/16/21 21:32:26
Design Summary
--------------
Number of PFU registers: 102 out of 256 (40%)
Number of SLICEs: 65 out of 128 (51%)
SLICEs as Logic/ROM: 65 out of 128 (51%)
SLICEs as RAM: 0 out of 64 (0%)
SLICEs as Carry: 9 out of 128 (7%)
Number of LUT4s: 129 out of 256 (50%)
Number used as logic LUTs: 111
Number used as distributed RAM: 0
Number used as ripple logic: 18
Number used as shift registers: 0
Number of external PIOs: 67 out of 78 (86%)
Number of GSRs: 0 out of 1 (0%)
JTAG used : No
Readback used : No
Oscillator used : No
Startup used : No
Number of TSALL: 0 out of 1 (0%)
Notes:-
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
distributed RAMs) + 2*(Number of ripple logic)
2. Number of logic LUT4s does not include count of distributed RAM and
ripple logic.
Number of clocks: 4
Net RCLK_c: 39 loads, 39 rising, 0 falling (Driver: PIO RCLK )
Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 )
Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS )
Number of Clock Enables: 13
Net PHI2_N_114_enable_7: 2 loads, 2 LSLICEs
Net RCLK_c_enable_6: 1 loads, 1 LSLICEs
Net RCLK_c_enable_4: 3 loads, 3 LSLICEs
Net RCLK_c_enable_24: 2 loads, 2 LSLICEs
Net RCLK_c_enable_3: 1 loads, 1 LSLICEs
Net RCLK_c_enable_7: 1 loads, 1 LSLICEs
Net RCLK_c_enable_23: 8 loads, 8 LSLICEs
Net PHI2_N_114_enable_1: 1 loads, 1 LSLICEs
Net PHI2_N_114_enable_8: 1 loads, 1 LSLICEs
Net PHI2_N_114_enable_6: 2 loads, 2 LSLICEs
Net PHI2_N_114_enable_2: 1 loads, 1 LSLICEs
Page 1
Design: RAM2GS Date: 08/16/21 21:32:26
Design Summary (cont)
---------------------
Net RCLK_c_enable_25: 1 loads, 1 LSLICEs
Net Ready_N_268: 1 loads, 1 LSLICEs
Number of LSRs: 9
Net RASr2: 1 loads, 1 LSLICEs
Net C1Submitted_N_225: 2 loads, 2 LSLICEs
Net n2299: 1 loads, 1 LSLICEs
Net nRowColSel_N_35: 1 loads, 1 LSLICEs
Net nRowColSel_N_34: 1 loads, 1 LSLICEs
Net LEDEN_N_88: 1 loads, 1 LSLICEs
Net n2291: 2 loads, 2 LSLICEs
Net Ready: 7 loads, 7 LSLICEs
Net nRWE_N_173: 1 loads, 1 LSLICEs
Number of nets driven by tri-state buffers: 0
Top 10 highest fanout non-clock nets:
Net Ready: 19 loads
Net InitReady: 17 loads
Net RASr2: 16 loads
Net nRowColSel_N_35: 14 loads
Net nRowColSel: 13 loads
Net Din_c_6: 9 loads
Net MAin_c_1: 9 loads
Net Din_c_5: 8 loads
Net FS_11: 8 loads
Net MAin_c_0: 8 loads
Number of warnings: 0
Number of errors: 0
Design Errors/Warnings
----------------------
No errors or warnings present.
IO (PIO) Attributes
-------------------
+---------------------+-----------+-----------+------------+------------+
| IO Name | Direction | Levelmode | IO | FIXEDDELAY |
| | | IO_TYPE | Register | |
+---------------------+-----------+-----------+------------+------------+
| RD[7] | BIDIR | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RD[6] | BIDIR | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RD[5] | BIDIR | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RD[4] | BIDIR | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RD[3] | BIDIR | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RD[2] | BIDIR | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
Page 2
Design: RAM2GS Date: 08/16/21 21:32:26
IO (PIO) Attributes (cont)
--------------------------
| RD[1] | BIDIR | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RD[0] | BIDIR | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| Dout[7] | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| Dout[6] | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| Dout[5] | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| Dout[4] | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| Dout[3] | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| Dout[2] | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| Dout[1] | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| Dout[0] | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| LED | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RBA[1] | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RBA[0] | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RA[11] | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RA[10] | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RA[9] | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RA[8] | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RA[7] | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RA[6] | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RA[5] | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RA[4] | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RA[3] | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RA[2] | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RA[1] | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RA[0] | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| nRCS | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RCKE | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| nRWE | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
Page 3
Design: RAM2GS Date: 08/16/21 21:32:26
IO (PIO) Attributes (cont)
--------------------------
| nRRAS | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| nRCAS | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RDQMH | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RDQML | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| nUFMCS | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| UFMCLK | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| UFMSDI | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| PHI2 | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| MAin[9] | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| MAin[8] | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| MAin[7] | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| MAin[6] | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| MAin[5] | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| MAin[4] | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| MAin[3] | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| MAin[2] | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| MAin[1] | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| MAin[0] | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| CROW[1] | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| CROW[0] | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| Din[7] | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| Din[6] | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| Din[5] | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| Din[4] | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| Din[3] | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| Din[2] | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| Din[1] | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| Din[0] | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
Page 4
Design: RAM2GS Date: 08/16/21 21:32:26
IO (PIO) Attributes (cont)
--------------------------
| nCCAS | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| nCRAS | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| nFWE | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RCLK | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| UFMSDO | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
Removed logic
-------------
Block i2 undriven or does not drive anything - clipped.
Block GSR_INST undriven or does not drive anything - clipped.
Signal PHI2_N_114 was merged into signal PHI2_c
Signal nCRAS_N_9 was merged into signal nCRAS_c
Signal nCCAS_N_3 was merged into signal nCCAS_c
Signal n2302 was merged into signal nRowColSel_N_35
Signal nRWE_N_172 was merged into signal nRWE_N_173
Signal n2307 was merged into signal Ready
Signal RASr2_N_63 was merged into signal RASr2
Signal n1377 was merged into signal nRowColSel_N_34
Signal n2306 was merged into signal nFWE_c
Signal UFMSDO_N_74 was merged into signal UFMSDO_c
Signal GND_net undriven or does not drive anything - clipped.
Signal VCC_net undriven or does not drive anything - clipped.
Signal FS_577_add_4_14/CO0 undriven or does not drive anything - clipped.
Signal FS_577_add_4_16/CO0 undriven or does not drive anything - clipped.
Signal FS_577_add_4_12/CO0 undriven or does not drive anything - clipped.
Signal FS_577_add_4_2/CO0 undriven or does not drive anything - clipped.
Signal FS_577_add_4_4/CO0 undriven or does not drive anything - clipped.
Signal FS_577_add_4_6/CO0 undriven or does not drive anything - clipped.
Signal FS_577_add_4_18/CO1 undriven or does not drive anything - clipped.
Signal FS_577_add_4_18/CO0 undriven or does not drive anything - clipped.
Signal FS_577_add_4_8/CO0 undriven or does not drive anything - clipped.
Signal FS_577_add_4_10/CO0 undriven or does not drive anything - clipped.
Block i1962 was optimized away.
Block i1961 was optimized away.
Block i1963 was optimized away.
Block i1070_1_lut_rep_25 was optimized away.
Block nRWE_I_49_1_lut was optimized away.
Block i604_1_lut_rep_30 was optimized away.
Block RASr2_I_0_1_lut was optimized away.
Block i1069_1_lut was optimized away.
Block i1_1_lut_rep_29 was optimized away.
Block UFMSDO_I_0_1_lut was optimized away.
Block i1 was optimized away.
Run Time and Memory Usage
-------------------------
Total CPU Time: 0 secs
Total REAL Time: 0 secs
Peak Memory Usage: 29 MB
Page 5
Design: RAM2GS Date: 08/16/21 21:32:26
Run Time and Memory Usage (cont)
--------------------------------
Page 6
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights
reserved.

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-v
1
-gt
-mapchkpnt 0
-sethld

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comp 0: SLICE_0 (FSLICE)
comp 1: SLICE_1 (FSLICE)
comp 2: SLICE_2 (FSLICE)
comp 3: SLICE_3 (FSLICE)
comp 4: SLICE_4 (FSLICE)
comp 5: SLICE_5 (FSLICE)
comp 6: SLICE_6 (FSLICE)
comp 7: SLICE_7 (FSLICE)
comp 8: SLICE_8 (FSLICE)
comp 9: SLICE_9 (FSLICE)
n1361 = ((ADSubmitted*(~MAin_c_1+n2290))+ADSubmitted_N_234)
ADSubmitted.D = n1361
ADSubmitted.CLK = ~PHI2_c
ADSubmitted.SP = VCC
ADSubmitted.LSR = C1Submitted_N_225
n2080 = (~MAin_c_0*(~ADSubmitted*n2122))
comp 10: SLICE_14 (FSLICE)
n2386 = GND
C1Submitted.D = n2386
C1Submitted.CLK = ~PHI2_c
C1Submitted.SP = PHI2_N_114_enable_1
C1Submitted.LSR = C1Submitted_N_225
n2098 = (MAin_c_0*(~C1Submitted*(MAin_c_1*n2108)))
comp 11: SLICE_18 (FSLICE)
CmdEnable_N_236 = (ADSubmitted_N_234+C1Submitted_N_225)
CmdEnable.D = CmdEnable_N_236
CmdEnable.CLK = ~PHI2_c
CmdEnable.SP = PHI2_N_114_enable_8
CmdEnable.LSR = GND
XOR8MEG_N_112 = (~n2290*(CmdEnable*(MAin_c_0*~MAin_c_1)))
comp 12: SLICE_19 (FSLICE)
n2387\000/BUF1 = VCC
CmdSubmitted.D = n2387\000/BUF1
CmdSubmitted.CLK = ~PHI2_c
CmdSubmitted.SP = PHI2_N_114_enable_6
CmdSubmitted.LSR = GND
n2308 = (~PHI2r2*(CmdSubmitted*PHI2r3))
comp 13: SLICE_23 (FSLICE)
Cmdn8MEGEN_N_248 = (~n2296*(~Din_c_5*~Din_c_0+Din_c_5*n8MEGEN)+n2296*n8MEGEN)
Cmdn8MEGEN.D = Cmdn8MEGEN_N_248
Cmdn8MEGEN.CLK = ~PHI2_c
Cmdn8MEGEN.SP = PHI2_N_114_enable_6
Cmdn8MEGEN.LSR = GND
n2296 = (~Din_c_4+(Din_c_6+Din_c_7))
comp 14: SLICE_25 (FSLICE)
n2387 = VCC
InitReady.D = n2387
InitReady.CLK = RCLK_c
InitReady.SP = RCLK_c_enable_6
InitReady.LSR = GND
RCLK_c_enable_24 = (~InitReady+(~PHI2r2*(CmdSubmitted*PHI2r3)))
comp 15: SLICE_31 (FSLICE)
RA11_N_180 = (~n8MEGEN*(XOR8MEG@Din_c_6)+n8MEGEN*XOR8MEG)
RA_c.D = RA11_N_180
RA_c.CLK = PHI2_c
RA_c.SP = VCC
RA_c.LSR = ~Ready
n2385 = (Din_c_6+Din_c_7)
comp 16: SLICE_33 (FSLICE)
RCKEEN_N_115 = (~Ready*InitReady+Ready*RCKEEN_N_116)
RCKEEN.D = RCKEEN_N_115
RCKEEN.CLK = RCLK_c
RCKEEN.SP = RCLK_c_enable_4
RCKEEN.LSR = GND
RCLK_c_enable_7 = (~n2119*(InitReady*n2308)+n2119*(~InitReady*~FS_5+InitReady*n2308))
comp 17: SLICE_34 (FSLICE)
RCKE_N_128 = (~RASr3*(~RASr2*(RCKEEN*RASr)+RASr2*RCKEEN)+RASr3*(~RASr2+RCKEEN))
RCKE_c.D = RCKE_N_128
RCKE_c.CLK = RCLK_c
RCKE_c.SP = VCC
RCKE_c.LSR = GND
nRWE_N_178 = (~RCKE_c+RASr2)
CASr2.D = CASr
CASr2.CLK = RCLK_c
CASr2.SP = VCC
CASr2.LSR = GND
comp 18: SLICE_35 (FSLICE)
n2387\001/BUF1 = VCC
Ready.D = n2387\001/BUF1
Ready.CLK = RCLK_c
Ready.SP = Ready_N_268
Ready.LSR = GND
RCLK_c_enable_23 = (InitReady*(RASr2*(nRowColSel_N_35*~Ready)))
comp 19: SLICE_42 (FSLICE)
UFMCLK_N_212 = (~n2076*(~InitReady*FS_4+InitReady*CmdUFMCLK)+n2076*(InitReady*CmdUFMCLK))
UFMCLK_c.D = UFMCLK_N_212
UFMCLK_c.CLK = RCLK_c
UFMCLK_c.SP = RCLK_c_enable_24
UFMCLK_c.LSR = n2291
RCLK_c_enable_6 = (n2076*FS_10)
comp 20: SLICE_43 (FSLICE)
UFMSDI_N_219 = (~InitReady*n1895+InitReady*CmdUFMSDI)
UFMSDI_c.D = UFMSDI_N_219
UFMSDI_c.CLK = RCLK_c
UFMSDI_c.SP = RCLK_c_enable_24
UFMSDI_c.LSR = n2291
n1895 = (~FS_10*(n2103*(~n2293*FS_6)))
comp 21: SLICE_55 (FSLICE)
n2128 = (((n2297+n2301)+nRCAS_N_161)+Ready)
n980.D = n2128
n980.CLK = RCLK_c
n980.SP = VCC
n980.LSR = ~nRWE_N_173
n2301 = (~InitReady+~RASr2)
comp 22: SLICE_56 (FSLICE)
n8MEGEN_N_94 = (~n4*(~FS_10*Cmdn8MEGEN+FS_10*~UFMSDO_c)+n4*Cmdn8MEGEN)
n8MEGEN.D = n8MEGEN_N_94
n8MEGEN.CLK = RCLK_c
n8MEGEN.SP = RCLK_c_enable_7
n8MEGEN.LSR = GND
n4 = ((~FS_11+n2300)+InitReady)
comp 23: SLICE_58 (FSLICE)
nRCAS_N_157 = (~nRowColSel_N_35*(~n2117+~Ready)+nRowColSel_N_35*n2287)
nRCAS_c.D = nRCAS_N_157
nRCAS_c.CLK = RCLK_c
nRCAS_c.SP = RCLK_c_enable_4
nRCAS_c.LSR = GND
n2287 = (~n2248*(~Ready*~RASr2+Ready*(~RASr2+~CBR))+n2248*(~Ready+(~RASr2+~CBR)))
comp 24: SLICE_60 (FSLICE)
nRCS_N_132 = (((~RCKE_c*nRowColSel_N_35*~RASr2)+(~n2117*~nRowColSel_N_35))*Ready)+((~InitReady+nRCS_N_135+~RASr2+~nRowColSel_N_35)*~Ready)
nRCS_c.D = nRCS_N_132
nRCS_c.CLK = RCLK_c
nRCS_c.SP = RCLK_c_enable_4
nRCS_c.LSR = GND
comp 25: SLICE_61 (FSLICE)
n33 = (~Ready*(n2244+n2297)+Ready*(n2244+n18))
nRRAS_c.D = n33
nRRAS_c.CLK = RCLK_c
nRRAS_c.SP = VCC
nRRAS_c.LSR = GND
n50 = ((nRowColSel_N_33+nRRAS_c)+nRowColSel_N_32)
RASr.D = ~nCRAS_c
RASr.CLK = RCLK_c
RASr.SP = VCC
RASr.LSR = GND
comp 26: SLICE_62 (FSLICE)
n1369 = (~n2308*nUFMCS_c+n2308*~CmdUFMCS)
nRWE_N_173.D = n705
nRWE_N_173.CLK = RCLK_c
nRWE_N_173.SP = RCLK_c_enable_23
nRWE_N_173.LSR = GND
nRCS_N_135.D = Ready_N_272
nRCS_N_135.CLK = RCLK_c
nRCS_N_135.SP = RCLK_c_enable_23
nRCS_N_135.LSR = GND
comp 27: SLICE_63 (FSLICE)
nRWE_N_167 = (~n2292*(~Ready*~n2164+Ready*nRWE_N_174)+n2292*(~Ready+nRWE_N_174))
nRWE_c.D = nRWE_N_167
nRWE_c.CLK = RCLK_c
nRWE_c.SP = RCLK_c_enable_3
nRWE_c.LSR = GND
nRWE_N_174 = (~nRowColSel_N_35*(~n1+n1627)+nRowColSel_N_35*nRWE_N_178)
comp 28: SLICE_64 (FSLICE)
n1368 = (~nRowColSel_N_32*(nRowColSel+n1627)+nRowColSel_N_32*(~nRowColSel_N_28+n1627))
nRowColSel.D = n1368
nRowColSel.CLK = RCLK_c
nRowColSel.SP = VCC
nRowColSel.LSR = n2299
RA_c_4 = (~nRowColSel*RowA_4+nRowColSel*MAin_c_4)
comp 29: SLICE_65 (FSLICE)
n1628 = (nRowColSel_N_32+nRowColSel_N_33)
nRowColSel_N_32.D = n1628
nRowColSel_N_32.CLK = RCLK_c
nRowColSel_N_32.SP = VCC
nRowColSel_N_32.LSR = ~RASr2
RCLK_c_enable_4 = (((nRowColSel_N_32+n2299)+nRowColSel_N_34)+nRowColSel_N_33)
comp 30: SLICE_66 (FSLICE)
n1135 = (RASr2*~nRowColSel_N_32)
nRowColSel_N_33.D = n1135
nRowColSel_N_33.CLK = RCLK_c
nRowColSel_N_33.SP = VCC
nRowColSel_N_33.LSR = ~nRowColSel_N_34
n2117 = (~nRowColSel_N_33*(n1*~nRowColSel_N_34)+nRowColSel_N_33*(~n2304*~nRowColSel_N_34))
comp 31: SLICE_67 (FSLICE)
LED_N_90 = (~LEDEN+nCRAS_c)
nRowColSel_N_34.D = n1135
nRowColSel_N_34.CLK = RCLK_c
nRowColSel_N_34.SP = VCC
nRowColSel_N_34.LSR = ~nRowColSel_N_35
n2154 = (MAin_c_4*Bank_7)
comp 32: SLICE_68 (FSLICE)
n2168 = (FS_3*(FS_2*(FS_0*FS_1)))
nRowColSel_N_35.D = ~RASr2
nRowColSel_N_35.CLK = RCLK_c
nRowColSel_N_35.SP = VCC
nRowColSel_N_35.LSR = GND
n962 = (nCCAS_c+nFWE_c)
CASr3.D = CASr2
CASr3.CLK = RCLK_c
CASr3.SP = VCC
CASr3.LSR = GND
comp 33: SLICE_69 (FSLICE)
n1348 = (~InitReady*n2076+InitReady*n1369)
nUFMCS_c.D = n1348
nUFMCS_c.CLK = RCLK_c
nUFMCS_c.SP = VCC
nUFMCS_c.LSR = LEDEN_N_88
n2076 = (FS_17*(FS_11*(n12_adj_2*FS_15)))
comp 34: i1912/SLICE_70 (FSLICE)
n2244 = (((~RCKE_c*nRowColSel_N_35*~RASr2)+(~nRowColSel_N_35*n50))*Ready)+(((~nRowColSel_N_35*n50)+~InitReady+~RASr2)*~Ready)
comp 35: RCKEEN_I_0_419/SLICE_71 (FSLICE)
RCKEEN_N_116 = (((~FWEr*~CBR)+~RASr2)*nRowColSel_N_35)+(((FWEr*n11_adj_3*~CBR)+(nRowColSel_N_34*~CBR))*~nRowColSel_N_35)
comp 36: SLICE_72 (FSLICE)
PHI2_N_114_enable_7 = (Din_c_5*(~n2296*(n2298*XOR8MEG_N_112)))
n702.D = n703
n702.CLK = RCLK_c
n702.SP = RCLK_c_enable_23
n702.LSR = GND
n2298 = (((Din_c_6+Din_c_7)+Din_c_5)+Din_c_4)
n701.D = n702
n701.CLK = RCLK_c
n701.SP = RCLK_c_enable_23
n701.LSR = GND
comp 37: SLICE_73 (FSLICE)
n11 = (~n2168+((~FS_11+n2300)+FS_6))
n706.D = n707
n706.CLK = RCLK_c
n706.SP = RCLK_c_enable_23
n706.LSR = GND
n2300 = ((FS_16+n10)+FS_17)
n705.D = n706
n705.CLK = RCLK_c
n705.SP = RCLK_c_enable_23
n705.LSR = GND
comp 38: SLICE_74 (FSLICE)
C1Submitted_N_225 = (~n2131*(~Din_c_2*(n2295*n2122)))
n710.D = n711
n710.CLK = RCLK_c
n710.SP = RCLK_c_enable_23
n710.LSR = GND
n2295 = (n2114*~nFWE_c)
n709.D = n710
n709.CLK = RCLK_c
n709.SP = RCLK_c_enable_23
n709.LSR = GND
comp 39: SLICE_75 (FSLICE)
n2119 = (~n12*(~n11*(FS_10*n2294)))
n708.D = n709
n708.CLK = RCLK_c
n708.SP = RCLK_c_enable_23
n708.LSR = GND
RCLK_c_enable_25 = (n2119*(FS_5*~InitReady))
n707.D = n708
n707.CLK = RCLK_c
n707.SP = RCLK_c_enable_23
n707.LSR = GND
comp 40: SLICE_76 (FSLICE)
n2131 = ((~MAin_c_1+n1285)+MAin_c_0)
WRD_0.D = Din_c_0
WRD_0.CLK = ~nCCAS_c
WRD_0.SP = VCC
WRD_0.LSR = GND
n1285 = (~MAin_c_5+(~n2170+(~Bank_3+n26)))
WRD_1.D = Din_c_1
WRD_1.CLK = ~nCCAS_c
WRD_1.SP = VCC
WRD_1.LSR = GND
comp 41: SLICE_77 (FSLICE)
PHI2_N_114_enable_8 = (~MAin_c_1*(~n2286*(~n2290*MAin_c_0))+MAin_c_1*(~n2286*~n2290))
RowA_2.D = MAin_c_2
RowA_2.CLK = ~nCRAS_c
RowA_2.SP = VCC
RowA_2.LSR = ~Ready
n2286 = (n2114*(~Din_c_2*n2080+Din_c_2*n2098))
RowA_3.D = MAin_c_3
RowA_3.CLK = ~nCRAS_c
RowA_3.SP = VCC
RowA_3.LSR = ~Ready
comp 42: SLICE_78 (FSLICE)
n10 = (((FS_14+FS_13)+FS_12)+FS_15)
CASr.D = ~nCCAS_c
CASr.CLK = RCLK_c
CASr.SP = VCC
CASr.LSR = GND
n2294 = (((FS_16+n10)+FS_17)+FS_11)
PHI2r2.D = PHI2r
PHI2r2.CLK = RCLK_c
PHI2r2.SP = VCC
PHI2r2.LSR = GND
comp 43: SLICE_79 (FSLICE)
n1627 = (nRowColSel_N_34+nRowColSel_N_33)
WRD_2.D = Din_c_2
WRD_2.CLK = ~nCCAS_c
WRD_2.SP = VCC
WRD_2.LSR = GND
RCLK_c_enable_3 = (((~Ready+nRowColSel_N_32)+n1627)+nRowColSel_N_35)
WRD_3.D = Din_c_3
WRD_3.CLK = ~nCCAS_c
WRD_3.SP = VCC
WRD_3.LSR = GND
comp 44: SLICE_80 (FSLICE)
ADSubmitted_N_234 = (~n2289*(n4_adj_1*(MAin_c_0*n2108)))
WRD_6.D = Din_c_6
WRD_6.CLK = ~nCCAS_c
WRD_6.SP = VCC
WRD_6.LSR = GND
n2289 = (~MAin_c_1+n1285)
WRD_7.D = Din_c_7
WRD_7.CLK = ~nCCAS_c
WRD_7.SP = VCC
WRD_7.LSR = GND
comp 45: SLICE_81 (FSLICE)
n4_adj_1 = (n2114*(Din_c_2*~nFWE_c))
RowA_8.D = MAin_c_8
RowA_8.CLK = ~nCRAS_c
RowA_8.SP = VCC
RowA_8.LSR = ~Ready
n2114 = (Din_c_7*(~Din_c_4*(~Din_c_1*Din_c_0)))
RowA_9.D = MAin_c_9
RowA_9.CLK = ~nCRAS_c
RowA_9.SP = VCC
RowA_9.LSR = ~Ready
comp 46: SLICE_82 (FSLICE)
n2166 = (Bank_6*(MAin_c_2*(Bank_5*Bank_0)))
RowA_0.D = MAin_c_0
RowA_0.CLK = ~nCRAS_c
RowA_0.SP = VCC
RowA_0.LSR = ~Ready
n26 = (~MAin_c_6+(~n2154+(~n2166+Bank_2)))
RowA_1.D = MAin_c_1
RowA_1.CLK = ~nCRAS_c
RowA_1.SP = VCC
RowA_1.LSR = ~Ready
comp 47: SLICE_83 (FSLICE)
n2245 = (InitReady*(Ready_N_272*(~RASr2*nRowColSel_N_32)))
CmdUFMCLK.D = Din_c_1
CmdUFMCLK.CLK = ~PHI2_c
CmdUFMCLK.SP = PHI2_N_114_enable_7
CmdUFMCLK.LSR = GND
Ready_N_268 = (n2245+Ready)
CmdUFMCS.D = Din_c_2
CmdUFMCS.CLK = ~PHI2_c
CmdUFMCS.SP = PHI2_N_114_enable_7
CmdUFMCS.LSR = GND
comp 48: SLICE_84 (FSLICE)
nRowColSel_N_28 = ((~FWEr+CASr3)+CBR)
nRCAS_N_161.D = nRCS_N_135
nRCAS_N_161.CLK = RCLK_c
nRCAS_N_161.SP = RCLK_c_enable_23
nRCAS_N_161.LSR = GND
n1 = (~CASr3*(CASr2*(FWEr*~CBR)))
n703.D = nRWE_N_173
n703.CLK = RCLK_c
n703.SP = RCLK_c_enable_23
n703.LSR = GND
comp 49: SLICE_85 (FSLICE)
n12 = (((~FS_4+FS_9)+FS_8)+FS_7)
PHI2r3.D = PHI2r2
PHI2r3.CLK = RCLK_c
PHI2r3.SP = VCC
PHI2r3.LSR = GND
n2103 = (~FS_9*(FS_7*~FS_8)+FS_9*(FS_5*(~FS_7*~FS_8)))
PHI2r.D = PHI2_c
PHI2r.CLK = RCLK_c
PHI2r.SP = VCC
PHI2r.LSR = GND
comp 50: SLICE_86 (FSLICE)
n2291 = (~InitReady*(~n2300*~FS_11))
RowA_6.D = MAin_c_6
RowA_6.CLK = ~nCRAS_c
RowA_6.SP = VCC
RowA_6.LSR = ~Ready
LEDEN_N_88 = (~InitReady*(~FS_10*(~n2300*~FS_11)))
RowA_7.D = MAin_c_7
RowA_7.CLK = ~nCRAS_c
RowA_7.SP = VCC
RowA_7.LSR = ~Ready
comp 51: SLICE_87 (FSLICE)
n2122 = (~Din_c_5*(Din_c_6*~Din_c_3))
Ready_N_272.D = n699
Ready_N_272.CLK = RCLK_c
Ready_N_272.SP = RCLK_c_enable_23
Ready_N_272.LSR = GND
n2108 = (Din_c_3*(Din_c_5*~Din_c_6))
n711.D = nRCAS_N_161
n711.CLK = RCLK_c
n711.SP = RCLK_c_enable_23
n711.LSR = GND
comp 52: SLICE_88 (FSLICE)
RDQMH_c = (~nRowColSel+MAin_c_9)
CmdUFMSDI.D = Din_c_0
CmdUFMSDI.CLK = ~PHI2_c
CmdUFMSDI.SP = PHI2_N_114_enable_7
CmdUFMSDI.LSR = GND
RA_c_9 = (~nRowColSel*RowA_9+nRowColSel*MAin_c_9)
comp 53: SLICE_89 (FSLICE)
n2290 = (nFWE_c+n1285)
LEDEN.D = ~UFMSDO_c
LEDEN.CLK = RCLK_c
LEDEN.SP = RCLK_c_enable_25
LEDEN.LSR = GND
PHI2_N_114_enable_1 = (MAin_c_1*(~n1285*~nFWE_c))
comp 54: SLICE_90 (FSLICE)
PHI2_N_114_enable_6 = (Din_c_4*(XOR8MEG_N_112*(~Din_c_7*~Din_c_6)))
n700.D = n701
n700.CLK = RCLK_c
n700.SP = RCLK_c_enable_23
n700.LSR = GND
PHI2_N_114_enable_2 = (XOR8MEG_N_112*(~Din_c_5*(~Din_c_4*~n2385)))
n699.D = n700
n699.CLK = RCLK_c
n699.SP = RCLK_c_enable_23
n699.LSR = GND
comp 55: SLICE_91 (FSLICE)
n2248 = (~InitReady+(nRCAS_N_161+nRCS_N_135))
CBR.D = ~nCCAS_c
CBR.CLK = ~nCRAS_c
CBR.SP = VCC
CBR.LSR = GND
n2292 = (~RASr2+(~InitReady+(~nRowColSel_N_35+nRCS_N_135)))
FWEr.D = ~nFWE_c
FWEr.CLK = ~nCRAS_c
FWEr.SP = VCC
FWEr.LSR = GND
comp 56: SLICE_92 (FSLICE)
RDQML_c = (~nRowColSel+~MAin_c_9)
RowA_4.D = MAin_c_4
RowA_4.CLK = ~nCRAS_c
RowA_4.SP = VCC
RowA_4.LSR = ~Ready
RA_c_0 = (~nRowColSel*RowA_0+nRowColSel*MAin_c_0)
RowA_5.D = MAin_c_5
RowA_5.CLK = ~nCRAS_c
RowA_5.SP = VCC
RowA_5.LSR = ~Ready
comp 57: SLICE_93 (FSLICE)
n12_adj_2 = (FS_12*(FS_13*(FS_16*FS_14)))
RASr2.D = RASr
RASr2.CLK = RCLK_c
RASr2.SP = VCC
RASr2.LSR = GND
n2293 = (~FS_11+((FS_16+n10)+FS_17))
RASr3.D = RASr2
RASr3.CLK = RCLK_c
RASr3.SP = VCC
RASr3.LSR = GND
comp 58: SLICE_94 (FSLICE)
RA_c_1 = (~nRowColSel*RowA_1+nRowColSel*MAin_c_1)
Bank_0.D = Din_c_0
Bank_0.CLK = PHI2_c
Bank_0.SP = VCC
Bank_0.LSR = GND
RA_c_3 = (~nRowColSel*RowA_3+nRowColSel*MAin_c_3)
Bank_1.D = Din_c_1
Bank_1.CLK = PHI2_c
Bank_1.SP = VCC
Bank_1.LSR = GND
comp 59: SLICE_95 (FSLICE)
RA_c_8 = (~nRowColSel*RowA_8+nRowColSel*MAin_c_8)
Bank_6.D = Din_c_6
Bank_6.CLK = PHI2_c
Bank_6.SP = VCC
Bank_6.LSR = GND
RA_c_2 = (~nRowColSel*RowA_2+nRowColSel*MAin_c_2)
Bank_7.D = Din_c_7
Bank_7.CLK = PHI2_c
Bank_7.SP = VCC
Bank_7.LSR = GND
comp 60: SLICE_96 (FSLICE)
n2299 = (~Ready+nRowColSel_N_35)
XOR8MEG.D = Din_c_0
XOR8MEG.CLK = ~PHI2_c
XOR8MEG.SP = PHI2_N_114_enable_2
XOR8MEG.LSR = GND
n2297 = (~nRowColSel_N_35+nRCS_N_135)
comp 61: SLICE_97 (FSLICE)
RA_c_7 = (~nRowColSel*RowA_7+nRowColSel*MAin_c_7)
Bank_4.D = Din_c_4
Bank_4.CLK = PHI2_c
Bank_4.SP = VCC
Bank_4.LSR = GND
n2170 = (Bank_1*(Bank_4*(MAin_c_3*MAin_c_7)))
Bank_5.D = Din_c_5
Bank_5.CLK = PHI2_c
Bank_5.SP = VCC
Bank_5.LSR = GND
comp 62: SLICE_98 (FSLICE)
RA_c_6 = (~nRowColSel*RowA_6+nRowColSel*MAin_c_6)
Bank_2.D = Din_c_2
Bank_2.CLK = PHI2_c
Bank_2.SP = VCC
Bank_2.LSR = GND
RA_c_5 = (~nRowColSel*RowA_5+nRowColSel*MAin_c_5)
Bank_3.D = Din_c_3
Bank_3.CLK = PHI2_c
Bank_3.SP = VCC
Bank_3.LSR = GND
comp 63: SLICE_99 (FSLICE)
n2164 = (nRCAS_N_161+nRWE_N_173)
RBA_c_0.D = CROW_c_0
RBA_c_0.CLK = ~nCRAS_c
RBA_c_0.SP = VCC
RBA_c_0.LSR = ~Ready
n18 = (nRowColSel_N_34*~nRowColSel_N_35)
RBA_c_1.D = CROW_c_1
RBA_c_1.CLK = ~nCRAS_c
RBA_c_1.SP = VCC
RBA_c_1.LSR = ~Ready
comp 64: SLICE_100 (FSLICE)
n11_adj_3 = (~CASr2+nRowColSel_N_33)
WRD_4.D = Din_c_4
WRD_4.CLK = ~nCCAS_c
WRD_4.SP = VCC
WRD_4.LSR = GND
n2304 = (FWEr+CBR)
WRD_5.D = Din_c_5
WRD_5.CLK = ~nCCAS_c
WRD_5.SP = VCC
WRD_5.LSR = GND

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@ -0,0 +1,9 @@
-w
-l 5
-i 6
-n 1
-t 1
-s 1
-c 0
-e 0
-exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1

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@ -0,0 +1,9 @@
-w
-l 5
-i 6
-n 1
-t 1
-s 1
-c 0
-e 0
-exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1

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@ -0,0 +1,5 @@
-rem
-distrce
-log "RAM2GS_LCMXO256C_impl1.log"
-o "RAM2GS_LCMXO256C_impl1.csv"
-pr "RAM2GS_LCMXO256C_impl1.prf"

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@ -0,0 +1,271 @@
PAD Specification File
***************************
PART TYPE: LCMXO256C
Performance Grade: 3
PACKAGE: TQFP100
Package Status: Final Version 1.19
Mon Aug 16 21:32:33 2021
Pinout by Port Name:
+-----------+----------+--------------+------+----------------------------------+
| Port Name | Pin/Bank | Buffer Type | Site | Properties |
+-----------+----------+--------------+------+----------------------------------+
| CROW[0] | 32/1 | LVTTL33_IN | PB2C | SLEW:FAST |
| CROW[1] | 34/1 | LVTTL33_IN | PB2D | SLEW:FAST |
| Din[0] | 21/1 | LVTTL33_IN | PL8A | SLEW:FAST |
| Din[1] | 15/1 | LVTTL33_IN | PL6A | SLEW:FAST |
| Din[2] | 14/1 | LVTTL33_IN | PL5D | SLEW:FAST |
| Din[3] | 16/1 | LVTTL33_IN | PL6B | SLEW:FAST |
| Din[4] | 18/1 | LVTTL33_IN | PL7B | SLEW:FAST |
| Din[5] | 17/1 | LVTTL33_IN | PL7A | SLEW:FAST |
| Din[6] | 20/1 | LVTTL33_IN | PL7D | SLEW:FAST |
| Din[7] | 19/1 | LVTTL33_IN | PL7C | SLEW:FAST |
| Dout[0] | 1/1 | LVTTL33_OUT | PL2A | DRIVE:4mA SLEW:SLOW |
| Dout[1] | 7/1 | LVTTL33_OUT | PL4A | DRIVE:4mA SLEW:SLOW |
| Dout[2] | 8/1 | LVTTL33_OUT | PL4B | DRIVE:4mA SLEW:SLOW |
| Dout[3] | 6/1 | LVTTL33_OUT | PL3D | DRIVE:4mA SLEW:SLOW |
| Dout[4] | 4/1 | LVTTL33_OUT | PL3B | DRIVE:4mA SLEW:SLOW |
| Dout[5] | 5/1 | LVTTL33_OUT | PL3C | DRIVE:4mA SLEW:SLOW |
| Dout[6] | 2/1 | LVTTL33_OUT | PL2B | DRIVE:4mA SLEW:SLOW |
| Dout[7] | 3/1 | LVTTL33_OUT | PL3A | DRIVE:4mA SLEW:SLOW |
| LED | 57/0 | LVTTL33_OUT | PR7B | DRIVE:16mA SLEW:SLOW |
| MAin[0] | 23/1 | LVTTL33_IN | PL9A | SLEW:FAST |
| MAin[1] | 38/1 | LVTTL33_IN | PB3C | SLEW:FAST |
| MAin[2] | 37/1 | LVTTL33_IN | PB3B | SLEW:FAST |
| MAin[3] | 47/1 | LVTTL33_IN | PB5A | SLEW:FAST |
| MAin[4] | 46/1 | LVTTL33_IN | PB4D | SLEW:FAST |
| MAin[5] | 45/1 | LVTTL33_IN | PB4C | SLEW:FAST |
| MAin[6] | 49/1 | LVTTL33_IN | PB5C | SLEW:FAST |
| MAin[7] | 44/1 | LVTTL33_IN | PB4B | SLEW:FAST |
| MAin[8] | 50/1 | LVTTL33_IN | PB5D | SLEW:FAST |
| MAin[9] | 51/0 | LVTTL33_IN | PR9B | SLEW:FAST |
| PHI2 | 39/1 | LVTTL33_IN | PB3D | SLEW:FAST |
| RA[0] | 98/0 | LVTTL33_OUT | PT2C | DRIVE:4mA SLEW:SLOW |
| RA[10] | 87/0 | LVTTL33_OUT | PT3D | DRIVE:4mA SLEW:SLOW |
| RA[11] | 79/0 | LVTTL33_OUT | PT5A | DRIVE:4mA SLEW:SLOW |
| RA[1] | 89/0 | LVTTL33_OUT | PT3C | DRIVE:4mA SLEW:SLOW |
| RA[2] | 94/0 | LVTTL33_OUT | PT3A | DRIVE:4mA SLEW:SLOW |
| RA[3] | 97/0 | LVTTL33_OUT | PT2D | DRIVE:4mA SLEW:SLOW |
| RA[4] | 99/0 | LVTTL33_OUT | PT2B | DRIVE:4mA SLEW:SLOW |
| RA[5] | 95/0 | LVTTL33_OUT | PT2F | DRIVE:4mA SLEW:SLOW |
| RA[6] | 91/0 | LVTTL33_OUT | PT3B | DRIVE:4mA SLEW:SLOW |
| RA[7] | 100/0 | LVTTL33_OUT | PT2A | DRIVE:4mA SLEW:SLOW |
| RA[8] | 96/0 | LVTTL33_OUT | PT2E | DRIVE:4mA SLEW:SLOW |
| RA[9] | 85/0 | LVTTL33_OUT | PT4B | DRIVE:4mA SLEW:SLOW |
| RBA[0] | 63/0 | LVTTL33_OUT | PR5D | DRIVE:4mA SLEW:SLOW |
| RBA[1] | 83/0 | LVTTL33_OUT | PT4C | DRIVE:4mA SLEW:SLOW |
| RCKE | 82/0 | LVTTL33_OUT | PT4D | DRIVE:4mA SLEW:SLOW |
| RCLK | 86/0 | LVTTL33_IN | PT4A | SLEW:FAST |
| RDQMH | 76/0 | LVTTL33_OUT | PR2A | DRIVE:4mA SLEW:SLOW |
| RDQML | 61/0 | LVTTL33_OUT | PR6A | DRIVE:4mA SLEW:SLOW |
| RD[0] | 64/0 | LVTTL33_BIDI | PR5C | DRIVE:4mA SLEW:SLOW PULL:KEEPER |
| RD[1] | 65/0 | LVTTL33_BIDI | PR5B | DRIVE:4mA SLEW:SLOW PULL:KEEPER |
| RD[2] | 66/0 | LVTTL33_BIDI | PR5A | DRIVE:4mA SLEW:SLOW PULL:KEEPER |
| RD[3] | 67/0 | LVTTL33_BIDI | PR4B | DRIVE:4mA SLEW:SLOW PULL:KEEPER |
| RD[4] | 68/0 | LVTTL33_BIDI | PR4A | DRIVE:4mA SLEW:SLOW PULL:KEEPER |
| RD[5] | 69/0 | LVTTL33_BIDI | PR3D | DRIVE:4mA SLEW:SLOW PULL:KEEPER |
| RD[6] | 70/0 | LVTTL33_BIDI | PR3C | DRIVE:4mA SLEW:SLOW PULL:KEEPER |
| RD[7] | 71/0 | LVTTL33_BIDI | PR3B | DRIVE:4mA SLEW:SLOW PULL:KEEPER |
| UFMCLK | 58/0 | LVTTL33_OUT | PR7A | DRIVE:4mA SLEW:SLOW |
| UFMSDI | 56/0 | LVTTL33_OUT | PR7C | DRIVE:4mA SLEW:SLOW |
| UFMSDO | 55/0 | LVTTL33_IN | PR7D | SLEW:FAST PULL:KEEPER |
| nCCAS | 27/1 | LVTTL33_IN | PL9B | SLEW:FAST |
| nCRAS | 43/1 | LVTTL33_IN | PB4A | SLEW:FAST |
| nFWE | 22/1 | LVTTL33_IN | PL8B | SLEW:FAST |
| nRCAS | 78/0 | LVTTL33_OUT | PT5B | DRIVE:4mA SLEW:SLOW |
| nRCS | 77/0 | LVTTL33_OUT | PT5C | DRIVE:4mA SLEW:SLOW |
| nRRAS | 73/0 | LVTTL33_OUT | PR2B | DRIVE:4mA SLEW:SLOW |
| nRWE | 72/0 | LVTTL33_OUT | PR3A | DRIVE:4mA SLEW:SLOW |
| nUFMCS | 53/0 | LVTTL33_OUT | PR8B | DRIVE:4mA SLEW:SLOW |
+-----------+----------+--------------+------+----------------------------------+
Vccio by Bank:
+------+-------+
| Bank | Vccio |
+------+-------+
| 0 | 3.3V |
| 1 | 3.3V |
+------+-------+
Vref by Bank:
+------+-----+-----------------+---------+
| Vref | Pin | Bank # / Vref # | Load(s) |
+------+-----+-----------------+---------+
+------+-----+-----------------+---------+
Pinout by Pin Number:
+----------+---------------------+------------+--------------+------+---------------+
| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function |
+----------+---------------------+------------+--------------+------+---------------+
| 1/1 | Dout[0] | LOCATED | LVTTL33_OUT | PL2A | |
| 2/1 | Dout[6] | LOCATED | LVTTL33_OUT | PL2B | |
| 3/1 | Dout[7] | LOCATED | LVTTL33_OUT | PL3A | |
| 4/1 | Dout[4] | LOCATED | LVTTL33_OUT | PL3B | |
| 5/1 | Dout[5] | LOCATED | LVTTL33_OUT | PL3C | |
| 6/1 | Dout[3] | LOCATED | LVTTL33_OUT | PL3D | |
| 7/1 | Dout[1] | LOCATED | LVTTL33_OUT | PL4A | |
| 8/1 | Dout[2] | LOCATED | LVTTL33_OUT | PL4B | |
| 9/1 | unused, PULL:UP | | | PL5A | |
| 11/1 | unused, PULL:UP | | | PL5B | |
| 13/1 | unused, PULL:UP | | | PL5C | |
| 14/1 | Din[2] | LOCATED | LVTTL33_IN | PL5D | GSR_PADN |
| 15/1 | Din[1] | LOCATED | LVTTL33_IN | PL6A | |
| 16/1 | Din[3] | LOCATED | LVTTL33_IN | PL6B | TSALLPAD |
| 17/1 | Din[5] | LOCATED | LVTTL33_IN | PL7A | |
| 18/1 | Din[4] | LOCATED | LVTTL33_IN | PL7B | |
| 19/1 | Din[7] | LOCATED | LVTTL33_IN | PL7C | |
| 20/1 | Din[6] | LOCATED | LVTTL33_IN | PL7D | |
| 21/1 | Din[0] | LOCATED | LVTTL33_IN | PL8A | |
| 22/1 | nFWE | LOCATED | LVTTL33_IN | PL8B | |
| 23/1 | MAin[0] | LOCATED | LVTTL33_IN | PL9A | |
| 27/1 | nCCAS | LOCATED | LVTTL33_IN | PL9B | |
| 29/1 | unused, PULL:UP | | | PB2A | |
| 30/1 | unused, PULL:UP | | | PB2B | |
| 32/1 | CROW[0] | LOCATED | LVTTL33_IN | PB2C | |
| 34/1 | CROW[1] | LOCATED | LVTTL33_IN | PB2D | |
| 36/1 | unused, PULL:UP | | | PB3A | PCLKT1_1 |
| 37/1 | MAin[2] | LOCATED | LVTTL33_IN | PB3B | |
| 38/1 | MAin[1] | LOCATED | LVTTL33_IN | PB3C | PCLKT1_0 |
| 39/1 | PHI2 | LOCATED | LVTTL33_IN | PB3D | |
| 43/1 | nCRAS | LOCATED | LVTTL33_IN | PB4A | |
| 44/1 | MAin[7] | LOCATED | LVTTL33_IN | PB4B | |
| 45/1 | MAin[5] | LOCATED | LVTTL33_IN | PB4C | |
| 46/1 | MAin[4] | LOCATED | LVTTL33_IN | PB4D | |
| 47/1 | MAin[3] | LOCATED | LVTTL33_IN | PB5A | |
| 49/1 | MAin[6] | LOCATED | LVTTL33_IN | PB5C | |
| 50/1 | MAin[8] | LOCATED | LVTTL33_IN | PB5D | |
| 51/0 | MAin[9] | LOCATED | LVTTL33_IN | PR9B | |
| 52/0 | unused, PULL:UP | | | PR9A | |
| 53/0 | nUFMCS | LOCATED | LVTTL33_OUT | PR8B | |
| 54/0 | unused, PULL:UP | | | PR8A | |
| 55/0 | UFMSDO | LOCATED | LVTTL33_IN | PR7D | |
| 56/0 | UFMSDI | LOCATED | LVTTL33_OUT | PR7C | |
| 57/0 | LED | LOCATED | LVTTL33_OUT | PR7B | |
| 58/0 | UFMCLK | LOCATED | LVTTL33_OUT | PR7A | |
| 59/0 | unused, PULL:UP | | | PR6B | |
| 61/0 | RDQML | LOCATED | LVTTL33_OUT | PR6A | |
| 63/0 | RBA[0] | LOCATED | LVTTL33_OUT | PR5D | |
| 64/0 | RD[0] | LOCATED | LVTTL33_BIDI | PR5C | |
| 65/0 | RD[1] | LOCATED | LVTTL33_BIDI | PR5B | |
| 66/0 | RD[2] | LOCATED | LVTTL33_BIDI | PR5A | |
| 67/0 | RD[3] | LOCATED | LVTTL33_BIDI | PR4B | |
| 68/0 | RD[4] | LOCATED | LVTTL33_BIDI | PR4A | |
| 69/0 | RD[5] | LOCATED | LVTTL33_BIDI | PR3D | |
| 70/0 | RD[6] | LOCATED | LVTTL33_BIDI | PR3C | |
| 71/0 | RD[7] | LOCATED | LVTTL33_BIDI | PR3B | |
| 72/0 | nRWE | LOCATED | LVTTL33_OUT | PR3A | |
| 73/0 | nRRAS | LOCATED | LVTTL33_OUT | PR2B | |
| 76/0 | RDQMH | LOCATED | LVTTL33_OUT | PR2A | |
| 77/0 | nRCS | LOCATED | LVTTL33_OUT | PT5C | |
| 78/0 | nRCAS | LOCATED | LVTTL33_OUT | PT5B | |
| 79/0 | RA[11] | LOCATED | LVTTL33_OUT | PT5A | |
| 80/0 | unused, PULL:UP | | | PT4F | |
| 81/0 | unused, PULL:UP | | | PT4E | |
| 82/0 | RCKE | LOCATED | LVTTL33_OUT | PT4D | |
| 83/0 | RBA[1] | LOCATED | LVTTL33_OUT | PT4C | |
| 85/0 | RA[9] | LOCATED | LVTTL33_OUT | PT4B | PCLKT0_1 |
| 86/0 | RCLK | LOCATED | LVTTL33_IN | PT4A | PCLKT0_0 |
| 87/0 | RA[10] | LOCATED | LVTTL33_OUT | PT3D | |
| 89/0 | RA[1] | LOCATED | LVTTL33_OUT | PT3C | |
| 91/0 | RA[6] | LOCATED | LVTTL33_OUT | PT3B | |
| 94/0 | RA[2] | LOCATED | LVTTL33_OUT | PT3A | |
| 95/0 | RA[5] | LOCATED | LVTTL33_OUT | PT2F | |
| 96/0 | RA[8] | LOCATED | LVTTL33_OUT | PT2E | |
| 97/0 | RA[3] | LOCATED | LVTTL33_OUT | PT2D | |
| 98/0 | RA[0] | LOCATED | LVTTL33_OUT | PT2C | |
| 99/0 | RA[4] | LOCATED | LVTTL33_OUT | PT2B | |
| 100/0 | RA[7] | LOCATED | LVTTL33_OUT | PT2A | |
| PB5B/0 | unused, PULL:UP | | | PB5B | |
| PT5D/0 | unused, PULL:UP | | | PT5D | |
| TCK/1 | | | | TCK | TCK |
| TDI/1 | | | | TDI | TDI |
| TDO/1 | | | | TDO | TDO |
| TMS/1 | | | | TMS | TMS |
+----------+---------------------+------------+--------------+------+---------------+
List of All Pins' Locate Preferences Based on Final Placement After PAR
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste):
LOCATE COMP "CROW[0]" SITE "32";
LOCATE COMP "CROW[1]" SITE "34";
LOCATE COMP "Din[0]" SITE "21";
LOCATE COMP "Din[1]" SITE "15";
LOCATE COMP "Din[2]" SITE "14";
LOCATE COMP "Din[3]" SITE "16";
LOCATE COMP "Din[4]" SITE "18";
LOCATE COMP "Din[5]" SITE "17";
LOCATE COMP "Din[6]" SITE "20";
LOCATE COMP "Din[7]" SITE "19";
LOCATE COMP "Dout[0]" SITE "1";
LOCATE COMP "Dout[1]" SITE "7";
LOCATE COMP "Dout[2]" SITE "8";
LOCATE COMP "Dout[3]" SITE "6";
LOCATE COMP "Dout[4]" SITE "4";
LOCATE COMP "Dout[5]" SITE "5";
LOCATE COMP "Dout[6]" SITE "2";
LOCATE COMP "Dout[7]" SITE "3";
LOCATE COMP "LED" SITE "57";
LOCATE COMP "MAin[0]" SITE "23";
LOCATE COMP "MAin[1]" SITE "38";
LOCATE COMP "MAin[2]" SITE "37";
LOCATE COMP "MAin[3]" SITE "47";
LOCATE COMP "MAin[4]" SITE "46";
LOCATE COMP "MAin[5]" SITE "45";
LOCATE COMP "MAin[6]" SITE "49";
LOCATE COMP "MAin[7]" SITE "44";
LOCATE COMP "MAin[8]" SITE "50";
LOCATE COMP "MAin[9]" SITE "51";
LOCATE COMP "PHI2" SITE "39";
LOCATE COMP "RA[0]" SITE "98";
LOCATE COMP "RA[10]" SITE "87";
LOCATE COMP "RA[11]" SITE "79";
LOCATE COMP "RA[1]" SITE "89";
LOCATE COMP "RA[2]" SITE "94";
LOCATE COMP "RA[3]" SITE "97";
LOCATE COMP "RA[4]" SITE "99";
LOCATE COMP "RA[5]" SITE "95";
LOCATE COMP "RA[6]" SITE "91";
LOCATE COMP "RA[7]" SITE "100";
LOCATE COMP "RA[8]" SITE "96";
LOCATE COMP "RA[9]" SITE "85";
LOCATE COMP "RBA[0]" SITE "63";
LOCATE COMP "RBA[1]" SITE "83";
LOCATE COMP "RCKE" SITE "82";
LOCATE COMP "RCLK" SITE "86";
LOCATE COMP "RDQMH" SITE "76";
LOCATE COMP "RDQML" SITE "61";
LOCATE COMP "RD[0]" SITE "64";
LOCATE COMP "RD[1]" SITE "65";
LOCATE COMP "RD[2]" SITE "66";
LOCATE COMP "RD[3]" SITE "67";
LOCATE COMP "RD[4]" SITE "68";
LOCATE COMP "RD[5]" SITE "69";
LOCATE COMP "RD[6]" SITE "70";
LOCATE COMP "RD[7]" SITE "71";
LOCATE COMP "UFMCLK" SITE "58";
LOCATE COMP "UFMSDI" SITE "56";
LOCATE COMP "UFMSDO" SITE "55";
LOCATE COMP "nCCAS" SITE "27";
LOCATE COMP "nCRAS" SITE "43";
LOCATE COMP "nFWE" SITE "22";
LOCATE COMP "nRCAS" SITE "78";
LOCATE COMP "nRCS" SITE "77";
LOCATE COMP "nRRAS" SITE "73";
LOCATE COMP "nRWE" SITE "72";
LOCATE COMP "nUFMCS" SITE "53";
PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Mon Aug 16 21:32:33 2021

View File

@ -0,0 +1,239 @@
PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Mon Aug 16 21:32:27 2021
C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO256C_impl1.p2t
RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir
RAM2GS_LCMXO256C_impl1.prf -gui -msgset
C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml
Preference file: RAM2GS_LCMXO256C_impl1.prf.
Level/ Number Worst Timing Worst Timing Run NCD
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
---------- -------- ----- ------ ----------- ----------- ---- ------
5_1 * 0 2.023 0 0.339 0 07 Completed
* : Design saved.
Total (real) run time for 1-seed: 7 secs
par done!
Note: user must run 'Trace' for timing closure signoff.
Lattice Place and Route Report for Design "RAM2GS_LCMXO256C_impl1_map.ncd"
Mon Aug 16 21:32:27 2021
PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir/5_1.ncd RAM2GS_LCMXO256C_impl1.prf
Preference file: RAM2GS_LCMXO256C_impl1.prf.
Placement level-cost: 5-1.
Routing Iterations: 6
Loading design for application par from file RAM2GS_LCMXO256C_impl1_map.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO256C
Package: TQFP100
Performance: 3
Loading device for application par from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.19.
Performance Hardware Data Status: Version 1.124.
License checked out.
Ignore Preference Error(s): True
Device utilization summary:
PIO (prelim) 67/79 84% used
67/78 85% bonded
SLICE 65/128 50% used
Number of Signals: 252
Number of Connections: 618
Pin Constraint Summary:
67 out of 67 pins locked (100% locked).
The following 4 signals are selected to use the primary clock routing resources:
RCLK_c (driver: RCLK, clk load #: 39)
PHI2_c (driver: PHI2, clk load #: 13)
nCCAS_c (driver: nCCAS, clk load #: 4)
nCRAS_c (driver: nCRAS, clk load #: 7)
No signal is selected as secondary clock.
No signal is selected as Global Set/Reset.
Starting Placer Phase 0.
........
Finished Placer Phase 0. REAL time: 0 secs
Starting Placer Phase 1.
...............
Placer score = 586066.
Finished Placer Phase 1. REAL time: 6 secs
Starting Placer Phase 2.
.
Placer score = 584668
Finished Placer Phase 2. REAL time: 6 secs
------------------ Clock Report ------------------
Global Clock Resources:
CLK_PIN : 1 out of 4 (25%)
General PIO: 3 out of 80 (3%)
Global Clocks:
PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "86 (PT4A)", clk load = 39
PRIMARY "PHI2_c" from comp "PHI2" on PIO site "39 (PB3D)", clk load = 13
PRIMARY "nCCAS_c" from comp "nCCAS" on PIO site "27 (PL9B)", clk load = 4
PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "43 (PB4A)", clk load = 7
PRIMARY : 4 out of 4 (100%)
SECONDARY: 0 out of 4 (0%)
--------------- End of Clock Report ---------------
I/O Usage Summary (final):
67 out of 79 (84.8%) PIO sites used.
67 out of 78 (85.9%) bonded PIO sites used.
Number of PIO comps: 67; differential: 0.
Number of Vref pins used: 0.
I/O Bank Usage Summary:
+----------+----------------+------------+------------+------------+
| I/O Bank | Usage | Bank Vccio | Bank Vref1 | Bank Vref2 |
+----------+----------------+------------+------------+------------+
| 0 | 36 / 41 ( 87%) | 3.3V | - | - |
| 1 | 31 / 37 ( 83%) | 3.3V | - | - |
+----------+----------------+------------+------------+------------+
Total placer CPU time: 6 secs
Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd.
0 connections routed; 618 unrouted.
Starting router resource preassignment
WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
WARNING - par: The driver of primary clock net nCCAS_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
Completed router resource preassignment. Real time: 6 secs
Start NBR router at 21:32:33 08/16/21
*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
in the earlier iterations. In each iteration, it tries to
solve the conflicts while keeping the critical connections
routed as short as possible. The routing process is said to
be completed when no conflicts exist and all connections
are routed.
Note: NBR uses a different method to calculate timing slacks. The
worst slack and total negative slack may not be the same as
that in TRCE report. You should always run TRCE to verify
your design.
*****************************************************************
Start NBR special constraint process at 21:32:33 08/16/21
Start NBR section for initial routing at 21:32:33 08/16/21
Level 1, iteration 1
0(0.00%) conflict; 535(86.57%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 2.084ns/0.000ns; real time: 6 secs
Level 2, iteration 1
0(0.00%) conflict; 535(86.57%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 2.084ns/0.000ns; real time: 6 secs
Level 3, iteration 1
0(0.00%) conflict; 509(82.36%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 2.038ns/0.000ns; real time: 6 secs
Level 4, iteration 1
23(0.19%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs
Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area at 75% usage is 0 (0.00%)
Start NBR section for normal routing at 21:32:33 08/16/21
Level 1, iteration 1
0(0.00%) conflict; 24(3.88%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs
Level 4, iteration 1
8(0.07%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs
Level 4, iteration 2
4(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs
Level 4, iteration 3
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs
Start NBR section for setup/hold timing optimization with effort level 3 at 21:32:33 08/16/21
Start NBR section for re-routing at 21:32:33 08/16/21
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 2.023ns/0.000ns; real time: 6 secs
Start NBR section for post-routing at 21:32:33 08/16/21
End NBR router with 0 unrouted connection
NBR Summary
-----------
Number of unrouted connections : 0 (0.00%)
Number of connections with timing violations : 0 (0.00%)
Estimated worst slack<setup> : 2.023ns
Timing score<setup> : 0
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
Total CPU time 6 secs
Total REAL time: 7 secs
Completely routed.
End of route. 618 routed (100.00%); 0 unrouted.
Hold time timing score: 0, hold timing errors: 0
Timing score: 0
Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd.
All signals are completely routed.
PAR_SUMMARY::Run status = Completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst slack<setup/<ns>> = 2.023
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.339
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
PAR_SUMMARY::Number of errors = 0
Total CPU time to completion: 6 secs
Total REAL time to completion: 7 secs
par done!
Note: user must run 'Trace' for timing closure signoff.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.

View File

@ -0,0 +1,165 @@
SCHEMATIC START ;
# map: version Diamond (64-bit) 3.12.0.240.2 -- WARNING: Map write only section -- Mon Aug 16 21:32:26 2021
SYSCONFIG INBUF=ON CONFIG_SECURE=OFF ;
LOCATE COMP "RD[7]" SITE "71" ;
LOCATE COMP "RD[6]" SITE "70" ;
LOCATE COMP "RD[5]" SITE "69" ;
LOCATE COMP "RD[4]" SITE "68" ;
LOCATE COMP "RD[3]" SITE "67" ;
LOCATE COMP "RD[2]" SITE "66" ;
LOCATE COMP "RD[1]" SITE "65" ;
LOCATE COMP "RD[0]" SITE "64" ;
LOCATE COMP "Dout[7]" SITE "3" ;
LOCATE COMP "Dout[6]" SITE "2" ;
LOCATE COMP "Dout[5]" SITE "5" ;
LOCATE COMP "Dout[4]" SITE "4" ;
LOCATE COMP "Dout[3]" SITE "6" ;
LOCATE COMP "Dout[2]" SITE "8" ;
LOCATE COMP "Dout[1]" SITE "7" ;
LOCATE COMP "Dout[0]" SITE "1" ;
LOCATE COMP "LED" SITE "57" ;
LOCATE COMP "RBA[1]" SITE "83" ;
LOCATE COMP "RBA[0]" SITE "63" ;
LOCATE COMP "RA[11]" SITE "79" ;
LOCATE COMP "RA[10]" SITE "87" ;
LOCATE COMP "RA[9]" SITE "85" ;
LOCATE COMP "RA[8]" SITE "96" ;
LOCATE COMP "RA[7]" SITE "100" ;
LOCATE COMP "RA[6]" SITE "91" ;
LOCATE COMP "RA[5]" SITE "95" ;
LOCATE COMP "RA[4]" SITE "99" ;
LOCATE COMP "RA[3]" SITE "97" ;
LOCATE COMP "RA[2]" SITE "94" ;
LOCATE COMP "RA[1]" SITE "89" ;
LOCATE COMP "RA[0]" SITE "98" ;
LOCATE COMP "nRCS" SITE "77" ;
LOCATE COMP "RCKE" SITE "82" ;
LOCATE COMP "nRWE" SITE "72" ;
LOCATE COMP "nRRAS" SITE "73" ;
LOCATE COMP "nRCAS" SITE "78" ;
LOCATE COMP "RDQMH" SITE "76" ;
LOCATE COMP "RDQML" SITE "61" ;
LOCATE COMP "nUFMCS" SITE "53" ;
LOCATE COMP "UFMCLK" SITE "58" ;
LOCATE COMP "UFMSDI" SITE "56" ;
LOCATE COMP "PHI2" SITE "39" ;
LOCATE COMP "MAin[9]" SITE "51" ;
LOCATE COMP "MAin[8]" SITE "50" ;
LOCATE COMP "MAin[7]" SITE "44" ;
LOCATE COMP "MAin[6]" SITE "49" ;
LOCATE COMP "MAin[5]" SITE "45" ;
LOCATE COMP "MAin[4]" SITE "46" ;
LOCATE COMP "MAin[3]" SITE "47" ;
LOCATE COMP "MAin[2]" SITE "37" ;
LOCATE COMP "MAin[1]" SITE "38" ;
LOCATE COMP "MAin[0]" SITE "23" ;
LOCATE COMP "CROW[1]" SITE "34" ;
LOCATE COMP "CROW[0]" SITE "32" ;
LOCATE COMP "Din[7]" SITE "19" ;
LOCATE COMP "Din[6]" SITE "20" ;
LOCATE COMP "Din[5]" SITE "17" ;
LOCATE COMP "Din[4]" SITE "18" ;
LOCATE COMP "Din[3]" SITE "16" ;
LOCATE COMP "Din[2]" SITE "14" ;
LOCATE COMP "Din[1]" SITE "15" ;
LOCATE COMP "Din[0]" SITE "21" ;
LOCATE COMP "nCCAS" SITE "27" ;
LOCATE COMP "nCRAS" SITE "43" ;
LOCATE COMP "nFWE" SITE "22" ;
LOCATE COMP "RCLK" SITE "86" ;
LOCATE COMP "UFMSDO" SITE "55" ;
PERIOD NET "PHI2_c" 350.000000 ns ;
USE PRIMARY NET "RCLK_c" ;
PERIOD NET "nCCAS_c" 350.000000 ns ;
USE PRIMARY NET "PHI2_c" ;
PERIOD NET "nCRAS_c" 350.000000 ns ;
USE PRIMARY NET "nCCAS_c" ;
PERIOD NET "RCLK_c" 16.000000 ns ;
USE PRIMARY NET "nCRAS_c" ;
SCHEMATIC END ;
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
OUTPUT PORT "RD[7]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[0]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[1]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[2]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[3]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[4]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[5]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[6]" LOAD 20.000000 pF ;
OUTPUT PORT "nUFMCS" LOAD 15.000000 pF ;
OUTPUT PORT "UFMCLK" LOAD 15.000000 pF ;
OUTPUT PORT "UFMSDI" LOAD 15.000000 pF ;
OUTPUT PORT "nRWE" LOAD 10.000000 pF ;
OUTPUT PORT "nRCAS" LOAD 10.000000 pF ;
OUTPUT PORT "nRCS" LOAD 10.000000 pF ;
OUTPUT PORT "nRRAS" LOAD 10.000000 pF ;
OUTPUT PORT "RDQML" LOAD 10.000000 pF ;
OUTPUT PORT "RDQMH" LOAD 10.000000 pF ;
OUTPUT PORT "RCKE" LOAD 10.000000 pF ;
OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ;
OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[11]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[10]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[9]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[8]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[7]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[6]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[5]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[4]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[3]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[2]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[1]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[0]" LOAD 10.000000 pF ;
OUTPUT PORT "LED" LOAD 25.000000 pF ;
OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ;
VOLTAGE 3.300 V;
VCCIO_DERATE BANK 0 PERCENT -5;
VCCIO_DERATE PERCENT -5;
VCCIO_DERATE BANK 1 PERCENT -5;
CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
COMMERCIAL ;

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-v
10
-gt
-sethld
-sp 3
-sphld m

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-g ES:No

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<HTML>
<HEAD><TITLE>Bitgen Report</TITLE>
<STYLE TYPE="text/css">
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<PRE><A name="Bgn"></A>BITGEN: Bitstream Generator Diamond (64-bit) 3.12.0.240.2
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Mon Aug 16 21:36:25 2021
Command: bitgen -w -g ES:No -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf
Loading design for application Bitgen from file RAM2GS_LCMXO256C_impl1.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO256C
Package: TQFP100
Performance: 3
Loading device for application Bitgen from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.19.
Performance Hardware Data Status: Version 1.124.
Running DRC.
DRC detected 0 errors and 0 warnings.
Reading Preference File from RAM2GS_LCMXO256C_impl1.prf.
<A name="bgn_ps"></A>
<B><U><big>Preference Summary:</big></U></B>
+---------------------------------+---------------------------------+
| Preference | Current Setting |
+---------------------------------+---------------------------------+
| CONFIG_SECURE | OFF** |
+---------------------------------+---------------------------------+
| INBUF | ON** |
+---------------------------------+---------------------------------+
| ES | No** |
+---------------------------------+---------------------------------+
* Default setting.
** The specified setting matches the default setting.
Creating bit map...
Saving bit stream in "RAM2GS_LCMXO256C_impl1.bit".
Total CPU Time: 0 secs
Total REAL Time: 0 secs
Peak Memory Usage: 44 MB
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<HEAD><TITLE>I/O Timing Report</TITLE>
<STYLE TYPE="text/css">
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<PRE><A name="Top"></A><B><U><big>I/O Timing Report</big></U></B>
Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO256C
Package: TQFP100
Performance: 4
Package Status: Final Version 1.19.
Performance Hardware Data Status: Version 1.124.
Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO256C
Package: TQFP100
Performance: 5
Package Status: Final Version 1.19.
Performance Hardware Data Status: Version 1.124.
Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO256C
Package: TQFP100
Performance: M
Package Status: Final Version 1.19.
Performance Hardware Data Status: Version 1.124.
// Design: RAM2GS
// Package: TQFP100
// ncd File: ram2gs_lcmxo256c_impl1.ncd
// Version: Diamond (64-bit) 3.12.0.240.2
// Written on Mon Aug 16 21:32:34 2021
// M: Minimum Performance Grade
// iotiming RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml
I/O Timing Report (All units are in ns)
Worst Case Results across Performance Grades (M, 5, 4, 3):
// Input Setup and Hold Times
Port Clock Edge Setup Performance_Grade Hold Performance_Grade
----------------------------------------------------------------------
CROW[0] nCRAS F 0.215 3 1.805 3
CROW[1] nCRAS F -0.050 M 2.105 3
Din[0] PHI2 F 5.083 3 2.097 3
Din[0] nCCAS F -0.020 M 2.133 3
Din[1] PHI2 F 3.519 3 2.454 3
Din[1] nCCAS F -0.146 M 2.462 3
Din[2] PHI2 F 4.416 3 2.660 3
Din[2] nCCAS F 0.272 3 1.853 3
Din[3] PHI2 F 5.627 3 2.084 3
Din[3] nCCAS F -0.024 M 2.144 3
Din[4] PHI2 F 4.808 3 2.117 3
Din[4] nCCAS F 0.350 3 1.766 3
Din[5] PHI2 F 5.446 3 2.212 3
Din[5] nCCAS F 0.435 3 1.708 3
Din[6] PHI2 F 5.339 3 1.487 3
Din[6] nCCAS F -0.140 M 2.452 3
Din[7] PHI2 F 4.546 3 1.555 3
Din[7] nCCAS F -0.016 M 2.122 3
MAin[0] PHI2 F 4.027 3 0.711 3
MAin[0] nCRAS F 1.132 3 0.987 3
MAin[1] PHI2 F 4.032 3 1.734 3
MAin[1] nCRAS F 0.704 3 1.373 3
MAin[2] PHI2 F 10.358 3 -0.773 M
MAin[2] nCRAS F -0.202 M 2.529 3
MAin[3] PHI2 F 10.442 3 -0.829 M
MAin[3] nCRAS F 0.186 3 1.819 3
MAin[4] PHI2 F 10.311 3 -0.765 M
MAin[4] nCRAS F 0.569 3 1.506 3
MAin[5] PHI2 F 7.007 3 0.178 3
MAin[5] nCRAS F 0.186 3 1.819 3
MAin[6] PHI2 F 9.786 3 -0.641 M
MAin[6] nCRAS F 0.177 3 1.829 3
MAin[7] PHI2 F 10.008 3 -0.718 M
MAin[7] nCRAS F -0.092 M 2.222 3
MAin[8] nCRAS F -0.202 M 2.532 3
MAin[9] nCRAS F 0.228 3 1.797 3
PHI2 RCLK R 5.091 3 -0.759 M
UFMSDO RCLK R 2.219 3 -0.104 M
nCCAS RCLK R 3.820 3 -0.611 M
nCCAS nCRAS F 1.538 3 0.708 3
nCRAS RCLK R 4.749 3 -0.670 M
nFWE PHI2 F 5.301 3 1.647 3
nFWE nCRAS F 1.049 3 1.128 3
// Clock to Output Delay
Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
------------------------------------------------------------------------
LED RCLK R 11.669 3 3.051 M
RA[0] RCLK R 9.674 3 2.492 M
RA[0] nCRAS F 12.127 3 3.067 M
RA[10] RCLK R 8.596 3 2.220 M
RA[11] PHI2 R 9.987 3 2.559 M
RA[1] RCLK R 8.766 3 2.284 M
RA[1] nCRAS F 11.652 3 2.982 M
RA[2] RCLK R 10.062 3 2.599 M
RA[2] nCRAS F 12.947 3 3.306 M
RA[3] RCLK R 9.933 3 2.555 M
RA[3] nCRAS F 12.783 3 3.240 M
RA[4] RCLK R 8.504 3 2.219 M
RA[4] nCRAS F 11.513 3 2.948 M
RA[5] RCLK R 9.609 3 2.481 M
RA[5] nCRAS F 11.870 3 3.010 M
RA[6] RCLK R 10.001 3 2.579 M
RA[6] nCRAS F 12.947 3 3.292 M
RA[7] RCLK R 10.255 3 2.652 M
RA[7] nCRAS F 12.177 3 3.089 M
RA[8] RCLK R 8.896 3 2.316 M
RA[8] nCRAS F 11.417 3 2.920 M
RA[9] RCLK R 8.766 3 2.284 M
RA[9] nCRAS F 11.617 3 2.957 M
RBA[0] nCRAS F 9.698 3 2.483 M
RBA[1] nCRAS F 11.425 3 2.916 M
RCKE RCLK R 9.080 3 2.363 M
RDQMH RCLK R 9.475 3 2.443 M
RDQML RCLK R 10.477 3 2.713 M
RD[0] nCCAS F 11.252 3 2.942 M
RD[1] nCCAS F 11.963 3 3.100 M
RD[2] nCCAS F 12.880 3 3.336 M
RD[3] nCCAS F 12.422 3 3.224 M
RD[4] nCCAS F 11.252 3 2.942 M
RD[5] nCCAS F 12.423 3 3.212 M
RD[6] nCCAS F 12.979 3 3.375 M
RD[7] nCCAS F 12.914 3 3.350 M
UFMCLK RCLK R 8.007 3 2.126 M
UFMSDI RCLK R 8.007 3 2.126 M
nRCAS RCLK R 8.595 3 2.232 M
nRCS RCLK R 7.429 3 1.949 M
nRRAS RCLK R 8.615 3 2.236 M
nRWE RCLK R 7.429 3 1.949 M
nUFMCS RCLK R 9.193 3 2.413 M
WARNING: you must also run trce with hold speed: 3
WARNING: you must also run trce with setup speed: M
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-a "MachXO"
-d LCMXO256C
-t TQFP100
-s 3
-frequency 200
-optimization_goal Balanced
-bram_utilization 100
-ramstyle Auto
-romstyle auto
-dsp_utilization 100
-use_dsp 1
-use_carry_chain 1
-carry_chain_length 0
-force_gsr Auto
-resource_sharing 1
-propagate_constants 1
-remove_duplicate_regs 1
-mux_style Auto
-max_fanout 1000
-fsm_encoding_style Auto
-twr_paths 3
-fix_gated_clocks 1
-loop_limit 1950
-use_io_insertion 1
-resolve_mixed_drivers 0
-use_io_reg auto
-lpf 1
-p "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C"
-ver "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v"
-top RAM2GS
-p "C:/lscc/diamond/3.12/ispfpga/mj5g00/data" "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/impl1" "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C"
-ngd "RAM2GS_LCMXO256C_impl1.ngd"

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[ActiveSupport MAP]
Device = LCMXO256C;
Package = TQFP100;
Performance = 3;
LUTS_avail = 256;
LUTS_used = 129;
FF_avail = 256;
FF_used = 102;
INPUT_LVTTL33 = 26;
OUTPUT_LVTTL33 = 33;
BIDI_LVTTL33 = 8;
IO_avail = 78;
IO_used = 67;

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[ START MERGED ]
nCRAS_N_9 nCRAS_c
nCCAS_N_3 nCCAS_c
n2307 Ready
n2306 nFWE_c
PHI2_N_114 PHI2_c
n2302 nRowColSel_N_35
nRWE_N_172 nRWE_N_173
UFMSDO_N_74 UFMSDO_c
n1377 nRowColSel_N_34
RASr2_N_63 RASr2
[ END MERGED ]
[ START CLIPPED ]
GND_net
VCC_net
FS_577_add_4_14/CO0
FS_577_add_4_16/CO0
FS_577_add_4_12/CO0
FS_577_add_4_2/CO0
FS_577_add_4_4/CO0
FS_577_add_4_6/CO0
FS_577_add_4_18/CO1
FS_577_add_4_18/CO0
FS_577_add_4_8/CO0
FS_577_add_4_10/CO0
[ END CLIPPED ]
[ START DESIGN PREFS ]
SCHEMATIC START ;
# map: version Diamond (64-bit) 3.12.0.240.2 -- WARNING: Map write only section -- Mon Aug 16 21:32:26 2021
SYSCONFIG INBUF=ON CONFIG_SECURE=OFF ;
LOCATE COMP "RD[7]" SITE "71" ;
LOCATE COMP "RD[6]" SITE "70" ;
LOCATE COMP "RD[5]" SITE "69" ;
LOCATE COMP "RD[4]" SITE "68" ;
LOCATE COMP "RD[3]" SITE "67" ;
LOCATE COMP "RD[2]" SITE "66" ;
LOCATE COMP "RD[1]" SITE "65" ;
LOCATE COMP "RD[0]" SITE "64" ;
LOCATE COMP "Dout[7]" SITE "3" ;
LOCATE COMP "Dout[6]" SITE "2" ;
LOCATE COMP "Dout[5]" SITE "5" ;
LOCATE COMP "Dout[4]" SITE "4" ;
LOCATE COMP "Dout[3]" SITE "6" ;
LOCATE COMP "Dout[2]" SITE "8" ;
LOCATE COMP "Dout[1]" SITE "7" ;
LOCATE COMP "Dout[0]" SITE "1" ;
LOCATE COMP "LED" SITE "57" ;
LOCATE COMP "RBA[1]" SITE "83" ;
LOCATE COMP "RBA[0]" SITE "63" ;
LOCATE COMP "RA[11]" SITE "79" ;
LOCATE COMP "RA[10]" SITE "87" ;
LOCATE COMP "RA[9]" SITE "85" ;
LOCATE COMP "RA[8]" SITE "96" ;
LOCATE COMP "RA[7]" SITE "100" ;
LOCATE COMP "RA[6]" SITE "91" ;
LOCATE COMP "RA[5]" SITE "95" ;
LOCATE COMP "RA[4]" SITE "99" ;
LOCATE COMP "RA[3]" SITE "97" ;
LOCATE COMP "RA[2]" SITE "94" ;
LOCATE COMP "RA[1]" SITE "89" ;
LOCATE COMP "RA[0]" SITE "98" ;
LOCATE COMP "nRCS" SITE "77" ;
LOCATE COMP "RCKE" SITE "82" ;
LOCATE COMP "nRWE" SITE "72" ;
LOCATE COMP "nRRAS" SITE "73" ;
LOCATE COMP "nRCAS" SITE "78" ;
LOCATE COMP "RDQMH" SITE "76" ;
LOCATE COMP "RDQML" SITE "61" ;
LOCATE COMP "nUFMCS" SITE "53" ;
LOCATE COMP "UFMCLK" SITE "58" ;
LOCATE COMP "UFMSDI" SITE "56" ;
LOCATE COMP "PHI2" SITE "39" ;
LOCATE COMP "MAin[9]" SITE "51" ;
LOCATE COMP "MAin[8]" SITE "50" ;
LOCATE COMP "MAin[7]" SITE "44" ;
LOCATE COMP "MAin[6]" SITE "49" ;
LOCATE COMP "MAin[5]" SITE "45" ;
LOCATE COMP "MAin[4]" SITE "46" ;
LOCATE COMP "MAin[3]" SITE "47" ;
LOCATE COMP "MAin[2]" SITE "37" ;
LOCATE COMP "MAin[1]" SITE "38" ;
LOCATE COMP "MAin[0]" SITE "23" ;
LOCATE COMP "CROW[1]" SITE "34" ;
LOCATE COMP "CROW[0]" SITE "32" ;
LOCATE COMP "Din[7]" SITE "19" ;
LOCATE COMP "Din[6]" SITE "20" ;
LOCATE COMP "Din[5]" SITE "17" ;
LOCATE COMP "Din[4]" SITE "18" ;
LOCATE COMP "Din[3]" SITE "16" ;
LOCATE COMP "Din[2]" SITE "14" ;
LOCATE COMP "Din[1]" SITE "15" ;
LOCATE COMP "Din[0]" SITE "21" ;
LOCATE COMP "nCCAS" SITE "27" ;
LOCATE COMP "nCRAS" SITE "43" ;
LOCATE COMP "nFWE" SITE "22" ;
LOCATE COMP "RCLK" SITE "86" ;
LOCATE COMP "UFMSDO" SITE "55" ;
PERIOD NET "PHI2_c" 350.000000 ns ;
USE PRIMARY NET "RCLK_c" ;
PERIOD NET "nCCAS_c" 350.000000 ns ;
USE PRIMARY NET "PHI2_c" ;
PERIOD NET "nCRAS_c" 350.000000 ns ;
USE PRIMARY NET "nCCAS_c" ;
PERIOD NET "RCLK_c" 16.000000 ns ;
USE PRIMARY NET "nCRAS_c" ;
SCHEMATIC END ;
[ END DESIGN PREFS ]

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---------------------------------------------------
Report for cell RAM2GS
Instance path: RAM2GS
Cell usage:
cell count Res Usage(%)
SLIC 65.00 100.0
LUT4 111.00 100.0
IOBUF 67 100.0
PFUREG 102 100.0
RIPPLE 9 100.0

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<HEAD><TITLE>Project Summary</TITLE>
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<PRE><A name="Mrp"></A>
Lattice Mapping Report File for Design Module 'RAM2GS'
<A name="mrp_di"></A><B><U><big>Design Information</big></U></B>
Command line: map -a MachXO -p LCMXO256C -t TQFP100 -s 3 -oc Commercial
RAM2GS_LCMXO256C_impl1.ngd -o RAM2GS_LCMXO256C_impl1_map.ncd -pr
RAM2GS_LCMXO256C_impl1.prf -mp RAM2GS_LCMXO256C_impl1.mrp -lpf C:/Users/Dog
/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.
lpf -lpf C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/RAM2GS_L
CMXO256C.lpf -c 0 -gui -msgset
C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml
Target Vendor: LATTICE
Target Device: LCMXO256CTQFP100
Target Performance: 3
Mapper: mj5g00, version: Diamond (64-bit) 3.12.0.240.2
Mapped on: 08/16/21 21:32:26
<A name="mrp_ds"></A><B><U><big>Design Summary</big></U></B>
Number of PFU registers: 102 out of 256 (40%)
Number of SLICEs: 65 out of 128 (51%)
SLICEs as Logic/ROM: 65 out of 128 (51%)
SLICEs as RAM: 0 out of 64 (0%)
SLICEs as Carry: 9 out of 128 (7%)
Number of LUT4s: 129 out of 256 (50%)
Number used as logic LUTs: 111
Number used as distributed RAM: 0
Number used as ripple logic: 18
Number used as shift registers: 0
Number of external PIOs: 67 out of 78 (86%)
Number of GSRs: 0 out of 1 (0%)
JTAG used : No
Readback used : No
Oscillator used : No
Startup used : No
Number of TSALL: 0 out of 1 (0%)
Notes:-
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
distributed RAMs) + 2*(Number of ripple logic)
2. Number of logic LUT4s does not include count of distributed RAM and
ripple logic.
Number of clocks: 4
Net RCLK_c: 39 loads, 39 rising, 0 falling (Driver: PIO RCLK )
Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 )
Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS )
Number of Clock Enables: 13
Net PHI2_N_114_enable_7: 2 loads, 2 LSLICEs
Net RCLK_c_enable_6: 1 loads, 1 LSLICEs
Net RCLK_c_enable_4: 3 loads, 3 LSLICEs
Net RCLK_c_enable_24: 2 loads, 2 LSLICEs
Net RCLK_c_enable_3: 1 loads, 1 LSLICEs
Net RCLK_c_enable_7: 1 loads, 1 LSLICEs
Net RCLK_c_enable_23: 8 loads, 8 LSLICEs
Net PHI2_N_114_enable_1: 1 loads, 1 LSLICEs
Net PHI2_N_114_enable_8: 1 loads, 1 LSLICEs
Net PHI2_N_114_enable_6: 2 loads, 2 LSLICEs
Net PHI2_N_114_enable_2: 1 loads, 1 LSLICEs
Net RCLK_c_enable_25: 1 loads, 1 LSLICEs
Net Ready_N_268: 1 loads, 1 LSLICEs
Number of LSRs: 9
Net RASr2: 1 loads, 1 LSLICEs
Net C1Submitted_N_225: 2 loads, 2 LSLICEs
Net n2299: 1 loads, 1 LSLICEs
Net nRowColSel_N_35: 1 loads, 1 LSLICEs
Net nRowColSel_N_34: 1 loads, 1 LSLICEs
Net LEDEN_N_88: 1 loads, 1 LSLICEs
Net n2291: 2 loads, 2 LSLICEs
Net Ready: 7 loads, 7 LSLICEs
Net nRWE_N_173: 1 loads, 1 LSLICEs
Number of nets driven by tri-state buffers: 0
Top 10 highest fanout non-clock nets:
Net Ready: 19 loads
Net InitReady: 17 loads
Net RASr2: 16 loads
Net nRowColSel_N_35: 14 loads
Net nRowColSel: 13 loads
Net Din_c_6: 9 loads
Net MAin_c_1: 9 loads
Net Din_c_5: 8 loads
Net FS_11: 8 loads
Net MAin_c_0: 8 loads
Number of warnings: 0
Number of errors: 0
<A name="mrp_dwe"></A><B><U><big>Design Errors/Warnings</big></U></B>
No errors or warnings present.
<A name="mrp_ioa"></A><B><U><big>IO (PIO) Attributes</big></U></B>
+---------------------+-----------+-----------+------------+------------+
| IO Name | Direction | Levelmode | IO | FIXEDDELAY |
| | | IO_TYPE | Register | |
+---------------------+-----------+-----------+------------+------------+
| RD[7] | BIDIR | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RD[6] | BIDIR | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RD[5] | BIDIR | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RD[4] | BIDIR | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RD[3] | BIDIR | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RD[2] | BIDIR | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RD[1] | BIDIR | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RD[0] | BIDIR | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| Dout[7] | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| Dout[6] | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| Dout[5] | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| Dout[4] | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| Dout[3] | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| Dout[2] | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| Dout[1] | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| Dout[0] | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| LED | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RBA[1] | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RBA[0] | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RA[11] | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RA[10] | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RA[9] | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RA[8] | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RA[7] | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RA[6] | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RA[5] | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RA[4] | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RA[3] | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RA[2] | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RA[1] | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RA[0] | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| nRCS | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RCKE | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| nRWE | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| nRRAS | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| nRCAS | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RDQMH | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RDQML | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| nUFMCS | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| UFMCLK | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| UFMSDI | OUTPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| PHI2 | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| MAin[9] | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| MAin[8] | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| MAin[7] | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| MAin[6] | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| MAin[5] | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| MAin[4] | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| MAin[3] | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| MAin[2] | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| MAin[1] | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| MAin[0] | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| CROW[1] | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| CROW[0] | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| Din[7] | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| Din[6] | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| Din[5] | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| Din[4] | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| Din[3] | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| Din[2] | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| Din[1] | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| Din[0] | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| nCCAS | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| nCRAS | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| nFWE | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| RCLK | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
| UFMSDO | INPUT | LVTTL33 | | |
+---------------------+-----------+-----------+------------+------------+
<A name="mrp_rm"></A><B><U><big>Removed logic</big></U></B>
Block i2 undriven or does not drive anything - clipped.
Block GSR_INST undriven or does not drive anything - clipped.
Signal PHI2_N_114 was merged into signal PHI2_c
Signal nCRAS_N_9 was merged into signal nCRAS_c
Signal nCCAS_N_3 was merged into signal nCCAS_c
Signal n2302 was merged into signal nRowColSel_N_35
Signal nRWE_N_172 was merged into signal nRWE_N_173
Signal n2307 was merged into signal Ready
Signal RASr2_N_63 was merged into signal RASr2
Signal n1377 was merged into signal nRowColSel_N_34
Signal n2306 was merged into signal nFWE_c
Signal UFMSDO_N_74 was merged into signal UFMSDO_c
Signal GND_net undriven or does not drive anything - clipped.
Signal VCC_net undriven or does not drive anything - clipped.
Signal FS_577_add_4_14/CO0 undriven or does not drive anything - clipped.
Signal FS_577_add_4_16/CO0 undriven or does not drive anything - clipped.
Signal FS_577_add_4_12/CO0 undriven or does not drive anything - clipped.
Signal FS_577_add_4_2/CO0 undriven or does not drive anything - clipped.
Signal FS_577_add_4_4/CO0 undriven or does not drive anything - clipped.
Signal FS_577_add_4_6/CO0 undriven or does not drive anything - clipped.
Signal FS_577_add_4_18/CO1 undriven or does not drive anything - clipped.
Signal FS_577_add_4_18/CO0 undriven or does not drive anything - clipped.
Signal FS_577_add_4_8/CO0 undriven or does not drive anything - clipped.
Signal FS_577_add_4_10/CO0 undriven or does not drive anything - clipped.
Block i1962 was optimized away.
Block i1961 was optimized away.
Block i1963 was optimized away.
Block i1070_1_lut_rep_25 was optimized away.
Block nRWE_I_49_1_lut was optimized away.
Block i604_1_lut_rep_30 was optimized away.
Block RASr2_I_0_1_lut was optimized away.
Block i1069_1_lut was optimized away.
Block i1_1_lut_rep_29 was optimized away.
Block UFMSDO_I_0_1_lut was optimized away.
Block i1 was optimized away.
<A name="mrp_runtime"></A><B><U><big>Run Time and Memory Usage</big></U></B>
-------------------------
Total CPU Time: 0 secs
Total REAL Time: 0 secs
Peak Memory Usage: 29 MB
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights
reserved.
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<HEAD><TITLE>PAD Specification File</TITLE>
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<PRE><A name="Pad"></A>PAD Specification File
***************************
PART TYPE: LCMXO256C
Performance Grade: 3
PACKAGE: TQFP100
Package Status: Final Version 1.19
Mon Aug 16 21:32:33 2021
Pinout by Port Name:
+-----------+----------+--------------+------+----------------------------------+
| Port Name | Pin/Bank | Buffer Type | Site | Properties |
+-----------+----------+--------------+------+----------------------------------+
| CROW[0] | 32/1 | LVTTL33_IN | PB2C | SLEW:FAST |
| CROW[1] | 34/1 | LVTTL33_IN | PB2D | SLEW:FAST |
| Din[0] | 21/1 | LVTTL33_IN | PL8A | SLEW:FAST |
| Din[1] | 15/1 | LVTTL33_IN | PL6A | SLEW:FAST |
| Din[2] | 14/1 | LVTTL33_IN | PL5D | SLEW:FAST |
| Din[3] | 16/1 | LVTTL33_IN | PL6B | SLEW:FAST |
| Din[4] | 18/1 | LVTTL33_IN | PL7B | SLEW:FAST |
| Din[5] | 17/1 | LVTTL33_IN | PL7A | SLEW:FAST |
| Din[6] | 20/1 | LVTTL33_IN | PL7D | SLEW:FAST |
| Din[7] | 19/1 | LVTTL33_IN | PL7C | SLEW:FAST |
| Dout[0] | 1/1 | LVTTL33_OUT | PL2A | DRIVE:4mA SLEW:SLOW |
| Dout[1] | 7/1 | LVTTL33_OUT | PL4A | DRIVE:4mA SLEW:SLOW |
| Dout[2] | 8/1 | LVTTL33_OUT | PL4B | DRIVE:4mA SLEW:SLOW |
| Dout[3] | 6/1 | LVTTL33_OUT | PL3D | DRIVE:4mA SLEW:SLOW |
| Dout[4] | 4/1 | LVTTL33_OUT | PL3B | DRIVE:4mA SLEW:SLOW |
| Dout[5] | 5/1 | LVTTL33_OUT | PL3C | DRIVE:4mA SLEW:SLOW |
| Dout[6] | 2/1 | LVTTL33_OUT | PL2B | DRIVE:4mA SLEW:SLOW |
| Dout[7] | 3/1 | LVTTL33_OUT | PL3A | DRIVE:4mA SLEW:SLOW |
| LED | 57/0 | LVTTL33_OUT | PR7B | DRIVE:16mA SLEW:SLOW |
| MAin[0] | 23/1 | LVTTL33_IN | PL9A | SLEW:FAST |
| MAin[1] | 38/1 | LVTTL33_IN | PB3C | SLEW:FAST |
| MAin[2] | 37/1 | LVTTL33_IN | PB3B | SLEW:FAST |
| MAin[3] | 47/1 | LVTTL33_IN | PB5A | SLEW:FAST |
| MAin[4] | 46/1 | LVTTL33_IN | PB4D | SLEW:FAST |
| MAin[5] | 45/1 | LVTTL33_IN | PB4C | SLEW:FAST |
| MAin[6] | 49/1 | LVTTL33_IN | PB5C | SLEW:FAST |
| MAin[7] | 44/1 | LVTTL33_IN | PB4B | SLEW:FAST |
| MAin[8] | 50/1 | LVTTL33_IN | PB5D | SLEW:FAST |
| MAin[9] | 51/0 | LVTTL33_IN | PR9B | SLEW:FAST |
| PHI2 | 39/1 | LVTTL33_IN | PB3D | SLEW:FAST |
| RA[0] | 98/0 | LVTTL33_OUT | PT2C | DRIVE:4mA SLEW:SLOW |
| RA[10] | 87/0 | LVTTL33_OUT | PT3D | DRIVE:4mA SLEW:SLOW |
| RA[11] | 79/0 | LVTTL33_OUT | PT5A | DRIVE:4mA SLEW:SLOW |
| RA[1] | 89/0 | LVTTL33_OUT | PT3C | DRIVE:4mA SLEW:SLOW |
| RA[2] | 94/0 | LVTTL33_OUT | PT3A | DRIVE:4mA SLEW:SLOW |
| RA[3] | 97/0 | LVTTL33_OUT | PT2D | DRIVE:4mA SLEW:SLOW |
| RA[4] | 99/0 | LVTTL33_OUT | PT2B | DRIVE:4mA SLEW:SLOW |
| RA[5] | 95/0 | LVTTL33_OUT | PT2F | DRIVE:4mA SLEW:SLOW |
| RA[6] | 91/0 | LVTTL33_OUT | PT3B | DRIVE:4mA SLEW:SLOW |
| RA[7] | 100/0 | LVTTL33_OUT | PT2A | DRIVE:4mA SLEW:SLOW |
| RA[8] | 96/0 | LVTTL33_OUT | PT2E | DRIVE:4mA SLEW:SLOW |
| RA[9] | 85/0 | LVTTL33_OUT | PT4B | DRIVE:4mA SLEW:SLOW |
| RBA[0] | 63/0 | LVTTL33_OUT | PR5D | DRIVE:4mA SLEW:SLOW |
| RBA[1] | 83/0 | LVTTL33_OUT | PT4C | DRIVE:4mA SLEW:SLOW |
| RCKE | 82/0 | LVTTL33_OUT | PT4D | DRIVE:4mA SLEW:SLOW |
| RCLK | 86/0 | LVTTL33_IN | PT4A | SLEW:FAST |
| RDQMH | 76/0 | LVTTL33_OUT | PR2A | DRIVE:4mA SLEW:SLOW |
| RDQML | 61/0 | LVTTL33_OUT | PR6A | DRIVE:4mA SLEW:SLOW |
| RD[0] | 64/0 | LVTTL33_BIDI | PR5C | DRIVE:4mA SLEW:SLOW PULL:KEEPER |
| RD[1] | 65/0 | LVTTL33_BIDI | PR5B | DRIVE:4mA SLEW:SLOW PULL:KEEPER |
| RD[2] | 66/0 | LVTTL33_BIDI | PR5A | DRIVE:4mA SLEW:SLOW PULL:KEEPER |
| RD[3] | 67/0 | LVTTL33_BIDI | PR4B | DRIVE:4mA SLEW:SLOW PULL:KEEPER |
| RD[4] | 68/0 | LVTTL33_BIDI | PR4A | DRIVE:4mA SLEW:SLOW PULL:KEEPER |
| RD[5] | 69/0 | LVTTL33_BIDI | PR3D | DRIVE:4mA SLEW:SLOW PULL:KEEPER |
| RD[6] | 70/0 | LVTTL33_BIDI | PR3C | DRIVE:4mA SLEW:SLOW PULL:KEEPER |
| RD[7] | 71/0 | LVTTL33_BIDI | PR3B | DRIVE:4mA SLEW:SLOW PULL:KEEPER |
| UFMCLK | 58/0 | LVTTL33_OUT | PR7A | DRIVE:4mA SLEW:SLOW |
| UFMSDI | 56/0 | LVTTL33_OUT | PR7C | DRIVE:4mA SLEW:SLOW |
| UFMSDO | 55/0 | LVTTL33_IN | PR7D | SLEW:FAST PULL:KEEPER |
| nCCAS | 27/1 | LVTTL33_IN | PL9B | SLEW:FAST |
| nCRAS | 43/1 | LVTTL33_IN | PB4A | SLEW:FAST |
| nFWE | 22/1 | LVTTL33_IN | PL8B | SLEW:FAST |
| nRCAS | 78/0 | LVTTL33_OUT | PT5B | DRIVE:4mA SLEW:SLOW |
| nRCS | 77/0 | LVTTL33_OUT | PT5C | DRIVE:4mA SLEW:SLOW |
| nRRAS | 73/0 | LVTTL33_OUT | PR2B | DRIVE:4mA SLEW:SLOW |
| nRWE | 72/0 | LVTTL33_OUT | PR3A | DRIVE:4mA SLEW:SLOW |
| nUFMCS | 53/0 | LVTTL33_OUT | PR8B | DRIVE:4mA SLEW:SLOW |
+-----------+----------+--------------+------+----------------------------------+
Vccio by Bank:
+------+-------+
| Bank | Vccio |
+------+-------+
| 0 | 3.3V |
| 1 | 3.3V |
+------+-------+
<A name="pad_vref"></A><B><U><big>Vref by Bank:</big></U></B>
+------+-----+-----------------+---------+
| Vref | Pin | Bank # / Vref # | Load(s) |
+------+-----+-----------------+---------+
+------+-----+-----------------+---------+
<A name="pad_pin"></A><B><U><big>Pinout by Pin Number:</big></U></B>
+----------+---------------------+------------+--------------+------+---------------+
| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function |
+----------+---------------------+------------+--------------+------+---------------+
| 1/1 | Dout[0] | LOCATED | LVTTL33_OUT | PL2A | |
| 2/1 | Dout[6] | LOCATED | LVTTL33_OUT | PL2B | |
| 3/1 | Dout[7] | LOCATED | LVTTL33_OUT | PL3A | |
| 4/1 | Dout[4] | LOCATED | LVTTL33_OUT | PL3B | |
| 5/1 | Dout[5] | LOCATED | LVTTL33_OUT | PL3C | |
| 6/1 | Dout[3] | LOCATED | LVTTL33_OUT | PL3D | |
| 7/1 | Dout[1] | LOCATED | LVTTL33_OUT | PL4A | |
| 8/1 | Dout[2] | LOCATED | LVTTL33_OUT | PL4B | |
| 9/1 | unused, PULL:UP | | | PL5A | |
| 11/1 | unused, PULL:UP | | | PL5B | |
| 13/1 | unused, PULL:UP | | | PL5C | |
| 14/1 | Din[2] | LOCATED | LVTTL33_IN | PL5D | GSR_PADN |
| 15/1 | Din[1] | LOCATED | LVTTL33_IN | PL6A | |
| 16/1 | Din[3] | LOCATED | LVTTL33_IN | PL6B | TSALLPAD |
| 17/1 | Din[5] | LOCATED | LVTTL33_IN | PL7A | |
| 18/1 | Din[4] | LOCATED | LVTTL33_IN | PL7B | |
| 19/1 | Din[7] | LOCATED | LVTTL33_IN | PL7C | |
| 20/1 | Din[6] | LOCATED | LVTTL33_IN | PL7D | |
| 21/1 | Din[0] | LOCATED | LVTTL33_IN | PL8A | |
| 22/1 | nFWE | LOCATED | LVTTL33_IN | PL8B | |
| 23/1 | MAin[0] | LOCATED | LVTTL33_IN | PL9A | |
| 27/1 | nCCAS | LOCATED | LVTTL33_IN | PL9B | |
| 29/1 | unused, PULL:UP | | | PB2A | |
| 30/1 | unused, PULL:UP | | | PB2B | |
| 32/1 | CROW[0] | LOCATED | LVTTL33_IN | PB2C | |
| 34/1 | CROW[1] | LOCATED | LVTTL33_IN | PB2D | |
| 36/1 | unused, PULL:UP | | | PB3A | PCLKT1_1 |
| 37/1 | MAin[2] | LOCATED | LVTTL33_IN | PB3B | |
| 38/1 | MAin[1] | LOCATED | LVTTL33_IN | PB3C | PCLKT1_0 |
| 39/1 | PHI2 | LOCATED | LVTTL33_IN | PB3D | |
| 43/1 | nCRAS | LOCATED | LVTTL33_IN | PB4A | |
| 44/1 | MAin[7] | LOCATED | LVTTL33_IN | PB4B | |
| 45/1 | MAin[5] | LOCATED | LVTTL33_IN | PB4C | |
| 46/1 | MAin[4] | LOCATED | LVTTL33_IN | PB4D | |
| 47/1 | MAin[3] | LOCATED | LVTTL33_IN | PB5A | |
| 49/1 | MAin[6] | LOCATED | LVTTL33_IN | PB5C | |
| 50/1 | MAin[8] | LOCATED | LVTTL33_IN | PB5D | |
| 51/0 | MAin[9] | LOCATED | LVTTL33_IN | PR9B | |
| 52/0 | unused, PULL:UP | | | PR9A | |
| 53/0 | nUFMCS | LOCATED | LVTTL33_OUT | PR8B | |
| 54/0 | unused, PULL:UP | | | PR8A | |
| 55/0 | UFMSDO | LOCATED | LVTTL33_IN | PR7D | |
| 56/0 | UFMSDI | LOCATED | LVTTL33_OUT | PR7C | |
| 57/0 | LED | LOCATED | LVTTL33_OUT | PR7B | |
| 58/0 | UFMCLK | LOCATED | LVTTL33_OUT | PR7A | |
| 59/0 | unused, PULL:UP | | | PR6B | |
| 61/0 | RDQML | LOCATED | LVTTL33_OUT | PR6A | |
| 63/0 | RBA[0] | LOCATED | LVTTL33_OUT | PR5D | |
| 64/0 | RD[0] | LOCATED | LVTTL33_BIDI | PR5C | |
| 65/0 | RD[1] | LOCATED | LVTTL33_BIDI | PR5B | |
| 66/0 | RD[2] | LOCATED | LVTTL33_BIDI | PR5A | |
| 67/0 | RD[3] | LOCATED | LVTTL33_BIDI | PR4B | |
| 68/0 | RD[4] | LOCATED | LVTTL33_BIDI | PR4A | |
| 69/0 | RD[5] | LOCATED | LVTTL33_BIDI | PR3D | |
| 70/0 | RD[6] | LOCATED | LVTTL33_BIDI | PR3C | |
| 71/0 | RD[7] | LOCATED | LVTTL33_BIDI | PR3B | |
| 72/0 | nRWE | LOCATED | LVTTL33_OUT | PR3A | |
| 73/0 | nRRAS | LOCATED | LVTTL33_OUT | PR2B | |
| 76/0 | RDQMH | LOCATED | LVTTL33_OUT | PR2A | |
| 77/0 | nRCS | LOCATED | LVTTL33_OUT | PT5C | |
| 78/0 | nRCAS | LOCATED | LVTTL33_OUT | PT5B | |
| 79/0 | RA[11] | LOCATED | LVTTL33_OUT | PT5A | |
| 80/0 | unused, PULL:UP | | | PT4F | |
| 81/0 | unused, PULL:UP | | | PT4E | |
| 82/0 | RCKE | LOCATED | LVTTL33_OUT | PT4D | |
| 83/0 | RBA[1] | LOCATED | LVTTL33_OUT | PT4C | |
| 85/0 | RA[9] | LOCATED | LVTTL33_OUT | PT4B | PCLKT0_1 |
| 86/0 | RCLK | LOCATED | LVTTL33_IN | PT4A | PCLKT0_0 |
| 87/0 | RA[10] | LOCATED | LVTTL33_OUT | PT3D | |
| 89/0 | RA[1] | LOCATED | LVTTL33_OUT | PT3C | |
| 91/0 | RA[6] | LOCATED | LVTTL33_OUT | PT3B | |
| 94/0 | RA[2] | LOCATED | LVTTL33_OUT | PT3A | |
| 95/0 | RA[5] | LOCATED | LVTTL33_OUT | PT2F | |
| 96/0 | RA[8] | LOCATED | LVTTL33_OUT | PT2E | |
| 97/0 | RA[3] | LOCATED | LVTTL33_OUT | PT2D | |
| 98/0 | RA[0] | LOCATED | LVTTL33_OUT | PT2C | |
| 99/0 | RA[4] | LOCATED | LVTTL33_OUT | PT2B | |
| 100/0 | RA[7] | LOCATED | LVTTL33_OUT | PT2A | |
| PB5B/0 | unused, PULL:UP | | | PB5B | |
| PT5D/0 | unused, PULL:UP | | | PT5D | |
| TCK/1 | | | | TCK | TCK |
| TDI/1 | | | | TDI | TDI |
| TDO/1 | | | | TDO | TDO |
| TMS/1 | | | | TMS | TMS |
+----------+---------------------+------------+--------------+------+---------------+
List of All Pins' Locate Preferences Based on Final Placement After PAR
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste):
LOCATE COMP "CROW[0]" SITE "32";
LOCATE COMP "CROW[1]" SITE "34";
LOCATE COMP "Din[0]" SITE "21";
LOCATE COMP "Din[1]" SITE "15";
LOCATE COMP "Din[2]" SITE "14";
LOCATE COMP "Din[3]" SITE "16";
LOCATE COMP "Din[4]" SITE "18";
LOCATE COMP "Din[5]" SITE "17";
LOCATE COMP "Din[6]" SITE "20";
LOCATE COMP "Din[7]" SITE "19";
LOCATE COMP "Dout[0]" SITE "1";
LOCATE COMP "Dout[1]" SITE "7";
LOCATE COMP "Dout[2]" SITE "8";
LOCATE COMP "Dout[3]" SITE "6";
LOCATE COMP "Dout[4]" SITE "4";
LOCATE COMP "Dout[5]" SITE "5";
LOCATE COMP "Dout[6]" SITE "2";
LOCATE COMP "Dout[7]" SITE "3";
LOCATE COMP "LED" SITE "57";
LOCATE COMP "MAin[0]" SITE "23";
LOCATE COMP "MAin[1]" SITE "38";
LOCATE COMP "MAin[2]" SITE "37";
LOCATE COMP "MAin[3]" SITE "47";
LOCATE COMP "MAin[4]" SITE "46";
LOCATE COMP "MAin[5]" SITE "45";
LOCATE COMP "MAin[6]" SITE "49";
LOCATE COMP "MAin[7]" SITE "44";
LOCATE COMP "MAin[8]" SITE "50";
LOCATE COMP "MAin[9]" SITE "51";
LOCATE COMP "PHI2" SITE "39";
LOCATE COMP "RA[0]" SITE "98";
LOCATE COMP "RA[10]" SITE "87";
LOCATE COMP "RA[11]" SITE "79";
LOCATE COMP "RA[1]" SITE "89";
LOCATE COMP "RA[2]" SITE "94";
LOCATE COMP "RA[3]" SITE "97";
LOCATE COMP "RA[4]" SITE "99";
LOCATE COMP "RA[5]" SITE "95";
LOCATE COMP "RA[6]" SITE "91";
LOCATE COMP "RA[7]" SITE "100";
LOCATE COMP "RA[8]" SITE "96";
LOCATE COMP "RA[9]" SITE "85";
LOCATE COMP "RBA[0]" SITE "63";
LOCATE COMP "RBA[1]" SITE "83";
LOCATE COMP "RCKE" SITE "82";
LOCATE COMP "RCLK" SITE "86";
LOCATE COMP "RDQMH" SITE "76";
LOCATE COMP "RDQML" SITE "61";
LOCATE COMP "RD[0]" SITE "64";
LOCATE COMP "RD[1]" SITE "65";
LOCATE COMP "RD[2]" SITE "66";
LOCATE COMP "RD[3]" SITE "67";
LOCATE COMP "RD[4]" SITE "68";
LOCATE COMP "RD[5]" SITE "69";
LOCATE COMP "RD[6]" SITE "70";
LOCATE COMP "RD[7]" SITE "71";
LOCATE COMP "UFMCLK" SITE "58";
LOCATE COMP "UFMSDI" SITE "56";
LOCATE COMP "UFMSDO" SITE "55";
LOCATE COMP "nCCAS" SITE "27";
LOCATE COMP "nCRAS" SITE "43";
LOCATE COMP "nFWE" SITE "22";
LOCATE COMP "nRCAS" SITE "78";
LOCATE COMP "nRCS" SITE "77";
LOCATE COMP "nRRAS" SITE "73";
LOCATE COMP "nRWE" SITE "72";
LOCATE COMP "nUFMCS" SITE "53";
PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Mon Aug 16 21:32:33 2021
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<PRE><A name="Par"></A>PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&amp;T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Mon Aug 16 21:32:27 2021
C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO256C_impl1.p2t
RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir
RAM2GS_LCMXO256C_impl1.prf -gui -msgset
C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml
Preference file: RAM2GS_LCMXO256C_impl1.prf.
<A name="par_cts"></A><B><U><big>Cost Table Summary</big></U></B>
Level/ Number Worst Timing Worst Timing Run NCD
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
---------- -------- ----- ------ ----------- ----------- ---- ------
5_1 * 0 2.023 0 0.339 0 07 Completed
* : Design saved.
Total (real) run time for 1-seed: 7 secs
par done!
Note: user must run &apos;Trace&apos; for timing closure signoff.
Lattice Place and Route Report for Design &quot;RAM2GS_LCMXO256C_impl1_map.ncd&quot;
Mon Aug 16 21:32:27 2021
<A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir/5_1.ncd RAM2GS_LCMXO256C_impl1.prf
Preference file: RAM2GS_LCMXO256C_impl1.prf.
Placement level-cost: 5-1.
Routing Iterations: 6
Loading design for application par from file RAM2GS_LCMXO256C_impl1_map.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO256C
Package: TQFP100
Performance: 3
Loading device for application par from file &apos;mj5g10x6.nph&apos; in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.19.
Performance Hardware Data Status: Version 1.124.
License checked out.
Ignore Preference Error(s): True
<A name="par_dus"></A><B><U><big>Device utilization summary:</big></U></B>
PIO (prelim) 67/79 84% used
67/78 85% bonded
SLICE 65/128 50% used
Number of Signals: 252
Number of Connections: 618
Pin Constraint Summary:
67 out of 67 pins locked (100% locked).
The following 4 signals are selected to use the primary clock routing resources:
RCLK_c (driver: RCLK, clk load #: 39)
PHI2_c (driver: PHI2, clk load #: 13)
nCCAS_c (driver: nCCAS, clk load #: 4)
nCRAS_c (driver: nCRAS, clk load #: 7)
No signal is selected as secondary clock.
No signal is selected as Global Set/Reset.
Starting Placer Phase 0.
........
Finished Placer Phase 0. REAL time: 0 secs
Starting Placer Phase 1.
...............
Placer score = 586066.
Finished Placer Phase 1. REAL time: 6 secs
Starting Placer Phase 2.
.
Placer score = 584668
Finished Placer Phase 2. REAL time: 6 secs
<A name="par_clk"></A><B><U><big>Clock Report</big></U></B>
Global Clock Resources:
CLK_PIN : 1 out of 4 (25%)
General PIO: 3 out of 80 (3%)
Global Clocks:
PRIMARY &quot;RCLK_c&quot; from comp &quot;RCLK&quot; on CLK_PIN site &quot;86 (PT4A)&quot;, clk load = 39
PRIMARY &quot;PHI2_c&quot; from comp &quot;PHI2&quot; on PIO site &quot;39 (PB3D)&quot;, clk load = 13
PRIMARY &quot;nCCAS_c&quot; from comp &quot;nCCAS&quot; on PIO site &quot;27 (PL9B)&quot;, clk load = 4
PRIMARY &quot;nCRAS_c&quot; from comp &quot;nCRAS&quot; on PIO site &quot;43 (PB4A)&quot;, clk load = 7
PRIMARY : 4 out of 4 (100%)
SECONDARY: 0 out of 4 (0%)
I/O Usage Summary (final):
67 out of 79 (84.8%) PIO sites used.
67 out of 78 (85.9%) bonded PIO sites used.
Number of PIO comps: 67; differential: 0.
Number of Vref pins used: 0.
I/O Bank Usage Summary:
+----------+----------------+------------+------------+------------+
| I/O Bank | Usage | Bank Vccio | Bank Vref1 | Bank Vref2 |
+----------+----------------+------------+------------+------------+
| 0 | 36 / 41 ( 87%) | 3.3V | - | - |
| 1 | 31 / 37 ( 83%) | 3.3V | - | - |
+----------+----------------+------------+------------+------------+
Total placer CPU time: 6 secs
Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd.
0 connections routed; 618 unrouted.
Starting router resource preassignment
WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
WARNING - par: The driver of primary clock net nCCAS_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
Completed router resource preassignment. Real time: 6 secs
Start NBR router at 21:32:33 08/16/21
*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
in the earlier iterations. In each iteration, it tries to
solve the conflicts while keeping the critical connections
routed as short as possible. The routing process is said to
be completed when no conflicts exist and all connections
are routed.
Note: NBR uses a different method to calculate timing slacks. The
worst slack and total negative slack may not be the same as
that in TRCE report. You should always run TRCE to verify
your design.
*****************************************************************
Start NBR special constraint process at 21:32:33 08/16/21
Start NBR section for initial routing at 21:32:33 08/16/21
Level 1, iteration 1
0(0.00%) conflict; 535(86.57%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 2.084ns/0.000ns; real time: 6 secs
Level 2, iteration 1
0(0.00%) conflict; 535(86.57%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 2.084ns/0.000ns; real time: 6 secs
Level 3, iteration 1
0(0.00%) conflict; 509(82.36%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 2.038ns/0.000ns; real time: 6 secs
Level 4, iteration 1
23(0.19%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 2.023ns/0.000ns; real time: 6 secs
Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area at 75% usage is 0 (0.00%)
Start NBR section for normal routing at 21:32:33 08/16/21
Level 1, iteration 1
0(0.00%) conflict; 24(3.88%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 2.023ns/0.000ns; real time: 6 secs
Level 4, iteration 1
8(0.07%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 2.023ns/0.000ns; real time: 6 secs
Level 4, iteration 2
4(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 2.023ns/0.000ns; real time: 6 secs
Level 4, iteration 3
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 2.023ns/0.000ns; real time: 6 secs
Start NBR section for setup/hold timing optimization with effort level 3 at 21:32:33 08/16/21
Start NBR section for re-routing at 21:32:33 08/16/21
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 2.023ns/0.000ns; real time: 6 secs
Start NBR section for post-routing at 21:32:33 08/16/21
End NBR router with 0 unrouted connection
NBR Summary
-----------
Number of unrouted connections : 0 (0.00%)
Number of connections with timing violations : 0 (0.00%)
Estimated worst slack&lt;setup&gt; : 2.023ns
Timing score&lt;setup&gt; : 0
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
Total CPU time 6 secs
Total REAL time: 7 secs
Completely routed.
End of route. 618 routed (100.00%); 0 unrouted.
Hold time timing score: 0, hold timing errors: 0
Timing score: 0
Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd.
All signals are completely routed.
PAR_SUMMARY::Run status = Completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst slack&lt;setup/&lt;ns&gt;&gt; = 2.023
PAR_SUMMARY::Timing score&lt;setup/&lt;ns&gt;&gt; = 0.000
PAR_SUMMARY::Worst slack&lt;hold /&lt;ns&gt;&gt; = 0.339
PAR_SUMMARY::Timing score&lt;hold /&lt;ns&gt;&gt; = 0.000
PAR_SUMMARY::Number of errors = 0
Total CPU time to completion: 6 secs
Total REAL time to completion: 7 secs
par done!
Note: user must run &apos;Trace&apos; for timing closure signoff.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&amp;T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
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<PRE><TABLE border=1 width=100% cellspacing=0 cellpadding=2><small>
<TR>
<TD align='center' BGCOLOR='#000099' COLSPAN='4'><SPAN style="COLOR: #FFFFFF"><B>RAM2GS_LCMXO256C project summary</B></SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Module Name:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">RAM2GS_LCMXO256C</SPAN></TD>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Synthesis:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">Lattice LSE</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Name:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">impl1</SPAN></TD>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Strategy Name:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">Strategy1</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Last Process:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">JEDEC File</SPAN></TD>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">State:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">Passed</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Target Device:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">LCMXO256C-3T100C</SPAN></TD>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Device Family:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">MachXO</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Device Type:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">LCMXO256C</SPAN></TD>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Package Type:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">TQFP100</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Performance grade:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">3</SPAN></TD>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Operating conditions:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">COM</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Logic preference file:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">RAM2GS_LCMXO256C.lpf</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Physical Preference file:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">impl1/RAM2GS_LCMXO256C_impl1.prf</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Product Version:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">3.12.0.240.2</SPAN></TD>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Patch Version:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000"></SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Updated:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2021/08/16 21:36:29</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Location:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/impl1</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Project File:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/RAM2GS_LCMXO256C.ldf</SPAN></TD>
</TR>
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Results of NGD DRC are available in RAM2GS_drc.log.
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
Running DRC...
DRC complete with no errors or warnings
Design Results:
304 blocks expanded
completed the first expansion
All blocks are expanded and NGD expansion is successful.
Writing NGD file RAM2GS_LCMXO256C_impl1.ngd.

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--------------------------------------------------------------------------------
Lattice Synthesis Timing Report, Version
Mon Aug 16 21:32:26 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Design: RAM2GS
Constraint file:
Report level: verbose report, limited to 3 items per constraint
--------------------------------------------------------------------------------
================================================================================
Constraint: create_clock -period 5.000000 -name clk3 [get_nets nCCAS_c]
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCRAS_c]
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Constraint: create_clock -period 5.000000 -name clk1 [get_nets PHI2_c]
122 items scored, 121 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path violates requirements by 10.378ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1S3AX CK Bank_i5 (from PHI2_c +)
Destination: FD1P3AX SP CmdUFMCS_385 (to PHI2_c -)
Delay: 12.614ns (23.4% logic, 76.6% route), 7 logic levels.
Constraint Details:
12.614ns data_path Bank_i5 to CmdUFMCS_385 violates
2.500ns delay constraint less
0.264ns LCE_S requirement (totaling 2.236ns) by 10.378ns
Path Details: Bank_i5 to CmdUFMCS_385
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.613 CK to Q Bank_i5 (from PHI2_c)
Route 1 e 1.220 Bank[5]
LUT4 --- 0.390 B to Z i1856_4_lut
Route 1 e 1.220 n2166
LUT4 --- 0.390 B to Z i12_4_lut
Route 1 e 1.220 n26
LUT4 --- 0.390 B to Z i13_4_lut
Route 4 e 1.552 n1285
LUT4 --- 0.390 B to Z i1830_2_lut_rep_13
Route 3 e 1.483 n2290
LUT4 --- 0.390 D to Z i3_4_lut
Route 3 e 1.483 XOR8MEG_N_112
LUT4 --- 0.390 A to Z i2_3_lut_4_lut
Route 3 e 1.483 PHI2_N_114_enable_7
--------
12.614 (23.4% logic, 76.6% route), 7 logic levels.
Error: The following path violates requirements by 10.378ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1S3AX CK Bank_i5 (from PHI2_c +)
Destination: FD1P3AX SP CmdUFMSDI_387 (to PHI2_c -)
Delay: 12.614ns (23.4% logic, 76.6% route), 7 logic levels.
Constraint Details:
12.614ns data_path Bank_i5 to CmdUFMSDI_387 violates
2.500ns delay constraint less
0.264ns LCE_S requirement (totaling 2.236ns) by 10.378ns
Path Details: Bank_i5 to CmdUFMSDI_387
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.613 CK to Q Bank_i5 (from PHI2_c)
Route 1 e 1.220 Bank[5]
LUT4 --- 0.390 B to Z i1856_4_lut
Route 1 e 1.220 n2166
LUT4 --- 0.390 B to Z i12_4_lut
Route 1 e 1.220 n26
LUT4 --- 0.390 B to Z i13_4_lut
Route 4 e 1.552 n1285
LUT4 --- 0.390 B to Z i1830_2_lut_rep_13
Route 3 e 1.483 n2290
LUT4 --- 0.390 D to Z i3_4_lut
Route 3 e 1.483 XOR8MEG_N_112
LUT4 --- 0.390 A to Z i2_3_lut_4_lut
Route 3 e 1.483 PHI2_N_114_enable_7
--------
12.614 (23.4% logic, 76.6% route), 7 logic levels.
Error: The following path violates requirements by 10.378ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1S3AX CK Bank_i5 (from PHI2_c +)
Destination: FD1P3AX SP CmdUFMCLK_386 (to PHI2_c -)
Delay: 12.614ns (23.4% logic, 76.6% route), 7 logic levels.
Constraint Details:
12.614ns data_path Bank_i5 to CmdUFMCLK_386 violates
2.500ns delay constraint less
0.264ns LCE_S requirement (totaling 2.236ns) by 10.378ns
Path Details: Bank_i5 to CmdUFMCLK_386
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.613 CK to Q Bank_i5 (from PHI2_c)
Route 1 e 1.220 Bank[5]
LUT4 --- 0.390 B to Z i1856_4_lut
Route 1 e 1.220 n2166
LUT4 --- 0.390 B to Z i12_4_lut
Route 1 e 1.220 n26
LUT4 --- 0.390 B to Z i13_4_lut
Route 4 e 1.552 n1285
LUT4 --- 0.390 B to Z i1830_2_lut_rep_13
Route 3 e 1.483 n2290
LUT4 --- 0.390 D to Z i3_4_lut
Route 3 e 1.483 XOR8MEG_N_112
LUT4 --- 0.390 A to Z i2_3_lut_4_lut
Route 3 e 1.483 PHI2_N_114_enable_7
--------
12.614 (23.4% logic, 76.6% route), 7 logic levels.
Warning: 12.878 ns is the maximum delay for this constraint.
================================================================================
Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c]
369 items scored, 244 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path violates requirements by 6.291ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1S3AX CK FS_577__i12 (from RCLK_c +)
Destination: FD1P3AX SP LEDEN_392 (to RCLK_c +)
Delay: 11.027ns (23.2% logic, 76.8% route), 6 logic levels.
Constraint Details:
11.027ns data_path FS_577__i12 to LEDEN_392 violates
5.000ns delay constraint less
0.264ns LCE_S requirement (totaling 4.736ns) by 6.291ns
Path Details: FS_577__i12 to LEDEN_392
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.613 CK to Q FS_577__i12 (from RCLK_c)
Route 3 e 1.603 FS[12]
LUT4 --- 0.390 C to Z i4_4_lut
Route 3 e 1.483 n10
LUT4 --- 0.390 B to Z i5_3_lut_rep_23
Route 4 e 1.552 n2300
LUT4 --- 0.390 B to Z i4_3_lut_4_lut
Route 1 e 1.220 n11
LUT4 --- 0.390 C to Z i2_4_lut_adj_4
Route 2 e 1.386 n2119
LUT4 --- 0.390 C to Z i2_3_lut_3_lut
Route 1 e 1.220 RCLK_c_enable_25
--------
11.027 (23.2% logic, 76.8% route), 6 logic levels.
Error: The following path violates requirements by 6.291ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1S3AX CK FS_577__i12 (from RCLK_c +)
Destination: FD1P3AX SP n8MEGEN_391 (to RCLK_c +)
Delay: 11.027ns (23.2% logic, 76.8% route), 6 logic levels.
Constraint Details:
11.027ns data_path FS_577__i12 to n8MEGEN_391 violates
5.000ns delay constraint less
0.264ns LCE_S requirement (totaling 4.736ns) by 6.291ns
Path Details: FS_577__i12 to n8MEGEN_391
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.613 CK to Q FS_577__i12 (from RCLK_c)
Route 3 e 1.603 FS[12]
LUT4 --- 0.390 C to Z i4_4_lut
Route 3 e 1.483 n10
LUT4 --- 0.390 B to Z i5_3_lut_rep_23
Route 4 e 1.552 n2300
LUT4 --- 0.390 B to Z i4_3_lut_4_lut
Route 1 e 1.220 n11
LUT4 --- 0.390 C to Z i2_4_lut_adj_4
Route 2 e 1.386 n2119
LUT4 --- 0.390 D to Z i1248_4_lut
Route 1 e 1.220 RCLK_c_enable_7
--------
11.027 (23.2% logic, 76.8% route), 6 logic levels.
Error: The following path violates requirements by 6.291ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1S3AX CK FS_577__i13 (from RCLK_c +)
Destination: FD1P3AX SP LEDEN_392 (to RCLK_c +)
Delay: 11.027ns (23.2% logic, 76.8% route), 6 logic levels.
Constraint Details:
11.027ns data_path FS_577__i13 to LEDEN_392 violates
5.000ns delay constraint less
0.264ns LCE_S requirement (totaling 4.736ns) by 6.291ns
Path Details: FS_577__i13 to LEDEN_392
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.613 CK to Q FS_577__i13 (from RCLK_c)
Route 3 e 1.603 FS[13]
LUT4 --- 0.390 B to Z i4_4_lut
Route 3 e 1.483 n10
LUT4 --- 0.390 B to Z i5_3_lut_rep_23
Route 4 e 1.552 n2300
LUT4 --- 0.390 B to Z i4_3_lut_4_lut
Route 1 e 1.220 n11
LUT4 --- 0.390 C to Z i2_4_lut_adj_4
Route 2 e 1.386 n2119
LUT4 --- 0.390 C to Z i2_3_lut_3_lut
Route 1 e 1.220 RCLK_c_enable_25
--------
11.027 (23.2% logic, 76.8% route), 6 logic levels.
Warning: 11.291 ns is the maximum delay for this constraint.
Timing Report Summary
--------------
--------------------------------------------------------------------------------
Constraint | Constraint| Actual|Levels
--------------------------------------------------------------------------------
| | |
create_clock -period 5.000000 -name | | |
clk3 [get_nets nCCAS_c] | -| -| 0
| | |
create_clock -period 5.000000 -name | | |
clk2 [get_nets nCRAS_c] | -| -| 0
| | |
create_clock -period 5.000000 -name | | |
clk1 [get_nets PHI2_c] | 5.000 ns| 25.756 ns| 7 *
| | |
create_clock -period 5.000000 -name | | |
clk0 [get_nets RCLK_c] | 5.000 ns| 11.291 ns| 6 *
| | |
--------------------------------------------------------------------------------
2 constraints not met.
--------------------------------------------------------------------------------
Critical Nets | Loads| Errors| % of total
--------------------------------------------------------------------------------
n1285 | 4| 112| 30.68%
| | |
n26 | 1| 70| 19.18%
| | |
RCLK_c_enable_23 | 16| 64| 17.53%
| | |
n2290 | 3| 64| 17.53%
| | |
XOR8MEG_N_112 | 3| 54| 14.79%
| | |
n2119 | 2| 48| 13.15%
| | |
n2166 | 1| 42| 11.51%
| | |
--------------------------------------------------------------------------------
Timing summary:
---------------
Timing errors: 365 Score: 2309745
Constraints cover 495 paths, 177 nets, and 464 connections (66.5% coverage)
Peak memory: 52502528 bytes, TRCE: 1482752 bytes, DLYMAN: 163840 bytes
CPU_TIME_REPORT: 0 secs

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<PRE><A name="Map_Twr"></A><B><U><big>Lattice Synthesis Timing Report</big></U></B>
--------------------------------------------------------------------------------
Lattice Synthesis Timing Report, Version
Mon Aug 16 21:32:26 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
<A name="mtw1_ri"></A><B><U><big>Report Information</big></U></B>
------------------
Design: RAM2GS
Constraint file:
Report level: verbose report, limited to 3 items per constraint
--------------------------------------------------------------------------------
================================================================================
Constraint: create_clock -period 5.000000 -name clk3 [get_nets nCCAS_c]
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCRAS_c]
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Constraint: create_clock -period 5.000000 -name clk1 [get_nets PHI2_c]
122 items scored, 121 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path violates requirements by 10.378ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1S3AX CK Bank_i5 (from PHI2_c +)
Destination: FD1P3AX SP CmdUFMCS_385 (to PHI2_c -)
Delay: 12.614ns (23.4% logic, 76.6% route), 7 logic levels.
Constraint Details:
12.614ns data_path Bank_i5 to CmdUFMCS_385 violates
2.500ns delay constraint less
0.264ns LCE_S requirement (totaling 2.236ns) by 10.378ns
Path Details: Bank_i5 to CmdUFMCS_385
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.613 CK to Q Bank_i5 (from PHI2_c)
Route 1 e 1.220 Bank[5]
LUT4 --- 0.390 B to Z i1856_4_lut
Route 1 e 1.220 n2166
LUT4 --- 0.390 B to Z i12_4_lut
Route 1 e 1.220 n26
LUT4 --- 0.390 B to Z i13_4_lut
Route 4 e 1.552 n1285
LUT4 --- 0.390 B to Z i1830_2_lut_rep_13
Route 3 e 1.483 n2290
LUT4 --- 0.390 D to Z i3_4_lut
Route 3 e 1.483 XOR8MEG_N_112
LUT4 --- 0.390 A to Z i2_3_lut_4_lut
Route 3 e 1.483 PHI2_N_114_enable_7
--------
12.614 (23.4% logic, 76.6% route), 7 logic levels.
Error: The following path violates requirements by 10.378ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1S3AX CK Bank_i5 (from PHI2_c +)
Destination: FD1P3AX SP CmdUFMSDI_387 (to PHI2_c -)
Delay: 12.614ns (23.4% logic, 76.6% route), 7 logic levels.
Constraint Details:
12.614ns data_path Bank_i5 to CmdUFMSDI_387 violates
2.500ns delay constraint less
0.264ns LCE_S requirement (totaling 2.236ns) by 10.378ns
Path Details: Bank_i5 to CmdUFMSDI_387
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.613 CK to Q Bank_i5 (from PHI2_c)
Route 1 e 1.220 Bank[5]
LUT4 --- 0.390 B to Z i1856_4_lut
Route 1 e 1.220 n2166
LUT4 --- 0.390 B to Z i12_4_lut
Route 1 e 1.220 n26
LUT4 --- 0.390 B to Z i13_4_lut
Route 4 e 1.552 n1285
LUT4 --- 0.390 B to Z i1830_2_lut_rep_13
Route 3 e 1.483 n2290
LUT4 --- 0.390 D to Z i3_4_lut
Route 3 e 1.483 XOR8MEG_N_112
LUT4 --- 0.390 A to Z i2_3_lut_4_lut
Route 3 e 1.483 PHI2_N_114_enable_7
--------
12.614 (23.4% logic, 76.6% route), 7 logic levels.
Error: The following path violates requirements by 10.378ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1S3AX CK Bank_i5 (from PHI2_c +)
Destination: FD1P3AX SP CmdUFMCLK_386 (to PHI2_c -)
Delay: 12.614ns (23.4% logic, 76.6% route), 7 logic levels.
Constraint Details:
12.614ns data_path Bank_i5 to CmdUFMCLK_386 violates
2.500ns delay constraint less
0.264ns LCE_S requirement (totaling 2.236ns) by 10.378ns
Path Details: Bank_i5 to CmdUFMCLK_386
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.613 CK to Q Bank_i5 (from PHI2_c)
Route 1 e 1.220 Bank[5]
LUT4 --- 0.390 B to Z i1856_4_lut
Route 1 e 1.220 n2166
LUT4 --- 0.390 B to Z i12_4_lut
Route 1 e 1.220 n26
LUT4 --- 0.390 B to Z i13_4_lut
Route 4 e 1.552 n1285
LUT4 --- 0.390 B to Z i1830_2_lut_rep_13
Route 3 e 1.483 n2290
LUT4 --- 0.390 D to Z i3_4_lut
Route 3 e 1.483 XOR8MEG_N_112
LUT4 --- 0.390 A to Z i2_3_lut_4_lut
Route 3 e 1.483 PHI2_N_114_enable_7
--------
12.614 (23.4% logic, 76.6% route), 7 logic levels.
Warning: 12.878 ns is the maximum delay for this constraint.
================================================================================
Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c]
369 items scored, 244 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path violates requirements by 6.291ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1S3AX CK FS_577__i12 (from RCLK_c +)
Destination: FD1P3AX SP LEDEN_392 (to RCLK_c +)
Delay: 11.027ns (23.2% logic, 76.8% route), 6 logic levels.
Constraint Details:
11.027ns data_path FS_577__i12 to LEDEN_392 violates
5.000ns delay constraint less
0.264ns LCE_S requirement (totaling 4.736ns) by 6.291ns
Path Details: FS_577__i12 to LEDEN_392
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.613 CK to Q FS_577__i12 (from RCLK_c)
Route 3 e 1.603 FS[12]
LUT4 --- 0.390 C to Z i4_4_lut
Route 3 e 1.483 n10
LUT4 --- 0.390 B to Z i5_3_lut_rep_23
Route 4 e 1.552 n2300
LUT4 --- 0.390 B to Z i4_3_lut_4_lut
Route 1 e 1.220 n11
LUT4 --- 0.390 C to Z i2_4_lut_adj_4
Route 2 e 1.386 n2119
LUT4 --- 0.390 C to Z i2_3_lut_3_lut
Route 1 e 1.220 RCLK_c_enable_25
--------
11.027 (23.2% logic, 76.8% route), 6 logic levels.
Error: The following path violates requirements by 6.291ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1S3AX CK FS_577__i12 (from RCLK_c +)
Destination: FD1P3AX SP n8MEGEN_391 (to RCLK_c +)
Delay: 11.027ns (23.2% logic, 76.8% route), 6 logic levels.
Constraint Details:
11.027ns data_path FS_577__i12 to n8MEGEN_391 violates
5.000ns delay constraint less
0.264ns LCE_S requirement (totaling 4.736ns) by 6.291ns
Path Details: FS_577__i12 to n8MEGEN_391
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.613 CK to Q FS_577__i12 (from RCLK_c)
Route 3 e 1.603 FS[12]
LUT4 --- 0.390 C to Z i4_4_lut
Route 3 e 1.483 n10
LUT4 --- 0.390 B to Z i5_3_lut_rep_23
Route 4 e 1.552 n2300
LUT4 --- 0.390 B to Z i4_3_lut_4_lut
Route 1 e 1.220 n11
LUT4 --- 0.390 C to Z i2_4_lut_adj_4
Route 2 e 1.386 n2119
LUT4 --- 0.390 D to Z i1248_4_lut
Route 1 e 1.220 RCLK_c_enable_7
--------
11.027 (23.2% logic, 76.8% route), 6 logic levels.
Error: The following path violates requirements by 6.291ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1S3AX CK FS_577__i13 (from RCLK_c +)
Destination: FD1P3AX SP LEDEN_392 (to RCLK_c +)
Delay: 11.027ns (23.2% logic, 76.8% route), 6 logic levels.
Constraint Details:
11.027ns data_path FS_577__i13 to LEDEN_392 violates
5.000ns delay constraint less
0.264ns LCE_S requirement (totaling 4.736ns) by 6.291ns
Path Details: FS_577__i13 to LEDEN_392
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.613 CK to Q FS_577__i13 (from RCLK_c)
Route 3 e 1.603 FS[13]
LUT4 --- 0.390 B to Z i4_4_lut
Route 3 e 1.483 n10
LUT4 --- 0.390 B to Z i5_3_lut_rep_23
Route 4 e 1.552 n2300
LUT4 --- 0.390 B to Z i4_3_lut_4_lut
Route 1 e 1.220 n11
LUT4 --- 0.390 C to Z i2_4_lut_adj_4
Route 2 e 1.386 n2119
LUT4 --- 0.390 C to Z i2_3_lut_3_lut
Route 1 e 1.220 RCLK_c_enable_25
--------
11.027 (23.2% logic, 76.8% route), 6 logic levels.
Warning: 11.291 ns is the maximum delay for this constraint.
<A name="mtw1_rs"></A><B><U><big>Timing Report Summary</big></U></B>
--------------
--------------------------------------------------------------------------------
Constraint | Constraint| Actual|Levels
--------------------------------------------------------------------------------
| | |
create_clock -period 5.000000 -name | | |
clk3 [get_nets nCCAS_c] | -| -| 0
| | |
create_clock -period 5.000000 -name | | |
clk2 [get_nets nCRAS_c] | -| -| 0
| | |
create_clock -period 5.000000 -name | | |
clk1 [get_nets PHI2_c] | 5.000 ns| 25.756 ns| 7 *
| | |
create_clock -period 5.000000 -name | | |
clk0 [get_nets RCLK_c] | 5.000 ns| 11.291 ns| 6 *
| | |
--------------------------------------------------------------------------------
2 constraints not met.
--------------------------------------------------------------------------------
Critical Nets | Loads| Errors| % of total
--------------------------------------------------------------------------------
n1285 | 4| 112| 30.68%
| | |
n26 | 1| 70| 19.18%
| | |
RCLK_c_enable_23 | 16| 64| 17.53%
| | |
n2290 | 3| 64| 17.53%
| | |
XOR8MEG_N_112 | 3| 54| 14.79%
| | |
n2119 | 2| 48| 13.15%
| | |
n2166 | 1| 42| 11.51%
| | |
--------------------------------------------------------------------------------
<A name="mtw1_ts"></A><B><U><big>Timing summary:</big></U></B>
---------------
Timing errors: 365 Score: 2309745
Constraints cover 495 paths, 177 nets, and 464 connections (66.5% coverage)
Peak memory: 52502528 bytes, TRCE: 1482752 bytes, DLYMAN: 163840 bytes
CPU_TIME_REPORT: 0 secs
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// Verilog netlist produced by program LSE : version Diamond (64-bit) 3.12.0.240.2
// Netlist written on Mon Aug 16 21:32:26 2021
//
// Verilog Description of module RAM2GS
//
module RAM2GS (PHI2, MAin, CROW, Din, Dout, nCCAS, nCRAS, nFWE,
LED, RBA, RA, RD, nRCS, RCLK, RCKE, nRWE, nRRAS,
nRCAS, RDQMH, RDQML, nUFMCS, UFMCLK, UFMSDI, UFMSDO) /* synthesis syn_module_defined=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(1[8:14])
input PHI2; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(8[8:12])
input [9:0]MAin; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18])
input [1:0]CROW; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(34[14:18])
input [7:0]Din; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17])
output [7:0]Dout; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19])
input nCCAS; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[8:13])
input nCRAS; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[15:20])
input nFWE; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(36[8:12])
output LED; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(12[9:12])
output [1:0]RBA; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(47[19:22])
output [11:0]RA; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
inout [7:0]RD; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16])
output nRCS; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[13:17])
input RCLK; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(41[8:12])
output RCKE; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(45[13:17])
output nRWE; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[45:49])
output nRRAS; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[23:28])
output nRCAS; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[34:39])
output RDQMH; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(56[16:21])
output RDQML; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(56[9:14])
output nUFMCS; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(63[13:19])
output UFMCLK; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(64[13:19])
output UFMSDI; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(65[13:19])
input UFMSDO; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(66[8:14])
wire PHI2_c /* synthesis is_clock=1, SET_AS_NETWORK=PHI2_c */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(8[8:12])
wire nCCAS_c /* synthesis is_clock=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[8:13])
wire nCRAS_c /* synthesis is_clock=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[15:20])
wire RCLK_c /* synthesis SET_AS_NETWORK=RCLK_c, is_clock=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(41[8:12])
wire nCCAS_N_3 /* synthesis is_inv_clock=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19])
wire nCRAS_N_9 /* synthesis is_inv_clock=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(47[19:22])
wire PHI2_N_114 /* synthesis is_inv_clock=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(38[6:13])
wire GND_net, VCC_net, LEDEN, PHI2r, PHI2r2, PHI2r3, RASr,
RASr2, RASr3, CASr, CASr2, CASr3, FWEr, CBR, Din_c_7,
Din_c_6, Din_c_5, Din_c_4, Din_c_3, Din_c_2, Din_c_1, Din_c_0,
n2131, n33, PHI2_N_114_enable_2, n1;
wire [7:0]Bank; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(31[12:16])
wire CROW_c_1, CROW_c_0, MAin_c_9, MAin_c_8, MAin_c_7, MAin_c_6,
MAin_c_5, MAin_c_4, MAin_c_3, MAin_c_2, MAin_c_1, MAin_c_0,
nFWE_c, n8MEGEN, XOR8MEG, RCKEEN, RCKE_c, nRCS_c, nRRAS_c,
nRCAS_c, nRWE_c, RBA_c_1, RBA_c_0, nRowColSel, RA_c, n980;
wire [9:0]RowA; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(51[12:16])
wire RA_c_9, RA_c_8, RA_c_7, RA_c_6, RA_c_5, RA_c_4, RA_c_3,
RA_c_2, RA_c_1, RA_c_0, RDQML_c, RDQMH_c;
wire [7:0]WRD; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(59[12:15])
wire nUFMCS_c, UFMCLK_c, UFMSDI_c, UFMSDO_c, C1Submitted, ADSubmitted,
CmdEnable, CmdSubmitted, Cmdn8MEGEN, CmdUFMCLK, CmdUFMSDI,
CmdUFMCS, InitReady, Ready;
wire [17:0]FS; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(86[13:15])
wire LED_N_90, RA11_N_180, n2164, n1895, n2294, n4, PHI2_N_114_enable_6,
n1881, RASr2_N_63, RCKE_N_128, nRowColSel_N_35, nRWE_N_178,
RCKEEN_N_126, nRowColSel_N_34, nRowColSel_N_33, nRowColSel_N_32,
nRowColSel_N_28, n1880, n4_adj_1, n2286, RCKEEN_N_117, nRWE_N_174,
RCKEEN_N_116, nRCS_N_135, nRCAS_N_161, nRWE_N_173, nRWE_N_172,
n1377, Ready_N_272, n2287, n26, Ready_N_268, nRCS_N_132,
nRCAS_N_157, nRWE_N_167, RCKEEN_N_115, n2290, n2289, n1361,
n1369, ADSubmitted_N_234, CmdEnable_N_236, C1Submitted_N_225,
XOR8MEG_N_112, n2098, PHI2_N_114_enable_1, n2248, Cmdn8MEGEN_N_248,
RCLK_c_enable_7, n2244, n2117, LEDEN_N_88, RCLK_c_enable_6,
UFMSDO_N_74, n2243, RCLK_c_enable_24, n8MEGEN_N_94, UFMCLK_N_212,
UFMSDI_N_219, n2242, n2114, n2080, PHI2_N_114_enable_7, n12,
n699, n700, n701, n702, n703, n705, n706, n707, n708,
n709, n710, n711, n11, n2076, n2119, n1368, n12_adj_2,
n1878, PHI2_N_114_enable_8, n2308, n2291, n2307, n11_adj_3,
n973, n1135, n78, n79, n80, n81, n82, n83, n84, n85,
n86, n87, n88, n89, n90, n91, n92, n93, n94, n95,
n1348, n50, n1877, RCLK_c_enable_23, n1876, n1875, n2293,
n2306, RCLK_c_enable_4, n2170, RCLK_c_enable_25, RCLK_c_enable_3,
n2128, n2103, n2304, n2386, n1879, n1874, n2310, n974,
n975, n962, n976, n2168, n977, n2245, n978, n2122, n979,
Dout_c, n2166, n2302, n2108, n2301, n2387, n1285, n2300,
n1628, n1627, n2299, n18, n2385, n2309, n2298, n2292,
n2297, n2154, n10, n2296, n2295;
VHI i2 (.Z(VCC_net));
INV i1963 (.A(nCCAS_c), .Z(nCCAS_N_3)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[8:13])
FD1S3AX PHI2r2_350 (.D(PHI2r), .CK(RCLK_c), .Q(PHI2r2)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5])
defparam PHI2r2_350.GSR = "ENABLED";
ORCALUT4 i2_3_lut_4_lut (.A(XOR8MEG_N_112), .B(n2298), .C(n2296),
.D(Din_c_5), .Z(PHI2_N_114_enable_7)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ;
defparam i2_3_lut_4_lut.init = 16'h0800;
ORCALUT4 i1_2_lut_3_lut (.A(FS[11]), .B(n2300), .C(InitReady), .Z(n4)) /* synthesis lut_function=((B+(C))+!A) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37])
defparam i1_2_lut_3_lut.init = 16'hfdfd;
FD1S3AX PHI2r3_351 (.D(PHI2r2), .CK(RCLK_c), .Q(PHI2r3)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5])
defparam PHI2r3_351.GSR = "ENABLED";
FD1S3AX RASr_352 (.D(nCRAS_N_9), .CK(RCLK_c), .Q(RASr)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5])
defparam RASr_352.GSR = "ENABLED";
FD1S3AX RASr2_353 (.D(RASr), .CK(RCLK_c), .Q(RASr2)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5])
defparam RASr2_353.GSR = "ENABLED";
FD1S3AX RASr3_354 (.D(RASr2), .CK(RCLK_c), .Q(RASr3)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5])
defparam RASr3_354.GSR = "ENABLED";
FD1S3AX CASr_355 (.D(nCCAS_N_3), .CK(RCLK_c), .Q(CASr)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5])
defparam CASr_355.GSR = "ENABLED";
FD1S3AX CASr2_356 (.D(CASr), .CK(RCLK_c), .Q(CASr2)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5])
defparam CASr2_356.GSR = "ENABLED";
FD1S3AX CASr3_357 (.D(CASr2), .CK(RCLK_c), .Q(CASr3)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5])
defparam CASr3_357.GSR = "ENABLED";
FD1S3IX RA11_358 (.D(RA11_N_180), .CK(PHI2_c), .CD(n2307), .Q(RA_c)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5])
defparam RA11_358.GSR = "ENABLED";
FD1S3IX RowA_i0 (.D(MAin_c_0), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[0])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
defparam RowA_i0.GSR = "ENABLED";
FD1S3AX WRD_i0 (.D(Din_c_0), .CK(nCCAS_N_3), .Q(WRD[0])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5])
defparam WRD_i0.GSR = "ENABLED";
FD1S3AX FWEr_362 (.D(n2306), .CK(nCRAS_N_9), .Q(FWEr)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
defparam FWEr_362.GSR = "ENABLED";
FD1S3AX CBR_363 (.D(nCCAS_N_3), .CK(nCRAS_N_9), .Q(CBR)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
defparam CBR_363.GSR = "ENABLED";
FD1S3IX ADSubmitted_380 (.D(n1361), .CK(PHI2_N_114), .CD(C1Submitted_N_225),
.Q(ADSubmitted)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5])
defparam ADSubmitted_380.GSR = "ENABLED";
ORCALUT4 MAin_9__I_0_400_i5_3_lut (.A(RowA[4]), .B(MAin_c_4), .C(nRowColSel),
.Z(RA_c_4)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54])
defparam MAin_9__I_0_400_i5_3_lut.init = 16'hcaca;
ORCALUT4 i1_2_lut (.A(FS[10]), .B(n2076), .Z(RCLK_c_enable_6)) /* synthesis lut_function=(A (B)) */ ;
defparam i1_2_lut.init = 16'h8888;
CCU2 FS_577_add_4_10 (.A0(FS[8]), .B0(GND_net), .C0(GND_net), .D0(GND_net),
.A1(FS[9]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1877),
.COUT1(n1878), .S0(n87), .S1(n86)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
defparam FS_577_add_4_10.INIT0 = 16'hfaaa;
defparam FS_577_add_4_10.INIT1 = 16'hfaaa;
defparam FS_577_add_4_10.INJECT1_0 = "NO";
defparam FS_577_add_4_10.INJECT1_1 = "NO";
FD1S3AX RCKE_368 (.D(RCKE_N_128), .CK(RCLK_c), .Q(RCKE_c)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(141[9] 144[5])
defparam RCKE_368.GSR = "ENABLED";
FD1P3AY nRCS_369 (.D(nRCS_N_132), .SP(RCLK_c_enable_4), .CK(RCLK_c),
.Q(nRCS_c)) /* synthesis lse_init_val=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
defparam nRCS_369.GSR = "ENABLED";
FD1S3IX nRowColSel_375 (.D(n1368), .CK(RCLK_c), .CD(n2299), .Q(nRowColSel)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
defparam nRowColSel_375.GSR = "ENABLED";
ORCALUT4 n1_bdd_4_lut (.A(n1), .B(n1627), .C(nRWE_N_178), .D(nRowColSel_N_35),
.Z(nRWE_N_174)) /* synthesis lut_function=(A (B (C+!(D))+!B (C (D)))+!A (C+!(D))) */ ;
defparam n1_bdd_4_lut.init = 16'hf0dd;
ORCALUT4 i2_3_lut_rep_31 (.A(PHI2r3), .B(CmdSubmitted), .C(PHI2r2),
.Z(n2308)) /* synthesis lut_function=(!(((C)+!B)+!A)) */ ;
defparam i2_3_lut_rep_31.init = 16'h0808;
ORCALUT4 i1_2_lut_2_lut_4_lut (.A(PHI2r3), .B(CmdSubmitted), .C(PHI2r2),
.D(InitReady), .Z(RCLK_c_enable_24)) /* synthesis lut_function=(!(A (B (C (D))+!B (D))+!A (D))) */ ;
defparam i1_2_lut_2_lut_4_lut.init = 16'h08ff;
CCU2 FS_577_add_4_8 (.A0(FS[6]), .B0(GND_net), .C0(GND_net), .D0(GND_net),
.A1(FS[7]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1876),
.COUT1(n1877), .S0(n89), .S1(n88)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
defparam FS_577_add_4_8.INIT0 = 16'hfaaa;
defparam FS_577_add_4_8.INIT1 = 16'hfaaa;
defparam FS_577_add_4_8.INJECT1_0 = "NO";
defparam FS_577_add_4_8.INJECT1_1 = "NO";
ORCALUT4 i1_4_lut (.A(nRowColSel_N_34), .B(n1), .C(n2304), .D(nRowColSel_N_33),
.Z(n2117)) /* synthesis lut_function=(!(A+(B (C (D))+!B (C+!(D))))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(84[6:11])
defparam i1_4_lut.init = 16'h0544;
ORCALUT4 i3_4_lut (.A(MAin_c_1), .B(MAin_c_0), .C(CmdEnable), .D(n2290),
.Z(XOR8MEG_N_112)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ;
defparam i3_4_lut.init = 16'h0040;
ORCALUT4 i4_3_lut_4_lut (.A(FS[11]), .B(n2300), .C(FS[6]), .D(n2168),
.Z(n11)) /* synthesis lut_function=((B+(C+!(D)))+!A) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37])
defparam i4_3_lut_4_lut.init = 16'hfdff;
FD1S3IX S_FSM_i2 (.D(n1135), .CK(RCLK_c), .CD(n2302), .Q(nRowColSel_N_34)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
defparam S_FSM_i2.GSR = "ENABLED";
ORCALUT4 i1_4_lut_adj_1 (.A(nRowColSel), .B(n1627), .C(nRowColSel_N_28),
.D(nRowColSel_N_32), .Z(n1368)) /* synthesis lut_function=(A (B+!(C (D)))+!A (B+!(C+!(D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
defparam i1_4_lut_adj_1.init = 16'hcfee;
FD1S3AY nRRAS_370 (.D(n33), .CK(RCLK_c), .Q(nRRAS_c)) /* synthesis lse_init_val=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
defparam nRRAS_370.GSR = "ENABLED";
ORCALUT4 i1055_3_lut_4_lut (.A(MAin_c_1), .B(n2290), .C(ADSubmitted),
.D(ADSubmitted_N_234), .Z(n1361)) /* synthesis lut_function=(A (B (C+(D))+!B (D))+!A (C+(D))) */ ;
defparam i1055_3_lut_4_lut.init = 16'hffd0;
ORCALUT4 i2_3_lut (.A(FWEr), .B(CASr3), .C(CBR), .Z(nRowColSel_N_28)) /* synthesis lut_function=((B+(C))+!A) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(230[16:37])
defparam i2_3_lut.init = 16'hfdfd;
BB Dout_pad_7__688 (.I(WRD[7]), .T(n962), .B(RD[7]), .O(n973)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16])
FD1P3AY nRCAS_371 (.D(nRCAS_N_157), .SP(RCLK_c_enable_4), .CK(RCLK_c),
.Q(nRCAS_c)) /* synthesis lse_init_val=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
defparam nRCAS_371.GSR = "ENABLED";
FD1P3AY nRWE_372 (.D(nRWE_N_167), .SP(RCLK_c_enable_3), .CK(RCLK_c),
.Q(nRWE_c)) /* synthesis lse_init_val=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
defparam nRWE_372.GSR = "ENABLED";
FD1S3JX RA10_373 (.D(n2128), .CK(RCLK_c), .PD(nRWE_N_172), .Q(n980)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
defparam RA10_373.GSR = "ENABLED";
FD1P3AX RCKEEN_374 (.D(RCKEEN_N_115), .SP(RCLK_c_enable_4), .CK(RCLK_c),
.Q(RCKEEN)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
defparam RCKEEN_374.GSR = "ENABLED";
ORCALUT4 i2_4_lut (.A(n2122), .B(n2295), .C(Din_c_2), .D(n2131),
.Z(C1Submitted_N_225)) /* synthesis lut_function=(!(((C+(D))+!B)+!A)) */ ;
defparam i2_4_lut.init = 16'h0008;
FD1S3IX RBA__i1 (.D(CROW_c_0), .CK(nCRAS_N_9), .CD(n2307), .Q(RBA_c_0)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
defparam RBA__i1.GSR = "ENABLED";
ORCALUT4 Din_7__I_0_442_i6_2_lut_rep_32 (.A(Din_c_6), .B(Din_c_7), .Z(n2385)) /* synthesis lut_function=(A+(B)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(312[17:31])
defparam Din_7__I_0_442_i6_2_lut_rep_32.init = 16'heeee;
ORCALUT4 i1248_4_lut (.A(FS[5]), .B(n2308), .C(InitReady), .D(n2119),
.Z(RCLK_c_enable_7)) /* synthesis lut_function=(A (B (C))+!A (B (C+(D))+!B !(C+!(D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(83[6:15])
defparam i1248_4_lut.init = 16'hc5c0;
ORCALUT4 i2_3_lut_4_lut_adj_2 (.A(nRowColSel_N_32), .B(n2299), .C(nRowColSel_N_34),
.D(nRowColSel_N_33), .Z(RCLK_c_enable_4)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
defparam i2_3_lut_4_lut_adj_2.init = 16'hfffe;
ORCALUT4 i1437_4_lut (.A(UFMSDO_c), .B(Cmdn8MEGEN), .C(FS[10]), .D(n4),
.Z(n8MEGEN_N_94)) /* synthesis lut_function=(A (B ((D)+!C))+!A (B+!((D)+!C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(83[6:15])
defparam i1437_4_lut.init = 16'hcc5c;
FD1P3AX IS_FSM__i0 (.D(Ready_N_272), .SP(RCLK_c_enable_23), .CK(RCLK_c),
.Q(nRCS_N_135)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
defparam IS_FSM__i0.GSR = "ENABLED";
ORCALUT4 i1_2_lut_adj_3 (.A(RASr2), .B(RCKE_c), .Z(nRWE_N_178)) /* synthesis lut_function=(A+!(B)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5])
defparam i1_2_lut_adj_3.init = 16'hbbbb;
ORCALUT4 i2_4_lut_adj_4 (.A(n2294), .B(FS[10]), .C(n11), .D(n12),
.Z(n2119)) /* synthesis lut_function=(!(((C+(D))+!B)+!A)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37])
defparam i2_4_lut_adj_4.init = 16'h0008;
FD1P3JX C1Submitted_379 (.D(n2386), .SP(PHI2_N_114_enable_1), .PD(C1Submitted_N_225),
.CK(PHI2_N_114), .Q(C1Submitted)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5])
defparam C1Submitted_379.GSR = "ENABLED";
FD1S3JX nUFMCS_388 (.D(n1348), .CK(RCLK_c), .PD(LEDEN_N_88), .Q(nUFMCS_c)) /* synthesis lse_init_val=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(327[9] 396[5])
defparam nUFMCS_388.GSR = "ENABLED";
ORCALUT4 m1_lut (.Z(n2387)) /* synthesis lut_function=1, syn_instantiated=1 */ ;
defparam m1_lut.init = 16'hffff;
ORCALUT4 i2_4_lut_adj_5 (.A(n2108), .B(MAin_c_1), .C(C1Submitted),
.D(MAin_c_0), .Z(n2098)) /* synthesis lut_function=(!(((C+!(D))+!B)+!A)) */ ;
defparam i2_4_lut_adj_5.init = 16'h0800;
ORCALUT4 i5_4_lut (.A(FS[9]), .B(FS[4]), .C(FS[8]), .D(FS[7]), .Z(n12)) /* synthesis lut_function=(A+((C+(D))+!B)) */ ;
defparam i5_4_lut.init = 16'hfffb;
FD1S3AX FS_577__i0 (.D(n95), .CK(RCLK_c), .Q(FS[0])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
defparam FS_577__i0.GSR = "ENABLED";
ORCALUT4 i2_3_lut_adj_6 (.A(n2122), .B(ADSubmitted), .C(MAin_c_0),
.Z(n2080)) /* synthesis lut_function=(!((B+(C))+!A)) */ ;
defparam i2_3_lut_adj_6.init = 16'h0202;
ORCALUT4 i1419_2_lut (.A(MAin_c_9), .B(nRowColSel), .Z(RDQMH_c)) /* synthesis lut_function=(A+!(B)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(58[17:46])
defparam i1419_2_lut.init = 16'hbbbb;
ORCALUT4 n50_bdd_4_lut_1911 (.A(n50), .B(RASr2), .C(RCKE_c), .D(nRowColSel_N_35),
.Z(n2242)) /* synthesis lut_function=(!(A (B (D)+!B (C (D)))+!A (B+(C+!(D))))) */ ;
defparam n50_bdd_4_lut_1911.init = 16'h03aa;
ORCALUT4 i1893_2_lut (.A(MAin_c_9), .B(nRowColSel), .Z(RDQML_c)) /* synthesis lut_function=(!(A (B))) */ ;
defparam i1893_2_lut.init = 16'h7777;
FD1S3AX Bank_i0 (.D(Din_c_0), .CK(PHI2_c), .Q(Bank[0])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5])
defparam Bank_i0.GSR = "ENABLED";
ORCALUT4 i1858_4_lut (.A(FS[1]), .B(FS[0]), .C(FS[2]), .D(FS[3]),
.Z(n2168)) /* synthesis lut_function=(A (B (C (D)))) */ ;
defparam i1858_4_lut.init = 16'h8000;
ORCALUT4 i1_2_lut_3_lut_adj_7 (.A(MAin_c_1), .B(n1285), .C(MAin_c_0),
.Z(n2131)) /* synthesis lut_function=((B+(C))+!A) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(80[15:31])
defparam i1_2_lut_3_lut_adj_7.init = 16'hfdfd;
ORCALUT4 i22_4_lut (.A(FS[4]), .B(CmdUFMCLK), .C(InitReady), .D(n2076),
.Z(UFMCLK_N_212)) /* synthesis lut_function=(A (B (C+!(D))+!B !(C+(D)))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(83[6:15])
defparam i22_4_lut.init = 16'hc0ca;
ORCALUT4 i5_4_lut_adj_8 (.A(FS[14]), .B(FS[16]), .C(FS[13]), .D(FS[12]),
.Z(n12_adj_2)) /* synthesis lut_function=(A (B (C (D)))) */ ;
defparam i5_4_lut_adj_8.init = 16'h8000;
ORCALUT4 i1889_4_lut_then_4_lut (.A(n2117), .B(RCKE_c), .C(RASr2),
.D(nRowColSel_N_35), .Z(n2310)) /* synthesis lut_function=(!(A (B+(C+!(D)))+!A (B (D)+!B (C (D))))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(84[6:11])
defparam i1889_4_lut_then_4_lut.init = 16'h0355;
ORCALUT4 i1889_4_lut_else_4_lut (.A(InitReady), .B(nRCS_N_135), .C(RASr2),
.D(nRowColSel_N_35), .Z(n2309)) /* synthesis lut_function=((B+!(C (D)))+!A) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(84[6:11])
defparam i1889_4_lut_else_4_lut.init = 16'hdfff;
CCU2 FS_577_add_4_18 (.A0(FS[16]), .B0(GND_net), .C0(GND_net), .D0(GND_net),
.A1(FS[17]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1881),
.S0(n79), .S1(n78)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
defparam FS_577_add_4_18.INIT0 = 16'hfaaa;
defparam FS_577_add_4_18.INIT1 = 16'hfaaa;
defparam FS_577_add_4_18.INJECT1_0 = "NO";
defparam FS_577_add_4_18.INJECT1_1 = "NO";
ORCALUT4 UFMSDO_I_0_1_lut (.A(UFMSDO_c), .Z(UFMSDO_N_74)) /* synthesis lut_function=(!(A)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(378[53:60])
defparam UFMSDO_I_0_1_lut.init = 16'h5555;
FD1S3IX S_FSM_i3 (.D(n1135), .CK(RCLK_c), .CD(n1377), .Q(nRowColSel_N_33)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
defparam S_FSM_i3.GSR = "ENABLED";
ORCALUT4 i1897_2_lut_rep_14_3_lut (.A(FS[11]), .B(n2300), .C(InitReady),
.Z(n2291)) /* synthesis lut_function=(!(A+(B+(C)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37])
defparam i1897_2_lut_rep_14_3_lut.init = 16'h0101;
ORCALUT4 i1878_2_lut_3_lut_4_lut (.A(FS[11]), .B(n2300), .C(FS[10]),
.D(InitReady), .Z(LEDEN_N_88)) /* synthesis lut_function=(!(A+(B+(C+(D))))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37])
defparam i1878_2_lut_3_lut_4_lut.init = 16'h0001;
ORCALUT4 i1884_4_lut (.A(MAin_c_0), .B(n2290), .C(n2286), .D(MAin_c_1),
.Z(PHI2_N_114_enable_8)) /* synthesis lut_function=(!(A (B+(C))+!A (B+(C+!(D))))) */ ;
defparam i1884_4_lut.init = 16'h0302;
FD1S3AX PHI2r_349 (.D(PHI2_c), .CK(RCLK_c), .Q(PHI2r)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(91[9] 95[5])
defparam PHI2r_349.GSR = "ENABLED";
ORCALUT4 i2_3_lut_rep_21_4_lut (.A(Din_c_6), .B(Din_c_7), .C(Din_c_5),
.D(Din_c_4), .Z(n2298)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(312[17:31])
defparam i2_3_lut_rep_21_4_lut.init = 16'hfffe;
ORCALUT4 i1830_2_lut_rep_13 (.A(nFWE_c), .B(n1285), .Z(n2290)) /* synthesis lut_function=(A+(B)) */ ;
defparam i1830_2_lut_rep_13.init = 16'heeee;
PFUMX i1912 (.BLUT(n2243), .ALUT(n2242), .C0(Ready), .Z(n2244));
FD1S3AX S_FSM_i1 (.D(RASr2_N_63), .CK(RCLK_c), .Q(nRowColSel_N_35)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
defparam S_FSM_i1.GSR = "ENABLED";
ORCALUT4 i1886_2_lut (.A(nRowColSel_N_32), .B(RASr2), .Z(n1135)) /* synthesis lut_function=(!(A+!(B))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
defparam i1886_2_lut.init = 16'h4444;
ORCALUT4 n50_bdd_4_lut (.A(n50), .B(InitReady), .C(RASr2), .D(nRowColSel_N_35),
.Z(n2243)) /* synthesis lut_function=(!(A (B (C (D)))+!A (B (C)))) */ ;
defparam n50_bdd_4_lut.init = 16'h3fbf;
ORCALUT4 i1034_2_lut (.A(ADSubmitted_N_234), .B(C1Submitted_N_225),
.Z(CmdEnable_N_236)) /* synthesis lut_function=(A+(B)) */ ;
defparam i1034_2_lut.init = 16'heeee;
ORCALUT4 i2_3_lut_4_lut_adj_9 (.A(Din_c_6), .B(Din_c_7), .C(XOR8MEG_N_112),
.D(Din_c_4), .Z(PHI2_N_114_enable_6)) /* synthesis lut_function=(!(A+(B+!(C (D))))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(312[17:31])
defparam i2_3_lut_4_lut_adj_9.init = 16'h1000;
ORCALUT4 i1832_2_lut_rep_19_3_lut (.A(Din_c_6), .B(Din_c_7), .C(Din_c_4),
.Z(n2296)) /* synthesis lut_function=(A+(B+!(C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(312[17:31])
defparam i1832_2_lut_rep_19_3_lut.init = 16'hefef;
FD1S3IX S_FSM_i4 (.D(n1628), .CK(RCLK_c), .CD(RASr2_N_63), .Q(nRowColSel_N_32)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
defparam S_FSM_i4.GSR = "ENABLED";
ORCALUT4 i1424_2_lut_rep_27 (.A(FWEr), .B(CBR), .Z(n2304)) /* synthesis lut_function=(A+(B)) */ ;
defparam i1424_2_lut_rep_27.init = 16'heeee;
ORCALUT4 i2_3_lut_adj_10 (.A(Din_c_3), .B(Din_c_6), .C(Din_c_5), .Z(n2122)) /* synthesis lut_function=(!(A+((C)+!B))) */ ;
defparam i2_3_lut_adj_10.init = 16'h0404;
ORCALUT4 i1429_2_lut_3_lut (.A(FWEr), .B(CBR), .C(RASr2), .Z(RCKEEN_N_126)) /* synthesis lut_function=(!(A (C)+!A (B (C)))) */ ;
defparam i1429_2_lut_3_lut.init = 16'h1f1f;
ORCALUT4 i4_4_lut (.A(FS[14]), .B(FS[13]), .C(FS[12]), .D(FS[15]),
.Z(n10)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37])
defparam i4_4_lut.init = 16'hfffe;
ORCALUT4 i5_3_lut_rep_23 (.A(FS[16]), .B(n10), .C(FS[17]), .Z(n2300)) /* synthesis lut_function=(A+(B+(C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37])
defparam i5_3_lut_rep_23.init = 16'hfefe;
ORCALUT4 i1_4_lut_adj_11 (.A(n2244), .B(n2297), .C(n18), .D(Ready),
.Z(n33)) /* synthesis lut_function=(A+(B (C+!(D))+!B (C (D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(84[6:11])
defparam i1_4_lut_adj_11.init = 16'hfaee;
ORCALUT4 i1_2_lut_rep_16_4_lut (.A(FS[16]), .B(n10), .C(FS[17]), .D(FS[11]),
.Z(n2293)) /* synthesis lut_function=(A+(B+(C+!(D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37])
defparam i1_2_lut_rep_16_4_lut.init = 16'hfeff;
ORCALUT4 i3_4_lut_adj_12 (.A(CBR), .B(FWEr), .C(CASr2), .D(CASr3),
.Z(n1)) /* synthesis lut_function=(!(A+(((D)+!C)+!B))) */ ;
defparam i3_4_lut_adj_12.init = 16'h0040;
ORCALUT4 i1_2_lut_adj_13 (.A(nRowColSel_N_34), .B(nRowColSel_N_33),
.Z(n1627)) /* synthesis lut_function=(A+(B)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
defparam i1_2_lut_adj_13.init = 16'heeee;
ORCALUT4 i1420_2_lut (.A(nCCAS_c), .B(nFWE_c), .Z(n962)) /* synthesis lut_function=(A+(B)) */ ;
defparam i1420_2_lut.init = 16'heeee;
ORCALUT4 i1_1_lut_rep_29 (.A(nFWE_c), .Z(n2306)) /* synthesis lut_function=(!(A)) */ ;
defparam i1_1_lut_rep_29.init = 16'h5555;
ORCALUT4 Cmdn8MEGEN_I_84_4_lut (.A(Din_c_0), .B(n8MEGEN), .C(Din_c_5),
.D(n2296), .Z(Cmdn8MEGEN_N_248)) /* synthesis lut_function=(A (B (C+(D)))+!A (B+!(C+(D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(316[13] 322[7])
defparam Cmdn8MEGEN_I_84_4_lut.init = 16'hccc5;
ORCALUT4 i1069_1_lut (.A(nRowColSel_N_34), .Z(n1377)) /* synthesis lut_function=(!(A)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
defparam i1069_1_lut.init = 16'h5555;
ORCALUT4 n2080_bdd_4_lut (.A(n2080), .B(n2098), .C(Din_c_2), .D(n2114),
.Z(n2286)) /* synthesis lut_function=(A (B (D)+!B !(C+!(D)))+!A (B (C (D)))) */ ;
defparam n2080_bdd_4_lut.init = 16'hca00;
ORCALUT4 RASr2_I_0_1_lut (.A(RASr2), .Z(RASr2_N_63)) /* synthesis lut_function=(!(A)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(143[40:46])
defparam RASr2_I_0_1_lut.init = 16'h5555;
ORCALUT4 i847_2_lut_4_lut (.A(n2385), .B(Din_c_4), .C(Din_c_5), .D(XOR8MEG_N_112),
.Z(PHI2_N_114_enable_2)) /* synthesis lut_function=(!(A+(B+(C+!(D))))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(310[8:22])
defparam i847_2_lut_4_lut.init = 16'h0100;
ORCALUT4 i1_4_lut_adj_14 (.A(n2108), .B(MAin_c_0), .C(n4_adj_1), .D(n2289),
.Z(ADSubmitted_N_234)) /* synthesis lut_function=(!((((D)+!C)+!B)+!A)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(309[7:24])
defparam i1_4_lut_adj_14.init = 16'h0080;
ORCALUT4 i1_2_lut_adj_15 (.A(nRowColSel_N_33), .B(CASr2), .Z(n11_adj_3)) /* synthesis lut_function=(A+!(B)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(48[6:16])
defparam i1_2_lut_adj_15.init = 16'hbbbb;
FD1S3AX FS_577__i17 (.D(n78), .CK(RCLK_c), .Q(FS[17])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
defparam FS_577__i17.GSR = "ENABLED";
ORCALUT4 i1_2_lut_3_lut_3_lut (.A(nFWE_c), .B(Din_c_2), .C(n2114),
.Z(n4_adj_1)) /* synthesis lut_function=(!(A+!(B (C)))) */ ;
defparam i1_2_lut_3_lut_3_lut.init = 16'h4040;
FD1S3AX FS_577__i16 (.D(n79), .CK(RCLK_c), .Q(FS[16])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
defparam FS_577__i16.GSR = "ENABLED";
FD1S3AX FS_577__i15 (.D(n80), .CK(RCLK_c), .Q(FS[15])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
defparam FS_577__i15.GSR = "ENABLED";
ORCALUT4 nRWE_I_0_428_4_lut (.A(n2164), .B(nRWE_N_174), .C(Ready),
.D(n2292), .Z(nRWE_N_167)) /* synthesis lut_function=(A (B (C+(D))+!B !(C+!(D)))+!A (B+!(C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(232[12] 284[6])
defparam nRWE_I_0_428_4_lut.init = 16'hcfc5;
ORCALUT4 i1257_3_lut (.A(n1895), .B(CmdUFMSDI), .C(InitReady), .Z(UFMSDI_N_219)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(83[6:15])
defparam i1257_3_lut.init = 16'hcaca;
ORCALUT4 RCKE_I_0_423_4_lut (.A(RASr), .B(RCKEEN), .C(RASr2), .D(RASr3),
.Z(RCKE_N_128)) /* synthesis lut_function=(A (B+!(C+!(D)))+!A (B (C+(D))+!B !(C+!(D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(143[11:55])
defparam RCKE_I_0_423_4_lut.init = 16'hcfc8;
FD1P3AX InitReady_367 (.D(n2387), .SP(RCLK_c_enable_6), .CK(RCLK_c),
.Q(InitReady)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(134[9] 138[5])
defparam InitReady_367.GSR = "ENABLED";
ORCALUT4 i1_2_lut_adj_16 (.A(nRowColSel_N_32), .B(nRowColSel_N_33),
.Z(n1628)) /* synthesis lut_function=(A+(B)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
defparam i1_2_lut_adj_16.init = 16'heeee;
ORCALUT4 i1854_2_lut (.A(nRCAS_N_161), .B(nRWE_N_173), .Z(n2164)) /* synthesis lut_function=(A+(B)) */ ;
defparam i1854_2_lut.init = 16'heeee;
ORCALUT4 i1_2_lut_rep_17_4_lut (.A(FS[16]), .B(n10), .C(FS[17]), .D(FS[11]),
.Z(n2294)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(328[21:37])
defparam i1_2_lut_rep_17_4_lut.init = 16'hfffe;
ORCALUT4 i1881_2_lut_rep_24 (.A(RASr2), .B(InitReady), .Z(n2301)) /* synthesis lut_function=(!(A (B))) */ ;
defparam i1881_2_lut_rep_24.init = 16'h7777;
GSR GSR_INST (.GSR(VCC_net));
ORCALUT4 i1_2_lut_rep_18_2_lut (.A(nFWE_c), .B(n2114), .Z(n2295)) /* synthesis lut_function=(!(A+!(B))) */ ;
defparam i1_2_lut_rep_18_2_lut.init = 16'h4444;
FD1S3AX FS_577__i14 (.D(n81), .CK(RCLK_c), .Q(FS[14])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
defparam FS_577__i14.GSR = "ENABLED";
ORCALUT4 i2_3_lut_3_lut (.A(InitReady), .B(FS[5]), .C(n2119), .Z(RCLK_c_enable_25)) /* synthesis lut_function=(!(A+!(B (C)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(384[16:26])
defparam i2_3_lut_3_lut.init = 16'h4040;
ORCALUT4 i2_3_lut_adj_17 (.A(Din_c_6), .B(Din_c_5), .C(Din_c_3), .Z(n2108)) /* synthesis lut_function=(!(A+!(B (C)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(309[7:24])
defparam i2_3_lut_adj_17.init = 16'h4040;
ORCALUT4 i2_4_lut_adj_18 (.A(FS[6]), .B(n2293), .C(n2103), .D(FS[10]),
.Z(n1895)) /* synthesis lut_function=(!((B+((D)+!C))+!A)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
defparam i2_4_lut_adj_18.init = 16'h0020;
ORCALUT4 i1_4_lut_adj_19 (.A(FS[8]), .B(FS[7]), .C(FS[5]), .D(FS[9]),
.Z(n2103)) /* synthesis lut_function=(!(A+(B (D)+!B !(C (D))))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(339[4] 372[11])
defparam i1_4_lut_adj_19.init = 16'h1044;
FD1P3AX XOR8MEG_381 (.D(Din_c_0), .SP(PHI2_N_114_enable_2), .CK(PHI2_N_114),
.Q(XOR8MEG)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5])
defparam XOR8MEG_381.GSR = "ENABLED";
FD1P3AX n8MEGEN_391 (.D(n8MEGEN_N_94), .SP(RCLK_c_enable_7), .CK(RCLK_c),
.Q(n8MEGEN)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(327[9] 396[5])
defparam n8MEGEN_391.GSR = "ENABLED";
FD1P3AX Ready_377 (.D(n2387), .SP(Ready_N_268), .CK(RCLK_c), .Q(Ready)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
defparam Ready_377.GSR = "ENABLED";
ORCALUT4 MAin_9__I_0_400_i2_3_lut (.A(RowA[1]), .B(MAin_c_1), .C(nRowColSel),
.Z(RA_c_1)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54])
defparam MAin_9__I_0_400_i2_3_lut.init = 16'hcaca;
FD1P3AX CmdUFMCLK_386 (.D(Din_c_1), .SP(PHI2_N_114_enable_7), .CK(PHI2_N_114),
.Q(CmdUFMCLK)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5])
defparam CmdUFMCLK_386.GSR = "ENABLED";
FD1P3AX CmdUFMSDI_387 (.D(Din_c_0), .SP(PHI2_N_114_enable_7), .CK(PHI2_N_114),
.Q(CmdUFMSDI)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5])
defparam CmdUFMSDI_387.GSR = "ENABLED";
FD1P3AX Cmdn8MEGEN_383 (.D(Cmdn8MEGEN_N_248), .SP(PHI2_N_114_enable_6),
.CK(PHI2_N_114), .Q(Cmdn8MEGEN)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5])
defparam Cmdn8MEGEN_383.GSR = "ENABLED";
FD1P3AX CmdSubmitted_384 (.D(n2387), .SP(PHI2_N_114_enable_6), .CK(PHI2_N_114),
.Q(CmdSubmitted)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5])
defparam CmdSubmitted_384.GSR = "ENABLED";
CCU2 FS_577_add_4_6 (.A0(FS[4]), .B0(GND_net), .C0(GND_net), .D0(GND_net),
.A1(FS[5]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1875),
.COUT1(n1876), .S0(n91), .S1(n90)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
defparam FS_577_add_4_6.INIT0 = 16'hfaaa;
defparam FS_577_add_4_6.INIT1 = 16'hfaaa;
defparam FS_577_add_4_6.INJECT1_0 = "NO";
defparam FS_577_add_4_6.INJECT1_1 = "NO";
FD1P3AX CmdUFMCS_385 (.D(Din_c_2), .SP(PHI2_N_114_enable_7), .CK(PHI2_N_114),
.Q(CmdUFMCS)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5])
defparam CmdUFMCS_385.GSR = "ENABLED";
FD1S3AX FS_577__i13 (.D(n82), .CK(RCLK_c), .Q(FS[13])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
defparam FS_577__i13.GSR = "ENABLED";
ORCALUT4 i1875_2_lut (.A(nCRAS_c), .B(LEDEN), .Z(LED_N_90)) /* synthesis lut_function=(A+!(B)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(13[15:34])
defparam i1875_2_lut.init = 16'hbbbb;
FD1S3AX FS_577__i12 (.D(n83), .CK(RCLK_c), .Q(FS[12])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
defparam FS_577__i12.GSR = "ENABLED";
PFUMX RCKEEN_I_0_419 (.BLUT(RCKEEN_N_117), .ALUT(RCKEEN_N_126), .C0(nRowColSel_N_35),
.Z(RCKEEN_N_116));
ORCALUT4 i1856_4_lut (.A(Bank[0]), .B(Bank[5]), .C(MAin_c_2), .D(Bank[6]),
.Z(n2166)) /* synthesis lut_function=(A (B (C (D)))) */ ;
defparam i1856_4_lut.init = 16'h8000;
FD1S3AX FS_577__i11 (.D(n84), .CK(RCLK_c), .Q(FS[11])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
defparam FS_577__i11.GSR = "ENABLED";
ORCALUT4 i1844_2_lut (.A(Bank[7]), .B(MAin_c_4), .Z(n2154)) /* synthesis lut_function=(A (B)) */ ;
defparam i1844_2_lut.init = 16'h8888;
ORCALUT4 RA11_I_53_3_lut (.A(Din_c_6), .B(XOR8MEG), .C(n8MEGEN), .Z(RA11_N_180)) /* synthesis lut_function=(A (B (C)+!B !(C))+!A (B)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(99[22:51])
defparam RA11_I_53_3_lut.init = 16'hc6c6;
ORCALUT4 Ready_bdd_3_lut_1922 (.A(nRCAS_N_161), .B(nRCS_N_135), .C(InitReady),
.Z(n2248)) /* synthesis lut_function=(A+(B+!(C))) */ ;
defparam Ready_bdd_3_lut_1922.init = 16'hefef;
FD1P3IX UFMSDI_390 (.D(UFMSDI_N_219), .SP(RCLK_c_enable_24), .CD(n2291),
.CK(RCLK_c), .Q(UFMSDI_c)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(327[9] 396[5])
defparam UFMSDI_390.GSR = "ENABLED";
ORCALUT4 MAin_9__I_0_400_i10_3_lut (.A(RowA[9]), .B(MAin_c_9), .C(nRowColSel),
.Z(RA_c_9)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54])
defparam MAin_9__I_0_400_i10_3_lut.init = 16'hcaca;
ORCALUT4 i604_1_lut_rep_30 (.A(Ready), .Z(n2307)) /* synthesis lut_function=(!(A)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
defparam i604_1_lut_rep_30.init = 16'h5555;
FD1S3AX FS_577__i10 (.D(n85), .CK(RCLK_c), .Q(FS[10])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
defparam FS_577__i10.GSR = "ENABLED";
FD1S3AX FS_577__i9 (.D(n86), .CK(RCLK_c), .Q(FS[9])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
defparam FS_577__i9.GSR = "ENABLED";
FD1S3AX FS_577__i8 (.D(n87), .CK(RCLK_c), .Q(FS[8])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
defparam FS_577__i8.GSR = "ENABLED";
FD1S3AX FS_577__i7 (.D(n88), .CK(RCLK_c), .Q(FS[7])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
defparam FS_577__i7.GSR = "ENABLED";
FD1S3AX FS_577__i6 (.D(n89), .CK(RCLK_c), .Q(FS[6])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
defparam FS_577__i6.GSR = "ENABLED";
FD1S3AX FS_577__i5 (.D(n90), .CK(RCLK_c), .Q(FS[5])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
defparam FS_577__i5.GSR = "ENABLED";
FD1S3AX FS_577__i4 (.D(n91), .CK(RCLK_c), .Q(FS[4])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
defparam FS_577__i4.GSR = "ENABLED";
FD1S3AX FS_577__i3 (.D(n92), .CK(RCLK_c), .Q(FS[3])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
defparam FS_577__i3.GSR = "ENABLED";
FD1S3AX FS_577__i2 (.D(n93), .CK(RCLK_c), .Q(FS[2])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
defparam FS_577__i2.GSR = "ENABLED";
FD1S3AX FS_577__i1 (.D(n94), .CK(RCLK_c), .Q(FS[1])) /* synthesis syn_use_carry_chain=1 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
defparam FS_577__i1.GSR = "ENABLED";
FD1P3AX IS_FSM__i15 (.D(n699), .SP(RCLK_c_enable_23), .CK(RCLK_c),
.Q(Ready_N_272)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
defparam IS_FSM__i15.GSR = "ENABLED";
FD1P3AX IS_FSM__i14 (.D(n700), .SP(RCLK_c_enable_23), .CK(RCLK_c),
.Q(n699)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
defparam IS_FSM__i14.GSR = "ENABLED";
FD1P3AX IS_FSM__i13 (.D(n701), .SP(RCLK_c_enable_23), .CK(RCLK_c),
.Q(n700)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
defparam IS_FSM__i13.GSR = "ENABLED";
FD1P3AX IS_FSM__i12 (.D(n702), .SP(RCLK_c_enable_23), .CK(RCLK_c),
.Q(n701)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
defparam IS_FSM__i12.GSR = "ENABLED";
FD1P3AX IS_FSM__i11 (.D(n703), .SP(RCLK_c_enable_23), .CK(RCLK_c),
.Q(n702)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
defparam IS_FSM__i11.GSR = "ENABLED";
FD1P3AX IS_FSM__i10 (.D(nRWE_N_173), .SP(RCLK_c_enable_23), .CK(RCLK_c),
.Q(n703)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
defparam IS_FSM__i10.GSR = "ENABLED";
FD1P3AX IS_FSM__i9 (.D(n705), .SP(RCLK_c_enable_23), .CK(RCLK_c),
.Q(nRWE_N_173)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
defparam IS_FSM__i9.GSR = "ENABLED";
FD1P3AX IS_FSM__i8 (.D(n706), .SP(RCLK_c_enable_23), .CK(RCLK_c),
.Q(n705)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
defparam IS_FSM__i8.GSR = "ENABLED";
FD1P3AX IS_FSM__i7 (.D(n707), .SP(RCLK_c_enable_23), .CK(RCLK_c),
.Q(n706)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
defparam IS_FSM__i7.GSR = "ENABLED";
FD1P3AX IS_FSM__i6 (.D(n708), .SP(RCLK_c_enable_23), .CK(RCLK_c),
.Q(n707)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
defparam IS_FSM__i6.GSR = "ENABLED";
FD1P3AX IS_FSM__i5 (.D(n709), .SP(RCLK_c_enable_23), .CK(RCLK_c),
.Q(n708)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
defparam IS_FSM__i5.GSR = "ENABLED";
FD1P3AX IS_FSM__i4 (.D(n710), .SP(RCLK_c_enable_23), .CK(RCLK_c),
.Q(n709)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
defparam IS_FSM__i4.GSR = "ENABLED";
FD1P3AX IS_FSM__i3 (.D(n711), .SP(RCLK_c_enable_23), .CK(RCLK_c),
.Q(n710)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
defparam IS_FSM__i3.GSR = "ENABLED";
FD1P3AX IS_FSM__i2 (.D(nRCAS_N_161), .SP(RCLK_c_enable_23), .CK(RCLK_c),
.Q(n711)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
defparam IS_FSM__i2.GSR = "ENABLED";
FD1P3AX IS_FSM__i1 (.D(nRCS_N_135), .SP(RCLK_c_enable_23), .CK(RCLK_c),
.Q(nRCAS_N_161)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263[11:15])
defparam IS_FSM__i1.GSR = "ENABLED";
FD1S3IX RBA__i2 (.D(CROW_c_1), .CK(nCRAS_N_9), .CD(n2307), .Q(RBA_c_1)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
defparam RBA__i2.GSR = "ENABLED";
FD1S3AX WRD_i7 (.D(Din_c_7), .CK(nCCAS_N_3), .Q(WRD[7])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5])
defparam WRD_i7.GSR = "ENABLED";
FD1S3AX WRD_i6 (.D(Din_c_6), .CK(nCCAS_N_3), .Q(WRD[6])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5])
defparam WRD_i6.GSR = "ENABLED";
FD1S3AX WRD_i5 (.D(Din_c_5), .CK(nCCAS_N_3), .Q(WRD[5])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5])
defparam WRD_i5.GSR = "ENABLED";
FD1S3AX WRD_i4 (.D(Din_c_4), .CK(nCCAS_N_3), .Q(WRD[4])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5])
defparam WRD_i4.GSR = "ENABLED";
FD1S3AX WRD_i3 (.D(Din_c_3), .CK(nCCAS_N_3), .Q(WRD[3])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5])
defparam WRD_i3.GSR = "ENABLED";
FD1S3AX WRD_i2 (.D(Din_c_2), .CK(nCCAS_N_3), .Q(WRD[2])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5])
defparam WRD_i2.GSR = "ENABLED";
FD1S3AX WRD_i1 (.D(Din_c_1), .CK(nCCAS_N_3), .Q(WRD[1])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(123[9] 125[5])
defparam WRD_i1.GSR = "ENABLED";
FD1S3JX RowA_i9 (.D(MAin_c_9), .CK(nCRAS_N_9), .PD(n2307), .Q(RowA[9])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
defparam RowA_i9.GSR = "ENABLED";
FD1S3IX RowA_i8 (.D(MAin_c_8), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[8])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
defparam RowA_i8.GSR = "ENABLED";
FD1S3IX RowA_i7 (.D(MAin_c_7), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[7])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
defparam RowA_i7.GSR = "ENABLED";
FD1S3IX RowA_i6 (.D(MAin_c_6), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[6])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
defparam RowA_i6.GSR = "ENABLED";
FD1S3JX RowA_i5 (.D(MAin_c_5), .CK(nCRAS_N_9), .PD(n2307), .Q(RowA[5])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
defparam RowA_i5.GSR = "ENABLED";
FD1S3IX RowA_i4 (.D(MAin_c_4), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[4])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
defparam RowA_i4.GSR = "ENABLED";
FD1S3IX RowA_i3 (.D(MAin_c_3), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[3])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
defparam RowA_i3.GSR = "ENABLED";
FD1S3IX RowA_i2 (.D(MAin_c_2), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[2])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
defparam RowA_i2.GSR = "ENABLED";
FD1S3IX RowA_i1 (.D(MAin_c_1), .CK(nCRAS_N_9), .CD(n2307), .Q(RowA[1])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(105[9] 120[5])
defparam RowA_i1.GSR = "ENABLED";
FD1S3AX Bank_i7 (.D(Din_c_7), .CK(PHI2_c), .Q(Bank[7])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5])
defparam Bank_i7.GSR = "ENABLED";
ORCALUT4 i1_2_lut_rep_12 (.A(MAin_c_1), .B(n1285), .Z(n2289)) /* synthesis lut_function=((B)+!A) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(80[15:31])
defparam i1_2_lut_rep_12.init = 16'hdddd;
ORCALUT4 i1_2_lut_rep_15_3_lut_4_lut_4_lut (.A(nRowColSel_N_35), .B(nRCS_N_135),
.C(InitReady), .D(RASr2), .Z(n2292)) /* synthesis lut_function=((B+!(C (D)))+!A) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
defparam i1_2_lut_rep_15_3_lut_4_lut_4_lut.init = 16'hdfff;
ORCALUT4 i1_2_lut_4_lut_4_lut (.A(Ready), .B(nRowColSel_N_35), .C(RASr2),
.D(InitReady), .Z(RCLK_c_enable_23)) /* synthesis lut_function=(!(A+!(B (C (D))))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
defparam i1_2_lut_4_lut_4_lut.init = 16'h4000;
FD1S3AX Bank_i6 (.D(Din_c_6), .CK(PHI2_c), .Q(Bank[6])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5])
defparam Bank_i6.GSR = "ENABLED";
FD1S3AX Bank_i5 (.D(Din_c_5), .CK(PHI2_c), .Q(Bank[5])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5])
defparam Bank_i5.GSR = "ENABLED";
FD1S3AX Bank_i4 (.D(Din_c_4), .CK(PHI2_c), .Q(Bank[4])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5])
defparam Bank_i4.GSR = "ENABLED";
FD1S3AX Bank_i3 (.D(Din_c_3), .CK(PHI2_c), .Q(Bank[3])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5])
defparam Bank_i3.GSR = "ENABLED";
FD1S3AX Bank_i2 (.D(Din_c_2), .CK(PHI2_c), .Q(Bank[2])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5])
defparam Bank_i2.GSR = "ENABLED";
FD1S3AX Bank_i1 (.D(Din_c_1), .CK(PHI2_c), .Q(Bank[1])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(98[9] 102[5])
defparam Bank_i1.GSR = "ENABLED";
BB Dout_pad_6__689 (.I(WRD[6]), .T(n962), .B(RD[6]), .O(n974)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16])
BB Dout_pad_5__690 (.I(WRD[5]), .T(n962), .B(RD[5]), .O(n975)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16])
BB Dout_pad_4__691 (.I(WRD[4]), .T(n962), .B(RD[4]), .O(n976)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16])
BB Dout_pad_3__692 (.I(WRD[3]), .T(n962), .B(RD[3]), .O(n977)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16])
BB Dout_pad_2__693 (.I(WRD[2]), .T(n962), .B(RD[2]), .O(n978)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16])
BB Dout_pad_1__694 (.I(WRD[1]), .T(n962), .B(RD[1]), .O(n979)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16])
ORCALUT4 nRWE_I_49_1_lut (.A(nRWE_N_173), .Z(nRWE_N_172)) /* synthesis lut_function=(!(A)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(255[14] 262[8])
defparam nRWE_I_49_1_lut.init = 16'h5555;
BB Dout_pad_0__695 (.I(WRD[0]), .T(n962), .B(RD[0]), .O(Dout_c)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(60[14:16])
OB Dout_pad_7 (.I(n973), .O(Dout[7])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19])
OB Dout_pad_6 (.I(n974), .O(Dout[6])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19])
OB Dout_pad_5 (.I(n975), .O(Dout[5])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19])
OB Dout_pad_4 (.I(n976), .O(Dout[4])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19])
OB Dout_pad_3 (.I(n977), .O(Dout[3])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19])
OB Dout_pad_2 (.I(n978), .O(Dout[2])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19])
OB Dout_pad_1 (.I(n979), .O(Dout[1])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19])
OB Dout_pad_0 (.I(Dout_c), .O(Dout[0])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(27[15:19])
OB LED_pad (.I(LED_N_90), .O(LED)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(12[9:12])
OB RBA_pad_1 (.I(RBA_c_1), .O(RBA[1])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(47[19:22])
OB RBA_pad_0 (.I(RBA_c_0), .O(RBA[0])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(47[19:22])
OB RA_pad_11 (.I(RA_c), .O(RA[11])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
OB RA_pad_10 (.I(n980), .O(RA[10])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
OB RA_pad_9 (.I(RA_c_9), .O(RA[9])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
OB RA_pad_8 (.I(RA_c_8), .O(RA[8])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
OB RA_pad_7 (.I(RA_c_7), .O(RA[7])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
OB RA_pad_6 (.I(RA_c_6), .O(RA[6])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
OB RA_pad_5 (.I(RA_c_5), .O(RA[5])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
OB RA_pad_4 (.I(RA_c_4), .O(RA[4])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
OB RA_pad_3 (.I(RA_c_3), .O(RA[3])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
OB RA_pad_2 (.I(RA_c_2), .O(RA[2])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
OB RA_pad_1 (.I(RA_c_1), .O(RA[1])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
OB RA_pad_0 (.I(RA_c_0), .O(RA[0])); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(52[16:18])
OB nRCS_pad (.I(nRCS_c), .O(nRCS)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[13:17])
OB RCKE_pad (.I(RCKE_c), .O(RCKE)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(45[13:17])
OB nRWE_pad (.I(nRWE_c), .O(nRWE)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[45:49])
OB nRRAS_pad (.I(nRRAS_c), .O(nRRAS)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[23:28])
OB nRCAS_pad (.I(nRCAS_c), .O(nRCAS)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(46[34:39])
OB RDQMH_pad (.I(RDQMH_c), .O(RDQMH)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(56[16:21])
OB RDQML_pad (.I(RDQML_c), .O(RDQML)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(56[9:14])
OB nUFMCS_pad (.I(nUFMCS_c), .O(nUFMCS)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(63[13:19])
OB UFMCLK_pad (.I(UFMCLK_c), .O(UFMCLK)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(64[13:19])
OB UFMSDI_pad (.I(UFMSDI_c), .O(UFMSDI)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(65[13:19])
IB PHI2_pad (.I(PHI2), .O(PHI2_c)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(8[8:12])
IB MAin_pad_9 (.I(MAin[9]), .O(MAin_c_9)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18])
IB MAin_pad_8 (.I(MAin[8]), .O(MAin_c_8)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18])
IB MAin_pad_7 (.I(MAin[7]), .O(MAin_c_7)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18])
IB MAin_pad_6 (.I(MAin[6]), .O(MAin_c_6)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18])
IB MAin_pad_5 (.I(MAin[5]), .O(MAin_c_5)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18])
IB MAin_pad_4 (.I(MAin[4]), .O(MAin_c_4)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18])
IB MAin_pad_3 (.I(MAin[3]), .O(MAin_c_3)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18])
IB MAin_pad_2 (.I(MAin[2]), .O(MAin_c_2)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18])
IB MAin_pad_1 (.I(MAin[1]), .O(MAin_c_1)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18])
IB MAin_pad_0 (.I(MAin[0]), .O(MAin_c_0)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(35[14:18])
IB CROW_pad_1 (.I(CROW[1]), .O(CROW_c_1)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(34[14:18])
IB CROW_pad_0 (.I(CROW[0]), .O(CROW_c_0)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(34[14:18])
IB Din_pad_7 (.I(Din[7]), .O(Din_c_7)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17])
IB Din_pad_6 (.I(Din[6]), .O(Din_c_6)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17])
IB Din_pad_5 (.I(Din[5]), .O(Din_c_5)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17])
IB Din_pad_4 (.I(Din[4]), .O(Din_c_4)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17])
IB Din_pad_3 (.I(Din[3]), .O(Din_c_3)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17])
IB Din_pad_2 (.I(Din[2]), .O(Din_c_2)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17])
IB Din_pad_1 (.I(Din[1]), .O(Din_c_1)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17])
IB Din_pad_0 (.I(Din[0]), .O(Din_c_0)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(26[14:17])
IB nCCAS_pad (.I(nCCAS), .O(nCCAS_c)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[8:13])
IB nCRAS_pad (.I(nCRAS), .O(nCRAS_c)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[15:20])
IB nFWE_pad (.I(nFWE), .O(nFWE_c)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(36[8:12])
IB RCLK_pad (.I(RCLK), .O(RCLK_c)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(41[8:12])
IB UFMSDO_pad (.I(UFMSDO), .O(UFMSDO_c)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(66[8:14])
ORCALUT4 MAin_9__I_0_400_i9_3_lut (.A(RowA[8]), .B(MAin_c_8), .C(nRowColSel),
.Z(RA_c_8)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54])
defparam MAin_9__I_0_400_i9_3_lut.init = 16'hcaca;
CCU2 FS_577_add_4_4 (.A0(FS[2]), .B0(GND_net), .C0(GND_net), .D0(GND_net),
.A1(FS[3]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1874),
.COUT1(n1875), .S0(n93), .S1(n92)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
defparam FS_577_add_4_4.INIT0 = 16'hfaaa;
defparam FS_577_add_4_4.INIT1 = 16'hfaaa;
defparam FS_577_add_4_4.INJECT1_0 = "NO";
defparam FS_577_add_4_4.INJECT1_1 = "NO";
ORCALUT4 i1_2_lut_3_lut_4_lut_4_lut (.A(Ready), .B(nRowColSel_N_32),
.C(n1627), .D(nRowColSel_N_35), .Z(RCLK_c_enable_3)) /* synthesis lut_function=((B+(C+(D)))+!A) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
defparam i1_2_lut_3_lut_4_lut_4_lut.init = 16'hfffd;
FD1P3IX UFMCLK_389 (.D(UFMCLK_N_212), .SP(RCLK_c_enable_24), .CD(n2291),
.CK(RCLK_c), .Q(UFMCLK_c)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(327[9] 396[5])
defparam UFMCLK_389.GSR = "ENABLED";
ORCALUT4 i2_2_lut_rep_22_2_lut (.A(Ready), .B(nRowColSel_N_35), .Z(n2299)) /* synthesis lut_function=((B)+!A) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(147[9] 285[5])
defparam i2_2_lut_rep_22_2_lut.init = 16'hdddd;
ORCALUT4 i2_3_lut_4_lut_adj_20 (.A(n2297), .B(n2301), .C(nRCAS_N_161),
.D(Ready), .Z(n2128)) /* synthesis lut_function=(A+(B+(C+(D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
defparam i2_3_lut_4_lut_adj_20.init = 16'hfffe;
ORCALUT4 i2_3_lut_adj_21 (.A(nRowColSel_N_33), .B(nRRAS_c), .C(nRowColSel_N_32),
.Z(n50)) /* synthesis lut_function=(A+(B+(C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
defparam i2_3_lut_adj_21.init = 16'hfefe;
ORCALUT4 MAin_9__I_0_400_i8_3_lut (.A(RowA[7]), .B(MAin_c_7), .C(nRowColSel),
.Z(RA_c_7)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54])
defparam MAin_9__I_0_400_i8_3_lut.init = 16'hcaca;
ORCALUT4 Ready_bdd_4_lut (.A(Ready), .B(n2117), .C(n2287), .D(nRowColSel_N_35),
.Z(nRCAS_N_157)) /* synthesis lut_function=(A (B (C (D))+!B (C+!(D)))+!A (C+!(D))) */ ;
defparam Ready_bdd_4_lut.init = 16'hf077;
ORCALUT4 i1366_3_lut (.A(InitReady), .B(RCKEEN_N_116), .C(Ready),
.Z(RCKEEN_N_115)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(84[6:11])
defparam i1366_3_lut.init = 16'hcaca;
ORCALUT4 i6_4_lut (.A(FS[15]), .B(n12_adj_2), .C(FS[11]), .D(FS[17]),
.Z(n2076)) /* synthesis lut_function=(A (B (C (D)))) */ ;
defparam i6_4_lut.init = 16'h8000;
ORCALUT4 i1_4_lut_4_lut (.A(CBR), .B(n11_adj_3), .C(FWEr), .D(nRowColSel_N_34),
.Z(RCKEEN_N_117)) /* synthesis lut_function=(!(A+!(B (C+(D))+!B (D)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(214[26:30])
defparam i1_4_lut_4_lut.init = 16'h5540;
ORCALUT4 i1_2_lut_rep_11_3_lut (.A(nFWE_c), .B(n1285), .C(MAin_c_1),
.Z(PHI2_N_114_enable_1)) /* synthesis lut_function=(!(A+(B+!(C)))) */ ;
defparam i1_2_lut_rep_11_3_lut.init = 16'h1010;
CCU2 FS_577_add_4_2 (.A0(FS[0]), .B0(GND_net), .C0(GND_net), .D0(GND_net),
.A1(FS[1]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(GND_net),
.COUT1(n1874), .S0(n95), .S1(n94)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
defparam FS_577_add_4_2.INIT0 = 16'h0555;
defparam FS_577_add_4_2.INIT1 = 16'hfaaa;
defparam FS_577_add_4_2.INJECT1_0 = "NO";
defparam FS_577_add_4_2.INJECT1_1 = "NO";
ORCALUT4 i3_4_lut_adj_22 (.A(Din_c_0), .B(Din_c_1), .C(Din_c_4), .D(Din_c_7),
.Z(n2114)) /* synthesis lut_function=(!((B+(C+!(D)))+!A)) */ ;
defparam i3_4_lut_adj_22.init = 16'h0200;
ORCALUT4 Ready_bdd_4_lut_1960 (.A(nRowColSel_N_32), .B(RASr2), .C(Ready_N_272),
.D(InitReady), .Z(n2245)) /* synthesis lut_function=(!((B+!(C (D)))+!A)) */ ;
defparam Ready_bdd_4_lut_1960.init = 16'h2000;
ORCALUT4 n2245_bdd_2_lut (.A(n2245), .B(Ready), .Z(Ready_N_268)) /* synthesis lut_function=(A+(B)) */ ;
defparam n2245_bdd_2_lut.init = 16'heeee;
ORCALUT4 n2248_bdd_4_lut_4_lut (.A(CBR), .B(RASr2), .C(Ready), .D(n2248),
.Z(n2287)) /* synthesis lut_function=(!(A (B (C+!(D)))+!A !((C+(D))+!B))) */ ;
defparam n2248_bdd_4_lut_4_lut.init = 16'h7f73;
FD1P3AX LEDEN_392 (.D(UFMSDO_N_74), .SP(RCLK_c_enable_25), .CK(RCLK_c),
.Q(LEDEN)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(327[9] 396[5])
defparam LEDEN_392.GSR = "ENABLED";
ORCALUT4 MAin_9__I_0_400_i7_3_lut (.A(RowA[6]), .B(MAin_c_6), .C(nRowColSel),
.Z(RA_c_6)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54])
defparam MAin_9__I_0_400_i7_3_lut.init = 16'hcaca;
ORCALUT4 MAin_9__I_0_400_i6_3_lut (.A(RowA[5]), .B(MAin_c_5), .C(nRowColSel),
.Z(RA_c_5)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54])
defparam MAin_9__I_0_400_i6_3_lut.init = 16'hcaca;
CCU2 FS_577_add_4_12 (.A0(FS[10]), .B0(GND_net), .C0(GND_net), .D0(GND_net),
.A1(FS[11]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1878),
.COUT1(n1879), .S0(n85), .S1(n84)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
defparam FS_577_add_4_12.INIT0 = 16'hfaaa;
defparam FS_577_add_4_12.INIT1 = 16'hfaaa;
defparam FS_577_add_4_12.INJECT1_0 = "NO";
defparam FS_577_add_4_12.INJECT1_1 = "NO";
FD1P3AX CmdEnable_378 (.D(CmdEnable_N_236), .SP(PHI2_N_114_enable_8),
.CK(PHI2_N_114), .Q(CmdEnable)) /* synthesis lse_init_val=0 */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(288[9] 324[5])
defparam CmdEnable_378.GSR = "ENABLED";
CCU2 FS_577_add_4_16 (.A0(FS[14]), .B0(GND_net), .C0(GND_net), .D0(GND_net),
.A1(FS[15]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1880),
.COUT1(n1881), .S0(n81), .S1(n80)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
defparam FS_577_add_4_16.INIT0 = 16'hfaaa;
defparam FS_577_add_4_16.INIT1 = 16'hfaaa;
defparam FS_577_add_4_16.INJECT1_0 = "NO";
defparam FS_577_add_4_16.INJECT1_1 = "NO";
CCU2 FS_577_add_4_14 (.A0(FS[12]), .B0(GND_net), .C0(GND_net), .D0(GND_net),
.A1(FS[13]), .B1(GND_net), .C1(GND_net), .D1(GND_net), .CIN(n1879),
.COUT1(n1880), .S0(n83), .S1(n82)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136[9:13])
defparam FS_577_add_4_14.INIT0 = 16'hfaaa;
defparam FS_577_add_4_14.INIT1 = 16'hfaaa;
defparam FS_577_add_4_14.INJECT1_0 = "NO";
defparam FS_577_add_4_14.INJECT1_1 = "NO";
ORCALUT4 MAin_9__I_0_400_i3_3_lut (.A(RowA[2]), .B(MAin_c_2), .C(nRowColSel),
.Z(RA_c_2)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54])
defparam MAin_9__I_0_400_i3_3_lut.init = 16'hcaca;
ORCALUT4 i1485_3_lut (.A(n2076), .B(n1369), .C(InitReady), .Z(n1348)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(83[6:15])
defparam i1485_3_lut.init = 16'hcaca;
ORCALUT4 i1_2_lut_2_lut (.A(nRowColSel_N_35), .B(nRowColSel_N_34), .Z(n18)) /* synthesis lut_function=(!(A+!(B))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
defparam i1_2_lut_2_lut.init = 16'h4444;
ORCALUT4 i1_2_lut_rep_20_2_lut (.A(nRowColSel_N_35), .B(nRCS_N_135),
.Z(n2297)) /* synthesis lut_function=((B)+!A) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
defparam i1_2_lut_rep_20_2_lut.init = 16'hdddd;
ORCALUT4 i1062_3_lut (.A(nUFMCS_c), .B(CmdUFMCS), .C(n2308), .Z(n1369)) /* synthesis lut_function=(!(A (B (C))+!A (B+!(C)))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(327[9] 396[5])
defparam i1062_3_lut.init = 16'h3a3a;
ORCALUT4 MAin_9__I_0_400_i4_3_lut (.A(RowA[3]), .B(MAin_c_3), .C(nRowColSel),
.Z(RA_c_3)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54])
defparam MAin_9__I_0_400_i4_3_lut.init = 16'hcaca;
ORCALUT4 MAin_9__I_0_400_i1_3_lut (.A(RowA[0]), .B(MAin_c_0), .C(nRowColSel),
.Z(RA_c_0)) /* synthesis lut_function=(A (B+!(C))+!A (B (C))) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(55[19:54])
defparam MAin_9__I_0_400_i1_3_lut.init = 16'hcaca;
INV i1961 (.A(nCRAS_c), .Z(nCRAS_N_9)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(16[15:20])
INV i1962 (.A(PHI2_c), .Z(PHI2_N_114)); // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(8[8:12])
VLO i1 (.Z(GND_net));
TSALL TSALL_INST (.TSALL(GND_net));
ORCALUT4 i1070_1_lut_rep_25 (.A(nRowColSel_N_35), .Z(n2302)) /* synthesis lut_function=(!(A)) */ ; // c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131[13:16])
defparam i1070_1_lut_rep_25.init = 16'h5555;
PUR PUR_INST (.PUR(VCC_net));
defparam PUR_INST.RST_PULSE = 1;
ORCALUT4 i13_4_lut (.A(Bank[3]), .B(n26), .C(n2170), .D(MAin_c_5),
.Z(n1285)) /* synthesis lut_function=((B+!(C (D)))+!A) */ ;
defparam i13_4_lut.init = 16'hdfff;
ORCALUT4 i12_4_lut (.A(Bank[2]), .B(n2166), .C(n2154), .D(MAin_c_6),
.Z(n26)) /* synthesis lut_function=(A+!(B (C (D)))) */ ;
defparam i12_4_lut.init = 16'hbfff;
ORCALUT4 i1860_4_lut (.A(MAin_c_7), .B(MAin_c_3), .C(Bank[4]), .D(Bank[1]),
.Z(n2170)) /* synthesis lut_function=(A (B (C (D)))) */ ;
defparam i1860_4_lut.init = 16'h8000;
ORCALUT4 m0_lut (.Z(n2386)) /* synthesis lut_function=0, syn_instantiated=1 */ ;
defparam m0_lut.init = 16'h0000;
PFUMX i1934 (.BLUT(n2309), .ALUT(n2310), .C0(Ready), .Z(nRCS_N_132));
endmodule
//
// Verilog Description of module TSALL
// module not written out since it is a black-box.
//
//
// Verilog Description of module PUR
// module not written out since it is a black-box.
//

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PERIOD NET "PHI2_c" 350.000000 ns ;
PERIOD NET "nCCAS_c" 350.000000 ns ;
PERIOD NET "nCRAS_c" 350.000000 ns ;
PERIOD NET "RCLK_c" 15.000000 ns ;
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
OUTPUT PORT "RD[7]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[0]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[1]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[2]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[3]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[4]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[5]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[6]" LOAD 20.000000 pF ;
OUTPUT PORT "nUFMCS" LOAD 15.000000 pF ;
OUTPUT PORT "UFMCLK" LOAD 15.000000 pF ;
OUTPUT PORT "UFMSDI" LOAD 15.000000 pF ;
OUTPUT PORT "nRWE" LOAD 10.000000 pF ;
OUTPUT PORT "nRCAS" LOAD 10.000000 pF ;
OUTPUT PORT "nRCS" LOAD 10.000000 pF ;
OUTPUT PORT "nRRAS" LOAD 10.000000 pF ;
OUTPUT PORT "RDQML" LOAD 10.000000 pF ;
OUTPUT PORT "RDQMH" LOAD 10.000000 pF ;
OUTPUT PORT "RCKE" LOAD 10.000000 pF ;
OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ;
OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[11]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[10]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[9]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[8]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[7]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[6]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[5]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[4]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[3]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[2]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[1]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[0]" LOAD 10.000000 pF ;
OUTPUT PORT "LED" LOAD 25.000000 pF ;
OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ;
VOLTAGE 3.300 V;
VCCIO_DERATE BANK 0 PERCENT -5;
VCCIO_DERATE PERCENT -5;
VCCIO_DERATE BANK 1 PERCENT -5;
CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
COMMERCIAL ;

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VOLTAGE 3.300 V;
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
IOBUF PORT "RD[7]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RD[6]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RD[5]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RD[4]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RD[3]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RD[2]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RD[1]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RD[0]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "Dout[7]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "Dout[6]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "Dout[5]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "Dout[4]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "Dout[3]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "Dout[2]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "Dout[1]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "Dout[0]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "LED" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RBA[1]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RBA[0]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RA[11]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RA[10]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RA[9]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RA[8]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RA[7]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RA[6]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RA[5]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RA[4]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RA[3]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RA[2]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RA[1]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RA[0]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "nRCS" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RCKE" IO_TYPE=LVCMOS25 ;
IOBUF PORT "nRWE" IO_TYPE=LVCMOS25 ;
IOBUF PORT "nRRAS" IO_TYPE=LVCMOS25 ;
IOBUF PORT "nRCAS" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RDQMH" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RDQML" IO_TYPE=LVCMOS25 ;
IOBUF PORT "nUFMCS" IO_TYPE=LVCMOS25 ;
IOBUF PORT "UFMCLK" IO_TYPE=LVCMOS25 ;
IOBUF PORT "UFMSDI" IO_TYPE=LVCMOS25 ;
IOBUF PORT "PHI2" IO_TYPE=LVCMOS25 ;
IOBUF PORT "MAin[9]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "MAin[8]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "MAin[7]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "MAin[6]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "MAin[5]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "MAin[4]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "MAin[3]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "MAin[2]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "MAin[1]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "MAin[0]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "CROW[1]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "CROW[0]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "Din[7]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "Din[6]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "Din[5]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "Din[4]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "Din[3]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "Din[2]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "Din[1]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "Din[0]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "nCCAS" IO_TYPE=LVCMOS25 ;
IOBUF PORT "nCRAS" IO_TYPE=LVCMOS25 ;
IOBUF PORT "nFWE" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RCLK" IO_TYPE=LVCMOS25 ;
IOBUF PORT "UFMSDO" IO_TYPE=LVCMOS25 ;
PERIOD NET "PHI2_c" 350.000000 ns ;
PERIOD NET "nCCAS_c" 350.000000 ns ;
PERIOD NET "nCRAS_c" 350.000000 ns ;
PERIOD NET "RCLK_c" 15.000000 ns ;
CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
OUTPUT PORT "RD[7]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[0]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[1]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[2]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[3]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[4]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[5]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[6]" LOAD 20.000000 pF ;
OUTPUT PORT "nUFMCS" LOAD 15.000000 pF ;
OUTPUT PORT "UFMCLK" LOAD 15.000000 pF ;
OUTPUT PORT "UFMSDI" LOAD 15.000000 pF ;
OUTPUT PORT "nRWE" LOAD 10.000000 pF ;
OUTPUT PORT "nRCAS" LOAD 10.000000 pF ;
OUTPUT PORT "nRCS" LOAD 10.000000 pF ;
OUTPUT PORT "nRRAS" LOAD 10.000000 pF ;
OUTPUT PORT "RDQML" LOAD 10.000000 pF ;
OUTPUT PORT "RDQMH" LOAD 10.000000 pF ;
OUTPUT PORT "RCKE" LOAD 10.000000 pF ;
OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ;
OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[11]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[10]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[9]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[8]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[7]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[6]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[5]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[4]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[3]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[2]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[1]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[0]" LOAD 10.000000 pF ;
OUTPUT PORT "LED" LOAD 25.000000 pF ;
OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ;
VCCIO_DERATE BANK 0 PERCENT -5;
VCCIO_DERATE PERCENT -5;
VCCIO_DERATE BANK 1 PERCENT -5;

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@ -0,0 +1,88 @@
PERIOD NET "PHI2_c" 350.000000 ns ;
PERIOD NET "nCCAS_c" 350.000000 ns ;
PERIOD NET "nCRAS_c" 350.000000 ns ;
PERIOD NET "RCLK_c" 15.000000 ns ;
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
OUTPUT PORT "RD[7]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[0]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[1]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[2]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[3]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[4]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[5]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[6]" LOAD 20.000000 pF ;
OUTPUT PORT "nUFMCS" LOAD 15.000000 pF ;
OUTPUT PORT "UFMCLK" LOAD 15.000000 pF ;
OUTPUT PORT "UFMSDI" LOAD 15.000000 pF ;
OUTPUT PORT "nRWE" LOAD 10.000000 pF ;
OUTPUT PORT "nRCAS" LOAD 10.000000 pF ;
OUTPUT PORT "nRCS" LOAD 10.000000 pF ;
OUTPUT PORT "nRRAS" LOAD 10.000000 pF ;
OUTPUT PORT "RDQML" LOAD 10.000000 pF ;
OUTPUT PORT "RDQMH" LOAD 10.000000 pF ;
OUTPUT PORT "RCKE" LOAD 10.000000 pF ;
OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ;
OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[11]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[10]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[9]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[8]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[7]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[6]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[5]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[4]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[3]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[2]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[1]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[0]" LOAD 10.000000 pF ;
OUTPUT PORT "LED" LOAD 25.000000 pF ;
OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ;
VOLTAGE 3.300 V;
VCCIO_DERATE BANK 0 PERCENT -5;
VCCIO_DERATE PERCENT -5;
VCCIO_DERATE BANK 1 PERCENT -5;
CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;

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@ -0,0 +1,155 @@
VOLTAGE 3.300 V;
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
IOBUF PORT "RD[7]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RD[6]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RD[5]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RD[4]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RD[3]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RD[2]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RD[1]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RD[0]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "Dout[7]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "Dout[6]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "Dout[5]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "Dout[4]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "Dout[3]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "Dout[2]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "Dout[1]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "Dout[0]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "LED" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RBA[1]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RBA[0]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RA[11]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RA[10]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RA[9]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RA[8]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RA[7]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RA[6]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RA[5]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RA[4]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RA[3]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RA[2]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RA[1]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RA[0]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "nRCS" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RCKE" IO_TYPE=LVCMOS25 ;
IOBUF PORT "nRWE" IO_TYPE=LVCMOS25 ;
IOBUF PORT "nRRAS" IO_TYPE=LVCMOS25 ;
IOBUF PORT "nRCAS" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RDQMH" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RDQML" IO_TYPE=LVCMOS25 ;
IOBUF PORT "nUFMCS" IO_TYPE=LVCMOS25 ;
IOBUF PORT "UFMCLK" IO_TYPE=LVCMOS25 ;
IOBUF PORT "UFMSDI" IO_TYPE=LVCMOS25 ;
IOBUF PORT "PHI2" IO_TYPE=LVCMOS25 ;
IOBUF PORT "MAin[9]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "MAin[8]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "MAin[7]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "MAin[6]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "MAin[5]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "MAin[4]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "MAin[3]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "MAin[2]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "MAin[1]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "MAin[0]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "CROW[1]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "CROW[0]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "Din[7]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "Din[6]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "Din[5]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "Din[4]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "Din[3]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "Din[2]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "Din[1]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "Din[0]" IO_TYPE=LVCMOS25 ;
IOBUF PORT "nCCAS" IO_TYPE=LVCMOS25 ;
IOBUF PORT "nCRAS" IO_TYPE=LVCMOS25 ;
IOBUF PORT "nFWE" IO_TYPE=LVCMOS25 ;
IOBUF PORT "RCLK" IO_TYPE=LVCMOS25 ;
IOBUF PORT "UFMSDO" IO_TYPE=LVCMOS25 ;
PERIOD NET "PHI2_c" 350.000000 ns ;
PERIOD NET "nCCAS_c" 350.000000 ns ;
PERIOD NET "nCRAS_c" 350.000000 ns ;
PERIOD NET "RCLK_c" 15.000000 ns ;
CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
OUTPUT PORT "RD[7]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[0]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[1]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[2]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[3]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[4]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[5]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[6]" LOAD 20.000000 pF ;
OUTPUT PORT "nUFMCS" LOAD 15.000000 pF ;
OUTPUT PORT "UFMCLK" LOAD 15.000000 pF ;
OUTPUT PORT "UFMSDI" LOAD 15.000000 pF ;
OUTPUT PORT "nRWE" LOAD 10.000000 pF ;
OUTPUT PORT "nRCAS" LOAD 10.000000 pF ;
OUTPUT PORT "nRCS" LOAD 10.000000 pF ;
OUTPUT PORT "nRRAS" LOAD 10.000000 pF ;
OUTPUT PORT "RDQML" LOAD 10.000000 pF ;
OUTPUT PORT "RDQMH" LOAD 10.000000 pF ;
OUTPUT PORT "RCKE" LOAD 10.000000 pF ;
OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ;
OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[11]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[10]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[9]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[8]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[7]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[6]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[5]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[4]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[3]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[2]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[1]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[0]" LOAD 10.000000 pF ;
OUTPUT PORT "LED" LOAD 25.000000 pF ;
OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ;
VCCIO_DERATE BANK 0 PERCENT -5;
VCCIO_DERATE PERCENT -5;
VCCIO_DERATE BANK 1 PERCENT -5;

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

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@ -0,0 +1,528 @@
ibisgen "RAM2GS_LCMXO256C_impl1.pad" "C:/lscc/diamond/3.12/cae_library/ibis/machxo.ibs"
IBIS Models Generator: Lattice Diamond (64-bit) 3.12.0.240.2
Mon Aug 16 21:36:25 2021
Comp: CROW[0]
Site: 32
Type: IN
IO_TYPE=LVTTL33
SLEW=FAST
-----------------------
Comp: CROW[1]
Site: 34
Type: IN
IO_TYPE=LVTTL33
SLEW=FAST
-----------------------
Comp: Din[0]
Site: 21
Type: IN
IO_TYPE=LVTTL33
SLEW=FAST
-----------------------
Comp: Din[1]
Site: 15
Type: IN
IO_TYPE=LVTTL33
SLEW=FAST
-----------------------
Comp: Din[2]
Site: 14
Type: IN
IO_TYPE=LVTTL33
SLEW=FAST
-----------------------
Comp: Din[3]
Site: 16
Type: IN
IO_TYPE=LVTTL33
SLEW=FAST
-----------------------
Comp: Din[4]
Site: 18
Type: IN
IO_TYPE=LVTTL33
SLEW=FAST
-----------------------
Comp: Din[5]
Site: 17
Type: IN
IO_TYPE=LVTTL33
SLEW=FAST
-----------------------
Comp: Din[6]
Site: 20
Type: IN
IO_TYPE=LVTTL33
SLEW=FAST
-----------------------
Comp: Din[7]
Site: 19
Type: IN
IO_TYPE=LVTTL33
SLEW=FAST
-----------------------
Comp: Dout[0]
Site: 1
Type: OUT
IO_TYPE=LVTTL33
DRIVE=4mA
SLEW=SLOW
-----------------------
Comp: Dout[1]
Site: 7
Type: OUT
IO_TYPE=LVTTL33
DRIVE=4mA
SLEW=SLOW
-----------------------
Comp: Dout[2]
Site: 8
Type: OUT
IO_TYPE=LVTTL33
DRIVE=4mA
SLEW=SLOW
-----------------------
Comp: Dout[3]
Site: 6
Type: OUT
IO_TYPE=LVTTL33
DRIVE=4mA
SLEW=SLOW
-----------------------
Comp: Dout[4]
Site: 4
Type: OUT
IO_TYPE=LVTTL33
DRIVE=4mA
SLEW=SLOW
-----------------------
Comp: Dout[5]
Site: 5
Type: OUT
IO_TYPE=LVTTL33
DRIVE=4mA
SLEW=SLOW
-----------------------
Comp: Dout[6]
Site: 2
Type: OUT
IO_TYPE=LVTTL33
DRIVE=4mA
SLEW=SLOW
-----------------------
Comp: Dout[7]
Site: 3
Type: OUT
IO_TYPE=LVTTL33
DRIVE=4mA
SLEW=SLOW
-----------------------
Comp: LED
Site: 57
Type: OUT
IO_TYPE=LVTTL33
DRIVE=16mA
SLEW=SLOW
-----------------------
Comp: MAin[0]
Site: 23
Type: IN
IO_TYPE=LVTTL33
SLEW=FAST
-----------------------
Comp: MAin[1]
Site: 38
Type: IN
IO_TYPE=LVTTL33
SLEW=FAST
-----------------------
Comp: MAin[2]
Site: 37
Type: IN
IO_TYPE=LVTTL33
SLEW=FAST
-----------------------
Comp: MAin[3]
Site: 47
Type: IN
IO_TYPE=LVTTL33
SLEW=FAST
-----------------------
Comp: MAin[4]
Site: 46
Type: IN
IO_TYPE=LVTTL33
SLEW=FAST
-----------------------
Comp: MAin[5]
Site: 45
Type: IN
IO_TYPE=LVTTL33
SLEW=FAST
-----------------------
Comp: MAin[6]
Site: 49
Type: IN
IO_TYPE=LVTTL33
SLEW=FAST
-----------------------
Comp: MAin[7]
Site: 44
Type: IN
IO_TYPE=LVTTL33
SLEW=FAST
-----------------------
Comp: MAin[8]
Site: 50
Type: IN
IO_TYPE=LVTTL33
SLEW=FAST
-----------------------
Comp: MAin[9]
Site: 51
Type: IN
IO_TYPE=LVTTL33
SLEW=FAST
-----------------------
Comp: PHI2
Site: 39
Type: IN
IO_TYPE=LVTTL33
SLEW=FAST
-----------------------
Comp: RA[0]
Site: 98
Type: OUT
IO_TYPE=LVTTL33
DRIVE=4mA
SLEW=SLOW
-----------------------
Comp: RA[10]
Site: 87
Type: OUT
IO_TYPE=LVTTL33
DRIVE=4mA
SLEW=SLOW
-----------------------
Comp: RA[11]
Site: 79
Type: OUT
IO_TYPE=LVTTL33
DRIVE=4mA
SLEW=SLOW
-----------------------
Comp: RA[1]
Site: 89
Type: OUT
IO_TYPE=LVTTL33
DRIVE=4mA
SLEW=SLOW
-----------------------
Comp: RA[2]
Site: 94
Type: OUT
IO_TYPE=LVTTL33
DRIVE=4mA
SLEW=SLOW
-----------------------
Comp: RA[3]
Site: 97
Type: OUT
IO_TYPE=LVTTL33
DRIVE=4mA
SLEW=SLOW
-----------------------
Comp: RA[4]
Site: 99
Type: OUT
IO_TYPE=LVTTL33
DRIVE=4mA
SLEW=SLOW
-----------------------
Comp: RA[5]
Site: 95
Type: OUT
IO_TYPE=LVTTL33
DRIVE=4mA
SLEW=SLOW
-----------------------
Comp: RA[6]
Site: 91
Type: OUT
IO_TYPE=LVTTL33
DRIVE=4mA
SLEW=SLOW
-----------------------
Comp: RA[7]
Site: 100
Type: OUT
IO_TYPE=LVTTL33
DRIVE=4mA
SLEW=SLOW
-----------------------
Comp: RA[8]
Site: 96
Type: OUT
IO_TYPE=LVTTL33
DRIVE=4mA
SLEW=SLOW
-----------------------
Comp: RA[9]
Site: 85
Type: OUT
IO_TYPE=LVTTL33
DRIVE=4mA
SLEW=SLOW
-----------------------
Comp: RBA[0]
Site: 63
Type: OUT
IO_TYPE=LVTTL33
DRIVE=4mA
SLEW=SLOW
-----------------------
Comp: RBA[1]
Site: 83
Type: OUT
IO_TYPE=LVTTL33
DRIVE=4mA
SLEW=SLOW
-----------------------
Comp: RCKE
Site: 82
Type: OUT
IO_TYPE=LVTTL33
DRIVE=4mA
SLEW=SLOW
-----------------------
Comp: RCLK
Site: 86
Type: IN
IO_TYPE=LVTTL33
SLEW=FAST
-----------------------
Comp: RDQMH
Site: 76
Type: OUT
IO_TYPE=LVTTL33
DRIVE=4mA
SLEW=SLOW
-----------------------
Comp: RDQML
Site: 61
Type: OUT
IO_TYPE=LVTTL33
DRIVE=4mA
SLEW=SLOW
-----------------------
Comp: RD[0]
Site: 64
Type: BIDI
IO_TYPE=LVTTL33
DRIVE=4mA
SLEW=SLOW
PULL=KEEPER
-----------------------
Comp: RD[1]
Site: 65
Type: BIDI
IO_TYPE=LVTTL33
DRIVE=4mA
SLEW=SLOW
PULL=KEEPER
-----------------------
Comp: RD[2]
Site: 66
Type: BIDI
IO_TYPE=LVTTL33
DRIVE=4mA
SLEW=SLOW
PULL=KEEPER
-----------------------
Comp: RD[3]
Site: 67
Type: BIDI
IO_TYPE=LVTTL33
DRIVE=4mA
SLEW=SLOW
PULL=KEEPER
-----------------------
Comp: RD[4]
Site: 68
Type: BIDI
IO_TYPE=LVTTL33
DRIVE=4mA
SLEW=SLOW
PULL=KEEPER
-----------------------
Comp: RD[5]
Site: 69
Type: BIDI
IO_TYPE=LVTTL33
DRIVE=4mA
SLEW=SLOW
PULL=KEEPER
-----------------------
Comp: RD[6]
Site: 70
Type: BIDI
IO_TYPE=LVTTL33
DRIVE=4mA
SLEW=SLOW
PULL=KEEPER
-----------------------
Comp: RD[7]
Site: 71
Type: BIDI
IO_TYPE=LVTTL33
DRIVE=4mA
SLEW=SLOW
PULL=KEEPER
-----------------------
Comp: UFMCLK
Site: 58
Type: OUT
IO_TYPE=LVTTL33
DRIVE=4mA
SLEW=SLOW
-----------------------
Comp: UFMSDI
Site: 56
Type: OUT
IO_TYPE=LVTTL33
DRIVE=4mA
SLEW=SLOW
-----------------------
Comp: UFMSDO
Site: 55
Type: IN
IO_TYPE=LVTTL33
SLEW=FAST
PULL=KEEPER
-----------------------
Comp: nCCAS
Site: 27
Type: IN
IO_TYPE=LVTTL33
SLEW=FAST
-----------------------
Comp: nCRAS
Site: 43
Type: IN
IO_TYPE=LVTTL33
SLEW=FAST
-----------------------
Comp: nFWE
Site: 22
Type: IN
IO_TYPE=LVTTL33
SLEW=FAST
-----------------------
Comp: nRCAS
Site: 78
Type: OUT
IO_TYPE=LVTTL33
DRIVE=4mA
SLEW=SLOW
-----------------------
Comp: nRCS
Site: 77
Type: OUT
IO_TYPE=LVTTL33
DRIVE=4mA
SLEW=SLOW
-----------------------
Comp: nRRAS
Site: 73
Type: OUT
IO_TYPE=LVTTL33
DRIVE=4mA
SLEW=SLOW
-----------------------
Comp: nRWE
Site: 72
Type: OUT
IO_TYPE=LVTTL33
DRIVE=4mA
SLEW=SLOW
-----------------------
Comp: nUFMCS
Site: 53
Type: OUT
IO_TYPE=LVTTL33
DRIVE=4mA
SLEW=SLOW
-----------------------
Created design models.
Generating: C:\Users\Dog\Documents\GitHub\RAM2GS\CPLD\LCMXO\LCMXO256C\impl1\IBIS\RAM2GS_LCMXO256C_im~.ibs
<postMsg mid="1191031" type="Info" dynamic="0" navigation="0" />
tmcheck -par "RAM2GS_LCMXO256C_impl1.par"
bitgen -w "RAM2GS_LCMXO256C_impl1.ncd" -f "RAM2GS_LCMXO256C_impl1.t2b" "RAM2GS_LCMXO256C_impl1.prf"
BITGEN: Bitstream Generator Diamond (64-bit) 3.12.0.240.2
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Loading design for application Bitgen from file RAM2GS_LCMXO256C_impl1.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO256C
Package: TQFP100
Performance: 3
Loading device for application Bitgen from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.19.
Performance Hardware Data Status: Version 1.124.
Running DRC.
DRC detected 0 errors and 0 warnings.
Reading Preference File from RAM2GS_LCMXO256C_impl1.prf.
Preference Summary:
+---------------------------------+---------------------------------+
| Preference | Current Setting |
+---------------------------------+---------------------------------+
| CONFIG_SECURE | OFF** |
+---------------------------------+---------------------------------+
| INBUF | ON** |
+---------------------------------+---------------------------------+
| ES | No** |
+---------------------------------+---------------------------------+
* Default setting.
** The specified setting matches the default setting.
Creating bit map...
Saving bit stream in "RAM2GS_LCMXO256C_impl1.bit".
Total CPU Time: 0 secs
Total REAL Time: 0 secs
Peak Memory Usage: 44 MB
ddtcmd -dev LCMXO256C-XXT100 -if "RAM2GS_LCMXO256C_impl1.bit" -oft -jed -of "RAM2GS_LCMXO256C_impl1.jed" -comment "RAM2GS_LCMXO256C_impl1.alt"
Lattice Diamond Deployment Tool 3.12 Command Line
Loading Programmer Device Database...
Generating JED.....
Device Name: LCMXO256C-XXT100
Reading Input File: RAM2GS_LCMXO256C_impl1.bit
Output File: RAM2GS_LCMXO256C_impl1.jed
Comment file RAM2GS_LCMXO256C_impl1.alt.
Generating JEDEC.....
File RAM2GS_LCMXO256C_impl1.jed generated successfully.
Lattice Diamond Deployment Tool has exited successfully.

File diff suppressed because one or more lines are too long

View File

@ -0,0 +1,137 @@
Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO256C
Package: TQFP100
Performance: 4
Package Status: Final Version 1.19.
Performance Hardware Data Status: Version 1.124.
Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO256C
Package: TQFP100
Performance: 5
Package Status: Final Version 1.19.
Performance Hardware Data Status: Version 1.124.
Loading design for application iotiming from file ram2gs_lcmxo256c_impl1.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO256C
Package: TQFP100
Performance: M
Package Status: Final Version 1.19.
Performance Hardware Data Status: Version 1.124.
// Design: RAM2GS
// Package: TQFP100
// ncd File: ram2gs_lcmxo256c_impl1.ncd
// Version: Diamond (64-bit) 3.12.0.240.2
// Written on Mon Aug 16 21:32:34 2021
// M: Minimum Performance Grade
// iotiming RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml
I/O Timing Report (All units are in ns)
Worst Case Results across Performance Grades (M, 5, 4, 3):
// Input Setup and Hold Times
Port Clock Edge Setup Performance_Grade Hold Performance_Grade
----------------------------------------------------------------------
CROW[0] nCRAS F 0.215 3 1.805 3
CROW[1] nCRAS F -0.050 M 2.105 3
Din[0] PHI2 F 5.083 3 2.097 3
Din[0] nCCAS F -0.020 M 2.133 3
Din[1] PHI2 F 3.519 3 2.454 3
Din[1] nCCAS F -0.146 M 2.462 3
Din[2] PHI2 F 4.416 3 2.660 3
Din[2] nCCAS F 0.272 3 1.853 3
Din[3] PHI2 F 5.627 3 2.084 3
Din[3] nCCAS F -0.024 M 2.144 3
Din[4] PHI2 F 4.808 3 2.117 3
Din[4] nCCAS F 0.350 3 1.766 3
Din[5] PHI2 F 5.446 3 2.212 3
Din[5] nCCAS F 0.435 3 1.708 3
Din[6] PHI2 F 5.339 3 1.487 3
Din[6] nCCAS F -0.140 M 2.452 3
Din[7] PHI2 F 4.546 3 1.555 3
Din[7] nCCAS F -0.016 M 2.122 3
MAin[0] PHI2 F 4.027 3 0.711 3
MAin[0] nCRAS F 1.132 3 0.987 3
MAin[1] PHI2 F 4.032 3 1.734 3
MAin[1] nCRAS F 0.704 3 1.373 3
MAin[2] PHI2 F 10.358 3 -0.773 M
MAin[2] nCRAS F -0.202 M 2.529 3
MAin[3] PHI2 F 10.442 3 -0.829 M
MAin[3] nCRAS F 0.186 3 1.819 3
MAin[4] PHI2 F 10.311 3 -0.765 M
MAin[4] nCRAS F 0.569 3 1.506 3
MAin[5] PHI2 F 7.007 3 0.178 3
MAin[5] nCRAS F 0.186 3 1.819 3
MAin[6] PHI2 F 9.786 3 -0.641 M
MAin[6] nCRAS F 0.177 3 1.829 3
MAin[7] PHI2 F 10.008 3 -0.718 M
MAin[7] nCRAS F -0.092 M 2.222 3
MAin[8] nCRAS F -0.202 M 2.532 3
MAin[9] nCRAS F 0.228 3 1.797 3
PHI2 RCLK R 5.091 3 -0.759 M
UFMSDO RCLK R 2.219 3 -0.104 M
nCCAS RCLK R 3.820 3 -0.611 M
nCCAS nCRAS F 1.538 3 0.708 3
nCRAS RCLK R 4.749 3 -0.670 M
nFWE PHI2 F 5.301 3 1.647 3
nFWE nCRAS F 1.049 3 1.128 3
// Clock to Output Delay
Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
------------------------------------------------------------------------
LED RCLK R 11.669 3 3.051 M
RA[0] RCLK R 9.674 3 2.492 M
RA[0] nCRAS F 12.127 3 3.067 M
RA[10] RCLK R 8.596 3 2.220 M
RA[11] PHI2 R 9.987 3 2.559 M
RA[1] RCLK R 8.766 3 2.284 M
RA[1] nCRAS F 11.652 3 2.982 M
RA[2] RCLK R 10.062 3 2.599 M
RA[2] nCRAS F 12.947 3 3.306 M
RA[3] RCLK R 9.933 3 2.555 M
RA[3] nCRAS F 12.783 3 3.240 M
RA[4] RCLK R 8.504 3 2.219 M
RA[4] nCRAS F 11.513 3 2.948 M
RA[5] RCLK R 9.609 3 2.481 M
RA[5] nCRAS F 11.870 3 3.010 M
RA[6] RCLK R 10.001 3 2.579 M
RA[6] nCRAS F 12.947 3 3.292 M
RA[7] RCLK R 10.255 3 2.652 M
RA[7] nCRAS F 12.177 3 3.089 M
RA[8] RCLK R 8.896 3 2.316 M
RA[8] nCRAS F 11.417 3 2.920 M
RA[9] RCLK R 8.766 3 2.284 M
RA[9] nCRAS F 11.617 3 2.957 M
RBA[0] nCRAS F 9.698 3 2.483 M
RBA[1] nCRAS F 11.425 3 2.916 M
RCKE RCLK R 9.080 3 2.363 M
RDQMH RCLK R 9.475 3 2.443 M
RDQML RCLK R 10.477 3 2.713 M
RD[0] nCCAS F 11.252 3 2.942 M
RD[1] nCCAS F 11.963 3 3.100 M
RD[2] nCCAS F 12.880 3 3.336 M
RD[3] nCCAS F 12.422 3 3.224 M
RD[4] nCCAS F 11.252 3 2.942 M
RD[5] nCCAS F 12.423 3 3.212 M
RD[6] nCCAS F 12.979 3 3.375 M
RD[7] nCCAS F 12.914 3 3.350 M
UFMCLK RCLK R 8.007 3 2.126 M
UFMSDI RCLK R 8.007 3 2.126 M
nRCAS RCLK R 8.595 3 2.232 M
nRCS RCLK R 7.429 3 1.949 M
nRRAS RCLK R 8.615 3 2.236 M
nRWE RCLK R 7.429 3 1.949 M
nUFMCS RCLK R 9.193 3 2.413 M
WARNING: you must also run trce with hold speed: 3
WARNING: you must also run trce with setup speed: M

View File

@ -0,0 +1,91 @@
[ActiveSupport TRCE]
; Setup Analysis
Period_0 = 26.150 ns (350.000 ns);
Period_1 = 2.000 ns (350.000 ns);
Period_2 = 2.000 ns (350.000 ns);
Period_3 = 8.434 ns (16.000 ns);
Tco_4 = - (-);
Tco_5 = - (-);
Tco_6 = - (-);
Tco_7 = - (-);
Tco_8 = - (-);
Tco_9 = - (-);
Tco_10 = - (-);
Tco_11 = - (-);
Tco_12 = - (-);
Tco_13 = - (-);
Tco_14 = - (-);
Tco_15 = - (-);
Tco_16 = 8.596 ns (12.500 ns);
Tco_17 = 8.766 ns (12.500 ns);
Tco_18 = 8.896 ns (12.500 ns);
Tco_19 = 10.255 ns (12.500 ns);
Tco_20 = 10.001 ns (12.500 ns);
Tco_21 = 9.609 ns (12.500 ns);
Tco_22 = 8.504 ns (12.500 ns);
Tco_23 = 9.933 ns (12.500 ns);
Tco_24 = 10.062 ns (12.500 ns);
Tco_25 = 8.766 ns (12.500 ns);
Tco_26 = 9.674 ns (12.500 ns);
Tco_27 = 7.429 ns (12.500 ns);
Tco_28 = 9.080 ns (12.500 ns);
Tco_29 = 7.429 ns (12.500 ns);
Tco_30 = 8.615 ns (12.500 ns);
Tco_31 = 8.595 ns (12.500 ns);
Tco_32 = 9.475 ns (12.500 ns);
Tco_33 = 10.477 ns (12.500 ns);
Tco_34 = - (-);
Tco_35 = - (-);
Tco_36 = - (-);
Tco_37 = - (-);
Tco_38 = - (-);
Tco_39 = - (-);
Tco_40 = - (-);
Failed = 0 (Total 41);
Clock_ports = 4;
Clock_nets = 4;
; Hold Analysis
Period_0 = - (-);
Period_1 = - (-);
Period_2 = - (-);
Period_3 = - (-);
Tco_4 = - (-);
Tco_5 = - (-);
Tco_6 = - (-);
Tco_7 = - (-);
Tco_8 = - (-);
Tco_9 = - (-);
Tco_10 = - (-);
Tco_11 = - (-);
Tco_12 = - (-);
Tco_13 = - (-);
Tco_14 = - (-);
Tco_15 = - (-);
Tco_16 = 2.220 ns (0.000 ns);
Tco_17 = 2.284 ns (0.000 ns);
Tco_18 = 2.316 ns (0.000 ns);
Tco_19 = 2.652 ns (0.000 ns);
Tco_20 = 2.579 ns (0.000 ns);
Tco_21 = 2.481 ns (0.000 ns);
Tco_22 = 2.219 ns (0.000 ns);
Tco_23 = 2.555 ns (0.000 ns);
Tco_24 = 2.599 ns (0.000 ns);
Tco_25 = 2.284 ns (0.000 ns);
Tco_26 = 2.492 ns (0.000 ns);
Tco_27 = 1.949 ns (0.000 ns);
Tco_28 = 2.363 ns (0.000 ns);
Tco_29 = 1.949 ns (0.000 ns);
Tco_30 = 2.236 ns (0.000 ns);
Tco_31 = 2.232 ns (0.000 ns);
Tco_32 = 2.443 ns (0.000 ns);
Tco_33 = 2.713 ns (0.000 ns);
Tco_34 = - (-);
Tco_35 = - (-);
Tco_36 = - (-);
Tco_37 = - (-);
Tco_38 = - (-);
Tco_39 = - (-);
Tco_40 = - (-);
Failed = 0 (Total 41);
Clock_ports = 4;
Clock_nets = 4;

View File

@ -0,0 +1,239 @@
synthesis: version Diamond (64-bit) 3.12.0.240.2
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Mon Aug 16 21:32:25 2021
Command Line: synthesis -f RAM2GS_LCMXO256C_impl1_lattice.synproj -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml
Synthesis options:
The -a option is MachXO.
The -s option is 3.
The -t option is TQFP100.
The -d option is LCMXO256C.
Using package TQFP100.
Using performance grade 3.
##########################################################
### Lattice Family : MachXO
### Device : LCMXO256C
### Package : TQFP100
### Speed : 3
##########################################################
INFO - synthesis: User-Selected Strategy Settings
Optimization goal = Balanced
Top-level module name = RAM2GS.
Target frequency = 200.000000 MHz.
Maximum fanout = 1000.
Timing path count = 3
BRAM utilization = 100.000000 %
DSP usage = true
DSP utilization = 100.000000 %
fsm_encoding_style = auto
resolve_mixed_drivers = 0
fix_gated_clocks = 1
Mux style = Auto
Use Carry Chain = true
carry_chain_length = 0
Loop Limit = 1950.
Use IO Insertion = TRUE
Use IO Reg = AUTO
Resource Sharing = TRUE
Propagate Constants = TRUE
Remove Duplicate Registers = TRUE
force_gsr = auto
ROM style = auto
RAM style = auto
The -comp option is FALSE.
The -syn option is FALSE.
-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C (searchpath added)
-p C:/lscc/diamond/3.12/ispfpga/mj5g00/data (searchpath added)
-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/impl1 (searchpath added)
-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C (searchpath added)
Verilog design file = C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v
NGD file = RAM2GS_LCMXO256C_impl1.ngd
-sdc option: SDC file input not used.
-lpf option: Output file option is ON.
Hardtimer checking is enabled (default). The -dt option is not used.
The -r option is OFF. [ Remove LOC Properties is OFF. ]
Technology check ok...
Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482
Compile design.
Compile Design Begin
Analyzing Verilog file c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v. VERI-1482
Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482
Top module name (Verilog): RAM2GS
INFO - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(1): compiling module RAM2GS. VERI-1018
WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131): expression size 32 truncated to fit in target size 2. VERI-1209
WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136): expression size 32 truncated to fit in target size 18. VERI-1209
WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263): expression size 32 truncated to fit in target size 4. VERI-1209
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
Loading device for application map from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.19.
Top-level module name = RAM2GS.
INFO - synthesis: Extracted state machine for register 'IS' with one-hot encoding
original encoding -> new encoding (one-hot encoding)
0000 -> 0000000000000001
0001 -> 0000000000000010
0010 -> 0000000000000100
0011 -> 0000000000001000
0100 -> 0000000000010000
0101 -> 0000000000100000
0110 -> 0000000001000000
0111 -> 0000000010000000
1000 -> 0000000100000000
1001 -> 0000001000000000
1010 -> 0000010000000000
1011 -> 0000100000000000
1100 -> 0001000000000000
1101 -> 0010000000000000
1110 -> 0100000000000000
1111 -> 1000000000000000
INFO - synthesis: Extracted state machine for register 'S' with one-hot encoding
original encoding -> new encoding (one-hot encoding)
00 -> 0001
01 -> 0010
10 -> 0100
11 -> 1000
GSR will not be inferred because no asynchronous signal was found in the netlist.
WARNING - synthesis: Initial value found on instance C1Submitted_379 will be ignored.
Applying 200.000000 MHz constraint to all clocks
WARNING - synthesis: No user .sdc file.
Results of NGD DRC are available in RAM2GS_drc.log.
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
All blocks are expanded and NGD expansion is successful.
Writing NGD file RAM2GS_LCMXO256C_impl1.ngd.
################### Begin Area Report (RAM2GS)######################
Number of register bits => 102 of 490 (20 % )
BB => 8
CCU2 => 9
FD1P3AX => 28
FD1P3AY => 3
FD1P3IX => 2
FD1P3JX => 1
FD1S3AX => 47
FD1S3AY => 1
FD1S3IX => 16
FD1S3JX => 4
GSR => 1
IB => 26
INV => 3
OB => 33
ORCALUT4 => 116
PFUMX => 3
################### End Area Report ##################
################### Begin BlackBox Report ######################
TSALL => 1
################### End BlackBox Report ##################
################### Begin Clock Report ######################
Clock Nets
Number of Clocks: 4
Net : RCLK_c, loads : 62
Net : PHI2_c, loads : 11
Net : nCCAS_c, loads : 2
Net : nCRAS_c, loads : 2
Clock Enable Nets
Number of Clock Enables: 13
Top 10 highest fanout Clock Enables:
Net : RCLK_c_enable_23, loads : 16
Net : RCLK_c_enable_4, loads : 3
Net : PHI2_N_114_enable_7, loads : 3
Net : RCLK_c_enable_24, loads : 2
Net : PHI2_N_114_enable_6, loads : 2
Net : RCLK_c_enable_7, loads : 1
Net : RCLK_c_enable_6, loads : 1
Net : RCLK_c_enable_3, loads : 1
Net : PHI2_N_114_enable_2, loads : 1
Net : PHI2_N_114_enable_1, loads : 1
Highest fanout non-clock nets
Top 10 highest fanout non-clock nets:
Net : InitReady, loads : 17
Net : RCLK_c_enable_23, loads : 16
Net : RASr2, loads : 15
Net : nCRAS_N_9, loads : 15
Net : nRowColSel_N_35, loads : 14
Net : nRowColSel, loads : 13
Net : Ready, loads : 13
Net : n2307, loads : 13
Net : nCCAS_N_3, loads : 10
Net : Din_c_6, loads : 9
################### End Clock Report ##################
Timing Report Summary
--------------
--------------------------------------------------------------------------------
Constraint | Constraint| Actual|Levels
--------------------------------------------------------------------------------
| | |
create_clock -period 5.000000 -name | | |
clk3 [get_nets nCCAS_c] | -| -| 0
| | |
create_clock -period 5.000000 -name | | |
clk2 [get_nets nCRAS_c] | -| -| 0
| | |
create_clock -period 5.000000 -name | | |
clk1 [get_nets PHI2_c] | 200.000 MHz| 38.826 MHz| 7 *
| | |
create_clock -period 5.000000 -name | | |
clk0 [get_nets RCLK_c] | 200.000 MHz| 88.566 MHz| 6 *
| | |
--------------------------------------------------------------------------------
2 constraints not met.
Peak Memory Usage: 50.406 MB
--------------------------------------------------------------
Elapsed CPU time for LSE flow : 0.530 secs
--------------------------------------------------------------

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<PRE><A name="Syn"></A><B><U><big>Synthesis and Ngdbuild Report</big></U></B>
synthesis: version Diamond (64-bit) 3.12.0.240.2
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Mon Aug 16 21:32:25 2021
Command Line: synthesis -f RAM2GS_LCMXO256C_impl1_lattice.synproj -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml
Synthesis options:
The -a option is MachXO.
The -s option is 3.
The -t option is TQFP100.
The -d option is LCMXO256C.
Using package TQFP100.
Using performance grade 3.
##########################################################
### Lattice Family : MachXO
### Device : LCMXO256C
### Package : TQFP100
### Speed : 3
##########################################################
INFO - synthesis: User-Selected Strategy Settings
Optimization goal = Balanced
Top-level module name = RAM2GS.
Target frequency = 200.000000 MHz.
Maximum fanout = 1000.
Timing path count = 3
BRAM utilization = 100.000000 %
DSP usage = true
DSP utilization = 100.000000 %
fsm_encoding_style = auto
resolve_mixed_drivers = 0
fix_gated_clocks = 1
Mux style = Auto
Use Carry Chain = true
carry_chain_length = 0
Loop Limit = 1950.
Use IO Insertion = TRUE
Use IO Reg = AUTO
Resource Sharing = TRUE
Propagate Constants = TRUE
Remove Duplicate Registers = TRUE
force_gsr = auto
ROM style = auto
RAM style = auto
The -comp option is FALSE.
The -syn option is FALSE.
-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C (searchpath added)
-p C:/lscc/diamond/3.12/ispfpga/mj5g00/data (searchpath added)
-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/impl1 (searchpath added)
-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C (searchpath added)
Verilog design file = C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v
NGD file = RAM2GS_LCMXO256C_impl1.ngd
-sdc option: SDC file input not used.
-lpf option: Output file option is ON.
Hardtimer checking is enabled (default). The -dt option is not used.
The -r option is OFF. [ Remove LOC Properties is OFF. ]
Technology check ok...
Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482
Compile design.
Compile Design Begin
Analyzing Verilog file c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v. VERI-1482
Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v. VERI-1482
Top module name (Verilog): RAM2GS
INFO - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(1): compiling module RAM2GS. VERI-1018
WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(131): expression size 32 truncated to fit in target size 2. VERI-1209
WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(136): expression size 32 truncated to fit in target size 18. VERI-1209
WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v(263): expression size 32 truncated to fit in target size 4. VERI-1209
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
Loading device for application map from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.19.
Top-level module name = RAM2GS.
INFO - synthesis: Extracted state machine for register 'IS' with one-hot encoding
original encoding -> new encoding (one-hot encoding)
0000 -> 0000000000000001
0001 -> 0000000000000010
0010 -> 0000000000000100
0011 -> 0000000000001000
0100 -> 0000000000010000
0101 -> 0000000000100000
0110 -> 0000000001000000
0111 -> 0000000010000000
1000 -> 0000000100000000
1001 -> 0000001000000000
1010 -> 0000010000000000
1011 -> 0000100000000000
1100 -> 0001000000000000
1101 -> 0010000000000000
1110 -> 0100000000000000
1111 -> 1000000000000000
INFO - synthesis: Extracted state machine for register 'S' with one-hot encoding
original encoding -> new encoding (one-hot encoding)
00 -> 0001
01 -> 0010
10 -> 0100
11 -> 1000
GSR will not be inferred because no asynchronous signal was found in the netlist.
WARNING - synthesis: Initial value found on instance C1Submitted_379 will be ignored.
Applying 200.000000 MHz constraint to all clocks
WARNING - synthesis: No user .sdc file.
Results of NGD DRC are available in RAM2GS_drc.log.
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mj5g00/data/mj5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
All blocks are expanded and NGD expansion is successful.
Writing NGD file RAM2GS_LCMXO256C_impl1.ngd.
################### Begin Area Report (RAM2GS)######################
Number of register bits => 102 of 490 (20 % )
BB => 8
CCU2 => 9
FD1P3AX => 28
FD1P3AY => 3
FD1P3IX => 2
FD1P3JX => 1
FD1S3AX => 47
FD1S3AY => 1
FD1S3IX => 16
FD1S3JX => 4
GSR => 1
IB => 26
INV => 3
OB => 33
ORCALUT4 => 116
PFUMX => 3
################### End Area Report ##################
################### Begin BlackBox Report ######################
TSALL => 1
################### End BlackBox Report ##################
################### Begin Clock Report ######################
Clock Nets
Number of Clocks: 4
Net : RCLK_c, loads : 62
Net : PHI2_c, loads : 11
Net : nCCAS_c, loads : 2
Net : nCRAS_c, loads : 2
Clock Enable Nets
Number of Clock Enables: 13
Top 10 highest fanout Clock Enables:
Net : RCLK_c_enable_23, loads : 16
Net : RCLK_c_enable_4, loads : 3
Net : PHI2_N_114_enable_7, loads : 3
Net : RCLK_c_enable_24, loads : 2
Net : PHI2_N_114_enable_6, loads : 2
Net : RCLK_c_enable_7, loads : 1
Net : RCLK_c_enable_6, loads : 1
Net : RCLK_c_enable_3, loads : 1
Net : PHI2_N_114_enable_2, loads : 1
Net : PHI2_N_114_enable_1, loads : 1
Highest fanout non-clock nets
Top 10 highest fanout non-clock nets:
Net : InitReady, loads : 17
Net : RCLK_c_enable_23, loads : 16
Net : RASr2, loads : 15
Net : nCRAS_N_9, loads : 15
Net : nRowColSel_N_35, loads : 14
Net : nRowColSel, loads : 13
Net : Ready, loads : 13
Net : n2307, loads : 13
Net : nCCAS_N_3, loads : 10
Net : Din_c_6, loads : 9
################### End Clock Report ##################
<A name="lse_trs"></A><B><U><big>Timing Report Summary</big></U></B>
--------------
--------------------------------------------------------------------------------
Constraint | Constraint| Actual|Levels
--------------------------------------------------------------------------------
| | |
create_clock -period 5.000000 -name | | |
clk3 [get_nets nCCAS_c] | -| -| 0
| | |
create_clock -period 5.000000 -name | | |
clk2 [get_nets nCRAS_c] | -| -| 0
| | |
create_clock -period 5.000000 -name | | |
clk1 [get_nets PHI2_c] | 200.000 MHz| 38.826 MHz| 7 *
| | |
create_clock -period 5.000000 -name | | |
clk0 [get_nets RCLK_c] | 200.000 MHz| 88.566 MHz| 6 *
| | |
--------------------------------------------------------------------------------
2 constraints not met.
Peak Memory Usage: 50.406 MB
--------------------------------------------------------------
Elapsed CPU time for LSE flow : 0.530 secs
--------------------------------------------------------------
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LSE_CPS_ID_196 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:63[13:19]"
LSE_CPS_ID_197 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:64[13:19]"
LSE_CPS_ID_198 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:65[13:19]"
LSE_CPS_ID_199 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:8[8:12]"
LSE_CPS_ID_200 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:35[14:18]"
LSE_CPS_ID_201 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:35[14:18]"
LSE_CPS_ID_202 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:35[14:18]"
LSE_CPS_ID_203 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:35[14:18]"
LSE_CPS_ID_204 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:35[14:18]"
LSE_CPS_ID_205 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:35[14:18]"
LSE_CPS_ID_206 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:35[14:18]"
LSE_CPS_ID_207 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:35[14:18]"
LSE_CPS_ID_208 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:35[14:18]"
LSE_CPS_ID_209 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:35[14:18]"
LSE_CPS_ID_210 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:34[14:18]"
LSE_CPS_ID_211 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:34[14:18]"
LSE_CPS_ID_212 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:26[14:17]"
LSE_CPS_ID_213 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:26[14:17]"
LSE_CPS_ID_214 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:26[14:17]"
LSE_CPS_ID_215 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:26[14:17]"
LSE_CPS_ID_216 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:26[14:17]"
LSE_CPS_ID_217 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:26[14:17]"
LSE_CPS_ID_218 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:26[14:17]"
LSE_CPS_ID_219 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:26[14:17]"
LSE_CPS_ID_220 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:16[8:13]"
LSE_CPS_ID_221 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:16[15:20]"
LSE_CPS_ID_222 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:36[8:12]"
LSE_CPS_ID_223 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:41[8:12]"
LSE_CPS_ID_224 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:66[8:14]"
LSE_CPS_ID_225 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:55[19:54]"
LSE_CPS_ID_226 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:136[9:13]"
LSE_CPS_ID_227 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:147[9] 285[5]"
LSE_CPS_ID_228 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:327[9] 396[5]"
LSE_CPS_ID_229 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:147[9] 285[5]"
LSE_CPS_ID_230 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:131[13:16]"
LSE_CPS_ID_231 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:131[13:16]"
LSE_CPS_ID_232 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:55[19:54]"
LSE_CPS_ID_233 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:84[6:11]"
LSE_CPS_ID_234 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:214[26:30]"
LSE_CPS_ID_235 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:136[9:13]"
LSE_CPS_ID_236 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:327[9] 396[5]"
LSE_CPS_ID_237 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:55[19:54]"
LSE_CPS_ID_238 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:55[19:54]"
LSE_CPS_ID_239 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:136[9:13]"
LSE_CPS_ID_240 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:288[9] 324[5]"
LSE_CPS_ID_241 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:136[9:13]"
LSE_CPS_ID_242 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:136[9:13]"
LSE_CPS_ID_243 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:55[19:54]"
LSE_CPS_ID_244 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:83[6:15]"
LSE_CPS_ID_245 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:131[13:16]"
LSE_CPS_ID_246 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:131[13:16]"
LSE_CPS_ID_247 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:327[9] 396[5]"
LSE_CPS_ID_248 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:55[19:54]"
LSE_CPS_ID_249 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:55[19:54]"
LSE_CPS_ID_250 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:16[15:20]"
LSE_CPS_ID_251 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:8[8:12]"
LSE_CPS_ID_252 "c:/users/dog/documents/github/ram2gs/cpld/lcmxo/ram2gs-lcmxo.v:131[13:16]"

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[Runmanager]
Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1c\0\0\0\xd8\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0)
windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)
headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0)
[impl1%3CStrategy1%3E]
isChecked=false
isHidden=false
isExpanded=false

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[General]
Export.auto_tasks=IBIS, Bitgen
Map.auto_tasks=MapEqu, MapTrace
PAR.auto_tasks=PARTrace, IOTiming

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[General]
COLUMN_POS_INFO_NAME_-1_0=Prioritize
COLUMN_POS_INFO_NAME_-1_1=PIO Register

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[General]
pin_sort_type=0
pin_sort_ascending=true
sig_sort_type=0
sig_sort_ascending=true
active_Sheet=Port Assignments
[Port%20Assignments]
Name="166,0"
Group%20By="84,1"
Pin="56,2"
BANK="62,3"
IO_TYPE="131,4"
PULLMODE="92,5"
DRIVE="67,6"
SLEWRATE="92,7"
OPENDRAIN="97,8"
Outload%20%28pF%29="103,9"
MaxSkew="87,10"
Clock%20Load%20Only="121,11"
sort_columns="Name,Ascending"
[Pin%20Assignments]
Pin="90,0"
Pad%20Name="89,1"
Dual%20Function="109,2"
Polarity="77,3"
BANK="0,4"
IO_TYPE="131,5"
Signal%20Name="113,6"
Signal%20Type="115,7"
sort_columns="Pin,Ascending"
[Clock%20Resource]
Clock%20Type="100,ELLIPSIS"
Clock%20Name="100,ELLIPSIS"
Selection="100,ELLIPSIS"
[Global%20Preferences]
Preference%20Name="222,ELLIPSIS"
Preference%20Value="236,ELLIPSIS"
[Cell%20Mapping]
Type="100,ELLIPSIS"
Name="100,ELLIPSIS"
Din\Dout="100,ELLIPSIS"
PIO%20Register="100,ELLIPSIS"
[Route%20Priority]
Type="100,ELLIPSIS"
Name="100,ELLIPSIS"
Prioritize="100,ELLIPSIS"
[Timing%20Preferences]
Preference%20Name="246,ELLIPSIS"
Preference%20Value="104,ELLIPSIS"
Preference%20Unit="98,ELLIPSIS"
[Group]
Group%20Type\Name="134,ELLIPSIS"
Value="38,ELLIPSIS"
[Misc%20Preferences]
Preference%20Name="117,ELLIPSIS"
Preference%20Value="104,ELLIPSIS"

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VERSION=20110520

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<?xml version="1.0" encoding="UTF-8"?>
<BaliProject version="3.2" title="RAM2GS_LCMXO640C" device="LCMXO640C-3T100C" default_implementation="impl1">
<Options/>
<Implementation title="impl1" dir="impl1" description="impl1" synthesis="lse" default_strategy="Strategy1">
<Options def_top="RAM2GS"/>
<Source name="../RAM2GS-LCMXO.v" type="Verilog" type_short="Verilog">
<Options top_module="RAM2GS"/>
</Source>
<Source name="RAM2GS_LCMXO640C.lpf" type="Logic Preference" type_short="LPF">
<Options/>
</Source>
</Implementation>
<Strategy name="Strategy1" file="RAM2GS_LCMXO640C1.sty"/>
</BaliProject>

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BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
LOCATE COMP "Dout[0]" SITE "1" ;
LOCATE COMP "Dout[6]" SITE "2" ;
LOCATE COMP "Dout[7]" SITE "3" ;
LOCATE COMP "Dout[4]" SITE "4" ;
LOCATE COMP "Dout[5]" SITE "5" ;
LOCATE COMP "Dout[3]" SITE "6" ;
LOCATE COMP "Dout[1]" SITE "7" ;
LOCATE COMP "Dout[2]" SITE "8" ;
LOCATE COMP "Din[2]" SITE "14" ;
LOCATE COMP "Din[1]" SITE "15" ;
LOCATE COMP "Din[3]" SITE "16" ;
LOCATE COMP "Din[5]" SITE "17" ;
LOCATE COMP "Din[4]" SITE "18" ;
LOCATE COMP "Din[7]" SITE "19" ;
LOCATE COMP "Din[6]" SITE "20" ;
LOCATE COMP "Din[0]" SITE "21" ;
LOCATE COMP "LED" SITE "57" ;
LOCATE COMP "RA[0]" SITE "98" ;
LOCATE COMP "RA[1]" SITE "89" ;
LOCATE COMP "RA[2]" SITE "94" ;
LOCATE COMP "RA[3]" SITE "97" ;
LOCATE COMP "RA[4]" SITE "99" ;
LOCATE COMP "RA[5]" SITE "95" ;
LOCATE COMP "RA[6]" SITE "91" ;
LOCATE COMP "RA[7]" SITE "100" ;
LOCATE COMP "RA[8]" SITE "96" ;
LOCATE COMP "RA[9]" SITE "85" ;
LOCATE COMP "RA[10]" SITE "87" ;
LOCATE COMP "RA[11]" SITE "79" ;
LOCATE COMP "RBA[1]" SITE "83" ;
LOCATE COMP "RBA[0]" SITE "63" ;
LOCATE COMP "RCKE" SITE "82" ;
LOCATE COMP "RDQMH" SITE "76" ;
LOCATE COMP "RDQML" SITE "61" ;
LOCATE COMP "UFMCLK" SITE "58" ;
LOCATE COMP "UFMSDI" SITE "56" ;
LOCATE COMP "nUFMCS" SITE "53" ;
LOCATE COMP "nRCAS" SITE "78" ;
LOCATE COMP "nRCS" SITE "77" ;
LOCATE COMP "nRRAS" SITE "73" ;
LOCATE COMP "nRWE" SITE "72" ;
LOCATE COMP "RD[0]" SITE "64" ;
LOCATE COMP "RD[1]" SITE "65" ;
LOCATE COMP "RD[2]" SITE "66" ;
LOCATE COMP "RD[3]" SITE "67" ;
LOCATE COMP "RD[4]" SITE "68" ;
LOCATE COMP "RD[5]" SITE "69" ;
LOCATE COMP "RD[6]" SITE "70" ;
LOCATE COMP "RD[7]" SITE "71" ;
LOCATE COMP "PHI2" SITE "39" ;
LOCATE COMP "RCLK" SITE "86" ;
LOCATE COMP "nCCAS" SITE "27" ;
LOCATE COMP "nCRAS" SITE "43" ;
LOCATE COMP "CROW[0]" SITE "32" ;
LOCATE COMP "CROW[1]" SITE "34" ;
LOCATE COMP "UFMSDO" SITE "55" ;
LOCATE COMP "nFWE" SITE "22" ;
LOCATE COMP "MAin[0]" SITE "23" ;
LOCATE COMP "MAin[1]" SITE "38" ;
LOCATE COMP "MAin[2]" SITE "37" ;
LOCATE COMP "MAin[3]" SITE "47" ;
LOCATE COMP "MAin[4]" SITE "46" ;
LOCATE COMP "MAin[5]" SITE "45" ;
LOCATE COMP "MAin[6]" SITE "49" ;
LOCATE COMP "MAin[7]" SITE "44" ;
LOCATE COMP "MAin[8]" SITE "50" ;
LOCATE COMP "MAin[9]" SITE "51" ;
IOBUF PORT "CROW[0]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "CROW[1]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "nCRAS" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "nCCAS" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "RCLK" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "PHI2" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "Din[0]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "Din[1]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "Din[2]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "Din[3]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "Din[4]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "Din[5]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "Din[6]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "Din[7]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "MAin[0]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "MAin[1]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "MAin[2]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "MAin[3]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "MAin[4]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "MAin[5]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "MAin[6]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "MAin[7]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "MAin[8]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "MAin[9]" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "UFMSDO" PULLMODE=KEEPER IO_TYPE=LVTTL33 ;
IOBUF PORT "nFWE" PULLMODE=NONE IO_TYPE=LVTTL33 ;
IOBUF PORT "Dout[0]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "Dout[1]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "Dout[2]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "Dout[3]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "Dout[4]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "Dout[5]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "Dout[6]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "Dout[7]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "LED" PULLMODE=NONE IO_TYPE=LVTTL33 DRIVE=16 SLEWRATE=SLOW ;
IOBUF PORT "RA[0]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RA[1]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RA[2]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RA[3]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RA[4]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RA[5]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RA[6]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RA[7]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RA[8]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RA[9]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RA[10]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RA[11]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RBA[0]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RBA[1]" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RCKE" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RDQMH" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RDQML" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "UFMCLK" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "UFMSDI" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "nRCAS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "nRCS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "nRRAS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "nRWE" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "nUFMCS" PULLMODE=NONE IO_TYPE=LVTTL33 SLEWRATE=SLOW DRIVE=4 ;
IOBUF PORT "RD[0]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
IOBUF PORT "RD[1]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
IOBUF PORT "RD[2]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
IOBUF PORT "RD[3]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
IOBUF PORT "RD[4]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
IOBUF PORT "RD[5]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
IOBUF PORT "RD[6]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
IOBUF PORT "RD[7]" PULLMODE=KEEPER IO_TYPE=LVTTL33 DRIVE=4 SLEWRATE=SLOW ;
OUTPUT PORT "RD[7]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[0]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[1]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[2]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[3]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[4]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[5]" LOAD 20.000000 pF ;
OUTPUT PORT "RD[6]" LOAD 20.000000 pF ;
OUTPUT PORT "nUFMCS" LOAD 15.000000 pF ;
OUTPUT PORT "UFMCLK" LOAD 15.000000 pF ;
OUTPUT PORT "UFMSDI" LOAD 15.000000 pF ;
OUTPUT PORT "nRWE" LOAD 10.000000 pF ;
OUTPUT PORT "nRCAS" LOAD 10.000000 pF ;
OUTPUT PORT "nRCS" LOAD 10.000000 pF ;
OUTPUT PORT "nRRAS" LOAD 10.000000 pF ;
OUTPUT PORT "RDQML" LOAD 10.000000 pF ;
OUTPUT PORT "RDQMH" LOAD 10.000000 pF ;
OUTPUT PORT "RCKE" LOAD 10.000000 pF ;
OUTPUT PORT "RBA[1]" LOAD 10.000000 pF ;
OUTPUT PORT "RBA[0]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[11]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[10]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[9]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[8]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[7]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[6]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[5]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[4]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[3]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[2]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[1]" LOAD 10.000000 pF ;
OUTPUT PORT "RA[0]" LOAD 10.000000 pF ;
OUTPUT PORT "LED" LOAD 25.000000 pF ;
OUTPUT PORT "Dout[0]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[1]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[2]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[4]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[3]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[5]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[6]" LOAD 20.000000 pF ;
OUTPUT PORT "Dout[7]" LOAD 20.000000 pF ;
USE PRIMARY NET "PHI2_c" ;
USE PRIMARY NET "RCLK_c" ;
VOLTAGE 3.300 V;
VCCIO_DERATE BANK 0 PERCENT -5;
VCCIO_DERATE PERCENT -5;
VCCIO_DERATE BANK 1 PERCENT -5;
PERIOD NET "PHI2_c" 350.000000 ns ;
PERIOD NET "nCCAS_c" 350.000000 ns ;
PERIOD NET "nCRAS_c" 350.000000 ns ;
PERIOD NET "RCLK_c" 16.000000 ns ;
CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
USE PRIMARY NET "nCCAS_c" ;
USE PRIMARY NET "nCRAS_c" ;

View File

@ -0,0 +1,205 @@
<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE strategy>
<Strategy version="1.0" predefined="0" description="" label="Strategy1">
<Property name="PROP_BD_CmdLineArgs" value="" time="0"/>
<Property name="PROP_BD_EdfHardtimer" value="Enable" time="0"/>
<Property name="PROP_BD_EdfInBusNameConv" value="None" time="0"/>
<Property name="PROP_BD_EdfInLibPath" value="" time="0"/>
<Property name="PROP_BD_EdfInRemLoc" value="Off" time="0"/>
<Property name="PROP_BD_EdfMemPath" value="" time="0"/>
<Property name="PROP_BD_ParSearchPath" value="" time="0"/>
<Property name="PROP_BIT_AddressBitGen" value="Increment" time="0"/>
<Property name="PROP_BIT_AllowReadBitGen" value="Disable" time="0"/>
<Property name="PROP_BIT_ByteWideBitMirror" value="Disable" time="0"/>
<Property name="PROP_BIT_CapReadBitGen" value="Disable" time="0"/>
<Property name="PROP_BIT_ConModBitGen" value="Disable" time="0"/>
<Property name="PROP_BIT_CreateBitFile" value="True" time="0"/>
<Property name="PROP_BIT_DisRAMResBitGen" value="True" time="0"/>
<Property name="PROP_BIT_DisableUESBitgen" value="False" time="0"/>
<Property name="PROP_BIT_DonePinBitGen" value="Pullup" time="0"/>
<Property name="PROP_BIT_DoneSigBitGen" value="4" time="0"/>
<Property name="PROP_BIT_EnIOBitGen" value="TriStateDuringReConfig" time="0"/>
<Property name="PROP_BIT_EnIntOscBitGen" value="Disable" time="0"/>
<Property name="PROP_BIT_ExtClockBitGen" value="False" time="0"/>
<Property name="PROP_BIT_GSREnableBitGen" value="True" time="0"/>
<Property name="PROP_BIT_GSRRelOnBitGen" value="DoneIn" time="0"/>
<Property name="PROP_BIT_GranTimBitGen" value="0" time="0"/>
<Property name="PROP_BIT_IOTriRelBitGen" value="Cycle 2" time="0"/>
<Property name="PROP_BIT_JTAGEnableBitGen" value="False" time="0"/>
<Property name="PROP_BIT_LenBitsBitGen" value="24" time="0"/>
<Property name="PROP_BIT_MIFFileBitGen" value="" time="0"/>
<Property name="PROP_BIT_NoHeader" value="False" time="0"/>
<Property name="PROP_BIT_OutFormatBitGen" value="Bit File (Binary)" time="0"/>
<Property name="PROP_BIT_OutFormatBitGen_REF" value="" time="0"/>
<Property name="PROP_BIT_OutFormatPromGen" value="Intel Hex 32-bit" time="0"/>
<Property name="PROP_BIT_ParityCheckBitGen" value="True" time="0"/>
<Property name="PROP_BIT_ReadBackBitGen" value="Flash" time="0"/>
<Property name="PROP_BIT_ReadCaptureBitGen" value="Disable" time="0"/>
<Property name="PROP_BIT_RemZeroFramesBitGen" value="False" time="0"/>
<Property name="PROP_BIT_RunDRCBitGen" value="True" time="0"/>
<Property name="PROP_BIT_SearchPthBitGen" value="" time="0"/>
<Property name="PROP_BIT_StartUpClkBitGen" value="Cclk" time="0"/>
<Property name="PROP_BIT_SynchIOBitGen" value="True" time="0"/>
<Property name="PROP_BIT_SysClockConBitGen" value="Reset" time="0"/>
<Property name="PROP_BIT_SysConBitGen" value="Reset" time="0"/>
<Property name="PROP_BIT_WaitStTimBitGen" value="5" time="0"/>
<Property name="PROP_IOTIMING_AllSpeed" value="False" time="0"/>
<Property name="PROP_LST_AllowDUPMod" value="False" time="0"/>
<Property name="PROP_LST_CarryChain" value="True" time="0"/>
<Property name="PROP_LST_CarryChainLength" value="0" time="0"/>
<Property name="PROP_LST_CmdLineArgs" value="" time="0"/>
<Property name="PROP_LST_DSPStyle" value="DSP" time="0"/>
<Property name="PROP_LST_DSPUtil" value="100" time="0"/>
<Property name="PROP_LST_DecodeUnreachableStates" value="False" time="0"/>
<Property name="PROP_LST_DisableDistRam" value="False" time="0"/>
<Property name="PROP_LST_EBRUtil" value="100" time="0"/>
<Property name="PROP_LST_EdfFrequency" value="200" time="0"/>
<Property name="PROP_LST_EdfHardtimer" value="Enable" time="0"/>
<Property name="PROP_LST_EdfInLibPath" value="" time="0"/>
<Property name="PROP_LST_EdfInRemLoc" value="Off" time="0"/>
<Property name="PROP_LST_EdfMemPath" value="" time="0"/>
<Property name="PROP_LST_FIXGATEDCLKS" value="True" time="0"/>
<Property name="PROP_LST_FSMEncodeStyle" value="Auto" time="0"/>
<Property name="PROP_LST_ForceGSRInfer" value="Auto" time="0"/>
<Property name="PROP_LST_IOInsertion" value="True" time="0"/>
<Property name="PROP_LST_InterFileDump" value="False" time="0"/>
<Property name="PROP_LST_LoopLimit" value="1950" time="0"/>
<Property name="PROP_LST_MaxFanout" value="1000" time="0"/>
<Property name="PROP_LST_MuxStyle" value="Auto" time="0"/>
<Property name="PROP_LST_NumCriticalPaths" value="3" time="0"/>
<Property name="PROP_LST_OptimizeGoal" value="Balanced" time="0"/>
<Property name="PROP_LST_PropagatConst" value="True" time="0"/>
<Property name="PROP_LST_RAMStyle" value="Auto" time="0"/>
<Property name="PROP_LST_ROMStyle" value="Auto" time="0"/>
<Property name="PROP_LST_RemoveDupRegs" value="True" time="0"/>
<Property name="PROP_LST_ResolvedMixedDrivers" value="False" time="0"/>
<Property name="PROP_LST_ResourceShare" value="True" time="0"/>
<Property name="PROP_LST_UseIOReg" value="Auto" time="0"/>
<Property name="PROP_LST_UseLPF" value="True" time="0"/>
<Property name="PROP_LST_VHDL2008" value="False" time="0"/>
<Property name="PROP_MAPSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
<Property name="PROP_MAPSTA_AutoTiming" value="True" time="0"/>
<Property name="PROP_MAPSTA_CheckUnconstrainedConns" value="False" time="0"/>
<Property name="PROP_MAPSTA_CheckUnconstrainedPaths" value="False" time="0"/>
<Property name="PROP_MAPSTA_FullName" value="False" time="0"/>
<Property name="PROP_MAPSTA_NumUnconstrainedPaths" value="0" time="0"/>
<Property name="PROP_MAPSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
<Property name="PROP_MAPSTA_RouteEstAlogtithm" value="0" time="0"/>
<Property name="PROP_MAPSTA_RptAsynTimLoop" value="False" time="0"/>
<Property name="PROP_MAPSTA_WordCasePaths" value="1" time="0"/>
<Property name="PROP_MAP_IgnorePreErr" value="True" time="0"/>
<Property name="PROP_MAP_MAPIORegister" value="Auto" time="0"/>
<Property name="PROP_MAP_MAPInferGSR" value="True" time="0"/>
<Property name="PROP_MAP_MapModArgs" value="" time="0"/>
<Property name="PROP_MAP_OvermapDevice" value="False" time="0"/>
<Property name="PROP_MAP_PackLogMapDes" value="0" time="0"/>
<Property name="PROP_MAP_RegRetiming" value="False" time="0"/>
<Property name="PROP_MAP_SigCrossRef" value="False" time="0"/>
<Property name="PROP_MAP_SymCrossRef" value="False" time="0"/>
<Property name="PROP_MAP_TimingDriven" value="False" time="0"/>
<Property name="PROP_MAP_TimingDrivenNodeRep" value="False" time="0"/>
<Property name="PROP_MAP_TimingDrivenPack" value="False" time="0"/>
<Property name="PROP_PARSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
<Property name="PROP_PARSTA_AutoTiming" value="True" time="0"/>
<Property name="PROP_PARSTA_CheckUnconstrainedConns" value="False" time="0"/>
<Property name="PROP_PARSTA_CheckUnconstrainedPaths" value="False" time="0"/>
<Property name="PROP_PARSTA_FullName" value="False" time="0"/>
<Property name="PROP_PARSTA_NumUnconstrainedPaths" value="0" time="0"/>
<Property name="PROP_PARSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
<Property name="PROP_PARSTA_RptAsynTimLoop" value="False" time="0"/>
<Property name="PROP_PARSTA_SpeedForHoldAnalysis" value="m" time="0"/>
<Property name="PROP_PARSTA_SpeedForSetupAnalysis" value="default" time="0"/>
<Property name="PROP_PARSTA_WordCasePaths" value="10" time="0"/>
<Property name="PROP_PAR_CrDlyStFileParDes" value="False" time="0"/>
<Property name="PROP_PAR_DisableTDParDes" value="False" time="0"/>
<Property name="PROP_PAR_EffortParDes" value="5" time="0"/>
<Property name="PROP_PAR_MultiSeedSortMode" value="Worst Slack" time="0"/>
<Property name="PROP_PAR_NewRouteParDes" value="NBR" time="0"/>
<Property name="PROP_PAR_PARClockSkew" value="Off" time="0"/>
<Property name="PROP_PAR_PARModArgs" value="" time="0"/>
<Property name="PROP_PAR_ParMultiNodeList" value="" time="0"/>
<Property name="PROP_PAR_ParRunPlaceOnly" value="False" time="0"/>
<Property name="PROP_PAR_PlcIterParDes" value="1" time="0"/>
<Property name="PROP_PAR_PlcStCostTblParDes" value="1" time="0"/>
<Property name="PROP_PAR_PrefErrorOut" value="True" time="0"/>
<Property name="PROP_PAR_RemoveDir" value="True" time="0"/>
<Property name="PROP_PAR_RouteDlyRedParDes" value="0" time="0"/>
<Property name="PROP_PAR_RoutePassParDes" value="6" time="0"/>
<Property name="PROP_PAR_RouteResOptParDes" value="0" time="0"/>
<Property name="PROP_PAR_RoutingCDP" value="0" time="0"/>
<Property name="PROP_PAR_RoutingCDR" value="0" time="0"/>
<Property name="PROP_PAR_RunParWithTrce" value="False" time="0"/>
<Property name="PROP_PAR_RunTimeReduction" value="True" time="0"/>
<Property name="PROP_PAR_SaveBestRsltParDes" value="1" time="0"/>
<Property name="PROP_PAR_StopZero" value="False" time="0"/>
<Property name="PROP_PAR_parHold" value="On" time="0"/>
<Property name="PROP_PAR_parPathBased" value="Off" time="0"/>
<Property name="PROP_PRE_CmdLineArgs" value="" time="0"/>
<Property name="PROP_PRE_EdfArrayBoundsCase" value="False" time="0"/>
<Property name="PROP_PRE_EdfAutoResOfRam" value="False" time="0"/>
<Property name="PROP_PRE_EdfClockDomainCross" value="False" time="0"/>
<Property name="PROP_PRE_EdfDSPAcrossHie" value="False" time="0"/>
<Property name="PROP_PRE_EdfFullCase" value="False" time="0"/>
<Property name="PROP_PRE_EdfIgnoreRamRWCol" value="False" time="0"/>
<Property name="PROP_PRE_EdfMissConstraint" value="False" time="0"/>
<Property name="PROP_PRE_EdfNetFanout" value="True" time="0"/>
<Property name="PROP_PRE_EdfParaCase" value="False" time="0"/>
<Property name="PROP_PRE_EdfReencodeFSM" value="True" time="0"/>
<Property name="PROP_PRE_EdfResSharing" value="True" time="0"/>
<Property name="PROP_PRE_EdfTimingViolation" value="True" time="0"/>
<Property name="PROP_PRE_EdfUseSafeFSM" value="False" time="0"/>
<Property name="PROP_PRE_EdfVlog2001" value="True" time="0"/>
<Property name="PROP_PRE_VSynComArea" value="True" time="0"/>
<Property name="PROP_PRE_VSynCritcal" value="3" time="0"/>
<Property name="PROP_PRE_VSynFSM" value="Auto" time="0"/>
<Property name="PROP_PRE_VSynFreq" value="200" time="0"/>
<Property name="PROP_PRE_VSynGSR" value="False" time="0"/>
<Property name="PROP_PRE_VSynGatedClk" value="False" time="0"/>
<Property name="PROP_PRE_VSynIOPad" value="False" time="0"/>
<Property name="PROP_PRE_VSynOutNetForm" value="None" time="0"/>
<Property name="PROP_PRE_VSynOutPref" value="True" time="0"/>
<Property name="PROP_PRE_VSynRepClkFreq" value="True" time="0"/>
<Property name="PROP_PRE_VSynRetime" value="True" time="0"/>
<Property name="PROP_PRE_VSynTimSum" value="10" time="0"/>
<Property name="PROP_PRE_VSynTransform" value="True" time="0"/>
<Property name="PROP_PRE_VSyninpd" value="0" time="0"/>
<Property name="PROP_PRE_VSynoutd" value="0" time="0"/>
<Property name="PROP_SYN_ClockConversion" value="True" time="0"/>
<Property name="PROP_SYN_CmdLineArgs" value="" time="0"/>
<Property name="PROP_SYN_DisableRegisterRep" value="False" time="0"/>
<Property name="PROP_SYN_EdfAllowDUPMod" value="False" time="0"/>
<Property name="PROP_SYN_EdfArea" value="False" time="0"/>
<Property name="PROP_SYN_EdfArrangeVHDLFiles" value="True" time="0"/>
<Property name="PROP_SYN_EdfDefEnumEncode" value="Default" time="0"/>
<Property name="PROP_SYN_EdfFanout" value="1000" time="0"/>
<Property name="PROP_SYN_EdfFrequency" value="100" time="0"/>
<Property name="PROP_SYN_EdfGSR" value="False" time="0"/>
<Property name="PROP_SYN_EdfInsertIO" value="False" time="0"/>
<Property name="PROP_SYN_EdfNumCritPath" value="" time="0"/>
<Property name="PROP_SYN_EdfNumStartEnd" value="" time="0"/>
<Property name="PROP_SYN_EdfOutNetForm" value="None" time="0"/>
<Property name="PROP_SYN_EdfPushTirstates" value="True" time="0"/>
<Property name="PROP_SYN_EdfResSharing" value="True" time="0"/>
<Property name="PROP_SYN_EdfRunRetiming" value="Pipelining Only" time="0"/>
<Property name="PROP_SYN_EdfSymFSM" value="True" time="0"/>
<Property name="PROP_SYN_EdfUnconsClk" value="False" time="0"/>
<Property name="PROP_SYN_EdfVerilogInput" value="Verilog 2001" time="0"/>
<Property name="PROP_SYN_ExportSetting" value="No" time="0"/>
<Property name="PROP_SYN_LibPath" value="" time="0"/>
<Property name="PROP_SYN_ResolvedMixedDrivers" value="False" time="0"/>
<Property name="PROP_SYN_UpdateCompilePtTimData" value="False" time="0"/>
<Property name="PROP_SYN_UseLPF" value="True" time="0"/>
<Property name="PROP_SYN_VHDL2008" value="False" time="0"/>
<Property name="PROP_THERMAL_DefaultFreq" value="0" time="0"/>
<Property name="PROP_TIM_MaxDelSimDes" value="" time="0"/>
<Property name="PROP_TIM_MinSpeedGrade" value="False" time="0"/>
<Property name="PROP_TIM_ModPreSimDes" value="" time="0"/>
<Property name="PROP_TIM_NegStupHldTim" value="True" time="0"/>
<Property name="PROP_TIM_TimSimGenPUR" value="True" time="0"/>
<Property name="PROP_TIM_TimSimGenX" value="False" time="0"/>
<Property name="PROP_TIM_TimSimHierSep" value="" time="0"/>
<Property name="PROP_TIM_TransportModeOfPathDelay" value="False" time="0"/>
<Property name="PROP_TIM_TrgtSpeedGrade" value="" time="0"/>
<Property name="PROP_TIM_WriteVerboseNetlist" value="False" time="0"/>
<Property name="PROP_TMCHK_EnableCheck" value="True" time="0"/>
</Strategy>

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@ -0,0 +1,75 @@
<HTML>
<HEAD><TITLE>Lattice TCL Log</TITLE>
<STYLE TYPE="text/css">
<!--
body,pre{ font-family:'Courier New', monospace; color: #000000; font-size:88%; background-color: #ffffff; } h1 { font-weight: bold; margin-top: 24px; margin-bottom: 10px; border-bottom: 3px solid #000; font-size: 1em; } h2 { font-weight: bold; margin-top: 18px; margin-bottom: 5px; font-size: 0.90em; } h3 { font-weight: bold; margin-top: 12px; margin-bottom: 5px; font-size: 0.80em; } p { font-size:78%; } P.Table { margin-top: 4px; margin-bottom: 4px; margin-right: 4px; margin-left: 4px; } table { border-width: 1px 1px 1px 1px; border-style: solid solid solid solid; border-color: black black black black; border-collapse: collapse; } th { font-weight:bold; padding: 4px; border-width: 1px 1px 1px 1px; border-style: solid solid solid solid; border-color: black black black black; vertical-align:top; text-align:left; font-size:78%; } td { padding: 4px; border-width: 1px 1px 1px 1px; border-style: solid solid solid solid; border-color: black black black black; vertical-align:top; font-size:78%; } a { color:#013C9A; text-decoration:none; } a:visited { color:#013C9A; } a:hover, a:active { text-decoration:underline; color:#5BAFD4; } .pass { background-color: #00ff00; } .fail { background-color: #ff0000; } .comment { font-size: 90%; font-style: italic; }
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</HEAD>
<PRE><A name="pn210816203903"></A><B><U><big>pn210816203903</big></U></B>
#Start recording tcl command: 8/16/2021 20:34:20
#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C; Project name: RAM2GS_LCMXO640C
prj_project new -name "RAM2GS_LCMXO640C" -impl "impl1" -dev LCMXO640C-3T100C -synthesis "lse"
prj_src add "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v"
prj_project save
prj_src add -exclude "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS_LCMXO.lpf"
prj_run Export -impl impl1 -forceAll
prj_src remove "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS_LCMXO.lpf"
prj_run Export -impl impl1 -forceAll
#Stop recording: 8/16/2021 20:39:03
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</HTML>

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#Start recording tcl command: 8/16/2021 20:34:20
#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C; Project name: RAM2GS_LCMXO640C
prj_project new -name "RAM2GS_LCMXO640C" -impl "impl1" -dev LCMXO640C-3T100C -synthesis "lse"
prj_src add "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS-LCMXO.v"
prj_project save
prj_src add -exclude "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS_LCMXO.lpf"
prj_run Export -impl impl1 -forceAll
prj_src remove "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/RAM2GS_LCMXO.lpf"
prj_run Export -impl impl1 -forceAll
#Stop recording: 8/16/2021 20:39:03

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#Start recording tcl command: 8/16/2021 21:33:25
#Project Location: C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C; Project name: RAM2GS_LCMXO640C
prj_project open "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/RAM2GS_LCMXO640C.ldf"
prj_run Export -impl impl1 -forceAll
prj_run Export -impl impl1 -forceOne
#Stop recording: 8/16/2021 21:41:12

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<?xml version="1.0" encoding="UTF-8"?>
<BuildStatus>
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RAM2GS_rtl.vdb

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NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
NOTE All Rights Reserved *
NOTE DATE CREATED: Mon Aug 16 21:36:33 2021 *
NOTE DESIGN NAME: RAM2GS *
NOTE DEVICE NAME: LCMXO640C-3TQFP100 *
NOTE PIN ASSIGNMENTS *
NOTE PINS RD[7] : 71 : inout *
NOTE PINS RD[6] : 70 : inout *
NOTE PINS RD[5] : 69 : inout *
NOTE PINS RD[4] : 68 : inout *
NOTE PINS RD[3] : 67 : inout *
NOTE PINS RD[2] : 66 : inout *
NOTE PINS RD[1] : 65 : inout *
NOTE PINS RD[0] : 64 : inout *
NOTE PINS Dout[7] : 3 : out *
NOTE PINS Dout[6] : 2 : out *
NOTE PINS Dout[5] : 5 : out *
NOTE PINS Dout[4] : 4 : out *
NOTE PINS Dout[3] : 6 : out *
NOTE PINS Dout[2] : 8 : out *
NOTE PINS Dout[1] : 7 : out *
NOTE PINS Dout[0] : 1 : out *
NOTE PINS LED : 57 : out *
NOTE PINS RBA[1] : 83 : out *
NOTE PINS RBA[0] : 63 : out *
NOTE PINS RA[11] : 79 : out *
NOTE PINS RA[10] : 87 : out *
NOTE PINS RA[9] : 85 : out *
NOTE PINS RA[8] : 96 : out *
NOTE PINS RA[7] : 100 : out *
NOTE PINS RA[6] : 91 : out *
NOTE PINS RA[5] : 95 : out *
NOTE PINS RA[4] : 99 : out *
NOTE PINS RA[3] : 97 : out *
NOTE PINS RA[2] : 94 : out *
NOTE PINS RA[1] : 89 : out *
NOTE PINS RA[0] : 98 : out *
NOTE PINS nRCS : 77 : out *
NOTE PINS RCKE : 82 : out *
NOTE PINS nRWE : 72 : out *
NOTE PINS nRRAS : 73 : out *
NOTE PINS nRCAS : 78 : out *
NOTE PINS RDQMH : 76 : out *
NOTE PINS RDQML : 61 : out *
NOTE PINS nUFMCS : 53 : out *
NOTE PINS UFMCLK : 58 : out *
NOTE PINS UFMSDI : 56 : out *
NOTE PINS PHI2 : 39 : in *
NOTE PINS MAin[9] : 51 : in *
NOTE PINS MAin[8] : 50 : in *
NOTE PINS MAin[7] : 44 : in *
NOTE PINS MAin[6] : 49 : in *
NOTE PINS MAin[5] : 45 : in *
NOTE PINS MAin[4] : 46 : in *
NOTE PINS MAin[3] : 47 : in *
NOTE PINS MAin[2] : 37 : in *
NOTE PINS MAin[1] : 38 : in *
NOTE PINS MAin[0] : 23 : in *
NOTE PINS CROW[1] : 34 : in *
NOTE PINS CROW[0] : 32 : in *
NOTE PINS Din[7] : 19 : in *
NOTE PINS Din[6] : 20 : in *
NOTE PINS Din[5] : 17 : in *
NOTE PINS Din[4] : 18 : in *
NOTE PINS Din[3] : 16 : in *
NOTE PINS Din[2] : 14 : in *
NOTE PINS Din[1] : 15 : in *
NOTE PINS Din[0] : 21 : in *
NOTE PINS nCCAS : 27 : in *
NOTE PINS nCRAS : 43 : in *
NOTE PINS nFWE : 22 : in *
NOTE PINS RCLK : 86 : in *
NOTE PINS UFMSDO : 55 : in *
NOTE CONFIGURATION MODE: NONE *
NOTE COMPRESSION: off *

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----------------------------------------------------------------------
Report for cell RAM2GS.TECH
Register bits: 102 of 862 (11.833%)
I/O cells: 67
Cell usage:
cell count Res Usage(%)
BB 8 100.0
CCU2 9 100.0
FD1P3AX 28 100.0
FD1P3AY 3 100.0
FD1P3IX 2 100.0
FD1P3JX 1 100.0
FD1S3AX 47 100.0
FD1S3AY 1 100.0
FD1S3IX 16 100.0
FD1S3JX 4 100.0
GSR 1 100.0
IB 26 100.0
INV 3 100.0
LUT4 114 100.0
OB 33 100.0
ORCALUT4 2 100.0
PFUMX 3 100.0
TOTAL 301

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BITGEN: Bitstream Generator Diamond (64-bit) 3.12.0.240.2
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Mon Aug 16 21:36:33 2021
Command: bitgen -w -g ES:No -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO640C/promote.xml RAM2GS_LCMXO640C_impl1.ncd RAM2GS_LCMXO640C_impl1.prf
Loading design for application Bitgen from file RAM2GS_LCMXO640C_impl1.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO640C
Package: TQFP100
Performance: 3
Loading device for application Bitgen from file 'mj5g12x10.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.17.
Performance Hardware Data Status: Version 1.124.
Running DRC.
DRC detected 0 errors and 0 warnings.
Reading Preference File from RAM2GS_LCMXO640C_impl1.prf.
Preference Summary:
+---------------------------------+---------------------------------+
| Preference | Current Setting |
+---------------------------------+---------------------------------+
| CONFIG_SECURE | OFF** |
+---------------------------------+---------------------------------+
| INBUF | ON** |
+---------------------------------+---------------------------------+
| ES | No** |
+---------------------------------+---------------------------------+
* Default setting.
** The specified setting matches the default setting.
Creating bit map...
Saving bit stream in "RAM2GS_LCMXO640C_impl1.bit".
Total CPU Time: 0 secs
Total REAL Time: 0 secs
Peak Memory Usage: 46 MB

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