mirror of
https://github.com/garrettsworkshop/RAM2GS.git
synced 2024-12-04 13:49:36 +00:00
426 lines
18 KiB
HTML
426 lines
18 KiB
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<HTML>
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<HEAD><TITLE>Project Summary</TITLE>
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</HEAD>
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<PRE><A name="Mrp"></A>
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Lattice Mapping Report File for Design Module 'RAM2GS'
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<A name="mrp_di"></A><B><U><big>Design Information</big></U></B>
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Command line: map -a MachXO -p LCMXO256C -t TQFP100 -s 3 -oc Commercial
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RAM2GS_LCMXO256C_impl1.ngd -o RAM2GS_LCMXO256C_impl1_map.ncd -pr
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RAM2GS_LCMXO256C_impl1.prf -mp RAM2GS_LCMXO256C_impl1.mrp -lpf C:/Users/Dog
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/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1.
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lpf -lpf C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/RAM2GS_L
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CMXO256C.lpf -c 0 -gui -msgset
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C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml
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Target Vendor: LATTICE
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Target Device: LCMXO256CTQFP100
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Target Performance: 3
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Mapper: mj5g00, version: Diamond (64-bit) 3.12.0.240.2
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Mapped on: 08/16/21 21:32:26
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<A name="mrp_ds"></A><B><U><big>Design Summary</big></U></B>
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Number of PFU registers: 102 out of 256 (40%)
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Number of SLICEs: 65 out of 128 (51%)
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SLICEs as Logic/ROM: 65 out of 128 (51%)
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SLICEs as RAM: 0 out of 64 (0%)
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SLICEs as Carry: 9 out of 128 (7%)
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Number of LUT4s: 129 out of 256 (50%)
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Number used as logic LUTs: 111
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Number used as distributed RAM: 0
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Number used as ripple logic: 18
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Number used as shift registers: 0
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Number of external PIOs: 67 out of 78 (86%)
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Number of GSRs: 0 out of 1 (0%)
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JTAG used : No
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Readback used : No
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Oscillator used : No
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Startup used : No
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Number of TSALL: 0 out of 1 (0%)
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Notes:-
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1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
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distributed RAMs) + 2*(Number of ripple logic)
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2. Number of logic LUT4s does not include count of distributed RAM and
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ripple logic.
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Number of clocks: 4
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Net RCLK_c: 39 loads, 39 rising, 0 falling (Driver: PIO RCLK )
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Net PHI2_c: 13 loads, 5 rising, 8 falling (Driver: PIO PHI2 )
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Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
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Net nCRAS_c: 7 loads, 0 rising, 7 falling (Driver: PIO nCRAS )
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Number of Clock Enables: 13
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Net PHI2_N_114_enable_7: 2 loads, 2 LSLICEs
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Net RCLK_c_enable_6: 1 loads, 1 LSLICEs
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Net RCLK_c_enable_4: 3 loads, 3 LSLICEs
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Net RCLK_c_enable_24: 2 loads, 2 LSLICEs
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Net RCLK_c_enable_3: 1 loads, 1 LSLICEs
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Net RCLK_c_enable_7: 1 loads, 1 LSLICEs
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Net RCLK_c_enable_23: 8 loads, 8 LSLICEs
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Net PHI2_N_114_enable_1: 1 loads, 1 LSLICEs
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Net PHI2_N_114_enable_8: 1 loads, 1 LSLICEs
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Net PHI2_N_114_enable_6: 2 loads, 2 LSLICEs
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Net PHI2_N_114_enable_2: 1 loads, 1 LSLICEs
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Net RCLK_c_enable_25: 1 loads, 1 LSLICEs
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Net Ready_N_268: 1 loads, 1 LSLICEs
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Number of LSRs: 9
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Net RASr2: 1 loads, 1 LSLICEs
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Net C1Submitted_N_225: 2 loads, 2 LSLICEs
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Net n2299: 1 loads, 1 LSLICEs
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Net nRowColSel_N_35: 1 loads, 1 LSLICEs
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Net nRowColSel_N_34: 1 loads, 1 LSLICEs
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Net LEDEN_N_88: 1 loads, 1 LSLICEs
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Net n2291: 2 loads, 2 LSLICEs
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Net Ready: 7 loads, 7 LSLICEs
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Net nRWE_N_173: 1 loads, 1 LSLICEs
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Number of nets driven by tri-state buffers: 0
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Top 10 highest fanout non-clock nets:
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Net Ready: 19 loads
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Net InitReady: 17 loads
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Net RASr2: 16 loads
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Net nRowColSel_N_35: 14 loads
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Net nRowColSel: 13 loads
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Net Din_c_6: 9 loads
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Net MAin_c_1: 9 loads
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Net Din_c_5: 8 loads
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Net FS_11: 8 loads
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Net MAin_c_0: 8 loads
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Number of warnings: 0
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Number of errors: 0
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<A name="mrp_dwe"></A><B><U><big>Design Errors/Warnings</big></U></B>
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No errors or warnings present.
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<A name="mrp_ioa"></A><B><U><big>IO (PIO) Attributes</big></U></B>
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+---------------------+-----------+-----------+------------+------------+
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| IO Name | Direction | Levelmode | IO | FIXEDDELAY |
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| | | IO_TYPE | Register | |
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+---------------------+-----------+-----------+------------+------------+
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| RD[7] | BIDIR | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| RD[6] | BIDIR | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| RD[5] | BIDIR | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| RD[4] | BIDIR | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| RD[3] | BIDIR | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| RD[2] | BIDIR | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| RD[1] | BIDIR | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| RD[0] | BIDIR | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| Dout[7] | OUTPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| Dout[6] | OUTPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| Dout[5] | OUTPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| Dout[4] | OUTPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| Dout[3] | OUTPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| Dout[2] | OUTPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| Dout[1] | OUTPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| Dout[0] | OUTPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| LED | OUTPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| RBA[1] | OUTPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| RBA[0] | OUTPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| RA[11] | OUTPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| RA[10] | OUTPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| RA[9] | OUTPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| RA[8] | OUTPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| RA[7] | OUTPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| RA[6] | OUTPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| RA[5] | OUTPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| RA[4] | OUTPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| RA[3] | OUTPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| RA[2] | OUTPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| RA[1] | OUTPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| RA[0] | OUTPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| nRCS | OUTPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| RCKE | OUTPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| nRWE | OUTPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| nRRAS | OUTPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| nRCAS | OUTPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| RDQMH | OUTPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| RDQML | OUTPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| nUFMCS | OUTPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| UFMCLK | OUTPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| UFMSDI | OUTPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| PHI2 | INPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| MAin[9] | INPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| MAin[8] | INPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| MAin[7] | INPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| MAin[6] | INPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| MAin[5] | INPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| MAin[4] | INPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| MAin[3] | INPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| MAin[2] | INPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| MAin[1] | INPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| MAin[0] | INPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| CROW[1] | INPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| CROW[0] | INPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| Din[7] | INPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| Din[6] | INPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| Din[5] | INPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| Din[4] | INPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| Din[3] | INPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| Din[2] | INPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| Din[1] | INPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| Din[0] | INPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| nCCAS | INPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| nCRAS | INPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| nFWE | INPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| RCLK | INPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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| UFMSDO | INPUT | LVTTL33 | | |
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+---------------------+-----------+-----------+------------+------------+
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<A name="mrp_rm"></A><B><U><big>Removed logic</big></U></B>
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Block i2 undriven or does not drive anything - clipped.
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Block GSR_INST undriven or does not drive anything - clipped.
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Signal PHI2_N_114 was merged into signal PHI2_c
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Signal nCRAS_N_9 was merged into signal nCRAS_c
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Signal nCCAS_N_3 was merged into signal nCCAS_c
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Signal n2302 was merged into signal nRowColSel_N_35
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Signal nRWE_N_172 was merged into signal nRWE_N_173
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Signal n2307 was merged into signal Ready
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Signal RASr2_N_63 was merged into signal RASr2
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Signal n1377 was merged into signal nRowColSel_N_34
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Signal n2306 was merged into signal nFWE_c
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Signal UFMSDO_N_74 was merged into signal UFMSDO_c
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Signal GND_net undriven or does not drive anything - clipped.
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Signal VCC_net undriven or does not drive anything - clipped.
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Signal FS_577_add_4_14/CO0 undriven or does not drive anything - clipped.
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Signal FS_577_add_4_16/CO0 undriven or does not drive anything - clipped.
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Signal FS_577_add_4_12/CO0 undriven or does not drive anything - clipped.
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Signal FS_577_add_4_2/CO0 undriven or does not drive anything - clipped.
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Signal FS_577_add_4_4/CO0 undriven or does not drive anything - clipped.
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Signal FS_577_add_4_6/CO0 undriven or does not drive anything - clipped.
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Signal FS_577_add_4_18/CO1 undriven or does not drive anything - clipped.
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Signal FS_577_add_4_18/CO0 undriven or does not drive anything - clipped.
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Signal FS_577_add_4_8/CO0 undriven or does not drive anything - clipped.
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Signal FS_577_add_4_10/CO0 undriven or does not drive anything - clipped.
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Block i1962 was optimized away.
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Block i1961 was optimized away.
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Block i1963 was optimized away.
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Block i1070_1_lut_rep_25 was optimized away.
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Block nRWE_I_49_1_lut was optimized away.
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Block i604_1_lut_rep_30 was optimized away.
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Block RASr2_I_0_1_lut was optimized away.
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Block i1069_1_lut was optimized away.
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Block i1_1_lut_rep_29 was optimized away.
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Block UFMSDO_I_0_1_lut was optimized away.
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Block i1 was optimized away.
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<A name="mrp_runtime"></A><B><U><big>Run Time and Memory Usage</big></U></B>
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-------------------------
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Total CPU Time: 0 secs
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Total REAL Time: 0 secs
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Peak Memory Usage: 29 MB
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||
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Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||
|
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||
|
|
Copyright (c) 2001 Agere Systems All rights reserved.
|
||
|
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Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights
|
||
|
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reserved.
|
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</PRE></FONT>
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</BODY>
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</HTML>
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