mirror of
https://github.com/garrettsworkshop/RAM2GS.git
synced 2025-02-20 09:29:07 +00:00
30 lines
1.4 KiB
Plaintext
30 lines
1.4 KiB
Plaintext
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Report for cell RAM2GS.verilog
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Register bits: 90 of 640 (14%)
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PIC Latch: 0
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I/O cells: 67
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Cell usage:
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cell count Res Usage(%)
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BB 8 100.0
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CCU2D 10 100.0
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FD1P3AX 11 100.0
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FD1S3AX 49 100.0
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FD1S3AY 1 100.0
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FD1S3IX 3 100.0
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GSR 1 100.0
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IB 26 100.0
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IFS1P3DX 9 100.0
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INV 7 100.0
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OB 33 100.0
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OFS1P3BX 4 100.0
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OFS1P3DX 12 100.0
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OFS1P3JX 1 100.0
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ORCALUT4 135 100.0
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PFUMX 1 100.0
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PUR 1 100.0
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VHI 1 100.0
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VLO 1 100.0
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TOTAL 314
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