mirror of
https://github.com/garrettsworkshop/RAM2GS.git
synced 2024-11-25 00:31:24 +00:00
278 lines
6.4 KiB
Plaintext
278 lines
6.4 KiB
Plaintext
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|RAM4GS
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PHI2 => Bank[0].CLK
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PHI2 => Bank[1].CLK
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PHI2 => Bank[2].CLK
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PHI2 => Bank[3].CLK
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PHI2 => Bank[4].CLK
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PHI2 => Bank[5].CLK
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PHI2 => Bank[6].CLK
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PHI2 => Bank[7].CLK
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PHI2 => RA11.CLK
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PHI2 => PHI2r.DATAIN
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PHI2 => CmdDRDIn.CLK
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PHI2 => CmdDRCLK.CLK
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PHI2 => CmdUFMPrgm.CLK
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PHI2 => CmdUFMErase.CLK
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PHI2 => CmdSubmitted.CLK
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PHI2 => Cmdn8MEGEN.CLK
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PHI2 => XOR8MEG.CLK
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PHI2 => ADSubmitted.CLK
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PHI2 => C1Submitted.CLK
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PHI2 => UFMOscEN.CLK
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PHI2 => CmdEnable.CLK
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MAin[0] => RA.DATAA
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MAin[0] => RowA.DATAB
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MAin[0] => Equal0.IN7
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MAin[0] => Equal1.IN7
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MAin[0] => Equal3.IN6
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MAin[1] => RA.DATAA
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MAin[1] => RowA.DATAB
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MAin[1] => Equal0.IN6
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MAin[1] => Equal1.IN6
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MAin[1] => Equal3.IN7
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MAin[2] => RA.DATAA
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MAin[2] => RowA.DATAB
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MAin[2] => Equal0.IN5
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MAin[2] => Equal1.IN5
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MAin[2] => Equal3.IN5
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MAin[3] => RA.DATAA
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MAin[3] => RowA.DATAB
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MAin[3] => Equal0.IN4
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MAin[3] => Equal1.IN4
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MAin[3] => Equal3.IN4
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MAin[4] => RA.DATAA
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MAin[4] => RowA.DATAB
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MAin[4] => Equal0.IN3
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MAin[4] => Equal1.IN3
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MAin[4] => Equal3.IN3
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MAin[5] => RA.DATAA
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MAin[5] => RowA.DATAB
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MAin[5] => Equal0.IN2
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MAin[5] => Equal1.IN2
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MAin[5] => Equal3.IN2
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MAin[6] => RA.DATAA
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MAin[6] => RowA.DATAB
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MAin[6] => Equal0.IN1
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MAin[6] => Equal1.IN1
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MAin[6] => Equal3.IN1
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MAin[7] => RA.DATAA
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MAin[7] => RowA.DATAB
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MAin[7] => Equal0.IN0
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MAin[7] => Equal1.IN0
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MAin[7] => Equal3.IN0
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MAin[8] => RA.DATAA
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MAin[8] => RowA.DATAB
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MAin[9] => RA.DATAA
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MAin[9] => comb.DATAA
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MAin[9] => RowA.DATAB
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MAin[9] => comb.DATAA
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CROW[0] => RBA.DATAB
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CROW[1] => RBA.DATAB
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Din[0] => CmdDRDIn.DATAB
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Din[0] => XOR8MEG.DATAB
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Din[0] => WRD[0].DATAIN
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Din[0] => Bank[0].DATAIN
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Din[0] => Equal14.IN2
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Din[0] => Equal15.IN4
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Din[0] => Cmdn8MEGEN.DATAB
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Din[1] => CmdDRCLK.DATAB
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Din[1] => WRD[1].DATAIN
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Din[1] => Bank[1].DATAIN
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Din[1] => Equal14.IN7
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Din[1] => Equal15.IN7
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Din[2] => CmdUFMPrgm.DATAB
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Din[2] => WRD[2].DATAIN
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Din[2] => Bank[2].DATAIN
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Din[2] => Equal14.IN6
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Din[2] => Equal15.IN3
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Din[3] => CmdUFMErase.DATAB
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Din[3] => WRD[3].DATAIN
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Din[3] => Bank[3].DATAIN
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Din[3] => Equal14.IN5
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Din[3] => Equal15.IN2
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Din[4] => WRD[4].DATAIN
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Din[4] => Bank[4].DATAIN
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Din[4] => Equal14.IN4
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Din[4] => Equal15.IN6
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Din[4] => Equal16.IN3
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Din[4] => Equal17.IN0
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Din[4] => Equal18.IN3
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Din[5] => WRD[5].DATAIN
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Din[5] => Bank[5].DATAIN
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Din[5] => Equal14.IN3
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Din[5] => Equal15.IN1
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Din[5] => Equal16.IN2
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Din[5] => Equal17.IN3
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Din[5] => Equal18.IN0
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Din[6] => RA11.IN1
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Din[6] => WRD[6].DATAIN
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Din[6] => Bank[6].DATAIN
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Din[6] => Equal14.IN1
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Din[6] => Equal15.IN5
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Din[6] => Equal16.IN1
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Din[6] => Equal17.IN2
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Din[6] => Equal18.IN2
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Din[7] => WRD[7].DATAIN
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Din[7] => Bank[7].DATAIN
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Din[7] => Equal14.IN0
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Din[7] => Equal15.IN0
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Din[7] => Equal16.IN0
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Din[7] => Equal17.IN1
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Din[7] => Equal18.IN1
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Dout[0] <= Dout[0].DB_MAX_OUTPUT_PORT_TYPE
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Dout[1] <= Dout[1].DB_MAX_OUTPUT_PORT_TYPE
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Dout[2] <= Dout[2].DB_MAX_OUTPUT_PORT_TYPE
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Dout[3] <= Dout[3].DB_MAX_OUTPUT_PORT_TYPE
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Dout[4] <= Dout[4].DB_MAX_OUTPUT_PORT_TYPE
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Dout[5] <= Dout[5].DB_MAX_OUTPUT_PORT_TYPE
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Dout[6] <= Dout[6].DB_MAX_OUTPUT_PORT_TYPE
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Dout[7] <= Dout[7].DB_MAX_OUTPUT_PORT_TYPE
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nCCAS => WRD[0].CLK
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nCCAS => WRD[1].CLK
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nCCAS => WRD[2].CLK
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nCCAS => WRD[3].CLK
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nCCAS => WRD[4].CLK
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nCCAS => WRD[5].CLK
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nCCAS => WRD[6].CLK
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nCCAS => WRD[7].CLK
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nCCAS => comb.IN0
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nCCAS => CBR.DATAIN
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nCCAS => CASr.DATAIN
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nCRAS => CBR.CLK
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nCRAS => FWEr.CLK
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nCRAS => RowA[0].CLK
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nCRAS => RowA[1].CLK
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nCRAS => RowA[2].CLK
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nCRAS => RowA[3].CLK
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nCRAS => RowA[4].CLK
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nCRAS => RowA[5].CLK
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nCRAS => RowA[6].CLK
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nCRAS => RowA[7].CLK
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nCRAS => RowA[8].CLK
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nCRAS => RowA[9].CLK
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nCRAS => RBA[0]~reg0.CLK
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nCRAS => RBA[1]~reg0.CLK
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nCRAS => RASr.DATAIN
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nFWE => comb.IN1
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nFWE => CMDWR.IN1
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nFWE => ADWR.IN1
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nFWE => C1WR.IN1
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nFWE => FWEr.DATAIN
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RBA[0] <= RBA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
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RBA[1] <= RBA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
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RA[0] <= RA.DB_MAX_OUTPUT_PORT_TYPE
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RA[1] <= RA.DB_MAX_OUTPUT_PORT_TYPE
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RA[2] <= RA.DB_MAX_OUTPUT_PORT_TYPE
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RA[3] <= RA.DB_MAX_OUTPUT_PORT_TYPE
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RA[4] <= RA.DB_MAX_OUTPUT_PORT_TYPE
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RA[5] <= RA.DB_MAX_OUTPUT_PORT_TYPE
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RA[6] <= RA.DB_MAX_OUTPUT_PORT_TYPE
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RA[7] <= RA.DB_MAX_OUTPUT_PORT_TYPE
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RA[8] <= RA.DB_MAX_OUTPUT_PORT_TYPE
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RA[9] <= RA.DB_MAX_OUTPUT_PORT_TYPE
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RA[10] <= RA10.DB_MAX_OUTPUT_PORT_TYPE
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RA[11] <= RA11.DB_MAX_OUTPUT_PORT_TYPE
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RD[0] <> RD[0]
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RD[1] <> RD[1]
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RD[2] <> RD[2]
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RD[3] <> RD[3]
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RD[4] <> RD[4]
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RD[5] <> RD[5]
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RD[6] <> RD[6]
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RD[7] <> RD[7]
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nRCS <= nRCS~reg0.DB_MAX_OUTPUT_PORT_TYPE
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RCLK => UFMProgram.CLK
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RCLK => UFMErase.CLK
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RCLK => UFMReqErase.CLK
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RCLK => n8MEGEN.CLK
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RCLK => UFMInitDone.CLK
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RCLK => UFMD.CLK
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RCLK => DRShift.CLK
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RCLK => DRDIn.CLK
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RCLK => DRCLK.CLK
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RCLK => ARShift.CLK
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RCLK => ARCLK.CLK
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RCLK => Ready.CLK
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RCLK => IS[0].CLK
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RCLK => IS[1].CLK
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RCLK => IS[2].CLK
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RCLK => IS[3].CLK
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RCLK => nRowColSel.CLK
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RCLK => RCKEEN.CLK
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RCLK => RA10.CLK
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RCLK => nRWE~reg0.CLK
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RCLK => nRCAS~reg0.CLK
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RCLK => nRRAS~reg0.CLK
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RCLK => nRCS~reg0.CLK
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RCLK => RCKE~reg0.CLK
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RCLK => InitReady.CLK
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RCLK => FS[0].CLK
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RCLK => FS[1].CLK
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RCLK => FS[2].CLK
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RCLK => FS[3].CLK
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RCLK => FS[4].CLK
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RCLK => FS[5].CLK
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RCLK => FS[6].CLK
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RCLK => FS[7].CLK
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RCLK => FS[8].CLK
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RCLK => FS[9].CLK
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RCLK => FS[10].CLK
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RCLK => FS[11].CLK
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RCLK => FS[12].CLK
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RCLK => FS[13].CLK
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RCLK => FS[14].CLK
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RCLK => FS[15].CLK
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RCLK => FS[16].CLK
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RCLK => FS[17].CLK
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RCLK => S[0].CLK
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RCLK => S[1].CLK
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RCLK => CASr3.CLK
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RCLK => CASr2.CLK
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RCLK => CASr.CLK
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RCLK => RASr3.CLK
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RCLK => RASr2.CLK
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RCLK => RASr.CLK
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RCLK => PHI2r3.CLK
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RCLK => PHI2r2.CLK
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RCLK => PHI2r.CLK
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RCKE <= RCKE~reg0.DB_MAX_OUTPUT_PORT_TYPE
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nRWE <= nRWE~reg0.DB_MAX_OUTPUT_PORT_TYPE
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nRRAS <= nRRAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
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nRCAS <= nRCAS~reg0.DB_MAX_OUTPUT_PORT_TYPE
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RDQMH <= comb.DB_MAX_OUTPUT_PORT_TYPE
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RDQML <= comb.DB_MAX_OUTPUT_PORT_TYPE
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|RAM4GS|UFM:UFM_inst
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arclk => arclk.IN1
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ardin => ardin.IN1
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arshft => arshft.IN1
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drclk => drclk.IN1
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drdin => drdin.IN1
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drshft => drshft.IN1
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erase => erase.IN1
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oscena => oscena.IN1
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program => program.IN1
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busy <= UFM_altufm_none_1br:UFM_altufm_none_1br_component.busy
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drdout <= UFM_altufm_none_1br:UFM_altufm_none_1br_component.drdout
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osc <= UFM_altufm_none_1br:UFM_altufm_none_1br_component.osc
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rtpbusy <= UFM_altufm_none_1br:UFM_altufm_none_1br_component.rtpbusy
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|RAM4GS|UFM:UFM_inst|UFM_altufm_none_1br:UFM_altufm_none_1br_component
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arclk => maxii_ufm_block1.ARCLK
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ardin => maxii_ufm_block1.ARDIN
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arshft => maxii_ufm_block1.ARSHFT
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busy <= maxii_ufm_block1.BUSY
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drclk => maxii_ufm_block1.DRCLK
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drdin => maxii_ufm_block1.DRDIN
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drdout <= maxii_ufm_block1.DRDOUT
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drshft => maxii_ufm_block1.DRSHFT
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erase => maxii_ufm_block1.ERASE
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osc <= maxii_ufm_block1.OSC
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oscena => maxii_ufm_block1.OSCENA
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program => maxii_ufm_block1.PROGRAM
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rtpbusy <= maxii_ufm_block1.BGPBUSY
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