Add GW4201D files
This commit is contained in:
Zane Kaminski
parent
98f0c533bc
commit
f99d3e4b9a
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RAM2GS II (GW4201D) expands the Apple IIgs's
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fast memory to 8 MB.
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Low-Power, SDRAM-Based Design
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----------------------------------------
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Thanks to a modern, low-power design,
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RAM2GS II uses a maximum of 0.15 watts when idle
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(30 mA @ 5V) and 0.3W in active use (60 mA @ 5V).
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Unlike other IIgs expansion RAM cards, which are
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built with vintage asynchronous DRAM chips,
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RAM2GS II uses modern SDRAM. This design allows for
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low power consumption and improved reliability
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over other memory cards using 15+ year old chips.
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Small Size, Low-Profile
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----------------------------------------
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RAM2GS II features a small board outline and is the
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thinnest Apple IIgs expansion memory card ever produced,
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at under 4mm thin. Small and thin dimensions improve
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the mechanical compatibility between RAM2GS II and
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peripheral cards installed into the IIgs's Slot 7.
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Adjustable Capacity, Highly Compatible
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----------------------------------------
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The Apple IIgs can utilize up to 8 MB of fast memory,
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but due to limitations of the Apple IIgs hardware,
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not all 8 MB is considered "DMA-compatible."
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Only 4 MB of the 8 MB provided by an expansion RAM
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card such as the RAM2GS II is DMA-compatible,
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and peripheral cards which use DMA are
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not able to access expansion memory beyond 4 MB.
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RAM2GS II implements an adjustable capacity
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feature, allowing the user to select between
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fully DMA-compatible 4 MB capacity, or
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partially DMA-compatible 8MB capacity.
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Capacity settings can be set temporarily
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or saved in nonvolatile memory.
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The capacity adjustment utility is available on
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_RAM2GS II's support page_.
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Ecologically Friendly, Gold-Plated PCB
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----------------------------------------
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RAM2GS II features a lead-free, ENIG gold-plated,
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4-layer PCB and is fully EU RoHS-compliant.
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All units are tested extensively before shipment.
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Only new parts are used to build RAM2GS II,
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and all RAM2GS II cards are manufactured in our
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semi-automated facility in Columbus, Ohio,
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in the United States.
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Open-Source Design
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----------------------------------------
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RAM2GS II's design is fully open-source.
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The schematics, board layouts, CPLD firmware,
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and utility software are all freely available
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for commercial and noncommercial use.
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To download the design files, visit the
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_Garrett's Workshop GitHub page_.
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EESchema-LIBRARY Version 2.4
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#encoding utf-8
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#
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# Connector_Generic_Conn_02x05_Odd_Even
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#
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DEF Connector_Generic_Conn_02x05_Odd_Even J 0 40 Y N 1 F N
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F0 "J" 50 300 50 H V C CNN
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F1 "Connector_Generic_Conn_02x05_Odd_Even" 50 -300 50 H V C CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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$FPLIST
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Connector*:*_2x??_*
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$ENDFPLIST
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DRAW
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S -50 -195 0 -205 1 1 6 N
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S -50 -95 0 -105 1 1 6 N
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S -50 5 0 -5 1 1 6 N
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S -50 105 0 95 1 1 6 N
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S -50 205 0 195 1 1 6 N
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S -50 250 150 -250 1 1 10 f
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S 150 -195 100 -205 1 1 6 N
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S 150 -95 100 -105 1 1 6 N
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S 150 5 100 -5 1 1 6 N
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S 150 105 100 95 1 1 6 N
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S 150 205 100 195 1 1 6 N
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X Pin_1 1 -200 200 150 R 50 50 1 1 P
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X Pin_10 10 300 -200 150 L 50 50 1 1 P
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X Pin_2 2 300 200 150 L 50 50 1 1 P
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X Pin_3 3 -200 100 150 R 50 50 1 1 P
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X Pin_4 4 300 100 150 L 50 50 1 1 P
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X Pin_5 5 -200 0 150 R 50 50 1 1 P
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X Pin_6 6 300 0 150 L 50 50 1 1 P
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X Pin_7 7 -200 -100 150 R 50 50 1 1 P
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X Pin_8 8 300 -100 150 L 50 50 1 1 P
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X Pin_9 9 -200 -200 150 R 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# Connector_Generic_Conn_02x22_Counter_Clockwise
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#
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DEF Connector_Generic_Conn_02x22_Counter_Clockwise J 0 40 Y N 1 F N
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F0 "J" 50 1100 50 H V C CNN
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F1 "Connector_Generic_Conn_02x22_Counter_Clockwise" 50 -1200 50 H V C CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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$FPLIST
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Connector*:*_2x??_*
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$ENDFPLIST
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DRAW
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S -50 -1095 0 -1105 1 1 6 N
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S -50 -995 0 -1005 1 1 6 N
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S -50 -895 0 -905 1 1 6 N
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S -50 -795 0 -805 1 1 6 N
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S -50 -695 0 -705 1 1 6 N
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S -50 -595 0 -605 1 1 6 N
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S -50 -495 0 -505 1 1 6 N
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S -50 -395 0 -405 1 1 6 N
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S -50 -295 0 -305 1 1 6 N
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S -50 -195 0 -205 1 1 6 N
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S -50 -95 0 -105 1 1 6 N
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S -50 5 0 -5 1 1 6 N
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S -50 105 0 95 1 1 6 N
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S -50 205 0 195 1 1 6 N
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S -50 305 0 295 1 1 6 N
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S -50 405 0 395 1 1 6 N
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S -50 505 0 495 1 1 6 N
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S -50 605 0 595 1 1 6 N
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S -50 705 0 695 1 1 6 N
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S -50 805 0 795 1 1 6 N
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S -50 905 0 895 1 1 6 N
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S -50 1005 0 995 1 1 6 N
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S -50 1050 150 -1150 1 1 10 f
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S 150 -1095 100 -1105 1 1 6 N
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S 150 -995 100 -1005 1 1 6 N
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S 150 -895 100 -905 1 1 6 N
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S 150 -795 100 -805 1 1 6 N
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S 150 -695 100 -705 1 1 6 N
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S 150 -595 100 -605 1 1 6 N
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S 150 -495 100 -505 1 1 6 N
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S 150 -395 100 -405 1 1 6 N
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S 150 -295 100 -305 1 1 6 N
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S 150 -195 100 -205 1 1 6 N
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S 150 -95 100 -105 1 1 6 N
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S 150 5 100 -5 1 1 6 N
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S 150 105 100 95 1 1 6 N
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S 150 205 100 195 1 1 6 N
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S 150 305 100 295 1 1 6 N
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S 150 405 100 395 1 1 6 N
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S 150 505 100 495 1 1 6 N
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S 150 605 100 595 1 1 6 N
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S 150 705 100 695 1 1 6 N
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S 150 805 100 795 1 1 6 N
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S 150 905 100 895 1 1 6 N
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S 150 1005 100 995 1 1 6 N
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X Pin_1 1 -200 1000 150 R 50 50 1 1 P
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X Pin_10 10 -200 100 150 R 50 50 1 1 P
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X Pin_11 11 -200 0 150 R 50 50 1 1 P
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X Pin_12 12 -200 -100 150 R 50 50 1 1 P
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X Pin_13 13 -200 -200 150 R 50 50 1 1 P
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X Pin_14 14 -200 -300 150 R 50 50 1 1 P
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X Pin_15 15 -200 -400 150 R 50 50 1 1 P
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X Pin_16 16 -200 -500 150 R 50 50 1 1 P
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X Pin_17 17 -200 -600 150 R 50 50 1 1 P
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X Pin_18 18 -200 -700 150 R 50 50 1 1 P
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X Pin_19 19 -200 -800 150 R 50 50 1 1 P
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X Pin_2 2 -200 900 150 R 50 50 1 1 P
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X Pin_20 20 -200 -900 150 R 50 50 1 1 P
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X Pin_21 21 -200 -1000 150 R 50 50 1 1 P
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X Pin_22 22 -200 -1100 150 R 50 50 1 1 P
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X Pin_23 23 300 -1100 150 L 50 50 1 1 P
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X Pin_24 24 300 -1000 150 L 50 50 1 1 P
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X Pin_25 25 300 -900 150 L 50 50 1 1 P
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X Pin_26 26 300 -800 150 L 50 50 1 1 P
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X Pin_27 27 300 -700 150 L 50 50 1 1 P
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X Pin_28 28 300 -600 150 L 50 50 1 1 P
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X Pin_29 29 300 -500 150 L 50 50 1 1 P
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X Pin_3 3 -200 800 150 R 50 50 1 1 P
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X Pin_30 30 300 -400 150 L 50 50 1 1 P
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X Pin_31 31 300 -300 150 L 50 50 1 1 P
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X Pin_32 32 300 -200 150 L 50 50 1 1 P
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X Pin_33 33 300 -100 150 L 50 50 1 1 P
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X Pin_34 34 300 0 150 L 50 50 1 1 P
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X Pin_35 35 300 100 150 L 50 50 1 1 P
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X Pin_36 36 300 200 150 L 50 50 1 1 P
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X Pin_37 37 300 300 150 L 50 50 1 1 P
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X Pin_38 38 300 400 150 L 50 50 1 1 P
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X Pin_39 39 300 500 150 L 50 50 1 1 P
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X Pin_4 4 -200 700 150 R 50 50 1 1 P
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X Pin_40 40 300 600 150 L 50 50 1 1 P
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X Pin_41 41 300 700 150 L 50 50 1 1 P
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X Pin_42 42 300 800 150 L 50 50 1 1 P
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X Pin_43 43 300 900 150 L 50 50 1 1 P
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X Pin_44 44 300 1000 150 L 50 50 1 1 P
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X Pin_5 5 -200 600 150 R 50 50 1 1 P
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X Pin_6 6 -200 500 150 R 50 50 1 1 P
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X Pin_7 7 -200 400 150 R 50 50 1 1 P
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X Pin_8 8 -200 300 150 R 50 50 1 1 P
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X Pin_9 9 -200 200 150 R 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# Device_C_Small
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#
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DEF Device_C_Small C 0 10 N N 1 F N
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F0 "C" 10 70 50 H V L CNN
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F1 "Device_C_Small" 10 -80 50 H V L CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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$FPLIST
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C_*
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$ENDFPLIST
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DRAW
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P 2 0 1 13 -60 -20 60 -20 N
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P 2 0 1 12 -60 20 60 20 N
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X ~ 1 0 100 80 D 50 50 1 1 P
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X ~ 2 0 -100 80 U 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# Device_R_Pack04
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#
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DEF Device_R_Pack04 RN 0 0 Y N 1 F N
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F0 "RN" -300 0 50 V V C CNN
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F1 "Device_R_Pack04" 200 0 50 V V C CNN
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F2 "" 275 0 50 V I C CNN
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F3 "" 0 0 50 H I C CNN
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$FPLIST
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DIP*
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SOIC*
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$ENDFPLIST
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DRAW
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S -250 -95 150 95 0 1 10 f
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S -225 75 -175 -75 0 1 10 N
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S -125 75 -75 -75 0 1 10 N
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S -25 75 25 -75 0 1 10 N
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S 75 75 125 -75 0 1 10 N
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P 2 0 1 0 -200 -100 -200 -75 N
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P 2 0 1 0 -200 75 -200 100 N
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P 2 0 1 0 -100 -100 -100 -75 N
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P 2 0 1 0 -100 75 -100 100 N
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P 2 0 1 0 0 -100 0 -75 N
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P 2 0 1 0 0 75 0 100 N
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P 2 0 1 0 100 -100 100 -75 N
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P 2 0 1 0 100 75 100 100 N
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X R1.1 1 -200 -200 100 U 50 50 1 1 P
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X R2.1 2 -100 -200 100 U 50 50 1 1 P
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X R3.1 3 0 -200 100 U 50 50 1 1 P
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X R4.1 4 100 -200 100 U 50 50 1 1 P
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X R4.2 5 100 200 100 D 50 50 1 1 P
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X R3.2 6 0 200 100 D 50 50 1 1 P
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X R2.2 7 -100 200 100 D 50 50 1 1 P
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X R1.2 8 -200 200 100 D 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# Device_R_Small
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#
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DEF Device_R_Small R 0 10 N N 1 F N
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F0 "R" 30 20 50 H V L CNN
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F1 "Device_R_Small" 30 -40 50 H V L CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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$FPLIST
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R_*
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$ENDFPLIST
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DRAW
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S -30 70 30 -70 0 1 8 N
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X ~ 1 0 100 30 D 50 50 1 1 P
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X ~ 2 0 -100 30 U 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# GW_Logic_741G04GW
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#
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DEF GW_Logic_741G04GW U 0 40 Y Y 1 F N
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F0 "U" 0 250 50 H V C CNN
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F1 "GW_Logic_741G04GW" 0 -250 50 H V C CNN
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F2 "stdpads:SOT-353" 0 -300 50 H I C TNN
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F3 "" 0 -200 60 H I C CNN
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DRAW
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S 200 -200 -200 200 0 1 10 f
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X NC 1 -350 100 150 R 50 50 1 1 N
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X A 2 -400 0 200 R 50 50 1 1 I
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X GND 3 -400 -100 200 R 50 50 1 1 W
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X Y 4 400 -100 200 L 50 50 1 1 O
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X Vcc 5 400 100 200 L 50 50 1 1 W
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ENDDRAW
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ENDDEF
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#
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# GW_Logic_74245
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#
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DEF GW_Logic_74245 U 0 40 Y Y 1 F N
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F0 "U" 0 600 50 H V C CNN
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F1 "GW_Logic_74245" 0 -600 50 H V C CNN
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F2 "" 0 -650 50 H I C TNN
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F3 "" 0 100 60 H I C CNN
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DRAW
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S -200 550 200 -550 0 1 10 f
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X AtoB 1 -400 450 200 R 50 50 1 1 I
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X GND 10 -400 -450 200 R 50 50 1 1 W
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X B7 11 400 -450 200 L 50 50 1 1 B
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X B6 12 400 -350 200 L 50 50 1 1 B
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X B5 13 400 -250 200 L 50 50 1 1 B
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X B4 14 400 -150 200 L 50 50 1 1 B
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X B3 15 400 -50 200 L 50 50 1 1 B
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X B2 16 400 50 200 L 50 50 1 1 B
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X B1 17 400 150 200 L 50 50 1 1 B
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X B0 18 400 250 200 L 50 50 1 1 B
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X ~OE~ 19 400 350 200 L 50 50 1 1 I
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X A0 2 -400 350 200 R 50 50 1 1 B
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X Vcc 20 400 450 200 L 50 50 1 1 W
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X A1 3 -400 250 200 R 50 50 1 1 B
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X A2 4 -400 150 200 R 50 50 1 1 B
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X A3 5 -400 50 200 R 50 50 1 1 B
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X A4 6 -400 -50 200 R 50 50 1 1 B
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X A5 7 -400 -150 200 R 50 50 1 1 B
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X A6 8 -400 -250 200 R 50 50 1 1 B
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X A7 9 -400 -350 200 R 50 50 1 1 B
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ENDDRAW
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ENDDEF
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#
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# GW_Logic_Oscillator_4P
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#
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DEF GW_Logic_Oscillator_4P U 0 40 Y Y 1 F N
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F0 "U" 0 250 50 H V C CNN
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F1 "GW_Logic_Oscillator_4P" 0 -150 50 H V C CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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DRAW
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S -250 200 250 -100 0 1 10 f
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X EN 1 -350 100 100 R 50 50 1 1 I
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X GND 2 -350 0 100 R 50 50 1 1 W
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X Output 3 350 0 100 L 50 50 1 1 O
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X Vdd 4 350 100 100 L 50 50 1 1 W
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ENDDRAW
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ENDDEF
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#
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# GW_PLD_EPM240T100
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#
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DEF GW_PLD_EPM240T100 U 0 40 Y Y 1 L N
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F0 "U" 0 50 50 H V C CNN
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F1 "GW_PLD_EPM240T100" 0 -50 50 H V C CNN
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F2 "Package_QFP:LQFP-100_14x14mm_P0.5mm" 0 -100 20 H I C CNN
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F3 "" 0 0 50 H I C CNN
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$FPLIST
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*QFP*P0.5mm*
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$ENDFPLIST
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DRAW
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S -800 2200 800 -2200 1 1 10 f
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X IO2_1 1 1000 2100 200 L 50 50 1 1 B
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X GNDIO 10 -200 -2400 200 U 50 50 1 1 W
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X IO2_100 100 1000 -2000 200 L 50 50 1 1 B
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X GNDINT 11 -400 -2400 200 U 50 50 1 1 W
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X IO1_12/GCLK0 12 -1000 1400 200 R 50 50 1 1 B C
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X VCCINT 13 -400 2400 200 D 50 50 1 1 W
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X IO1_14/GCLK1 14 -1000 1300 200 R 50 50 1 1 B C
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X IO1_15 15 -1000 1200 200 R 50 50 1 1 B
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X IO1_16 16 -1000 1100 200 R 50 50 1 1 B
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X IO1_17 17 -1000 1000 200 R 50 50 1 1 B
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X IO1_18 18 -1000 900 200 R 50 50 1 1 B
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X IO1_19 19 -1000 800 200 R 50 50 1 1 B
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X IO1_2 2 -1000 2100 200 R 50 50 1 1 B
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X IO1_20 20 -1000 700 200 R 50 50 1 1 B
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X IO1_21 21 -1000 600 200 R 50 50 1 1 B
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X TMS 22 -1000 -1700 200 R 50 50 1 1 I
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X TDI 23 -1000 -1800 200 R 50 50 1 1 I
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X TCK 24 -1000 -1900 200 R 50 50 1 1 I C
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X TDO 25 -1000 -2000 200 R 50 50 1 1 O
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X IO1_26 26 -1000 500 200 R 50 50 1 1 B
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X IO1_27 27 -1000 400 200 R 50 50 1 1 B
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X IO1_28 28 -1000 300 200 R 50 50 1 1 B
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X IO1_29 29 -1000 200 200 R 50 50 1 1 B
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X IO1_3 3 -1000 2000 200 R 50 50 1 1 B
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X IO1_30 30 -1000 100 200 R 50 50 1 1 B
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X VCCIO1 31 -100 2400 200 D 50 50 1 1 W
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X GNDIO 32 -100 -2400 200 U 50 50 1 1 W
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X IO1_33 33 -1000 0 200 R 50 50 1 1 B
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X IO1_34 34 -1000 -100 200 R 50 50 1 1 B
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X IO1_35 35 -1000 -200 200 R 50 50 1 1 B
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X IO1_36 36 -1000 -300 200 R 50 50 1 1 B
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X IO1_37 37 -1000 -400 200 R 50 50 1 1 B
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X IO1_38 38 -1000 -500 200 R 50 50 1 1 B
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X IO1_39 39 -1000 -600 200 R 50 50 1 1 B
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X IO1_4 4 -1000 1900 200 R 50 50 1 1 B
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X IO1_40 40 -1000 -700 200 R 50 50 1 1 B
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X IO1_41 41 -1000 -800 200 R 50 50 1 1 B
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X IO1_42 42 -1000 -900 200 R 50 50 1 1 B
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X IO1_43/DEV_OE 43 -1000 -1000 200 R 50 50 1 1 B
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X IO1_44/DEV_CLRn 44 -1000 -1100 200 R 50 50 1 1 B
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X VCCIO1 45 0 2400 200 D 50 50 1 1 W
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X GNDIO 46 0 -2400 200 U 50 50 1 1 W
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X IO1_47 47 -1000 -1200 200 R 50 50 1 1 B
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X IO1_48 48 -1000 -1300 200 R 50 50 1 1 B
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X IO1_49 49 -1000 -1400 200 R 50 50 1 1 B
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X IO1_5 5 -1000 1800 200 R 50 50 1 1 B
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X IO1_50 50 -1000 -1500 200 R 50 50 1 1 B
|
||||
X IO1_51 51 -1000 -1600 200 R 50 50 1 1 B
|
||||
X IO2_52 52 1000 2000 200 L 50 50 1 1 B
|
||||
X IO2_53 53 1000 1900 200 L 50 50 1 1 B
|
||||
X IO2_54 54 1000 1800 200 L 50 50 1 1 B
|
||||
X IO2_55 55 1000 1700 200 L 50 50 1 1 B
|
||||
X IO2_56 56 1000 1600 200 L 50 50 1 1 B
|
||||
X IO2_57 57 1000 1500 200 L 50 50 1 1 B
|
||||
X IO2_58 58 1000 1400 200 L 50 50 1 1 B
|
||||
X VCCIO2 59 100 2400 200 D 50 50 1 1 W
|
||||
X IO1_6 6 -1000 1700 200 R 50 50 1 1 B
|
||||
X GNDIO 60 100 -2400 200 U 50 50 1 1 W
|
||||
X IO2_61 61 1000 1300 200 L 50 50 1 1 B
|
||||
X IO2_62/GCLK2 62 1000 1200 200 L 50 50 1 1 B C
|
||||
X VCCINT 63 -300 2400 200 D 50 50 1 1 W
|
||||
X IO2_64/GCLK3 64 1000 1100 200 L 50 50 1 1 B C
|
||||
X GNDINT 65 -300 -2400 200 U 50 50 1 1 W
|
||||
X IO2_66 66 1000 1000 200 L 50 50 1 1 B
|
||||
X IO2_67 67 1000 900 200 L 50 50 1 1 B
|
||||
X IO2_68 68 1000 800 200 L 50 50 1 1 B
|
||||
X IO2_69 69 1000 700 200 L 50 50 1 1 B
|
||||
X IO1_7 7 -1000 1600 200 R 50 50 1 1 B
|
||||
X IO2_70 70 1000 600 200 L 50 50 1 1 B
|
||||
X IO2_71 71 1000 500 200 L 50 50 1 1 B
|
||||
X IO2_72 72 1000 400 200 L 50 50 1 1 B
|
||||
X IO2_73 73 1000 300 200 L 50 50 1 1 B
|
||||
X IO2_74 74 1000 200 200 L 50 50 1 1 B
|
||||
X IO2_75 75 1000 100 200 L 50 50 1 1 B
|
||||
X IO2_76 76 1000 0 200 L 50 50 1 1 B
|
||||
X IO2_77 77 1000 -100 200 L 50 50 1 1 B
|
||||
X IO2_78 78 1000 -200 200 L 50 50 1 1 B
|
||||
X GNDIO 79 200 -2400 200 U 50 50 1 1 W
|
||||
X IO1_8 8 -1000 1500 200 R 50 50 1 1 B
|
||||
X VCCIO2 80 200 2400 200 D 50 50 1 1 W
|
||||
X IO2_81 81 1000 -300 200 L 50 50 1 1 B
|
||||
X IO2_82 82 1000 -400 200 L 50 50 1 1 B
|
||||
X IO2_83 83 1000 -500 200 L 50 50 1 1 B
|
||||
X IO2_84 84 1000 -600 200 L 50 50 1 1 B
|
||||
X IO2_85 85 1000 -700 200 L 50 50 1 1 B
|
||||
X IO2_86 86 1000 -800 200 L 50 50 1 1 B
|
||||
X IO2_87 87 1000 -900 200 L 50 50 1 1 B
|
||||
X IO2_88 88 1000 -1000 200 L 50 50 1 1 B
|
||||
X IO2_89 89 1000 -1100 200 L 50 50 1 1 B
|
||||
X VCCIO1 9 -200 2400 200 D 50 50 1 1 W
|
||||
X IO2_90 90 1000 -1200 200 L 50 50 1 1 B
|
||||
X IO2_91 91 1000 -1300 200 L 50 50 1 1 B
|
||||
X IO2_92 92 1000 -1400 200 L 50 50 1 1 B
|
||||
X GNDIO 93 300 -2400 200 U 50 50 1 1 W
|
||||
X VCCIO2 94 300 2400 200 D 50 50 1 1 W
|
||||
X IO2_95 95 1000 -1500 200 L 50 50 1 1 B
|
||||
X IO2_96 96 1000 -1600 200 L 50 50 1 1 B
|
||||
X IO2_97 97 1000 -1700 200 L 50 50 1 1 B
|
||||
X IO2_98 98 1000 -1800 200 L 50 50 1 1 B
|
||||
X IO2_99 99 1000 -1900 200 L 50 50 1 1 B
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# GW_RAM_SDRAM-16Mx16-TSOP2-54
|
||||
#
|
||||
DEF GW_RAM_SDRAM-16Mx16-TSOP2-54 U 0 40 Y Y 1 F N
|
||||
F0 "U" 0 1150 50 H V C CNN
|
||||
F1 "GW_RAM_SDRAM-16Mx16-TSOP2-54" 0 0 50 V V C CNN
|
||||
F2 "stdpads:Winbond_TSOPII-54" 0 -1650 50 H I C CIN
|
||||
F3 "" 0 -250 50 H I C CNN
|
||||
DRAW
|
||||
S -300 1100 300 -1400 0 1 10 f
|
||||
X VDD 1 -500 1000 200 R 50 50 1 1 W
|
||||
X DQ5 10 500 500 200 L 50 50 1 1 B
|
||||
X DQ6 11 500 400 200 L 50 50 1 1 B
|
||||
X VSSQ 12 -500 -1300 200 R 50 50 1 1 W N
|
||||
X DQ7 13 500 300 200 L 50 50 1 1 B
|
||||
X VDD 14 -500 1000 200 R 50 50 1 1 W N
|
||||
X DQML 15 500 -600 200 L 50 50 1 1 I
|
||||
X ~WE~ 16 500 -1100 200 L 50 50 1 1 I
|
||||
X ~CAS~ 17 500 -1200 200 L 50 50 1 1 I
|
||||
X ~RAS~ 18 500 -1300 200 L 50 50 1 1 I
|
||||
X ~CS~ 19 500 -1000 200 L 50 50 1 1 I
|
||||
X DQ0 2 500 1000 200 L 50 50 1 1 B
|
||||
X BA0 20 -500 -600 200 R 50 50 1 1 I
|
||||
X BA1 21 -500 -700 200 R 50 50 1 1 I
|
||||
X A10 22 -500 -300 200 R 50 50 1 1 I
|
||||
X A0 23 -500 700 200 R 50 50 1 1 I
|
||||
X A1 24 -500 600 200 R 50 50 1 1 I
|
||||
X A2 25 -500 500 200 R 50 50 1 1 I
|
||||
X A3 26 -500 400 200 R 50 50 1 1 I
|
||||
X VDD 27 -500 1000 200 R 50 50 1 1 W N
|
||||
X VSS 28 -500 -1200 200 R 50 50 1 1 W
|
||||
X A4 29 -500 300 200 R 50 50 1 1 I
|
||||
X VDDQ 3 -500 900 200 R 50 50 1 1 W
|
||||
X A5 30 -500 200 200 R 50 50 1 1 I
|
||||
X A6 31 -500 100 200 R 50 50 1 1 I
|
||||
X A7 32 -500 0 200 R 50 50 1 1 I
|
||||
X A8 33 -500 -100 200 R 50 50 1 1 I
|
||||
X A9 34 -500 -200 200 R 50 50 1 1 I
|
||||
X A11 35 -500 -400 200 R 50 50 1 1 I
|
||||
X A11 36 -500 -500 200 R 50 50 1 1 I
|
||||
X CKE 37 -500 -900 200 R 50 50 1 1 I
|
||||
X CLK 38 -500 -1000 200 R 50 50 1 1 I
|
||||
X DQMH 39 500 -700 200 L 50 50 1 1 I
|
||||
X DQ1 4 500 900 200 L 50 50 1 1 B
|
||||
X VSS 41 -500 -1200 200 R 50 50 1 1 W N
|
||||
X DQ8 42 500 200 200 L 50 50 1 1 B
|
||||
X VDDQ 43 -500 900 200 R 50 50 1 1 W N
|
||||
X DQ9 44 500 100 200 L 50 50 1 1 B
|
||||
X DQ10 45 500 0 200 L 50 50 1 1 B
|
||||
X VSSQ 46 -500 -1300 200 R 50 50 1 1 W N
|
||||
X DQ11 47 500 -100 200 L 50 50 1 1 B
|
||||
X DQ12 48 500 -200 200 L 50 50 1 1 B
|
||||
X VDDQ 49 -500 900 200 R 50 50 1 1 W N
|
||||
X DQ2 5 500 800 200 L 50 50 1 1 B
|
||||
X DQ13 50 500 -300 200 L 50 50 1 1 B
|
||||
X DQ14 51 500 -400 200 L 50 50 1 1 B
|
||||
X VSSQ 52 -500 -1300 200 R 50 50 1 1 W N
|
||||
X DQ15 53 500 -500 200 L 50 50 1 1 B
|
||||
X VSS 54 -500 -1200 200 R 50 50 1 1 W N
|
||||
X VSSQ 6 -500 -1300 200 R 50 50 1 1 W
|
||||
X DQ3 7 500 700 200 L 50 50 1 1 B
|
||||
X DQ4 8 500 600 200 L 50 50 1 1 B
|
||||
X VDDQ 9 -500 900 200 R 50 50 1 1 W N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Mechanical_MountingHole
|
||||
#
|
||||
DEF Mechanical_MountingHole H 0 40 Y Y 1 F N
|
||||
F0 "H" 0 200 50 H V C CNN
|
||||
F1 "Mechanical_MountingHole" 0 125 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
MountingHole*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
C 0 0 50 0 1 50 N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Mechanical_MountingHole_Pad
|
||||
#
|
||||
DEF Mechanical_MountingHole_Pad H 0 40 N N 1 F N
|
||||
F0 "H" 0 250 50 H V C CNN
|
||||
F1 "Mechanical_MountingHole_Pad" 0 175 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
MountingHole*Pad*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
C 0 50 50 0 1 50 N
|
||||
X 1 1 0 -100 100 U 50 50 1 1 I
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Regulator_Linear_LD1117S33TR_SOT223
|
||||
#
|
||||
DEF Regulator_Linear_LD1117S33TR_SOT223 U 0 10 Y Y 1 F N
|
||||
F0 "U" -150 125 50 H V C CNN
|
||||
F1 "Regulator_Linear_LD1117S33TR_SOT223" 0 125 50 H V L CNN
|
||||
F2 "Package_TO_SOT_SMD:SOT-223-3_TabPin2" 0 200 50 H I C CNN
|
||||
F3 "" 100 -250 50 H I C CNN
|
||||
ALIAS AP1117-18 AP1117-25 AP1117-33 AP1117-50 LD1117S33TR_SOT223 LD1117S12TR_SOT223 LD1117S18TR_SOT223 LD1117S25TR_SOT223 LD1117S50TR_SOT223 NCP1117-12_SOT223 NCP1117-1.5_SOT223 NCP1117-1.8_SOT223 NCP1117-2.0_SOT223 NCP1117-2.5_SOT223 NCP1117-2.85_SOT223 NCP1117-3.3_SOT223 NCP1117-5.0_SOT223 AMS1117-1.5 AMS1117-1.8 AMS1117-2.5 AMS1117-2.85 AMS1117-3.3 AMS1117-5.0
|
||||
$FPLIST
|
||||
SOT?223*TabPin2*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
S -200 -200 200 75 0 1 10 f
|
||||
X GND 1 0 -300 100 U 50 50 1 1 W
|
||||
X VO 2 300 0 100 L 50 50 1 1 w
|
||||
X VI 3 -300 0 100 R 50 50 1 1 W
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# power_+3V3
|
||||
#
|
||||
DEF power_+3V3 #PWR 0 0 Y Y 1 F P
|
||||
F0 "#PWR" 0 -150 50 H I C CNN
|
||||
F1 "power_+3V3" 0 140 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
ALIAS +3.3V
|
||||
DRAW
|
||||
P 2 0 1 0 -30 50 0 100 N
|
||||
P 2 0 1 0 0 0 0 100 N
|
||||
P 2 0 1 0 0 100 30 50 N
|
||||
X +3V3 1 0 0 0 U 50 50 1 1 W N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# power_+5V
|
||||
#
|
||||
DEF power_+5V #PWR 0 0 Y Y 1 F P
|
||||
F0 "#PWR" 0 -150 50 H I C CNN
|
||||
F1 "power_+5V" 0 140 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
P 2 0 1 0 -30 50 0 100 N
|
||||
P 2 0 1 0 0 0 0 100 N
|
||||
P 2 0 1 0 0 100 30 50 N
|
||||
X +5V 1 0 0 0 U 50 50 1 1 W N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# power_GND
|
||||
#
|
||||
DEF power_GND #PWR 0 0 Y Y 1 F P
|
||||
F0 "#PWR" 0 -250 50 H I C CNN
|
||||
F1 "power_GND" 0 -150 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
|
||||
X GND 1 0 0 0 D 50 50 1 1 W N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
#End Library
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,274 @@
|
|||
update=Sunday, July 05, 2020 at 10:26:01 PM
|
||||
version=1
|
||||
last_client=kicad
|
||||
[general]
|
||||
version=1
|
||||
RootSch=
|
||||
BoardNm=
|
||||
[cvpcb]
|
||||
version=1
|
||||
NetIExt=net
|
||||
[eeschema]
|
||||
version=1
|
||||
LibDir=
|
||||
[eeschema/libraries]
|
||||
[schematic_editor]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
PlotDirectoryName=
|
||||
SubpartIdSeparator=0
|
||||
SubpartFirstId=65
|
||||
NetFmtName=Pcbnew
|
||||
SpiceAjustPassiveValues=0
|
||||
LabSize=50
|
||||
ERC_TestSimilarLabels=1
|
||||
[pcbnew]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
LastNetListRead=RAM2GS.net
|
||||
CopperLayerCount=4
|
||||
BoardThickness=1.6
|
||||
AllowMicroVias=0
|
||||
AllowBlindVias=0
|
||||
RequireCourtyardDefinitions=0
|
||||
ProhibitOverlappingCourtyards=1
|
||||
MinTrackWidth=0.15
|
||||
MinViaDiameter=0.5
|
||||
MinViaDrill=0.2
|
||||
MinMicroViaDiameter=0.2
|
||||
MinMicroViaDrill=0.09999999999999999
|
||||
MinHoleToHole=0.25
|
||||
TrackWidth1=0.15
|
||||
TrackWidth2=0.254
|
||||
TrackWidth3=0.3
|
||||
TrackWidth4=0.4
|
||||
TrackWidth5=0.45
|
||||
TrackWidth6=0.5
|
||||
TrackWidth7=0.508
|
||||
TrackWidth8=0.6
|
||||
TrackWidth9=0.762
|
||||
TrackWidth10=0.8
|
||||
TrackWidth11=0.85
|
||||
TrackWidth12=0.895
|
||||
TrackWidth13=0.9
|
||||
TrackWidth14=1
|
||||
TrackWidth15=1.2
|
||||
TrackWidth16=1.27
|
||||
TrackWidth17=1.524
|
||||
ViaDiameter1=0.5
|
||||
ViaDrill1=0.2
|
||||
ViaDiameter2=0.6
|
||||
ViaDrill2=0.3
|
||||
ViaDiameter3=0.762
|
||||
ViaDrill3=0.381
|
||||
ViaDiameter4=0.8
|
||||
ViaDrill4=0.4
|
||||
ViaDiameter5=1
|
||||
ViaDrill5=0.5
|
||||
ViaDiameter6=1.524
|
||||
ViaDrill6=0.762
|
||||
dPairWidth1=0.2
|
||||
dPairGap1=0.25
|
||||
dPairViaGap1=0.25
|
||||
SilkLineWidth=0.15
|
||||
SilkTextSizeV=1
|
||||
SilkTextSizeH=1
|
||||
SilkTextSizeThickness=0.15
|
||||
SilkTextItalic=0
|
||||
SilkTextUpright=1
|
||||
CopperLineWidth=0.2
|
||||
CopperTextSizeV=1.5
|
||||
CopperTextSizeH=1.5
|
||||
CopperTextThickness=0.3
|
||||
CopperTextItalic=0
|
||||
CopperTextUpright=1
|
||||
EdgeCutLineWidth=0.15
|
||||
CourtyardLineWidth=0.05
|
||||
OthersLineWidth=0.15
|
||||
OthersTextSizeV=1
|
||||
OthersTextSizeH=1
|
||||
OthersTextSizeThickness=0.15
|
||||
OthersTextItalic=0
|
||||
OthersTextUpright=1
|
||||
SolderMaskClearance=0.075
|
||||
SolderMaskMinWidth=0.09999999999999999
|
||||
SolderPasteClearance=-0.03809999999999999
|
||||
SolderPasteRatio=0
|
||||
[pcbnew/Layer.F.Cu]
|
||||
Name=F.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.In1.Cu]
|
||||
Name=In1.Cu
|
||||
Type=1
|
||||
Enabled=1
|
||||
[pcbnew/Layer.In2.Cu]
|
||||
Name=In2.Cu
|
||||
Type=1
|
||||
Enabled=1
|
||||
[pcbnew/Layer.In3.Cu]
|
||||
Name=In3.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In4.Cu]
|
||||
Name=In4.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In5.Cu]
|
||||
Name=In5.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In6.Cu]
|
||||
Name=In6.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In7.Cu]
|
||||
Name=In7.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In8.Cu]
|
||||
Name=In8.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In9.Cu]
|
||||
Name=In9.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In10.Cu]
|
||||
Name=In10.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In11.Cu]
|
||||
Name=In11.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In12.Cu]
|
||||
Name=In12.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In13.Cu]
|
||||
Name=In13.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In14.Cu]
|
||||
Name=In14.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In15.Cu]
|
||||
Name=In15.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In16.Cu]
|
||||
Name=In16.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In17.Cu]
|
||||
Name=In17.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In18.Cu]
|
||||
Name=In18.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In19.Cu]
|
||||
Name=In19.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In20.Cu]
|
||||
Name=In20.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In21.Cu]
|
||||
Name=In21.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In22.Cu]
|
||||
Name=In22.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In23.Cu]
|
||||
Name=In23.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In24.Cu]
|
||||
Name=In24.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In25.Cu]
|
||||
Name=In25.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In26.Cu]
|
||||
Name=In26.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In27.Cu]
|
||||
Name=In27.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In28.Cu]
|
||||
Name=In28.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In29.Cu]
|
||||
Name=In29.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In30.Cu]
|
||||
Name=In30.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.B.Cu]
|
||||
Name=B.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Dwgs.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Cmts.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco1.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco2.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Edge.Cuts]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Margin]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Rescue]
|
||||
Enabled=0
|
||||
[pcbnew/Netclasses]
|
||||
[pcbnew/Netclasses/Default]
|
||||
Name=Default
|
||||
Clearance=0.15
|
||||
TrackWidth=0.15
|
||||
ViaDiameter=0.5
|
||||
ViaDrill=0.2
|
||||
uViaDiameter=0.3
|
||||
uViaDrill=0.1
|
||||
dPairWidth=0.2
|
||||
dPairGap=0.25
|
||||
dPairViaGap=0.25
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
-- Copyright (C) 1991-2013 Altera Corporation
|
||||
-- Your use of Altera Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Altera Program License
|
||||
-- Subscription Agreement, Altera MegaCore Function License
|
||||
-- Agreement, or other applicable license agreement, including,
|
||||
-- without limitation, that your use is for the sole purpose of
|
||||
-- programming logic devices manufactured by Altera and sold by
|
||||
-- Altera or its authorized distributors. Please refer to the
|
||||
-- applicable agreement for further details.
|
||||
|
||||
-- Quartus II generated Memory Initialization File (.mif)
|
||||
|
||||
WIDTH=16;
|
||||
DEPTH=512;
|
||||
|
||||
ADDRESS_RADIX=HEX;
|
||||
DATA_RADIX=HEX;
|
||||
|
||||
CONTENT BEGIN
|
||||
[000..0FD] : 0000;
|
||||
0FE : 7FFF;
|
||||
[0FF..1FF] : FFFF;
|
||||
END;
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2013 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 32-bit
|
||||
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
|
||||
# Date created = 21:16:34 March 08, 2020
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "13.0"
|
||||
DATE = "21:16:34 March 08, 2020"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "RAM4GS"
|
||||
|
|
@ -0,0 +1,213 @@
|
|||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2013 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 32-bit
|
||||
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
|
||||
# Date created = 21:16:34 March 08, 2020
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# RAM4GS_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus II software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
|
||||
set_global_assignment -name FAMILY "MAX II"
|
||||
set_global_assignment -name DEVICE EPM240T100C5
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY RAM4GS
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:16:34 MARCH 08, 2020"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
|
||||
set_global_assignment -name SDC_FILE constraints.sdc
|
||||
set_global_assignment -name VERILOG_FILE RAM4GS.v
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
|
||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100
|
||||
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5
|
||||
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
|
||||
set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE BALANCED
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
|
||||
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
|
||||
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
|
||||
set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER OFF
|
||||
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"
|
||||
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
|
||||
set_global_assignment -name SMART_RECOMPILE OFF
|
||||
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 10
|
||||
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 10
|
||||
set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING "PACK ALL IO REGISTERS"
|
||||
set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON
|
||||
set_global_assignment -name SAFE_STATE_MACHINE ON
|
||||
|
||||
|
||||
|
||||
set_location_assignment PIN_12 -to RCLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RCLK
|
||||
|
||||
set_location_assignment PIN_52 -to PHI2
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PHI2
|
||||
|
||||
set_location_assignment PIN_67 -to nCRAS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCRAS
|
||||
|
||||
set_location_assignment PIN_53 -to nCCAS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCCAS
|
||||
|
||||
set_location_assignment PIN_48 -to nFWE
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nFWE
|
||||
|
||||
set_location_assignment PIN_49 -to MAin[0]
|
||||
set_location_assignment PIN_51 -to MAin[1]
|
||||
set_location_assignment PIN_50 -to MAin[2]
|
||||
set_location_assignment PIN_71 -to MAin[3]
|
||||
set_location_assignment PIN_70 -to MAin[4]
|
||||
set_location_assignment PIN_69 -to MAin[5]
|
||||
set_location_assignment PIN_72 -to MAin[6]
|
||||
set_location_assignment PIN_68 -to MAin[7]
|
||||
set_location_assignment PIN_73 -to MAin[8]
|
||||
set_location_assignment PIN_74 -to MAin[9]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to MAin
|
||||
|
||||
set_location_assignment PIN_54 -to CROW[0]
|
||||
set_location_assignment PIN_55 -to CROW[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CROW
|
||||
|
||||
set_location_assignment PIN_35 -to Din[2]
|
||||
set_location_assignment PIN_36 -to Din[1]
|
||||
set_location_assignment PIN_37 -to Din[3]
|
||||
set_location_assignment PIN_38 -to Din[5]
|
||||
set_location_assignment PIN_39 -to Din[4]
|
||||
set_location_assignment PIN_40 -to Din[7]
|
||||
set_location_assignment PIN_41 -to Din[6]
|
||||
set_location_assignment PIN_42 -to Din[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Din
|
||||
|
||||
set_location_assignment PIN_33 -to Dout[0]
|
||||
set_location_assignment PIN_57 -to Dout[1]
|
||||
set_location_assignment PIN_56 -to Dout[2]
|
||||
set_location_assignment PIN_47 -to Dout[3]
|
||||
set_location_assignment PIN_44 -to Dout[4]
|
||||
set_location_assignment PIN_28 -to Dout[5]
|
||||
set_location_assignment PIN_34 -to Dout[6]
|
||||
set_location_assignment PIN_43 -to Dout[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Dout
|
||||
|
||||
set_location_assignment PIN_8 -to RCKE
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RCKE
|
||||
|
||||
set_location_assignment PIN_3 -to nRCS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRCS
|
||||
|
||||
set_location_assignment PIN_100 -to nRWE
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRWE
|
||||
|
||||
set_location_assignment PIN_6 -to nRRAS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRRAS
|
||||
|
||||
set_location_assignment PIN_4 -to nRCAS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRCAS
|
||||
|
||||
set_location_assignment PIN_5 -to RBA[0]
|
||||
set_location_assignment PIN_14 -to RBA[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RBA
|
||||
|
||||
set_location_assignment PIN_18 -to RA[0]
|
||||
set_location_assignment PIN_20 -to RA[1]
|
||||
set_location_assignment PIN_30 -to RA[2]
|
||||
set_location_assignment PIN_27 -to RA[3]
|
||||
set_location_assignment PIN_26 -to RA[4]
|
||||
set_location_assignment PIN_29 -to RA[5]
|
||||
set_location_assignment PIN_21 -to RA[6]
|
||||
set_location_assignment PIN_19 -to RA[7]
|
||||
set_location_assignment PIN_17 -to RA[8]
|
||||
set_location_assignment PIN_15 -to RA[9]
|
||||
set_location_assignment PIN_16 -to RA[10]
|
||||
set_location_assignment PIN_7 -to RA[11]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RA
|
||||
|
||||
set_location_assignment PIN_2 -to RDQMH
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RDQMH
|
||||
|
||||
set_location_assignment PIN_98 -to RDQML
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RDQML
|
||||
|
||||
set_location_assignment PIN_96 -to RD[0]
|
||||
set_location_assignment PIN_90 -to RD[1]
|
||||
set_location_assignment PIN_89 -to RD[2]
|
||||
set_location_assignment PIN_99 -to RD[3]
|
||||
set_location_assignment PIN_92 -to RD[4]
|
||||
set_location_assignment PIN_91 -to RD[5]
|
||||
set_location_assignment PIN_95 -to RD[6]
|
||||
set_location_assignment PIN_97 -to RD[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RD
|
||||
|
||||
set_global_assignment -name MIF_FILE RAM4GS.mif
|
||||
set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nCRAS
|
||||
set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nCCAS
|
||||
set_instance_assignment -name PAD_TO_CORE_DELAY 1 -to nFWE
|
||||
set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to MAin
|
||||
set_instance_assignment -name PAD_TO_CORE_DELAY 1 -to CROW
|
||||
set_instance_assignment -name PAD_TO_CORE_DELAY 1 -to Din
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to Dout
|
||||
set_instance_assignment -name SLOW_SLEW_RATE OFF -to Dout
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RCKE
|
||||
set_instance_assignment -name SLOW_SLEW_RATE OFF -to RCKE
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to RCKE
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRCS
|
||||
set_instance_assignment -name SLOW_SLEW_RATE OFF -to nRCS
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRCS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRWE
|
||||
set_instance_assignment -name SLOW_SLEW_RATE OFF -to nRWE
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRWE
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRRAS
|
||||
set_instance_assignment -name SLOW_SLEW_RATE OFF -to nRRAS
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRRAS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRCAS
|
||||
set_instance_assignment -name SLOW_SLEW_RATE OFF -to nRCAS
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRCAS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RBA
|
||||
set_instance_assignment -name SLOW_SLEW_RATE OFF -to RBA
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to RBA
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RA
|
||||
set_instance_assignment -name SLOW_SLEW_RATE OFF -to RA
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RDQMH
|
||||
set_instance_assignment -name SLOW_SLEW_RATE OFF -to RDQMH
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RDQML
|
||||
set_instance_assignment -name SLOW_SLEW_RATE OFF -to RDQML
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RD
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to RD
|
||||
set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to RD
|
||||
set_global_assignment -name QIP_FILE UFM.qip
|
||||
Binary file not shown.
|
|
@ -0,0 +1,436 @@
|
|||
module RAM4GS(PHI2, MAin, CROW, Din, Dout,
|
||||
nCCAS, nCRAS, nFWE,
|
||||
RBA, RA, RD, nRCS, RCLK, RCKE,
|
||||
nRWE, nRRAS, nRCAS, RDQMH, RDQML);
|
||||
|
||||
/* 65816 Phase 2 Clock */
|
||||
input PHI2;
|
||||
|
||||
/* Async. DRAM Control Inputs */
|
||||
input nCCAS, nCRAS;
|
||||
|
||||
/* Synchronized PHI2 and DRAM signals */
|
||||
reg PHI2r, PHI2r2, PHI2r3;
|
||||
reg RASr, RASr2, RASr3;
|
||||
reg CASr, CASr2, CASr3;
|
||||
reg FWEr;
|
||||
reg CBR;
|
||||
|
||||
/* 65816 Data */
|
||||
input [7:0] Din;
|
||||
output [7:0] Dout = RD[7:0];
|
||||
|
||||
/* Latched 65816 Bank Address */
|
||||
reg [7:0] Bank;
|
||||
|
||||
/* Async. DRAM Address Bus */
|
||||
input [1:0] CROW;
|
||||
input [9:0] MAin;
|
||||
input nFWE;
|
||||
reg n8MEGEN = 0;
|
||||
reg XOR8MEG = 0;
|
||||
|
||||
/* SDRAM Clock */
|
||||
input RCLK;
|
||||
|
||||
/* SDRAM */
|
||||
reg RCKEEN;
|
||||
output reg RCKE = 0;
|
||||
output reg nRCS = 1, nRRAS = 1, nRCAS = 1, nRWE = 1;
|
||||
output reg [1:0] RBA;
|
||||
reg nRowColSel;
|
||||
reg RA11;
|
||||
reg RA10;
|
||||
reg [9:0] RowA;
|
||||
output [11:0] RA;
|
||||
assign RA[11] = RA11;
|
||||
assign RA[10] = RA10;
|
||||
assign RA[9:0] = ~nRowColSel ? RowA[9:0] : MAin[9:0];
|
||||
output RDQML = ~nRowColSel ? 1'b1 : ~MAin[9];
|
||||
output RDQMH = ~nRowColSel ? 1'b1 : MAin[9];
|
||||
reg [7:0] WRD;
|
||||
inout [7:0] RD = (~nCCAS & ~nFWE) ? WRD[7:0] : 8'bZ;
|
||||
|
||||
/* UFM Interface */
|
||||
reg UFMD = 0; // UFM data register bit 15
|
||||
reg ARCLK = 0; // UFM address register clock
|
||||
// UFM address register data input tied to 0
|
||||
reg ARShift = 0; // 1 to Shift UFM address in, 0 to increment
|
||||
reg DRCLK = 0; // UFM data register clock
|
||||
reg DRDIn = 0; // UFM data register input
|
||||
reg DRShift = 0; // 1 to shift UFM out, 0 to load from current address
|
||||
reg UFMErase = 0; // Rising edge starts erase. UFM+RTP must not be busy
|
||||
reg UFMProgram = 0; // Rising edge starts program. UFM+RTP must not be busy
|
||||
reg UFMOscEN = 0; // UFM oscillator enable
|
||||
wire UFMBusy; // 1 if UFM is doing user operation. Asynchronous
|
||||
wire RTPBusy; // 1 if real-time programming in progress. Asynchronous
|
||||
wire DRDOut; // UFM data output
|
||||
// UFM oscillator always enabled
|
||||
wire UFMOsc; // UFM oscillator output (3.3-5.5 MHz)
|
||||
UFM UFM_inst ( // UFM IP block (for Altera MAX II and MAX V)
|
||||
.arclk (ARCLK),
|
||||
.ardin (1'b0),
|
||||
.arshft (ARShift),
|
||||
.drclk (DRCLK),
|
||||
.drdin (DRDIn),
|
||||
.drshft (DRShift),
|
||||
.erase (UFMErase),
|
||||
.oscena (UFMOscEN),
|
||||
.program (UFMProgram),
|
||||
.busy (UFMBusy),
|
||||
.drdout (DRDOut),
|
||||
.osc (UFMOsc),
|
||||
.rtpbusy (RTPBusy));
|
||||
reg UFMBusyReg = 0; // UFMBusy registered to sync with RCLK
|
||||
reg RTPBusyReg = 0; // RTPBusy registered to sync with RCLK
|
||||
|
||||
/* UFM State */
|
||||
reg UFMInitDone = 0; // 1 if UFM initialization finished
|
||||
reg UFMReqErase = 0; // 1 if UFM requires erase
|
||||
|
||||
/* UFM Command Interface */
|
||||
reg C1Submitted = 0;
|
||||
reg ADSubmitted = 0;
|
||||
reg CmdEnable = 0;
|
||||
reg CmdSubmitted = 0;
|
||||
reg Cmdn8MEGEN = 0;
|
||||
reg CmdDRCLK = 0;
|
||||
reg CmdDRDIn = 0;
|
||||
reg CmdUFMErase = 0; // Set by user command. Programs UFM
|
||||
reg CmdUFMPrgm = 0; // Set by user command. Erases UFM
|
||||
wire ADWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFF & ~nFWE;
|
||||
wire C1WR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFE & ~nFWE;
|
||||
wire CMDWR = Bank[7:0]==8'hFB & MAin[7:0]==8'hFD & ~nFWE;
|
||||
|
||||
/* State Counters */
|
||||
reg InitReady = 0; // 1 if ready for init sequence
|
||||
reg Ready = 0; // 1 if done with init sequence
|
||||
reg [1:0] S = 0; // post-RAS State counter
|
||||
reg [17:0] FS = 0; // Fast init state counter
|
||||
reg [3:0] IS = 0; // Init state counter
|
||||
reg WriteDone;
|
||||
|
||||
/* Synchronize PHI2, RAS, CAS */
|
||||
always @(posedge RCLK) begin
|
||||
PHI2r <= PHI2; PHI2r2 <= PHI2r; PHI2r3 <= PHI2r2;
|
||||
RASr <= ~nCRAS; RASr2 <= RASr; RASr3 <= RASr2;
|
||||
CASr <= ~nCCAS; CASr2 <= CASr; CASr3 <= CASr2;
|
||||
end
|
||||
|
||||
/* Latch 65816 bank when PHI2 rises */
|
||||
always @(posedge PHI2) begin
|
||||
if (Ready) RA11 <= (Din[6] & ~n8MEGEN) ^ XOR8MEG; // Set RA11
|
||||
else RA11 <= 1'b0; // Reserved in mode register
|
||||
Bank[7:0] <= Din[7:0]; // Latch bank
|
||||
end
|
||||
|
||||
/* Latch bank address, row address, WE, and CAS when RAS falls */
|
||||
always @(negedge nCRAS) begin
|
||||
if (Ready) begin
|
||||
RBA[1:0] <= CROW[1:0];
|
||||
RowA[9:0] <= MAin[9:0];
|
||||
end else begin
|
||||
RBA[1:0] <= 2'b00; // Reserved in mode register
|
||||
RowA[9] <= 1'b1; // "1" for single write mode
|
||||
RowA[8] <= 1'b0; // Reserved
|
||||
RowA[7] <= 1'b0; // "0" for not test mode
|
||||
RowA[6:4] <= 3'b010; // "2" for CAS latency 2
|
||||
RowA[3] <= 1'b0; // "0" for sequential burst (not used)
|
||||
RowA[2:0] <= 3'b000; // "0" for burst length 1 (no burst)
|
||||
end
|
||||
FWEr <= ~nFWE;
|
||||
CBR <= ~nCCAS;
|
||||
end
|
||||
|
||||
/* Latch write data when CAS falls */
|
||||
always @(negedge nCCAS) begin
|
||||
WRD[7:0] <= Din[7:0];
|
||||
end
|
||||
|
||||
/* State counter from RAS */
|
||||
always @(posedge RCLK) begin
|
||||
if (~RASr2) S <= 0;
|
||||
else if (S==2'h3) S <= 2'h3;
|
||||
else S <= S+1;
|
||||
end
|
||||
/* Init state counter */
|
||||
always @(posedge RCLK) begin
|
||||
// Wait ~4.178ms (at 62.5 MHz) before starting init sequence
|
||||
FS <= FS+1;
|
||||
if (FS[17:10] == 8'hFF) InitReady <= 1'b1;
|
||||
end
|
||||
|
||||
/* SDRAM CKE */
|
||||
always @(posedge RCLK) begin
|
||||
// Only 1 LUT4 allowed for this function!
|
||||
RCKE <= ((RASr | RASr2) & RCKEEN) | (~RASr2 & RASr3);
|
||||
end
|
||||
|
||||
/* SDRAM command */
|
||||
always @(posedge RCLK) begin
|
||||
if (Ready) begin
|
||||
if (S==0) begin
|
||||
if (RASr2) begin
|
||||
if (CBR) begin
|
||||
// AREF
|
||||
nRCS <= 1'b0;
|
||||
nRRAS <= 1'b0;
|
||||
nRCAS <= 1'b0;
|
||||
nRWE <= 1'b1;
|
||||
RA10 <= 1'b1; // RA10 is don't care
|
||||
end else begin
|
||||
// ACT
|
||||
nRCS <= 1'b0;
|
||||
nRRAS <= 1'b0;
|
||||
nRCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
RA10 <= 1'b1; // Bank RA10 consistently "1"
|
||||
end
|
||||
// Enable clock only for reads
|
||||
RCKEEN <= ~CBR & ~FWEr;
|
||||
end else if (RCKE) begin
|
||||
// PCall
|
||||
nRCS <= 1'b0;
|
||||
nRRAS <= 1'b0;
|
||||
nRCAS <= 1'b1;
|
||||
nRWE <= 1'b0;
|
||||
RA10 <= 1'b1; // "all"
|
||||
RCKEEN <= 1'b1;
|
||||
end else begin
|
||||
// NOP
|
||||
nRCS <= 1'b1;
|
||||
nRRAS <= 1'b1;
|
||||
nRCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
RA10 <= 1'b1; // RA10 is don't care
|
||||
RCKEEN <= 1'b1;
|
||||
end
|
||||
nRowColSel <= 1'b0; // Select registered row addres
|
||||
end else if (S==1) begin
|
||||
// NOP
|
||||
nRCS <= 1'b1;
|
||||
nRRAS <= 1'b1;
|
||||
nRCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
RA10 <= 1'b1; // RA10 is don't care
|
||||
nRowColSel <= 1'b1; // Select asynchronous column address
|
||||
RCKEEN <= ~CBR; // Disable clock if refresh cycle
|
||||
end else if (S==2) begin
|
||||
if (~FWEr & ~CBR) begin
|
||||
// RD
|
||||
nRCS <= 1'b0;
|
||||
nRRAS <= 1'b1;
|
||||
nRCAS <= 1'b0;
|
||||
nRWE <= 1'b1;
|
||||
RA10 <= 1'b1; // Auto-precharge
|
||||
end else begin
|
||||
// NOP
|
||||
nRCS <= 1'b1;
|
||||
nRRAS <= 1'b1;
|
||||
nRCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
RA10 <= 1'b1; // RA10 is don't care
|
||||
end
|
||||
nRowColSel <= 1'b1; // Select asynchronous column address
|
||||
RCKEEN <= ~CBR & FWEr; // Enable clock only for writes
|
||||
end else if (S==3) begin
|
||||
if (CASr2 & ~CASr3 & ~CBR & FWEr) begin
|
||||
// WR
|
||||
nRCS <= 1'b0;
|
||||
nRRAS <= 1'b1;
|
||||
nRCAS <= 1'b0;
|
||||
nRWE <= 1'b0;
|
||||
RA10 <= 1'b1; // Auto-precharge
|
||||
end else begin
|
||||
// NOP
|
||||
nRCS <= 1'b1;
|
||||
nRRAS <= 1'b1;
|
||||
nRCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
RA10 <= 1'b1; // RA10 is don't care
|
||||
end
|
||||
nRowColSel <= ~(~FWEr | CASr3 | CBR);
|
||||
RCKEEN <= ~(~FWEr | CASr2 | CBR);
|
||||
end
|
||||
end else if (InitReady) begin
|
||||
if (S==0 & RASr2) begin
|
||||
if (IS==0) begin
|
||||
// NOP
|
||||
nRCS <= 1'b1;
|
||||
nRRAS <= 1'b1;
|
||||
nRCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
RA10 <= 1'b1; // RA10 is don't care
|
||||
end else if (IS==1) begin
|
||||
// PC all
|
||||
nRCS <= 1'b0;
|
||||
nRRAS <= 1'b0;
|
||||
nRCAS <= 1'b1;
|
||||
nRWE <= 1'b0;
|
||||
RA10 <= 1'b1; // "all"
|
||||
end else if (IS==9) begin
|
||||
// Load mode register
|
||||
nRCS <= 1'b0;
|
||||
nRRAS <= 1'b0;
|
||||
nRCAS <= 1'b0;
|
||||
nRWE <= 1'b0;
|
||||
RA10 <= 1'b0; // Reserved in mode register
|
||||
end else begin
|
||||
// AREF
|
||||
nRCS <= 1'b0;
|
||||
nRRAS <= 1'b0;
|
||||
nRCAS <= 1'b0;
|
||||
nRWE <= 1'b1;
|
||||
RA10 <= 1'b1; // RA10 is don't care
|
||||
end
|
||||
IS <= IS+1;
|
||||
end else begin
|
||||
// NOP
|
||||
nRCS <= 1'b1;
|
||||
nRRAS <= 1'b1;
|
||||
nRCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
RA10 <= 1'b1; // RA10 is don't care
|
||||
end
|
||||
if (S==3 & ~RASr2 & IS==15) Ready <= 1'b1;
|
||||
nRowColSel <= 1'b0; // Select registered row address
|
||||
RCKEEN <= 1'b1;
|
||||
end else begin
|
||||
// NOP
|
||||
nRCS <= 1'b1;
|
||||
nRRAS <= 1'b1;
|
||||
nRCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
RA10 <= 1'b1; // RA10 is don't care
|
||||
nRowColSel <= 1'b0; // Select registered row address
|
||||
RCKEEN <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
/* Submit command when PHI2 falls */
|
||||
always @(negedge PHI2) begin
|
||||
// Magic number check
|
||||
if (C1WR & Din[7:0]==8'hC1) begin // "C1" magic number
|
||||
if (ADSubmitted) begin
|
||||
CmdEnable <= 1'b1;
|
||||
UFMOscEN <= 1'b1;
|
||||
end
|
||||
C1Submitted <= 1'b1;
|
||||
ADSubmitted <= 1'b0;
|
||||
end else if (ADWR & Din[7:0]==8'hAD) begin // "AD" magic number
|
||||
if (C1Submitted) begin
|
||||
CmdEnable <= 1'b1;
|
||||
UFMOscEN <= 1'b1;
|
||||
end
|
||||
ADSubmitted <= 1'b1;
|
||||
C1Submitted <= 1'b0;
|
||||
end else if (C1WR | ADWR) begin // wrong magic number submitted
|
||||
CmdEnable <= 1'b0;
|
||||
C1Submitted <= 1'b0;
|
||||
ADSubmitted <= 1'b0;
|
||||
end else if (CMDWR) CmdEnable <= 1'b0;
|
||||
|
||||
// Submit command
|
||||
if (CMDWR & CmdEnable) begin
|
||||
if (Din[7:4]==4'h0) begin
|
||||
XOR8MEG <= Din[0];
|
||||
end else if (Din[7:4]==4'h1) begin
|
||||
Cmdn8MEGEN <= ~Din[0];
|
||||
CmdSubmitted <= 1'b1;
|
||||
end else if (Din[7:4]==4'h2) begin
|
||||
Cmdn8MEGEN <= n8MEGEN;
|
||||
CmdUFMErase <= Din[3];
|
||||
CmdUFMPrgm <= Din[2];
|
||||
CmdDRCLK <= Din[1];
|
||||
CmdDRDIn <= Din[0];
|
||||
CmdSubmitted <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
/* UFM Control */
|
||||
always @(posedge RCLK) begin
|
||||
if (~Ready) begin
|
||||
if (~UFMInitDone & FS[17:16]==2'b00) begin
|
||||
// Shift 0 into address register
|
||||
ARCLK <= FS[3]; // Clock address register
|
||||
ARShift <= 1'b1; // Shift 0 into address register
|
||||
DRCLK <= 1'b0; // Don't clock data register
|
||||
DRDIn <= 1'b0; // DRDIn is don't care
|
||||
DRShift <= 1'b0; // DRShift is don't care
|
||||
end else if (~UFMInitDone & FS[17:16]==2'b01 & FS[7:4]==4'h0) begin
|
||||
// Parallel transfer UFM data to shift register
|
||||
ARCLK <= 1'b0; // Don't clock address register
|
||||
ARShift <= 1'b0; // ARShift is don't care
|
||||
DRCLK <= FS[3]; // Clock data register
|
||||
DRDIn <= 1'b0; // DRDIn is don't care
|
||||
DRShift <= 1'b0; // Parallel transfer to data register
|
||||
end else if (~UFMInitDone & FS[17:16]==2'b01 & FS[7:4]==4'h4) begin
|
||||
// Shift UFM
|
||||
ARCLK <= 1'b0; // Don't clock address register
|
||||
ARShift <= 1'b0; // ARShift is don't care
|
||||
DRCLK <= FS[3]; // Clock data register
|
||||
DRDIn <= 1'b0; // DRDIn is don't care
|
||||
DRShift <= 1'b1; // Shift data register
|
||||
// Capture bit 15 of this UFM word in UFMD register
|
||||
if (FS[3:0]==4'h7) UFMD <= DRDOut;
|
||||
end else if (~UFMInitDone & FS[17:16]==2'b01 & FS[7:4]==4'h5) begin
|
||||
// Check saved capacity entry
|
||||
if (UFMD) UFMInitDone <= 1'b1; // If erased, quit iterating
|
||||
else begin // If valid setting here
|
||||
n8MEGEN <= ~DRDOut; // Set capacity setting
|
||||
// If last byte in sector, mark need to erase
|
||||
if (FS[15:8]==8'hFF) begin
|
||||
UFMReqErase <= 1'b1; // Mark need to wrap around
|
||||
UFMInitDone <= 1'b1; // Quit iterating
|
||||
end
|
||||
end
|
||||
end else if (~UFMInitDone & FS[17:16]==2'b01 & FS[7:4]==4'h6) begin
|
||||
// Increment UFM address
|
||||
ARCLK <= FS[3]; // Clock address register
|
||||
ARShift <= 1'b0; // Increment UFM address
|
||||
DRCLK <= 1'b0; // Don't clock data register
|
||||
DRDIn <= 1'b0; // DRDIn is don't care
|
||||
DRShift <= 1'b0; // DRShift is don't care
|
||||
end else if (FS[17:16]==2'b10 & UFMReqErase) begin
|
||||
// Shift 0 into address register
|
||||
ARCLK <= FS[3]; // Clock address register
|
||||
ARShift <= 1'b1; // Shift 0 into address register
|
||||
DRCLK <= 1'b0; // Don't clock data register
|
||||
DRDIn <= 1'b0; // DRDIn is don't care
|
||||
DRShift <= 1'b0; // DRShift is don't care
|
||||
end else begin
|
||||
// Don't do anything with UFM
|
||||
ARCLK <= 1'b0; // Don't clock address register
|
||||
ARShift <= 1'b0; // ARShift is don't care
|
||||
DRCLK <= 1'b0; // Don't clock data register
|
||||
DRDIn <= 1'b0; // DRDIn is don't care
|
||||
DRShift <= 1'b0; // DRShift is don't care
|
||||
end
|
||||
|
||||
// Don't erase or program UFM during initialization
|
||||
UFMErase <= 1'b0;
|
||||
UFMProgram <= 1'b0;
|
||||
end else begin
|
||||
// Can only shift UFM data register now
|
||||
ARCLK <= 1'b0;
|
||||
ARShift <= 1'b0;
|
||||
DRShift <= 1'b1;
|
||||
|
||||
// Set user command signals after PHI2 falls
|
||||
if (~PHI2r2 & PHI2r3 & CmdSubmitted) begin
|
||||
n8MEGEN <= Cmdn8MEGEN;
|
||||
DRCLK <= CmdDRCLK;
|
||||
DRDIn <= CmdDRDIn;
|
||||
end
|
||||
|
||||
// UFM programming sequence
|
||||
if (CmdUFMPrgm | CmdUFMErase) begin
|
||||
if (~UFMBusyReg & ~RTPBusyReg) begin
|
||||
if (UFMReqErase | CmdUFMErase) UFMErase <= 1'b1;
|
||||
else if (CmdUFMPrgm) UFMProgram <= 1'b1;
|
||||
end else if (UFMBusyReg) UFMReqErase <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
set_global_assignment -name IP_TOOL_NAME "ALTUFM_NONE"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.0"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "UFM.v"]
|
||||