RAM2GS/CPLD/LCMXO256C/impl1/RAM2GS_LCMXO256C_impl1_synplify.lpf

#
# Logical Preferences generated for Lattice by Synplify map202103lat, Build 070R.
#

# Period Constraints 
FREQUENCY PORT "PHI2" 2.9 MHz;
FREQUENCY PORT "nCCAS" 2.9 MHz;
FREQUENCY PORT "nCRAS" 2.9 MHz;
FREQUENCY PORT "RCLK" 62.5 MHz;


# Output Constraints 

# Input Constraints 

# Point-to-point Delay Constraints 



# Block Path Constraints 

BLOCK ASYNCPATHS;

# End of generated Logical Preferences.