MAX, MachXO, MachXO2 working
This commit is contained in:
Zane Kaminski
parent
43e816b74c
commit
a59177004e
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@ -1,9 +1,9 @@
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[Runmanager]
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Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1c\0\0\0\xd8\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0)
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||||
windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)
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headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0)
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[impl1%3CStrategy1%3E]
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isChecked=false
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isHidden=false
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isExpanded=false
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[Runmanager]
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||||
Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1c\0\0\0\xd8\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0)
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windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)
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headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0)
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[impl1%3CStrategy1%3E]
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isChecked=false
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isHidden=false
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isExpanded=false
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@ -1,3 +1,4 @@
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[General]
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Export.auto_tasks=Jedecgen
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PAR.auto_tasks=@@empty()
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[General]
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Export.auto_tasks=IBIS, TimingSimFileVlg, TimingSimFileVHD, Bitgen, Jedecgen
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PAR.auto_tasks=PARTrace, IOTiming
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Map.auto_tasks=MapTrace, MapVerilogSimFile, MapVHDLSimFile
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@ -9,6 +9,9 @@
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<Source name="REFB.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="impl1/impl1.xcf" type="Programming Project File" type_short="Programming">
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<Options/>
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</Source>
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<Source name="../RAM2GS-LCMXO2.lpf" type="Logic Preference" type_short="LPF">
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<Options/>
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</Source>
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@ -1,2 +0,0 @@
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BLOCK RESETPATHS;
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BLOCK ASYNCPATHS;
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@ -17,6 +17,142 @@ prj_src add -exclude "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.lpf
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<A name="pn230816210353"></A><B><U><big>pn230816210353</big></U></B>
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#Start recording tcl command: 8/16/2023 20:34:55
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#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
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prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
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prj_run Export -impl impl1
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prj_run Export -impl impl1
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prj_run Synthesis -impl impl1
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prj_run Map -impl impl1
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prj_run Export -impl impl1
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prj_run PAR -impl impl1
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prj_run Export -impl impl1
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prj_run Export -impl impl1
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prj_run Export -impl impl1
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prj_run Export -impl impl1
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prj_run Export -impl impl1
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prj_run Export -impl impl1
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prj_run Export -impl impl1
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prj_src add "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/REFB.v"
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prj_run Export -impl impl1
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prj_run Export -impl impl1
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prj_run Export -impl impl1
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prj_run Export -impl impl1
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prj_src add "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS.sdc"
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prj_run Export -impl impl1
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#Stop recording: 8/16/2023 21:03:53
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<A name="pn230819062748"></A><B><U><big>pn230819062748</big></U></B>
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#Start recording tcl command: 8/18/2023 08:16:23
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#Project Location: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
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prj_project open "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
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prj_run Export -impl impl1
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prj_run Export -impl impl1
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prj_run Synthesis -impl impl1
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#Stop recording: 8/19/2023 06:27:48
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<A name="pn230819062826"></A><B><U><big>pn230819062826</big></U></B>
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#Start recording tcl command: 8/19/2023 06:27:54
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#Project Location: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
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prj_project open "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
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prj_run Synthesis -impl impl1 -task Synplify_Synthesis
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#Stop recording: 8/19/2023 06:28:26
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<A name="pn230819062853"></A><B><U><big>pn230819062853</big></U></B>
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#Start recording tcl command: 8/19/2023 06:28:30
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#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
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prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
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prj_run Synthesis -impl impl1
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prj_project close
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#Stop recording: 8/19/2023 06:28:53
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<A name="pn230819062900"></A><B><U><big>pn230819062900</big></U></B>
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#Start recording tcl command: 8/19/2023 06:28:53
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#Project Location: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
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prj_project open "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
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prj_project close
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#Stop recording: 8/19/2023 06:29:00
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<A name="pn230819063021"></A><B><U><big>pn230819063021</big></U></B>
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#Start recording tcl command: 8/19/2023 06:29:00
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#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
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prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
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#Stop recording: 8/19/2023 06:30:21
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<A name="pn230819205234"></A><B><U><big>pn230819205234</big></U></B>
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#Start recording tcl command: 8/19/2023 06:30:42
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#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
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prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
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prj_run Export -impl impl1
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prj_run Export -impl impl1 -forceAll
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pgr_project save "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
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prj_src add -exclude "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
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prj_src enable "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
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pgr_program run
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pgr_program run
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pgr_program set -cable USB2
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pgr_program set -port FTUSB-0
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pgr_program run
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prj_run Export -impl impl1
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prj_run Export -impl impl1
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prj_run Export -impl impl1
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prj_run Export -impl impl1
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prj_run Export -impl impl1
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prj_run Export -impl impl1
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prj_run Export -impl impl1
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prj_run Export -impl impl1
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prj_run Export -impl impl1
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prj_run Export -impl impl1
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prj_run Export -impl impl1
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prj_run Export -impl impl1
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prj_run Export -impl impl1
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prj_run Export -impl impl1
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prj_run Export -impl impl1 -forceAll
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prj_run Export -impl impl1
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prj_run Export -impl impl1
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prj_run Export -impl impl1
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prj_run Export -impl impl1 -forceAll
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prj_run Export -impl impl1 -forceAll
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pgr_project save "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
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prj_run Export -impl impl1
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prj_run Export -impl impl1
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pgr_project close
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prj_run Export -impl impl1
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prj_run Export -impl impl1 -forceAll
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prj_run Export -impl impl1
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prj_run Export -impl impl1 -forceOne
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prj_run Export -impl impl1 -forceOne
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prj_run Export -impl impl1 -forceOne
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prj_run Export -impl impl1 -forceOne
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prj_project save
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prj_project close
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#Stop recording: 8/19/2023 20:52:34
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<A name="pn230820055534"></A><B><U><big>pn230820055534</big></U></B>
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#Start recording tcl command: 8/19/2023 21:54:38
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#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
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prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
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prj_run Export -impl impl1 -forceAll
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prj_project close
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#Stop recording: 8/20/2023 05:55:34
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<BR>
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<BR>
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<BR>
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@ -0,0 +1,7 @@
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#Start recording tcl command: 8/18/2023 08:16:23
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#Project Location: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
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prj_project open "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
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prj_run Export -impl impl1
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prj_run Export -impl impl1
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prj_run Synthesis -impl impl1
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#Stop recording: 8/19/2023 06:27:48
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@ -0,0 +1,5 @@
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#Start recording tcl command: 8/19/2023 06:27:54
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#Project Location: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
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prj_project open "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
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prj_run Synthesis -impl impl1 -task Synplify_Synthesis
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#Stop recording: 8/19/2023 06:28:26
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@ -0,0 +1,6 @@
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#Start recording tcl command: 8/19/2023 06:28:30
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#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
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prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
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prj_run Synthesis -impl impl1
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prj_project close
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#Stop recording: 8/19/2023 06:28:53
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@ -0,0 +1,5 @@
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#Start recording tcl command: 8/19/2023 06:28:53
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#Project Location: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
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prj_project open "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
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prj_project close
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#Stop recording: 8/19/2023 06:29:00
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@ -0,0 +1,4 @@
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#Start recording tcl command: 8/19/2023 06:29:00
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#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
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prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
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#Stop recording: 8/19/2023 06:30:21
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@ -0,0 +1,47 @@
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#Start recording tcl command: 8/19/2023 06:30:42
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#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
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prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
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prj_run Export -impl impl1
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prj_run Export -impl impl1 -forceAll
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pgr_project save "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
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prj_src add -exclude "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
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prj_src enable "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
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pgr_program run
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pgr_program run
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pgr_program set -cable USB2
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pgr_program set -port FTUSB-0
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pgr_program run
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prj_run Export -impl impl1
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prj_run Export -impl impl1
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prj_run Export -impl impl1
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prj_run Export -impl impl1
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prj_run Export -impl impl1
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prj_run Export -impl impl1
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prj_run Export -impl impl1
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prj_run Export -impl impl1
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prj_run Export -impl impl1
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prj_run Export -impl impl1
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prj_run Export -impl impl1
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prj_run Export -impl impl1
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prj_run Export -impl impl1
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prj_run Export -impl impl1
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prj_run Export -impl impl1 -forceAll
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prj_run Export -impl impl1
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prj_run Export -impl impl1
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prj_run Export -impl impl1
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prj_run Export -impl impl1 -forceAll
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prj_run Export -impl impl1 -forceAll
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pgr_project save "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
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prj_run Export -impl impl1
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prj_run Export -impl impl1
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pgr_project close
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prj_run Export -impl impl1
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prj_run Export -impl impl1 -forceAll
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prj_run Export -impl impl1
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prj_run Export -impl impl1 -forceOne
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prj_run Export -impl impl1 -forceOne
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prj_run Export -impl impl1 -forceOne
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prj_run Export -impl impl1 -forceOne
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prj_project save
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prj_project close
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#Stop recording: 8/19/2023 20:52:34
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@ -0,0 +1,6 @@
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#Start recording tcl command: 8/19/2023 21:54:38
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#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
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prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
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prj_run Export -impl impl1 -forceAll
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prj_project close
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#Stop recording: 8/20/2023 05:55:34
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@ -0,0 +1,4 @@
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#Start recording tcl command: 8/20/2023 05:55:58
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#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
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prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
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#Stop recording: 8/20/2023 05:56:26
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@ -4,9 +4,9 @@
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(keywordMap (keywordLevel 0))
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(status
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(written
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(timestamp 2023 8 16 20 52 2)
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(timestamp 2023 8 19 7 25 4)
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(program "SCUBA" (version "Diamond (64-bit) 3.12.1.454"))))
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(comment "C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 62.5 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640 ")
|
||||
(comment "C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 66.7 -ufm -ufm_ebr 190 -mem_size 1 -memfile ../RAM2GS-LCMXO2.mem -memformat hex -wb -dev 640 ")
|
||||
(library ORCLIB
|
||||
(edifLevel 0)
|
||||
(technology
|
||||
|
|
@ -287,9 +287,9 @@
|
|||
(property UFM_INIT_FILE_FORMAT
|
||||
(string "HEX"))
|
||||
(property UFM_INIT_FILE_NAME
|
||||
(string "NONE"))
|
||||
(string "../RAM2GS-LCMXO2.mem"))
|
||||
(property UFM_INIT_ALL_ZEROS
|
||||
(string "ENABLED"))
|
||||
(string "DISABLED"))
|
||||
(property UFM_INIT_START_PAGE
|
||||
(string "190"))
|
||||
(property UFM_INIT_PAGES
|
||||
|
|
@ -383,7 +383,7 @@
|
|||
(property EFB_I2C1
|
||||
(string "DISABLED"))
|
||||
(property EFB_WB_CLK_FREQ
|
||||
(string "62.5")))
|
||||
(string "66.7")))
|
||||
(net scuba_vhi
|
||||
(joined
|
||||
(portRef Z (instanceRef scuba_vhi_inst))
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<DiamondModule name="REFB" module="EFB" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2023 08 16 20:52:14.413" version="1.2" type="Module" synthesis="synplify" source_format="Verilog">
|
||||
<DiamondModule name="REFB" module="EFB" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2023 08 19 07:25:06.194" version="1.2" type="Module" synthesis="synplify" source_format="Verilog">
|
||||
<Package>
|
||||
<File name="REFB.lpc" type="lpc" modified="2023 08 16 20:52:02.825"/>
|
||||
<File name="REFB.v" type="top_level_verilog" modified="2023 08 16 20:52:02.871"/>
|
||||
<File name="REFB_tmpl.v" type="template_verilog" modified="2023 08 16 20:52:02.871"/>
|
||||
<File name="REFB.lpc" type="lpc" modified="2023 08 19 07:25:04.117"/>
|
||||
<File name="REFB.v" type="top_level_verilog" modified="2023 08 19 07:25:04.191"/>
|
||||
<File name="REFB_tmpl.v" type="template_verilog" modified="2023 08 19 07:25:04.191"/>
|
||||
</Package>
|
||||
</DiamondModule>
|
||||
|
|
|
|||
|
|
@ -1,141 +1,141 @@
|
|||
[Device]
|
||||
Family=machxo2
|
||||
PartType=LCMXO2-640HC
|
||||
PartName=LCMXO2-640HC-4TG100C
|
||||
SpeedGrade=4
|
||||
Package=TQFP100
|
||||
OperatingCondition=COM
|
||||
Status=S
|
||||
|
||||
[IP]
|
||||
VendorName=Lattice Semiconductor Corporation
|
||||
CoreType=LPM
|
||||
CoreStatus=Demo
|
||||
CoreName=EFB
|
||||
CoreRevision=1.2
|
||||
ModuleName=REFB
|
||||
SourceFormat=Verilog HDL
|
||||
ParameterFileVersion=1.0
|
||||
Date=08/16/2023
|
||||
Time=20:52:02
|
||||
|
||||
[Parameters]
|
||||
Verilog=1
|
||||
VHDL=0
|
||||
EDIF=1
|
||||
Destination=Synplicity
|
||||
Expression=BusA(0 to 7)
|
||||
Order=Big Endian [MSB:LSB]
|
||||
IO=0
|
||||
freq=
|
||||
i2c1=0
|
||||
i2c1config=0
|
||||
i2c1_addr=7-Bit Addressing
|
||||
i2c1_ce=0
|
||||
i2c1_freq=100
|
||||
i2c1_sa=10000
|
||||
i2c1_we=0
|
||||
i2c2=0
|
||||
i2c2_addr=7-Bit Addressing
|
||||
i2c2_ce=0
|
||||
i2c2_freq=100
|
||||
i2c2_sa=10000
|
||||
i2c2_we=0
|
||||
ufm_addr=7-Bit Addressing
|
||||
ufm_sa=10000
|
||||
pll=0
|
||||
pll_cnt=1
|
||||
spi=0
|
||||
spi_clkinv=0
|
||||
spi_cs=1
|
||||
spi_en=0
|
||||
spi_freq=1
|
||||
spi_lsb=0
|
||||
spi_mode=Slave
|
||||
spi_ib=0
|
||||
spi_ph=0
|
||||
spi_hs=0
|
||||
spi_rxo=0
|
||||
spi_rxr=0
|
||||
spi_txo=0
|
||||
spi_txr=0
|
||||
spi_we=0
|
||||
static_tc=Static
|
||||
tc=0
|
||||
tc_clkinv=Positive
|
||||
tc_ctr=1
|
||||
tc_div=1
|
||||
tc_ipcap=0
|
||||
tc_mode=CTCM
|
||||
tc_ocr=32767
|
||||
tc_oflow=1
|
||||
tc_o=TOGGLE
|
||||
tc_opcomp=0
|
||||
tc_osc=0
|
||||
tc_sa_oflow=0
|
||||
tc_top=65535
|
||||
ufm=1
|
||||
ufm0=0
|
||||
ufm1=0
|
||||
ufm2=0
|
||||
ufm3=0
|
||||
ufm_cfg0=0
|
||||
ufm_cfg1=0
|
||||
wb_clk_freq=62.5
|
||||
ufm_usage=SHARED_EBR_TAG
|
||||
ufm_ebr=190
|
||||
ufm_remain=
|
||||
mem_size=1
|
||||
ufm_start=
|
||||
ufm_init=0
|
||||
memfile=
|
||||
ufm_dt=hex
|
||||
ufm0_ebr=
|
||||
mem_size0=1
|
||||
ufm0_init=0
|
||||
memfile0=
|
||||
ufm0_dt=hex
|
||||
ufm1_ebr=
|
||||
mem_size1=1
|
||||
ufm1_init=0
|
||||
memfile1=
|
||||
ufm1_dt=hex
|
||||
ufm2_ebr=
|
||||
mem_size2=1
|
||||
ufm2_init=0
|
||||
memfile2=
|
||||
ufm2_dt=hex
|
||||
ufm3_ebr=
|
||||
mem_size3=1
|
||||
ufm3_init=0
|
||||
memfile3=
|
||||
ufm3_dt=hex
|
||||
ufm_cfg0_ebr=
|
||||
mem_size_cfg0=1
|
||||
ufm_cfg0_init=0
|
||||
memfile_cfg0=
|
||||
ufm_cfg0_dt=hex
|
||||
ufm_cfg1_ebr=
|
||||
mem_size_cfg1=1
|
||||
ufm_cfg1_init=0
|
||||
memfile_cfg1=
|
||||
ufm_cfg1_dt=hex
|
||||
wb=1
|
||||
boot_option=Internal
|
||||
efb_ufm=0
|
||||
boot_option_internal=Single Boot
|
||||
internal_ufm0=0
|
||||
internal_ufm1=0
|
||||
efb_ufm_boot=
|
||||
tamperdr=0
|
||||
t_pwd=0
|
||||
t_lockflash=0
|
||||
t_manmode=0
|
||||
t_jtagport=0
|
||||
t_sspiport=0
|
||||
t_sic2port=0
|
||||
t_wbport=0
|
||||
t_portlock=0
|
||||
|
||||
[Command]
|
||||
cmd_line= -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 62.5 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640
|
||||
[Device]
|
||||
Family=machxo2
|
||||
PartType=LCMXO2-640HC
|
||||
PartName=LCMXO2-640HC-4TG100C
|
||||
SpeedGrade=4
|
||||
Package=TQFP100
|
||||
OperatingCondition=COM
|
||||
Status=S
|
||||
|
||||
[IP]
|
||||
VendorName=Lattice Semiconductor Corporation
|
||||
CoreType=LPM
|
||||
CoreStatus=Demo
|
||||
CoreName=EFB
|
||||
CoreRevision=1.2
|
||||
ModuleName=REFB
|
||||
SourceFormat=Verilog HDL
|
||||
ParameterFileVersion=1.0
|
||||
Date=08/19/2023
|
||||
Time=07:25:04
|
||||
|
||||
[Parameters]
|
||||
Verilog=1
|
||||
VHDL=0
|
||||
EDIF=1
|
||||
Destination=Synplicity
|
||||
Expression=BusA(0 to 7)
|
||||
Order=Big Endian [MSB:LSB]
|
||||
IO=0
|
||||
freq=
|
||||
i2c1=0
|
||||
i2c1config=0
|
||||
i2c1_addr=7-Bit Addressing
|
||||
i2c1_ce=0
|
||||
i2c1_freq=100
|
||||
i2c1_sa=10000
|
||||
i2c1_we=0
|
||||
i2c2=0
|
||||
i2c2_addr=7-Bit Addressing
|
||||
i2c2_ce=0
|
||||
i2c2_freq=100
|
||||
i2c2_sa=10000
|
||||
i2c2_we=0
|
||||
ufm_addr=7-Bit Addressing
|
||||
ufm_sa=10000
|
||||
pll=0
|
||||
pll_cnt=1
|
||||
spi=0
|
||||
spi_clkinv=0
|
||||
spi_cs=1
|
||||
spi_en=0
|
||||
spi_freq=1
|
||||
spi_lsb=0
|
||||
spi_mode=Slave
|
||||
spi_ib=0
|
||||
spi_ph=0
|
||||
spi_hs=0
|
||||
spi_rxo=0
|
||||
spi_rxr=0
|
||||
spi_txo=0
|
||||
spi_txr=0
|
||||
spi_we=0
|
||||
static_tc=Static
|
||||
tc=0
|
||||
tc_clkinv=Positive
|
||||
tc_ctr=1
|
||||
tc_div=1
|
||||
tc_ipcap=0
|
||||
tc_mode=CTCM
|
||||
tc_ocr=32767
|
||||
tc_oflow=1
|
||||
tc_o=TOGGLE
|
||||
tc_opcomp=0
|
||||
tc_osc=0
|
||||
tc_sa_oflow=0
|
||||
tc_top=65535
|
||||
ufm=1
|
||||
ufm0=0
|
||||
ufm1=0
|
||||
ufm2=0
|
||||
ufm3=0
|
||||
ufm_cfg0=0
|
||||
ufm_cfg1=0
|
||||
wb_clk_freq=66.7
|
||||
ufm_usage=SHARED_EBR_TAG
|
||||
ufm_ebr=190
|
||||
ufm_remain=
|
||||
mem_size=1
|
||||
ufm_start=
|
||||
ufm_init=mem
|
||||
memfile=../RAM2GS-LCMXO2.mem
|
||||
ufm_dt=hex
|
||||
ufm0_ebr=
|
||||
mem_size0=1
|
||||
ufm0_init=0
|
||||
memfile0=
|
||||
ufm0_dt=hex
|
||||
ufm1_ebr=
|
||||
mem_size1=1
|
||||
ufm1_init=0
|
||||
memfile1=
|
||||
ufm1_dt=hex
|
||||
ufm2_ebr=
|
||||
mem_size2=1
|
||||
ufm2_init=0
|
||||
memfile2=
|
||||
ufm2_dt=hex
|
||||
ufm3_ebr=
|
||||
mem_size3=1
|
||||
ufm3_init=0
|
||||
memfile3=
|
||||
ufm3_dt=hex
|
||||
ufm_cfg0_ebr=
|
||||
mem_size_cfg0=1
|
||||
ufm_cfg0_init=0
|
||||
memfile_cfg0=
|
||||
ufm_cfg0_dt=hex
|
||||
ufm_cfg1_ebr=
|
||||
mem_size_cfg1=1
|
||||
ufm_cfg1_init=0
|
||||
memfile_cfg1=
|
||||
ufm_cfg1_dt=hex
|
||||
wb=1
|
||||
boot_option=Internal
|
||||
efb_ufm=0
|
||||
boot_option_internal=Single Boot
|
||||
internal_ufm0=0
|
||||
internal_ufm1=0
|
||||
efb_ufm_boot=
|
||||
tamperdr=0
|
||||
t_pwd=0
|
||||
t_lockflash=0
|
||||
t_manmode=0
|
||||
t_jtagport=0
|
||||
t_sspiport=0
|
||||
t_sic2port=0
|
||||
t_wbport=0
|
||||
t_portlock=0
|
||||
|
||||
[Command]
|
||||
cmd_line= -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 66.7 -ufm -ufm_ebr 190 -mem_size 1 -memfile ../RAM2GS-LCMXO2.mem -memformat hex -wb -dev 640
|
||||
|
|
|
|||
|
|
@ -1,31 +1,31 @@
|
|||
wb_clk_i i
|
||||
wb_rst_i i
|
||||
wb_cyc_i i
|
||||
wb_stb_i i
|
||||
wb_we_i i
|
||||
wb_adr_i[7] i
|
||||
wb_adr_i[6] i
|
||||
wb_adr_i[5] i
|
||||
wb_adr_i[4] i
|
||||
wb_adr_i[3] i
|
||||
wb_adr_i[2] i
|
||||
wb_adr_i[1] i
|
||||
wb_adr_i[0] i
|
||||
wb_dat_i[7] i
|
||||
wb_dat_i[6] i
|
||||
wb_dat_i[5] i
|
||||
wb_dat_i[4] i
|
||||
wb_dat_i[3] i
|
||||
wb_dat_i[2] i
|
||||
wb_dat_i[1] i
|
||||
wb_dat_i[0] i
|
||||
wb_dat_o[7] o
|
||||
wb_dat_o[6] o
|
||||
wb_dat_o[5] o
|
||||
wb_dat_o[4] o
|
||||
wb_dat_o[3] o
|
||||
wb_dat_o[2] o
|
||||
wb_dat_o[1] o
|
||||
wb_dat_o[0] o
|
||||
wb_ack_o o
|
||||
wbc_ufm_irq o
|
||||
wb_clk_i i
|
||||
wb_rst_i i
|
||||
wb_cyc_i i
|
||||
wb_stb_i i
|
||||
wb_we_i i
|
||||
wb_adr_i[7] i
|
||||
wb_adr_i[6] i
|
||||
wb_adr_i[5] i
|
||||
wb_adr_i[4] i
|
||||
wb_adr_i[3] i
|
||||
wb_adr_i[2] i
|
||||
wb_adr_i[1] i
|
||||
wb_adr_i[0] i
|
||||
wb_dat_i[7] i
|
||||
wb_dat_i[6] i
|
||||
wb_dat_i[5] i
|
||||
wb_dat_i[4] i
|
||||
wb_dat_i[3] i
|
||||
wb_dat_i[2] i
|
||||
wb_dat_i[1] i
|
||||
wb_dat_i[0] i
|
||||
wb_dat_o[7] o
|
||||
wb_dat_o[6] o
|
||||
wb_dat_o[5] o
|
||||
wb_dat_o[4] o
|
||||
wb_dat_o[3] o
|
||||
wb_dat_o[2] o
|
||||
wb_dat_o[1] o
|
||||
wb_dat_o[0] o
|
||||
wb_ack_o o
|
||||
wbc_ufm_irq o
|
||||
|
|
|
|||
|
|
@ -1 +1 @@
|
|||
REFB.v
|
||||
REFB.v
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
SCUBA, Version Diamond (64-bit) 3.12.1.454
|
||||
Wed Aug 16 20:52:02 2023
|
||||
Sat Aug 19 07:25:04 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
|
|
@ -7,7 +7,7 @@ Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
|||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 62.5 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640
|
||||
Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 66.7 -ufm -ufm_ebr 190 -mem_size 1 -memfile ../RAM2GS-LCMXO2.mem -memformat hex -wb -dev 640
|
||||
Circuit name : REFB
|
||||
Module type : efb
|
||||
Module Version : 1.2
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 */
|
||||
/* Module Version: 1.2 */
|
||||
/* C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 62.5 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640 */
|
||||
/* Wed Aug 16 20:52:02 2023 */
|
||||
/* C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 66.7 -ufm -ufm_ebr 190 -mem_size 1 -memfile ../RAM2GS-LCMXO2.mem -memformat hex -wb -dev 640 */
|
||||
/* Sat Aug 19 07:25:04 2023 */
|
||||
|
||||
|
||||
`timescale 1 ns / 1 ps
|
||||
|
|
@ -26,8 +26,8 @@ module REFB (wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i,
|
|||
VLO scuba_vlo_inst (.Z(scuba_vlo));
|
||||
|
||||
defparam EFBInst_0.UFM_INIT_FILE_FORMAT = "HEX" ;
|
||||
defparam EFBInst_0.UFM_INIT_FILE_NAME = "NONE" ;
|
||||
defparam EFBInst_0.UFM_INIT_ALL_ZEROS = "ENABLED" ;
|
||||
defparam EFBInst_0.UFM_INIT_FILE_NAME = "../RAM2GS-LCMXO2.mem" ;
|
||||
defparam EFBInst_0.UFM_INIT_ALL_ZEROS = "DISABLED" ;
|
||||
defparam EFBInst_0.UFM_INIT_START_PAGE = 190 ;
|
||||
defparam EFBInst_0.UFM_INIT_PAGES = 1 ;
|
||||
defparam EFBInst_0.DEV_DENSITY = "640L" ;
|
||||
|
|
@ -74,7 +74,7 @@ module REFB (wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i,
|
|||
defparam EFBInst_0.I2C1_SLAVE_ADDR = "0b1000001" ;
|
||||
defparam EFBInst_0.I2C1_ADDRESSING = "7BIT" ;
|
||||
defparam EFBInst_0.EFB_I2C1 = "DISABLED" ;
|
||||
defparam EFBInst_0.EFB_WB_CLK_FREQ = "62.5" ;
|
||||
defparam EFBInst_0.EFB_WB_CLK_FREQ = "66.7" ;
|
||||
EFB EFBInst_0 (.WBCLKI(wb_clk_i), .WBRSTI(wb_rst_i), .WBCYCI(wb_cyc_i),
|
||||
.WBSTBI(wb_stb_i), .WBWEI(wb_we_i), .WBADRI7(wb_adr_i[7]), .WBADRI6(wb_adr_i[6]),
|
||||
.WBADRI5(wb_adr_i[5]), .WBADRI4(wb_adr_i[4]), .WBADRI3(wb_adr_i[3]),
|
||||
|
|
|
|||
|
|
@ -1,44 +1,44 @@
|
|||
Starting process: Module
|
||||
|
||||
Starting process:
|
||||
|
||||
SCUBA, Version Diamond (64-bit) 3.12.1.454
|
||||
Wed Aug 16 20:52:02 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
BEGIN SCUBA Module Synthesis
|
||||
|
||||
Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 62.5 -ufm -ufm_ebr 190 -mem_size 1 -ufm_0 -wb -dev 640
|
||||
Circuit name : REFB
|
||||
Module type : efb
|
||||
Module Version : 1.2
|
||||
Ports :
|
||||
Inputs : wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i[7:0], wb_dat_i[7:0]
|
||||
Outputs : wb_dat_o[7:0], wb_ack_o, wbc_ufm_irq
|
||||
I/O buffer : not inserted
|
||||
EDIF output : REFB.edn
|
||||
Verilog output : REFB.v
|
||||
Verilog template : REFB_tmpl.v
|
||||
Verilog purpose : for synthesis and simulation
|
||||
Bus notation : big endian
|
||||
Report output : REFB.srp
|
||||
Estimated Resource Usage:
|
||||
|
||||
END SCUBA Module Synthesis
|
||||
|
||||
File: REFB.lpc created.
|
||||
|
||||
|
||||
End process: completed successfully.
|
||||
|
||||
|
||||
Total Warnings: 0
|
||||
|
||||
Total Errors: 0
|
||||
|
||||
|
||||
Starting process: Module
|
||||
|
||||
Starting process:
|
||||
|
||||
SCUBA, Version Diamond (64-bit) 3.12.1.454
|
||||
Sat Aug 19 07:25:04 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
BEGIN SCUBA Module Synthesis
|
||||
|
||||
Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 66.7 -ufm -ufm_ebr 190 -mem_size 1 -memfile ../RAM2GS-LCMXO2.mem -memformat hex -wb -dev 640
|
||||
Circuit name : REFB
|
||||
Module type : efb
|
||||
Module Version : 1.2
|
||||
Ports :
|
||||
Inputs : wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i[7:0], wb_dat_i[7:0]
|
||||
Outputs : wb_dat_o[7:0], wb_ack_o, wbc_ufm_irq
|
||||
I/O buffer : not inserted
|
||||
EDIF output : REFB.edn
|
||||
Verilog output : REFB.v
|
||||
Verilog template : REFB_tmpl.v
|
||||
Verilog purpose : for synthesis and simulation
|
||||
Bus notation : big endian
|
||||
Report output : REFB.srp
|
||||
Estimated Resource Usage:
|
||||
|
||||
END SCUBA Module Synthesis
|
||||
|
||||
File: REFB.lpc created.
|
||||
|
||||
|
||||
End process: completed successfully.
|
||||
|
||||
|
||||
Total Warnings: 0
|
||||
|
||||
Total Errors: 0
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.12.1.454 */
|
||||
/* Module Version: 1.2 */
|
||||
/* Wed Aug 16 20:52:02 2023 */
|
||||
/* Sat Aug 19 07:25:04 2023 */
|
||||
|
||||
/* parameterized module instance */
|
||||
REFB __ (.wb_clk_i( ), .wb_rst_i( ), .wb_cyc_i( ), .wb_stb_i( ),
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,100 +1,100 @@
|
|||
#!/usr/local/bin/wish
|
||||
|
||||
proc GetPlatform {} {
|
||||
global tcl_platform
|
||||
|
||||
set cpu $tcl_platform(machine)
|
||||
|
||||
switch $cpu {
|
||||
intel -
|
||||
i*86* {
|
||||
set cpu ix86
|
||||
}
|
||||
x86_64 {
|
||||
if {$tcl_platform(wordSize) == 4} {
|
||||
set cpu ix86
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
switch $tcl_platform(platform) {
|
||||
windows {
|
||||
if {$cpu == "amd64"} {
|
||||
# Do not check wordSize, win32-x64 is an IL32P64 platform.
|
||||
set cpu x86_64
|
||||
}
|
||||
if {$cpu == "x86_64"} {
|
||||
return "nt64"
|
||||
} else {
|
||||
return "nt"
|
||||
}
|
||||
}
|
||||
unix {
|
||||
if {$tcl_platform(os) == "Linux"} {
|
||||
if {$cpu == "x86_64"} {
|
||||
return "lin64"
|
||||
} else {
|
||||
return "lin"
|
||||
}
|
||||
} else {
|
||||
return "sol"
|
||||
}
|
||||
}
|
||||
}
|
||||
return "nt"
|
||||
}
|
||||
|
||||
proc GetCmdLine {lpcfile} {
|
||||
global Para
|
||||
|
||||
if [catch {open $lpcfile r} fileid] {
|
||||
puts "Cannot open $para_file file!"
|
||||
exit -1
|
||||
}
|
||||
|
||||
seek $fileid 0 start
|
||||
set default_match 0
|
||||
while {[gets $fileid line] >= 0} {
|
||||
if {[string first "\[Command\]" $line] == 0} {
|
||||
set default_match 1
|
||||
continue
|
||||
}
|
||||
if {[string first "\[" $line] == 0} {
|
||||
set default_match 0
|
||||
}
|
||||
if {$default_match == 1} {
|
||||
if [regexp {([^=]*)=(.*)} $line match parameter value] {
|
||||
if [regexp {([ |\t]*;)} $parameter match] {continue}
|
||||
if [regexp {(.*)[ |\t]*;} $value match temp] {
|
||||
set Para($parameter) $temp
|
||||
} else {
|
||||
set Para($parameter) $value
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
set default_match 0
|
||||
close $fileid
|
||||
|
||||
return $Para(cmd_line)
|
||||
}
|
||||
|
||||
set platformpath [GetPlatform]
|
||||
set Para(sbp_path) [file dirname [info script]]
|
||||
set Para(install_dir) $env(TOOLRTF)
|
||||
set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
|
||||
|
||||
set scuba "$Para(FPGAPath)/scuba"
|
||||
set modulename "REFB"
|
||||
set lang "verilog"
|
||||
set lpcfile "$Para(sbp_path)/$modulename.lpc"
|
||||
set arch "xo2c00"
|
||||
set cmd_line [GetCmdLine $lpcfile]
|
||||
set fdcfile "$Para(sbp_path)/$modulename.fdc"
|
||||
if {[file exists $fdcfile] == 0} {
|
||||
append scuba " " $cmd_line
|
||||
} else {
|
||||
append scuba " " $cmd_line " " -fdc " " \"$fdcfile\"
|
||||
}
|
||||
set Para(result) [catch {eval exec "$scuba"} msg]
|
||||
#puts $msg
|
||||
#!/usr/local/bin/wish
|
||||
|
||||
proc GetPlatform {} {
|
||||
global tcl_platform
|
||||
|
||||
set cpu $tcl_platform(machine)
|
||||
|
||||
switch $cpu {
|
||||
intel -
|
||||
i*86* {
|
||||
set cpu ix86
|
||||
}
|
||||
x86_64 {
|
||||
if {$tcl_platform(wordSize) == 4} {
|
||||
set cpu ix86
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
switch $tcl_platform(platform) {
|
||||
windows {
|
||||
if {$cpu == "amd64"} {
|
||||
# Do not check wordSize, win32-x64 is an IL32P64 platform.
|
||||
set cpu x86_64
|
||||
}
|
||||
if {$cpu == "x86_64"} {
|
||||
return "nt64"
|
||||
} else {
|
||||
return "nt"
|
||||
}
|
||||
}
|
||||
unix {
|
||||
if {$tcl_platform(os) == "Linux"} {
|
||||
if {$cpu == "x86_64"} {
|
||||
return "lin64"
|
||||
} else {
|
||||
return "lin"
|
||||
}
|
||||
} else {
|
||||
return "sol"
|
||||
}
|
||||
}
|
||||
}
|
||||
return "nt"
|
||||
}
|
||||
|
||||
proc GetCmdLine {lpcfile} {
|
||||
global Para
|
||||
|
||||
if [catch {open $lpcfile r} fileid] {
|
||||
puts "Cannot open $para_file file!"
|
||||
exit -1
|
||||
}
|
||||
|
||||
seek $fileid 0 start
|
||||
set default_match 0
|
||||
while {[gets $fileid line] >= 0} {
|
||||
if {[string first "\[Command\]" $line] == 0} {
|
||||
set default_match 1
|
||||
continue
|
||||
}
|
||||
if {[string first "\[" $line] == 0} {
|
||||
set default_match 0
|
||||
}
|
||||
if {$default_match == 1} {
|
||||
if [regexp {([^=]*)=(.*)} $line match parameter value] {
|
||||
if [regexp {([ |\t]*;)} $parameter match] {continue}
|
||||
if [regexp {(.*)[ |\t]*;} $value match temp] {
|
||||
set Para($parameter) $temp
|
||||
} else {
|
||||
set Para($parameter) $value
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
set default_match 0
|
||||
close $fileid
|
||||
|
||||
return $Para(cmd_line)
|
||||
}
|
||||
|
||||
set platformpath [GetPlatform]
|
||||
set Para(sbp_path) [file dirname [info script]]
|
||||
set Para(install_dir) $env(TOOLRTF)
|
||||
set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
|
||||
|
||||
set scuba "$Para(FPGAPath)/scuba"
|
||||
set modulename "REFB"
|
||||
set lang "verilog"
|
||||
set lpcfile "$Para(sbp_path)/$modulename.lpc"
|
||||
set arch "xo2c00"
|
||||
set cmd_line [GetCmdLine $lpcfile]
|
||||
set fdcfile "$Para(sbp_path)/$modulename.fdc"
|
||||
if {[file exists $fdcfile] == 0} {
|
||||
append scuba " " $cmd_line
|
||||
} else {
|
||||
append scuba " " $cmd_line " " -fdc " " \"$fdcfile\"
|
||||
}
|
||||
set Para(result) [catch {eval exec "$scuba"} msg]
|
||||
#puts $msg
|
||||
|
|
|
|||
|
|
@ -1,74 +1,74 @@
|
|||
#!/usr/local/bin/wish
|
||||
|
||||
proc GetPlatform {} {
|
||||
global tcl_platform
|
||||
|
||||
set cpu $tcl_platform(machine)
|
||||
|
||||
switch $cpu {
|
||||
intel -
|
||||
i*86* {
|
||||
set cpu ix86
|
||||
}
|
||||
x86_64 {
|
||||
if {$tcl_platform(wordSize) == 4} {
|
||||
set cpu ix86
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
switch $tcl_platform(platform) {
|
||||
windows {
|
||||
if {$cpu == "amd64"} {
|
||||
# Do not check wordSize, win32-x64 is an IL32P64 platform.
|
||||
set cpu x86_64
|
||||
}
|
||||
if {$cpu == "x86_64"} {
|
||||
return "nt64"
|
||||
} else {
|
||||
return "nt"
|
||||
}
|
||||
}
|
||||
unix {
|
||||
if {$tcl_platform(os) == "Linux"} {
|
||||
if {$cpu == "x86_64"} {
|
||||
return "lin64"
|
||||
} else {
|
||||
return "lin"
|
||||
}
|
||||
} else {
|
||||
return "sol"
|
||||
}
|
||||
}
|
||||
}
|
||||
return "nt"
|
||||
}
|
||||
|
||||
set platformpath [GetPlatform]
|
||||
set Para(sbp_path) [file dirname [info script]]
|
||||
set Para(install_dir) $env(TOOLRTF)
|
||||
set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
|
||||
set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]"
|
||||
|
||||
set Para(ModuleName) "REFB"
|
||||
set Para(Module) "EFB"
|
||||
set Para(libname) machxo2
|
||||
set Para(arch_name) xo2c00
|
||||
set Para(PartType) "LCMXO2-640HC"
|
||||
|
||||
set Para(tech_syn) machxo2
|
||||
set Para(tech_cae) machxo2
|
||||
set Para(Package) "TQFP100"
|
||||
set Para(SpeedGrade) "4"
|
||||
set Para(FMax) "100"
|
||||
set fdcfile "$Para(sbp_path)/$Para(ModuleName).fdc"
|
||||
|
||||
#edif2ngd
|
||||
set edif2ngd "$Para(FPGAPath)/edif2ngd"
|
||||
set Para(result) [catch {eval exec $edif2ngd -l $Para(libname) -d $Para(PartType) -nopropwarn $Para(ModuleName).edn $Para(ModuleName).ngo} msg]
|
||||
#puts $msg
|
||||
|
||||
#ngdbuild
|
||||
set ngdbuild "$Para(FPGAPath)/ngdbuild"
|
||||
set Para(result) [catch {eval exec $ngdbuild -addiobuf -dt -a $Para(arch_name) $Para(ModuleName).ngo $Para(ModuleName).ngd} msg]
|
||||
#puts $msg
|
||||
#!/usr/local/bin/wish
|
||||
|
||||
proc GetPlatform {} {
|
||||
global tcl_platform
|
||||
|
||||
set cpu $tcl_platform(machine)
|
||||
|
||||
switch $cpu {
|
||||
intel -
|
||||
i*86* {
|
||||
set cpu ix86
|
||||
}
|
||||
x86_64 {
|
||||
if {$tcl_platform(wordSize) == 4} {
|
||||
set cpu ix86
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
switch $tcl_platform(platform) {
|
||||
windows {
|
||||
if {$cpu == "amd64"} {
|
||||
# Do not check wordSize, win32-x64 is an IL32P64 platform.
|
||||
set cpu x86_64
|
||||
}
|
||||
if {$cpu == "x86_64"} {
|
||||
return "nt64"
|
||||
} else {
|
||||
return "nt"
|
||||
}
|
||||
}
|
||||
unix {
|
||||
if {$tcl_platform(os) == "Linux"} {
|
||||
if {$cpu == "x86_64"} {
|
||||
return "lin64"
|
||||
} else {
|
||||
return "lin"
|
||||
}
|
||||
} else {
|
||||
return "sol"
|
||||
}
|
||||
}
|
||||
}
|
||||
return "nt"
|
||||
}
|
||||
|
||||
set platformpath [GetPlatform]
|
||||
set Para(sbp_path) [file dirname [info script]]
|
||||
set Para(install_dir) $env(TOOLRTF)
|
||||
set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
|
||||
set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]"
|
||||
|
||||
set Para(ModuleName) "REFB"
|
||||
set Para(Module) "EFB"
|
||||
set Para(libname) machxo2
|
||||
set Para(arch_name) xo2c00
|
||||
set Para(PartType) "LCMXO2-640HC"
|
||||
|
||||
set Para(tech_syn) machxo2
|
||||
set Para(tech_cae) machxo2
|
||||
set Para(Package) "TQFP100"
|
||||
set Para(SpeedGrade) "4"
|
||||
set Para(FMax) "100"
|
||||
set fdcfile "$Para(sbp_path)/$Para(ModuleName).fdc"
|
||||
|
||||
#edif2ngd
|
||||
set edif2ngd "$Para(FPGAPath)/edif2ngd"
|
||||
set Para(result) [catch {eval exec $edif2ngd -l $Para(libname) -d $Para(PartType) -nopropwarn $Para(ModuleName).edn $Para(ModuleName).ngo} msg]
|
||||
#puts $msg
|
||||
|
||||
#ngdbuild
|
||||
set ngdbuild "$Para(FPGAPath)/ngdbuild"
|
||||
set Para(result) [catch {eval exec $ngdbuild -addiobuf -dt -a $Para(arch_name) $Para(ModuleName).ngo $Para(ModuleName).ngd} msg]
|
||||
#puts $msg
|
||||
|
|
|
|||
|
|
@ -2,41 +2,54 @@
|
|||
<BuildStatus>
|
||||
<Strategy name="Strategy1">
|
||||
<Milestone name="Export" build_result="0" build_time="0">
|
||||
<Task name="IBIS" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="TimingSimFileVlg" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="TimingSimFileVHD" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="Bitgen" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="Jedecgen" build_result="2" update_result="0" update_time="1692233986"/>
|
||||
<Task name="IBIS" build_result="2" update_result="0" update_time="1692496517"/>
|
||||
<Task name="TimingSimFileVlg" build_result="2" update_result="0" update_time="1692496519"/>
|
||||
<Task name="TimingSimFileVHD" build_result="2" update_result="0" update_time="1692496520"/>
|
||||
<Task name="Bitgen" build_result="2" update_result="0" update_time="1692496523"/>
|
||||
<Task name="Jedecgen" build_result="2" update_result="0" update_time="1692496527"/>
|
||||
</Milestone>
|
||||
<Milestone name="Map" build_result="2" build_time="1692233977">
|
||||
<Task name="Map" build_result="2" update_result="0" update_time="1692233977"/>
|
||||
<Task name="MapTrace" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="MapVerilogSimFile" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="MapVHDLSimFile" build_result="0" update_result="3" update_time="0"/>
|
||||
<Milestone name="Map" build_result="2" build_time="1692496497">
|
||||
<Task name="Map" build_result="2" update_result="0" update_time="1692496497"/>
|
||||
<Task name="MapTrace" build_result="2" update_result="0" update_time="1692496498"/>
|
||||
<Task name="MapVerilogSimFile" build_result="2" update_result="0" update_time="1692496499"/>
|
||||
<Task name="MapVHDLSimFile" build_result="2" update_result="0" update_time="1692496501"/>
|
||||
</Milestone>
|
||||
<Milestone name="PAR" build_result="2" build_time="1692233984">
|
||||
<Task name="PAR" build_result="2" update_result="0" update_time="1692233984"/>
|
||||
<Task name="PARTrace" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="IOTiming" build_result="0" update_result="3" update_time="0"/>
|
||||
<Milestone name="PAR" build_result="2" build_time="1692496511">
|
||||
<Task name="PAR" build_result="2" update_result="0" update_time="1692496511"/>
|
||||
<Task name="PARTrace" build_result="2" update_result="0" update_time="1692496511"/>
|
||||
<Task name="IOTiming" build_result="2" update_result="0" update_time="1692496513"/>
|
||||
</Milestone>
|
||||
<Milestone name="Synthesis" build_result="2" build_time="1692233976">
|
||||
<Task name="Synplify_Synthesis" build_result="2" update_result="0" update_time="1692233976"/>
|
||||
<Milestone name="Synthesis" build_result="2" build_time="1692496496">
|
||||
<Task name="Synplify_Synthesis" build_result="2" update_result="0" update_time="1692496496"/>
|
||||
</Milestone>
|
||||
<Milestone name="TOOL_Report" build_result="0" build_time="0">
|
||||
<Task name="HDLE" build_result="0" update_result="2" update_time="1692233963"/>
|
||||
<Task name="BKM" build_result="0" update_result="2" update_time="1692233963"/>
|
||||
<Task name="HDLE" build_result="2" update_result="0" update_time="1692444754"/>
|
||||
<Task name="BKM" build_result="0" update_result="2" update_time="1692444754"/>
|
||||
<Task name="SSO" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="PIODRC" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="DEC" build_result="0" update_result="3" update_time="0"/>
|
||||
</Milestone>
|
||||
<Milestone name="Translate" build_result="2" build_time="1692233976">
|
||||
<Task name="Translate" build_result="2" update_result="0" update_time="1692233976"/>
|
||||
<Milestone name="Translate" build_result="2" build_time="1692496497">
|
||||
<Task name="Translate" build_result="2" update_result="0" update_time="1692496497"/>
|
||||
</Milestone>
|
||||
<Report name="LCMXO2_640HC_impl1.bgn" last_build_time="1692233986" last_build_size="4399"/>
|
||||
<Report name="LCMXO2_640HC_impl1.edi" last_build_time="1692233975" last_build_size="204145"/>
|
||||
<Report name="LCMXO2_640HC_impl1.jed" last_build_time="1692233986" last_build_size="177085"/>
|
||||
<Report name="LCMXO2_640HC_impl1.ncd" last_build_time="1692233984" last_build_size="278109"/>
|
||||
<Report name="LCMXO2_640HC_impl1.ngd" last_build_time="1692233976" last_build_size="207794"/>
|
||||
<Report name="LCMXO2_640HC_impl1_map.ncd" last_build_time="1692233977" last_build_size="197654"/>
|
||||
<Report name="IBIS/LCMXO2_640HC_impl1.ibs" last_build_time="1692496517" last_build_size="184928"/>
|
||||
<Report name="LCMXO2_640HC_impl1.bgn" last_build_time="1692496527" last_build_size="4359"/>
|
||||
<Report name="LCMXO2_640HC_impl1.bit" last_build_time="1692496523" last_build_size="6185"/>
|
||||
<Report name="LCMXO2_640HC_impl1.edi" last_build_time="1692496494" last_build_size="198884"/>
|
||||
<Report name="LCMXO2_640HC_impl1.ior" last_build_time="1692496513" last_build_size="6573"/>
|
||||
<Report name="LCMXO2_640HC_impl1.jed" last_build_time="1692496527" last_build_size="177085"/>
|
||||
<Report name="LCMXO2_640HC_impl1.ncd" last_build_time="1692496511" last_build_size="268674"/>
|
||||
<Report name="LCMXO2_640HC_impl1.ngd" last_build_time="1692496497" last_build_size="204730"/>
|
||||
<Report name="LCMXO2_640HC_impl1.tw1" last_build_time="1692496498" last_build_size="17550"/>
|
||||
<Report name="LCMXO2_640HC_impl1.twr" last_build_time="1692496511" last_build_size="90277"/>
|
||||
<Report name="LCMXO2_640HC_impl1_map.ncd" last_build_time="1692496497" last_build_size="193033"/>
|
||||
<Report name="LCMXO2_640HC_impl1_mapvho.sdf" last_build_time="1692496501" last_build_size="164487"/>
|
||||
<Report name="LCMXO2_640HC_impl1_mapvho.vho" last_build_time="1692496501" last_build_size="1365291"/>
|
||||
<Report name="LCMXO2_640HC_impl1_mapvo.sdf" last_build_time="1692496499" last_build_size="163556"/>
|
||||
<Report name="LCMXO2_640HC_impl1_mapvo.vo" last_build_time="1692496499" last_build_size="201461"/>
|
||||
<Report name="LCMXO2_640HC_impl1_vho.sdf" last_build_time="1692496520" last_build_size="181438"/>
|
||||
<Report name="LCMXO2_640HC_impl1_vho.vho" last_build_time="1692496520" last_build_size="1408234"/>
|
||||
<Report name="LCMXO2_640HC_impl1_vo.sdf" last_build_time="1692496519" last_build_size="180465"/>
|
||||
<Report name="LCMXO2_640HC_impl1_vo.vo" last_build_time="1692496519" last_build_size="212142"/>
|
||||
</Strategy>
|
||||
</BuildStatus>
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,71 +1,71 @@
|
|||
NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
|
||||
NOTE All Rights Reserved *
|
||||
NOTE DATE CREATED: Wed Aug 16 20:59:46 2023 *
|
||||
NOTE DESIGN NAME: RAM2GS *
|
||||
NOTE DEVICE NAME: LCMXO2-640HC-4TQFP100 *
|
||||
NOTE PIN ASSIGNMENTS *
|
||||
NOTE PINS RD[0] : 36 : inout *
|
||||
NOTE PINS Dout[0] : 76 : out *
|
||||
NOTE PINS PHI2 : 8 : in *
|
||||
NOTE PINS RDQML : 48 : out *
|
||||
NOTE PINS RDQMH : 51 : out *
|
||||
NOTE PINS nRCAS : 52 : out *
|
||||
NOTE PINS nRRAS : 54 : out *
|
||||
NOTE PINS nRWE : 49 : out *
|
||||
NOTE PINS RCKE : 53 : out *
|
||||
NOTE PINS RCLK : 62 : in *
|
||||
NOTE PINS nRCS : 57 : out *
|
||||
NOTE PINS RD[7] : 43 : inout *
|
||||
NOTE PINS RD[6] : 42 : inout *
|
||||
NOTE PINS RD[5] : 41 : inout *
|
||||
NOTE PINS RD[4] : 40 : inout *
|
||||
NOTE PINS RD[3] : 39 : inout *
|
||||
NOTE PINS RD[2] : 38 : inout *
|
||||
NOTE PINS RD[1] : 37 : inout *
|
||||
NOTE PINS RA[11] : 59 : out *
|
||||
NOTE PINS RA[10] : 64 : out *
|
||||
NOTE PINS RA[9] : 63 : out *
|
||||
NOTE PINS RA[8] : 65 : out *
|
||||
NOTE PINS RA[7] : 75 : out *
|
||||
NOTE PINS RA[6] : 68 : out *
|
||||
NOTE PINS RA[5] : 70 : out *
|
||||
NOTE PINS RA[4] : 74 : out *
|
||||
NOTE PINS RA[3] : 71 : out *
|
||||
NOTE PINS RA[2] : 69 : out *
|
||||
NOTE PINS RA[1] : 67 : out *
|
||||
NOTE PINS RA[0] : 66 : out *
|
||||
NOTE PINS RBA[1] : 60 : out *
|
||||
NOTE PINS RBA[0] : 58 : out *
|
||||
NOTE PINS LED : 34 : out *
|
||||
NOTE PINS nFWE : 15 : in *
|
||||
NOTE PINS nCRAS : 17 : in *
|
||||
NOTE PINS nCCAS : 9 : in *
|
||||
NOTE PINS Dout[7] : 82 : out *
|
||||
NOTE PINS Dout[6] : 78 : out *
|
||||
NOTE PINS Dout[5] : 84 : out *
|
||||
NOTE PINS Dout[4] : 83 : out *
|
||||
NOTE PINS Dout[3] : 85 : out *
|
||||
NOTE PINS Dout[2] : 87 : out *
|
||||
NOTE PINS Dout[1] : 86 : out *
|
||||
NOTE PINS Din[7] : 1 : in *
|
||||
NOTE PINS Din[6] : 2 : in *
|
||||
NOTE PINS Din[5] : 98 : in *
|
||||
NOTE PINS Din[4] : 99 : in *
|
||||
NOTE PINS Din[3] : 97 : in *
|
||||
NOTE PINS Din[2] : 88 : in *
|
||||
NOTE PINS Din[1] : 96 : in *
|
||||
NOTE PINS Din[0] : 3 : in *
|
||||
NOTE PINS CROW[1] : 16 : in *
|
||||
NOTE PINS CROW[0] : 10 : in *
|
||||
NOTE PINS MAin[9] : 32 : in *
|
||||
NOTE PINS MAin[8] : 25 : in *
|
||||
NOTE PINS MAin[7] : 18 : in *
|
||||
NOTE PINS MAin[6] : 24 : in *
|
||||
NOTE PINS MAin[5] : 19 : in *
|
||||
NOTE PINS MAin[4] : 20 : in *
|
||||
NOTE PINS MAin[3] : 21 : in *
|
||||
NOTE PINS MAin[2] : 13 : in *
|
||||
NOTE PINS MAin[1] : 12 : in *
|
||||
NOTE PINS MAin[0] : 14 : in *
|
||||
NOTE CONFIGURATION MODE: NONE *
|
||||
NOTE COMPRESSION: on *
|
||||
NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
|
||||
NOTE All Rights Reserved *
|
||||
NOTE DATE CREATED: Sat Aug 19 21:55:27 2023 *
|
||||
NOTE DESIGN NAME: RAM2GS *
|
||||
NOTE DEVICE NAME: LCMXO2-640HC-4TQFP100 *
|
||||
NOTE PIN ASSIGNMENTS *
|
||||
NOTE PINS RD[0] : 36 : inout *
|
||||
NOTE PINS Dout[0] : 76 : out *
|
||||
NOTE PINS PHI2 : 8 : in *
|
||||
NOTE PINS RDQML : 48 : out *
|
||||
NOTE PINS RDQMH : 51 : out *
|
||||
NOTE PINS nRCAS : 52 : out *
|
||||
NOTE PINS nRRAS : 54 : out *
|
||||
NOTE PINS nRWE : 49 : out *
|
||||
NOTE PINS RCKE : 53 : out *
|
||||
NOTE PINS RCLK : 62 : in *
|
||||
NOTE PINS nRCS : 57 : out *
|
||||
NOTE PINS RD[7] : 43 : inout *
|
||||
NOTE PINS RD[6] : 42 : inout *
|
||||
NOTE PINS RD[5] : 41 : inout *
|
||||
NOTE PINS RD[4] : 40 : inout *
|
||||
NOTE PINS RD[3] : 39 : inout *
|
||||
NOTE PINS RD[2] : 38 : inout *
|
||||
NOTE PINS RD[1] : 37 : inout *
|
||||
NOTE PINS RA[11] : 59 : out *
|
||||
NOTE PINS RA[10] : 64 : out *
|
||||
NOTE PINS RA[9] : 63 : out *
|
||||
NOTE PINS RA[8] : 65 : out *
|
||||
NOTE PINS RA[7] : 75 : out *
|
||||
NOTE PINS RA[6] : 68 : out *
|
||||
NOTE PINS RA[5] : 70 : out *
|
||||
NOTE PINS RA[4] : 74 : out *
|
||||
NOTE PINS RA[3] : 71 : out *
|
||||
NOTE PINS RA[2] : 69 : out *
|
||||
NOTE PINS RA[1] : 67 : out *
|
||||
NOTE PINS RA[0] : 66 : out *
|
||||
NOTE PINS RBA[1] : 60 : out *
|
||||
NOTE PINS RBA[0] : 58 : out *
|
||||
NOTE PINS LED : 34 : out *
|
||||
NOTE PINS nFWE : 15 : in *
|
||||
NOTE PINS nCRAS : 17 : in *
|
||||
NOTE PINS nCCAS : 9 : in *
|
||||
NOTE PINS Dout[7] : 82 : out *
|
||||
NOTE PINS Dout[6] : 78 : out *
|
||||
NOTE PINS Dout[5] : 84 : out *
|
||||
NOTE PINS Dout[4] : 83 : out *
|
||||
NOTE PINS Dout[3] : 85 : out *
|
||||
NOTE PINS Dout[2] : 87 : out *
|
||||
NOTE PINS Dout[1] : 86 : out *
|
||||
NOTE PINS Din[7] : 1 : in *
|
||||
NOTE PINS Din[6] : 2 : in *
|
||||
NOTE PINS Din[5] : 98 : in *
|
||||
NOTE PINS Din[4] : 99 : in *
|
||||
NOTE PINS Din[3] : 97 : in *
|
||||
NOTE PINS Din[2] : 88 : in *
|
||||
NOTE PINS Din[1] : 96 : in *
|
||||
NOTE PINS Din[0] : 3 : in *
|
||||
NOTE PINS CROW[1] : 16 : in *
|
||||
NOTE PINS CROW[0] : 10 : in *
|
||||
NOTE PINS MAin[9] : 32 : in *
|
||||
NOTE PINS MAin[8] : 25 : in *
|
||||
NOTE PINS MAin[7] : 18 : in *
|
||||
NOTE PINS MAin[6] : 24 : in *
|
||||
NOTE PINS MAin[5] : 19 : in *
|
||||
NOTE PINS MAin[4] : 20 : in *
|
||||
NOTE PINS MAin[3] : 21 : in *
|
||||
NOTE PINS MAin[2] : 13 : in *
|
||||
NOTE PINS MAin[1] : 12 : in *
|
||||
NOTE PINS MAin[0] : 14 : in *
|
||||
NOTE CONFIGURATION MODE: NONE *
|
||||
NOTE COMPRESSION: on *
|
||||
|
|
|
|||
|
|
@ -1,42 +1,43 @@
|
|||
----------------------------------------------------------------------
|
||||
Report for cell RAM2GS.verilog
|
||||
|
||||
Register bits: 109 of 640 (17%)
|
||||
PIC Latch: 0
|
||||
I/O cells: 63
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
BB 8 100.0
|
||||
CCU2D 10 100.0
|
||||
EFB 1 100.0
|
||||
FD1P3AX 27 100.0
|
||||
FD1P3IX 3 100.0
|
||||
FD1S3AX 51 100.0
|
||||
FD1S3IX 3 100.0
|
||||
GSR 1 100.0
|
||||
IB 25 100.0
|
||||
IFS1P3DX 9 100.0
|
||||
INV 8 100.0
|
||||
OB 30 100.0
|
||||
OFS1P3BX 4 100.0
|
||||
OFS1P3DX 11 100.0
|
||||
OFS1P3JX 1 100.0
|
||||
ORCALUT4 206 100.0
|
||||
PFUMX 1 100.0
|
||||
PUR 1 100.0
|
||||
VHI 2 100.0
|
||||
VLO 2 100.0
|
||||
SUB MODULES
|
||||
REFB 1 100.0
|
||||
|
||||
TOTAL 405
|
||||
----------------------------------------------------------------------
|
||||
Report for cell REFB.netlist
|
||||
Instance path: ufmefb
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
EFB 1 100.0
|
||||
VHI 1 50.0
|
||||
VLO 1 50.0
|
||||
|
||||
TOTAL 3
|
||||
----------------------------------------------------------------------
|
||||
Report for cell RAM2GS.verilog
|
||||
|
||||
Register bits: 111 of 640 (17%)
|
||||
PIC Latch: 0
|
||||
I/O cells: 63
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
BB 8 100.0
|
||||
CCU2D 10 100.0
|
||||
EFB 1 100.0
|
||||
FD1P3AX 28 100.0
|
||||
FD1P3IX 2 100.0
|
||||
FD1S3AX 52 100.0
|
||||
FD1S3IX 4 100.0
|
||||
GSR 1 100.0
|
||||
IB 25 100.0
|
||||
IFS1P3DX 9 100.0
|
||||
INV 6 100.0
|
||||
OB 30 100.0
|
||||
OFS1P3BX 4 100.0
|
||||
OFS1P3DX 11 100.0
|
||||
OFS1P3JX 1 100.0
|
||||
ORCALUT4 199 100.0
|
||||
PFUMX 3 100.0
|
||||
PUR 1 100.0
|
||||
VHI 2 100.0
|
||||
VLO 2 100.0
|
||||
SUB MODULES
|
||||
REFB 1 100.0
|
||||
|
||||
TOTAL 400
|
||||
----------------------------------------------------------------------
|
||||
Report for cell REFB.netlist
|
||||
Instance path: ufmefb
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
EFB 1 100.0
|
||||
ORCALUT4 1 0.5
|
||||
VHI 1 50.0
|
||||
VLO 1 50.0
|
||||
|
||||
TOTAL 4
|
||||
|
|
|
|||
|
|
@ -1,86 +1,86 @@
|
|||
BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454
|
||||
BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Wed Aug 16 20:59:44 2023
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Sat Aug 19 21:55:24 2023
|
||||
|
||||
|
||||
|
||||
Command: bitgen -g RamCfg:Reset -path D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC -w -jedec -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1.ncd LCMXO2_640HC_impl1.prf
|
||||
|
||||
Loading design for application Bitgen from file LCMXO2_640HC_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-640HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application Bitgen from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.39.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
|
||||
Running DRC.
|
||||
DRC detected 0 errors and 0 warnings.
|
||||
Reading Preference File from LCMXO2_640HC_impl1.prf.
|
||||
|
||||
Preference Summary:
|
||||
+---------------------------------+---------------------------------+
|
||||
| Preference | Current Setting |
|
||||
+---------------------------------+---------------------------------+
|
||||
| RamCfg | Reset** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MCCLK_FREQ | 2.08** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| CONFIG_SECURE | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| INBUF | ON** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| JTAG_PORT | ENABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SDM_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SLAVE_SPI_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MASTER_SPI_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| I2C_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MUX_CONFIGURATION_PORTS | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| CONFIGURATION | CFG** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| COMPRESS_CONFIG | ON** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MY_ASSP | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| ONE_TIME_PROGRAM | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| ENABLE_TRANSFR | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SHAREDEBRINIT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| BACKGROUND_RECONFIG | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
* Default setting.
|
||||
** The specified setting matches the default setting.
|
||||
|
||||
|
||||
Creating bit map...
|
||||
|
||||
Bitstream Status: Final Version 1.95.
|
||||
|
||||
Saving bit stream in "LCMXO2_640HC_impl1.jed".
|
||||
|
||||
===========
|
||||
UFM Summary.
|
||||
===========
|
||||
UFM Size: 191 Pages (128*191 Bits).
|
||||
UFM Utilization: General Purpose Flash Memory.
|
||||
|
||||
Available General Purpose Flash Memory: 191 Pages (Page 0 to Page 190).
|
||||
Initialized UFM Pages: 1 Page (Page 190).
|
||||
|
||||
Total CPU Time: 1 secs
|
||||
Total REAL Time: 2 secs
|
||||
Peak Memory Usage: 245 MB
|
||||
Command: bitgen -g RamCfg:Reset -path Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC -w -jedec -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1.ncd LCMXO2_640HC_impl1.prf
|
||||
|
||||
Loading design for application Bitgen from file LCMXO2_640HC_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-640HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application Bitgen from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.39.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
|
||||
Running DRC.
|
||||
DRC detected 0 errors and 0 warnings.
|
||||
Reading Preference File from LCMXO2_640HC_impl1.prf.
|
||||
|
||||
Preference Summary:
|
||||
+---------------------------------+---------------------------------+
|
||||
| Preference | Current Setting |
|
||||
+---------------------------------+---------------------------------+
|
||||
| RamCfg | Reset** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MCCLK_FREQ | 2.08** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| CONFIG_SECURE | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| INBUF | ON** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| JTAG_PORT | ENABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SDM_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SLAVE_SPI_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MASTER_SPI_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| I2C_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MUX_CONFIGURATION_PORTS | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| CONFIGURATION | CFG** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| COMPRESS_CONFIG | ON** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MY_ASSP | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| ONE_TIME_PROGRAM | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| ENABLE_TRANSFR | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SHAREDEBRINIT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| BACKGROUND_RECONFIG | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
* Default setting.
|
||||
** The specified setting matches the default setting.
|
||||
|
||||
|
||||
Creating bit map...
|
||||
|
||||
Bitstream Status: Final Version 1.95.
|
||||
|
||||
Saving bit stream in "LCMXO2_640HC_impl1.jed".
|
||||
|
||||
===========
|
||||
UFM Summary.
|
||||
===========
|
||||
UFM Size: 191 Pages (128*191 Bits).
|
||||
UFM Utilization: General Purpose Flash Memory.
|
||||
|
||||
Available General Purpose Flash Memory: 191 Pages (Page 0 to Page 190).
|
||||
Initialized UFM Pages: 1 Page (Page 190).
|
||||
|
||||
Total CPU Time: 3 secs
|
||||
Total REAL Time: 3 secs
|
||||
Peak Memory Usage: 266 MB
|
||||
|
|
|
|||
Binary file not shown.
Binary file not shown.
|
|
@ -1,273 +1,273 @@
|
|||
PAD Specification File
|
||||
***************************
|
||||
|
||||
PART TYPE: LCMXO2-640HC
|
||||
Performance Grade: 4
|
||||
PACKAGE: TQFP100
|
||||
Package Status: Final Version 1.39
|
||||
|
||||
Wed Aug 16 20:59:41 2023
|
||||
|
||||
Pinout by Port Name:
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties |
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
| CROW[0] | 10/3 | LVCMOS33_IN | PL3D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| CROW[1] | 16/3 | LVCMOS33_IN | PL6A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[0] | 3/3 | LVCMOS33_IN | PL2C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[1] | 96/0 | LVCMOS33_IN | PT6D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[2] | 88/0 | LVCMOS33_IN | PT9A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[3] | 97/0 | LVCMOS33_IN | PT6C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[4] | 99/0 | LVCMOS33_IN | PT6A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[5] | 98/0 | LVCMOS33_IN | PT6B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[6] | 2/3 | LVCMOS33_IN | PL2B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[7] | 1/3 | LVCMOS33_IN | PL2A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Dout[0] | 76/0 | LVCMOS33_OUT | PT11D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| Dout[1] | 86/0 | LVCMOS33_OUT | PT9C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| Dout[2] | 87/0 | LVCMOS33_OUT | PT9B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| Dout[3] | 85/0 | LVCMOS33_OUT | PT9D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| Dout[4] | 83/0 | LVCMOS33_OUT | PT10B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| Dout[5] | 84/0 | LVCMOS33_OUT | PT10A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| Dout[6] | 78/0 | LVCMOS33_OUT | PT11A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| Dout[7] | 82/0 | LVCMOS33_OUT | PT10C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| LED | 34/2 | LVCMOS33_OUT | PB6C | | | DRIVE:24mA PULL:KEEPER SLEW:SLOW |
|
||||
| MAin[0] | 14/3 | LVCMOS33_IN | PL5C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[1] | 12/3 | LVCMOS33_IN | PL5A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[2] | 13/3 | LVCMOS33_IN | PL5B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[3] | 21/3 | LVCMOS33_IN | PL7B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[4] | 20/3 | LVCMOS33_IN | PL7A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[5] | 19/3 | LVCMOS33_IN | PL6D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[6] | 24/3 | LVCMOS33_IN | PL7C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[7] | 18/3 | LVCMOS33_IN | PL6C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[8] | 25/3 | LVCMOS33_IN | PL7D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[9] | 32/2 | LVCMOS33_IN | PB6B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| PHI2 | 8/3 | LVCMOS33_IN | PL3B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| RA[0] | 66/1 | LVCMOS33_OUT | PR3D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[10] | 64/1 | LVCMOS33_OUT | PR5B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[11] | 59/1 | LVCMOS33_OUT | PR6B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[1] | 67/1 | LVCMOS33_OUT | PR3C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[2] | 69/1 | LVCMOS33_OUT | PR3A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[3] | 71/1 | LVCMOS33_OUT | PR2C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[4] | 74/1 | LVCMOS33_OUT | PR2B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[5] | 70/1 | LVCMOS33_OUT | PR2D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[6] | 68/1 | LVCMOS33_OUT | PR3B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[7] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[9] | 63/1 | LVCMOS33_OUT | PR5C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RBA[0] | 58/1 | LVCMOS33_OUT | PR6C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RBA[1] | 60/1 | LVCMOS33_OUT | PR6A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RCKE | 53/1 | LVCMOS33_OUT | PR7B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RCLK | 62/1 | LVCMOS33_IN | PR5D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| RDQMH | 51/1 | LVCMOS33_OUT | PR7D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RDQML | 48/2 | LVCMOS33_OUT | PB14C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RD[0] | 36/2 | LVCMOS33_BIDI | PB10A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[1] | 37/2 | LVCMOS33_BIDI | PB10B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[2] | 38/2 | LVCMOS33_BIDI | PB10C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[3] | 39/2 | LVCMOS33_BIDI | PB10D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[4] | 40/2 | LVCMOS33_BIDI | PB12A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[5] | 41/2 | LVCMOS33_BIDI | PB12B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[6] | 42/2 | LVCMOS33_BIDI | PB12C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[7] | 43/2 | LVCMOS33_BIDI | PB12D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| nCCAS | 9/3 | LVCMOS33_IN | PL3C | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nCRAS | 17/3 | LVCMOS33_IN | PL6B | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nFWE | 15/3 | LVCMOS33_IN | PL5D | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nRCAS | 52/1 | LVCMOS33_OUT | PR7C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| nRCS | 57/1 | LVCMOS33_OUT | PR6D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| nRRAS | 54/1 | LVCMOS33_OUT | PR7A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| nRWE | 49/2 | LVCMOS33_OUT | PB14D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
|
||||
Vccio by Bank:
|
||||
+------+-------+
|
||||
| Bank | Vccio |
|
||||
+------+-------+
|
||||
| 0 | 3.3V |
|
||||
| 1 | 3.3V |
|
||||
| 2 | 3.3V |
|
||||
| 3 | 3.3V |
|
||||
+------+-------+
|
||||
|
||||
Vref by Bank:
|
||||
+------+-----+-----------------+---------+
|
||||
| Vref | Pin | Bank # / Vref # | Load(s) |
|
||||
+------+-----+-----------------+---------+
|
||||
+------+-----+-----------------+---------+
|
||||
|
||||
Pinout by Pin Number:
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable |
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
| 1/3 | Din[7] | LOCATED | LVCMOS33_IN | PL2A | | | |
|
||||
| 2/3 | Din[6] | LOCATED | LVCMOS33_IN | PL2B | | | |
|
||||
| 3/3 | Din[0] | LOCATED | LVCMOS33_IN | PL2C | PCLKT3_2 | | |
|
||||
| 4/3 | unused, PULL:DOWN | | | PL2D | PCLKC3_2 | | |
|
||||
| 7/3 | unused, PULL:DOWN | | | PL3A | | | |
|
||||
| 8/3 | PHI2 | LOCATED | LVCMOS33_IN | PL3B | | | |
|
||||
| 9/3 | nCCAS | LOCATED | LVCMOS33_IN | PL3C | | | |
|
||||
| 10/3 | CROW[0] | LOCATED | LVCMOS33_IN | PL3D | | | |
|
||||
| 12/3 | MAin[1] | LOCATED | LVCMOS33_IN | PL5A | PCLKT3_1 | | |
|
||||
| 13/3 | MAin[2] | LOCATED | LVCMOS33_IN | PL5B | PCLKC3_1 | | |
|
||||
| 14/3 | MAin[0] | LOCATED | LVCMOS33_IN | PL5C | | | |
|
||||
| 15/3 | nFWE | LOCATED | LVCMOS33_IN | PL5D | | | |
|
||||
| 16/3 | CROW[1] | LOCATED | LVCMOS33_IN | PL6A | | | |
|
||||
| 17/3 | nCRAS | LOCATED | LVCMOS33_IN | PL6B | | | |
|
||||
| 18/3 | MAin[7] | LOCATED | LVCMOS33_IN | PL6C | | | |
|
||||
| 19/3 | MAin[5] | LOCATED | LVCMOS33_IN | PL6D | | | |
|
||||
| 20/3 | MAin[4] | LOCATED | LVCMOS33_IN | PL7A | PCLKT3_0 | | |
|
||||
| 21/3 | MAin[3] | LOCATED | LVCMOS33_IN | PL7B | PCLKC3_0 | | |
|
||||
| 24/3 | MAin[6] | LOCATED | LVCMOS33_IN | PL7C | | | |
|
||||
| 25/3 | MAin[8] | LOCATED | LVCMOS33_IN | PL7D | | | |
|
||||
| 27/2 | unused, PULL:DOWN | | | PB4A | CSSPIN | | |
|
||||
| 28/2 | unused, PULL:DOWN | | | PB4B | | | |
|
||||
| 29/2 | unused, PULL:DOWN | | | PB4C | | | |
|
||||
| 30/2 | unused, PULL:DOWN | | | PB4D | | | |
|
||||
| 31/2 | unused, PULL:DOWN | | | PB6A | MCLK/CCLK | | |
|
||||
| 32/2 | MAin[9] | LOCATED | LVCMOS33_IN | PB6B | SO/SPISO | | |
|
||||
| 34/2 | LED | LOCATED | LVCMOS33_OUT | PB6C | PCLKT2_0 | | |
|
||||
| 35/2 | unused, PULL:DOWN | | | PB6D | PCLKC2_0 | | |
|
||||
| 36/2 | RD[0] | LOCATED | LVCMOS33_BIDI | PB10A | | | |
|
||||
| 37/2 | RD[1] | LOCATED | LVCMOS33_BIDI | PB10B | | | |
|
||||
| 38/2 | RD[2] | LOCATED | LVCMOS33_BIDI | PB10C | PCLKT2_1 | | |
|
||||
| 39/2 | RD[3] | LOCATED | LVCMOS33_BIDI | PB10D | PCLKC2_1 | | |
|
||||
| 40/2 | RD[4] | LOCATED | LVCMOS33_BIDI | PB12A | | | |
|
||||
| 41/2 | RD[5] | LOCATED | LVCMOS33_BIDI | PB12B | | | |
|
||||
| 42/2 | RD[6] | LOCATED | LVCMOS33_BIDI | PB12C | | | |
|
||||
| 43/2 | RD[7] | LOCATED | LVCMOS33_BIDI | PB12D | | | |
|
||||
| 45/2 | unused, PULL:DOWN | | | PB14A | | | |
|
||||
| 47/2 | unused, PULL:DOWN | | | PB14B | | | |
|
||||
| 48/2 | RDQML | LOCATED | LVCMOS33_OUT | PB14C | SN | | |
|
||||
| 49/2 | nRWE | LOCATED | LVCMOS33_OUT | PB14D | SI/SISPI | | |
|
||||
| 51/1 | RDQMH | LOCATED | LVCMOS33_OUT | PR7D | | | |
|
||||
| 52/1 | nRCAS | LOCATED | LVCMOS33_OUT | PR7C | | | |
|
||||
| 53/1 | RCKE | LOCATED | LVCMOS33_OUT | PR7B | | | |
|
||||
| 54/1 | nRRAS | LOCATED | LVCMOS33_OUT | PR7A | | | |
|
||||
| 57/1 | nRCS | LOCATED | LVCMOS33_OUT | PR6D | | | |
|
||||
| 58/1 | RBA[0] | LOCATED | LVCMOS33_OUT | PR6C | | | |
|
||||
| 59/1 | RA[11] | LOCATED | LVCMOS33_OUT | PR6B | | | |
|
||||
| 60/1 | RBA[1] | LOCATED | LVCMOS33_OUT | PR6A | | | |
|
||||
| 62/1 | RCLK | LOCATED | LVCMOS33_IN | PR5D | PCLKC1_0 | | |
|
||||
| 63/1 | RA[9] | LOCATED | LVCMOS33_OUT | PR5C | PCLKT1_0 | | |
|
||||
| 64/1 | RA[10] | LOCATED | LVCMOS33_OUT | PR5B | | | |
|
||||
| 65/1 | RA[8] | LOCATED | LVCMOS33_OUT | PR5A | | | |
|
||||
| 66/1 | RA[0] | LOCATED | LVCMOS33_OUT | PR3D | | | |
|
||||
| 67/1 | RA[1] | LOCATED | LVCMOS33_OUT | PR3C | | | |
|
||||
| 68/1 | RA[6] | LOCATED | LVCMOS33_OUT | PR3B | | | |
|
||||
| 69/1 | RA[2] | LOCATED | LVCMOS33_OUT | PR3A | | | |
|
||||
| 70/1 | RA[5] | LOCATED | LVCMOS33_OUT | PR2D | | | |
|
||||
| 71/1 | RA[3] | LOCATED | LVCMOS33_OUT | PR2C | | | |
|
||||
| 74/1 | RA[4] | LOCATED | LVCMOS33_OUT | PR2B | | | |
|
||||
| 75/1 | RA[7] | LOCATED | LVCMOS33_OUT | PR2A | | | |
|
||||
| 76/0 | Dout[0] | LOCATED | LVCMOS33_OUT | PT11D | DONE | | |
|
||||
| 77/0 | unused, PULL:DOWN | | | PT11C | INITN | | |
|
||||
| 78/0 | Dout[6] | LOCATED | LVCMOS33_OUT | PT11A | | | |
|
||||
| 81/0 | unused, PULL:DOWN | | | PT10D | PROGRAMN | | |
|
||||
| 82/0 | Dout[7] | LOCATED | LVCMOS33_OUT | PT10C | JTAGENB | | |
|
||||
| 83/0 | Dout[4] | LOCATED | LVCMOS33_OUT | PT10B | | | |
|
||||
| 84/0 | Dout[5] | LOCATED | LVCMOS33_OUT | PT10A | | | |
|
||||
| 85/0 | Dout[3] | LOCATED | LVCMOS33_OUT | PT9D | SDA/PCLKC0_0 | | |
|
||||
| 86/0 | Dout[1] | LOCATED | LVCMOS33_OUT | PT9C | SCL/PCLKT0_0 | | |
|
||||
| 87/0 | Dout[2] | LOCATED | LVCMOS33_OUT | PT9B | PCLKC0_1 | | |
|
||||
| 88/0 | Din[2] | LOCATED | LVCMOS33_IN | PT9A | PCLKT0_1 | | |
|
||||
| 90/0 | Reserved: sysCONFIG | | | PT7D | TMS | | |
|
||||
| 91/0 | Reserved: sysCONFIG | | | PT7C | TCK | | |
|
||||
| 94/0 | Reserved: sysCONFIG | | | PT7B | TDI | | |
|
||||
| 95/0 | Reserved: sysCONFIG | | | PT7A | TDO | | |
|
||||
| 96/0 | Din[1] | LOCATED | LVCMOS33_IN | PT6D | | | |
|
||||
| 97/0 | Din[3] | LOCATED | LVCMOS33_IN | PT6C | | | |
|
||||
| 98/0 | Din[5] | LOCATED | LVCMOS33_IN | PT6B | | | |
|
||||
| 99/0 | Din[4] | LOCATED | LVCMOS33_IN | PT6A | | | |
|
||||
| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | |
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
|
||||
sysCONFIG Pins:
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode |
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
| PT7D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP |
|
||||
| PT7C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down |
|
||||
| PT7B | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP |
|
||||
| PT7A | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP |
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
|
||||
Dedicated sysCONFIG Pins:
|
||||
|
||||
|
||||
List of All Pins' Locate Preferences Based on Final Placement After PAR
|
||||
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste):
|
||||
|
||||
LOCATE COMP "CROW[0]" SITE "10";
|
||||
LOCATE COMP "CROW[1]" SITE "16";
|
||||
LOCATE COMP "Din[0]" SITE "3";
|
||||
LOCATE COMP "Din[1]" SITE "96";
|
||||
LOCATE COMP "Din[2]" SITE "88";
|
||||
LOCATE COMP "Din[3]" SITE "97";
|
||||
LOCATE COMP "Din[4]" SITE "99";
|
||||
LOCATE COMP "Din[5]" SITE "98";
|
||||
LOCATE COMP "Din[6]" SITE "2";
|
||||
LOCATE COMP "Din[7]" SITE "1";
|
||||
LOCATE COMP "Dout[0]" SITE "76";
|
||||
LOCATE COMP "Dout[1]" SITE "86";
|
||||
LOCATE COMP "Dout[2]" SITE "87";
|
||||
LOCATE COMP "Dout[3]" SITE "85";
|
||||
LOCATE COMP "Dout[4]" SITE "83";
|
||||
LOCATE COMP "Dout[5]" SITE "84";
|
||||
LOCATE COMP "Dout[6]" SITE "78";
|
||||
LOCATE COMP "Dout[7]" SITE "82";
|
||||
LOCATE COMP "LED" SITE "34";
|
||||
LOCATE COMP "MAin[0]" SITE "14";
|
||||
LOCATE COMP "MAin[1]" SITE "12";
|
||||
LOCATE COMP "MAin[2]" SITE "13";
|
||||
LOCATE COMP "MAin[3]" SITE "21";
|
||||
LOCATE COMP "MAin[4]" SITE "20";
|
||||
LOCATE COMP "MAin[5]" SITE "19";
|
||||
LOCATE COMP "MAin[6]" SITE "24";
|
||||
LOCATE COMP "MAin[7]" SITE "18";
|
||||
LOCATE COMP "MAin[8]" SITE "25";
|
||||
LOCATE COMP "MAin[9]" SITE "32";
|
||||
LOCATE COMP "PHI2" SITE "8";
|
||||
LOCATE COMP "RA[0]" SITE "66";
|
||||
LOCATE COMP "RA[10]" SITE "64";
|
||||
LOCATE COMP "RA[11]" SITE "59";
|
||||
LOCATE COMP "RA[1]" SITE "67";
|
||||
LOCATE COMP "RA[2]" SITE "69";
|
||||
LOCATE COMP "RA[3]" SITE "71";
|
||||
LOCATE COMP "RA[4]" SITE "74";
|
||||
LOCATE COMP "RA[5]" SITE "70";
|
||||
LOCATE COMP "RA[6]" SITE "68";
|
||||
LOCATE COMP "RA[7]" SITE "75";
|
||||
LOCATE COMP "RA[8]" SITE "65";
|
||||
LOCATE COMP "RA[9]" SITE "63";
|
||||
LOCATE COMP "RBA[0]" SITE "58";
|
||||
LOCATE COMP "RBA[1]" SITE "60";
|
||||
LOCATE COMP "RCKE" SITE "53";
|
||||
LOCATE COMP "RCLK" SITE "62";
|
||||
LOCATE COMP "RDQMH" SITE "51";
|
||||
LOCATE COMP "RDQML" SITE "48";
|
||||
LOCATE COMP "RD[0]" SITE "36";
|
||||
LOCATE COMP "RD[1]" SITE "37";
|
||||
LOCATE COMP "RD[2]" SITE "38";
|
||||
LOCATE COMP "RD[3]" SITE "39";
|
||||
LOCATE COMP "RD[4]" SITE "40";
|
||||
LOCATE COMP "RD[5]" SITE "41";
|
||||
LOCATE COMP "RD[6]" SITE "42";
|
||||
LOCATE COMP "RD[7]" SITE "43";
|
||||
LOCATE COMP "nCCAS" SITE "9";
|
||||
LOCATE COMP "nCRAS" SITE "17";
|
||||
LOCATE COMP "nFWE" SITE "15";
|
||||
LOCATE COMP "nRCAS" SITE "52";
|
||||
LOCATE COMP "nRCS" SITE "57";
|
||||
LOCATE COMP "nRRAS" SITE "54";
|
||||
LOCATE COMP "nRWE" SITE "49";
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Wed Aug 16 20:59:42 2023
|
||||
|
||||
PAD Specification File
|
||||
***************************
|
||||
|
||||
PART TYPE: LCMXO2-640HC
|
||||
Performance Grade: 4
|
||||
PACKAGE: TQFP100
|
||||
Package Status: Final Version 1.39
|
||||
|
||||
Sat Aug 19 21:55:06 2023
|
||||
|
||||
Pinout by Port Name:
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties |
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
| CROW[0] | 10/3 | LVCMOS33_IN | PL3D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| CROW[1] | 16/3 | LVCMOS33_IN | PL6A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[0] | 3/3 | LVCMOS33_IN | PL2C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[1] | 96/0 | LVCMOS33_IN | PT6D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[2] | 88/0 | LVCMOS33_IN | PT9A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[3] | 97/0 | LVCMOS33_IN | PT6C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[4] | 99/0 | LVCMOS33_IN | PT6A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[5] | 98/0 | LVCMOS33_IN | PT6B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[6] | 2/3 | LVCMOS33_IN | PL2B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[7] | 1/3 | LVCMOS33_IN | PL2A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Dout[0] | 76/0 | LVCMOS33_OUT | PT11D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| Dout[1] | 86/0 | LVCMOS33_OUT | PT9C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| Dout[2] | 87/0 | LVCMOS33_OUT | PT9B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| Dout[3] | 85/0 | LVCMOS33_OUT | PT9D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| Dout[4] | 83/0 | LVCMOS33_OUT | PT10B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| Dout[5] | 84/0 | LVCMOS33_OUT | PT10A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| Dout[6] | 78/0 | LVCMOS33_OUT | PT11A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| Dout[7] | 82/0 | LVCMOS33_OUT | PT10C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| LED | 34/2 | LVCMOS33_OUT | PB6C | | | DRIVE:24mA PULL:KEEPER SLEW:SLOW |
|
||||
| MAin[0] | 14/3 | LVCMOS33_IN | PL5C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[1] | 12/3 | LVCMOS33_IN | PL5A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[2] | 13/3 | LVCMOS33_IN | PL5B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[3] | 21/3 | LVCMOS33_IN | PL7B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[4] | 20/3 | LVCMOS33_IN | PL7A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[5] | 19/3 | LVCMOS33_IN | PL6D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[6] | 24/3 | LVCMOS33_IN | PL7C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[7] | 18/3 | LVCMOS33_IN | PL6C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[8] | 25/3 | LVCMOS33_IN | PL7D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[9] | 32/2 | LVCMOS33_IN | PB6B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| PHI2 | 8/3 | LVCMOS33_IN | PL3B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| RA[0] | 66/1 | LVCMOS33_OUT | PR3D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[10] | 64/1 | LVCMOS33_OUT | PR5B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[11] | 59/1 | LVCMOS33_OUT | PR6B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[1] | 67/1 | LVCMOS33_OUT | PR3C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[2] | 69/1 | LVCMOS33_OUT | PR3A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[3] | 71/1 | LVCMOS33_OUT | PR2C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[4] | 74/1 | LVCMOS33_OUT | PR2B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[5] | 70/1 | LVCMOS33_OUT | PR2D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[6] | 68/1 | LVCMOS33_OUT | PR3B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[7] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[9] | 63/1 | LVCMOS33_OUT | PR5C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RBA[0] | 58/1 | LVCMOS33_OUT | PR6C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RBA[1] | 60/1 | LVCMOS33_OUT | PR6A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RCKE | 53/1 | LVCMOS33_OUT | PR7B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RCLK | 62/1 | LVCMOS33_IN | PR5D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| RDQMH | 51/1 | LVCMOS33_OUT | PR7D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RDQML | 48/2 | LVCMOS33_OUT | PB14C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RD[0] | 36/2 | LVCMOS33_BIDI | PB10A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[1] | 37/2 | LVCMOS33_BIDI | PB10B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[2] | 38/2 | LVCMOS33_BIDI | PB10C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[3] | 39/2 | LVCMOS33_BIDI | PB10D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[4] | 40/2 | LVCMOS33_BIDI | PB12A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[5] | 41/2 | LVCMOS33_BIDI | PB12B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[6] | 42/2 | LVCMOS33_BIDI | PB12C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[7] | 43/2 | LVCMOS33_BIDI | PB12D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| nCCAS | 9/3 | LVCMOS33_IN | PL3C | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nCRAS | 17/3 | LVCMOS33_IN | PL6B | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nFWE | 15/3 | LVCMOS33_IN | PL5D | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nRCAS | 52/1 | LVCMOS33_OUT | PR7C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| nRCS | 57/1 | LVCMOS33_OUT | PR6D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| nRRAS | 54/1 | LVCMOS33_OUT | PR7A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| nRWE | 49/2 | LVCMOS33_OUT | PB14D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
|
||||
Vccio by Bank:
|
||||
+------+-------+
|
||||
| Bank | Vccio |
|
||||
+------+-------+
|
||||
| 0 | 3.3V |
|
||||
| 1 | 3.3V |
|
||||
| 2 | 3.3V |
|
||||
| 3 | 3.3V |
|
||||
+------+-------+
|
||||
|
||||
Vref by Bank:
|
||||
+------+-----+-----------------+---------+
|
||||
| Vref | Pin | Bank # / Vref # | Load(s) |
|
||||
+------+-----+-----------------+---------+
|
||||
+------+-----+-----------------+---------+
|
||||
|
||||
Pinout by Pin Number:
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable |
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
| 1/3 | Din[7] | LOCATED | LVCMOS33_IN | PL2A | | | |
|
||||
| 2/3 | Din[6] | LOCATED | LVCMOS33_IN | PL2B | | | |
|
||||
| 3/3 | Din[0] | LOCATED | LVCMOS33_IN | PL2C | PCLKT3_2 | | |
|
||||
| 4/3 | unused, PULL:DOWN | | | PL2D | PCLKC3_2 | | |
|
||||
| 7/3 | unused, PULL:DOWN | | | PL3A | | | |
|
||||
| 8/3 | PHI2 | LOCATED | LVCMOS33_IN | PL3B | | | |
|
||||
| 9/3 | nCCAS | LOCATED | LVCMOS33_IN | PL3C | | | |
|
||||
| 10/3 | CROW[0] | LOCATED | LVCMOS33_IN | PL3D | | | |
|
||||
| 12/3 | MAin[1] | LOCATED | LVCMOS33_IN | PL5A | PCLKT3_1 | | |
|
||||
| 13/3 | MAin[2] | LOCATED | LVCMOS33_IN | PL5B | PCLKC3_1 | | |
|
||||
| 14/3 | MAin[0] | LOCATED | LVCMOS33_IN | PL5C | | | |
|
||||
| 15/3 | nFWE | LOCATED | LVCMOS33_IN | PL5D | | | |
|
||||
| 16/3 | CROW[1] | LOCATED | LVCMOS33_IN | PL6A | | | |
|
||||
| 17/3 | nCRAS | LOCATED | LVCMOS33_IN | PL6B | | | |
|
||||
| 18/3 | MAin[7] | LOCATED | LVCMOS33_IN | PL6C | | | |
|
||||
| 19/3 | MAin[5] | LOCATED | LVCMOS33_IN | PL6D | | | |
|
||||
| 20/3 | MAin[4] | LOCATED | LVCMOS33_IN | PL7A | PCLKT3_0 | | |
|
||||
| 21/3 | MAin[3] | LOCATED | LVCMOS33_IN | PL7B | PCLKC3_0 | | |
|
||||
| 24/3 | MAin[6] | LOCATED | LVCMOS33_IN | PL7C | | | |
|
||||
| 25/3 | MAin[8] | LOCATED | LVCMOS33_IN | PL7D | | | |
|
||||
| 27/2 | unused, PULL:DOWN | | | PB4A | CSSPIN | | |
|
||||
| 28/2 | unused, PULL:DOWN | | | PB4B | | | |
|
||||
| 29/2 | unused, PULL:DOWN | | | PB4C | | | |
|
||||
| 30/2 | unused, PULL:DOWN | | | PB4D | | | |
|
||||
| 31/2 | unused, PULL:DOWN | | | PB6A | MCLK/CCLK | | |
|
||||
| 32/2 | MAin[9] | LOCATED | LVCMOS33_IN | PB6B | SO/SPISO | | |
|
||||
| 34/2 | LED | LOCATED | LVCMOS33_OUT | PB6C | PCLKT2_0 | | |
|
||||
| 35/2 | unused, PULL:DOWN | | | PB6D | PCLKC2_0 | | |
|
||||
| 36/2 | RD[0] | LOCATED | LVCMOS33_BIDI | PB10A | | | |
|
||||
| 37/2 | RD[1] | LOCATED | LVCMOS33_BIDI | PB10B | | | |
|
||||
| 38/2 | RD[2] | LOCATED | LVCMOS33_BIDI | PB10C | PCLKT2_1 | | |
|
||||
| 39/2 | RD[3] | LOCATED | LVCMOS33_BIDI | PB10D | PCLKC2_1 | | |
|
||||
| 40/2 | RD[4] | LOCATED | LVCMOS33_BIDI | PB12A | | | |
|
||||
| 41/2 | RD[5] | LOCATED | LVCMOS33_BIDI | PB12B | | | |
|
||||
| 42/2 | RD[6] | LOCATED | LVCMOS33_BIDI | PB12C | | | |
|
||||
| 43/2 | RD[7] | LOCATED | LVCMOS33_BIDI | PB12D | | | |
|
||||
| 45/2 | unused, PULL:DOWN | | | PB14A | | | |
|
||||
| 47/2 | unused, PULL:DOWN | | | PB14B | | | |
|
||||
| 48/2 | RDQML | LOCATED | LVCMOS33_OUT | PB14C | SN | | |
|
||||
| 49/2 | nRWE | LOCATED | LVCMOS33_OUT | PB14D | SI/SISPI | | |
|
||||
| 51/1 | RDQMH | LOCATED | LVCMOS33_OUT | PR7D | | | |
|
||||
| 52/1 | nRCAS | LOCATED | LVCMOS33_OUT | PR7C | | | |
|
||||
| 53/1 | RCKE | LOCATED | LVCMOS33_OUT | PR7B | | | |
|
||||
| 54/1 | nRRAS | LOCATED | LVCMOS33_OUT | PR7A | | | |
|
||||
| 57/1 | nRCS | LOCATED | LVCMOS33_OUT | PR6D | | | |
|
||||
| 58/1 | RBA[0] | LOCATED | LVCMOS33_OUT | PR6C | | | |
|
||||
| 59/1 | RA[11] | LOCATED | LVCMOS33_OUT | PR6B | | | |
|
||||
| 60/1 | RBA[1] | LOCATED | LVCMOS33_OUT | PR6A | | | |
|
||||
| 62/1 | RCLK | LOCATED | LVCMOS33_IN | PR5D | PCLKC1_0 | | |
|
||||
| 63/1 | RA[9] | LOCATED | LVCMOS33_OUT | PR5C | PCLKT1_0 | | |
|
||||
| 64/1 | RA[10] | LOCATED | LVCMOS33_OUT | PR5B | | | |
|
||||
| 65/1 | RA[8] | LOCATED | LVCMOS33_OUT | PR5A | | | |
|
||||
| 66/1 | RA[0] | LOCATED | LVCMOS33_OUT | PR3D | | | |
|
||||
| 67/1 | RA[1] | LOCATED | LVCMOS33_OUT | PR3C | | | |
|
||||
| 68/1 | RA[6] | LOCATED | LVCMOS33_OUT | PR3B | | | |
|
||||
| 69/1 | RA[2] | LOCATED | LVCMOS33_OUT | PR3A | | | |
|
||||
| 70/1 | RA[5] | LOCATED | LVCMOS33_OUT | PR2D | | | |
|
||||
| 71/1 | RA[3] | LOCATED | LVCMOS33_OUT | PR2C | | | |
|
||||
| 74/1 | RA[4] | LOCATED | LVCMOS33_OUT | PR2B | | | |
|
||||
| 75/1 | RA[7] | LOCATED | LVCMOS33_OUT | PR2A | | | |
|
||||
| 76/0 | Dout[0] | LOCATED | LVCMOS33_OUT | PT11D | DONE | | |
|
||||
| 77/0 | unused, PULL:DOWN | | | PT11C | INITN | | |
|
||||
| 78/0 | Dout[6] | LOCATED | LVCMOS33_OUT | PT11A | | | |
|
||||
| 81/0 | unused, PULL:DOWN | | | PT10D | PROGRAMN | | |
|
||||
| 82/0 | Dout[7] | LOCATED | LVCMOS33_OUT | PT10C | JTAGENB | | |
|
||||
| 83/0 | Dout[4] | LOCATED | LVCMOS33_OUT | PT10B | | | |
|
||||
| 84/0 | Dout[5] | LOCATED | LVCMOS33_OUT | PT10A | | | |
|
||||
| 85/0 | Dout[3] | LOCATED | LVCMOS33_OUT | PT9D | SDA/PCLKC0_0 | | |
|
||||
| 86/0 | Dout[1] | LOCATED | LVCMOS33_OUT | PT9C | SCL/PCLKT0_0 | | |
|
||||
| 87/0 | Dout[2] | LOCATED | LVCMOS33_OUT | PT9B | PCLKC0_1 | | |
|
||||
| 88/0 | Din[2] | LOCATED | LVCMOS33_IN | PT9A | PCLKT0_1 | | |
|
||||
| 90/0 | Reserved: sysCONFIG | | | PT7D | TMS | | |
|
||||
| 91/0 | Reserved: sysCONFIG | | | PT7C | TCK | | |
|
||||
| 94/0 | Reserved: sysCONFIG | | | PT7B | TDI | | |
|
||||
| 95/0 | Reserved: sysCONFIG | | | PT7A | TDO | | |
|
||||
| 96/0 | Din[1] | LOCATED | LVCMOS33_IN | PT6D | | | |
|
||||
| 97/0 | Din[3] | LOCATED | LVCMOS33_IN | PT6C | | | |
|
||||
| 98/0 | Din[5] | LOCATED | LVCMOS33_IN | PT6B | | | |
|
||||
| 99/0 | Din[4] | LOCATED | LVCMOS33_IN | PT6A | | | |
|
||||
| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | |
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
|
||||
sysCONFIG Pins:
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode |
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
| PT7D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP |
|
||||
| PT7C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down |
|
||||
| PT7B | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP |
|
||||
| PT7A | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP |
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
|
||||
Dedicated sysCONFIG Pins:
|
||||
|
||||
|
||||
List of All Pins' Locate Preferences Based on Final Placement After PAR
|
||||
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste):
|
||||
|
||||
LOCATE COMP "CROW[0]" SITE "10";
|
||||
LOCATE COMP "CROW[1]" SITE "16";
|
||||
LOCATE COMP "Din[0]" SITE "3";
|
||||
LOCATE COMP "Din[1]" SITE "96";
|
||||
LOCATE COMP "Din[2]" SITE "88";
|
||||
LOCATE COMP "Din[3]" SITE "97";
|
||||
LOCATE COMP "Din[4]" SITE "99";
|
||||
LOCATE COMP "Din[5]" SITE "98";
|
||||
LOCATE COMP "Din[6]" SITE "2";
|
||||
LOCATE COMP "Din[7]" SITE "1";
|
||||
LOCATE COMP "Dout[0]" SITE "76";
|
||||
LOCATE COMP "Dout[1]" SITE "86";
|
||||
LOCATE COMP "Dout[2]" SITE "87";
|
||||
LOCATE COMP "Dout[3]" SITE "85";
|
||||
LOCATE COMP "Dout[4]" SITE "83";
|
||||
LOCATE COMP "Dout[5]" SITE "84";
|
||||
LOCATE COMP "Dout[6]" SITE "78";
|
||||
LOCATE COMP "Dout[7]" SITE "82";
|
||||
LOCATE COMP "LED" SITE "34";
|
||||
LOCATE COMP "MAin[0]" SITE "14";
|
||||
LOCATE COMP "MAin[1]" SITE "12";
|
||||
LOCATE COMP "MAin[2]" SITE "13";
|
||||
LOCATE COMP "MAin[3]" SITE "21";
|
||||
LOCATE COMP "MAin[4]" SITE "20";
|
||||
LOCATE COMP "MAin[5]" SITE "19";
|
||||
LOCATE COMP "MAin[6]" SITE "24";
|
||||
LOCATE COMP "MAin[7]" SITE "18";
|
||||
LOCATE COMP "MAin[8]" SITE "25";
|
||||
LOCATE COMP "MAin[9]" SITE "32";
|
||||
LOCATE COMP "PHI2" SITE "8";
|
||||
LOCATE COMP "RA[0]" SITE "66";
|
||||
LOCATE COMP "RA[10]" SITE "64";
|
||||
LOCATE COMP "RA[11]" SITE "59";
|
||||
LOCATE COMP "RA[1]" SITE "67";
|
||||
LOCATE COMP "RA[2]" SITE "69";
|
||||
LOCATE COMP "RA[3]" SITE "71";
|
||||
LOCATE COMP "RA[4]" SITE "74";
|
||||
LOCATE COMP "RA[5]" SITE "70";
|
||||
LOCATE COMP "RA[6]" SITE "68";
|
||||
LOCATE COMP "RA[7]" SITE "75";
|
||||
LOCATE COMP "RA[8]" SITE "65";
|
||||
LOCATE COMP "RA[9]" SITE "63";
|
||||
LOCATE COMP "RBA[0]" SITE "58";
|
||||
LOCATE COMP "RBA[1]" SITE "60";
|
||||
LOCATE COMP "RCKE" SITE "53";
|
||||
LOCATE COMP "RCLK" SITE "62";
|
||||
LOCATE COMP "RDQMH" SITE "51";
|
||||
LOCATE COMP "RDQML" SITE "48";
|
||||
LOCATE COMP "RD[0]" SITE "36";
|
||||
LOCATE COMP "RD[1]" SITE "37";
|
||||
LOCATE COMP "RD[2]" SITE "38";
|
||||
LOCATE COMP "RD[3]" SITE "39";
|
||||
LOCATE COMP "RD[4]" SITE "40";
|
||||
LOCATE COMP "RD[5]" SITE "41";
|
||||
LOCATE COMP "RD[6]" SITE "42";
|
||||
LOCATE COMP "RD[7]" SITE "43";
|
||||
LOCATE COMP "nCCAS" SITE "9";
|
||||
LOCATE COMP "nCRAS" SITE "17";
|
||||
LOCATE COMP "nFWE" SITE "15";
|
||||
LOCATE COMP "nRCAS" SITE "52";
|
||||
LOCATE COMP "nRCS" SITE "57";
|
||||
LOCATE COMP "nRRAS" SITE "54";
|
||||
LOCATE COMP "nRWE" SITE "49";
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Sat Aug 19 21:55:09 2023
|
||||
|
||||
|
|
|
|||
|
|
@ -1,237 +1,216 @@
|
|||
|
||||
Lattice Place and Route Report for Design "LCMXO2_640HC_impl1_map.ncd"
|
||||
Wed Aug 16 20:59:37 2023
|
||||
|
||||
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
|
||||
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir/5_1.ncd LCMXO2_640HC_impl1.prf
|
||||
Preference file: LCMXO2_640HC_impl1.prf.
|
||||
Placement level-cost: 5-1.
|
||||
Routing Iterations: 6
|
||||
|
||||
Loading design for application par from file LCMXO2_640HC_impl1_map.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-640HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application par from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.39.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
License checked out.
|
||||
|
||||
|
||||
Ignore Preference Error(s): True
|
||||
Device utilization summary:
|
||||
|
||||
PIO (prelim) 63+4(JTAG)/80 84% used
|
||||
63+4(JTAG)/79 85% bonded
|
||||
IOLOGIC 25/80 31% used
|
||||
|
||||
SLICE 117/320 36% used
|
||||
|
||||
EFB 1/1 100% used
|
||||
|
||||
|
||||
Number of Signals: 380
|
||||
Number of Connections: 1008
|
||||
|
||||
Pin Constraint Summary:
|
||||
63 out of 63 pins locked (100% locked).
|
||||
|
||||
The following 3 signals are selected to use the primary clock routing resources:
|
||||
RCLK_c (driver: RCLK, clk load #: 46)
|
||||
PHI2_c (driver: PHI2, clk load #: 19)
|
||||
nCRAS_c (driver: nCRAS, clk load #: 10)
|
||||
|
||||
WARNING - par: Signal "RCLK_c" is selected to use Primary clock resources. However, its driver comp "RCLK" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
WARNING - par: Signal "nCRAS_c" is selected to use Primary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
|
||||
The following 2 signals are selected to use the secondary clock routing resources:
|
||||
nCCAS_c (driver: nCCAS, clk load #: 8, sr load #: 0, ce load #: 0)
|
||||
un1_wb_clk32_i (driver: SLICE_103, clk load #: 0, sr load #: 0, ce load #: 10)
|
||||
|
||||
WARNING - par: Signal "nCCAS_c" is selected to use Secondary clock resources. However, its driver comp "nCCAS" is located at "9", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
No signal is selected as Global Set/Reset.
|
||||
Starting Placer Phase 0.
|
||||
..............
|
||||
Finished Placer Phase 0. REAL time: 0 secs
|
||||
|
||||
Starting Placer Phase 1.
|
||||
...................
|
||||
Placer score = 55012.
|
||||
Finished Placer Phase 1. REAL time: 4 secs
|
||||
|
||||
Starting Placer Phase 2.
|
||||
.
|
||||
Placer score = 54994
|
||||
Finished Placer Phase 2. REAL time: 4 secs
|
||||
|
||||
|
||||
------------------ Clock Report ------------------
|
||||
|
||||
Global Clock Resources:
|
||||
CLK_PIN : 0 out of 8 (0%)
|
||||
General PIO: 4 out of 80 (5%)
|
||||
DCM : 0 out of 2 (0%)
|
||||
DCC : 0 out of 8 (0%)
|
||||
|
||||
Global Clocks:
|
||||
PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 46
|
||||
PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 19
|
||||
PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 10
|
||||
SECONDARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 8, ce load = 0, sr load = 0
|
||||
SECONDARY "un1_wb_clk32_i" from F0 on comp "SLICE_103" on site "R6C8B", clk load = 0, ce load = 10, sr load = 0
|
||||
|
||||
PRIMARY : 3 out of 8 (37%)
|
||||
SECONDARY: 2 out of 8 (25%)
|
||||
|
||||
--------------- End of Clock Report ---------------
|
||||
|
||||
|
||||
I/O Usage Summary (final):
|
||||
63 + 4(JTAG) out of 80 (83.8%) PIO sites used.
|
||||
63 + 4(JTAG) out of 79 (84.8%) bonded PIO sites used.
|
||||
Number of PIO comps: 63; differential: 0.
|
||||
Number of Vref pins used: 0.
|
||||
|
||||
I/O Bank Usage Summary:
|
||||
+----------+----------------+------------+-----------+
|
||||
| I/O Bank | Usage | Bank Vccio | Bank Vref |
|
||||
+----------+----------------+------------+-----------+
|
||||
| 0 | 13 / 19 ( 68%) | 3.3V | - |
|
||||
| 1 | 20 / 20 (100%) | 3.3V | - |
|
||||
| 2 | 12 / 20 ( 60%) | 3.3V | - |
|
||||
| 3 | 18 / 20 ( 90%) | 3.3V | - |
|
||||
+----------+----------------+------------+-----------+
|
||||
|
||||
Total placer CPU time: 3 secs
|
||||
|
||||
Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd.
|
||||
|
||||
0 connections routed; 1008 unrouted.
|
||||
Starting router resource preassignment
|
||||
WARNING - par: The driver of primary clock net RCLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
|
||||
WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
|
||||
|
||||
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
|
||||
Signal=wb_clk loads=1 clock_loads=1
|
||||
|
||||
Completed router resource preassignment. Real time: 5 secs
|
||||
|
||||
Start NBR router at 20:59:43 08/16/23
|
||||
|
||||
*****************************************************************
|
||||
Info: NBR allows conflicts(one node used by more than one signal)
|
||||
in the earlier iterations. In each iteration, it tries to
|
||||
solve the conflicts while keeping the critical connections
|
||||
routed as short as possible. The routing process is said to
|
||||
be completed when no conflicts exist and all connections
|
||||
are routed.
|
||||
Note: NBR uses a different method to calculate timing slacks. The
|
||||
worst slack and total negative slack may not be the same as
|
||||
that in TRCE report. You should always run TRCE to verify
|
||||
your design.
|
||||
*****************************************************************
|
||||
|
||||
Start NBR special constraint process at 20:59:43 08/16/23
|
||||
|
||||
Start NBR section for initial routing at 20:59:43 08/16/23
|
||||
Level 1, iteration 1
|
||||
0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs
|
||||
Level 2, iteration 1
|
||||
0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs
|
||||
Level 3, iteration 1
|
||||
0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs
|
||||
Level 4, iteration 1
|
||||
7(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs
|
||||
|
||||
Info: Initial congestion level at 75% usage is 0
|
||||
Info: Initial congestion area at 75% usage is 0 (0.00%)
|
||||
|
||||
Start NBR section for normal routing at 20:59:43 08/16/23
|
||||
Level 1, iteration 1
|
||||
0(0.00%) conflict; 11(1.09%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs
|
||||
Level 4, iteration 1
|
||||
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs
|
||||
Level 4, iteration 2
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs
|
||||
|
||||
Start NBR section for setup/hold timing optimization with effort level 3 at 20:59:43 08/16/23
|
||||
Level 4, iteration 0
|
||||
Level 4, iteration 1
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<hold >: 0.083ns/0.000ns; real time: 6 secs
|
||||
Level 4, iteration 0
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 4.902ns/0.000ns; real time: 6 secs
|
||||
Level 4, iteration 1
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 4.902ns/0.000ns; real time: 6 secs
|
||||
|
||||
Start NBR section for re-routing at 20:59:44 08/16/23
|
||||
Level 4, iteration 1
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 7 secs
|
||||
|
||||
Start NBR section for post-routing at 20:59:44 08/16/23
|
||||
|
||||
End NBR router with 0 unrouted connection
|
||||
|
||||
NBR Summary
|
||||
-----------
|
||||
Number of unrouted connections : 0 (0.00%)
|
||||
Number of connections with timing violations : 0 (0.00%)
|
||||
Estimated worst slack<setup> : 4.922ns
|
||||
Timing score<setup> : 0
|
||||
-----------
|
||||
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
|
||||
|
||||
|
||||
|
||||
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
|
||||
Signal=wb_clk loads=1 clock_loads=1
|
||||
|
||||
Total CPU time 6 secs
|
||||
Total REAL time: 7 secs
|
||||
Completely routed.
|
||||
End of route. 1008 routed (100.00%); 0 unrouted.
|
||||
|
||||
Hold time timing score: 0, hold timing errors: 0
|
||||
|
||||
Timing score: 0
|
||||
|
||||
Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd.
|
||||
|
||||
|
||||
All signals are completely routed.
|
||||
|
||||
|
||||
PAR_SUMMARY::Run status = Completed
|
||||
PAR_SUMMARY::Number of unrouted conns = 0
|
||||
PAR_SUMMARY::Worst slack<setup/<ns>> = 4.922
|
||||
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
|
||||
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.088
|
||||
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
|
||||
PAR_SUMMARY::Number of errors = 0
|
||||
|
||||
Total CPU time to completion: 6 secs
|
||||
Total REAL time to completion: 7 secs
|
||||
|
||||
par done!
|
||||
|
||||
Note: user must run 'Trace' for timing closure signoff.
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
Lattice Place and Route Report for Design "LCMXO2_640HC_impl1_map.ncd"
|
||||
Sat Aug 19 21:55:01 2023
|
||||
|
||||
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
|
||||
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir/5_1.ncd LCMXO2_640HC_impl1.prf
|
||||
Preference file: LCMXO2_640HC_impl1.prf.
|
||||
Placement level-cost: 5-1.
|
||||
Routing Iterations: 6
|
||||
|
||||
Loading design for application par from file LCMXO2_640HC_impl1_map.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-640HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application par from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.39.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
License checked out.
|
||||
|
||||
|
||||
Ignore Preference Error(s): True
|
||||
Device utilization summary:
|
||||
|
||||
PIO (prelim) 63+4(JTAG)/80 84% used
|
||||
63+4(JTAG)/79 85% bonded
|
||||
IOLOGIC 25/80 31% used
|
||||
|
||||
SLICE 113/320 35% used
|
||||
|
||||
EFB 1/1 100% used
|
||||
|
||||
|
||||
Number of Signals: 374
|
||||
Number of Connections: 978
|
||||
|
||||
Pin Constraint Summary:
|
||||
63 out of 63 pins locked (100% locked).
|
||||
|
||||
The following 3 signals are selected to use the primary clock routing resources:
|
||||
RCLK_c (driver: RCLK, clk load #: 47)
|
||||
PHI2_c (driver: PHI2, clk load #: 21)
|
||||
nCRAS_c (driver: nCRAS, clk load #: 10)
|
||||
|
||||
WARNING - par: Signal "RCLK_c" is selected to use Primary clock resources. However, its driver comp "RCLK" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
WARNING - par: Signal "nCRAS_c" is selected to use Primary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
|
||||
The following 1 signal is selected to use the secondary clock routing resources:
|
||||
nCCAS_c (driver: nCCAS, clk load #: 8, sr load #: 0, ce load #: 0)
|
||||
|
||||
WARNING - par: Signal "nCCAS_c" is selected to use Secondary clock resources. However, its driver comp "nCCAS" is located at "9", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
No signal is selected as Global Set/Reset.
|
||||
Starting Placer Phase 0.
|
||||
............
|
||||
Finished Placer Phase 0. REAL time: 0 secs
|
||||
|
||||
Starting Placer Phase 1.
|
||||
....................
|
||||
Placer score = 53481.
|
||||
Finished Placer Phase 1. REAL time: 5 secs
|
||||
|
||||
Starting Placer Phase 2.
|
||||
.
|
||||
Placer score = 53406
|
||||
Finished Placer Phase 2. REAL time: 5 secs
|
||||
|
||||
|
||||
------------------ Clock Report ------------------
|
||||
|
||||
Global Clock Resources:
|
||||
CLK_PIN : 0 out of 8 (0%)
|
||||
General PIO: 4 out of 80 (5%)
|
||||
DCM : 0 out of 2 (0%)
|
||||
DCC : 0 out of 8 (0%)
|
||||
|
||||
Global Clocks:
|
||||
PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 47
|
||||
PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 21
|
||||
PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 10
|
||||
SECONDARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 8, ce load = 0, sr load = 0
|
||||
|
||||
PRIMARY : 3 out of 8 (37%)
|
||||
SECONDARY: 1 out of 8 (12%)
|
||||
|
||||
--------------- End of Clock Report ---------------
|
||||
|
||||
|
||||
I/O Usage Summary (final):
|
||||
63 + 4(JTAG) out of 80 (83.8%) PIO sites used.
|
||||
63 + 4(JTAG) out of 79 (84.8%) bonded PIO sites used.
|
||||
Number of PIO comps: 63; differential: 0.
|
||||
Number of Vref pins used: 0.
|
||||
|
||||
I/O Bank Usage Summary:
|
||||
+----------+----------------+------------+-----------+
|
||||
| I/O Bank | Usage | Bank Vccio | Bank Vref |
|
||||
+----------+----------------+------------+-----------+
|
||||
| 0 | 13 / 19 ( 68%) | 3.3V | - |
|
||||
| 1 | 20 / 20 (100%) | 3.3V | - |
|
||||
| 2 | 12 / 20 ( 60%) | 3.3V | - |
|
||||
| 3 | 18 / 20 ( 90%) | 3.3V | - |
|
||||
+----------+----------------+------------+-----------+
|
||||
|
||||
Total placer CPU time: 5 secs
|
||||
|
||||
Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd.
|
||||
|
||||
0 connections routed; 978 unrouted.
|
||||
Starting router resource preassignment
|
||||
WARNING - par: The driver of primary clock net RCLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
|
||||
WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
|
||||
|
||||
Completed router resource preassignment. Real time: 8 secs
|
||||
|
||||
Start NBR router at 21:55:09 08/19/23
|
||||
|
||||
*****************************************************************
|
||||
Info: NBR allows conflicts(one node used by more than one signal)
|
||||
in the earlier iterations. In each iteration, it tries to
|
||||
solve the conflicts while keeping the critical connections
|
||||
routed as short as possible. The routing process is said to
|
||||
be completed when no conflicts exist and all connections
|
||||
are routed.
|
||||
Note: NBR uses a different method to calculate timing slacks. The
|
||||
worst slack and total negative slack may not be the same as
|
||||
that in TRCE report. You should always run TRCE to verify
|
||||
your design.
|
||||
*****************************************************************
|
||||
|
||||
Start NBR special constraint process at 21:55:09 08/19/23
|
||||
|
||||
Start NBR section for initial routing at 21:55:10 08/19/23
|
||||
Level 1, iteration 1
|
||||
0(0.00%) conflict; 776(79.35%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 7.085ns/0.000ns; real time: 9 secs
|
||||
Level 2, iteration 1
|
||||
0(0.00%) conflict; 771(78.83%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 7.138ns/0.000ns; real time: 9 secs
|
||||
Level 3, iteration 1
|
||||
0(0.00%) conflict; 765(78.22%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 7.276ns/0.000ns; real time: 9 secs
|
||||
Level 4, iteration 1
|
||||
10(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 6.966ns/0.000ns; real time: 9 secs
|
||||
|
||||
Info: Initial congestion level at 75% usage is 0
|
||||
Info: Initial congestion area at 75% usage is 0 (0.00%)
|
||||
|
||||
Start NBR section for normal routing at 21:55:10 08/19/23
|
||||
Level 4, iteration 1
|
||||
3(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 6.966ns/0.000ns; real time: 9 secs
|
||||
Level 4, iteration 2
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 6.966ns/0.000ns; real time: 9 secs
|
||||
|
||||
Start NBR section for setup/hold timing optimization with effort level 3 at 21:55:10 08/19/23
|
||||
|
||||
Start NBR section for re-routing at 21:55:10 08/19/23
|
||||
Level 4, iteration 1
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 6.966ns/0.000ns; real time: 9 secs
|
||||
|
||||
Start NBR section for post-routing at 21:55:10 08/19/23
|
||||
|
||||
End NBR router with 0 unrouted connection
|
||||
|
||||
NBR Summary
|
||||
-----------
|
||||
Number of unrouted connections : 0 (0.00%)
|
||||
Number of connections with timing violations : 0 (0.00%)
|
||||
Estimated worst slack<setup> : 6.966ns
|
||||
Timing score<setup> : 0
|
||||
-----------
|
||||
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
|
||||
|
||||
|
||||
|
||||
Total CPU time 9 secs
|
||||
Total REAL time: 9 secs
|
||||
Completely routed.
|
||||
End of route. 978 routed (100.00%); 0 unrouted.
|
||||
|
||||
Hold time timing score: 0, hold timing errors: 0
|
||||
|
||||
Timing score: 0
|
||||
|
||||
Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd.
|
||||
|
||||
|
||||
All signals are completely routed.
|
||||
|
||||
|
||||
PAR_SUMMARY::Run status = Completed
|
||||
PAR_SUMMARY::Number of unrouted conns = 0
|
||||
PAR_SUMMARY::Worst slack<setup/<ns>> = 6.966
|
||||
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
|
||||
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.304
|
||||
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
|
||||
PAR_SUMMARY::Number of errors = 0
|
||||
|
||||
Total CPU time to completion: 9 secs
|
||||
Total REAL time to completion: 10 secs
|
||||
|
||||
par done!
|
||||
|
||||
Note: user must run 'Trace' for timing closure signoff.
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
|
|
|||
|
|
@ -1,47 +1,42 @@
|
|||
[ActiveSupport PAR]
|
||||
; Global primary clocks
|
||||
GLOBAL_PRIMARY_USED = 3;
|
||||
; Global primary clock #0
|
||||
GLOBAL_PRIMARY_0_SIGNALNAME = RCLK_c;
|
||||
GLOBAL_PRIMARY_0_DRIVERTYPE = PIO;
|
||||
GLOBAL_PRIMARY_0_LOADNUM = 46;
|
||||
; Global primary clock #1
|
||||
GLOBAL_PRIMARY_1_SIGNALNAME = PHI2_c;
|
||||
GLOBAL_PRIMARY_1_DRIVERTYPE = PIO;
|
||||
GLOBAL_PRIMARY_1_LOADNUM = 19;
|
||||
; Global primary clock #2
|
||||
GLOBAL_PRIMARY_2_SIGNALNAME = nCRAS_c;
|
||||
GLOBAL_PRIMARY_2_DRIVERTYPE = PIO;
|
||||
GLOBAL_PRIMARY_2_LOADNUM = 10;
|
||||
; # of global secondary clocks
|
||||
GLOBAL_SECONDARY_USED = 2;
|
||||
; Global secondary clock #0
|
||||
GLOBAL_SECONDARY_0_SIGNALNAME = un1_wb_clk32_i;
|
||||
GLOBAL_SECONDARY_0_DRIVERTYPE = SLICE;
|
||||
GLOBAL_SECONDARY_0_LOADNUM = 10;
|
||||
GLOBAL_SECONDARY_0_SIGTYPE = CE;
|
||||
; Global secondary clock #1
|
||||
GLOBAL_SECONDARY_1_SIGNALNAME = nCCAS_c;
|
||||
GLOBAL_SECONDARY_1_DRIVERTYPE = PIO;
|
||||
GLOBAL_SECONDARY_1_LOADNUM = 10;
|
||||
GLOBAL_SECONDARY_1_SIGTYPE = CLK;
|
||||
; I/O Bank 0 Usage
|
||||
BANK_0_USED = 13;
|
||||
BANK_0_AVAIL = 19;
|
||||
BANK_0_VCCIO = 3.3V;
|
||||
BANK_0_VREF1 = NA;
|
||||
; I/O Bank 1 Usage
|
||||
BANK_1_USED = 20;
|
||||
BANK_1_AVAIL = 20;
|
||||
BANK_1_VCCIO = 3.3V;
|
||||
BANK_1_VREF1 = NA;
|
||||
; I/O Bank 2 Usage
|
||||
BANK_2_USED = 12;
|
||||
BANK_2_AVAIL = 20;
|
||||
BANK_2_VCCIO = 3.3V;
|
||||
BANK_2_VREF1 = NA;
|
||||
; I/O Bank 3 Usage
|
||||
BANK_3_USED = 18;
|
||||
BANK_3_AVAIL = 20;
|
||||
BANK_3_VCCIO = 3.3V;
|
||||
BANK_3_VREF1 = NA;
|
||||
[ActiveSupport PAR]
|
||||
; Global primary clocks
|
||||
GLOBAL_PRIMARY_USED = 3;
|
||||
; Global primary clock #0
|
||||
GLOBAL_PRIMARY_0_SIGNALNAME = RCLK_c;
|
||||
GLOBAL_PRIMARY_0_DRIVERTYPE = PIO;
|
||||
GLOBAL_PRIMARY_0_LOADNUM = 47;
|
||||
; Global primary clock #1
|
||||
GLOBAL_PRIMARY_1_SIGNALNAME = PHI2_c;
|
||||
GLOBAL_PRIMARY_1_DRIVERTYPE = PIO;
|
||||
GLOBAL_PRIMARY_1_LOADNUM = 21;
|
||||
; Global primary clock #2
|
||||
GLOBAL_PRIMARY_2_SIGNALNAME = nCRAS_c;
|
||||
GLOBAL_PRIMARY_2_DRIVERTYPE = PIO;
|
||||
GLOBAL_PRIMARY_2_LOADNUM = 10;
|
||||
; # of global secondary clocks
|
||||
GLOBAL_SECONDARY_USED = 1;
|
||||
; Global secondary clock #0
|
||||
GLOBAL_SECONDARY_0_SIGNALNAME = nCCAS_c;
|
||||
GLOBAL_SECONDARY_0_DRIVERTYPE = PIO;
|
||||
GLOBAL_SECONDARY_0_LOADNUM = 10;
|
||||
GLOBAL_SECONDARY_0_SIGTYPE = CLK;
|
||||
; I/O Bank 0 Usage
|
||||
BANK_0_USED = 13;
|
||||
BANK_0_AVAIL = 19;
|
||||
BANK_0_VCCIO = 3.3V;
|
||||
BANK_0_VREF1 = NA;
|
||||
; I/O Bank 1 Usage
|
||||
BANK_1_USED = 20;
|
||||
BANK_1_AVAIL = 20;
|
||||
BANK_1_VCCIO = 3.3V;
|
||||
BANK_1_VREF1 = NA;
|
||||
; I/O Bank 2 Usage
|
||||
BANK_2_USED = 12;
|
||||
BANK_2_AVAIL = 20;
|
||||
BANK_2_VCCIO = 3.3V;
|
||||
BANK_2_VREF1 = NA;
|
||||
; I/O Bank 3 Usage
|
||||
BANK_3_USED = 18;
|
||||
BANK_3_AVAIL = 20;
|
||||
BANK_3_VCCIO = 3.3V;
|
||||
BANK_3_VREF1 = NA;
|
||||
|
|
|
|||
|
|
@ -1,27 +1,27 @@
|
|||
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Wed Aug 16 20:59:37 2023
|
||||
|
||||
C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f LCMXO2_640HC_impl1.p2t
|
||||
LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir LCMXO2_640HC_impl1.prf -gui
|
||||
-msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
|
||||
|
||||
|
||||
Preference file: LCMXO2_640HC_impl1.prf.
|
||||
|
||||
Level/ Number Worst Timing Worst Timing Run NCD
|
||||
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
|
||||
---------- -------- ----- ------ ----------- ----------- ---- ------
|
||||
5_1 * 0 4.922 0 0.088 0 07 Completed
|
||||
|
||||
* : Design saved.
|
||||
|
||||
Total (real) run time for 1-seed: 7 secs
|
||||
|
||||
par done!
|
||||
|
||||
Note: user must run 'Trace' for timing closure signoff.
|
||||
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Sat Aug 19 21:55:01 2023
|
||||
|
||||
C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f LCMXO2_640HC_impl1.p2t
|
||||
LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir LCMXO2_640HC_impl1.prf -gui
|
||||
-msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
|
||||
|
||||
|
||||
Preference file: LCMXO2_640HC_impl1.prf.
|
||||
|
||||
Level/ Number Worst Timing Worst Timing Run NCD
|
||||
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
|
||||
---------- -------- ----- ------ ----------- ----------- ---- ------
|
||||
5_1 * 0 6.966 0 0.304 0 10 Completed
|
||||
|
||||
* : Design saved.
|
||||
|
||||
Total (real) run time for 1-seed: 10 secs
|
||||
|
||||
par done!
|
||||
|
||||
Note: user must run 'Trace' for timing closure signoff.
|
||||
|
|
|
|||
|
|
@ -1 +1 @@
|
|||
DRC detected 0 errors and 0 warnings.
|
||||
DRC detected 0 errors and 0 warnings.
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,9 +1,9 @@
|
|||
<html>
|
||||
<head>
|
||||
<title>syntmp/LCMXO2_640HC_impl1_srr.htm log file</title>
|
||||
</head>
|
||||
<frameset cols="20%, 80%">
|
||||
<frame src="syntmp/LCMXO2_640HC_impl1_toc.htm" name="tocFrame" />
|
||||
<frame src="syntmp/LCMXO2_640HC_impl1_srr.htm" name="srrFrame"/>
|
||||
</frameset>
|
||||
</html>
|
||||
<html>
|
||||
<head>
|
||||
<title>syntmp/LCMXO2_640HC_impl1_srr.htm log file</title>
|
||||
</head>
|
||||
<frameset cols="20%, 80%">
|
||||
<frame src="syntmp/LCMXO2_640HC_impl1_toc.htm" name="tocFrame" />
|
||||
<frame src="syntmp/LCMXO2_640HC_impl1_srr.htm" name="srrFrame"/>
|
||||
</frameset>
|
||||
</html>
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,4 +1,4 @@
|
|||
---- MParTrce Tool Log File ----
|
||||
|
||||
==== Par Standard Out ====
|
||||
==== End of Par Standard Out ====
|
||||
---- MParTrce Tool Log File ----
|
||||
|
||||
==== Par Standard Out ====
|
||||
==== End of Par Standard Out ====
|
||||
|
|
|
|||
|
|
@ -1,468 +1,468 @@
|
|||
|
||||
Lattice Mapping Report File for Design Module 'RAM2GS'
|
||||
|
||||
|
||||
Design Information
|
||||
------------------
|
||||
|
||||
Command line: map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial
|
||||
LCMXO2_640HC_impl1.ngd -o LCMXO2_640HC_impl1_map.ncd -pr
|
||||
LCMXO2_640HC_impl1.prf -mp LCMXO2_640HC_impl1.mrp -lpf D:/OneDrive/Document
|
||||
s/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify.lpf
|
||||
-lpf D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.lpf -c 0 -gui
|
||||
-msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
|
||||
Target Vendor: LATTICE
|
||||
Target Device: LCMXO2-640HCTQFP100
|
||||
Target Performance: 4
|
||||
Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454
|
||||
Mapped on: 08/16/23 20:59:36
|
||||
|
||||
Design Summary
|
||||
--------------
|
||||
|
||||
Number of registers: 109 out of 877 (12%)
|
||||
PFU registers: 84 out of 640 (13%)
|
||||
PIO registers: 25 out of 237 (11%)
|
||||
Number of SLICEs: 117 out of 320 (37%)
|
||||
SLICEs as Logic/ROM: 117 out of 320 (37%)
|
||||
SLICEs as RAM: 0 out of 240 (0%)
|
||||
SLICEs as Carry: 10 out of 320 (3%)
|
||||
Number of LUT4s: 230 out of 640 (36%)
|
||||
Number used as logic LUTs: 210
|
||||
Number used as distributed RAM: 0
|
||||
Number used as ripple logic: 20
|
||||
Number used as shift registers: 0
|
||||
Number of PIO sites used: 63 + 4(JTAG) out of 79 (85%)
|
||||
Number of block RAMs: 0 out of 2 (0%)
|
||||
Number of GSRs: 0 out of 1 (0%)
|
||||
EFB used : Yes
|
||||
JTAG used : No
|
||||
Readback used : No
|
||||
Oscillator used : No
|
||||
Startup used : No
|
||||
POR : On
|
||||
Bandgap : On
|
||||
Number of Power Controller: 0 out of 1 (0%)
|
||||
Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
|
||||
Number of DCCA: 0 out of 8 (0%)
|
||||
Number of DCMA: 0 out of 2 (0%)
|
||||
Notes:-
|
||||
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
|
||||
distributed RAMs) + 2*(Number of ripple logic)
|
||||
2. Number of logic LUT4s does not include count of distributed RAM and
|
||||
ripple logic.
|
||||
Number of clocks: 5
|
||||
Net PHI2_c: 19 loads, 9 rising, 10 falling (Driver: PIO PHI2 )
|
||||
Net RCLK_c: 46 loads, 46 rising, 0 falling (Driver: PIO RCLK )
|
||||
Net wb_clk: 1 loads, 1 rising, 0 falling (Driver: wb_clk )
|
||||
Net nCRAS_c: 10 loads, 0 rising, 10 falling (Driver: PIO nCRAS )
|
||||
Net nCCAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCCAS )
|
||||
Number of Clock Enables: 7
|
||||
Net N_245_i: 1 loads, 1 LSLICEs
|
||||
Net CMDUFMWrite_1_sqmuxa: 2 loads, 2 LSLICEs
|
||||
|
||||
Page 1
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 08/16/23 20:59:36
|
||||
|
||||
Design Summary (cont)
|
||||
---------------------
|
||||
Net InitReady: 1 loads, 1 LSLICEs
|
||||
Net un1_wb_clk32_i: 10 loads, 10 LSLICEs
|
||||
Net N_18: 2 loads, 2 LSLICEs
|
||||
Net XOR8MEG18: 3 loads, 3 LSLICEs
|
||||
Net N_193_i: 2 loads, 2 LSLICEs
|
||||
Number of LSRs: 5
|
||||
Net RA10s_i: 1 loads, 0 LSLICEs
|
||||
Net wb_clk23: 3 loads, 3 LSLICEs
|
||||
Net wb_rst: 1 loads, 0 LSLICEs
|
||||
Net nRRAS_0_sqmuxa: 1 loads, 1 LSLICEs
|
||||
Net RASr2: 2 loads, 2 LSLICEs
|
||||
Number of nets driven by tri-state buffers: 0
|
||||
Top 10 highest fanout non-clock nets:
|
||||
Net InitReady: 42 loads
|
||||
Net FS[12]: 27 loads
|
||||
Net FS[10]: 25 loads
|
||||
Net FS[11]: 22 loads
|
||||
Net FS[7]: 17 loads
|
||||
Net FS[6]: 16 loads
|
||||
Net Ready: 15 loads
|
||||
Net Ready_fast: 14 loads
|
||||
Net nRowColSel: 12 loads
|
||||
Net S[1]: 12 loads
|
||||
|
||||
|
||||
|
||||
|
||||
Number of warnings: 1
|
||||
Number of errors: 0
|
||||
|
||||
|
||||
Design Errors/Warnings
|
||||
----------------------
|
||||
|
||||
WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
||||
temporarily disable certain features of the device including Power
|
||||
Controller, GSR, Hardened User SPI Port, Hardened Primary User I2C Port.
|
||||
Functionality is restored after the Flash Memory (UFM/Configuration)
|
||||
Interface is disabled using Disable Configuration Interface command 0x26
|
||||
followed by Bypass command 0xFF.
|
||||
|
||||
IO (PIO) Attributes
|
||||
-------------------
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| IO Name | Direction | Levelmode | IO |
|
||||
| | | IO_TYPE | Register |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[0] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[0] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| PHI2 | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RDQML | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
Page 2
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 08/16/23 20:59:36
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
| RDQMH | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRCAS | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRRAS | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRWE | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RCKE | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RCLK | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRCS | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[7] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[6] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[5] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[4] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[3] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[2] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[1] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[11] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[10] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[9] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[8] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[7] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[6] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[5] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[4] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[3] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[2] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[1] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[0] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RBA[1] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RBA[0] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
Page 3
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 08/16/23 20:59:36
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
| LED | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nFWE | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nCRAS | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nCCAS | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[7] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[6] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[5] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[4] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[3] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[2] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[1] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[7] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[6] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[5] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[4] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[3] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[2] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[1] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[0] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| CROW[1] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| CROW[0] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[9] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[8] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[7] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[6] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[5] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[4] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[3] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
Page 4
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 08/16/23 20:59:36
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
| MAin[2] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[1] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[0] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
Removed logic
|
||||
-------------
|
||||
|
||||
Block GSR_INST undriven or does not drive anything - clipped.
|
||||
Signal nCRAS_c_i was merged into signal nCRAS_c
|
||||
Signal RASr2_i was merged into signal RASr2
|
||||
Signal InitReady_i was merged into signal InitReady
|
||||
Signal XOR8MEG.CN was merged into signal PHI2_c
|
||||
Signal GND undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/VCC undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/GND undriven or does not drive anything - clipped.
|
||||
Signal FS_s_0_S1[17] undriven or does not drive anything - clipped.
|
||||
Signal FS_s_0_COUT[17] undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/CFGWAKE undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wbc_ufm_irq undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/TCOC undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/TCINT undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIIRQO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPICSNEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMOSIEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMOSIO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMISOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMISOO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPISCKEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPISCKO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SDAOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SCLOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SDAOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SCLOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
|
||||
|
||||
Page 5
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 08/16/23 20:59:36
|
||||
|
||||
Removed logic (cont)
|
||||
--------------------
|
||||
Signal ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO4 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLWEO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLL1STBO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLL0STBO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLRSTO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLCLKO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wb_ack_o undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wb_dat_o_1[2] undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wb_dat_o_1[3] undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wb_dat_o_1[4] undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wb_dat_o_1[5] undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wb_dat_o_1[6] undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wb_dat_o_1[7] undriven or does not drive anything - clipped.
|
||||
Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped.
|
||||
Signal N_1 undriven or does not drive anything - clipped.
|
||||
Block nCRAS_pad_RNIBPVB was optimized away.
|
||||
Block RASr2_RNIAFR1 was optimized away.
|
||||
Block wb_rst_RNO_0 was optimized away.
|
||||
Block XOR8MEG.CN was optimized away.
|
||||
Block GND was optimized away.
|
||||
Block ufmefb/VCC was optimized away.
|
||||
Block ufmefb/GND was optimized away.
|
||||
|
||||
|
||||
|
||||
Embedded Functional Block Connection Summary
|
||||
--------------------------------------------
|
||||
|
||||
Desired WISHBONE clock frequency: 62.5 MHz
|
||||
Clock source: wb_clk
|
||||
Reset source: wb_rst
|
||||
Functions mode:
|
||||
I2C #1 (Primary) Function: DISABLED
|
||||
I2C #2 (Secondary) Function: DISABLED
|
||||
SPI Function: DISABLED
|
||||
Timer/Counter Function: DISABLED
|
||||
Timer/Counter Mode: WB
|
||||
UFM Connection: ENABLED
|
||||
PLL0 Connection: DISABLED
|
||||
PLL1 Connection: DISABLED
|
||||
I2C Function Summary:
|
||||
--------------------
|
||||
None
|
||||
SPI Function Summary:
|
||||
--------------------
|
||||
None
|
||||
Timer/Counter Function Summary:
|
||||
------------------------------
|
||||
None
|
||||
|
||||
Page 6
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 08/16/23 20:59:36
|
||||
|
||||
Embedded Functional Block Connection Summary (cont)
|
||||
---------------------------------------------------
|
||||
UFM Function Summary:
|
||||
--------------------
|
||||
UFM Utilization: General Purpose Flash Memory
|
||||
Initialized UFM Pages: 1 Pages (1*128 Bits)
|
||||
Available General
|
||||
Purpose Flash Memory: 191 Pages (191*128 Bits)
|
||||
|
||||
EBR Blocks with Unique
|
||||
Initialization Data: 0
|
||||
|
||||
WID EBR Instance
|
||||
--- ------------
|
||||
|
||||
|
||||
ASIC Components
|
||||
---------------
|
||||
|
||||
Instance Name: ufmefb/EFBInst_0
|
||||
Type: EFB
|
||||
|
||||
Run Time and Memory Usage
|
||||
-------------------------
|
||||
|
||||
Total CPU Time: 0 secs
|
||||
Total REAL Time: 0 secs
|
||||
Peak Memory Usage: 37 MB
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Page 7
|
||||
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights
|
||||
reserved.
|
||||
|
||||
Lattice Mapping Report File for Design Module 'RAM2GS'
|
||||
|
||||
|
||||
Design Information
|
||||
------------------
|
||||
|
||||
Command line: map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial
|
||||
LCMXO2_640HC_impl1.ngd -o LCMXO2_640HC_impl1_map.ncd -pr
|
||||
LCMXO2_640HC_impl1.prf -mp LCMXO2_640HC_impl1.mrp -lpf
|
||||
Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify.lpf
|
||||
-lpf Y:/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.lpf -c 0 -gui -msgset
|
||||
Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
|
||||
Target Vendor: LATTICE
|
||||
Target Device: LCMXO2-640HCTQFP100
|
||||
Target Performance: 4
|
||||
Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454
|
||||
Mapped on: 08/19/23 21:54:57
|
||||
|
||||
Design Summary
|
||||
--------------
|
||||
|
||||
Number of registers: 111 out of 877 (13%)
|
||||
PFU registers: 86 out of 640 (13%)
|
||||
PIO registers: 25 out of 237 (11%)
|
||||
Number of SLICEs: 113 out of 320 (35%)
|
||||
SLICEs as Logic/ROM: 113 out of 320 (35%)
|
||||
SLICEs as RAM: 0 out of 240 (0%)
|
||||
SLICEs as Carry: 10 out of 320 (3%)
|
||||
Number of LUT4s: 222 out of 640 (35%)
|
||||
Number used as logic LUTs: 202
|
||||
Number used as distributed RAM: 0
|
||||
Number used as ripple logic: 20
|
||||
Number used as shift registers: 0
|
||||
Number of PIO sites used: 63 + 4(JTAG) out of 79 (85%)
|
||||
Number of block RAMs: 0 out of 2 (0%)
|
||||
Number of GSRs: 0 out of 1 (0%)
|
||||
EFB used : Yes
|
||||
JTAG used : No
|
||||
Readback used : No
|
||||
Oscillator used : No
|
||||
Startup used : No
|
||||
POR : On
|
||||
Bandgap : On
|
||||
Number of Power Controller: 0 out of 1 (0%)
|
||||
Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
|
||||
Number of DCCA: 0 out of 8 (0%)
|
||||
Number of DCMA: 0 out of 2 (0%)
|
||||
Notes:-
|
||||
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
|
||||
distributed RAMs) + 2*(Number of ripple logic)
|
||||
2. Number of logic LUT4s does not include count of distributed RAM and
|
||||
ripple logic.
|
||||
Number of clocks: 4
|
||||
Net PHI2_c: 21 loads, 9 rising, 12 falling (Driver: PIO PHI2 )
|
||||
Net RCLK_c: 47 loads, 47 rising, 0 falling (Driver: PIO RCLK )
|
||||
Net nCRAS_c: 10 loads, 0 rising, 10 falling (Driver: PIO nCRAS )
|
||||
Net nCCAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCCAS )
|
||||
Number of Clock Enables: 6
|
||||
Net un1_wb_cyc_stb_2_sqmuxa_i_0_N_4_i: 1 loads, 1 LSLICEs
|
||||
Net XOR8MEG18: 6 loads, 6 LSLICEs
|
||||
Net CmdUFMData_1_sqmuxa: 1 loads, 1 LSLICEs
|
||||
|
||||
Page 1
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 08/19/23 21:54:57
|
||||
|
||||
Design Summary (cont)
|
||||
---------------------
|
||||
Net un1_wb_rst14_i: 9 loads, 9 LSLICEs
|
||||
Net un1_FS_38_i: 2 loads, 2 LSLICEs
|
||||
Net N_253_i: 2 loads, 2 LSLICEs
|
||||
Number of LSRs: 5
|
||||
Net RA10s_i: 1 loads, 0 LSLICEs
|
||||
Net wb_rst10: 3 loads, 3 LSLICEs
|
||||
Net wb_rst: 1 loads, 0 LSLICEs
|
||||
Net nRRAS_0_sqmuxa: 1 loads, 1 LSLICEs
|
||||
Net RASr2: 2 loads, 2 LSLICEs
|
||||
Number of nets driven by tri-state buffers: 0
|
||||
Top 10 highest fanout non-clock nets:
|
||||
Net InitReady: 33 loads
|
||||
Net FS[13]: 22 loads
|
||||
Net FS[12]: 21 loads
|
||||
Net FS[14]: 20 loads
|
||||
Net wb_rst11: 18 loads
|
||||
Net FS[10]: 16 loads
|
||||
Net Ready: 16 loads
|
||||
Net FS[11]: 15 loads
|
||||
Net FS[9]: 15 loads
|
||||
Net Ready_fast: 14 loads
|
||||
|
||||
|
||||
|
||||
|
||||
Number of warnings: 1
|
||||
Number of errors: 0
|
||||
|
||||
|
||||
Design Errors/Warnings
|
||||
----------------------
|
||||
|
||||
WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
||||
temporarily disable certain features of the device including Power
|
||||
Controller, GSR, Hardened User SPI Port, Hardened Primary User I2C Port.
|
||||
Functionality is restored after the Flash Memory (UFM/Configuration)
|
||||
Interface is disabled using Disable Configuration Interface command 0x26
|
||||
followed by Bypass command 0xFF.
|
||||
|
||||
IO (PIO) Attributes
|
||||
-------------------
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| IO Name | Direction | Levelmode | IO |
|
||||
| | | IO_TYPE | Register |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[0] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[0] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| PHI2 | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RDQML | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RDQMH | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
Page 2
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 08/19/23 21:54:57
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
| nRCAS | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRRAS | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRWE | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RCKE | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RCLK | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRCS | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[7] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[6] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[5] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[4] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[3] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[2] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[1] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[11] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[10] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[9] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[8] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[7] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[6] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[5] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[4] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[3] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[2] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[1] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[0] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RBA[1] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RBA[0] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| LED | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
Page 3
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 08/19/23 21:54:57
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
| nFWE | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nCRAS | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nCCAS | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[7] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[6] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[5] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[4] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[3] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[2] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[1] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[7] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[6] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[5] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[4] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[3] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[2] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[1] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[0] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| CROW[1] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| CROW[0] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[9] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[8] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[7] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[6] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[5] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[4] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[3] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[2] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
Page 4
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 08/19/23 21:54:57
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
| MAin[1] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[0] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
Removed logic
|
||||
-------------
|
||||
|
||||
Block GSR_INST undriven or does not drive anything - clipped.
|
||||
Signal nCRAS_c_i was merged into signal nCRAS_c
|
||||
Signal RASr2_i was merged into signal RASr2
|
||||
Signal XOR8MEG.CN was merged into signal PHI2_c
|
||||
Signal XOR8MEG_3_u_0_am was merged into signal XOR8MEG
|
||||
Signal GND undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/VCC undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/GND undriven or does not drive anything - clipped.
|
||||
Signal FS_s_0_S1[17] undriven or does not drive anything - clipped.
|
||||
Signal FS_s_0_COUT[17] undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/CFGWAKE undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wbc_ufm_irq undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/TCOC undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/TCINT undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIIRQO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPICSNEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMOSIEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMOSIO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMISOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMISOO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPISCKEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPISCKO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SDAOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SCLOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SDAOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SCLOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
|
||||
|
||||
Page 5
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 08/19/23 21:54:57
|
||||
|
||||
Removed logic (cont)
|
||||
--------------------
|
||||
Signal ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO4 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLWEO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLL1STBO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLL0STBO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLRSTO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLCLKO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wb_dat_o_1[2] undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wb_dat_o_1[3] undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wb_dat_o_1[4] undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wb_dat_o_1[5] undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wb_dat_o_1[6] undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wb_dat_o_1[7] undriven or does not drive anything - clipped.
|
||||
Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped.
|
||||
Signal N_1 undriven or does not drive anything - clipped.
|
||||
Block nCRAS_pad_RNIBPVB was optimized away.
|
||||
Block RASr2_RNIAFR1 was optimized away.
|
||||
Block XOR8MEG.CN was optimized away.
|
||||
Block XOR8MEG_3_u_0_am was optimized away.
|
||||
Block GND was optimized away.
|
||||
Block ufmefb/VCC was optimized away.
|
||||
Block ufmefb/GND was optimized away.
|
||||
|
||||
|
||||
|
||||
Embedded Functional Block Connection Summary
|
||||
--------------------------------------------
|
||||
|
||||
Desired WISHBONE clock frequency: 66.7 MHz
|
||||
Clock source: RCLK_c
|
||||
Reset source: wb_rst
|
||||
Functions mode:
|
||||
I2C #1 (Primary) Function: DISABLED
|
||||
I2C #2 (Secondary) Function: DISABLED
|
||||
SPI Function: DISABLED
|
||||
Timer/Counter Function: DISABLED
|
||||
Timer/Counter Mode: WB
|
||||
UFM Connection: ENABLED
|
||||
PLL0 Connection: DISABLED
|
||||
PLL1 Connection: DISABLED
|
||||
I2C Function Summary:
|
||||
--------------------
|
||||
None
|
||||
SPI Function Summary:
|
||||
--------------------
|
||||
None
|
||||
Timer/Counter Function Summary:
|
||||
------------------------------
|
||||
None
|
||||
UFM Function Summary:
|
||||
--------------------
|
||||
UFM Utilization: General Purpose Flash Memory
|
||||
|
||||
Page 6
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 08/19/23 21:54:57
|
||||
|
||||
Embedded Functional Block Connection Summary (cont)
|
||||
---------------------------------------------------
|
||||
Initialized UFM Pages: 1 Pages (1*128 Bits)
|
||||
Available General
|
||||
Purpose Flash Memory: 191 Pages (191*128 Bits)
|
||||
|
||||
EBR Blocks with Unique
|
||||
Initialization Data: 0
|
||||
|
||||
WID EBR Instance
|
||||
--- ------------
|
||||
|
||||
|
||||
ASIC Components
|
||||
---------------
|
||||
|
||||
Instance Name: ufmefb/EFBInst_0
|
||||
Type: EFB
|
||||
|
||||
Run Time and Memory Usage
|
||||
-------------------------
|
||||
|
||||
Total CPU Time: 0 secs
|
||||
Total REAL Time: 0 secs
|
||||
Peak Memory Usage: 57 MB
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Page 7
|
||||
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights
|
||||
reserved.
|
||||
|
|
|
|||
|
|
@ -0,0 +1,9 @@
|
|||
-v
|
||||
1
|
||||
|
||||
|
||||
-gt
|
||||
|
||||
|
||||
-mapchkpnt 0
|
||||
-sethld
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -1,9 +1,9 @@
|
|||
-w
|
||||
-l 5
|
||||
-i 6
|
||||
-n 1
|
||||
-t 1
|
||||
-s 1
|
||||
-c 0
|
||||
-e 0
|
||||
-exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1
|
||||
-w
|
||||
-l 5
|
||||
-i 6
|
||||
-n 1
|
||||
-t 1
|
||||
-s 1
|
||||
-c 0
|
||||
-e 0
|
||||
-exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1
|
||||
|
|
|
|||
|
|
@ -1,273 +1,273 @@
|
|||
PAD Specification File
|
||||
***************************
|
||||
|
||||
PART TYPE: LCMXO2-640HC
|
||||
Performance Grade: 4
|
||||
PACKAGE: TQFP100
|
||||
Package Status: Final Version 1.39
|
||||
|
||||
Wed Aug 16 20:59:41 2023
|
||||
|
||||
Pinout by Port Name:
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties |
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
| CROW[0] | 10/3 | LVCMOS33_IN | PL3D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| CROW[1] | 16/3 | LVCMOS33_IN | PL6A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[0] | 3/3 | LVCMOS33_IN | PL2C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[1] | 96/0 | LVCMOS33_IN | PT6D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[2] | 88/0 | LVCMOS33_IN | PT9A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[3] | 97/0 | LVCMOS33_IN | PT6C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[4] | 99/0 | LVCMOS33_IN | PT6A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[5] | 98/0 | LVCMOS33_IN | PT6B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[6] | 2/3 | LVCMOS33_IN | PL2B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[7] | 1/3 | LVCMOS33_IN | PL2A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Dout[0] | 76/0 | LVCMOS33_OUT | PT11D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| Dout[1] | 86/0 | LVCMOS33_OUT | PT9C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| Dout[2] | 87/0 | LVCMOS33_OUT | PT9B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| Dout[3] | 85/0 | LVCMOS33_OUT | PT9D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| Dout[4] | 83/0 | LVCMOS33_OUT | PT10B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| Dout[5] | 84/0 | LVCMOS33_OUT | PT10A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| Dout[6] | 78/0 | LVCMOS33_OUT | PT11A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| Dout[7] | 82/0 | LVCMOS33_OUT | PT10C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| LED | 34/2 | LVCMOS33_OUT | PB6C | | | DRIVE:24mA PULL:KEEPER SLEW:SLOW |
|
||||
| MAin[0] | 14/3 | LVCMOS33_IN | PL5C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[1] | 12/3 | LVCMOS33_IN | PL5A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[2] | 13/3 | LVCMOS33_IN | PL5B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[3] | 21/3 | LVCMOS33_IN | PL7B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[4] | 20/3 | LVCMOS33_IN | PL7A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[5] | 19/3 | LVCMOS33_IN | PL6D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[6] | 24/3 | LVCMOS33_IN | PL7C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[7] | 18/3 | LVCMOS33_IN | PL6C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[8] | 25/3 | LVCMOS33_IN | PL7D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[9] | 32/2 | LVCMOS33_IN | PB6B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| PHI2 | 8/3 | LVCMOS33_IN | PL3B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| RA[0] | 66/1 | LVCMOS33_OUT | PR3D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[10] | 64/1 | LVCMOS33_OUT | PR5B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[11] | 59/1 | LVCMOS33_OUT | PR6B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[1] | 67/1 | LVCMOS33_OUT | PR3C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[2] | 69/1 | LVCMOS33_OUT | PR3A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[3] | 71/1 | LVCMOS33_OUT | PR2C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[4] | 74/1 | LVCMOS33_OUT | PR2B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[5] | 70/1 | LVCMOS33_OUT | PR2D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[6] | 68/1 | LVCMOS33_OUT | PR3B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[7] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[9] | 63/1 | LVCMOS33_OUT | PR5C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RBA[0] | 58/1 | LVCMOS33_OUT | PR6C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RBA[1] | 60/1 | LVCMOS33_OUT | PR6A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RCKE | 53/1 | LVCMOS33_OUT | PR7B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RCLK | 62/1 | LVCMOS33_IN | PR5D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| RDQMH | 51/1 | LVCMOS33_OUT | PR7D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RDQML | 48/2 | LVCMOS33_OUT | PB14C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RD[0] | 36/2 | LVCMOS33_BIDI | PB10A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[1] | 37/2 | LVCMOS33_BIDI | PB10B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[2] | 38/2 | LVCMOS33_BIDI | PB10C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[3] | 39/2 | LVCMOS33_BIDI | PB10D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[4] | 40/2 | LVCMOS33_BIDI | PB12A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[5] | 41/2 | LVCMOS33_BIDI | PB12B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[6] | 42/2 | LVCMOS33_BIDI | PB12C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[7] | 43/2 | LVCMOS33_BIDI | PB12D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| nCCAS | 9/3 | LVCMOS33_IN | PL3C | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nCRAS | 17/3 | LVCMOS33_IN | PL6B | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nFWE | 15/3 | LVCMOS33_IN | PL5D | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nRCAS | 52/1 | LVCMOS33_OUT | PR7C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| nRCS | 57/1 | LVCMOS33_OUT | PR6D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| nRRAS | 54/1 | LVCMOS33_OUT | PR7A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| nRWE | 49/2 | LVCMOS33_OUT | PB14D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
|
||||
Vccio by Bank:
|
||||
+------+-------+
|
||||
| Bank | Vccio |
|
||||
+------+-------+
|
||||
| 0 | 3.3V |
|
||||
| 1 | 3.3V |
|
||||
| 2 | 3.3V |
|
||||
| 3 | 3.3V |
|
||||
+------+-------+
|
||||
|
||||
Vref by Bank:
|
||||
+------+-----+-----------------+---------+
|
||||
| Vref | Pin | Bank # / Vref # | Load(s) |
|
||||
+------+-----+-----------------+---------+
|
||||
+------+-----+-----------------+---------+
|
||||
|
||||
Pinout by Pin Number:
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable |
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
| 1/3 | Din[7] | LOCATED | LVCMOS33_IN | PL2A | | | |
|
||||
| 2/3 | Din[6] | LOCATED | LVCMOS33_IN | PL2B | | | |
|
||||
| 3/3 | Din[0] | LOCATED | LVCMOS33_IN | PL2C | PCLKT3_2 | | |
|
||||
| 4/3 | unused, PULL:DOWN | | | PL2D | PCLKC3_2 | | |
|
||||
| 7/3 | unused, PULL:DOWN | | | PL3A | | | |
|
||||
| 8/3 | PHI2 | LOCATED | LVCMOS33_IN | PL3B | | | |
|
||||
| 9/3 | nCCAS | LOCATED | LVCMOS33_IN | PL3C | | | |
|
||||
| 10/3 | CROW[0] | LOCATED | LVCMOS33_IN | PL3D | | | |
|
||||
| 12/3 | MAin[1] | LOCATED | LVCMOS33_IN | PL5A | PCLKT3_1 | | |
|
||||
| 13/3 | MAin[2] | LOCATED | LVCMOS33_IN | PL5B | PCLKC3_1 | | |
|
||||
| 14/3 | MAin[0] | LOCATED | LVCMOS33_IN | PL5C | | | |
|
||||
| 15/3 | nFWE | LOCATED | LVCMOS33_IN | PL5D | | | |
|
||||
| 16/3 | CROW[1] | LOCATED | LVCMOS33_IN | PL6A | | | |
|
||||
| 17/3 | nCRAS | LOCATED | LVCMOS33_IN | PL6B | | | |
|
||||
| 18/3 | MAin[7] | LOCATED | LVCMOS33_IN | PL6C | | | |
|
||||
| 19/3 | MAin[5] | LOCATED | LVCMOS33_IN | PL6D | | | |
|
||||
| 20/3 | MAin[4] | LOCATED | LVCMOS33_IN | PL7A | PCLKT3_0 | | |
|
||||
| 21/3 | MAin[3] | LOCATED | LVCMOS33_IN | PL7B | PCLKC3_0 | | |
|
||||
| 24/3 | MAin[6] | LOCATED | LVCMOS33_IN | PL7C | | | |
|
||||
| 25/3 | MAin[8] | LOCATED | LVCMOS33_IN | PL7D | | | |
|
||||
| 27/2 | unused, PULL:DOWN | | | PB4A | CSSPIN | | |
|
||||
| 28/2 | unused, PULL:DOWN | | | PB4B | | | |
|
||||
| 29/2 | unused, PULL:DOWN | | | PB4C | | | |
|
||||
| 30/2 | unused, PULL:DOWN | | | PB4D | | | |
|
||||
| 31/2 | unused, PULL:DOWN | | | PB6A | MCLK/CCLK | | |
|
||||
| 32/2 | MAin[9] | LOCATED | LVCMOS33_IN | PB6B | SO/SPISO | | |
|
||||
| 34/2 | LED | LOCATED | LVCMOS33_OUT | PB6C | PCLKT2_0 | | |
|
||||
| 35/2 | unused, PULL:DOWN | | | PB6D | PCLKC2_0 | | |
|
||||
| 36/2 | RD[0] | LOCATED | LVCMOS33_BIDI | PB10A | | | |
|
||||
| 37/2 | RD[1] | LOCATED | LVCMOS33_BIDI | PB10B | | | |
|
||||
| 38/2 | RD[2] | LOCATED | LVCMOS33_BIDI | PB10C | PCLKT2_1 | | |
|
||||
| 39/2 | RD[3] | LOCATED | LVCMOS33_BIDI | PB10D | PCLKC2_1 | | |
|
||||
| 40/2 | RD[4] | LOCATED | LVCMOS33_BIDI | PB12A | | | |
|
||||
| 41/2 | RD[5] | LOCATED | LVCMOS33_BIDI | PB12B | | | |
|
||||
| 42/2 | RD[6] | LOCATED | LVCMOS33_BIDI | PB12C | | | |
|
||||
| 43/2 | RD[7] | LOCATED | LVCMOS33_BIDI | PB12D | | | |
|
||||
| 45/2 | unused, PULL:DOWN | | | PB14A | | | |
|
||||
| 47/2 | unused, PULL:DOWN | | | PB14B | | | |
|
||||
| 48/2 | RDQML | LOCATED | LVCMOS33_OUT | PB14C | SN | | |
|
||||
| 49/2 | nRWE | LOCATED | LVCMOS33_OUT | PB14D | SI/SISPI | | |
|
||||
| 51/1 | RDQMH | LOCATED | LVCMOS33_OUT | PR7D | | | |
|
||||
| 52/1 | nRCAS | LOCATED | LVCMOS33_OUT | PR7C | | | |
|
||||
| 53/1 | RCKE | LOCATED | LVCMOS33_OUT | PR7B | | | |
|
||||
| 54/1 | nRRAS | LOCATED | LVCMOS33_OUT | PR7A | | | |
|
||||
| 57/1 | nRCS | LOCATED | LVCMOS33_OUT | PR6D | | | |
|
||||
| 58/1 | RBA[0] | LOCATED | LVCMOS33_OUT | PR6C | | | |
|
||||
| 59/1 | RA[11] | LOCATED | LVCMOS33_OUT | PR6B | | | |
|
||||
| 60/1 | RBA[1] | LOCATED | LVCMOS33_OUT | PR6A | | | |
|
||||
| 62/1 | RCLK | LOCATED | LVCMOS33_IN | PR5D | PCLKC1_0 | | |
|
||||
| 63/1 | RA[9] | LOCATED | LVCMOS33_OUT | PR5C | PCLKT1_0 | | |
|
||||
| 64/1 | RA[10] | LOCATED | LVCMOS33_OUT | PR5B | | | |
|
||||
| 65/1 | RA[8] | LOCATED | LVCMOS33_OUT | PR5A | | | |
|
||||
| 66/1 | RA[0] | LOCATED | LVCMOS33_OUT | PR3D | | | |
|
||||
| 67/1 | RA[1] | LOCATED | LVCMOS33_OUT | PR3C | | | |
|
||||
| 68/1 | RA[6] | LOCATED | LVCMOS33_OUT | PR3B | | | |
|
||||
| 69/1 | RA[2] | LOCATED | LVCMOS33_OUT | PR3A | | | |
|
||||
| 70/1 | RA[5] | LOCATED | LVCMOS33_OUT | PR2D | | | |
|
||||
| 71/1 | RA[3] | LOCATED | LVCMOS33_OUT | PR2C | | | |
|
||||
| 74/1 | RA[4] | LOCATED | LVCMOS33_OUT | PR2B | | | |
|
||||
| 75/1 | RA[7] | LOCATED | LVCMOS33_OUT | PR2A | | | |
|
||||
| 76/0 | Dout[0] | LOCATED | LVCMOS33_OUT | PT11D | DONE | | |
|
||||
| 77/0 | unused, PULL:DOWN | | | PT11C | INITN | | |
|
||||
| 78/0 | Dout[6] | LOCATED | LVCMOS33_OUT | PT11A | | | |
|
||||
| 81/0 | unused, PULL:DOWN | | | PT10D | PROGRAMN | | |
|
||||
| 82/0 | Dout[7] | LOCATED | LVCMOS33_OUT | PT10C | JTAGENB | | |
|
||||
| 83/0 | Dout[4] | LOCATED | LVCMOS33_OUT | PT10B | | | |
|
||||
| 84/0 | Dout[5] | LOCATED | LVCMOS33_OUT | PT10A | | | |
|
||||
| 85/0 | Dout[3] | LOCATED | LVCMOS33_OUT | PT9D | SDA/PCLKC0_0 | | |
|
||||
| 86/0 | Dout[1] | LOCATED | LVCMOS33_OUT | PT9C | SCL/PCLKT0_0 | | |
|
||||
| 87/0 | Dout[2] | LOCATED | LVCMOS33_OUT | PT9B | PCLKC0_1 | | |
|
||||
| 88/0 | Din[2] | LOCATED | LVCMOS33_IN | PT9A | PCLKT0_1 | | |
|
||||
| 90/0 | Reserved: sysCONFIG | | | PT7D | TMS | | |
|
||||
| 91/0 | Reserved: sysCONFIG | | | PT7C | TCK | | |
|
||||
| 94/0 | Reserved: sysCONFIG | | | PT7B | TDI | | |
|
||||
| 95/0 | Reserved: sysCONFIG | | | PT7A | TDO | | |
|
||||
| 96/0 | Din[1] | LOCATED | LVCMOS33_IN | PT6D | | | |
|
||||
| 97/0 | Din[3] | LOCATED | LVCMOS33_IN | PT6C | | | |
|
||||
| 98/0 | Din[5] | LOCATED | LVCMOS33_IN | PT6B | | | |
|
||||
| 99/0 | Din[4] | LOCATED | LVCMOS33_IN | PT6A | | | |
|
||||
| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | |
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
|
||||
sysCONFIG Pins:
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode |
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
| PT7D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP |
|
||||
| PT7C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down |
|
||||
| PT7B | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP |
|
||||
| PT7A | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP |
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
|
||||
Dedicated sysCONFIG Pins:
|
||||
|
||||
|
||||
List of All Pins' Locate Preferences Based on Final Placement After PAR
|
||||
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste):
|
||||
|
||||
LOCATE COMP "CROW[0]" SITE "10";
|
||||
LOCATE COMP "CROW[1]" SITE "16";
|
||||
LOCATE COMP "Din[0]" SITE "3";
|
||||
LOCATE COMP "Din[1]" SITE "96";
|
||||
LOCATE COMP "Din[2]" SITE "88";
|
||||
LOCATE COMP "Din[3]" SITE "97";
|
||||
LOCATE COMP "Din[4]" SITE "99";
|
||||
LOCATE COMP "Din[5]" SITE "98";
|
||||
LOCATE COMP "Din[6]" SITE "2";
|
||||
LOCATE COMP "Din[7]" SITE "1";
|
||||
LOCATE COMP "Dout[0]" SITE "76";
|
||||
LOCATE COMP "Dout[1]" SITE "86";
|
||||
LOCATE COMP "Dout[2]" SITE "87";
|
||||
LOCATE COMP "Dout[3]" SITE "85";
|
||||
LOCATE COMP "Dout[4]" SITE "83";
|
||||
LOCATE COMP "Dout[5]" SITE "84";
|
||||
LOCATE COMP "Dout[6]" SITE "78";
|
||||
LOCATE COMP "Dout[7]" SITE "82";
|
||||
LOCATE COMP "LED" SITE "34";
|
||||
LOCATE COMP "MAin[0]" SITE "14";
|
||||
LOCATE COMP "MAin[1]" SITE "12";
|
||||
LOCATE COMP "MAin[2]" SITE "13";
|
||||
LOCATE COMP "MAin[3]" SITE "21";
|
||||
LOCATE COMP "MAin[4]" SITE "20";
|
||||
LOCATE COMP "MAin[5]" SITE "19";
|
||||
LOCATE COMP "MAin[6]" SITE "24";
|
||||
LOCATE COMP "MAin[7]" SITE "18";
|
||||
LOCATE COMP "MAin[8]" SITE "25";
|
||||
LOCATE COMP "MAin[9]" SITE "32";
|
||||
LOCATE COMP "PHI2" SITE "8";
|
||||
LOCATE COMP "RA[0]" SITE "66";
|
||||
LOCATE COMP "RA[10]" SITE "64";
|
||||
LOCATE COMP "RA[11]" SITE "59";
|
||||
LOCATE COMP "RA[1]" SITE "67";
|
||||
LOCATE COMP "RA[2]" SITE "69";
|
||||
LOCATE COMP "RA[3]" SITE "71";
|
||||
LOCATE COMP "RA[4]" SITE "74";
|
||||
LOCATE COMP "RA[5]" SITE "70";
|
||||
LOCATE COMP "RA[6]" SITE "68";
|
||||
LOCATE COMP "RA[7]" SITE "75";
|
||||
LOCATE COMP "RA[8]" SITE "65";
|
||||
LOCATE COMP "RA[9]" SITE "63";
|
||||
LOCATE COMP "RBA[0]" SITE "58";
|
||||
LOCATE COMP "RBA[1]" SITE "60";
|
||||
LOCATE COMP "RCKE" SITE "53";
|
||||
LOCATE COMP "RCLK" SITE "62";
|
||||
LOCATE COMP "RDQMH" SITE "51";
|
||||
LOCATE COMP "RDQML" SITE "48";
|
||||
LOCATE COMP "RD[0]" SITE "36";
|
||||
LOCATE COMP "RD[1]" SITE "37";
|
||||
LOCATE COMP "RD[2]" SITE "38";
|
||||
LOCATE COMP "RD[3]" SITE "39";
|
||||
LOCATE COMP "RD[4]" SITE "40";
|
||||
LOCATE COMP "RD[5]" SITE "41";
|
||||
LOCATE COMP "RD[6]" SITE "42";
|
||||
LOCATE COMP "RD[7]" SITE "43";
|
||||
LOCATE COMP "nCCAS" SITE "9";
|
||||
LOCATE COMP "nCRAS" SITE "17";
|
||||
LOCATE COMP "nFWE" SITE "15";
|
||||
LOCATE COMP "nRCAS" SITE "52";
|
||||
LOCATE COMP "nRCS" SITE "57";
|
||||
LOCATE COMP "nRRAS" SITE "54";
|
||||
LOCATE COMP "nRWE" SITE "49";
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Wed Aug 16 20:59:42 2023
|
||||
|
||||
PAD Specification File
|
||||
***************************
|
||||
|
||||
PART TYPE: LCMXO2-640HC
|
||||
Performance Grade: 4
|
||||
PACKAGE: TQFP100
|
||||
Package Status: Final Version 1.39
|
||||
|
||||
Sat Aug 19 21:55:06 2023
|
||||
|
||||
Pinout by Port Name:
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties |
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
| CROW[0] | 10/3 | LVCMOS33_IN | PL3D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| CROW[1] | 16/3 | LVCMOS33_IN | PL6A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[0] | 3/3 | LVCMOS33_IN | PL2C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[1] | 96/0 | LVCMOS33_IN | PT6D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[2] | 88/0 | LVCMOS33_IN | PT9A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[3] | 97/0 | LVCMOS33_IN | PT6C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[4] | 99/0 | LVCMOS33_IN | PT6A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[5] | 98/0 | LVCMOS33_IN | PT6B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[6] | 2/3 | LVCMOS33_IN | PL2B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[7] | 1/3 | LVCMOS33_IN | PL2A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Dout[0] | 76/0 | LVCMOS33_OUT | PT11D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| Dout[1] | 86/0 | LVCMOS33_OUT | PT9C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| Dout[2] | 87/0 | LVCMOS33_OUT | PT9B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| Dout[3] | 85/0 | LVCMOS33_OUT | PT9D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| Dout[4] | 83/0 | LVCMOS33_OUT | PT10B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| Dout[5] | 84/0 | LVCMOS33_OUT | PT10A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| Dout[6] | 78/0 | LVCMOS33_OUT | PT11A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| Dout[7] | 82/0 | LVCMOS33_OUT | PT10C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| LED | 34/2 | LVCMOS33_OUT | PB6C | | | DRIVE:24mA PULL:KEEPER SLEW:SLOW |
|
||||
| MAin[0] | 14/3 | LVCMOS33_IN | PL5C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[1] | 12/3 | LVCMOS33_IN | PL5A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[2] | 13/3 | LVCMOS33_IN | PL5B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[3] | 21/3 | LVCMOS33_IN | PL7B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[4] | 20/3 | LVCMOS33_IN | PL7A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[5] | 19/3 | LVCMOS33_IN | PL6D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[6] | 24/3 | LVCMOS33_IN | PL7C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[7] | 18/3 | LVCMOS33_IN | PL6C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[8] | 25/3 | LVCMOS33_IN | PL7D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[9] | 32/2 | LVCMOS33_IN | PB6B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| PHI2 | 8/3 | LVCMOS33_IN | PL3B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| RA[0] | 66/1 | LVCMOS33_OUT | PR3D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[10] | 64/1 | LVCMOS33_OUT | PR5B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[11] | 59/1 | LVCMOS33_OUT | PR6B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[1] | 67/1 | LVCMOS33_OUT | PR3C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[2] | 69/1 | LVCMOS33_OUT | PR3A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[3] | 71/1 | LVCMOS33_OUT | PR2C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[4] | 74/1 | LVCMOS33_OUT | PR2B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[5] | 70/1 | LVCMOS33_OUT | PR2D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[6] | 68/1 | LVCMOS33_OUT | PR3B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[7] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[9] | 63/1 | LVCMOS33_OUT | PR5C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RBA[0] | 58/1 | LVCMOS33_OUT | PR6C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RBA[1] | 60/1 | LVCMOS33_OUT | PR6A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RCKE | 53/1 | LVCMOS33_OUT | PR7B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RCLK | 62/1 | LVCMOS33_IN | PR5D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| RDQMH | 51/1 | LVCMOS33_OUT | PR7D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RDQML | 48/2 | LVCMOS33_OUT | PB14C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RD[0] | 36/2 | LVCMOS33_BIDI | PB10A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[1] | 37/2 | LVCMOS33_BIDI | PB10B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[2] | 38/2 | LVCMOS33_BIDI | PB10C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[3] | 39/2 | LVCMOS33_BIDI | PB10D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[4] | 40/2 | LVCMOS33_BIDI | PB12A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[5] | 41/2 | LVCMOS33_BIDI | PB12B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[6] | 42/2 | LVCMOS33_BIDI | PB12C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[7] | 43/2 | LVCMOS33_BIDI | PB12D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| nCCAS | 9/3 | LVCMOS33_IN | PL3C | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nCRAS | 17/3 | LVCMOS33_IN | PL6B | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nFWE | 15/3 | LVCMOS33_IN | PL5D | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nRCAS | 52/1 | LVCMOS33_OUT | PR7C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| nRCS | 57/1 | LVCMOS33_OUT | PR6D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| nRRAS | 54/1 | LVCMOS33_OUT | PR7A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| nRWE | 49/2 | LVCMOS33_OUT | PB14D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
|
||||
Vccio by Bank:
|
||||
+------+-------+
|
||||
| Bank | Vccio |
|
||||
+------+-------+
|
||||
| 0 | 3.3V |
|
||||
| 1 | 3.3V |
|
||||
| 2 | 3.3V |
|
||||
| 3 | 3.3V |
|
||||
+------+-------+
|
||||
|
||||
Vref by Bank:
|
||||
+------+-----+-----------------+---------+
|
||||
| Vref | Pin | Bank # / Vref # | Load(s) |
|
||||
+------+-----+-----------------+---------+
|
||||
+------+-----+-----------------+---------+
|
||||
|
||||
Pinout by Pin Number:
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable |
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
| 1/3 | Din[7] | LOCATED | LVCMOS33_IN | PL2A | | | |
|
||||
| 2/3 | Din[6] | LOCATED | LVCMOS33_IN | PL2B | | | |
|
||||
| 3/3 | Din[0] | LOCATED | LVCMOS33_IN | PL2C | PCLKT3_2 | | |
|
||||
| 4/3 | unused, PULL:DOWN | | | PL2D | PCLKC3_2 | | |
|
||||
| 7/3 | unused, PULL:DOWN | | | PL3A | | | |
|
||||
| 8/3 | PHI2 | LOCATED | LVCMOS33_IN | PL3B | | | |
|
||||
| 9/3 | nCCAS | LOCATED | LVCMOS33_IN | PL3C | | | |
|
||||
| 10/3 | CROW[0] | LOCATED | LVCMOS33_IN | PL3D | | | |
|
||||
| 12/3 | MAin[1] | LOCATED | LVCMOS33_IN | PL5A | PCLKT3_1 | | |
|
||||
| 13/3 | MAin[2] | LOCATED | LVCMOS33_IN | PL5B | PCLKC3_1 | | |
|
||||
| 14/3 | MAin[0] | LOCATED | LVCMOS33_IN | PL5C | | | |
|
||||
| 15/3 | nFWE | LOCATED | LVCMOS33_IN | PL5D | | | |
|
||||
| 16/3 | CROW[1] | LOCATED | LVCMOS33_IN | PL6A | | | |
|
||||
| 17/3 | nCRAS | LOCATED | LVCMOS33_IN | PL6B | | | |
|
||||
| 18/3 | MAin[7] | LOCATED | LVCMOS33_IN | PL6C | | | |
|
||||
| 19/3 | MAin[5] | LOCATED | LVCMOS33_IN | PL6D | | | |
|
||||
| 20/3 | MAin[4] | LOCATED | LVCMOS33_IN | PL7A | PCLKT3_0 | | |
|
||||
| 21/3 | MAin[3] | LOCATED | LVCMOS33_IN | PL7B | PCLKC3_0 | | |
|
||||
| 24/3 | MAin[6] | LOCATED | LVCMOS33_IN | PL7C | | | |
|
||||
| 25/3 | MAin[8] | LOCATED | LVCMOS33_IN | PL7D | | | |
|
||||
| 27/2 | unused, PULL:DOWN | | | PB4A | CSSPIN | | |
|
||||
| 28/2 | unused, PULL:DOWN | | | PB4B | | | |
|
||||
| 29/2 | unused, PULL:DOWN | | | PB4C | | | |
|
||||
| 30/2 | unused, PULL:DOWN | | | PB4D | | | |
|
||||
| 31/2 | unused, PULL:DOWN | | | PB6A | MCLK/CCLK | | |
|
||||
| 32/2 | MAin[9] | LOCATED | LVCMOS33_IN | PB6B | SO/SPISO | | |
|
||||
| 34/2 | LED | LOCATED | LVCMOS33_OUT | PB6C | PCLKT2_0 | | |
|
||||
| 35/2 | unused, PULL:DOWN | | | PB6D | PCLKC2_0 | | |
|
||||
| 36/2 | RD[0] | LOCATED | LVCMOS33_BIDI | PB10A | | | |
|
||||
| 37/2 | RD[1] | LOCATED | LVCMOS33_BIDI | PB10B | | | |
|
||||
| 38/2 | RD[2] | LOCATED | LVCMOS33_BIDI | PB10C | PCLKT2_1 | | |
|
||||
| 39/2 | RD[3] | LOCATED | LVCMOS33_BIDI | PB10D | PCLKC2_1 | | |
|
||||
| 40/2 | RD[4] | LOCATED | LVCMOS33_BIDI | PB12A | | | |
|
||||
| 41/2 | RD[5] | LOCATED | LVCMOS33_BIDI | PB12B | | | |
|
||||
| 42/2 | RD[6] | LOCATED | LVCMOS33_BIDI | PB12C | | | |
|
||||
| 43/2 | RD[7] | LOCATED | LVCMOS33_BIDI | PB12D | | | |
|
||||
| 45/2 | unused, PULL:DOWN | | | PB14A | | | |
|
||||
| 47/2 | unused, PULL:DOWN | | | PB14B | | | |
|
||||
| 48/2 | RDQML | LOCATED | LVCMOS33_OUT | PB14C | SN | | |
|
||||
| 49/2 | nRWE | LOCATED | LVCMOS33_OUT | PB14D | SI/SISPI | | |
|
||||
| 51/1 | RDQMH | LOCATED | LVCMOS33_OUT | PR7D | | | |
|
||||
| 52/1 | nRCAS | LOCATED | LVCMOS33_OUT | PR7C | | | |
|
||||
| 53/1 | RCKE | LOCATED | LVCMOS33_OUT | PR7B | | | |
|
||||
| 54/1 | nRRAS | LOCATED | LVCMOS33_OUT | PR7A | | | |
|
||||
| 57/1 | nRCS | LOCATED | LVCMOS33_OUT | PR6D | | | |
|
||||
| 58/1 | RBA[0] | LOCATED | LVCMOS33_OUT | PR6C | | | |
|
||||
| 59/1 | RA[11] | LOCATED | LVCMOS33_OUT | PR6B | | | |
|
||||
| 60/1 | RBA[1] | LOCATED | LVCMOS33_OUT | PR6A | | | |
|
||||
| 62/1 | RCLK | LOCATED | LVCMOS33_IN | PR5D | PCLKC1_0 | | |
|
||||
| 63/1 | RA[9] | LOCATED | LVCMOS33_OUT | PR5C | PCLKT1_0 | | |
|
||||
| 64/1 | RA[10] | LOCATED | LVCMOS33_OUT | PR5B | | | |
|
||||
| 65/1 | RA[8] | LOCATED | LVCMOS33_OUT | PR5A | | | |
|
||||
| 66/1 | RA[0] | LOCATED | LVCMOS33_OUT | PR3D | | | |
|
||||
| 67/1 | RA[1] | LOCATED | LVCMOS33_OUT | PR3C | | | |
|
||||
| 68/1 | RA[6] | LOCATED | LVCMOS33_OUT | PR3B | | | |
|
||||
| 69/1 | RA[2] | LOCATED | LVCMOS33_OUT | PR3A | | | |
|
||||
| 70/1 | RA[5] | LOCATED | LVCMOS33_OUT | PR2D | | | |
|
||||
| 71/1 | RA[3] | LOCATED | LVCMOS33_OUT | PR2C | | | |
|
||||
| 74/1 | RA[4] | LOCATED | LVCMOS33_OUT | PR2B | | | |
|
||||
| 75/1 | RA[7] | LOCATED | LVCMOS33_OUT | PR2A | | | |
|
||||
| 76/0 | Dout[0] | LOCATED | LVCMOS33_OUT | PT11D | DONE | | |
|
||||
| 77/0 | unused, PULL:DOWN | | | PT11C | INITN | | |
|
||||
| 78/0 | Dout[6] | LOCATED | LVCMOS33_OUT | PT11A | | | |
|
||||
| 81/0 | unused, PULL:DOWN | | | PT10D | PROGRAMN | | |
|
||||
| 82/0 | Dout[7] | LOCATED | LVCMOS33_OUT | PT10C | JTAGENB | | |
|
||||
| 83/0 | Dout[4] | LOCATED | LVCMOS33_OUT | PT10B | | | |
|
||||
| 84/0 | Dout[5] | LOCATED | LVCMOS33_OUT | PT10A | | | |
|
||||
| 85/0 | Dout[3] | LOCATED | LVCMOS33_OUT | PT9D | SDA/PCLKC0_0 | | |
|
||||
| 86/0 | Dout[1] | LOCATED | LVCMOS33_OUT | PT9C | SCL/PCLKT0_0 | | |
|
||||
| 87/0 | Dout[2] | LOCATED | LVCMOS33_OUT | PT9B | PCLKC0_1 | | |
|
||||
| 88/0 | Din[2] | LOCATED | LVCMOS33_IN | PT9A | PCLKT0_1 | | |
|
||||
| 90/0 | Reserved: sysCONFIG | | | PT7D | TMS | | |
|
||||
| 91/0 | Reserved: sysCONFIG | | | PT7C | TCK | | |
|
||||
| 94/0 | Reserved: sysCONFIG | | | PT7B | TDI | | |
|
||||
| 95/0 | Reserved: sysCONFIG | | | PT7A | TDO | | |
|
||||
| 96/0 | Din[1] | LOCATED | LVCMOS33_IN | PT6D | | | |
|
||||
| 97/0 | Din[3] | LOCATED | LVCMOS33_IN | PT6C | | | |
|
||||
| 98/0 | Din[5] | LOCATED | LVCMOS33_IN | PT6B | | | |
|
||||
| 99/0 | Din[4] | LOCATED | LVCMOS33_IN | PT6A | | | |
|
||||
| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | |
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
|
||||
sysCONFIG Pins:
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode |
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
| PT7D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP |
|
||||
| PT7C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down |
|
||||
| PT7B | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP |
|
||||
| PT7A | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP |
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
|
||||
Dedicated sysCONFIG Pins:
|
||||
|
||||
|
||||
List of All Pins' Locate Preferences Based on Final Placement After PAR
|
||||
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste):
|
||||
|
||||
LOCATE COMP "CROW[0]" SITE "10";
|
||||
LOCATE COMP "CROW[1]" SITE "16";
|
||||
LOCATE COMP "Din[0]" SITE "3";
|
||||
LOCATE COMP "Din[1]" SITE "96";
|
||||
LOCATE COMP "Din[2]" SITE "88";
|
||||
LOCATE COMP "Din[3]" SITE "97";
|
||||
LOCATE COMP "Din[4]" SITE "99";
|
||||
LOCATE COMP "Din[5]" SITE "98";
|
||||
LOCATE COMP "Din[6]" SITE "2";
|
||||
LOCATE COMP "Din[7]" SITE "1";
|
||||
LOCATE COMP "Dout[0]" SITE "76";
|
||||
LOCATE COMP "Dout[1]" SITE "86";
|
||||
LOCATE COMP "Dout[2]" SITE "87";
|
||||
LOCATE COMP "Dout[3]" SITE "85";
|
||||
LOCATE COMP "Dout[4]" SITE "83";
|
||||
LOCATE COMP "Dout[5]" SITE "84";
|
||||
LOCATE COMP "Dout[6]" SITE "78";
|
||||
LOCATE COMP "Dout[7]" SITE "82";
|
||||
LOCATE COMP "LED" SITE "34";
|
||||
LOCATE COMP "MAin[0]" SITE "14";
|
||||
LOCATE COMP "MAin[1]" SITE "12";
|
||||
LOCATE COMP "MAin[2]" SITE "13";
|
||||
LOCATE COMP "MAin[3]" SITE "21";
|
||||
LOCATE COMP "MAin[4]" SITE "20";
|
||||
LOCATE COMP "MAin[5]" SITE "19";
|
||||
LOCATE COMP "MAin[6]" SITE "24";
|
||||
LOCATE COMP "MAin[7]" SITE "18";
|
||||
LOCATE COMP "MAin[8]" SITE "25";
|
||||
LOCATE COMP "MAin[9]" SITE "32";
|
||||
LOCATE COMP "PHI2" SITE "8";
|
||||
LOCATE COMP "RA[0]" SITE "66";
|
||||
LOCATE COMP "RA[10]" SITE "64";
|
||||
LOCATE COMP "RA[11]" SITE "59";
|
||||
LOCATE COMP "RA[1]" SITE "67";
|
||||
LOCATE COMP "RA[2]" SITE "69";
|
||||
LOCATE COMP "RA[3]" SITE "71";
|
||||
LOCATE COMP "RA[4]" SITE "74";
|
||||
LOCATE COMP "RA[5]" SITE "70";
|
||||
LOCATE COMP "RA[6]" SITE "68";
|
||||
LOCATE COMP "RA[7]" SITE "75";
|
||||
LOCATE COMP "RA[8]" SITE "65";
|
||||
LOCATE COMP "RA[9]" SITE "63";
|
||||
LOCATE COMP "RBA[0]" SITE "58";
|
||||
LOCATE COMP "RBA[1]" SITE "60";
|
||||
LOCATE COMP "RCKE" SITE "53";
|
||||
LOCATE COMP "RCLK" SITE "62";
|
||||
LOCATE COMP "RDQMH" SITE "51";
|
||||
LOCATE COMP "RDQML" SITE "48";
|
||||
LOCATE COMP "RD[0]" SITE "36";
|
||||
LOCATE COMP "RD[1]" SITE "37";
|
||||
LOCATE COMP "RD[2]" SITE "38";
|
||||
LOCATE COMP "RD[3]" SITE "39";
|
||||
LOCATE COMP "RD[4]" SITE "40";
|
||||
LOCATE COMP "RD[5]" SITE "41";
|
||||
LOCATE COMP "RD[6]" SITE "42";
|
||||
LOCATE COMP "RD[7]" SITE "43";
|
||||
LOCATE COMP "nCCAS" SITE "9";
|
||||
LOCATE COMP "nCRAS" SITE "17";
|
||||
LOCATE COMP "nFWE" SITE "15";
|
||||
LOCATE COMP "nRCAS" SITE "52";
|
||||
LOCATE COMP "nRCS" SITE "57";
|
||||
LOCATE COMP "nRRAS" SITE "54";
|
||||
LOCATE COMP "nRWE" SITE "49";
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Sat Aug 19 21:55:09 2023
|
||||
|
||||
|
|
|
|||
|
|
@ -1,264 +1,243 @@
|
|||
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Wed Aug 16 20:59:37 2023
|
||||
|
||||
C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f LCMXO2_640HC_impl1.p2t
|
||||
LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir LCMXO2_640HC_impl1.prf -gui
|
||||
-msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
|
||||
|
||||
|
||||
Preference file: LCMXO2_640HC_impl1.prf.
|
||||
|
||||
Level/ Number Worst Timing Worst Timing Run NCD
|
||||
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
|
||||
---------- -------- ----- ------ ----------- ----------- ---- ------
|
||||
5_1 * 0 4.922 0 0.088 0 07 Completed
|
||||
|
||||
* : Design saved.
|
||||
|
||||
Total (real) run time for 1-seed: 7 secs
|
||||
|
||||
par done!
|
||||
|
||||
Note: user must run 'Trace' for timing closure signoff.
|
||||
|
||||
Lattice Place and Route Report for Design "LCMXO2_640HC_impl1_map.ncd"
|
||||
Wed Aug 16 20:59:37 2023
|
||||
|
||||
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
|
||||
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir/5_1.ncd LCMXO2_640HC_impl1.prf
|
||||
Preference file: LCMXO2_640HC_impl1.prf.
|
||||
Placement level-cost: 5-1.
|
||||
Routing Iterations: 6
|
||||
|
||||
Loading design for application par from file LCMXO2_640HC_impl1_map.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-640HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application par from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.39.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
License checked out.
|
||||
|
||||
|
||||
Ignore Preference Error(s): True
|
||||
Device utilization summary:
|
||||
|
||||
PIO (prelim) 63+4(JTAG)/80 84% used
|
||||
63+4(JTAG)/79 85% bonded
|
||||
IOLOGIC 25/80 31% used
|
||||
|
||||
SLICE 117/320 36% used
|
||||
|
||||
EFB 1/1 100% used
|
||||
|
||||
|
||||
Number of Signals: 380
|
||||
Number of Connections: 1008
|
||||
|
||||
Pin Constraint Summary:
|
||||
63 out of 63 pins locked (100% locked).
|
||||
|
||||
The following 3 signals are selected to use the primary clock routing resources:
|
||||
RCLK_c (driver: RCLK, clk load #: 46)
|
||||
PHI2_c (driver: PHI2, clk load #: 19)
|
||||
nCRAS_c (driver: nCRAS, clk load #: 10)
|
||||
|
||||
WARNING - par: Signal "RCLK_c" is selected to use Primary clock resources. However, its driver comp "RCLK" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
WARNING - par: Signal "nCRAS_c" is selected to use Primary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
|
||||
The following 2 signals are selected to use the secondary clock routing resources:
|
||||
nCCAS_c (driver: nCCAS, clk load #: 8, sr load #: 0, ce load #: 0)
|
||||
un1_wb_clk32_i (driver: SLICE_103, clk load #: 0, sr load #: 0, ce load #: 10)
|
||||
|
||||
WARNING - par: Signal "nCCAS_c" is selected to use Secondary clock resources. However, its driver comp "nCCAS" is located at "9", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
No signal is selected as Global Set/Reset.
|
||||
Starting Placer Phase 0.
|
||||
..............
|
||||
Finished Placer Phase 0. REAL time: 0 secs
|
||||
|
||||
Starting Placer Phase 1.
|
||||
...................
|
||||
Placer score = 55012.
|
||||
Finished Placer Phase 1. REAL time: 4 secs
|
||||
|
||||
Starting Placer Phase 2.
|
||||
.
|
||||
Placer score = 54994
|
||||
Finished Placer Phase 2. REAL time: 4 secs
|
||||
|
||||
|
||||
------------------ Clock Report ------------------
|
||||
|
||||
Global Clock Resources:
|
||||
CLK_PIN : 0 out of 8 (0%)
|
||||
General PIO: 4 out of 80 (5%)
|
||||
DCM : 0 out of 2 (0%)
|
||||
DCC : 0 out of 8 (0%)
|
||||
|
||||
Global Clocks:
|
||||
PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 46
|
||||
PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 19
|
||||
PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 10
|
||||
SECONDARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 8, ce load = 0, sr load = 0
|
||||
SECONDARY "un1_wb_clk32_i" from F0 on comp "SLICE_103" on site "R6C8B", clk load = 0, ce load = 10, sr load = 0
|
||||
|
||||
PRIMARY : 3 out of 8 (37%)
|
||||
SECONDARY: 2 out of 8 (25%)
|
||||
|
||||
--------------- End of Clock Report ---------------
|
||||
|
||||
|
||||
I/O Usage Summary (final):
|
||||
63 + 4(JTAG) out of 80 (83.8%) PIO sites used.
|
||||
63 + 4(JTAG) out of 79 (84.8%) bonded PIO sites used.
|
||||
Number of PIO comps: 63; differential: 0.
|
||||
Number of Vref pins used: 0.
|
||||
|
||||
I/O Bank Usage Summary:
|
||||
+----------+----------------+------------+-----------+
|
||||
| I/O Bank | Usage | Bank Vccio | Bank Vref |
|
||||
+----------+----------------+------------+-----------+
|
||||
| 0 | 13 / 19 ( 68%) | 3.3V | - |
|
||||
| 1 | 20 / 20 (100%) | 3.3V | - |
|
||||
| 2 | 12 / 20 ( 60%) | 3.3V | - |
|
||||
| 3 | 18 / 20 ( 90%) | 3.3V | - |
|
||||
+----------+----------------+------------+-----------+
|
||||
|
||||
Total placer CPU time: 3 secs
|
||||
|
||||
Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd.
|
||||
|
||||
0 connections routed; 1008 unrouted.
|
||||
Starting router resource preassignment
|
||||
WARNING - par: The driver of primary clock net RCLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
|
||||
WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
|
||||
|
||||
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
|
||||
Signal=wb_clk loads=1 clock_loads=1
|
||||
|
||||
Completed router resource preassignment. Real time: 5 secs
|
||||
|
||||
Start NBR router at 20:59:43 08/16/23
|
||||
|
||||
*****************************************************************
|
||||
Info: NBR allows conflicts(one node used by more than one signal)
|
||||
in the earlier iterations. In each iteration, it tries to
|
||||
solve the conflicts while keeping the critical connections
|
||||
routed as short as possible. The routing process is said to
|
||||
be completed when no conflicts exist and all connections
|
||||
are routed.
|
||||
Note: NBR uses a different method to calculate timing slacks. The
|
||||
worst slack and total negative slack may not be the same as
|
||||
that in TRCE report. You should always run TRCE to verify
|
||||
your design.
|
||||
*****************************************************************
|
||||
|
||||
Start NBR special constraint process at 20:59:43 08/16/23
|
||||
|
||||
Start NBR section for initial routing at 20:59:43 08/16/23
|
||||
Level 1, iteration 1
|
||||
0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs
|
||||
Level 2, iteration 1
|
||||
0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs
|
||||
Level 3, iteration 1
|
||||
0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs
|
||||
Level 4, iteration 1
|
||||
7(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs
|
||||
|
||||
Info: Initial congestion level at 75% usage is 0
|
||||
Info: Initial congestion area at 75% usage is 0 (0.00%)
|
||||
|
||||
Start NBR section for normal routing at 20:59:43 08/16/23
|
||||
Level 1, iteration 1
|
||||
0(0.00%) conflict; 11(1.09%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs
|
||||
Level 4, iteration 1
|
||||
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs
|
||||
Level 4, iteration 2
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs
|
||||
|
||||
Start NBR section for setup/hold timing optimization with effort level 3 at 20:59:43 08/16/23
|
||||
Level 4, iteration 0
|
||||
Level 4, iteration 1
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<hold >: 0.083ns/0.000ns; real time: 6 secs
|
||||
Level 4, iteration 0
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 4.902ns/0.000ns; real time: 6 secs
|
||||
Level 4, iteration 1
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 4.902ns/0.000ns; real time: 6 secs
|
||||
|
||||
Start NBR section for re-routing at 20:59:44 08/16/23
|
||||
Level 4, iteration 1
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 7 secs
|
||||
|
||||
Start NBR section for post-routing at 20:59:44 08/16/23
|
||||
|
||||
End NBR router with 0 unrouted connection
|
||||
|
||||
NBR Summary
|
||||
-----------
|
||||
Number of unrouted connections : 0 (0.00%)
|
||||
Number of connections with timing violations : 0 (0.00%)
|
||||
Estimated worst slack<setup> : 4.922ns
|
||||
Timing score<setup> : 0
|
||||
-----------
|
||||
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
|
||||
|
||||
|
||||
|
||||
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
|
||||
Signal=wb_clk loads=1 clock_loads=1
|
||||
|
||||
Total CPU time 6 secs
|
||||
Total REAL time: 7 secs
|
||||
Completely routed.
|
||||
End of route. 1008 routed (100.00%); 0 unrouted.
|
||||
|
||||
Hold time timing score: 0, hold timing errors: 0
|
||||
|
||||
Timing score: 0
|
||||
|
||||
Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd.
|
||||
|
||||
|
||||
All signals are completely routed.
|
||||
|
||||
|
||||
PAR_SUMMARY::Run status = Completed
|
||||
PAR_SUMMARY::Number of unrouted conns = 0
|
||||
PAR_SUMMARY::Worst slack<setup/<ns>> = 4.922
|
||||
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
|
||||
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.088
|
||||
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
|
||||
PAR_SUMMARY::Number of errors = 0
|
||||
|
||||
Total CPU time to completion: 6 secs
|
||||
Total REAL time to completion: 7 secs
|
||||
|
||||
par done!
|
||||
|
||||
Note: user must run 'Trace' for timing closure signoff.
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Sat Aug 19 21:55:01 2023
|
||||
|
||||
C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f LCMXO2_640HC_impl1.p2t
|
||||
LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir LCMXO2_640HC_impl1.prf -gui
|
||||
-msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
|
||||
|
||||
|
||||
Preference file: LCMXO2_640HC_impl1.prf.
|
||||
|
||||
Level/ Number Worst Timing Worst Timing Run NCD
|
||||
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
|
||||
---------- -------- ----- ------ ----------- ----------- ---- ------
|
||||
5_1 * 0 6.966 0 0.304 0 10 Completed
|
||||
|
||||
* : Design saved.
|
||||
|
||||
Total (real) run time for 1-seed: 10 secs
|
||||
|
||||
par done!
|
||||
|
||||
Note: user must run 'Trace' for timing closure signoff.
|
||||
|
||||
Lattice Place and Route Report for Design "LCMXO2_640HC_impl1_map.ncd"
|
||||
Sat Aug 19 21:55:01 2023
|
||||
|
||||
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
|
||||
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir/5_1.ncd LCMXO2_640HC_impl1.prf
|
||||
Preference file: LCMXO2_640HC_impl1.prf.
|
||||
Placement level-cost: 5-1.
|
||||
Routing Iterations: 6
|
||||
|
||||
Loading design for application par from file LCMXO2_640HC_impl1_map.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-640HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application par from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.39.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
License checked out.
|
||||
|
||||
|
||||
Ignore Preference Error(s): True
|
||||
Device utilization summary:
|
||||
|
||||
PIO (prelim) 63+4(JTAG)/80 84% used
|
||||
63+4(JTAG)/79 85% bonded
|
||||
IOLOGIC 25/80 31% used
|
||||
|
||||
SLICE 113/320 35% used
|
||||
|
||||
EFB 1/1 100% used
|
||||
|
||||
|
||||
Number of Signals: 374
|
||||
Number of Connections: 978
|
||||
|
||||
Pin Constraint Summary:
|
||||
63 out of 63 pins locked (100% locked).
|
||||
|
||||
The following 3 signals are selected to use the primary clock routing resources:
|
||||
RCLK_c (driver: RCLK, clk load #: 47)
|
||||
PHI2_c (driver: PHI2, clk load #: 21)
|
||||
nCRAS_c (driver: nCRAS, clk load #: 10)
|
||||
|
||||
WARNING - par: Signal "RCLK_c" is selected to use Primary clock resources. However, its driver comp "RCLK" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
WARNING - par: Signal "nCRAS_c" is selected to use Primary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
|
||||
The following 1 signal is selected to use the secondary clock routing resources:
|
||||
nCCAS_c (driver: nCCAS, clk load #: 8, sr load #: 0, ce load #: 0)
|
||||
|
||||
WARNING - par: Signal "nCCAS_c" is selected to use Secondary clock resources. However, its driver comp "nCCAS" is located at "9", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
No signal is selected as Global Set/Reset.
|
||||
Starting Placer Phase 0.
|
||||
............
|
||||
Finished Placer Phase 0. REAL time: 0 secs
|
||||
|
||||
Starting Placer Phase 1.
|
||||
....................
|
||||
Placer score = 53481.
|
||||
Finished Placer Phase 1. REAL time: 5 secs
|
||||
|
||||
Starting Placer Phase 2.
|
||||
.
|
||||
Placer score = 53406
|
||||
Finished Placer Phase 2. REAL time: 5 secs
|
||||
|
||||
|
||||
------------------ Clock Report ------------------
|
||||
|
||||
Global Clock Resources:
|
||||
CLK_PIN : 0 out of 8 (0%)
|
||||
General PIO: 4 out of 80 (5%)
|
||||
DCM : 0 out of 2 (0%)
|
||||
DCC : 0 out of 8 (0%)
|
||||
|
||||
Global Clocks:
|
||||
PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 47
|
||||
PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 21
|
||||
PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 10
|
||||
SECONDARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 8, ce load = 0, sr load = 0
|
||||
|
||||
PRIMARY : 3 out of 8 (37%)
|
||||
SECONDARY: 1 out of 8 (12%)
|
||||
|
||||
--------------- End of Clock Report ---------------
|
||||
|
||||
|
||||
I/O Usage Summary (final):
|
||||
63 + 4(JTAG) out of 80 (83.8%) PIO sites used.
|
||||
63 + 4(JTAG) out of 79 (84.8%) bonded PIO sites used.
|
||||
Number of PIO comps: 63; differential: 0.
|
||||
Number of Vref pins used: 0.
|
||||
|
||||
I/O Bank Usage Summary:
|
||||
+----------+----------------+------------+-----------+
|
||||
| I/O Bank | Usage | Bank Vccio | Bank Vref |
|
||||
+----------+----------------+------------+-----------+
|
||||
| 0 | 13 / 19 ( 68%) | 3.3V | - |
|
||||
| 1 | 20 / 20 (100%) | 3.3V | - |
|
||||
| 2 | 12 / 20 ( 60%) | 3.3V | - |
|
||||
| 3 | 18 / 20 ( 90%) | 3.3V | - |
|
||||
+----------+----------------+------------+-----------+
|
||||
|
||||
Total placer CPU time: 5 secs
|
||||
|
||||
Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd.
|
||||
|
||||
0 connections routed; 978 unrouted.
|
||||
Starting router resource preassignment
|
||||
WARNING - par: The driver of primary clock net RCLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
|
||||
WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
|
||||
|
||||
Completed router resource preassignment. Real time: 8 secs
|
||||
|
||||
Start NBR router at 21:55:09 08/19/23
|
||||
|
||||
*****************************************************************
|
||||
Info: NBR allows conflicts(one node used by more than one signal)
|
||||
in the earlier iterations. In each iteration, it tries to
|
||||
solve the conflicts while keeping the critical connections
|
||||
routed as short as possible. The routing process is said to
|
||||
be completed when no conflicts exist and all connections
|
||||
are routed.
|
||||
Note: NBR uses a different method to calculate timing slacks. The
|
||||
worst slack and total negative slack may not be the same as
|
||||
that in TRCE report. You should always run TRCE to verify
|
||||
your design.
|
||||
*****************************************************************
|
||||
|
||||
Start NBR special constraint process at 21:55:09 08/19/23
|
||||
|
||||
Start NBR section for initial routing at 21:55:10 08/19/23
|
||||
Level 1, iteration 1
|
||||
0(0.00%) conflict; 776(79.35%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 7.085ns/0.000ns; real time: 9 secs
|
||||
Level 2, iteration 1
|
||||
0(0.00%) conflict; 771(78.83%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 7.138ns/0.000ns; real time: 9 secs
|
||||
Level 3, iteration 1
|
||||
0(0.00%) conflict; 765(78.22%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 7.276ns/0.000ns; real time: 9 secs
|
||||
Level 4, iteration 1
|
||||
10(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 6.966ns/0.000ns; real time: 9 secs
|
||||
|
||||
Info: Initial congestion level at 75% usage is 0
|
||||
Info: Initial congestion area at 75% usage is 0 (0.00%)
|
||||
|
||||
Start NBR section for normal routing at 21:55:10 08/19/23
|
||||
Level 4, iteration 1
|
||||
3(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 6.966ns/0.000ns; real time: 9 secs
|
||||
Level 4, iteration 2
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 6.966ns/0.000ns; real time: 9 secs
|
||||
|
||||
Start NBR section for setup/hold timing optimization with effort level 3 at 21:55:10 08/19/23
|
||||
|
||||
Start NBR section for re-routing at 21:55:10 08/19/23
|
||||
Level 4, iteration 1
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 6.966ns/0.000ns; real time: 9 secs
|
||||
|
||||
Start NBR section for post-routing at 21:55:10 08/19/23
|
||||
|
||||
End NBR router with 0 unrouted connection
|
||||
|
||||
NBR Summary
|
||||
-----------
|
||||
Number of unrouted connections : 0 (0.00%)
|
||||
Number of connections with timing violations : 0 (0.00%)
|
||||
Estimated worst slack<setup> : 6.966ns
|
||||
Timing score<setup> : 0
|
||||
-----------
|
||||
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
|
||||
|
||||
|
||||
|
||||
Total CPU time 9 secs
|
||||
Total REAL time: 9 secs
|
||||
Completely routed.
|
||||
End of route. 978 routed (100.00%); 0 unrouted.
|
||||
|
||||
Hold time timing score: 0, hold timing errors: 0
|
||||
|
||||
Timing score: 0
|
||||
|
||||
Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd.
|
||||
|
||||
|
||||
All signals are completely routed.
|
||||
|
||||
|
||||
PAR_SUMMARY::Run status = Completed
|
||||
PAR_SUMMARY::Number of unrouted conns = 0
|
||||
PAR_SUMMARY::Worst slack<setup/<ns>> = 6.966
|
||||
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
|
||||
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.304
|
||||
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
|
||||
PAR_SUMMARY::Number of errors = 0
|
||||
|
||||
Total CPU time to completion: 9 secs
|
||||
Total REAL time to completion: 10 secs
|
||||
|
||||
par done!
|
||||
|
||||
Note: user must run 'Trace' for timing closure signoff.
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
|
|
|||
|
|
@ -1,75 +1,75 @@
|
|||
SCHEMATIC START ;
|
||||
# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Wed Aug 16 20:59:37 2023
|
||||
|
||||
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
|
||||
LOCATE COMP "RD[0]" SITE "36" ;
|
||||
LOCATE COMP "Dout[0]" SITE "76" ;
|
||||
LOCATE COMP "PHI2" SITE "8" ;
|
||||
LOCATE COMP "RDQML" SITE "48" ;
|
||||
LOCATE COMP "RDQMH" SITE "51" ;
|
||||
LOCATE COMP "nRCAS" SITE "52" ;
|
||||
LOCATE COMP "nRRAS" SITE "54" ;
|
||||
LOCATE COMP "nRWE" SITE "49" ;
|
||||
LOCATE COMP "RCKE" SITE "53" ;
|
||||
LOCATE COMP "RCLK" SITE "62" ;
|
||||
LOCATE COMP "nRCS" SITE "57" ;
|
||||
LOCATE COMP "RD[7]" SITE "43" ;
|
||||
LOCATE COMP "RD[6]" SITE "42" ;
|
||||
LOCATE COMP "RD[5]" SITE "41" ;
|
||||
LOCATE COMP "RD[4]" SITE "40" ;
|
||||
LOCATE COMP "RD[3]" SITE "39" ;
|
||||
LOCATE COMP "RD[2]" SITE "38" ;
|
||||
LOCATE COMP "RD[1]" SITE "37" ;
|
||||
LOCATE COMP "RA[11]" SITE "59" ;
|
||||
LOCATE COMP "RA[10]" SITE "64" ;
|
||||
LOCATE COMP "RA[9]" SITE "63" ;
|
||||
LOCATE COMP "RA[8]" SITE "65" ;
|
||||
LOCATE COMP "RA[7]" SITE "75" ;
|
||||
LOCATE COMP "RA[6]" SITE "68" ;
|
||||
LOCATE COMP "RA[5]" SITE "70" ;
|
||||
LOCATE COMP "RA[4]" SITE "74" ;
|
||||
LOCATE COMP "RA[3]" SITE "71" ;
|
||||
LOCATE COMP "RA[2]" SITE "69" ;
|
||||
LOCATE COMP "RA[1]" SITE "67" ;
|
||||
LOCATE COMP "RA[0]" SITE "66" ;
|
||||
LOCATE COMP "RBA[1]" SITE "60" ;
|
||||
LOCATE COMP "RBA[0]" SITE "58" ;
|
||||
LOCATE COMP "LED" SITE "34" ;
|
||||
LOCATE COMP "nFWE" SITE "15" ;
|
||||
LOCATE COMP "nCRAS" SITE "17" ;
|
||||
LOCATE COMP "nCCAS" SITE "9" ;
|
||||
LOCATE COMP "Dout[7]" SITE "82" ;
|
||||
LOCATE COMP "Dout[6]" SITE "78" ;
|
||||
LOCATE COMP "Dout[5]" SITE "84" ;
|
||||
LOCATE COMP "Dout[4]" SITE "83" ;
|
||||
LOCATE COMP "Dout[3]" SITE "85" ;
|
||||
LOCATE COMP "Dout[2]" SITE "87" ;
|
||||
LOCATE COMP "Dout[1]" SITE "86" ;
|
||||
LOCATE COMP "Din[7]" SITE "1" ;
|
||||
LOCATE COMP "Din[6]" SITE "2" ;
|
||||
LOCATE COMP "Din[5]" SITE "98" ;
|
||||
LOCATE COMP "Din[4]" SITE "99" ;
|
||||
LOCATE COMP "Din[3]" SITE "97" ;
|
||||
LOCATE COMP "Din[2]" SITE "88" ;
|
||||
LOCATE COMP "Din[1]" SITE "96" ;
|
||||
LOCATE COMP "Din[0]" SITE "3" ;
|
||||
LOCATE COMP "CROW[1]" SITE "16" ;
|
||||
LOCATE COMP "CROW[0]" SITE "10" ;
|
||||
LOCATE COMP "MAin[9]" SITE "32" ;
|
||||
LOCATE COMP "MAin[8]" SITE "25" ;
|
||||
LOCATE COMP "MAin[7]" SITE "18" ;
|
||||
LOCATE COMP "MAin[6]" SITE "24" ;
|
||||
LOCATE COMP "MAin[5]" SITE "19" ;
|
||||
LOCATE COMP "MAin[4]" SITE "20" ;
|
||||
LOCATE COMP "MAin[3]" SITE "21" ;
|
||||
LOCATE COMP "MAin[2]" SITE "13" ;
|
||||
LOCATE COMP "MAin[1]" SITE "12" ;
|
||||
LOCATE COMP "MAin[0]" SITE "14" ;
|
||||
FREQUENCY PORT "PHI2" 2.900000 MHz ;
|
||||
FREQUENCY PORT "nCCAS" 2.900000 MHz ;
|
||||
FREQUENCY PORT "nCRAS" 2.900000 MHz ;
|
||||
FREQUENCY PORT "RCLK" 62.500000 MHz ;
|
||||
SCHEMATIC END ;
|
||||
BLOCK RESETPATHS ;
|
||||
BLOCK ASYNCPATHS ;
|
||||
COMMERCIAL ;
|
||||
SCHEMATIC START ;
|
||||
# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Sat Aug 19 21:54:57 2023
|
||||
|
||||
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
|
||||
LOCATE COMP "RD[0]" SITE "36" ;
|
||||
LOCATE COMP "Dout[0]" SITE "76" ;
|
||||
LOCATE COMP "PHI2" SITE "8" ;
|
||||
LOCATE COMP "RDQML" SITE "48" ;
|
||||
LOCATE COMP "RDQMH" SITE "51" ;
|
||||
LOCATE COMP "nRCAS" SITE "52" ;
|
||||
LOCATE COMP "nRRAS" SITE "54" ;
|
||||
LOCATE COMP "nRWE" SITE "49" ;
|
||||
LOCATE COMP "RCKE" SITE "53" ;
|
||||
LOCATE COMP "RCLK" SITE "62" ;
|
||||
LOCATE COMP "nRCS" SITE "57" ;
|
||||
LOCATE COMP "RD[7]" SITE "43" ;
|
||||
LOCATE COMP "RD[6]" SITE "42" ;
|
||||
LOCATE COMP "RD[5]" SITE "41" ;
|
||||
LOCATE COMP "RD[4]" SITE "40" ;
|
||||
LOCATE COMP "RD[3]" SITE "39" ;
|
||||
LOCATE COMP "RD[2]" SITE "38" ;
|
||||
LOCATE COMP "RD[1]" SITE "37" ;
|
||||
LOCATE COMP "RA[11]" SITE "59" ;
|
||||
LOCATE COMP "RA[10]" SITE "64" ;
|
||||
LOCATE COMP "RA[9]" SITE "63" ;
|
||||
LOCATE COMP "RA[8]" SITE "65" ;
|
||||
LOCATE COMP "RA[7]" SITE "75" ;
|
||||
LOCATE COMP "RA[6]" SITE "68" ;
|
||||
LOCATE COMP "RA[5]" SITE "70" ;
|
||||
LOCATE COMP "RA[4]" SITE "74" ;
|
||||
LOCATE COMP "RA[3]" SITE "71" ;
|
||||
LOCATE COMP "RA[2]" SITE "69" ;
|
||||
LOCATE COMP "RA[1]" SITE "67" ;
|
||||
LOCATE COMP "RA[0]" SITE "66" ;
|
||||
LOCATE COMP "RBA[1]" SITE "60" ;
|
||||
LOCATE COMP "RBA[0]" SITE "58" ;
|
||||
LOCATE COMP "LED" SITE "34" ;
|
||||
LOCATE COMP "nFWE" SITE "15" ;
|
||||
LOCATE COMP "nCRAS" SITE "17" ;
|
||||
LOCATE COMP "nCCAS" SITE "9" ;
|
||||
LOCATE COMP "Dout[7]" SITE "82" ;
|
||||
LOCATE COMP "Dout[6]" SITE "78" ;
|
||||
LOCATE COMP "Dout[5]" SITE "84" ;
|
||||
LOCATE COMP "Dout[4]" SITE "83" ;
|
||||
LOCATE COMP "Dout[3]" SITE "85" ;
|
||||
LOCATE COMP "Dout[2]" SITE "87" ;
|
||||
LOCATE COMP "Dout[1]" SITE "86" ;
|
||||
LOCATE COMP "Din[7]" SITE "1" ;
|
||||
LOCATE COMP "Din[6]" SITE "2" ;
|
||||
LOCATE COMP "Din[5]" SITE "98" ;
|
||||
LOCATE COMP "Din[4]" SITE "99" ;
|
||||
LOCATE COMP "Din[3]" SITE "97" ;
|
||||
LOCATE COMP "Din[2]" SITE "88" ;
|
||||
LOCATE COMP "Din[1]" SITE "96" ;
|
||||
LOCATE COMP "Din[0]" SITE "3" ;
|
||||
LOCATE COMP "CROW[1]" SITE "16" ;
|
||||
LOCATE COMP "CROW[0]" SITE "10" ;
|
||||
LOCATE COMP "MAin[9]" SITE "32" ;
|
||||
LOCATE COMP "MAin[8]" SITE "25" ;
|
||||
LOCATE COMP "MAin[7]" SITE "18" ;
|
||||
LOCATE COMP "MAin[6]" SITE "24" ;
|
||||
LOCATE COMP "MAin[5]" SITE "19" ;
|
||||
LOCATE COMP "MAin[4]" SITE "20" ;
|
||||
LOCATE COMP "MAin[3]" SITE "21" ;
|
||||
LOCATE COMP "MAin[2]" SITE "13" ;
|
||||
LOCATE COMP "MAin[1]" SITE "12" ;
|
||||
LOCATE COMP "MAin[0]" SITE "14" ;
|
||||
FREQUENCY PORT "PHI2" 2.900000 MHz ;
|
||||
FREQUENCY PORT "nCCAS" 2.900000 MHz ;
|
||||
FREQUENCY PORT "nCRAS" 2.900000 MHz ;
|
||||
FREQUENCY PORT "RCLK" 62.500000 MHz ;
|
||||
SCHEMATIC END ;
|
||||
BLOCK RESETPATHS ;
|
||||
BLOCK ASYNCPATHS ;
|
||||
COMMERCIAL ;
|
||||
|
|
|
|||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
Binary file not shown.
File diff suppressed because it is too large
Load Diff
Binary file not shown.
Binary file not shown.
|
|
@ -2,4 +2,4 @@
|
|||
|
||||
-g RamCfg:Reset
|
||||
|
||||
-path "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC"
|
||||
-path "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC"
|
||||
|
|
|
|||
|
|
@ -0,0 +1,423 @@
|
|||
|
||||
Loading design for application trce from file lcmxo2_640hc_impl1_map.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-640HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.39.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
Setup and Hold Report
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
|
||||
Sat Aug 19 21:54:58 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
Report Information
|
||||
------------------
|
||||
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o LCMXO2_640HC_impl1.tw1 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.prf
|
||||
Design file: lcmxo2_640hc_impl1_map.ncd
|
||||
Preference file: lcmxo2_640hc_impl1.prf
|
||||
Device,speed: LCMXO2-640HC,4
|
||||
Report level: verbose report, limited to 1 item per preference
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
BLOCK ASYNCPATHS
|
||||
BLOCK RESETPATHS
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
================================================================================
|
||||
Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
|
||||
158 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 163.025ns (weighted slack = 326.050ns)
|
||||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q Bank_0io[2] (from PHI2_c +)
|
||||
Destination: FF Data in ADSubmitted (to PHI2_c -)
|
||||
|
||||
Delay: 9.223ns (33.1% logic, 66.9% route), 6 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
9.223ns physical path delay Din[2]_MGIOL to SLICE_10 meets
|
||||
172.414ns delay constraint less
|
||||
0.166ns DIN_SET requirement (totaling 172.248ns) by 163.025ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path Din[2]_MGIOL to SLICE_10:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
C2INP_DEL --- 0.577 *[2]_MGIOL.CLK to *n[2]_MGIOL.IN Din[2]_MGIOL (from PHI2_c)
|
||||
ROUTE 1 e 1.234 *n[2]_MGIOL.IN to SLICE_37.A1 Bank[2]
|
||||
CTOF_DEL --- 0.495 SLICE_37.A1 to SLICE_37.F1 SLICE_37
|
||||
ROUTE 1 e 1.234 SLICE_37.F1 to SLICE_94.D0 un1_Bank_1_4
|
||||
CTOF_DEL --- 0.495 SLICE_94.D0 to SLICE_94.F0 SLICE_94
|
||||
ROUTE 2 e 1.234 SLICE_94.F0 to SLICE_90.D0 N_304
|
||||
CTOF_DEL --- 0.495 SLICE_90.D0 to SLICE_90.F0 SLICE_90
|
||||
ROUTE 5 e 1.234 SLICE_90.F0 to SLICE_91.C1 C1WR_7
|
||||
CTOF_DEL --- 0.495 SLICE_91.C1 to SLICE_91.F1 SLICE_91
|
||||
ROUTE 2 e 1.234 SLICE_91.F1 to SLICE_10.B0 un1_ADWR
|
||||
CTOF_DEL --- 0.495 SLICE_10.B0 to SLICE_10.F0 SLICE_10
|
||||
ROUTE 1 e 0.001 SLICE_10.F0 to SLICE_10.DI0 ADSubmitted_r (to PHI2_c)
|
||||
--------
|
||||
9.223 (33.1% logic, 66.9% route), 6 logic levels.
|
||||
|
||||
Report: 53.254MHz is the maximum frequency for this preference.
|
||||
|
||||
|
||||
================================================================================
|
||||
Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
|
||||
0 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 338.168ns
|
||||
The internal maximum frequency of the following component is 150.150 MHz
|
||||
|
||||
Logical Details: Cell type Pin name Component name
|
||||
|
||||
Destination: PIO PAD nCCAS
|
||||
|
||||
Delay: 6.660ns -- based on Minimum Pulse Width
|
||||
|
||||
Report: 150.150MHz is the maximum frequency for this preference.
|
||||
|
||||
|
||||
================================================================================
|
||||
Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
|
||||
0 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 338.168ns
|
||||
The internal maximum frequency of the following component is 150.150 MHz
|
||||
|
||||
Logical Details: Cell type Pin name Component name
|
||||
|
||||
Destination: PIO PAD nCRAS
|
||||
|
||||
Delay: 6.660ns -- based on Minimum Pulse Width
|
||||
|
||||
Report: 150.150MHz is the maximum frequency for this preference.
|
||||
|
||||
|
||||
================================================================================
|
||||
Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
|
||||
844 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 6.226ns
|
||||
The internal maximum frequency of the following component is 102.312 MHz
|
||||
|
||||
Logical Details: Cell type Pin name Component name
|
||||
|
||||
Destination: EFB WBCLKI ufmefb/EFBInst_0
|
||||
|
||||
Delay: 9.774ns -- based on Minimum Pulse Width
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 6.270ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q S[0] (from RCLK_c +)
|
||||
Destination: FF Data in nRCS_0io (to RCLK_c +)
|
||||
|
||||
Delay: 9.577ns (30.6% logic, 69.4% route), 6 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
9.577ns physical path delay SLICE_16 to nRCS_MGIOL meets
|
||||
16.000ns delay constraint less
|
||||
0.153ns DO_SET requirement (totaling 15.847ns) by 6.270ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path SLICE_16 to nRCS_MGIOL:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.452 SLICE_16.CLK to SLICE_16.Q0 SLICE_16 (from RCLK_c)
|
||||
ROUTE 9 e 1.234 SLICE_16.Q0 to SLICE_45.A0 CO0
|
||||
CTOF_DEL --- 0.495 SLICE_45.A0 to SLICE_45.F0 SLICE_45
|
||||
ROUTE 4 e 0.480 SLICE_45.F0 to SLICE_45.A1 N_41
|
||||
CTOF_DEL --- 0.495 SLICE_45.A1 to SLICE_45.F1 SLICE_45
|
||||
ROUTE 2 e 1.234 SLICE_45.F1 to SLICE_77.D0 nRRAS_5_u_i_0
|
||||
CTOF_DEL --- 0.495 SLICE_77.D0 to SLICE_77.F0 SLICE_77
|
||||
ROUTE 1 e 1.234 SLICE_77.F0 to SLICE_117.B1 N_25
|
||||
CTOF_DEL --- 0.495 SLICE_117.B1 to SLICE_117.F1 SLICE_117
|
||||
ROUTE 1 e 1.234 SLICE_117.F1 to SLICE_88.C1 N_28_i_sn
|
||||
CTOF_DEL --- 0.495 SLICE_88.C1 to SLICE_88.F1 SLICE_88
|
||||
ROUTE 1 e 1.234 SLICE_88.F1 to *CS_MGIOL.OPOS N_28_i (to RCLK_c)
|
||||
--------
|
||||
9.577 (30.6% logic, 69.4% route), 6 logic levels.
|
||||
|
||||
Report: 102.312MHz is the maximum frequency for this preference.
|
||||
|
||||
Report Summary
|
||||
--------------
|
||||
----------------------------------------------------------------------------
|
||||
Preference | Constraint| Actual|Levels
|
||||
----------------------------------------------------------------------------
|
||||
| | |
|
||||
FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 53.254 MHz| 6
|
||||
| | |
|
||||
FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
|
||||
| | |
|
||||
FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
|
||||
| | |
|
||||
FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 102.312 MHz| 0
|
||||
| | |
|
||||
----------------------------------------------------------------------------
|
||||
|
||||
|
||||
All preferences were met.
|
||||
|
||||
|
||||
Clock Domains Analysis
|
||||
------------------------
|
||||
|
||||
Found 4 clocks:
|
||||
|
||||
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12
|
||||
No transfer within this clock domain is found
|
||||
|
||||
Data transfers from:
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD
|
||||
Not reported because source and destination domains are unrelated.
|
||||
To report these transfers please refer to preference CLKSKEWDIFF to define
|
||||
external clock skew between clock ports.
|
||||
|
||||
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
|
||||
No transfer within this clock domain is found
|
||||
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47
|
||||
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
|
||||
|
||||
Data transfers from:
|
||||
Clock Domain: nCRAS_c Source: nCRAS.PAD
|
||||
Not reported because source and destination domains are unrelated.
|
||||
To report these transfers please refer to preference CLKSKEWDIFF to define
|
||||
external clock skew between clock ports.
|
||||
|
||||
Clock Domain: PHI2_c Source: PHI2.PAD
|
||||
Not reported because source and destination domains are unrelated.
|
||||
To report these transfers please refer to preference CLKSKEWDIFF to define
|
||||
external clock skew between clock ports.
|
||||
|
||||
Clock Domain: PHI2_c Source: PHI2.PAD Loads: 22
|
||||
Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
|
||||
|
||||
Data transfers from:
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD
|
||||
Not reported because source and destination domains are unrelated.
|
||||
To report these transfers please refer to preference CLKSKEWDIFF to define
|
||||
external clock skew between clock ports.
|
||||
|
||||
|
||||
Timing summary (Setup):
|
||||
---------------
|
||||
|
||||
Timing errors: 0 Score: 0
|
||||
Cumulative negative slack: 0
|
||||
|
||||
Constraints cover 1002 paths, 4 nets, and 687 connections (70.25% coverage)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
|
||||
Sat Aug 19 21:54:58 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
Report Information
|
||||
------------------
|
||||
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o LCMXO2_640HC_impl1.tw1 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.prf
|
||||
Design file: lcmxo2_640hc_impl1_map.ncd
|
||||
Preference file: lcmxo2_640hc_impl1.prf
|
||||
Device,speed: LCMXO2-640HC,M
|
||||
Report level: verbose report, limited to 1 item per preference
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
BLOCK ASYNCPATHS
|
||||
BLOCK RESETPATHS
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
================================================================================
|
||||
Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
|
||||
158 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 0.447ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q ADSubmitted (from PHI2_c -)
|
||||
Destination: FF Data in ADSubmitted (to PHI2_c -)
|
||||
|
||||
Delay: 0.434ns (53.9% logic, 46.1% route), 2 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
0.434ns physical path delay SLICE_10 to SLICE_10 meets
|
||||
-0.013ns DIN_HLD and
|
||||
0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path SLICE_10 to SLICE_10:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.133 SLICE_10.CLK to SLICE_10.Q0 SLICE_10 (from PHI2_c)
|
||||
ROUTE 2 e 0.199 SLICE_10.Q0 to SLICE_10.A0 ADSubmitted
|
||||
CTOF_DEL --- 0.101 SLICE_10.A0 to SLICE_10.F0 SLICE_10
|
||||
ROUTE 1 e 0.001 SLICE_10.F0 to SLICE_10.DI0 ADSubmitted_r (to PHI2_c)
|
||||
--------
|
||||
0.434 (53.9% logic, 46.1% route), 2 logic levels.
|
||||
|
||||
|
||||
================================================================================
|
||||
Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
|
||||
0 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
================================================================================
|
||||
Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
|
||||
0 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
================================================================================
|
||||
Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
|
||||
844 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 0.351ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q CASr (from RCLK_c +)
|
||||
Destination: FF Data in CASr2 (to RCLK_c +)
|
||||
|
||||
Delay: 0.332ns (40.1% logic, 59.9% route), 1 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
0.332ns physical path delay SLICE_12 to SLICE_12 meets
|
||||
-0.019ns M_HLD and
|
||||
0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path SLICE_12 to SLICE_12:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.133 SLICE_12.CLK to SLICE_12.Q0 SLICE_12 (from RCLK_c)
|
||||
ROUTE 1 e 0.199 SLICE_12.Q0 to SLICE_12.M1 CASr (to RCLK_c)
|
||||
--------
|
||||
0.332 (40.1% logic, 59.9% route), 1 logic levels.
|
||||
|
||||
Report Summary
|
||||
--------------
|
||||
----------------------------------------------------------------------------
|
||||
Preference(MIN Delays) | Constraint| Actual|Levels
|
||||
----------------------------------------------------------------------------
|
||||
| | |
|
||||
FREQUENCY PORT "PHI2" 2.900000 MHz ; | -| -| 2
|
||||
| | |
|
||||
FREQUENCY PORT "nCCAS" 2.900000 MHz ; | -| -| 0
|
||||
| | |
|
||||
FREQUENCY PORT "nCRAS" 2.900000 MHz ; | -| -| 0
|
||||
| | |
|
||||
FREQUENCY PORT "RCLK" 62.500000 MHz ; | -| -| 1
|
||||
| | |
|
||||
----------------------------------------------------------------------------
|
||||
|
||||
|
||||
All preferences were met.
|
||||
|
||||
|
||||
Clock Domains Analysis
|
||||
------------------------
|
||||
|
||||
Found 4 clocks:
|
||||
|
||||
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12
|
||||
No transfer within this clock domain is found
|
||||
|
||||
Data transfers from:
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD
|
||||
Not reported because source and destination domains are unrelated.
|
||||
To report these transfers please refer to preference CLKSKEWDIFF to define
|
||||
external clock skew between clock ports.
|
||||
|
||||
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
|
||||
No transfer within this clock domain is found
|
||||
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47
|
||||
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
|
||||
|
||||
Data transfers from:
|
||||
Clock Domain: nCRAS_c Source: nCRAS.PAD
|
||||
Not reported because source and destination domains are unrelated.
|
||||
To report these transfers please refer to preference CLKSKEWDIFF to define
|
||||
external clock skew between clock ports.
|
||||
|
||||
Clock Domain: PHI2_c Source: PHI2.PAD
|
||||
Not reported because source and destination domains are unrelated.
|
||||
To report these transfers please refer to preference CLKSKEWDIFF to define
|
||||
external clock skew between clock ports.
|
||||
|
||||
Clock Domain: PHI2_c Source: PHI2.PAD Loads: 22
|
||||
Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
|
||||
|
||||
Data transfers from:
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD
|
||||
Not reported because source and destination domains are unrelated.
|
||||
To report these transfers please refer to preference CLKSKEWDIFF to define
|
||||
external clock skew between clock ports.
|
||||
|
||||
|
||||
Timing summary (Hold):
|
||||
---------------
|
||||
|
||||
Timing errors: 0 Score: 0
|
||||
Cumulative negative slack: 0
|
||||
|
||||
Constraints cover 1002 paths, 4 nets, and 687 connections (70.25% coverage)
|
||||
|
||||
|
||||
|
||||
Timing summary (Setup and Hold):
|
||||
---------------
|
||||
|
||||
Timing errors: 0 (setup), 0 (hold)
|
||||
Score: 0 (setup), 0 (hold)
|
||||
Cumulative negative slack: 0 (0+0)
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -12,10 +12,10 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Wed Aug 16 20:58:50 2023
|
||||
Sat Aug 19 21:55:24 2023
|
||||
|
||||
|
||||
Command: bitgen -g RamCfg:Reset -path D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC -w -jedec -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1.ncd LCMXO2_640HC_impl1.prf
|
||||
Command: bitgen -g RamCfg:Reset -path Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC -w -jedec -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1.ncd LCMXO2_640HC_impl1.prf
|
||||
|
||||
Loading design for application Bitgen from file LCMXO2_640HC_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
|
|
@ -91,9 +91,9 @@ UFM Utilization: General Purpose Flash Memory.
|
|||
Available General Purpose Flash Memory: 191 Pages (Page 0 to Page 190).
|
||||
Initialized UFM Pages: 1 Page (Page 190).
|
||||
|
||||
Total CPU Time: 1 secs
|
||||
Total REAL Time: 2 secs
|
||||
Peak Memory Usage: 246 MB
|
||||
Total CPU Time: 3 secs
|
||||
Total REAL Time: 3 secs
|
||||
Peak Memory Usage: 266 MB
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,153 +1,153 @@
|
|||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: R-2021.03L-SP1
|
||||
Install: C:\lscc\diamond\3.12\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEPC
|
||||
|
||||
Implementation : impl1
|
||||
|
||||
# Written on Wed Aug 16 20:59:31 2023
|
||||
|
||||
##### DESIGN INFO #######################################################
|
||||
|
||||
Top View: "RAM2GS"
|
||||
Constraint File(s): "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc"
|
||||
|
||||
|
||||
|
||||
|
||||
##### SUMMARY ############################################################
|
||||
|
||||
Found 0 issues in 0 out of 4 constraints
|
||||
|
||||
|
||||
##### DETAILS ############################################################
|
||||
|
||||
|
||||
|
||||
Clock Relationships
|
||||
*******************
|
||||
|
||||
Starting Ending | rise to rise | fall to fall | rise to fall | fall to rise
|
||||
-----------------------------------------------------------------------------------------------------------------------------------
|
||||
System RCLK | 16.000 | No paths | No paths | No paths
|
||||
RCLK System | 16.000 | No paths | No paths | No paths
|
||||
RCLK RCLK | 16.000 | No paths | No paths | No paths
|
||||
RCLK PHI2 | 2.000 | No paths | 1.000 | No paths
|
||||
RCLK nCRAS | No paths | No paths | 1.000 | No paths
|
||||
PHI2 RCLK | No paths | No paths | No paths | 1.000
|
||||
PHI2 PHI2 | No paths | 350.000 | 175.000 | 175.000
|
||||
nCRAS RCLK | No paths | No paths | No paths | 1.000
|
||||
===================================================================================================================================
|
||||
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
|
||||
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
|
||||
|
||||
|
||||
@W:"d:/onedrive/documents/github/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.
|
||||
@W:"d:/onedrive/documents/github/ram2gs/cpld/ram2gs.sdc":2:0:2:0|Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.
|
||||
@W:"d:/onedrive/documents/github/ram2gs/cpld/ram2gs.sdc":3:0:3:0|Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.
|
||||
@W:"d:/onedrive/documents/github/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.
|
||||
@W:"d:/onedrive/documents/github/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.
|
||||
|
||||
|
||||
Unconstrained Start/End Points
|
||||
******************************
|
||||
|
||||
p:CROW[0]
|
||||
p:CROW[1]
|
||||
p:Din[0]
|
||||
p:Din[1]
|
||||
p:Din[2]
|
||||
p:Din[3]
|
||||
p:Din[4]
|
||||
p:Din[5]
|
||||
p:Din[6]
|
||||
p:Din[7]
|
||||
p:Dout[0]
|
||||
p:Dout[1]
|
||||
p:Dout[2]
|
||||
p:Dout[3]
|
||||
p:Dout[4]
|
||||
p:Dout[5]
|
||||
p:Dout[6]
|
||||
p:Dout[7]
|
||||
p:MAin[0]
|
||||
p:MAin[1]
|
||||
p:MAin[2]
|
||||
p:MAin[3]
|
||||
p:MAin[4]
|
||||
p:MAin[5]
|
||||
p:MAin[6]
|
||||
p:MAin[7]
|
||||
p:MAin[8]
|
||||
p:MAin[9]
|
||||
p:RA[0]
|
||||
p:RA[1]
|
||||
p:RA[2]
|
||||
p:RA[3]
|
||||
p:RA[4]
|
||||
p:RA[5]
|
||||
p:RA[6]
|
||||
p:RA[7]
|
||||
p:RA[8]
|
||||
p:RA[9]
|
||||
p:RA[10]
|
||||
p:RA[11]
|
||||
p:RBA[0]
|
||||
p:RBA[1]
|
||||
p:RCKE
|
||||
p:RDQMH
|
||||
p:RDQML
|
||||
p:RD[0] (bidir end point)
|
||||
p:RD[0] (bidir start point)
|
||||
p:RD[1] (bidir end point)
|
||||
p:RD[1] (bidir start point)
|
||||
p:RD[2] (bidir end point)
|
||||
p:RD[2] (bidir start point)
|
||||
p:RD[3] (bidir end point)
|
||||
p:RD[3] (bidir start point)
|
||||
p:RD[4] (bidir end point)
|
||||
p:RD[4] (bidir start point)
|
||||
p:RD[5] (bidir end point)
|
||||
p:RD[5] (bidir start point)
|
||||
p:RD[6] (bidir end point)
|
||||
p:RD[6] (bidir start point)
|
||||
p:RD[7] (bidir end point)
|
||||
p:RD[7] (bidir start point)
|
||||
p:nFWE
|
||||
p:nRCAS
|
||||
p:nRCS
|
||||
p:nRRAS
|
||||
p:nRWE
|
||||
|
||||
|
||||
Inapplicable constraints
|
||||
************************
|
||||
|
||||
(none)
|
||||
|
||||
|
||||
Applicable constraints with issues
|
||||
**********************************
|
||||
|
||||
(none)
|
||||
|
||||
|
||||
Constraints with matching wildcard expressions
|
||||
**********************************************
|
||||
|
||||
(none)
|
||||
|
||||
|
||||
Library Report
|
||||
**************
|
||||
|
||||
|
||||
# End of Constraint Checker Report
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: R-2021.03L-SP1
|
||||
Install: C:\lscc\diamond\3.12\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
|
||||
# Written on Sat Aug 19 21:54:51 2023
|
||||
|
||||
##### DESIGN INFO #######################################################
|
||||
|
||||
Top View: "RAM2GS"
|
||||
Constraint File(s): "Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc"
|
||||
|
||||
|
||||
|
||||
|
||||
##### SUMMARY ############################################################
|
||||
|
||||
Found 0 issues in 0 out of 4 constraints
|
||||
|
||||
|
||||
##### DETAILS ############################################################
|
||||
|
||||
|
||||
|
||||
Clock Relationships
|
||||
*******************
|
||||
|
||||
Starting Ending | rise to rise | fall to fall | rise to fall | fall to rise
|
||||
-----------------------------------------------------------------------------------------------------------------------------------
|
||||
System RCLK | 16.000 | No paths | No paths | No paths
|
||||
RCLK System | 16.000 | No paths | No paths | No paths
|
||||
RCLK RCLK | 16.000 | No paths | No paths | No paths
|
||||
RCLK PHI2 | 2.000 | No paths | 1.000 | No paths
|
||||
RCLK nCRAS | No paths | No paths | 1.000 | No paths
|
||||
PHI2 RCLK | No paths | No paths | No paths | 1.000
|
||||
PHI2 PHI2 | No paths | 350.000 | 175.000 | 175.000
|
||||
nCRAS RCLK | No paths | No paths | No paths | 1.000
|
||||
===================================================================================================================================
|
||||
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
|
||||
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
|
||||
|
||||
|
||||
@W:"y:/repos/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.
|
||||
@W:"y:/repos/ram2gs/cpld/ram2gs.sdc":3:0:3:0|Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.
|
||||
@W:"y:/repos/ram2gs/cpld/ram2gs.sdc":2:0:2:0|Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.
|
||||
@W:"y:/repos/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.
|
||||
@W:"y:/repos/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.
|
||||
|
||||
|
||||
Unconstrained Start/End Points
|
||||
******************************
|
||||
|
||||
p:CROW[0]
|
||||
p:CROW[1]
|
||||
p:Din[0]
|
||||
p:Din[1]
|
||||
p:Din[2]
|
||||
p:Din[3]
|
||||
p:Din[4]
|
||||
p:Din[5]
|
||||
p:Din[6]
|
||||
p:Din[7]
|
||||
p:Dout[0]
|
||||
p:Dout[1]
|
||||
p:Dout[2]
|
||||
p:Dout[3]
|
||||
p:Dout[4]
|
||||
p:Dout[5]
|
||||
p:Dout[6]
|
||||
p:Dout[7]
|
||||
p:MAin[0]
|
||||
p:MAin[1]
|
||||
p:MAin[2]
|
||||
p:MAin[3]
|
||||
p:MAin[4]
|
||||
p:MAin[5]
|
||||
p:MAin[6]
|
||||
p:MAin[7]
|
||||
p:MAin[8]
|
||||
p:MAin[9]
|
||||
p:RA[0]
|
||||
p:RA[1]
|
||||
p:RA[2]
|
||||
p:RA[3]
|
||||
p:RA[4]
|
||||
p:RA[5]
|
||||
p:RA[6]
|
||||
p:RA[7]
|
||||
p:RA[8]
|
||||
p:RA[9]
|
||||
p:RA[10]
|
||||
p:RA[11]
|
||||
p:RBA[0]
|
||||
p:RBA[1]
|
||||
p:RCKE
|
||||
p:RDQMH
|
||||
p:RDQML
|
||||
p:RD[0] (bidir end point)
|
||||
p:RD[0] (bidir start point)
|
||||
p:RD[1] (bidir end point)
|
||||
p:RD[1] (bidir start point)
|
||||
p:RD[2] (bidir end point)
|
||||
p:RD[2] (bidir start point)
|
||||
p:RD[3] (bidir end point)
|
||||
p:RD[3] (bidir start point)
|
||||
p:RD[4] (bidir end point)
|
||||
p:RD[4] (bidir start point)
|
||||
p:RD[5] (bidir end point)
|
||||
p:RD[5] (bidir start point)
|
||||
p:RD[6] (bidir end point)
|
||||
p:RD[6] (bidir start point)
|
||||
p:RD[7] (bidir end point)
|
||||
p:RD[7] (bidir start point)
|
||||
p:nFWE
|
||||
p:nRCAS
|
||||
p:nRCS
|
||||
p:nRRAS
|
||||
p:nRWE
|
||||
|
||||
|
||||
Inapplicable constraints
|
||||
************************
|
||||
|
||||
(none)
|
||||
|
||||
|
||||
Applicable constraints with issues
|
||||
**********************************
|
||||
|
||||
(none)
|
||||
|
||||
|
||||
Constraints with matching wildcard expressions
|
||||
**********************************************
|
||||
|
||||
(none)
|
||||
|
||||
|
||||
Library Report
|
||||
**************
|
||||
|
||||
|
||||
# End of Constraint Checker Report
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -0,0 +1,9 @@
|
|||
<html>
|
||||
<head>
|
||||
<title>syntmp/LCMXO2_640HC_impl1_fpga_mapper_srr.htm log file</title>
|
||||
</head>
|
||||
<frameset cols="20%, 80%">
|
||||
<frame src="syntmp/LCMXO2_640HC_impl1_fpga_mapper_toc.htm" name="tocFrame" />
|
||||
<frame src="syntmp/LCMXO2_640HC_impl1_fpga_mapper_srr.htm" name="srrFrame"/>
|
||||
</frameset>
|
||||
</html>
|
||||
|
|
@ -0,0 +1,200 @@
|
|||
<HTML>
|
||||
<HEAD><TITLE>I/O Timing Report</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Top"></A><B><U><big>I/O Timing Report</big></U></B>
|
||||
Loading design for application iotiming from file lcmxo2_640hc_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-640HC
|
||||
Package: TQFP100
|
||||
Performance: 5
|
||||
Package Status: Final Version 1.39.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
Loading design for application iotiming from file lcmxo2_640hc_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-640HC
|
||||
Package: TQFP100
|
||||
Performance: 6
|
||||
Package Status: Final Version 1.39.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
Loading design for application iotiming from file lcmxo2_640hc_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-640HC
|
||||
Package: TQFP100
|
||||
Performance: M
|
||||
Package Status: Final Version 1.39.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
// Design: RAM2GS
|
||||
// Package: TQFP100
|
||||
// ncd File: lcmxo2_640hc_impl1.ncd
|
||||
// Version: Diamond (64-bit) 3.12.1.454
|
||||
// Written on Sat Aug 19 21:55:13 2023
|
||||
// M: Minimum Performance Grade
|
||||
// iotiming LCMXO2_640HC_impl1.ncd LCMXO2_640HC_impl1.prf -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
|
||||
|
||||
I/O Timing Report (All units are in ns)
|
||||
|
||||
Worst Case Results across Performance Grades (M, 6, 5, 4):
|
||||
|
||||
// Input Setup and Hold Times
|
||||
|
||||
Port Clock Edge Setup Performance_Grade Hold Performance_Grade
|
||||
----------------------------------------------------------------------
|
||||
CROW[0] nCRAS F 2.553 4 -0.117 M
|
||||
CROW[1] nCRAS F 2.019 4 0.001 M
|
||||
Din[0] PHI2 F 4.715 4 3.636 4
|
||||
Din[0] nCCAS F 0.790 4 0.535 4
|
||||
Din[1] PHI2 F 5.021 4 3.516 4
|
||||
Din[1] nCCAS F 1.086 4 0.264 4
|
||||
Din[2] PHI2 F 3.385 4 3.516 4
|
||||
Din[2] nCCAS F 0.282 4 0.948 4
|
||||
Din[3] PHI2 F 4.644 4 3.516 4
|
||||
Din[3] nCCAS F 1.278 4 0.095 4
|
||||
Din[4] PHI2 F 4.335 4 3.516 4
|
||||
Din[4] nCCAS F 2.446 4 -0.199 M
|
||||
Din[5] PHI2 F 3.662 4 3.516 4
|
||||
Din[5] nCCAS F 0.907 4 0.402 4
|
||||
Din[6] PHI2 F 4.869 4 3.636 4
|
||||
Din[6] nCCAS F 1.378 4 0.023 M
|
||||
Din[7] PHI2 F 4.138 4 3.636 4
|
||||
Din[7] nCCAS F 2.072 4 -0.120 M
|
||||
MAin[0] PHI2 F 5.613 4 0.006 M
|
||||
MAin[0] nCRAS F 0.244 4 1.146 4
|
||||
MAin[1] PHI2 F 3.409 4 0.354 6
|
||||
MAin[1] nCRAS F 0.244 4 1.146 4
|
||||
MAin[2] PHI2 F 5.391 4 0.132 M
|
||||
MAin[2] nCRAS F 0.250 4 1.141 4
|
||||
MAin[3] PHI2 F 4.627 4 0.087 M
|
||||
MAin[3] nCRAS F 0.507 4 0.910 4
|
||||
MAin[4] PHI2 F 5.665 4 -0.133 M
|
||||
MAin[4] nCRAS F 0.675 4 0.777 4
|
||||
MAin[5] PHI2 F 5.569 4 0.129 M
|
||||
MAin[5] nCRAS F 0.050 4 1.238 4
|
||||
MAin[6] PHI2 F 5.717 4 -0.141 M
|
||||
MAin[6] nCRAS F 0.242 4 1.146 4
|
||||
MAin[7] PHI2 F 5.943 4 -0.173 M
|
||||
MAin[7] nCRAS F 0.170 4 1.228 4
|
||||
MAin[8] nCRAS F 0.759 4 0.696 4
|
||||
MAin[9] nCRAS F 0.516 4 0.891 4
|
||||
PHI2 RCLK R -0.312 M 3.167 4
|
||||
nCCAS RCLK R 2.600 4 -0.176 M
|
||||
nCCAS nCRAS F 3.106 4 -0.235 M
|
||||
nCRAS RCLK R 1.803 4 -0.055 M
|
||||
nFWE PHI2 F 4.680 4 0.261 M
|
||||
nFWE nCRAS F 2.234 4 1.143 4
|
||||
|
||||
|
||||
// Clock to Output Delay
|
||||
|
||||
Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
|
||||
------------------------------------------------------------------------
|
||||
LED RCLK R 9.922 4 2.878 M
|
||||
LED nCRAS F 10.555 4 3.057 M
|
||||
RA[0] RCLK R 11.638 4 3.406 M
|
||||
RA[0] nCRAS F 11.771 4 3.430 M
|
||||
RA[10] RCLK R 8.141 4 2.620 M
|
||||
RA[11] PHI2 R 8.610 4 2.756 M
|
||||
RA[1] RCLK R 11.674 4 3.407 M
|
||||
RA[1] nCRAS F 10.635 4 3.155 M
|
||||
RA[2] RCLK R 12.933 4 3.729 M
|
||||
RA[2] nCRAS F 11.858 4 3.449 M
|
||||
RA[3] RCLK R 12.587 4 3.664 M
|
||||
RA[3] nCRAS F 11.255 4 3.298 M
|
||||
RA[4] RCLK R 11.721 4 3.433 M
|
||||
RA[4] nCRAS F 11.153 4 3.297 M
|
||||
RA[5] RCLK R 12.544 4 3.620 M
|
||||
RA[5] nCRAS F 11.480 4 3.360 M
|
||||
RA[6] RCLK R 12.984 4 3.775 M
|
||||
RA[6] nCRAS F 11.528 4 3.407 M
|
||||
RA[7] RCLK R 12.553 4 3.625 M
|
||||
RA[7] nCRAS F 11.610 4 3.368 M
|
||||
RA[8] RCLK R 11.836 4 3.453 M
|
||||
RA[8] nCRAS F 10.797 4 3.201 M
|
||||
RA[9] RCLK R 11.182 4 3.271 M
|
||||
RA[9] nCRAS F 11.135 4 3.279 M
|
||||
RBA[0] nCRAS F 8.439 4 2.703 M
|
||||
RBA[1] nCRAS F 8.439 4 2.703 M
|
||||
RCKE RCLK R 10.083 4 3.081 M
|
||||
RDQMH RCLK R 11.381 4 3.325 M
|
||||
RDQML RCLK R 10.735 4 3.173 M
|
||||
RD[0] nCCAS F 8.223 4 2.594 M
|
||||
RD[1] nCCAS F 8.223 4 2.594 M
|
||||
RD[2] nCCAS F 8.223 4 2.594 M
|
||||
RD[3] nCCAS F 8.223 4 2.594 M
|
||||
RD[4] nCCAS F 8.223 4 2.594 M
|
||||
RD[5] nCCAS F 8.223 4 2.594 M
|
||||
RD[6] nCCAS F 8.223 4 2.594 M
|
||||
RD[7] nCCAS F 8.223 4 2.594 M
|
||||
nRCAS RCLK R 8.141 4 2.620 M
|
||||
nRCS RCLK R 8.141 4 2.620 M
|
||||
nRRAS RCLK R 8.141 4 2.620 M
|
||||
nRWE RCLK R 8.121 4 2.627 M
|
||||
WARNING: you must also run trce with hold speed: 4
|
||||
WARNING: you must also run trce with hold speed: 6
|
||||
WARNING: you must also run trce with setup speed: M
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
|
|
@ -1,24 +1,24 @@
|
|||
[ActiveSupport MAP]
|
||||
Device = LCMXO2-640HC;
|
||||
Package = TQFP100;
|
||||
Performance = 4;
|
||||
LUTS_avail = 640;
|
||||
LUTS_used = 230;
|
||||
FF_avail = 719;
|
||||
FF_used = 109;
|
||||
INPUT_LVCMOS33 = 25;
|
||||
OUTPUT_LVCMOS33 = 30;
|
||||
BIDI_LVCMOS33 = 8;
|
||||
IO_avail = 79;
|
||||
IO_used = 63;
|
||||
EBR_avail = 2;
|
||||
EBR_used = 0;
|
||||
;
|
||||
; start of EFB statistics
|
||||
I2C = 0;
|
||||
SPI = 0;
|
||||
TimerCounter = 0;
|
||||
UFM = 1;
|
||||
PLL = 0;
|
||||
; end of EFB statistics
|
||||
;
|
||||
[ActiveSupport MAP]
|
||||
Device = LCMXO2-640HC;
|
||||
Package = TQFP100;
|
||||
Performance = 4;
|
||||
LUTS_avail = 640;
|
||||
LUTS_used = 222;
|
||||
FF_avail = 719;
|
||||
FF_used = 111;
|
||||
INPUT_LVCMOS33 = 25;
|
||||
OUTPUT_LVCMOS33 = 30;
|
||||
BIDI_LVCMOS33 = 8;
|
||||
IO_avail = 79;
|
||||
IO_used = 63;
|
||||
EBR_avail = 2;
|
||||
EBR_used = 0;
|
||||
;
|
||||
; start of EFB statistics
|
||||
I2C = 0;
|
||||
SPI = 0;
|
||||
TimerCounter = 0;
|
||||
UFM = 1;
|
||||
PLL = 0;
|
||||
; end of EFB statistics
|
||||
;
|
||||
|
|
|
|||
|
|
@ -1,145 +1,144 @@
|
|||
[ START MERGED ]
|
||||
RASr2_i RASr2
|
||||
XOR8MEG.CN PHI2_c
|
||||
nCRAS_c_i nCRAS_c
|
||||
InitReady_i InitReady
|
||||
[ END MERGED ]
|
||||
[ START CLIPPED ]
|
||||
GND
|
||||
ufmefb/VCC
|
||||
ufmefb/GND
|
||||
FS_s_0_S1[17]
|
||||
FS_s_0_COUT[17]
|
||||
ufmefb/CFGSTDBY
|
||||
ufmefb/CFGWAKE
|
||||
ufmefb/wbc_ufm_irq
|
||||
ufmefb/TCOC
|
||||
ufmefb/TCINT
|
||||
ufmefb/SPIIRQO
|
||||
ufmefb/SPICSNEN
|
||||
ufmefb/SPIMCSN7
|
||||
ufmefb/SPIMCSN6
|
||||
ufmefb/SPIMCSN5
|
||||
ufmefb/SPIMCSN4
|
||||
ufmefb/SPIMCSN3
|
||||
ufmefb/SPIMCSN2
|
||||
ufmefb/SPIMCSN1
|
||||
ufmefb/SPIMCSN0
|
||||
ufmefb/SPIMOSIEN
|
||||
ufmefb/SPIMOSIO
|
||||
ufmefb/SPIMISOEN
|
||||
ufmefb/SPIMISOO
|
||||
ufmefb/SPISCKEN
|
||||
ufmefb/SPISCKO
|
||||
ufmefb/I2C2IRQO
|
||||
ufmefb/I2C1IRQO
|
||||
ufmefb/I2C2SDAOEN
|
||||
ufmefb/I2C2SDAO
|
||||
ufmefb/I2C2SCLOEN
|
||||
ufmefb/I2C2SCLO
|
||||
ufmefb/I2C1SDAOEN
|
||||
ufmefb/I2C1SDAO
|
||||
ufmefb/I2C1SCLOEN
|
||||
ufmefb/I2C1SCLO
|
||||
ufmefb/PLLDATO0
|
||||
ufmefb/PLLDATO1
|
||||
ufmefb/PLLDATO2
|
||||
ufmefb/PLLDATO3
|
||||
ufmefb/PLLDATO4
|
||||
ufmefb/PLLDATO5
|
||||
ufmefb/PLLDATO6
|
||||
ufmefb/PLLDATO7
|
||||
ufmefb/PLLADRO0
|
||||
ufmefb/PLLADRO1
|
||||
ufmefb/PLLADRO2
|
||||
ufmefb/PLLADRO3
|
||||
ufmefb/PLLADRO4
|
||||
ufmefb/PLLWEO
|
||||
ufmefb/PLL1STBO
|
||||
ufmefb/PLL0STBO
|
||||
ufmefb/PLLRSTO
|
||||
ufmefb/PLLCLKO
|
||||
ufmefb/wb_ack_o
|
||||
ufmefb/wb_dat_o_1[2]
|
||||
ufmefb/wb_dat_o_1[3]
|
||||
ufmefb/wb_dat_o_1[4]
|
||||
ufmefb/wb_dat_o_1[5]
|
||||
ufmefb/wb_dat_o_1[6]
|
||||
ufmefb/wb_dat_o_1[7]
|
||||
FS_cry_0_S0[0]
|
||||
N_1
|
||||
[ END CLIPPED ]
|
||||
[ START DESIGN PREFS ]
|
||||
SCHEMATIC START ;
|
||||
# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Wed Aug 16 20:59:37 2023
|
||||
|
||||
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
|
||||
LOCATE COMP "RD[0]" SITE "36" ;
|
||||
LOCATE COMP "Dout[0]" SITE "76" ;
|
||||
LOCATE COMP "PHI2" SITE "8" ;
|
||||
LOCATE COMP "RDQML" SITE "48" ;
|
||||
LOCATE COMP "RDQMH" SITE "51" ;
|
||||
LOCATE COMP "nRCAS" SITE "52" ;
|
||||
LOCATE COMP "nRRAS" SITE "54" ;
|
||||
LOCATE COMP "nRWE" SITE "49" ;
|
||||
LOCATE COMP "RCKE" SITE "53" ;
|
||||
LOCATE COMP "RCLK" SITE "62" ;
|
||||
LOCATE COMP "nRCS" SITE "57" ;
|
||||
LOCATE COMP "RD[7]" SITE "43" ;
|
||||
LOCATE COMP "RD[6]" SITE "42" ;
|
||||
LOCATE COMP "RD[5]" SITE "41" ;
|
||||
LOCATE COMP "RD[4]" SITE "40" ;
|
||||
LOCATE COMP "RD[3]" SITE "39" ;
|
||||
LOCATE COMP "RD[2]" SITE "38" ;
|
||||
LOCATE COMP "RD[1]" SITE "37" ;
|
||||
LOCATE COMP "RA[11]" SITE "59" ;
|
||||
LOCATE COMP "RA[10]" SITE "64" ;
|
||||
LOCATE COMP "RA[9]" SITE "63" ;
|
||||
LOCATE COMP "RA[8]" SITE "65" ;
|
||||
LOCATE COMP "RA[7]" SITE "75" ;
|
||||
LOCATE COMP "RA[6]" SITE "68" ;
|
||||
LOCATE COMP "RA[5]" SITE "70" ;
|
||||
LOCATE COMP "RA[4]" SITE "74" ;
|
||||
LOCATE COMP "RA[3]" SITE "71" ;
|
||||
LOCATE COMP "RA[2]" SITE "69" ;
|
||||
LOCATE COMP "RA[1]" SITE "67" ;
|
||||
LOCATE COMP "RA[0]" SITE "66" ;
|
||||
LOCATE COMP "RBA[1]" SITE "60" ;
|
||||
LOCATE COMP "RBA[0]" SITE "58" ;
|
||||
LOCATE COMP "LED" SITE "34" ;
|
||||
LOCATE COMP "nFWE" SITE "15" ;
|
||||
LOCATE COMP "nCRAS" SITE "17" ;
|
||||
LOCATE COMP "nCCAS" SITE "9" ;
|
||||
LOCATE COMP "Dout[7]" SITE "82" ;
|
||||
LOCATE COMP "Dout[6]" SITE "78" ;
|
||||
LOCATE COMP "Dout[5]" SITE "84" ;
|
||||
LOCATE COMP "Dout[4]" SITE "83" ;
|
||||
LOCATE COMP "Dout[3]" SITE "85" ;
|
||||
LOCATE COMP "Dout[2]" SITE "87" ;
|
||||
LOCATE COMP "Dout[1]" SITE "86" ;
|
||||
LOCATE COMP "Din[7]" SITE "1" ;
|
||||
LOCATE COMP "Din[6]" SITE "2" ;
|
||||
LOCATE COMP "Din[5]" SITE "98" ;
|
||||
LOCATE COMP "Din[4]" SITE "99" ;
|
||||
LOCATE COMP "Din[3]" SITE "97" ;
|
||||
LOCATE COMP "Din[2]" SITE "88" ;
|
||||
LOCATE COMP "Din[1]" SITE "96" ;
|
||||
LOCATE COMP "Din[0]" SITE "3" ;
|
||||
LOCATE COMP "CROW[1]" SITE "16" ;
|
||||
LOCATE COMP "CROW[0]" SITE "10" ;
|
||||
LOCATE COMP "MAin[9]" SITE "32" ;
|
||||
LOCATE COMP "MAin[8]" SITE "25" ;
|
||||
LOCATE COMP "MAin[7]" SITE "18" ;
|
||||
LOCATE COMP "MAin[6]" SITE "24" ;
|
||||
LOCATE COMP "MAin[5]" SITE "19" ;
|
||||
LOCATE COMP "MAin[4]" SITE "20" ;
|
||||
LOCATE COMP "MAin[3]" SITE "21" ;
|
||||
LOCATE COMP "MAin[2]" SITE "13" ;
|
||||
LOCATE COMP "MAin[1]" SITE "12" ;
|
||||
LOCATE COMP "MAin[0]" SITE "14" ;
|
||||
FREQUENCY PORT "PHI2" 2.900000 MHz ;
|
||||
FREQUENCY PORT "nCCAS" 2.900000 MHz ;
|
||||
FREQUENCY PORT "nCRAS" 2.900000 MHz ;
|
||||
FREQUENCY PORT "RCLK" 62.500000 MHz ;
|
||||
SCHEMATIC END ;
|
||||
[ END DESIGN PREFS ]
|
||||
[ START MERGED ]
|
||||
RASr2_i RASr2
|
||||
XOR8MEG.CN PHI2_c
|
||||
XOR8MEG_3_u_0_am XOR8MEG
|
||||
nCRAS_c_i nCRAS_c
|
||||
[ END MERGED ]
|
||||
[ START CLIPPED ]
|
||||
GND
|
||||
ufmefb/VCC
|
||||
ufmefb/GND
|
||||
FS_s_0_S1[17]
|
||||
FS_s_0_COUT[17]
|
||||
ufmefb/CFGSTDBY
|
||||
ufmefb/CFGWAKE
|
||||
ufmefb/wbc_ufm_irq
|
||||
ufmefb/TCOC
|
||||
ufmefb/TCINT
|
||||
ufmefb/SPIIRQO
|
||||
ufmefb/SPICSNEN
|
||||
ufmefb/SPIMCSN7
|
||||
ufmefb/SPIMCSN6
|
||||
ufmefb/SPIMCSN5
|
||||
ufmefb/SPIMCSN4
|
||||
ufmefb/SPIMCSN3
|
||||
ufmefb/SPIMCSN2
|
||||
ufmefb/SPIMCSN1
|
||||
ufmefb/SPIMCSN0
|
||||
ufmefb/SPIMOSIEN
|
||||
ufmefb/SPIMOSIO
|
||||
ufmefb/SPIMISOEN
|
||||
ufmefb/SPIMISOO
|
||||
ufmefb/SPISCKEN
|
||||
ufmefb/SPISCKO
|
||||
ufmefb/I2C2IRQO
|
||||
ufmefb/I2C1IRQO
|
||||
ufmefb/I2C2SDAOEN
|
||||
ufmefb/I2C2SDAO
|
||||
ufmefb/I2C2SCLOEN
|
||||
ufmefb/I2C2SCLO
|
||||
ufmefb/I2C1SDAOEN
|
||||
ufmefb/I2C1SDAO
|
||||
ufmefb/I2C1SCLOEN
|
||||
ufmefb/I2C1SCLO
|
||||
ufmefb/PLLDATO0
|
||||
ufmefb/PLLDATO1
|
||||
ufmefb/PLLDATO2
|
||||
ufmefb/PLLDATO3
|
||||
ufmefb/PLLDATO4
|
||||
ufmefb/PLLDATO5
|
||||
ufmefb/PLLDATO6
|
||||
ufmefb/PLLDATO7
|
||||
ufmefb/PLLADRO0
|
||||
ufmefb/PLLADRO1
|
||||
ufmefb/PLLADRO2
|
||||
ufmefb/PLLADRO3
|
||||
ufmefb/PLLADRO4
|
||||
ufmefb/PLLWEO
|
||||
ufmefb/PLL1STBO
|
||||
ufmefb/PLL0STBO
|
||||
ufmefb/PLLRSTO
|
||||
ufmefb/PLLCLKO
|
||||
ufmefb/wb_dat_o_1[2]
|
||||
ufmefb/wb_dat_o_1[3]
|
||||
ufmefb/wb_dat_o_1[4]
|
||||
ufmefb/wb_dat_o_1[5]
|
||||
ufmefb/wb_dat_o_1[6]
|
||||
ufmefb/wb_dat_o_1[7]
|
||||
FS_cry_0_S0[0]
|
||||
N_1
|
||||
[ END CLIPPED ]
|
||||
[ START DESIGN PREFS ]
|
||||
SCHEMATIC START ;
|
||||
# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Sat Aug 19 21:54:57 2023
|
||||
|
||||
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
|
||||
LOCATE COMP "RD[0]" SITE "36" ;
|
||||
LOCATE COMP "Dout[0]" SITE "76" ;
|
||||
LOCATE COMP "PHI2" SITE "8" ;
|
||||
LOCATE COMP "RDQML" SITE "48" ;
|
||||
LOCATE COMP "RDQMH" SITE "51" ;
|
||||
LOCATE COMP "nRCAS" SITE "52" ;
|
||||
LOCATE COMP "nRRAS" SITE "54" ;
|
||||
LOCATE COMP "nRWE" SITE "49" ;
|
||||
LOCATE COMP "RCKE" SITE "53" ;
|
||||
LOCATE COMP "RCLK" SITE "62" ;
|
||||
LOCATE COMP "nRCS" SITE "57" ;
|
||||
LOCATE COMP "RD[7]" SITE "43" ;
|
||||
LOCATE COMP "RD[6]" SITE "42" ;
|
||||
LOCATE COMP "RD[5]" SITE "41" ;
|
||||
LOCATE COMP "RD[4]" SITE "40" ;
|
||||
LOCATE COMP "RD[3]" SITE "39" ;
|
||||
LOCATE COMP "RD[2]" SITE "38" ;
|
||||
LOCATE COMP "RD[1]" SITE "37" ;
|
||||
LOCATE COMP "RA[11]" SITE "59" ;
|
||||
LOCATE COMP "RA[10]" SITE "64" ;
|
||||
LOCATE COMP "RA[9]" SITE "63" ;
|
||||
LOCATE COMP "RA[8]" SITE "65" ;
|
||||
LOCATE COMP "RA[7]" SITE "75" ;
|
||||
LOCATE COMP "RA[6]" SITE "68" ;
|
||||
LOCATE COMP "RA[5]" SITE "70" ;
|
||||
LOCATE COMP "RA[4]" SITE "74" ;
|
||||
LOCATE COMP "RA[3]" SITE "71" ;
|
||||
LOCATE COMP "RA[2]" SITE "69" ;
|
||||
LOCATE COMP "RA[1]" SITE "67" ;
|
||||
LOCATE COMP "RA[0]" SITE "66" ;
|
||||
LOCATE COMP "RBA[1]" SITE "60" ;
|
||||
LOCATE COMP "RBA[0]" SITE "58" ;
|
||||
LOCATE COMP "LED" SITE "34" ;
|
||||
LOCATE COMP "nFWE" SITE "15" ;
|
||||
LOCATE COMP "nCRAS" SITE "17" ;
|
||||
LOCATE COMP "nCCAS" SITE "9" ;
|
||||
LOCATE COMP "Dout[7]" SITE "82" ;
|
||||
LOCATE COMP "Dout[6]" SITE "78" ;
|
||||
LOCATE COMP "Dout[5]" SITE "84" ;
|
||||
LOCATE COMP "Dout[4]" SITE "83" ;
|
||||
LOCATE COMP "Dout[3]" SITE "85" ;
|
||||
LOCATE COMP "Dout[2]" SITE "87" ;
|
||||
LOCATE COMP "Dout[1]" SITE "86" ;
|
||||
LOCATE COMP "Din[7]" SITE "1" ;
|
||||
LOCATE COMP "Din[6]" SITE "2" ;
|
||||
LOCATE COMP "Din[5]" SITE "98" ;
|
||||
LOCATE COMP "Din[4]" SITE "99" ;
|
||||
LOCATE COMP "Din[3]" SITE "97" ;
|
||||
LOCATE COMP "Din[2]" SITE "88" ;
|
||||
LOCATE COMP "Din[1]" SITE "96" ;
|
||||
LOCATE COMP "Din[0]" SITE "3" ;
|
||||
LOCATE COMP "CROW[1]" SITE "16" ;
|
||||
LOCATE COMP "CROW[0]" SITE "10" ;
|
||||
LOCATE COMP "MAin[9]" SITE "32" ;
|
||||
LOCATE COMP "MAin[8]" SITE "25" ;
|
||||
LOCATE COMP "MAin[7]" SITE "18" ;
|
||||
LOCATE COMP "MAin[6]" SITE "24" ;
|
||||
LOCATE COMP "MAin[5]" SITE "19" ;
|
||||
LOCATE COMP "MAin[4]" SITE "20" ;
|
||||
LOCATE COMP "MAin[3]" SITE "21" ;
|
||||
LOCATE COMP "MAin[2]" SITE "13" ;
|
||||
LOCATE COMP "MAin[1]" SITE "12" ;
|
||||
LOCATE COMP "MAin[0]" SITE "14" ;
|
||||
FREQUENCY PORT "PHI2" 2.900000 MHz ;
|
||||
FREQUENCY PORT "nCCAS" 2.900000 MHz ;
|
||||
FREQUENCY PORT "nCRAS" 2.900000 MHz ;
|
||||
FREQUENCY PORT "RCLK" 62.500000 MHz ;
|
||||
SCHEMATIC END ;
|
||||
[ END DESIGN PREFS ]
|
||||
|
|
|
|||
|
|
@ -1,20 +1,22 @@
|
|||
---------------------------------------------------
|
||||
Report for cell RAM2GS
|
||||
Instance path: RAM2GS
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
SLIC 117.00 100.0
|
||||
IOLGC 25.00 100.0
|
||||
LUT4 210.00 100.0
|
||||
IOREG 25 100.0
|
||||
IOBUF 63 100.0
|
||||
PFUREG 84 100.0
|
||||
RIPPLE 10 100.0
|
||||
SUB MODULES
|
||||
cell count SLC Usage(%)
|
||||
REFB 1 0.0
|
||||
---------------------------------------------------
|
||||
Report for cell REFB
|
||||
Instance path: RAM2GS/ufmefb
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
---------------------------------------------------
|
||||
Report for cell RAM2GS
|
||||
Instance path: RAM2GS
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
SLIC 113.00 100.0
|
||||
IOLGC 25.00 100.0
|
||||
LUT4 202.00 100.0
|
||||
IOREG 25 100.0
|
||||
IOBUF 63 100.0
|
||||
PFUREG 86 100.0
|
||||
RIPPLE 10 100.0
|
||||
SUB MODULES
|
||||
cell count SLC Usage(%)
|
||||
REFB 1 0.4
|
||||
---------------------------------------------------
|
||||
Report for cell REFB
|
||||
Instance path: RAM2GS/ufmefb
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
SLIC 0.50 0.4
|
||||
LUT4 1.00 0.5
|
||||
|
|
|
|||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -15,27 +15,27 @@
|
|||
|
||||
Command line: map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial
|
||||
LCMXO2_640HC_impl1.ngd -o LCMXO2_640HC_impl1_map.ncd -pr
|
||||
LCMXO2_640HC_impl1.prf -mp LCMXO2_640HC_impl1.mrp -lpf D:/OneDrive/Document
|
||||
s/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify.lpf
|
||||
-lpf D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.lpf -c 0 -gui
|
||||
-msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
|
||||
LCMXO2_640HC_impl1.prf -mp LCMXO2_640HC_impl1.mrp -lpf
|
||||
Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1_synplify.lpf
|
||||
-lpf Y:/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.lpf -c 0 -gui -msgset
|
||||
Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
|
||||
Target Vendor: LATTICE
|
||||
Target Device: LCMXO2-640HCTQFP100
|
||||
Target Performance: 4
|
||||
Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454
|
||||
Mapped on: 08/16/23 20:59:36
|
||||
Mapped on: 08/19/23 21:54:57
|
||||
|
||||
|
||||
<A name="mrp_ds"></A><B><U><big>Design Summary</big></U></B>
|
||||
Number of registers: 109 out of 877 (12%)
|
||||
PFU registers: 84 out of 640 (13%)
|
||||
Number of registers: 111 out of 877 (13%)
|
||||
PFU registers: 86 out of 640 (13%)
|
||||
PIO registers: 25 out of 237 (11%)
|
||||
Number of SLICEs: 117 out of 320 (37%)
|
||||
SLICEs as Logic/ROM: 117 out of 320 (37%)
|
||||
Number of SLICEs: 113 out of 320 (35%)
|
||||
SLICEs as Logic/ROM: 113 out of 320 (35%)
|
||||
SLICEs as RAM: 0 out of 240 (0%)
|
||||
SLICEs as Carry: 10 out of 320 (3%)
|
||||
Number of LUT4s: 230 out of 640 (36%)
|
||||
Number used as logic LUTs: 210
|
||||
Number of LUT4s: 222 out of 640 (35%)
|
||||
Number used as logic LUTs: 202
|
||||
Number used as distributed RAM: 0
|
||||
Number used as ripple logic: 20
|
||||
Number used as shift registers: 0
|
||||
|
|
@ -58,39 +58,37 @@ Mapped on: 08/16/23 20:59:36
|
|||
distributed RAMs) + 2*(Number of ripple logic)
|
||||
2. Number of logic LUT4s does not include count of distributed RAM and
|
||||
ripple logic.
|
||||
Number of clocks: 5
|
||||
Net PHI2_c: 19 loads, 9 rising, 10 falling (Driver: PIO PHI2 )
|
||||
Net RCLK_c: 46 loads, 46 rising, 0 falling (Driver: PIO RCLK )
|
||||
Net wb_clk: 1 loads, 1 rising, 0 falling (Driver: wb_clk )
|
||||
Number of clocks: 4
|
||||
Net PHI2_c: 21 loads, 9 rising, 12 falling (Driver: PIO PHI2 )
|
||||
Net RCLK_c: 47 loads, 47 rising, 0 falling (Driver: PIO RCLK )
|
||||
Net nCRAS_c: 10 loads, 0 rising, 10 falling (Driver: PIO nCRAS )
|
||||
Net nCCAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCCAS )
|
||||
Number of Clock Enables: 7
|
||||
Net N_245_i: 1 loads, 1 LSLICEs
|
||||
Net CMDUFMWrite_1_sqmuxa: 2 loads, 2 LSLICEs
|
||||
Number of Clock Enables: 6
|
||||
Net un1_wb_cyc_stb_2_sqmuxa_i_0_N_4_i: 1 loads, 1 LSLICEs
|
||||
Net XOR8MEG18: 6 loads, 6 LSLICEs
|
||||
Net CmdUFMData_1_sqmuxa: 1 loads, 1 LSLICEs
|
||||
|
||||
Net InitReady: 1 loads, 1 LSLICEs
|
||||
Net un1_wb_clk32_i: 10 loads, 10 LSLICEs
|
||||
Net N_18: 2 loads, 2 LSLICEs
|
||||
Net XOR8MEG18: 3 loads, 3 LSLICEs
|
||||
Net N_193_i: 2 loads, 2 LSLICEs
|
||||
Net un1_wb_rst14_i: 9 loads, 9 LSLICEs
|
||||
Net un1_FS_38_i: 2 loads, 2 LSLICEs
|
||||
Net N_253_i: 2 loads, 2 LSLICEs
|
||||
Number of LSRs: 5
|
||||
Net RA10s_i: 1 loads, 0 LSLICEs
|
||||
Net wb_clk23: 3 loads, 3 LSLICEs
|
||||
Net wb_rst10: 3 loads, 3 LSLICEs
|
||||
Net wb_rst: 1 loads, 0 LSLICEs
|
||||
Net nRRAS_0_sqmuxa: 1 loads, 1 LSLICEs
|
||||
Net RASr2: 2 loads, 2 LSLICEs
|
||||
Number of nets driven by tri-state buffers: 0
|
||||
Top 10 highest fanout non-clock nets:
|
||||
Net InitReady: 42 loads
|
||||
Net FS[12]: 27 loads
|
||||
Net FS[10]: 25 loads
|
||||
Net FS[11]: 22 loads
|
||||
Net FS[7]: 17 loads
|
||||
Net FS[6]: 16 loads
|
||||
Net Ready: 15 loads
|
||||
Net InitReady: 33 loads
|
||||
Net FS[13]: 22 loads
|
||||
Net FS[12]: 21 loads
|
||||
Net FS[14]: 20 loads
|
||||
Net wb_rst11: 18 loads
|
||||
Net FS[10]: 16 loads
|
||||
Net Ready: 16 loads
|
||||
Net FS[11]: 15 loads
|
||||
Net FS[9]: 15 loads
|
||||
Net Ready_fast: 14 loads
|
||||
Net nRowColSel: 12 loads
|
||||
Net S[1]: 12 loads
|
||||
|
||||
|
||||
|
||||
|
|
@ -127,9 +125,9 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
|||
+---------------------+-----------+-----------+------------+
|
||||
| RDQML | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
| RDQMH | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
| nRCAS | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRRAS | OUTPUT | LVCMOS33 | OUT |
|
||||
|
|
@ -184,9 +182,9 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
|||
+---------------------+-----------+-----------+------------+
|
||||
| RBA[0] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
| LED | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
| nFWE | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nCRAS | INPUT | LVCMOS33 | |
|
||||
|
|
@ -241,9 +239,9 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
|||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[3] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
| MAin[2] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
| MAin[1] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[0] | INPUT | LVCMOS33 | |
|
||||
|
|
@ -256,8 +254,8 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
|||
Block GSR_INST undriven or does not drive anything - clipped.
|
||||
Signal nCRAS_c_i was merged into signal nCRAS_c
|
||||
Signal RASr2_i was merged into signal RASr2
|
||||
Signal InitReady_i was merged into signal InitReady
|
||||
Signal XOR8MEG.CN was merged into signal PHI2_c
|
||||
Signal XOR8MEG_3_u_0_am was merged into signal XOR8MEG
|
||||
Signal GND undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/VCC undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/GND undriven or does not drive anything - clipped.
|
||||
|
|
@ -299,9 +297,9 @@ Signal ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
|
|||
Signal ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
|
||||
|
||||
Signal ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
|
||||
|
||||
Signal ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
|
||||
|
|
@ -313,7 +311,6 @@ Signal ufmefb/PLL1STBO undriven or does not drive anything - clipped.
|
|||
Signal ufmefb/PLL0STBO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLRSTO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLCLKO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wb_ack_o undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wb_dat_o_1[2] undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wb_dat_o_1[3] undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wb_dat_o_1[4] undriven or does not drive anything - clipped.
|
||||
|
|
@ -324,8 +321,8 @@ Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped.
|
|||
Signal N_1 undriven or does not drive anything - clipped.
|
||||
Block nCRAS_pad_RNIBPVB was optimized away.
|
||||
Block RASr2_RNIAFR1 was optimized away.
|
||||
Block wb_rst_RNO_0 was optimized away.
|
||||
Block XOR8MEG.CN was optimized away.
|
||||
Block XOR8MEG_3_u_0_am was optimized away.
|
||||
Block GND was optimized away.
|
||||
Block ufmefb/VCC was optimized away.
|
||||
Block ufmefb/GND was optimized away.
|
||||
|
|
@ -336,8 +333,8 @@ Block ufmefb/GND was optimized away.
|
|||
|
||||
<A name="mrp_efb"></A><B><U><big>Embedded Functional Block Connection Summary</big></U></B>
|
||||
|
||||
Desired WISHBONE clock frequency: 62.5 MHz
|
||||
Clock source: wb_clk
|
||||
Desired WISHBONE clock frequency: 66.7 MHz
|
||||
Clock source: RCLK_c
|
||||
Reset source: wb_rst
|
||||
Functions mode:
|
||||
I2C #1 (Primary) Function: DISABLED
|
||||
|
|
@ -357,10 +354,10 @@ Block ufmefb/GND was optimized away.
|
|||
Timer/Counter Function Summary:
|
||||
------------------------------
|
||||
None
|
||||
|
||||
UFM Function Summary:
|
||||
--------------------
|
||||
UFM Utilization: General Purpose Flash Memory
|
||||
|
||||
Initialized UFM Pages: 1 Pages (1*128 Bits)
|
||||
Available General
|
||||
Purpose Flash Memory: 191 Pages (191*128 Bits)
|
||||
|
|
@ -387,7 +384,7 @@ Instance Name: ufmefb/EFBInst_0
|
|||
|
||||
Total CPU Time: 0 secs
|
||||
Total REAL Time: 0 secs
|
||||
Peak Memory Usage: 37 MB
|
||||
Peak Memory Usage: 57 MB
|
||||
|
||||
|
||||
|
||||
|
|
@ -417,6 +414,9 @@ Instance Name: ufmefb/EFBInst_0
|
|||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
<html>
|
||||
<head>
|
||||
<title>syntmp/LCMXO2_640HC_impl1_multi_srs_gen_srr.htm log file</title>
|
||||
</head>
|
||||
<frameset cols="20%, 80%">
|
||||
<frame src="syntmp/LCMXO2_640HC_impl1_multi_srs_gen_toc.htm" name="tocFrame" />
|
||||
<frame src="syntmp/LCMXO2_640HC_impl1_multi_srs_gen_srr.htm" name="srrFrame"/>
|
||||
</frameset>
|
||||
</html>
|
||||
<html>
|
||||
<head>
|
||||
<title>syntmp/LCMXO2_640HC_impl1_multi_srs_gen_srr.htm log file</title>
|
||||
</head>
|
||||
<frameset cols="20%, 80%">
|
||||
<frame src="syntmp/LCMXO2_640HC_impl1_multi_srs_gen_toc.htm" name="tocFrame" />
|
||||
<frame src="syntmp/LCMXO2_640HC_impl1_multi_srs_gen_srr.htm" name="srrFrame"/>
|
||||
</frameset>
|
||||
</html>
|
||||
|
|
|
|||
|
|
@ -1 +1 @@
|
|||
[ActiveSupport NGD]
|
||||
[ActiveSupport NGD]
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@ Performance Grade: 4
|
|||
PACKAGE: TQFP100
|
||||
Package Status: Final Version 1.39
|
||||
|
||||
Wed Aug 16 20:59:41 2023
|
||||
Sat Aug 19 21:55:06 2023
|
||||
|
||||
Pinout by Port Name:
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
|
|
@ -278,7 +278,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Wed Aug 16 20:59:42 2023
|
||||
Sat Aug 19 21:55:09 2023
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -12,11 +12,11 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Wed Aug 16 20:59:37 2023
|
||||
Sat Aug 19 21:55:01 2023
|
||||
|
||||
C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f LCMXO2_640HC_impl1.p2t
|
||||
LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir LCMXO2_640HC_impl1.prf -gui
|
||||
-msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
|
||||
-msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
|
||||
|
||||
|
||||
Preference file: LCMXO2_640HC_impl1.prf.
|
||||
|
|
@ -25,22 +25,22 @@ Preference file: LCMXO2_640HC_impl1.prf.
|
|||
Level/ Number Worst Timing Worst Timing Run NCD
|
||||
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
|
||||
---------- -------- ----- ------ ----------- ----------- ---- ------
|
||||
5_1 * 0 4.922 0 0.088 0 07 Completed
|
||||
5_1 * 0 6.966 0 0.304 0 10 Completed
|
||||
* : Design saved.
|
||||
|
||||
Total (real) run time for 1-seed: 7 secs
|
||||
Total (real) run time for 1-seed: 10 secs
|
||||
|
||||
par done!
|
||||
|
||||
Note: user must run 'Trace' for timing closure signoff.
|
||||
|
||||
Lattice Place and Route Report for Design "LCMXO2_640HC_impl1_map.ncd"
|
||||
Wed Aug 16 20:59:37 2023
|
||||
Sat Aug 19 21:55:01 2023
|
||||
|
||||
|
||||
<A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
|
||||
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
|
||||
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir/5_1.ncd LCMXO2_640HC_impl1.prf
|
||||
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir/5_1.ncd LCMXO2_640HC_impl1.prf
|
||||
Preference file: LCMXO2_640HC_impl1.prf.
|
||||
Placement level-cost: 5-1.
|
||||
Routing Iterations: 6
|
||||
|
|
@ -66,45 +66,44 @@ Ignore Preference Error(s): True
|
|||
63+4(JTAG)/79 85% bonded
|
||||
IOLOGIC 25/80 31% used
|
||||
|
||||
SLICE 117/320 36% used
|
||||
SLICE 113/320 35% used
|
||||
|
||||
EFB 1/1 100% used
|
||||
|
||||
|
||||
Number of Signals: 380
|
||||
Number of Connections: 1008
|
||||
Number of Signals: 374
|
||||
Number of Connections: 978
|
||||
|
||||
Pin Constraint Summary:
|
||||
63 out of 63 pins locked (100% locked).
|
||||
|
||||
The following 3 signals are selected to use the primary clock routing resources:
|
||||
RCLK_c (driver: RCLK, clk load #: 46)
|
||||
PHI2_c (driver: PHI2, clk load #: 19)
|
||||
RCLK_c (driver: RCLK, clk load #: 47)
|
||||
PHI2_c (driver: PHI2, clk load #: 21)
|
||||
nCRAS_c (driver: nCRAS, clk load #: 10)
|
||||
|
||||
WARNING - par: Signal "RCLK_c" is selected to use Primary clock resources. However, its driver comp "RCLK" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
WARNING - par: Signal "nCRAS_c" is selected to use Primary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
|
||||
The following 2 signals are selected to use the secondary clock routing resources:
|
||||
The following 1 signal is selected to use the secondary clock routing resources:
|
||||
nCCAS_c (driver: nCCAS, clk load #: 8, sr load #: 0, ce load #: 0)
|
||||
un1_wb_clk32_i (driver: SLICE_103, clk load #: 0, sr load #: 0, ce load #: 10)
|
||||
|
||||
WARNING - par: Signal "nCCAS_c" is selected to use Secondary clock resources. However, its driver comp "nCCAS" is located at "9", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
No signal is selected as Global Set/Reset.
|
||||
Starting Placer Phase 0.
|
||||
..............
|
||||
............
|
||||
Finished Placer Phase 0. REAL time: 0 secs
|
||||
|
||||
Starting Placer Phase 1.
|
||||
...................
|
||||
Placer score = 55012.
|
||||
Finished Placer Phase 1. REAL time: 4 secs
|
||||
....................
|
||||
Placer score = 53481.
|
||||
Finished Placer Phase 1. REAL time: 5 secs
|
||||
|
||||
Starting Placer Phase 2.
|
||||
.
|
||||
Placer score = 54994
|
||||
Finished Placer Phase 2. REAL time: 4 secs
|
||||
Placer score = 53406
|
||||
Finished Placer Phase 2. REAL time: 5 secs
|
||||
|
||||
|
||||
|
||||
|
|
@ -117,14 +116,13 @@ Global Clock Resources:
|
|||
DCC : 0 out of 8 (0%)
|
||||
|
||||
Global Clocks:
|
||||
PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 46
|
||||
PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 19
|
||||
PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 47
|
||||
PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 21
|
||||
PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 10
|
||||
SECONDARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 8, ce load = 0, sr load = 0
|
||||
SECONDARY "un1_wb_clk32_i" from F0 on comp "SLICE_103" on site "R6C8B", clk load = 0, ce load = 10, sr load = 0
|
||||
|
||||
PRIMARY : 3 out of 8 (37%)
|
||||
SECONDARY: 2 out of 8 (25%)
|
||||
SECONDARY: 1 out of 8 (12%)
|
||||
|
||||
|
||||
|
||||
|
|
@ -145,21 +143,18 @@ I/O Bank Usage Summary:
|
|||
| 3 | 18 / 20 ( 90%) | 3.3V | - |
|
||||
+----------+----------------+------------+-----------+
|
||||
|
||||
Total placer CPU time: 3 secs
|
||||
Total placer CPU time: 5 secs
|
||||
|
||||
Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd.
|
||||
|
||||
0 connections routed; 1008 unrouted.
|
||||
0 connections routed; 978 unrouted.
|
||||
Starting router resource preassignment
|
||||
WARNING - par: The driver of primary clock net RCLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
|
||||
WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
|
||||
|
||||
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
|
||||
Signal=wb_clk loads=1 clock_loads=1
|
||||
Completed router resource preassignment. Real time: 8 secs
|
||||
|
||||
Completed router resource preassignment. Real time: 5 secs
|
||||
|
||||
Start NBR router at 20:59:43 08/16/23
|
||||
Start NBR router at 21:55:09 08/19/23
|
||||
|
||||
*****************************************************************
|
||||
Info: NBR allows conflicts(one node used by more than one signal)
|
||||
|
|
@ -174,54 +169,41 @@ Note: NBR uses a different method to calculate timing slacks. The
|
|||
your design.
|
||||
*****************************************************************
|
||||
|
||||
Start NBR special constraint process at 20:59:43 08/16/23
|
||||
Start NBR special constraint process at 21:55:09 08/19/23
|
||||
|
||||
Start NBR section for initial routing at 20:59:43 08/16/23
|
||||
Start NBR section for initial routing at 21:55:10 08/19/23
|
||||
Level 1, iteration 1
|
||||
0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs
|
||||
0(0.00%) conflict; 776(79.35%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 7.085ns/0.000ns; real time: 9 secs
|
||||
Level 2, iteration 1
|
||||
0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs
|
||||
0(0.00%) conflict; 771(78.83%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 7.138ns/0.000ns; real time: 9 secs
|
||||
Level 3, iteration 1
|
||||
0(0.00%) conflict; 806(79.96%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs
|
||||
0(0.00%) conflict; 765(78.22%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 7.276ns/0.000ns; real time: 9 secs
|
||||
Level 4, iteration 1
|
||||
7(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs
|
||||
10(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 6.966ns/0.000ns; real time: 9 secs
|
||||
|
||||
Info: Initial congestion level at 75% usage is 0
|
||||
Info: Initial congestion area at 75% usage is 0 (0.00%)
|
||||
|
||||
Start NBR section for normal routing at 20:59:43 08/16/23
|
||||
Level 1, iteration 1
|
||||
0(0.00%) conflict; 11(1.09%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs
|
||||
Start NBR section for normal routing at 21:55:10 08/19/23
|
||||
Level 4, iteration 1
|
||||
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs
|
||||
3(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 6.966ns/0.000ns; real time: 9 secs
|
||||
Level 4, iteration 2
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 6 secs
|
||||
Estimated worst slack/total negative slack<setup>: 6.966ns/0.000ns; real time: 9 secs
|
||||
|
||||
Start NBR section for setup/hold timing optimization with effort level 3 at 20:59:43 08/16/23
|
||||
Level 4, iteration 0
|
||||
Start NBR section for setup/hold timing optimization with effort level 3 at 21:55:10 08/19/23
|
||||
|
||||
Start NBR section for re-routing at 21:55:10 08/19/23
|
||||
Level 4, iteration 1
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<hold >: 0.083ns/0.000ns; real time: 6 secs
|
||||
Level 4, iteration 0
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 4.902ns/0.000ns; real time: 6 secs
|
||||
Level 4, iteration 1
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 4.902ns/0.000ns; real time: 6 secs
|
||||
Estimated worst slack/total negative slack<setup>: 6.966ns/0.000ns; real time: 9 secs
|
||||
|
||||
Start NBR section for re-routing at 20:59:44 08/16/23
|
||||
Level 4, iteration 1
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 4.922ns/0.000ns; real time: 7 secs
|
||||
|
||||
Start NBR section for post-routing at 20:59:44 08/16/23
|
||||
Start NBR section for post-routing at 21:55:10 08/19/23
|
||||
|
||||
End NBR router with 0 unrouted connection
|
||||
|
||||
|
|
@ -229,20 +211,17 @@ NBR Summary
|
|||
-----------
|
||||
Number of unrouted connections : 0 (0.00%)
|
||||
Number of connections with timing violations : 0 (0.00%)
|
||||
Estimated worst slack<setup> : 4.922ns
|
||||
Estimated worst slack<setup> : 6.966ns
|
||||
Timing score<setup> : 0
|
||||
-----------
|
||||
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
|
||||
|
||||
|
||||
|
||||
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
|
||||
Signal=wb_clk loads=1 clock_loads=1
|
||||
|
||||
Total CPU time 6 secs
|
||||
Total REAL time: 7 secs
|
||||
Total CPU time 9 secs
|
||||
Total REAL time: 9 secs
|
||||
Completely routed.
|
||||
End of route. 1008 routed (100.00%); 0 unrouted.
|
||||
End of route. 978 routed (100.00%); 0 unrouted.
|
||||
|
||||
Hold time timing score: 0, hold timing errors: 0
|
||||
|
||||
|
|
@ -256,14 +235,14 @@ All signals are completely routed.
|
|||
|
||||
PAR_SUMMARY::Run status = Completed
|
||||
PAR_SUMMARY::Number of unrouted conns = 0
|
||||
PAR_SUMMARY::Worst slack<setup/<ns>> = 4.922
|
||||
PAR_SUMMARY::Worst slack<setup/<ns>> = 6.966
|
||||
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
|
||||
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.088
|
||||
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.304
|
||||
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
|
||||
PAR_SUMMARY::Number of errors = 0
|
||||
|
||||
Total CPU time to completion: 6 secs
|
||||
Total REAL time to completion: 7 secs
|
||||
Total CPU time to completion: 9 secs
|
||||
Total REAL time to completion: 10 secs
|
||||
|
||||
par done!
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,9 @@
|
|||
<html>
|
||||
<head>
|
||||
<title>syntmp/LCMXO2_640HC_impl1_premap_srr.htm log file</title>
|
||||
</head>
|
||||
<frameset cols="20%, 80%">
|
||||
<frame src="syntmp/LCMXO2_640HC_impl1_premap_toc.htm" name="tocFrame" />
|
||||
<frame src="syntmp/LCMXO2_640HC_impl1_premap_srr.htm" name="srrFrame"/>
|
||||
</frameset>
|
||||
</html>
|
||||
|
|
@ -1,63 +1,63 @@
|
|||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: R-2021.03L-SP1
|
||||
Install: C:\lscc\diamond\3.12\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEPC
|
||||
|
||||
Implementation : impl1
|
||||
|
||||
# Written on Wed Aug 16 20:59:30 2023
|
||||
|
||||
##### FILES SYNTAX CHECKED ##############################################
|
||||
Constraint File(s): "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS.sdc"
|
||||
|
||||
#Run constraint checker to find more issues with constraints.
|
||||
#########################################################################
|
||||
|
||||
|
||||
|
||||
No issues found in constraint syntax.
|
||||
|
||||
|
||||
|
||||
Clock Summary
|
||||
*************
|
||||
|
||||
Start Requested Requested Clock Clock Clock
|
||||
Level Clock Frequency Period Type Group Load
|
||||
----------------------------------------------------------------------------------------
|
||||
0 - RCLK 62.5 MHz 16.000 declared default_clkgroup 65
|
||||
|
||||
0 - PHI2 2.9 MHz 350.000 declared default_clkgroup 18
|
||||
|
||||
0 - nCRAS 2.9 MHz 350.000 declared default_clkgroup 14
|
||||
|
||||
0 - nCCAS 2.9 MHz 350.000 declared default_clkgroup 8
|
||||
|
||||
0 - System 100.0 MHz 10.000 system system_clkgroup 0
|
||||
========================================================================================
|
||||
|
||||
|
||||
Clock Load Summary
|
||||
******************
|
||||
|
||||
Clock Source Clock Pin Non-clock Pin Non-clock Pin
|
||||
Clock Load Pin Seq Example Seq Example Comb Example
|
||||
-----------------------------------------------------------------------------------------
|
||||
RCLK 65 RCLK(port) CASr2.C - -
|
||||
|
||||
PHI2 18 PHI2(port) Bank[7:0].C PHI2r.D[0] un1_PHI2.I[0](inv)
|
||||
|
||||
nCRAS 14 nCRAS(port) CBR.C RASr.D[0] RASr_2.I[0](inv)
|
||||
|
||||
nCCAS 8 nCCAS(port) WRD[7:0].C CASr.D[0] CASr_2.I[0](inv)
|
||||
|
||||
System 0 - - - -
|
||||
=========================================================================================
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
||||
and may only be used pursuant to the terms and conditions of a written license agreement
|
||||
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
||||
Synopsys software or the associated documentation is strictly prohibited.
|
||||
Tool: Synplify Pro (R)
|
||||
Build: R-2021.03L-SP1
|
||||
Install: C:\lscc\diamond\3.12\synpbase
|
||||
OS: Windows 6.2
|
||||
|
||||
Hostname: ZANEMACWIN11
|
||||
|
||||
Implementation : impl1
|
||||
|
||||
# Written on Sat Aug 19 21:54:50 2023
|
||||
|
||||
##### FILES SYNTAX CHECKED ##############################################
|
||||
Constraint File(s): "Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc"
|
||||
|
||||
#Run constraint checker to find more issues with constraints.
|
||||
#########################################################################
|
||||
|
||||
|
||||
|
||||
No issues found in constraint syntax.
|
||||
|
||||
|
||||
|
||||
Clock Summary
|
||||
*************
|
||||
|
||||
Start Requested Requested Clock Clock Clock
|
||||
Level Clock Frequency Period Type Group Load
|
||||
----------------------------------------------------------------------------------------
|
||||
0 - RCLK 62.5 MHz 16.000 declared default_clkgroup 65
|
||||
|
||||
0 - PHI2 2.9 MHz 350.000 declared default_clkgroup 19
|
||||
|
||||
0 - nCRAS 2.9 MHz 350.000 declared default_clkgroup 14
|
||||
|
||||
0 - nCCAS 2.9 MHz 350.000 declared default_clkgroup 8
|
||||
|
||||
0 - System 100.0 MHz 10.000 system system_clkgroup 0
|
||||
========================================================================================
|
||||
|
||||
|
||||
Clock Load Summary
|
||||
******************
|
||||
|
||||
Clock Source Clock Pin Non-clock Pin Non-clock Pin
|
||||
Clock Load Pin Seq Example Seq Example Comb Example
|
||||
-----------------------------------------------------------------------------------------
|
||||
RCLK 65 RCLK(port) CASr2.C - -
|
||||
|
||||
PHI2 19 PHI2(port) Bank[7:0].C PHI2r.D[0] un1_PHI2.I[0](inv)
|
||||
|
||||
nCRAS 14 nCRAS(port) CBR.C RASr.D[0] RASr_2.I[0](inv)
|
||||
|
||||
nCCAS 8 nCCAS(port) WRD[7:0].C CASr.D[0] CASr_2.I[0](inv)
|
||||
|
||||
System 0 - - - -
|
||||
=========================================================================================
|
||||
|
|
|
|||
|
|
@ -24,9 +24,9 @@
|
|||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Last Process:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">JEDEC File</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000"></SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">State:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">Passed</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000"></SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Target Device:</SPAN></TD>
|
||||
|
|
@ -62,15 +62,15 @@
|
|||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Updated:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2023/08/16 20:59:46</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2023/08/20 05:55:58</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Location:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Project File:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf</SPAN></TD>
|
||||
</TR>
|
||||
</small></TABLE>
|
||||
<BR>
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,24 +1,24 @@
|
|||
#
|
||||
# Logical Preferences generated for Lattice by Synplify map202103lat, Build 070R.
|
||||
#
|
||||
|
||||
# Period Constraints
|
||||
FREQUENCY PORT "PHI2" 2.9 MHz;
|
||||
FREQUENCY PORT "nCCAS" 2.9 MHz;
|
||||
FREQUENCY PORT "nCRAS" 2.9 MHz;
|
||||
FREQUENCY PORT "RCLK" 62.5 MHz;
|
||||
|
||||
|
||||
# Output Constraints
|
||||
|
||||
# Input Constraints
|
||||
|
||||
# Point-to-point Delay Constraints
|
||||
|
||||
|
||||
|
||||
# Block Path Constraints
|
||||
|
||||
BLOCK ASYNCPATHS;
|
||||
|
||||
# End of generated Logical Preferences.
|
||||
#
|
||||
# Logical Preferences generated for Lattice by Synplify map202103lat, Build 070R.
|
||||
#
|
||||
|
||||
# Period Constraints
|
||||
FREQUENCY PORT "PHI2" 2.9 MHz;
|
||||
FREQUENCY PORT "nCCAS" 2.9 MHz;
|
||||
FREQUENCY PORT "nCRAS" 2.9 MHz;
|
||||
FREQUENCY PORT "RCLK" 62.5 MHz;
|
||||
|
||||
|
||||
# Output Constraints
|
||||
|
||||
# Input Constraints
|
||||
|
||||
# Point-to-point Delay Constraints
|
||||
|
||||
|
||||
|
||||
# Block Path Constraints
|
||||
|
||||
BLOCK ASYNCPATHS;
|
||||
|
||||
# End of generated Logical Preferences.
|
||||
|
|
|
|||
|
|
@ -1,66 +1,66 @@
|
|||
#-- Lattice Semiconductor Corporation Ltd.
|
||||
#-- Synplify OEM project file
|
||||
|
||||
#device options
|
||||
set_option -technology MACHXO2
|
||||
set_option -part LCMXO2_640HC
|
||||
set_option -package TG100C
|
||||
set_option -speed_grade -4
|
||||
|
||||
#compilation/mapping options
|
||||
set_option -symbolic_fsm_compiler true
|
||||
set_option -resource_sharing true
|
||||
|
||||
#use verilog 2001 standard option
|
||||
set_option -vlog_std v2001
|
||||
|
||||
#map options
|
||||
set_option -frequency 100
|
||||
set_option -maxfan 1000
|
||||
set_option -auto_constrain_io 0
|
||||
set_option -disable_io_insertion false
|
||||
set_option -retiming false; set_option -pipe true
|
||||
set_option -force_gsr false
|
||||
set_option -compiler_compatible 0
|
||||
set_option -dup false
|
||||
|
||||
add_file -constraint {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS.sdc}
|
||||
set_option -default_enum_encoding default
|
||||
|
||||
#simulation options
|
||||
|
||||
|
||||
#timing analysis options
|
||||
|
||||
|
||||
|
||||
#automatic place and route (vendor) options
|
||||
set_option -write_apr_constraint 1
|
||||
|
||||
#synplifyPro options
|
||||
set_option -fix_gated_and_generated_clocks 1
|
||||
set_option -update_models_cp 0
|
||||
set_option -resolve_multiple_driver 0
|
||||
|
||||
|
||||
set_option -seqshift_no_replicate 0
|
||||
|
||||
#-- add_file options
|
||||
set_option -include_path {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC}
|
||||
add_file -verilog -vlog_std v2001 {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.v}
|
||||
add_file -verilog -vlog_std v2001 {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/REFB.v}
|
||||
|
||||
#-- top module name
|
||||
set_option -top_module RAM2GS
|
||||
|
||||
#-- set result format/file last
|
||||
project -result_file {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.edi}
|
||||
|
||||
#-- error message log file
|
||||
project -log_file {LCMXO2_640HC_impl1.srf}
|
||||
|
||||
#-- set any command lines input by customer
|
||||
|
||||
|
||||
#-- run Synplify with 'arrange HDL file'
|
||||
project -run
|
||||
#-- Lattice Semiconductor Corporation Ltd.
|
||||
#-- Synplify OEM project file
|
||||
|
||||
#device options
|
||||
set_option -technology MACHXO2
|
||||
set_option -part LCMXO2_640HC
|
||||
set_option -package TG100C
|
||||
set_option -speed_grade -4
|
||||
|
||||
#compilation/mapping options
|
||||
set_option -symbolic_fsm_compiler true
|
||||
set_option -resource_sharing true
|
||||
|
||||
#use verilog 2001 standard option
|
||||
set_option -vlog_std v2001
|
||||
|
||||
#map options
|
||||
set_option -frequency 100
|
||||
set_option -maxfan 1000
|
||||
set_option -auto_constrain_io 0
|
||||
set_option -disable_io_insertion false
|
||||
set_option -retiming false; set_option -pipe true
|
||||
set_option -force_gsr false
|
||||
set_option -compiler_compatible 0
|
||||
set_option -dup false
|
||||
|
||||
add_file -constraint {Y:/Repos/RAM2GS/CPLD/RAM2GS.sdc}
|
||||
set_option -default_enum_encoding default
|
||||
|
||||
#simulation options
|
||||
|
||||
|
||||
#timing analysis options
|
||||
|
||||
|
||||
|
||||
#automatic place and route (vendor) options
|
||||
set_option -write_apr_constraint 1
|
||||
|
||||
#synplifyPro options
|
||||
set_option -fix_gated_and_generated_clocks 1
|
||||
set_option -update_models_cp 0
|
||||
set_option -resolve_multiple_driver 0
|
||||
|
||||
|
||||
set_option -seqshift_no_replicate 0
|
||||
|
||||
#-- add_file options
|
||||
set_option -include_path {Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC}
|
||||
add_file -verilog -vlog_std v2001 {Y:/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v}
|
||||
add_file -verilog -vlog_std v2001 {Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/REFB.v}
|
||||
|
||||
#-- top module name
|
||||
set_option -top_module RAM2GS
|
||||
|
||||
#-- set result format/file last
|
||||
project -result_file {Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.edi}
|
||||
|
||||
#-- error message log file
|
||||
project -log_file {LCMXO2_640HC_impl1.srf}
|
||||
|
||||
#-- set any command lines input by customer
|
||||
|
||||
|
||||
#-- run Synplify with 'arrange HDL file'
|
||||
project -run -clean
|
||||
|
|
|
|||
|
|
@ -0,0 +1,512 @@
|
|||
<HTML>
|
||||
<HEAD><TITLE>Lattice Map TRACE Report</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Map_Twr"></A><B><U><big>Map TRACE Report</big></U></B>
|
||||
|
||||
Loading design for application trce from file lcmxo2_640hc_impl1_map.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-640HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.39.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
Setup and Hold Report
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
<A name="Map_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454</big></U></B>
|
||||
Sat Aug 19 21:54:58 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
<A name="mtw1_set_ri"></A><B><U><big>Report Information</big></U></B>
|
||||
------------------
|
||||
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o LCMXO2_640HC_impl1.tw1 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.prf
|
||||
Design file: lcmxo2_640hc_impl1_map.ncd
|
||||
Preference file: lcmxo2_640hc_impl1.prf
|
||||
Device,speed: LCMXO2-640HC,4
|
||||
Report level: verbose report, limited to 1 item per preference
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
<A name="mtw1_set_ps"></A><B><U><big>Preference Summary</big></U></B>
|
||||
|
||||
<LI><A href='#map_twr_pref_0_0' Target='right'>FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)</A></LI> 158 items scored, 0 timing errors detected.
|
||||
Report: 53.254MHz is the maximum frequency for this preference.
|
||||
|
||||
<LI><A href='#map_twr_pref_0_1' Target='right'>FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
|
||||
Report: 150.150MHz is the maximum frequency for this preference.
|
||||
|
||||
<LI><A href='#map_twr_pref_0_2' Target='right'>FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
|
||||
Report: 150.150MHz is the maximum frequency for this preference.
|
||||
|
||||
<LI><A href='#map_twr_pref_0_3' Target='right'>FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)</A></LI> 844 items scored, 0 timing errors detected.
|
||||
Report: 102.312MHz is the maximum frequency for this preference.
|
||||
|
||||
BLOCK ASYNCPATHS
|
||||
BLOCK RESETPATHS
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
================================================================================
|
||||
<A name="map_twr_pref_0_0"></A>Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
|
||||
158 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 163.025ns (weighted slack = 326.050ns)
|
||||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q Bank_0io[2] (from PHI2_c +)
|
||||
Destination: FF Data in ADSubmitted (to PHI2_c -)
|
||||
|
||||
Delay: 9.223ns (33.1% logic, 66.9% route), 6 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
9.223ns physical path delay Din[2]_MGIOL to SLICE_10 meets
|
||||
172.414ns delay constraint less
|
||||
0.166ns DIN_SET requirement (totaling 172.248ns) by 163.025ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path Din[2]_MGIOL to SLICE_10:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
C2INP_DEL --- 0.577 *[2]_MGIOL.CLK to *n[2]_MGIOL.IN Din[2]_MGIOL (from PHI2_c)
|
||||
ROUTE 1 e 1.234 *n[2]_MGIOL.IN to SLICE_37.A1 Bank[2]
|
||||
CTOF_DEL --- 0.495 SLICE_37.A1 to SLICE_37.F1 SLICE_37
|
||||
ROUTE 1 e 1.234 SLICE_37.F1 to SLICE_94.D0 un1_Bank_1_4
|
||||
CTOF_DEL --- 0.495 SLICE_94.D0 to SLICE_94.F0 SLICE_94
|
||||
ROUTE 2 e 1.234 SLICE_94.F0 to SLICE_90.D0 N_304
|
||||
CTOF_DEL --- 0.495 SLICE_90.D0 to SLICE_90.F0 SLICE_90
|
||||
ROUTE 5 e 1.234 SLICE_90.F0 to SLICE_91.C1 C1WR_7
|
||||
CTOF_DEL --- 0.495 SLICE_91.C1 to SLICE_91.F1 SLICE_91
|
||||
ROUTE 2 e 1.234 SLICE_91.F1 to SLICE_10.B0 un1_ADWR
|
||||
CTOF_DEL --- 0.495 SLICE_10.B0 to SLICE_10.F0 SLICE_10
|
||||
ROUTE 1 e 0.001 SLICE_10.F0 to SLICE_10.DI0 ADSubmitted_r (to PHI2_c)
|
||||
--------
|
||||
9.223 (33.1% logic, 66.9% route), 6 logic levels.
|
||||
|
||||
Report: 53.254MHz is the maximum frequency for this preference.
|
||||
|
||||
|
||||
================================================================================
|
||||
<A name="map_twr_pref_0_1"></A>Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
|
||||
0 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 338.168ns
|
||||
The internal maximum frequency of the following component is 150.150 MHz
|
||||
|
||||
Logical Details: Cell type Pin name Component name
|
||||
|
||||
Destination: PIO PAD nCCAS
|
||||
|
||||
Delay: 6.660ns -- based on Minimum Pulse Width
|
||||
|
||||
Report: 150.150MHz is the maximum frequency for this preference.
|
||||
|
||||
|
||||
================================================================================
|
||||
<A name="map_twr_pref_0_2"></A>Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
|
||||
0 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 338.168ns
|
||||
The internal maximum frequency of the following component is 150.150 MHz
|
||||
|
||||
Logical Details: Cell type Pin name Component name
|
||||
|
||||
Destination: PIO PAD nCRAS
|
||||
|
||||
Delay: 6.660ns -- based on Minimum Pulse Width
|
||||
|
||||
Report: 150.150MHz is the maximum frequency for this preference.
|
||||
|
||||
|
||||
================================================================================
|
||||
<A name="map_twr_pref_0_3"></A>Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
|
||||
844 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 6.226ns
|
||||
The internal maximum frequency of the following component is 102.312 MHz
|
||||
|
||||
Logical Details: Cell type Pin name Component name
|
||||
|
||||
Destination: EFB WBCLKI ufmefb/EFBInst_0
|
||||
|
||||
Delay: 9.774ns -- based on Minimum Pulse Width
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 6.270ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q S[0] (from RCLK_c +)
|
||||
Destination: FF Data in nRCS_0io (to RCLK_c +)
|
||||
|
||||
Delay: 9.577ns (30.6% logic, 69.4% route), 6 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
9.577ns physical path delay SLICE_16 to nRCS_MGIOL meets
|
||||
16.000ns delay constraint less
|
||||
0.153ns DO_SET requirement (totaling 15.847ns) by 6.270ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path SLICE_16 to nRCS_MGIOL:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.452 SLICE_16.CLK to SLICE_16.Q0 SLICE_16 (from RCLK_c)
|
||||
ROUTE 9 e 1.234 SLICE_16.Q0 to SLICE_45.A0 CO0
|
||||
CTOF_DEL --- 0.495 SLICE_45.A0 to SLICE_45.F0 SLICE_45
|
||||
ROUTE 4 e 0.480 SLICE_45.F0 to SLICE_45.A1 N_41
|
||||
CTOF_DEL --- 0.495 SLICE_45.A1 to SLICE_45.F1 SLICE_45
|
||||
ROUTE 2 e 1.234 SLICE_45.F1 to SLICE_77.D0 nRRAS_5_u_i_0
|
||||
CTOF_DEL --- 0.495 SLICE_77.D0 to SLICE_77.F0 SLICE_77
|
||||
ROUTE 1 e 1.234 SLICE_77.F0 to SLICE_117.B1 N_25
|
||||
CTOF_DEL --- 0.495 SLICE_117.B1 to SLICE_117.F1 SLICE_117
|
||||
ROUTE 1 e 1.234 SLICE_117.F1 to SLICE_88.C1 N_28_i_sn
|
||||
CTOF_DEL --- 0.495 SLICE_88.C1 to SLICE_88.F1 SLICE_88
|
||||
ROUTE 1 e 1.234 SLICE_88.F1 to *CS_MGIOL.OPOS N_28_i (to RCLK_c)
|
||||
--------
|
||||
9.577 (30.6% logic, 69.4% route), 6 logic levels.
|
||||
|
||||
Report: 102.312MHz is the maximum frequency for this preference.
|
||||
|
||||
<A name="mtw1_set_rs"></A><B><U><big>Report Summary</big></U></B>
|
||||
--------------
|
||||
----------------------------------------------------------------------------
|
||||
Preference | Constraint| Actual|Levels
|
||||
----------------------------------------------------------------------------
|
||||
| | |
|
||||
FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 53.254 MHz| 6
|
||||
| | |
|
||||
FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
|
||||
| | |
|
||||
FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
|
||||
| | |
|
||||
FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 102.312 MHz| 0
|
||||
| | |
|
||||
----------------------------------------------------------------------------
|
||||
|
||||
|
||||
All preferences were met.
|
||||
|
||||
|
||||
<A name="mtw1_set_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
|
||||
------------------------
|
||||
|
||||
Found 4 clocks:
|
||||
|
||||
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12
|
||||
No transfer within this clock domain is found
|
||||
|
||||
Data transfers from:
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD
|
||||
Not reported because source and destination domains are unrelated.
|
||||
To report these transfers please refer to preference CLKSKEWDIFF to define
|
||||
external clock skew between clock ports.
|
||||
|
||||
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
|
||||
No transfer within this clock domain is found
|
||||
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47
|
||||
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
|
||||
|
||||
Data transfers from:
|
||||
Clock Domain: nCRAS_c Source: nCRAS.PAD
|
||||
Not reported because source and destination domains are unrelated.
|
||||
To report these transfers please refer to preference CLKSKEWDIFF to define
|
||||
external clock skew between clock ports.
|
||||
|
||||
Clock Domain: PHI2_c Source: PHI2.PAD
|
||||
Not reported because source and destination domains are unrelated.
|
||||
To report these transfers please refer to preference CLKSKEWDIFF to define
|
||||
external clock skew between clock ports.
|
||||
|
||||
Clock Domain: PHI2_c Source: PHI2.PAD Loads: 22
|
||||
Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
|
||||
|
||||
Data transfers from:
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD
|
||||
Not reported because source and destination domains are unrelated.
|
||||
To report these transfers please refer to preference CLKSKEWDIFF to define
|
||||
external clock skew between clock ports.
|
||||
|
||||
|
||||
<A name="mtw1_set_ts"></A><B><U><big>Timing summary (Setup):</big></U></B>
|
||||
---------------
|
||||
|
||||
Timing errors: 0 Score: 0
|
||||
Cumulative negative slack: 0
|
||||
|
||||
Constraints cover 1002 paths, 4 nets, and 687 connections (70.25% coverage)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
<A name="Map_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454</big></U></B>
|
||||
Sat Aug 19 21:54:58 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
<A name="mtw1_hold_ri"></A><B><U><big>Report Information</big></U></B>
|
||||
------------------
|
||||
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o LCMXO2_640HC_impl1.tw1 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.prf
|
||||
Design file: lcmxo2_640hc_impl1_map.ncd
|
||||
Preference file: lcmxo2_640hc_impl1.prf
|
||||
Device,speed: LCMXO2-640HC,M
|
||||
Report level: verbose report, limited to 1 item per preference
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
<A name="mtw1_hold_ps"></A><B><U><big>Preference Summary</big></U></B>
|
||||
|
||||
<LI><A href='#map_twr_pref_1_0' Target='right'>FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)</A></LI> 158 items scored, 0 timing errors detected.
|
||||
|
||||
<LI><A href='#map_twr_pref_1_1' Target='right'>FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
|
||||
|
||||
<LI><A href='#map_twr_pref_1_2' Target='right'>FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
|
||||
|
||||
<LI><A href='#map_twr_pref_1_3' Target='right'>FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)</A></LI> 844 items scored, 0 timing errors detected.
|
||||
|
||||
BLOCK ASYNCPATHS
|
||||
BLOCK RESETPATHS
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
================================================================================
|
||||
<A name="map_twr_pref_1_0"></A>Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
|
||||
158 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 0.447ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q ADSubmitted (from PHI2_c -)
|
||||
Destination: FF Data in ADSubmitted (to PHI2_c -)
|
||||
|
||||
Delay: 0.434ns (53.9% logic, 46.1% route), 2 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
0.434ns physical path delay SLICE_10 to SLICE_10 meets
|
||||
-0.013ns DIN_HLD and
|
||||
0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path SLICE_10 to SLICE_10:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.133 SLICE_10.CLK to SLICE_10.Q0 SLICE_10 (from PHI2_c)
|
||||
ROUTE 2 e 0.199 SLICE_10.Q0 to SLICE_10.A0 ADSubmitted
|
||||
CTOF_DEL --- 0.101 SLICE_10.A0 to SLICE_10.F0 SLICE_10
|
||||
ROUTE 1 e 0.001 SLICE_10.F0 to SLICE_10.DI0 ADSubmitted_r (to PHI2_c)
|
||||
--------
|
||||
0.434 (53.9% logic, 46.1% route), 2 logic levels.
|
||||
|
||||
|
||||
================================================================================
|
||||
<A name="map_twr_pref_1_1"></A>Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
|
||||
0 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
================================================================================
|
||||
<A name="map_twr_pref_1_2"></A>Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
|
||||
0 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
================================================================================
|
||||
<A name="map_twr_pref_1_3"></A>Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
|
||||
844 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 0.351ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q CASr (from RCLK_c +)
|
||||
Destination: FF Data in CASr2 (to RCLK_c +)
|
||||
|
||||
Delay: 0.332ns (40.1% logic, 59.9% route), 1 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
0.332ns physical path delay SLICE_12 to SLICE_12 meets
|
||||
-0.019ns M_HLD and
|
||||
0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path SLICE_12 to SLICE_12:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.133 SLICE_12.CLK to SLICE_12.Q0 SLICE_12 (from RCLK_c)
|
||||
ROUTE 1 e 0.199 SLICE_12.Q0 to SLICE_12.M1 CASr (to RCLK_c)
|
||||
--------
|
||||
0.332 (40.1% logic, 59.9% route), 1 logic levels.
|
||||
|
||||
<A name="mtw1_hold_rs"></A><B><U><big>Report Summary</big></U></B>
|
||||
--------------
|
||||
----------------------------------------------------------------------------
|
||||
Preference(MIN Delays) | Constraint| Actual|Levels
|
||||
----------------------------------------------------------------------------
|
||||
| | |
|
||||
FREQUENCY PORT "PHI2" 2.900000 MHz ; | -| -| 2
|
||||
| | |
|
||||
FREQUENCY PORT "nCCAS" 2.900000 MHz ; | -| -| 0
|
||||
| | |
|
||||
FREQUENCY PORT "nCRAS" 2.900000 MHz ; | -| -| 0
|
||||
| | |
|
||||
FREQUENCY PORT "RCLK" 62.500000 MHz ; | -| -| 1
|
||||
| | |
|
||||
----------------------------------------------------------------------------
|
||||
|
||||
|
||||
All preferences were met.
|
||||
|
||||
|
||||
<A name="mtw1_hold_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
|
||||
------------------------
|
||||
|
||||
Found 4 clocks:
|
||||
|
||||
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12
|
||||
No transfer within this clock domain is found
|
||||
|
||||
Data transfers from:
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD
|
||||
Not reported because source and destination domains are unrelated.
|
||||
To report these transfers please refer to preference CLKSKEWDIFF to define
|
||||
external clock skew between clock ports.
|
||||
|
||||
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
|
||||
No transfer within this clock domain is found
|
||||
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47
|
||||
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
|
||||
|
||||
Data transfers from:
|
||||
Clock Domain: nCRAS_c Source: nCRAS.PAD
|
||||
Not reported because source and destination domains are unrelated.
|
||||
To report these transfers please refer to preference CLKSKEWDIFF to define
|
||||
external clock skew between clock ports.
|
||||
|
||||
Clock Domain: PHI2_c Source: PHI2.PAD
|
||||
Not reported because source and destination domains are unrelated.
|
||||
To report these transfers please refer to preference CLKSKEWDIFF to define
|
||||
external clock skew between clock ports.
|
||||
|
||||
Clock Domain: PHI2_c Source: PHI2.PAD Loads: 22
|
||||
Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
|
||||
|
||||
Data transfers from:
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD
|
||||
Not reported because source and destination domains are unrelated.
|
||||
To report these transfers please refer to preference CLKSKEWDIFF to define
|
||||
external clock skew between clock ports.
|
||||
|
||||
|
||||
<A name="mtw1_hold_ts"></A><B><U><big>Timing summary (Hold):</big></U></B>
|
||||
---------------
|
||||
|
||||
Timing errors: 0 Score: 0
|
||||
Cumulative negative slack: 0
|
||||
|
||||
Constraints cover 1002 paths, 4 nets, and 687 connections (70.25% coverage)
|
||||
|
||||
|
||||
|
||||
<A name="mtw1_ts"></A><B><U><big>Timing summary (Setup and Hold):</big></U></B>
|
||||
---------------
|
||||
|
||||
Timing errors: 0 (setup), 0 (hold)
|
||||
Score: 0 (setup), 0 (hold)
|
||||
Cumulative negative slack: 0 (0+0)
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,197 +1,199 @@
|
|||
%%% protect protected_file
|
||||
@EG<?lPDRCHs#F"M=4"3jROCMFM8Hok="0UV-"
|
||||
?>
|
||||
-<!-7R]pHR]CssNORE$7HCVMHH0FwMRHRDCwlFsN-0R-<>
|
||||
]17p0Osk0CksRsPC#MHF=3"4j
|
||||
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|
||||
!S<-1-RFOksCHRVDRC#O0FMskHL0oHMRR0F0REC8HC#o-MR-S>
|
||||
<k1Fs#OC>S
|
||||
S<k1FsROCbB=":#\DO8O\HFNlMd8\3\4.#b$MLCN#\LDH\ODkC\M0lENOG3F.PN"R=""jR"D=PHCsD"FoRHOD#"0=-R4"b#DH0-="4>"/
|
||||
<SS1sFkObCR=:"B\OD#OH\8NMlF83\d4#.\$LMbN\#CD\HLDCkOMb0\l8H_CPV3"=RN"R4"DP="CDsHFRo"O#DH0-="4b"RD0H#=4"-"
|
||||
/>S1S<FOksC=Rb"\B:DO#O\N8Hl8FM\4d3.$\#MNbL#DC\HPL\D\FoEC$bs8lF#"3PR"N=.D"R=C"PsFHDoO"RD0H#=4"-"DRbH=#0""-4/S>
|
||||
SF<1kCsOR"b=BD:\#\OO8lHNF\M8d.34\M#$b#LNCH\DLD\PFko\lOs_NlbH3RP"Nd=""=RD"sPCHoDF"DROH=#0""-4RHbD#"0=-/4">S
|
||||
S<k1FsROCbB=":#\DO8O\HFNlMd8\3\4.#b$MLCN#\LDH\FPDoO\#C_lHFCL[O30#PN"R=""cR"D=PHCsD"FoRHOD#"0=-R4"b#DH0-="4>"/
|
||||
<SS1sFkObCR=:"B\OD#OH\8NMlF83\d4#.\$LMbN\#CD\HLPoDF\C#OlbH_H#bC3E#P"=RN"R6"DP="CDsHFRo"O#DH0-="4b"RD0H#=4"-"
|
||||
/>S1S<FOksC=Rb"\7:m7MCsCHP\O7FkMlC0t#\Hk0]Lq\)v1.t\pBu7q\)v1.t-vpBX3m.PN"R=""nR"D=PHCsD"FoRHOD#"0=RR("b#DH0-="4>"/
|
||||
<SS1sFkObCR=:"7\CmM7PsHCF\7OCklM\0#t]H0k)L\qtv.1u\Bpp7\BmvX.c-nj\]B)A w3RP"N(=""=RD"sPCHoDF"DROH=#0""-4RHbD#"0=R/n"><
|
||||
S/k1Fs#OC>S
|
||||
|
||||
<-!-R8vFkRDCs0FFR>--
|
||||
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|
||||
|
||||
|
||||
|
||||
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|
||||
S!R--vkF8D7CRCMVHHF0HM-R-><
|
||||
S7RCVMI="F3s e3]QPHCsD"FoR"D=PHCsD"Fo>S
|
||||
S<NWR=""jR=LD".44jL"RO(=""DRC=4"4.Rj"C"O=g/"R>S
|
||||
S<MqR=C"3Gs0CM"NDR"P=4>"/
|
||||
<SSq=RM"s3FHNohlRC"PI="F3s e"]Q/S>
|
||||
SR<qM3="#_$Mks#CLRL"P4=""
|
||||
/>SqS<R"M=3M#$_LDH_DOCDP"R=""4/S>
|
||||
SR<qM3="#_$M0NsC0#_N_NLDOF LGP"R=""4/S>
|
||||
SR<qM#="$DM_HOL_C"DDR"P=4>"/
|
||||
/S<7>CV
|
||||
<
|
||||
S!R--vkF8D7CRCMVHHF0HM-R-><
|
||||
S7RCVMI="F3s e3pmPHCsD"FoR"D=PHCsD"Fo>S
|
||||
S<NWR=""jR=LD".44cL"RO(=""DRC=4"4.Rc"C"O=g/"R>S
|
||||
S<MqR=C"3Gs0CM"NDR"P=4>"/
|
||||
<SSq=RM"s3FHNohlRC"PI="F3s e"pm/S>
|
||||
SR<qM3="#_$Mks#CLRL"P4=""
|
||||
/>SqS<R"M=3M#$_LDH_DOCDP"R=""4/S>
|
||||
SR<qM3="#_$M0NsC0#_N_NLDOF LGP"R=""4/S>
|
||||
SR<qM#="$DM_HOL_C"DDR"P=4>"/
|
||||
/S<7>CV
|
||||
<
|
||||
S!R--vkF8D7CRCMVHHF0HM-R-><
|
||||
S7RCVMI="F3s 3wAPHCsD"FoR"D=PHCsD"Fo>S
|
||||
S<NWR=""jR=LD"j4UjL"RO(=""DRC=U"4jRj"C"O=g/"R>S
|
||||
S<MqR=C"3Gs0CM"NDR"P=4>"/
|
||||
<SSq=RM"s3FHNohlRC"PI="F3s "wA/S>
|
||||
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|||
File diff suppressed because one or more lines are too long
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|
@ -0,0 +1,49 @@
|
|||
<?xml version='1.0' encoding='utf-8' ?>
|
||||
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|
||||
<ispXCF version="3.12">
|
||||
<Comment></Comment>
|
||||
<Chain>
|
||||
<Comm>JTAG</Comm>
|
||||
<Device>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<VerifyUsercode value="FALSE"/>
|
||||
<TCKDelay>1</TCKDelay>
|
||||
</ProjectOptions>
|
||||
<CableOptions>
|
||||
<CableName>USB2</CableName>
|
||||
<PortAdd>FTUSB-0</PortAdd>
|
||||
</CableOptions>
|
||||
</ispXCF>
|
||||
|
|
@ -0,0 +1,135 @@
|
|||
Loading design for application iotiming from file lcmxo2_640hc_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-640HC
|
||||
Package: TQFP100
|
||||
Performance: 5
|
||||
Package Status: Final Version 1.39.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
Loading design for application iotiming from file lcmxo2_640hc_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-640HC
|
||||
Package: TQFP100
|
||||
Performance: 6
|
||||
Package Status: Final Version 1.39.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
Loading design for application iotiming from file lcmxo2_640hc_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-640HC
|
||||
Package: TQFP100
|
||||
Performance: M
|
||||
Package Status: Final Version 1.39.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
// Design: RAM2GS
|
||||
// Package: TQFP100
|
||||
// ncd File: lcmxo2_640hc_impl1.ncd
|
||||
// Version: Diamond (64-bit) 3.12.1.454
|
||||
// Written on Sat Aug 19 21:55:13 2023
|
||||
// M: Minimum Performance Grade
|
||||
// iotiming LCMXO2_640HC_impl1.ncd LCMXO2_640HC_impl1.prf -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
|
||||
|
||||
I/O Timing Report (All units are in ns)
|
||||
|
||||
Worst Case Results across Performance Grades (M, 6, 5, 4):
|
||||
|
||||
// Input Setup and Hold Times
|
||||
|
||||
Port Clock Edge Setup Performance_Grade Hold Performance_Grade
|
||||
----------------------------------------------------------------------
|
||||
CROW[0] nCRAS F 2.553 4 -0.117 M
|
||||
CROW[1] nCRAS F 2.019 4 0.001 M
|
||||
Din[0] PHI2 F 4.715 4 3.636 4
|
||||
Din[0] nCCAS F 0.790 4 0.535 4
|
||||
Din[1] PHI2 F 5.021 4 3.516 4
|
||||
Din[1] nCCAS F 1.086 4 0.264 4
|
||||
Din[2] PHI2 F 3.385 4 3.516 4
|
||||
Din[2] nCCAS F 0.282 4 0.948 4
|
||||
Din[3] PHI2 F 4.644 4 3.516 4
|
||||
Din[3] nCCAS F 1.278 4 0.095 4
|
||||
Din[4] PHI2 F 4.335 4 3.516 4
|
||||
Din[4] nCCAS F 2.446 4 -0.199 M
|
||||
Din[5] PHI2 F 3.662 4 3.516 4
|
||||
Din[5] nCCAS F 0.907 4 0.402 4
|
||||
Din[6] PHI2 F 4.869 4 3.636 4
|
||||
Din[6] nCCAS F 1.378 4 0.023 M
|
||||
Din[7] PHI2 F 4.138 4 3.636 4
|
||||
Din[7] nCCAS F 2.072 4 -0.120 M
|
||||
MAin[0] PHI2 F 5.613 4 0.006 M
|
||||
MAin[0] nCRAS F 0.244 4 1.146 4
|
||||
MAin[1] PHI2 F 3.409 4 0.354 6
|
||||
MAin[1] nCRAS F 0.244 4 1.146 4
|
||||
MAin[2] PHI2 F 5.391 4 0.132 M
|
||||
MAin[2] nCRAS F 0.250 4 1.141 4
|
||||
MAin[3] PHI2 F 4.627 4 0.087 M
|
||||
MAin[3] nCRAS F 0.507 4 0.910 4
|
||||
MAin[4] PHI2 F 5.665 4 -0.133 M
|
||||
MAin[4] nCRAS F 0.675 4 0.777 4
|
||||
MAin[5] PHI2 F 5.569 4 0.129 M
|
||||
MAin[5] nCRAS F 0.050 4 1.238 4
|
||||
MAin[6] PHI2 F 5.717 4 -0.141 M
|
||||
MAin[6] nCRAS F 0.242 4 1.146 4
|
||||
MAin[7] PHI2 F 5.943 4 -0.173 M
|
||||
MAin[7] nCRAS F 0.170 4 1.228 4
|
||||
MAin[8] nCRAS F 0.759 4 0.696 4
|
||||
MAin[9] nCRAS F 0.516 4 0.891 4
|
||||
PHI2 RCLK R -0.312 M 3.167 4
|
||||
nCCAS RCLK R 2.600 4 -0.176 M
|
||||
nCCAS nCRAS F 3.106 4 -0.235 M
|
||||
nCRAS RCLK R 1.803 4 -0.055 M
|
||||
nFWE PHI2 F 4.680 4 0.261 M
|
||||
nFWE nCRAS F 2.234 4 1.143 4
|
||||
|
||||
|
||||
// Clock to Output Delay
|
||||
|
||||
Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
|
||||
------------------------------------------------------------------------
|
||||
LED RCLK R 9.922 4 2.878 M
|
||||
LED nCRAS F 10.555 4 3.057 M
|
||||
RA[0] RCLK R 11.638 4 3.406 M
|
||||
RA[0] nCRAS F 11.771 4 3.430 M
|
||||
RA[10] RCLK R 8.141 4 2.620 M
|
||||
RA[11] PHI2 R 8.610 4 2.756 M
|
||||
RA[1] RCLK R 11.674 4 3.407 M
|
||||
RA[1] nCRAS F 10.635 4 3.155 M
|
||||
RA[2] RCLK R 12.933 4 3.729 M
|
||||
RA[2] nCRAS F 11.858 4 3.449 M
|
||||
RA[3] RCLK R 12.587 4 3.664 M
|
||||
RA[3] nCRAS F 11.255 4 3.298 M
|
||||
RA[4] RCLK R 11.721 4 3.433 M
|
||||
RA[4] nCRAS F 11.153 4 3.297 M
|
||||
RA[5] RCLK R 12.544 4 3.620 M
|
||||
RA[5] nCRAS F 11.480 4 3.360 M
|
||||
RA[6] RCLK R 12.984 4 3.775 M
|
||||
RA[6] nCRAS F 11.528 4 3.407 M
|
||||
RA[7] RCLK R 12.553 4 3.625 M
|
||||
RA[7] nCRAS F 11.610 4 3.368 M
|
||||
RA[8] RCLK R 11.836 4 3.453 M
|
||||
RA[8] nCRAS F 10.797 4 3.201 M
|
||||
RA[9] RCLK R 11.182 4 3.271 M
|
||||
RA[9] nCRAS F 11.135 4 3.279 M
|
||||
RBA[0] nCRAS F 8.439 4 2.703 M
|
||||
RBA[1] nCRAS F 8.439 4 2.703 M
|
||||
RCKE RCLK R 10.083 4 3.081 M
|
||||
RDQMH RCLK R 11.381 4 3.325 M
|
||||
RDQML RCLK R 10.735 4 3.173 M
|
||||
RD[0] nCCAS F 8.223 4 2.594 M
|
||||
RD[1] nCCAS F 8.223 4 2.594 M
|
||||
RD[2] nCCAS F 8.223 4 2.594 M
|
||||
RD[3] nCCAS F 8.223 4 2.594 M
|
||||
RD[4] nCCAS F 8.223 4 2.594 M
|
||||
RD[5] nCCAS F 8.223 4 2.594 M
|
||||
RD[6] nCCAS F 8.223 4 2.594 M
|
||||
RD[7] nCCAS F 8.223 4 2.594 M
|
||||
nRCAS RCLK R 8.141 4 2.620 M
|
||||
nRCS RCLK R 8.141 4 2.620 M
|
||||
nRRAS RCLK R 8.141 4 2.620 M
|
||||
nRWE RCLK R 8.121 4 2.627 M
|
||||
WARNING: you must also run trce with hold speed: 4
|
||||
WARNING: you must also run trce with hold speed: 6
|
||||
WARNING: you must also run trce with setup speed: M
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
[ActiveSupport TRCE]
|
||||
; Setup Analysis
|
||||
Fmax_0 = 47.556 MHz (2.900 MHz);
|
||||
Fmax_1 = 150.150 MHz (2.900 MHz);
|
||||
Fmax_2 = 150.150 MHz (2.900 MHz);
|
||||
Fmax_3 = 102.312 MHz (62.500 MHz);
|
||||
Failed = 0 (Total 4);
|
||||
Clock_ports = 4;
|
||||
Clock_nets = 4;
|
||||
; Hold Analysis
|
||||
Fmax_0 = - (-);
|
||||
Fmax_1 = - (-);
|
||||
Fmax_2 = - (-);
|
||||
Fmax_3 = - (-);
|
||||
Failed = 0 (Total 4);
|
||||
Clock_ports = 4;
|
||||
Clock_nets = 4;
|
||||
|
|
@ -1,81 +1,81 @@
|
|||
#-- Synopsys, Inc.
|
||||
#-- Version R-2021.03L-SP1
|
||||
#-- Project file D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\run_options.txt
|
||||
#-- Written on Wed Aug 16 20:59:29 2023
|
||||
|
||||
|
||||
#project files
|
||||
add_file -constraint "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS.sdc"
|
||||
add_file -verilog -vlog_std v2001 "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.v"
|
||||
add_file -verilog -vlog_std v2001 "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/REFB.v"
|
||||
|
||||
|
||||
#implementation: "impl1"
|
||||
impl -add impl1 -type fpga
|
||||
|
||||
#
|
||||
#implementation attributes
|
||||
|
||||
set_option -vlog_std v2001
|
||||
set_option -project_relative_includes 1
|
||||
set_option -include_path {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC}
|
||||
|
||||
#device options
|
||||
set_option -technology MACHXO2
|
||||
set_option -part LCMXO2_640HC
|
||||
set_option -package TG100C
|
||||
set_option -speed_grade -4
|
||||
set_option -part_companion ""
|
||||
|
||||
#compilation/mapping options
|
||||
set_option -top_module "RAM2GS"
|
||||
|
||||
# hdl_compiler_options
|
||||
set_option -distributed_compile 0
|
||||
set_option -hdl_strict_syntax 0
|
||||
|
||||
# mapper_without_write_options
|
||||
set_option -frequency 100
|
||||
set_option -srs_instrumentation 1
|
||||
|
||||
# mapper_options
|
||||
set_option -write_verilog 0
|
||||
set_option -write_structural_verilog 0
|
||||
set_option -write_vhdl 0
|
||||
|
||||
# Lattice XP
|
||||
set_option -maxfan 1000
|
||||
set_option -disable_io_insertion 0
|
||||
set_option -retiming 0
|
||||
set_option -pipe 1
|
||||
set_option -forcegsr false
|
||||
set_option -fix_gated_and_generated_clocks 1
|
||||
set_option -rw_check_on_ram 1
|
||||
set_option -update_models_cp 0
|
||||
set_option -syn_edif_array_rename 1
|
||||
set_option -Write_declared_clocks_only 1
|
||||
set_option -seqshift_no_replicate 0
|
||||
|
||||
# NFilter
|
||||
set_option -no_sequential_opt 0
|
||||
|
||||
# sequential_optimization_options
|
||||
set_option -symbolic_fsm_compiler 1
|
||||
|
||||
# Compiler Options
|
||||
set_option -compiler_compatible 0
|
||||
set_option -resource_sharing 1
|
||||
set_option -multi_file_compilation_unit 1
|
||||
|
||||
# Compiler Options
|
||||
set_option -auto_infer_blackbox 0
|
||||
|
||||
#automatic place and route (vendor) options
|
||||
set_option -write_apr_constraint 1
|
||||
|
||||
#set result format/file last
|
||||
project -result_file "./LCMXO2_640HC_impl1.edi"
|
||||
|
||||
#set log file
|
||||
set_option log_file "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.srf"
|
||||
impl -active "impl1"
|
||||
#-- Synopsys, Inc.
|
||||
#-- Version R-2021.03L-SP1
|
||||
#-- Project file Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\run_options.txt
|
||||
#-- Written on Sat Aug 19 21:54:48 2023
|
||||
|
||||
|
||||
#project files
|
||||
add_file -constraint "Y:/Repos/RAM2GS/CPLD/RAM2GS.sdc"
|
||||
add_file -verilog -vlog_std v2001 "Y:/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v"
|
||||
add_file -verilog -vlog_std v2001 "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/REFB.v"
|
||||
|
||||
|
||||
#implementation: "impl1"
|
||||
impl -add impl1 -type fpga
|
||||
|
||||
#
|
||||
#implementation attributes
|
||||
|
||||
set_option -vlog_std v2001
|
||||
set_option -project_relative_includes 1
|
||||
set_option -include_path {Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC}
|
||||
|
||||
#device options
|
||||
set_option -technology MACHXO2
|
||||
set_option -part LCMXO2_640HC
|
||||
set_option -package TG100C
|
||||
set_option -speed_grade -4
|
||||
set_option -part_companion ""
|
||||
|
||||
#compilation/mapping options
|
||||
set_option -top_module "RAM2GS"
|
||||
|
||||
# hdl_compiler_options
|
||||
set_option -distributed_compile 0
|
||||
set_option -hdl_strict_syntax 0
|
||||
|
||||
# mapper_without_write_options
|
||||
set_option -frequency 100
|
||||
set_option -srs_instrumentation 1
|
||||
|
||||
# mapper_options
|
||||
set_option -write_verilog 0
|
||||
set_option -write_structural_verilog 0
|
||||
set_option -write_vhdl 0
|
||||
|
||||
# Lattice XP
|
||||
set_option -maxfan 1000
|
||||
set_option -disable_io_insertion 0
|
||||
set_option -retiming 0
|
||||
set_option -pipe 1
|
||||
set_option -forcegsr false
|
||||
set_option -fix_gated_and_generated_clocks 1
|
||||
set_option -rw_check_on_ram 1
|
||||
set_option -update_models_cp 0
|
||||
set_option -syn_edif_array_rename 1
|
||||
set_option -Write_declared_clocks_only 1
|
||||
set_option -seqshift_no_replicate 0
|
||||
|
||||
# NFilter
|
||||
set_option -no_sequential_opt 0
|
||||
|
||||
# sequential_optimization_options
|
||||
set_option -symbolic_fsm_compiler 1
|
||||
|
||||
# Compiler Options
|
||||
set_option -compiler_compatible 0
|
||||
set_option -resource_sharing 1
|
||||
set_option -multi_file_compilation_unit 1
|
||||
|
||||
# Compiler Options
|
||||
set_option -auto_infer_blackbox 0
|
||||
|
||||
#automatic place and route (vendor) options
|
||||
set_option -write_apr_constraint 1
|
||||
|
||||
#set result format/file last
|
||||
project -result_file "./LCMXO2_640HC_impl1.edi"
|
||||
|
||||
#set log file
|
||||
set_option log_file "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.srf"
|
||||
impl -active "impl1"
|
||||
|
|
|
|||
|
|
@ -1,80 +1,80 @@
|
|||
#-- Synopsys, Inc.
|
||||
#-- Version R-2021.03L-SP1
|
||||
#-- Project file D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\scratchproject.prs
|
||||
|
||||
#project files
|
||||
add_file -constraint "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS.sdc"
|
||||
add_file -verilog -vlog_std v2001 "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.v"
|
||||
add_file -verilog -vlog_std v2001 "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/REFB.v"
|
||||
|
||||
|
||||
#implementation: "impl1"
|
||||
impl -add D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1 -type fpga
|
||||
|
||||
#
|
||||
#implementation attributes
|
||||
|
||||
set_option -vlog_std v2001
|
||||
set_option -project_relative_includes 1
|
||||
set_option -include_path {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/}
|
||||
set_option -include_path {D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC}
|
||||
|
||||
#device options
|
||||
set_option -technology MACHXO2
|
||||
set_option -part LCMXO2_640HC
|
||||
set_option -package TG100C
|
||||
set_option -speed_grade -4
|
||||
set_option -part_companion ""
|
||||
|
||||
#compilation/mapping options
|
||||
set_option -top_module "RAM2GS"
|
||||
|
||||
# hdl_compiler_options
|
||||
set_option -distributed_compile 0
|
||||
set_option -hdl_strict_syntax 0
|
||||
|
||||
# mapper_without_write_options
|
||||
set_option -frequency 100
|
||||
set_option -srs_instrumentation 1
|
||||
|
||||
# mapper_options
|
||||
set_option -write_verilog 0
|
||||
set_option -write_structural_verilog 0
|
||||
set_option -write_vhdl 0
|
||||
|
||||
# Lattice XP
|
||||
set_option -maxfan 1000
|
||||
set_option -disable_io_insertion 0
|
||||
set_option -retiming 0
|
||||
set_option -pipe 1
|
||||
set_option -forcegsr false
|
||||
set_option -fix_gated_and_generated_clocks 1
|
||||
set_option -rw_check_on_ram 1
|
||||
set_option -update_models_cp 0
|
||||
set_option -syn_edif_array_rename 1
|
||||
set_option -Write_declared_clocks_only 1
|
||||
set_option -seqshift_no_replicate 0
|
||||
|
||||
# NFilter
|
||||
set_option -no_sequential_opt 0
|
||||
|
||||
# sequential_optimization_options
|
||||
set_option -symbolic_fsm_compiler 1
|
||||
|
||||
# Compiler Options
|
||||
set_option -compiler_compatible 0
|
||||
set_option -resource_sharing 1
|
||||
set_option -multi_file_compilation_unit 1
|
||||
|
||||
# Compiler Options
|
||||
set_option -auto_infer_blackbox 0
|
||||
|
||||
#automatic place and route (vendor) options
|
||||
set_option -write_apr_constraint 1
|
||||
|
||||
#set result format/file last
|
||||
project -result_file "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.edi"
|
||||
|
||||
#set log file
|
||||
set_option log_file "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.srf"
|
||||
impl -active "impl1"
|
||||
#-- Synopsys, Inc.
|
||||
#-- Version R-2021.03L-SP1
|
||||
#-- Project file Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\scratchproject.prs
|
||||
|
||||
#project files
|
||||
add_file -constraint "Y:/Repos/RAM2GS/CPLD/RAM2GS.sdc"
|
||||
add_file -verilog -vlog_std v2001 "Y:/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v"
|
||||
add_file -verilog -vlog_std v2001 "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/REFB.v"
|
||||
|
||||
|
||||
#implementation: "impl1"
|
||||
impl -add Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1 -type fpga
|
||||
|
||||
#
|
||||
#implementation attributes
|
||||
|
||||
set_option -vlog_std v2001
|
||||
set_option -project_relative_includes 1
|
||||
set_option -include_path {Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/}
|
||||
set_option -include_path {Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC}
|
||||
|
||||
#device options
|
||||
set_option -technology MACHXO2
|
||||
set_option -part LCMXO2_640HC
|
||||
set_option -package TG100C
|
||||
set_option -speed_grade -4
|
||||
set_option -part_companion ""
|
||||
|
||||
#compilation/mapping options
|
||||
set_option -top_module "RAM2GS"
|
||||
|
||||
# hdl_compiler_options
|
||||
set_option -distributed_compile 0
|
||||
set_option -hdl_strict_syntax 0
|
||||
|
||||
# mapper_without_write_options
|
||||
set_option -frequency 100
|
||||
set_option -srs_instrumentation 1
|
||||
|
||||
# mapper_options
|
||||
set_option -write_verilog 0
|
||||
set_option -write_structural_verilog 0
|
||||
set_option -write_vhdl 0
|
||||
|
||||
# Lattice XP
|
||||
set_option -maxfan 1000
|
||||
set_option -disable_io_insertion 0
|
||||
set_option -retiming 0
|
||||
set_option -pipe 1
|
||||
set_option -forcegsr false
|
||||
set_option -fix_gated_and_generated_clocks 1
|
||||
set_option -rw_check_on_ram 1
|
||||
set_option -update_models_cp 0
|
||||
set_option -syn_edif_array_rename 1
|
||||
set_option -Write_declared_clocks_only 1
|
||||
set_option -seqshift_no_replicate 0
|
||||
|
||||
# NFilter
|
||||
set_option -no_sequential_opt 0
|
||||
|
||||
# sequential_optimization_options
|
||||
set_option -symbolic_fsm_compiler 1
|
||||
|
||||
# Compiler Options
|
||||
set_option -compiler_compatible 0
|
||||
set_option -resource_sharing 1
|
||||
set_option -multi_file_compilation_unit 1
|
||||
|
||||
# Compiler Options
|
||||
set_option -auto_infer_blackbox 0
|
||||
|
||||
#automatic place and route (vendor) options
|
||||
set_option -write_apr_constraint 1
|
||||
|
||||
#set result format/file last
|
||||
project -result_file "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.edi"
|
||||
|
||||
#set log file
|
||||
set_option log_file "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.srf"
|
||||
impl -active "impl1"
|
||||
|
|
|
|||
|
|
@ -1,82 +1,89 @@
|
|||
Running in Lattice mode
|
||||
|
||||
Synplify Pro (R)
|
||||
|
||||
Version R-2021.03L-SP1 for win64 - Aug 10, 2021
|
||||
|
||||
Copyright (c) 1988 - 2021 Synopsys, Inc.
|
||||
This software and the associated documentation are proprietary to Synopsys,
|
||||
Inc. This software may only be used in accordance with the terms and conditions
|
||||
of a written license agreement with Synopsys, Inc. All other use, reproduction,
|
||||
or distribution of this software is strictly prohibited.
|
||||
|
||||
Starting: C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe
|
||||
Install: C:\lscc\diamond\3.12\synpbase
|
||||
Hostname: ZANEPC
|
||||
Date: Wed Aug 16 20:59:29 2023
|
||||
Version: R-2021.03L-SP1
|
||||
|
||||
Arguments: -product synplify_pro -batch LCMXO2_640HC_impl1_synplify.tcl
|
||||
ProductType: synplify_pro
|
||||
|
||||
|
||||
|
||||
|
||||
log file: "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr"
|
||||
Running: impl1 in foreground
|
||||
|
||||
Running proj_1|impl1
|
||||
|
||||
Running Flow: compile (Compile) on proj_1|impl1
|
||||
# Wed Aug 16 20:59:29 2023
|
||||
|
||||
Running Flow: compile_flow (Compile Process) on proj_1|impl1
|
||||
# Wed Aug 16 20:59:29 2023
|
||||
|
||||
Running: compiler (Compile Input) on proj_1|impl1
|
||||
# Wed Aug 16 20:59:29 2023
|
||||
|
||||
compiler completed
|
||||
# Wed Aug 16 20:59:30 2023
|
||||
|
||||
Return Code: 0
|
||||
Run Time:00h:00m:01s
|
||||
|
||||
Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
|
||||
# Wed Aug 16 20:59:30 2023
|
||||
Up-To-Date: multi_srs_gen. No run necessary
|
||||
Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
|
||||
Complete: Compile Process on proj_1|impl1
|
||||
|
||||
Running: premap (Premap) on proj_1|impl1
|
||||
# Wed Aug 16 20:59:30 2023
|
||||
|
||||
premap completed with warnings
|
||||
# Wed Aug 16 20:59:32 2023
|
||||
|
||||
Return Code: 1
|
||||
Run Time:00h:00m:02s
|
||||
Complete: Compile on proj_1|impl1
|
||||
|
||||
Running Flow: map (Map) on proj_1|impl1
|
||||
# Wed Aug 16 20:59:32 2023
|
||||
License granted for 4 parallel jobs
|
||||
|
||||
Running: fpga_mapper (Map & Optimize) on proj_1|impl1
|
||||
# Wed Aug 16 20:59:32 2023
|
||||
Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srm
|
||||
|
||||
fpga_mapper completed with warnings
|
||||
# Wed Aug 16 20:59:35 2023
|
||||
|
||||
Return Code: 1
|
||||
Run Time:00h:00m:03s
|
||||
Complete: Map on proj_1|impl1
|
||||
Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
|
||||
Complete: Logic Synthesis on proj_1|impl1
|
||||
TCL script complete: "LCMXO2_640HC_impl1_synplify.tcl"
|
||||
exit status=0
|
||||
exit status=0
|
||||
Save changes for project:
|
||||
D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\proj_1.prj
|
||||
batch mode default:no
|
||||
Running in Lattice mode
|
||||
|
||||
Synplify Pro (R)
|
||||
|
||||
Version R-2021.03L-SP1 for win64 - Aug 10, 2021
|
||||
|
||||
Copyright (c) 1988 - 2021 Synopsys, Inc.
|
||||
This software and the associated documentation are proprietary to Synopsys,
|
||||
Inc. This software may only be used in accordance with the terms and conditions
|
||||
of a written license agreement with Synopsys, Inc. All other use, reproduction,
|
||||
or distribution of this software is strictly prohibited.
|
||||
|
||||
Starting: C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe
|
||||
Install: C:\lscc\diamond\3.12\synpbase
|
||||
Hostname: ZANEMACWIN11
|
||||
Date: Sat Aug 19 21:54:47 2023
|
||||
Version: R-2021.03L-SP1
|
||||
|
||||
Arguments: -product synplify_pro -batch LCMXO2_640HC_impl1_synplify.tcl
|
||||
ProductType: synplify_pro
|
||||
|
||||
|
||||
|
||||
|
||||
log file: "Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr"
|
||||
Running: impl1 in foreground
|
||||
|
||||
Running proj_1|impl1
|
||||
|
||||
Running Flow: compile (Compile) on proj_1|impl1
|
||||
# Sat Aug 19 21:54:48 2023
|
||||
|
||||
Running Flow: compile_flow (Compile Process) on proj_1|impl1
|
||||
# Sat Aug 19 21:54:48 2023
|
||||
|
||||
Running: compiler (Compile Input) on proj_1|impl1
|
||||
# Sat Aug 19 21:54:48 2023
|
||||
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.srs to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
|
||||
|
||||
compiler completed
|
||||
# Sat Aug 19 21:54:49 2023
|
||||
|
||||
Return Code: 0
|
||||
Run Time:00h:00m:01s
|
||||
|
||||
Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
|
||||
# Sat Aug 19 21:54:49 2023
|
||||
|
||||
multi_srs_gen completed
|
||||
# Sat Aug 19 21:54:50 2023
|
||||
|
||||
Return Code: 0
|
||||
Run Time:00h:00m:01s
|
||||
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_mult.srs to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
|
||||
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
|
||||
Complete: Compile Process on proj_1|impl1
|
||||
|
||||
Running: premap (Premap) on proj_1|impl1
|
||||
# Sat Aug 19 21:54:50 2023
|
||||
|
||||
premap completed with warnings
|
||||
# Sat Aug 19 21:54:51 2023
|
||||
|
||||
Return Code: 1
|
||||
Run Time:00h:00m:01s
|
||||
Complete: Compile on proj_1|impl1
|
||||
|
||||
Running Flow: map (Map) on proj_1|impl1
|
||||
# Sat Aug 19 21:54:51 2023
|
||||
License granted for 4 parallel jobs
|
||||
|
||||
Running: fpga_mapper (Map & Optimize) on proj_1|impl1
|
||||
# Sat Aug 19 21:54:51 2023
|
||||
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srm
|
||||
|
||||
fpga_mapper completed with warnings
|
||||
# Sat Aug 19 21:54:55 2023
|
||||
|
||||
Return Code: 1
|
||||
Run Time:00h:00m:04s
|
||||
Complete: Map on proj_1|impl1
|
||||
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
|
||||
Complete: Logic Synthesis on proj_1|impl1
|
||||
TCL script complete: "LCMXO2_640HC_impl1_synplify.tcl"
|
||||
exit status=0
|
||||
exit status=0
|
||||
Save changes for project:
|
||||
Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\proj_1.prj
|
||||
batch mode default:no
|
||||
|
|
|
|||
|
|
@ -1,89 +1,89 @@
|
|||
Running in Lattice mode
|
||||
|
||||
Synplify Pro (R)
|
||||
|
||||
Version R-2021.03L-SP1 for win64 - Aug 10, 2021
|
||||
|
||||
Copyright (c) 1988 - 2021 Synopsys, Inc.
|
||||
This software and the associated documentation are proprietary to Synopsys,
|
||||
Inc. This software may only be used in accordance with the terms and conditions
|
||||
of a written license agreement with Synopsys, Inc. All other use, reproduction,
|
||||
or distribution of this software is strictly prohibited.
|
||||
|
||||
Starting: C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe
|
||||
Install: C:\lscc\diamond\3.12\synpbase
|
||||
Hostname: ZANEPC
|
||||
Date: Wed Aug 16 20:57:40 2023
|
||||
Version: R-2021.03L-SP1
|
||||
|
||||
Arguments: -product synplify_pro -batch LCMXO2_640HC_impl1_synplify.tcl
|
||||
ProductType: synplify_pro
|
||||
|
||||
|
||||
|
||||
|
||||
log file: "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr"
|
||||
Running: impl1 in foreground
|
||||
|
||||
Running proj_1|impl1
|
||||
|
||||
Running Flow: compile (Compile) on proj_1|impl1
|
||||
# Wed Aug 16 20:57:40 2023
|
||||
|
||||
Running Flow: compile_flow (Compile Process) on proj_1|impl1
|
||||
# Wed Aug 16 20:57:40 2023
|
||||
|
||||
Running: compiler (Compile Input) on proj_1|impl1
|
||||
# Wed Aug 16 20:57:40 2023
|
||||
Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.srs to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
|
||||
|
||||
compiler completed
|
||||
# Wed Aug 16 20:57:43 2023
|
||||
|
||||
Return Code: 0
|
||||
Run Time:00h:00m:03s
|
||||
|
||||
Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
|
||||
# Wed Aug 16 20:57:43 2023
|
||||
|
||||
multi_srs_gen completed
|
||||
# Wed Aug 16 20:57:43 2023
|
||||
|
||||
Return Code: 0
|
||||
Run Time:00h:00m:00s
|
||||
Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_mult.srs to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
|
||||
Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
|
||||
Complete: Compile Process on proj_1|impl1
|
||||
|
||||
Running: premap (Premap) on proj_1|impl1
|
||||
# Wed Aug 16 20:57:43 2023
|
||||
|
||||
premap completed with warnings
|
||||
# Wed Aug 16 20:57:45 2023
|
||||
|
||||
Return Code: 1
|
||||
Run Time:00h:00m:02s
|
||||
Complete: Compile on proj_1|impl1
|
||||
|
||||
Running Flow: map (Map) on proj_1|impl1
|
||||
# Wed Aug 16 20:57:45 2023
|
||||
License granted for 4 parallel jobs
|
||||
|
||||
Running: fpga_mapper (Map & Optimize) on proj_1|impl1
|
||||
# Wed Aug 16 20:57:45 2023
|
||||
Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srm
|
||||
|
||||
fpga_mapper completed with warnings
|
||||
# Wed Aug 16 20:57:49 2023
|
||||
|
||||
Return Code: 1
|
||||
Run Time:00h:00m:04s
|
||||
Complete: Map on proj_1|impl1
|
||||
Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
|
||||
Complete: Logic Synthesis on proj_1|impl1
|
||||
TCL script complete: "LCMXO2_640HC_impl1_synplify.tcl"
|
||||
exit status=0
|
||||
exit status=0
|
||||
Save changes for project:
|
||||
D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\proj_1.prj
|
||||
batch mode default:no
|
||||
Running in Lattice mode
|
||||
|
||||
Synplify Pro (R)
|
||||
|
||||
Version R-2021.03L-SP1 for win64 - Aug 10, 2021
|
||||
|
||||
Copyright (c) 1988 - 2021 Synopsys, Inc.
|
||||
This software and the associated documentation are proprietary to Synopsys,
|
||||
Inc. This software may only be used in accordance with the terms and conditions
|
||||
of a written license agreement with Synopsys, Inc. All other use, reproduction,
|
||||
or distribution of this software is strictly prohibited.
|
||||
|
||||
Starting: C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe
|
||||
Install: C:\lscc\diamond\3.12\synpbase
|
||||
Hostname: ZANEMACWIN11
|
||||
Date: Sat Aug 19 07:28:27 2023
|
||||
Version: R-2021.03L-SP1
|
||||
|
||||
Arguments: -product synplify_pro -batch LCMXO2_640HC_impl1_synplify.tcl
|
||||
ProductType: synplify_pro
|
||||
|
||||
|
||||
|
||||
|
||||
log file: "Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr"
|
||||
Running: impl1 in foreground
|
||||
|
||||
Running proj_1|impl1
|
||||
|
||||
Running Flow: compile (Compile) on proj_1|impl1
|
||||
# Sat Aug 19 07:28:28 2023
|
||||
|
||||
Running Flow: compile_flow (Compile Process) on proj_1|impl1
|
||||
# Sat Aug 19 07:28:28 2023
|
||||
|
||||
Running: compiler (Compile Input) on proj_1|impl1
|
||||
# Sat Aug 19 07:28:28 2023
|
||||
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.srs to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
|
||||
|
||||
compiler completed
|
||||
# Sat Aug 19 07:28:29 2023
|
||||
|
||||
Return Code: 0
|
||||
Run Time:00h:00m:01s
|
||||
|
||||
Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
|
||||
# Sat Aug 19 07:28:29 2023
|
||||
|
||||
multi_srs_gen completed
|
||||
# Sat Aug 19 07:28:29 2023
|
||||
|
||||
Return Code: 0
|
||||
Run Time:00h:00m:00s
|
||||
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_mult.srs to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
|
||||
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
|
||||
Complete: Compile Process on proj_1|impl1
|
||||
|
||||
Running: premap (Premap) on proj_1|impl1
|
||||
# Sat Aug 19 07:28:29 2023
|
||||
|
||||
premap completed with warnings
|
||||
# Sat Aug 19 07:28:31 2023
|
||||
|
||||
Return Code: 1
|
||||
Run Time:00h:00m:02s
|
||||
Complete: Compile on proj_1|impl1
|
||||
|
||||
Running Flow: map (Map) on proj_1|impl1
|
||||
# Sat Aug 19 07:28:31 2023
|
||||
License granted for 4 parallel jobs
|
||||
|
||||
Running: fpga_mapper (Map & Optimize) on proj_1|impl1
|
||||
# Sat Aug 19 07:28:31 2023
|
||||
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srm
|
||||
|
||||
fpga_mapper completed with warnings
|
||||
# Sat Aug 19 07:28:34 2023
|
||||
|
||||
Return Code: 1
|
||||
Run Time:00h:00m:03s
|
||||
Complete: Map on proj_1|impl1
|
||||
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
|
||||
Complete: Logic Synthesis on proj_1|impl1
|
||||
TCL script complete: "LCMXO2_640HC_impl1_synplify.tcl"
|
||||
exit status=0
|
||||
exit status=0
|
||||
Save changes for project:
|
||||
Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\proj_1.prj
|
||||
batch mode default:no
|
||||
|
|
|
|||
|
|
@ -1,59 +1,89 @@
|
|||
Running in Lattice mode
|
||||
|
||||
Synplify Pro (R)
|
||||
|
||||
Version R-2021.03L-SP1 for win64 - Aug 10, 2021
|
||||
|
||||
Copyright (c) 1988 - 2021 Synopsys, Inc.
|
||||
This software and the associated documentation are proprietary to Synopsys,
|
||||
Inc. This software may only be used in accordance with the terms and conditions
|
||||
of a written license agreement with Synopsys, Inc. All other use, reproduction,
|
||||
or distribution of this software is strictly prohibited.
|
||||
|
||||
Starting: C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe
|
||||
Install: C:\lscc\diamond\3.12\synpbase
|
||||
Hostname: ZANEPC
|
||||
Date: Wed Aug 16 20:52:48 2023
|
||||
Version: R-2021.03L-SP1
|
||||
|
||||
Arguments: -product synplify_pro -batch LCMXO2_640HC_impl1_synplify.tcl
|
||||
ProductType: synplify_pro
|
||||
|
||||
|
||||
|
||||
|
||||
log file: "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr"
|
||||
Running: impl1 in foreground
|
||||
|
||||
Running proj_1|impl1
|
||||
|
||||
Running Flow: compile (Compile) on proj_1|impl1
|
||||
# Wed Aug 16 20:52:48 2023
|
||||
|
||||
Running Flow: compile_flow (Compile Process) on proj_1|impl1
|
||||
# Wed Aug 16 20:52:48 2023
|
||||
|
||||
Running: compiler (Compile Input) on proj_1|impl1
|
||||
# Wed Aug 16 20:52:48 2023
|
||||
compiler exited with errors
|
||||
Job failed on: proj_1|impl1
|
||||
|
||||
Job: "compiler" terminated with error status: 2
|
||||
See log file: "D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synlog\LCMXO2_640HC_impl1_compiler.srr"
|
||||
# Wed Aug 16 20:52:49 2023
|
||||
|
||||
Return Code: 2
|
||||
Run Time:00h:00m:01s
|
||||
Complete: Compile Process on proj_1|impl1
|
||||
Complete: Compile on proj_1|impl1
|
||||
Complete: Logic Synthesis on proj_1|impl1
|
||||
Copied D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
|
||||
Error: At line 65 while processing "LCMXO2_640HC_impl1_synplify.tcl"
|
||||
2
|
||||
TCL script complete: "LCMXO2_640HC_impl1_synplify.tcl"
|
||||
TCL script had errors: "LCMXO2_640HC_impl1_synplify.tcl"
|
||||
exit status=9
|
||||
exit status=9
|
||||
Save changes for project:
|
||||
D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\proj_1.prj
|
||||
batch mode default:no
|
||||
Running in Lattice mode
|
||||
|
||||
Synplify Pro (R)
|
||||
|
||||
Version R-2021.03L-SP1 for win64 - Aug 10, 2021
|
||||
|
||||
Copyright (c) 1988 - 2021 Synopsys, Inc.
|
||||
This software and the associated documentation are proprietary to Synopsys,
|
||||
Inc. This software may only be used in accordance with the terms and conditions
|
||||
of a written license agreement with Synopsys, Inc. All other use, reproduction,
|
||||
or distribution of this software is strictly prohibited.
|
||||
|
||||
Starting: C:\lscc\diamond\3.12\synpbase\bin64\mbin\synbatch.exe
|
||||
Install: C:\lscc\diamond\3.12\synpbase
|
||||
Hostname: ZANEMACWIN11
|
||||
Date: Sat Aug 19 07:27:36 2023
|
||||
Version: R-2021.03L-SP1
|
||||
|
||||
Arguments: -product synplify_pro -batch LCMXO2_640HC_impl1_synplify.tcl
|
||||
ProductType: synplify_pro
|
||||
|
||||
|
||||
|
||||
|
||||
log file: "Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr"
|
||||
Running: impl1 in foreground
|
||||
|
||||
Running proj_1|impl1
|
||||
|
||||
Running Flow: compile (Compile) on proj_1|impl1
|
||||
# Sat Aug 19 07:27:37 2023
|
||||
|
||||
Running Flow: compile_flow (Compile Process) on proj_1|impl1
|
||||
# Sat Aug 19 07:27:37 2023
|
||||
|
||||
Running: compiler (Compile Input) on proj_1|impl1
|
||||
# Sat Aug 19 07:27:37 2023
|
||||
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_comp.srs to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
|
||||
|
||||
compiler completed
|
||||
# Sat Aug 19 07:27:38 2023
|
||||
|
||||
Return Code: 0
|
||||
Run Time:00h:00m:01s
|
||||
|
||||
Running: multi_srs_gen (Multi-srs Generator) on proj_1|impl1
|
||||
# Sat Aug 19 07:27:38 2023
|
||||
|
||||
multi_srs_gen completed
|
||||
# Sat Aug 19 07:27:38 2023
|
||||
|
||||
Return Code: 0
|
||||
Run Time:00h:00m:00s
|
||||
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_mult.srs to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srs
|
||||
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
|
||||
Complete: Compile Process on proj_1|impl1
|
||||
|
||||
Running: premap (Premap) on proj_1|impl1
|
||||
# Sat Aug 19 07:27:38 2023
|
||||
|
||||
premap completed with warnings
|
||||
# Sat Aug 19 07:27:40 2023
|
||||
|
||||
Return Code: 1
|
||||
Run Time:00h:00m:02s
|
||||
Complete: Compile on proj_1|impl1
|
||||
|
||||
Running Flow: map (Map) on proj_1|impl1
|
||||
# Sat Aug 19 07:27:40 2023
|
||||
License granted for 4 parallel jobs
|
||||
|
||||
Running: fpga_mapper (Map & Optimize) on proj_1|impl1
|
||||
# Sat Aug 19 07:27:40 2023
|
||||
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\LCMXO2_640HC_impl1_m.srm to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srm
|
||||
|
||||
fpga_mapper completed with warnings
|
||||
# Sat Aug 19 07:27:43 2023
|
||||
|
||||
Return Code: 1
|
||||
Run Time:00h:00m:03s
|
||||
Complete: Map on proj_1|impl1
|
||||
Copied Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srr to Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\LCMXO2_640HC_impl1.srf
|
||||
Complete: Logic Synthesis on proj_1|impl1
|
||||
TCL script complete: "LCMXO2_640HC_impl1_synplify.tcl"
|
||||
exit status=0
|
||||
exit status=0
|
||||
Save changes for project:
|
||||
Y:\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\proj_1.prj
|
||||
batch mode default:no
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue