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This commit is contained in:
Zane Kaminski
2022-02-06 23:40:30 -05:00
parent ef01c01e6b
commit 7ffe55abe2
40 changed files with 1900 additions and 2220 deletions
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CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcl.html
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@@ -29,6 +29,34 @@ prj_run Export -impl impl1 -forceAll
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC_tcr.dir/pn211010064144.tcr
+6
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@@ -0,0 +1,6 @@
#Start recording tcl command: 10/9/2021 01:18:46
#Project Location: C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
prj_project open "C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf"
prj_run Map -impl impl1 -forceAll
prj_run PAR -impl impl1 -forceAll
#Stop recording: 10/10/2021 06:41:44
CPLD/LCMXO2/LCMXO2-640HC/impl1/.build_status
+21 -21
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@@ -2,26 +2,26 @@
<BuildStatus>
<Strategy name="Strategy1">
<Milestone name="Export" build_result="0" build_time="0">
<Task name="IBIS" build_result="0" update_result="2" update_time="1629195665"/>
<Task name="IBIS" build_result="0" update_result="2" update_time="1633756763"/>
<Task name="TimingSimFileVlg" build_result="0" update_result="3" update_time="0"/>
<Task name="TimingSimFileVHD" build_result="0" update_result="3" update_time="0"/>
<Task name="Bitgen" build_result="2" update_result="0" update_time="1629195667"/>
<Task name="Jedecgen" build_result="2" update_result="0" update_time="1629195669"/>
<Task name="Bitgen" build_result="0" update_result="2" update_time="1633756763"/>
<Task name="Jedecgen" build_result="0" update_result="2" update_time="1633756763"/>
</Milestone>
<Milestone name="Map" build_result="2" build_time="1629195651">
<Task name="Map" build_result="2" update_result="0" update_time="1629195651"/>
<Task name="MapTrace" build_result="2" update_result="0" update_time="1629195651"/>
<Milestone name="Map" build_result="2" build_time="1633756755">
<Task name="Map" build_result="2" update_result="0" update_time="1633756755"/>
<Task name="MapTrace" build_result="2" update_result="0" update_time="1633756755"/>
<Task name="MapVerilogSimFile" build_result="0" update_result="3" update_time="0"/>
<Task name="MapVHDLSimFile" build_result="0" update_result="3" update_time="0"/>
</Milestone>
<Milestone name="PAR" build_result="2" build_time="1629195661">
<Task name="PAR" build_result="2" update_result="0" update_time="1629195661"/>
<Task name="PARTrace" build_result="2" update_result="0" update_time="1629195661"/>
<Task name="IOTiming" build_result="2" update_result="0" update_time="1629195663"/>
<Milestone name="PAR" build_result="2" build_time="1633756763">
<Task name="PAR" build_result="2" update_result="0" update_time="1633756763"/>
<Task name="PARTrace" build_result="2" update_result="0" update_time="1633756764"/>
<Task name="IOTiming" build_result="2" update_result="0" update_time="1633756765"/>
</Milestone>
<Milestone name="Synthesis" build_result="2" build_time="1629195586">
<Task name="Lattice_Synthesis" build_result="2" update_result="0" update_time="1629195586"/>
<Task name="LSE_Compile" build_result="2" update_result="0" update_time="1629195585"/>
<Milestone name="Synthesis" build_result="2" build_time="1633756754">
<Task name="Lattice_Synthesis" build_result="2" update_result="0" update_time="1633756754"/>
<Task name="LSE_Compile" build_result="2" update_result="0" update_time="1633756753"/>
</Milestone>
<Milestone name="TOOL_Report" build_result="0" build_time="0">
<Task name="HDLE" build_result="2" update_result="0" update_time="1629194861"/>
@@ -30,17 +30,17 @@
<Task name="PIODRC" build_result="0" update_result="3" update_time="0"/>
<Task name="DEC" build_result="0" update_result="3" update_time="0"/>
</Milestone>
<Report name=".vdbs/RAM2GS_LCMXO2_640HC_impl1_map.vdb" last_build_time="1629195651" last_build_size="90359"/>
<Report name=".vdbs/RAM2GS_LCMXO2_640HC_impl1_map.vdb" last_build_time="1633756755" last_build_size="91027"/>
<Report name="IBIS/RAM2GS_LCMXO2_640HC_impl1.ibs" last_build_time="0" last_build_size="0"/>
<Report name="RAM2GS_LCMXO2_640HC_impl1.bgn" last_build_time="1629195669" last_build_size="4441"/>
<Report name="RAM2GS_LCMXO2_640HC_impl1.bit" last_build_time="1629195667" last_build_size="6667"/>
<Report name="RAM2GS_LCMXO2_640HC_impl1.ior" last_build_time="1629195663" last_build_size="6533"/>
<Report name="RAM2GS_LCMXO2_640HC_impl1.ior" last_build_time="1633756765" last_build_size="6451"/>
<Report name="RAM2GS_LCMXO2_640HC_impl1.jed" last_build_time="1629195669" last_build_size="177066"/>
<Report name="RAM2GS_LCMXO2_640HC_impl1.lsedata" last_build_time="1629195585" last_build_size="407682"/>
<Report name="RAM2GS_LCMXO2_640HC_impl1.ncd" last_build_time="1629195661" last_build_size="302666"/>
<Report name="RAM2GS_LCMXO2_640HC_impl1.ngd" last_build_time="1629195586" last_build_size="234541"/>
<Report name="RAM2GS_LCMXO2_640HC_impl1.tw1" last_build_time="1629195651" last_build_size="113451"/>
<Report name="RAM2GS_LCMXO2_640HC_impl1.twr" last_build_time="1629195661" last_build_size="194524"/>
<Report name="RAM2GS_LCMXO2_640HC_impl1_map.ncd" last_build_time="1629195650" last_build_size="212106"/>
<Report name="RAM2GS_LCMXO2_640HC_impl1.lsedata" last_build_time="1633756753" last_build_size="407682"/>
<Report name="RAM2GS_LCMXO2_640HC_impl1.ncd" last_build_time="1633756763" last_build_size="302666"/>
<Report name="RAM2GS_LCMXO2_640HC_impl1.ngd" last_build_time="1633756754" last_build_size="234541"/>
<Report name="RAM2GS_LCMXO2_640HC_impl1.tw1" last_build_time="1633756755" last_build_size="113287"/>
<Report name="RAM2GS_LCMXO2_640HC_impl1.twr" last_build_time="1633756764" last_build_size="194360"/>
<Report name="RAM2GS_LCMXO2_640HC_impl1_map.ncd" last_build_time="1633756755" last_build_size="212106"/>
</Strategy>
</BuildStatus>
CPLD/LCMXO2/LCMXO2-640HC/impl1/.vdbs/RAM2GS_LCMXO2_640HC_impl1_map.vdb
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CPLD/LCMXO2/LCMXO2-640HC/impl1/.vdbs/RAM2GS_rtl.vdb
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CPLD/LCMXO2/LCMXO2-640HC/impl1/.vdbs/RAM2GS_tech.vdb
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CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd
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CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.pad
+2 -2
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@@ -6,7 +6,7 @@ Performance Grade: 4
PACKAGE: TQFP100
Package Status: Final Version 1.39
Tue Aug 17 06:20:57 2021
Sat Oct 09 01:19:20 2021
Pinout by Port Name:
+-----------+----------+--------------+-------+-----------+-----------+------------------------------------------------------------+
@@ -269,5 +269,5 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Tue Aug 17 06:20:59 2021
Sat Oct 09 01:19:22 2021
CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/5_1.par
+28 -28
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@@ -1,9 +1,9 @@
Lattice Place and Route Report for Design "RAM2GS_LCMXO2_640HC_impl1_map.ncd"
Tue Aug 17 06:20:51 2021
Sat Oct 09 01:19:16 2021
PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
Placement level-cost: 5-1.
Routing Iterations: 6
@@ -58,12 +58,12 @@ Finished Placer Phase 0. REAL time: 0 secs
Starting Placer Phase 1.
....................
Placer score = 65362.
Finished Placer Phase 1. REAL time: 6 secs
Finished Placer Phase 1. REAL time: 4 secs
Starting Placer Phase 2.
.
Placer score = 65089
Finished Placer Phase 2. REAL time: 6 secs
Finished Placer Phase 2. REAL time: 4 secs
------------------ Clock Report ------------------
@@ -102,7 +102,7 @@ I/O Bank Usage Summary:
| 3 | 18 / 20 ( 90%) | 3.3V | - |
+----------+----------------+------------+-----------+
Total placer CPU time: 5 secs
Total placer CPU time: 4 secs
Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
@@ -115,9 +115,9 @@ WARNING - par: The driver of primary clock net nCCAS_c is not placed on one of t
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
Signal=wb_clk loads=1 clock_loads=1
Completed router resource preassignment. Real time: 8 secs
Completed router resource preassignment. Real time: 6 secs
Start NBR router at 06:20:59 08/17/21
Start NBR router at 01:19:22 10/09/21
*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
@@ -132,53 +132,53 @@ Note: NBR uses a different method to calculate timing slacks. The
your design.
*****************************************************************
Start NBR special constraint process at 06:20:59 08/17/21
Start NBR special constraint process at 01:19:22 10/09/21
Start NBR section for initial routing at 06:20:59 08/17/21
Start NBR section for initial routing at 01:19:22 10/09/21
Level 1, iteration 1
0(0.00%) conflict; 980(86.65%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.167ns/0.000ns; real time: 8 secs
Estimated worst slack/total negative slack<setup>: 1.167ns/0.000ns; real time: 6 secs
Level 2, iteration 1
1(0.00%) conflict; 970(85.76%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.141ns/0.000ns; real time: 9 secs
Estimated worst slack/total negative slack<setup>: 1.141ns/0.000ns; real time: 6 secs
Level 3, iteration 1
1(0.00%) conflict; 904(79.93%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 6 secs
Level 4, iteration 1
26(0.06%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 6 secs
Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area at 75% usage is 0 (0.00%)
Start NBR section for normal routing at 06:21:00 08/17/21
Start NBR section for normal routing at 01:19:22 10/09/21
Level 1, iteration 1
1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 6 secs
Level 2, iteration 1
1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 6 secs
Level 3, iteration 1
1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 7 secs
Level 4, iteration 1
12(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 7 secs
Level 4, iteration 2
5(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 7 secs
Level 4, iteration 3
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 7 secs
Start NBR section for setup/hold timing optimization with effort level 3 at 06:21:00 08/17/21
Start NBR section for setup/hold timing optimization with effort level 3 at 01:19:23 10/09/21
Start NBR section for re-routing at 06:21:00 08/17/21
Start NBR section for re-routing at 01:19:23 10/09/21
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 7 secs
Start NBR section for post-routing at 06:21:00 08/17/21
Start NBR section for post-routing at 01:19:23 10/09/21
End NBR router with 0 unrouted connection
@@ -196,8 +196,8 @@ Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
Signal=wb_clk loads=1 clock_loads=1
Total CPU time 9 secs
Total REAL time: 10 secs
Total CPU time 7 secs
Total REAL time: 7 secs
Completely routed.
End of route. 1131 routed (100.00%); 0 unrouted.
@@ -219,8 +219,8 @@ PAR_SUMMARY::Worst slack<hold /<ns>> = 0.304
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
PAR_SUMMARY::Number of errors = 0
Total CPU time to completion: 9 secs
Total REAL time to completion: 10 secs
Total CPU time to completion: 7 secs
Total REAL time to completion: 7 secs
par done!
CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.dir/RAM2GS_LCMXO2_640HC_impl1.par
+4 -5
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@@ -4,12 +4,11 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Tue Aug 17 06:20:51 2021
Sat Oct 09 01:19:16 2021
C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_640HC_impl1.p2t
RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir
RAM2GS_LCMXO2_640HC_impl1.prf -gui -msgset
C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml
RAM2GS_LCMXO2_640HC_impl1.prf -gui
Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
@@ -17,11 +16,11 @@ Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
Level/ Number Worst Timing Worst Timing Run NCD
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
---------- -------- ----- ------ ----------- ----------- ---- ------
5_1 * 0 1.135 0 0.304 0 10 Completed
5_1 * 0 1.135 0 0.304 0 07 Completed
* : Design saved.
Total (real) run time for 1-seed: 10 secs
Total (real) run time for 1-seed: 7 secs
par done!
CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.lsedata
+2 -2
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@@ -1,9 +1,9 @@
<top name = "RAM2GS" library = "work" arch = "" entry = "Verilog">
<clocks>
<clockitem name = "PHI2" type = "port" />
<clockitem name = "nCCAS" type = "port" />
<clockitem name = "nCRAS" type = "port" />
<clockitem name = "nCCAS" type = "port" />
<clockitem name = "PHI2" type = "port" />
<clockitem name = "RCLK" type = "port" />
<clockitem name = "wb_clk" type = "net" />
</clocks>
CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.mrp
+16 -16
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@@ -8,15 +8,14 @@ Design Information
Command line: map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial
RAM2GS_LCMXO2_640HC_impl1.ngd -o RAM2GS_LCMXO2_640HC_impl1_map.ncd -pr
RAM2GS_LCMXO2_640HC_impl1.prf -mp RAM2GS_LCMXO2_640HC_impl1.mrp -lpf C:/Use
rs/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2
_640HC_impl1.lpf -lpf C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMX
O2-640HC/RAM2GS_LCMXO2_640HC.lpf -c 0 -gui -msgset
C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml
rs/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMX
O2_640HC_impl1.lpf -lpf C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/
LCMXO2-640HC/RAM2GS_LCMXO2_640HC.lpf -c 0 -gui
Target Vendor: LATTICE
Target Device: LCMXO2-640HCTQFP100
Target Performance: 4
Mapper: xo2c00, version: Diamond (64-bit) 3.12.0.240.2
Mapped on: 08/17/21 06:20:50
Mapped on: 10/09/21 01:19:14
Design Summary
--------------
@@ -60,17 +59,17 @@ Design Summary
Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
Number of Clock Enables: 14
Net RCLK_c_enable_27: 8 loads, 8 LSLICEs
Net RCLK_c_enable_20: 4 loads, 4 LSLICEs
Page 1
Design: RAM2GS Date: 08/17/21 06:20:50
Design: RAM2GS Date: 10/09/21 01:19:14
Design Summary (cont)
---------------------
Net RCLK_c_enable_20: 4 loads, 4 LSLICEs
Net RCLK_c_enable_29: 2 loads, 2 LSLICEs
Net RCLK_c_enable_25: 2 loads, 2 LSLICEs
Net InitReady: 1 loads, 1 LSLICEs
@@ -126,17 +125,17 @@ IO (PIO) Attributes
+---------------------+-----------+-----------+------------+
| RCLK | INPUT | LVTTL33 | |
+---------------------+-----------+-----------+------------+
| nFWE | INPUT | LVTTL33 | |
Page 2
Design: RAM2GS Date: 08/17/21 06:20:50
Design: RAM2GS Date: 10/09/21 01:19:14
IO (PIO) Attributes (cont)
--------------------------
| nFWE | INPUT | LVTTL33 | |
+---------------------+-----------+-----------+------------+
| nCRAS | INPUT | LVTTL33 | |
+---------------------+-----------+-----------+------------+
@@ -192,17 +191,17 @@ IO (PIO) Attributes (cont)
+---------------------+-----------+-----------+------------+
| nRRAS | OUTPUT | LVTTL33 | |
+---------------------+-----------+-----------+------------+
| nRWE | OUTPUT | LVTTL33 | |
Page 3
Design: RAM2GS Date: 08/17/21 06:20:50
Design: RAM2GS Date: 10/09/21 01:19:14
IO (PIO) Attributes (cont)
--------------------------
| nRWE | OUTPUT | LVTTL33 | |
+---------------------+-----------+-----------+------------+
| RCKE | OUTPUT | LVTTL33 | |
+---------------------+-----------+-----------+------------+
@@ -258,17 +257,17 @@ IO (PIO) Attributes (cont)
+---------------------+-----------+-----------+------------+
| RD[1] | BIDIR | LVTTL33 | |
+---------------------+-----------+-----------+------------+
| RD[2] | BIDIR | LVTTL33 | |
Page 4
Design: RAM2GS Date: 08/17/21 06:20:50
Design: RAM2GS Date: 10/09/21 01:19:14
IO (PIO) Attributes (cont)
--------------------------
| RD[2] | BIDIR | LVTTL33 | |
+---------------------+-----------+-----------+------------+
| RD[3] | BIDIR | LVTTL33 | |
+---------------------+-----------+-----------+------------+
@@ -324,17 +323,17 @@ Embedded Functional Block Connection Summary
PLL0 Connection: DISABLED
PLL1 Connection: DISABLED
I2C Function Summary:
--------------------
Page 5
Design: RAM2GS Date: 08/17/21 06:20:50
Design: RAM2GS Date: 10/09/21 01:19:14
Embedded Functional Block Connection Summary (cont)
---------------------------------------------------
--------------------
None
SPI Function Summary:
--------------------
@@ -366,7 +365,7 @@ Run Time and Memory Usage
Total CPU Time: 0 secs
Total REAL Time: 0 secs
Peak Memory Usage: 36 MB
Peak Memory Usage: 37 MB
@@ -389,6 +388,7 @@ Run Time and Memory Usage
Page 6
CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.ncd
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CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.ngd
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CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.pad
+2 -2
View File
@@ -6,7 +6,7 @@ Performance Grade: 4
PACKAGE: TQFP100
Package Status: Final Version 1.39
Tue Aug 17 06:20:57 2021
Sat Oct 09 01:19:20 2021
Pinout by Port Name:
+-----------+----------+--------------+-------+-----------+-----------+------------------------------------------------------------+
@@ -269,5 +269,5 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Tue Aug 17 06:20:59 2021
Sat Oct 09 01:19:22 2021
CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.par
+32 -33
View File
@@ -4,12 +4,11 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Tue Aug 17 06:20:51 2021
Sat Oct 09 01:19:16 2021
C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_640HC_impl1.p2t
RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir
RAM2GS_LCMXO2_640HC_impl1.prf -gui -msgset
C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml
RAM2GS_LCMXO2_640HC_impl1.prf -gui
Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
@@ -17,21 +16,21 @@ Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
Level/ Number Worst Timing Worst Timing Run NCD
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
---------- -------- ----- ------ ----------- ----------- ---- ------
5_1 * 0 1.135 0 0.304 0 10 Completed
5_1 * 0 1.135 0 0.304 0 07 Completed
* : Design saved.
Total (real) run time for 1-seed: 10 secs
Total (real) run time for 1-seed: 7 secs
par done!
Note: user must run 'Trace' for timing closure signoff.
Lattice Place and Route Report for Design "RAM2GS_LCMXO2_640HC_impl1_map.ncd"
Tue Aug 17 06:20:51 2021
Sat Oct 09 01:19:16 2021
PAR: Place And Route Diamond (64-bit) 3.12.0.240.2.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
Placement level-cost: 5-1.
Routing Iterations: 6
@@ -86,12 +85,12 @@ Finished Placer Phase 0. REAL time: 0 secs
Starting Placer Phase 1.
....................
Placer score = 65362.
Finished Placer Phase 1. REAL time: 6 secs
Finished Placer Phase 1. REAL time: 4 secs
Starting Placer Phase 2.
.
Placer score = 65089
Finished Placer Phase 2. REAL time: 6 secs
Finished Placer Phase 2. REAL time: 4 secs
------------------ Clock Report ------------------
@@ -130,7 +129,7 @@ I/O Bank Usage Summary:
| 3 | 18 / 20 ( 90%) | 3.3V | - |
+----------+----------------+------------+-----------+
Total placer CPU time: 5 secs
Total placer CPU time: 4 secs
Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
@@ -143,9 +142,9 @@ WARNING - par: The driver of primary clock net nCCAS_c is not placed on one of t
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
Signal=wb_clk loads=1 clock_loads=1
Completed router resource preassignment. Real time: 8 secs
Completed router resource preassignment. Real time: 6 secs
Start NBR router at 06:20:59 08/17/21
Start NBR router at 01:19:22 10/09/21
*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
@@ -160,53 +159,53 @@ Note: NBR uses a different method to calculate timing slacks. The
your design.
*****************************************************************
Start NBR special constraint process at 06:20:59 08/17/21
Start NBR special constraint process at 01:19:22 10/09/21
Start NBR section for initial routing at 06:20:59 08/17/21
Start NBR section for initial routing at 01:19:22 10/09/21
Level 1, iteration 1
0(0.00%) conflict; 980(86.65%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.167ns/0.000ns; real time: 8 secs
Estimated worst slack/total negative slack<setup>: 1.167ns/0.000ns; real time: 6 secs
Level 2, iteration 1
1(0.00%) conflict; 970(85.76%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.141ns/0.000ns; real time: 9 secs
Estimated worst slack/total negative slack<setup>: 1.141ns/0.000ns; real time: 6 secs
Level 3, iteration 1
1(0.00%) conflict; 904(79.93%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 6 secs
Level 4, iteration 1
26(0.06%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 6 secs
Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area at 75% usage is 0 (0.00%)
Start NBR section for normal routing at 06:21:00 08/17/21
Start NBR section for normal routing at 01:19:22 10/09/21
Level 1, iteration 1
1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 6 secs
Level 2, iteration 1
1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 6 secs
Level 3, iteration 1
1(0.00%) conflict; 28(2.48%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 7 secs
Level 4, iteration 1
12(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 7 secs
Level 4, iteration 2
5(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 7 secs
Level 4, iteration 3
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 7 secs
Start NBR section for setup/hold timing optimization with effort level 3 at 06:21:00 08/17/21
Start NBR section for setup/hold timing optimization with effort level 3 at 01:19:23 10/09/21
Start NBR section for re-routing at 06:21:00 08/17/21
Start NBR section for re-routing at 01:19:23 10/09/21
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 9 secs
Estimated worst slack/total negative slack<setup>: 1.135ns/0.000ns; real time: 7 secs
Start NBR section for post-routing at 06:21:00 08/17/21
Start NBR section for post-routing at 01:19:23 10/09/21
End NBR router with 0 unrouted connection
@@ -224,8 +223,8 @@ Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
Signal=wb_clk loads=1 clock_loads=1
Total CPU time 9 secs
Total REAL time: 10 secs
Total CPU time 7 secs
Total REAL time: 7 secs
Completely routed.
End of route. 1131 routed (100.00%); 0 unrouted.
@@ -247,8 +246,8 @@ PAR_SUMMARY::Worst slack<hold /<ns>> = 0.304
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
PAR_SUMMARY::Number of errors = 0
Total CPU time to completion: 9 secs
Total REAL time to completion: 10 secs
Total CPU time to completion: 7 secs
Total REAL time to completion: 7 secs
par done!
CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.prf
+1 -1
View File
@@ -1,5 +1,5 @@
SCHEMATIC START ;
# map: version Diamond (64-bit) 3.12.0.240.2 -- WARNING: Map write only section -- Tue Aug 17 06:20:50 2021
# map: version Diamond (64-bit) 3.12.0.240.2 -- WARNING: Map write only section -- Sat Oct 09 01:19:15 2021
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
LOCATE COMP "RCLK" SITE "63" ;
CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.tw1
+4 -4
View File
@@ -13,7 +13,7 @@ Setup and Hold Report
--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
Tue Aug 17 06:20:51 2021
Sat Oct 09 01:19:15 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
@@ -23,7 +23,7 @@ Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf
Design file: ram2gs_lcmxo2_640hc_impl1_map.ncd
Preference file: ram2gs_lcmxo2_640hc_impl1.prf
Device,speed: LCMXO2-640HC,4
@@ -1302,7 +1302,7 @@ Constraints cover 1548 paths, 9 nets, and 889 connections (78.60% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
Tue Aug 17 06:20:51 2021
Sat Oct 09 01:19:15 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
@@ -1312,7 +1312,7 @@ Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_640HC_impl1.tw1 -gui RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.prf
Design file: ram2gs_lcmxo2_640hc_impl1_map.ncd
Preference file: ram2gs_lcmxo2_640hc_impl1.prf
Device,speed: LCMXO2-640HC,M
CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1.twr
+4 -4
View File
@@ -13,7 +13,7 @@ Setup and Hold Report
--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
Tue Aug 17 06:21:01 2021
Sat Oct 09 01:19:23 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
@@ -23,7 +23,7 @@ Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
Design file: ram2gs_lcmxo2_640hc_impl1.ncd
Preference file: ram2gs_lcmxo2_640hc_impl1.prf
Device,speed: LCMXO2-640HC,4
@@ -2376,7 +2376,7 @@ Constraints cover 1548 paths, 9 nets, and 900 connections (79.58% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
Tue Aug 17 06:21:01 2021
Sat Oct 09 01:19:24 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
@@ -2386,7 +2386,7 @@ Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
Design file: ram2gs_lcmxo2_640hc_impl1.ncd
Preference file: ram2gs_lcmxo2_640hc_impl1.prf
Device,speed: LCMXO2-640HC,m
CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_iotiming.html
+2 -2
View File
@@ -38,9 +38,9 @@ Performance Hardware Data Status: Final Version 34.4.
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
border-collapse: collapse;
}
th {
font-weight:bold;
CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_lattice.synproj
+3 -3
View File
@@ -30,12 +30,12 @@
-lpf 1
-p "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC"
-ver "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v"
-p "C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC"
-ver "C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v"
-top RAM2GS
-p "C:/lscc/diamond/3.12/ispfpga/xo2c00/data" "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1" "C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC"
-p "C:/lscc/diamond/3.12/ispfpga/xo2c00/data" "C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1" "C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC"
-ngd "RAM2GS_LCMXO2_640HC_impl1.ngd"
CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.cam
+1 -1
View File
@@ -16,7 +16,7 @@ FS_972_add_4_19/CO
[ END CLIPPED ]
[ START DESIGN PREFS ]
SCHEMATIC START ;
# map: version Diamond (64-bit) 3.12.0.240.2 -- WARNING: Map write only section -- Tue Aug 17 06:20:50 2021
# map: version Diamond (64-bit) 3.12.0.240.2 -- WARNING: Map write only section -- Sat Oct 09 01:19:15 2021
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
LOCATE COMP "RCLK" SITE "63" ;
CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_map.ncd
BIN
View File
Binary file not shown.
CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_mrp.html
+11 -11
View File
@@ -16,15 +16,14 @@
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
font-size: 0.80em;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
@@ -67,8 +66,8 @@ Mapped on: 08/17/21 06:20:50
}
a:visited {
}
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
@@ -127,8 +126,8 @@ Mapped on: 08/17/21 06:20:50
Number of PIO sites used: 63 + 4(JTAG) out of 79 (85%)
Number of block RAMs: 0 out of 2 (0%)
Number of GSRs: 0 out of 1 (0%)
EFB used : Yes
EFB used : Yes
JTAG used : No
Readback used : No
Oscillator used : No
Startup used : No
@@ -184,8 +183,8 @@ Mapped on: 08/17/21 06:20:50
Net FS_8: 23 loads
Net FS_5: 21 loads
Net FS_6: 21 loads
Net FS_12: 20 loads
Net FS_12: 20 loads
Net Ready: 18 loads
@@ -241,8 +240,8 @@ Mapped on: 08/17/21 06:20:50
| MAin[0] | INPUT | LVTTL33 | |
+---------------------+-----------+-----------+------------+
| MAin[1] | INPUT | LVTTL33 | |
+---------------------+-----------+-----------+------------+
+---------------------+-----------+-----------+------------+
| MAin[2] | INPUT | LVTTL33 | |
+---------------------+-----------+-----------+------------+
| MAin[3] | INPUT | LVTTL33 | |
+---------------------+-----------+-----------+------------+
@@ -300,8 +299,8 @@ Block i1 was optimized away.
| RA[11] | OUTPUT | LVTTL33 | |
+---------------------+-----------+-----------+------------+
| RBA[0] | OUTPUT | LVTTL33 | |
+---------------------+-----------+-----------+------------+
+---------------------+-----------+-----------+------------+
| RBA[1] | OUTPUT | LVTTL33 | |
+---------------------+-----------+-----------+------------+
| LED | OUTPUT | LVTTL33 | |
+---------------------+-----------+-----------+------------+
@@ -337,7 +336,7 @@ Instance Name: ufmefb
| RD[6] | BIDIR | LVTTL33 | |
+---------------------+-----------+-----------+------------+
| RD[7] | BIDIR | LVTTL33 | |
+---------------------+-----------+-----------+------------+
+---------------------+-----------+-----------+------------+
@@ -362,6 +361,7 @@ Instance Name: ufmefb
Block InitReady_I_0_586_1_lut_rep_73 was optimized away.
Block i1683_1_lut was optimized away.
Block i1044_1_lut_rep_86 was optimized away.
Block i1684_1_lut_rep_84 was optimized away.
Block i1 was optimized away.
CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_pad.html
+2 -2
View File
@@ -14,7 +14,7 @@ Performance Grade: 4
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
@@ -278,7 +278,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
+----------+--------------------+--------------------+----------+-------------+-------------------+
| PT7D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP |
| PT7C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down |
| PT7B | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP |
| PT7B | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP |
| PT7A | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP |
+----------+--------------------+--------------------+----------+-------------+-------------------+
CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_par.html
+32 -33
View File
@@ -12,12 +12,11 @@ Copyright (c) 1995 AT&amp;T Corp. All rights reserved.
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
@@ -26,22 +25,22 @@ Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
p {
}
p {
font-size:78%;
P.Table {
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
{
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
}
border-collapse: collapse;
}
th {
font-weight:bold;
@@ -97,12 +96,12 @@ Finished Placer Phase 0. REAL time: 0 secs
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Sat Oct 09 01:19:16 2021
C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_640HC_impl1.p2t
RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir
RAM2GS_LCMXO2_640HC_impl1.prf -gui
Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
@@ -142,7 +141,7 @@ I/O Bank Usage Summary:
Performance Hardware Data Status: Final Version 34.4.
License checked out.
Ignore Preference Error(s): True
<A name="par_dus"></A><B><U><big>Device utilization summary:</big></U></B>
@@ -155,9 +154,9 @@ WARNING - par: The driver of primary clock net nCCAS_c is not placed on one of t
EFB 1/1 100% used
Number of Signals: 401
Number of Signals: 401
Number of Connections: 1131
Pin Constraint Summary:
63 out of 63 pins locked (100% locked).
@@ -172,53 +171,53 @@ Note: NBR uses a different method to calculate timing slacks. The
WARNING - par: Signal &quot;nCCAS_c&quot; is selected to use Primary clock resources. However, its driver comp &quot;nCCAS&quot; is located at &quot;9&quot;, which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
No signal is selected as secondary clock.
No signal is selected as Global Set/Reset.
Starting Placer Phase 0.
Starting Placer Phase 0.
............
Finished Placer Phase 0. REAL time: 0 secs
Starting Placer Phase 1.
....................
Placer score = 65362.
Placer score = 65362.
Finished Placer Phase 1. REAL time: 4 secs
Starting Placer Phase 2.
Starting Placer Phase 2.
.
Placer score = 65089
Finished Placer Phase 2. REAL time: 6 secs
Finished Placer Phase 2. REAL time: 4 secs
<A name="par_clk"></A><B><U><big>Clock Report</big></U></B>
Global Clock Resources:
CLK_PIN : 1 out of 8 (12%)
General PIO: 3 out of 80 (3%)
General PIO: 3 out of 80 (3%)
DCM : 0 out of 2 (0%)
DCC : 0 out of 8 (0%)
Global Clocks:
PRIMARY &quot;RCLK_c&quot; from comp &quot;RCLK&quot; on CLK_PIN site &quot;63 (PR5C)&quot;, clk load = 52
PRIMARY &quot;PHI2_c&quot; from comp &quot;PHI2&quot; on PIO site &quot;8 (PL3B)&quot;, clk load = 13
PRIMARY &quot;PHI2_c&quot; from comp &quot;PHI2&quot; on PIO site &quot;8 (PL3B)&quot;, clk load = 13
PRIMARY &quot;nCRAS_c&quot; from comp &quot;nCRAS&quot; on PIO site &quot;17 (PL6B)&quot;, clk load = 7
PRIMARY &quot;nCCAS_c&quot; from comp &quot;nCCAS&quot; on PIO site &quot;9 (PL3C)&quot;, clk load = 4
PRIMARY : 4 out of 8 (50%)
SECONDARY: 0 out of 8 (0%)
I/O Usage Summary (final):
63 + 4(JTAG) out of 80 (83.8%) PIO sites used.
63 + 4(JTAG) out of 80 (83.8%) PIO sites used.
63 + 4(JTAG) out of 79 (84.8%) bonded PIO sites used.
Number of PIO comps: 63; differential: 0.
Number of PIO comps: 63; differential: 0.
Number of Vref pins used: 0.
I/O Bank Usage Summary:
I/O Bank Usage Summary:
+----------+----------------+------------+-----------+
| I/O Bank | Usage | Bank Vccio | Bank Vref |
| I/O Bank | Usage | Bank Vccio | Bank Vref |
+----------+----------------+------------+-----------+
| 0 | 13 / 19 ( 68%) | 3.3V | - |
| 1 | 20 / 20 (100%) | 3.3V | - |
@@ -236,8 +235,8 @@ Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored
WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
WARNING - par: The driver of primary clock net nCCAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
Signal=wb_clk loads=1 clock_loads=1
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
Signal=wb_clk loads=1 clock_loads=1
Completed router resource preassignment. Real time: 6 secs
@@ -259,8 +258,8 @@ PAR_SUMMARY::Worst slack&lt;hold /&lt;ns&gt;&gt; = 0.304
Start NBR special constraint process at 01:19:22 10/09/21
Start NBR section for initial routing at 01:19:22 10/09/21
Level 1, iteration 1
0(0.00%) conflict; 980(86.65%) untouched conns; 0 (nbr) score;
Level 1, iteration 1
0(0.00%) conflict; 980(86.65%) untouched conns; 0 (nbr) score;
Estimated worst slack/total negative slack&lt;setup&gt;: 1.167ns/0.000ns; real time: 6 secs
Level 2, iteration 1
1(0.00%) conflict; 970(85.76%) untouched conns; 0 (nbr) score;
CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_summary.html
+4 -4
View File
@@ -24,7 +24,7 @@
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
font-size: 0.80em;
}
p {
font-size:78%;
@@ -62,15 +62,15 @@
}
a {
color:#013C9A;
text-decoration:none;
text-decoration:none;
}
a:visited {
color:#013C9A;
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
text-decoration:underline;
color:#5BAFD4;
}
.pass
CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_tw1.html
+4 -4
View File
@@ -22,7 +22,7 @@ Setup and Hold Report
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
@@ -32,7 +32,7 @@ Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
@@ -1395,7 +1395,7 @@ Constraints cover 1548 paths, 9 nets, and 889 connections (78.60% coverage)
CLOCK_TO_OUT PORT "RDQML" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 9.886 ns| 3
| | |
CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns | | |
CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns | | |
@@ -1405,7 +1405,7 @@ Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_twr.html
+4 -4
View File
@@ -22,7 +22,7 @@ Setup and Hold Report
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
@@ -32,7 +32,7 @@ Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
@@ -2469,7 +2469,7 @@ Constraints cover 1548 paths, 9 nets, and 900 connections (79.58% coverage)
CLOCK_TO_OUT PORT "RDQML" 12.500000 ns | | |
CLKPORT "RCLK" ; | 12.500 ns| 10.641 ns| 3
| | |
CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns | | |
CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns | | |
@@ -2479,7 +2479,7 @@ Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_lse.twr
+2 -2
View File
@@ -1,6 +1,6 @@
--------------------------------------------------------------------------------
Lattice Synthesis Timing Report, Version
Tue Aug 17 06:19:46 2021
Sat Oct 09 01:19:14 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
@@ -331,5 +331,5 @@ Timing errors: 1272 Score: 5951146
Constraints cover 1577 paths, 335 nets, and 954 connections (77.9% coverage)
Peak memory: 59748352 bytes, TRCE: 3297280 bytes, DLYMAN: 0 bytes
Peak memory: 60768256 bytes, TRCE: 3186688 bytes, DLYMAN: 0 bytes
CPU_TIME_REPORT: 0 secs
CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_lse_lsetwr.html
+223 -225
View File
@@ -9,7 +9,7 @@
background-color: #ffffff;
}
h1 {
font-weight: bold;
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
@@ -27,248 +27,272 @@ Report level: verbose report, limited to 3 items per constraint
font-size: 0.80em;
}
p {
font-size:78%;
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
-->
</STYLE>
</HEAD>
<PRE><A name="Map_Twr"></A><B><U><big>Lattice Synthesis Timing Report</big></U></B>
--------------------------------------------------------------------------------
Lattice Synthesis Timing Report, Version
Sat Oct 09 01:19:14 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
<A name="mtw1_ri"></A><B><U><big>Report Information</big></U></B>
------------------
Design: RAM2GS
Constraint file:
Report level: verbose report, limited to 3 items per constraint
--------------------------------------------------------------------------------
================================================================================
Constraint: create_clock -period 5.000000 -name clk3 [get_nets PHI2_c]
130 items scored, 125 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path violates requirements by 10.606ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1S3AX CK Bank_i4 (from PHI2_c +)
Destination: FD1P3AX SP CmdLEDEN_545 (to PHI2_c -)
Delay: 12.821ns (30.4% logic, 69.6% route), 8 logic levels.
Constraint Details:
12.821ns data_path Bank_i4 to CmdLEDEN_545 violates
2.500ns delay constraint less
0.285ns LCE_S requirement (totaling 2.215ns) by 10.606ns
Path Details: Bank_i4 to CmdLEDEN_545
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.444 CK to Q Bank_i4 (from PHI2_c)
Route 1 e 0.941 Bank[4]
LUT4 --- 0.493 C to Z i3734_4_lut
Route 1 e 0.941 n4610
LUT4 --- 0.493 B to Z i3751_4_lut
Route 2 e 1.141 n4628
LUT4 --- 0.493 B to Z i13_4_lut_adj_13
Route 4 e 1.340 n2384
LUT4 --- 0.493 B to Z i3712_2_lut_rep_40
Route 2 e 1.141 n4889
LUT4 --- 0.493 D to Z i3_4_lut_adj_23
Route 4 e 1.340 XOR8MEG_N_149
LUT4 --- 0.493 D to Z i2_3_lut_rep_33_4_lut
Route 1 e 0.941 n4882
LUT4 --- 0.493 A to Z i1_3_lut_adj_21
Route 2 e 1.141 PHI2_N_151_enable_5
--------
12.821 (30.4% logic, 69.6% route), 8 logic levels.
Error: The following path violates requirements by 10.606ns
margin-left: 4px;
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1S3AX CK Bank_i4 (from PHI2_c +)
Destination: FD1P3AX SP Cmdn8MEGEN_546 (to PHI2_c -)
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
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a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
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.pass
{
background-color: #00ff00;
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.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
-->
</STYLE>
</HEAD>
<PRE><A name="Map_Twr"></A><B><U><big>Lattice Synthesis Timing Report</big></U></B>
--------------------------------------------------------------------------------
Lattice Synthesis Timing Report, Version
Tue Aug 17 05:43:37 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
<A name="mtw1_ri"></A><B><U><big>Report Information</big></U></B>
------------------
Design: RAM2GS
Constraint file:
Report level: verbose report, limited to 3 items per constraint
--------------------------------------------------------------------------------
================================================================================
Constraint: create_clock -period 5.000000 -name clk3 [get_nets nCCAS_c]
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCRAS_c]
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Constraint: create_clock -period 5.000000 -name clk1 [get_nets PHI2_c]
120 items scored, 116 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path violates requirements by 10.528ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1S3AX CK Bank_i1 (from PHI2_c +)
Destination: FD1P3AX SP CmdEnable_541 (to PHI2_c -)
Delay: 12.743ns (30.6% logic, 69.4% route), 8 logic levels.
Constraint Details:
12.743ns data_path Bank_i1 to CmdEnable_541 violates
2.500ns delay constraint less
0.285ns LCE_S requirement (totaling 2.215ns) by 10.528ns
Path Details: Bank_i1 to CmdEnable_541
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.444 CK to Q Bank_i1 (from PHI2_c)
Route 2 e 1.198 Bank[1]
LUT4 --- 0.493 B to Z i1819_2_lut
Route 1 e 0.941 n2427
LUT4 --- 0.493 C to Z i1857_4_lut
Route 1 e 0.941 n2465
LUT4 --- 0.493 A to Z i13_4_lut_adj_4
Route 5 e 1.405 n1712
LUT4 --- 0.493 A to Z i1_2_lut_rep_12
Route 2 e 1.141 n2551
LUT4 --- 0.493 D to Z i1827_4_lut
Route 1 e 0.941 n2435
LUT4 --- 0.493 B to Z i3_4_lut_adj_1
Route 4 e 1.340 C1Submitted_N_200
LUT4 --- 0.493 C to Z i34_4_lut
Delay: 12.821ns (30.4% logic, 69.6% route), 8 logic levels.
12.743 (30.6% logic, 69.4% route), 8 logic levels.
Constraint Details:
12.821ns data_path Bank_i4 to Cmdn8MEGEN_546 violates
2.500ns delay constraint less
0.285ns LCE_S requirement (totaling 2.215ns) by 10.606ns
Path Details: Bank_i4 to Cmdn8MEGEN_546
Destination: FD1P3AX SP CmdEnable_541 (to PHI2_c -)
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.444 CK to Q Bank_i4 (from PHI2_c)
Route 1 e 0.941 Bank[4]
LUT4 --- 0.493 C to Z i3734_4_lut
Route 1 e 0.941 n4610
LUT4 --- 0.493 B to Z i3751_4_lut
Route 2 e 1.141 n4628
2.500ns delay constraint less
LUT4 --- 0.493 B to Z i13_4_lut_adj_13
Route 4 e 1.340 n2384
LUT4 --- 0.493 B to Z i3712_2_lut_rep_40
Route 2 e 1.141 n4889
LUT4 --- 0.493 D to Z i3_4_lut_adj_23
Route 4 e 1.340 XOR8MEG_N_149
LUT4 --- 0.493 D to Z i2_3_lut_rep_33_4_lut
Route 1 e 0.941 Bank[3]
LUT4 --- 0.493 B to Z i1799_2_lut
Route 2 e 1.141 n2407
LUT4 --- 0.493 A to Z i1857_4_lut
Route 1 e 0.941 n2465
LUT4 --- 0.493 A to Z i13_4_lut_adj_4
Route 5 e 1.405 n1712
LUT4 --- 0.493 A to Z i1_2_lut_rep_12
Route 2 e 1.141 n2551
LUT4 --- 0.493 D to Z i1827_4_lut
Route 1 e 0.941 n2435
LUT4 --- 0.493 B to Z i3_4_lut_adj_1
Route 1 e 0.941 n4882
LUT4 --- 0.493 A to Z i1_3_lut_adj_21
Route 2 e 1.141 PHI2_N_151_enable_5
--------
12.821 (30.4% logic, 69.6% route), 8 logic levels.
Error: The following path violates requirements by 10.606ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1S3AX CK Bank_i5 (from PHI2_c +)
Destination: FD1P3AX SP CmdLEDEN_545 (to PHI2_c -)
Delay: 12.821ns (30.4% logic, 69.6% route), 8 logic levels.
Constraint Details:
12.821ns data_path Bank_i5 to CmdLEDEN_545 violates
2.500ns delay constraint less
0.285ns LCE_S requirement (totaling 2.215ns) by 10.606ns
LUT4 --- 0.493 C to Z i34_4_lut
Path Details: Bank_i5 to CmdLEDEN_545
12.686 (30.7% logic, 69.3% route), 8 logic levels.
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.444 CK to Q Bank_i5 (from PHI2_c)
Route 1 e 0.941 Bank[5]
LUT4 --- 0.493 B to Z i3734_4_lut
Logical Details: Cell type Pin type Cell name (clock net +/-)
Route 1 e 0.941 n4610
LUT4 --- 0.493 B to Z i3751_4_lut
Route 2 e 1.141 n4628
Source: FD1S3AX CK Bank_i6 (from PHI2_c +)
LUT4 --- 0.493 B to Z i13_4_lut_adj_13
Route 4 e 1.340 n2384
LUT4 --- 0.493 B to Z i3712_2_lut_rep_40
Route 2 e 1.141 n4889
LUT4 --- 0.493 D to Z i3_4_lut_adj_23
Route 4 e 1.340 XOR8MEG_N_149
LUT4 --- 0.493 D to Z i2_3_lut_rep_33_4_lut
Route 1 e 0.941 n4882
2.500ns delay constraint less
LUT4 --- 0.493 A to Z i1_3_lut_adj_21
Route 2 e 1.141 PHI2_N_151_enable_5
--------
Path Details: Bank_i6 to CmdEnable_541
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.444 CK to Q Bank_i6 (from PHI2_c)
Route 1 e 0.941 Bank[6]
LUT4 --- 0.493 A to Z i1799_2_lut
Route 2 e 1.141 n2407
LUT4 --- 0.493 A to Z i1857_4_lut
Route 1 e 0.941 n2465
LUT4 --- 0.493 A to Z i13_4_lut_adj_4
Route 5 e 1.405 n1712
LUT4 --- 0.493 A to Z i1_2_lut_rep_12
12.821 (30.4% logic, 69.6% route), 8 logic levels.
Warning: 13.106 ns is the maximum delay for this constraint.
================================================================================
Constraint: create_clock -period 5.000000 -name clk2 [get_nets nCCAS_c]
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Constraint: create_clock -period 5.000000 -name clk1 [get_nets nCRAS_c]
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c]
1392 items scored, 1147 timing errors detected.
LUT4 --- 0.493 D to Z i1827_4_lut
--------------------------------------------------------------------------------
Route 4 e 1.340 C1Submitted_N_200
Error: The following path violates requirements by 10.222ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
12.686 (30.7% logic, 69.3% route), 8 logic levels.
Source: FD1S3AX CK FS_972__i8 (from RCLK_c +)
Destination: FD1S3AX D wb_adr_i4 (to RCLK_c +)
Delay: 15.062ns (30.7% logic, 69.3% route), 10 logic levels.
Constraint Details:
Constraint: create_clock -period 5.000000 -name clk0 [get_nets RCLK_c]
15.062ns data_path FS_972__i8 to wb_adr_i4 violates
5.000ns delay constraint less
--------------------------------------------------------------------------------
0.160ns L_S requirement (totaling 4.840ns) by 10.222ns
Path Details: FS_972__i8 to wb_adr_i4
Name Fanout Delay (ns) Pins Resource(Cell.Net)
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1S3AX CK FS_725__i9 (from RCLK_c +)
Destination: FD1P3IX SP n8MEGEN_557 (to RCLK_c +)
Delay: 7.948ns (33.3% logic, 66.7% route), 6 logic levels.
Constraint Details:
7.948ns data_path FS_725__i9 to n8MEGEN_557 violates
5.000ns delay constraint less
0.285ns LCE_S requirement (totaling 4.715ns) by 3.233ns
L_CO --- 0.444 CK to Q FS_972__i8 (from RCLK_c)
Route 23 e 1.894 FS[8]
LUT4 --- 0.493 B to Z i1_2_lut_rep_75
Route 4 e 1.340 n4924
LUT4 --- 0.493 B to Z i2387_3_lut_4_lut
Route 1 e 0.941 n98
LUT4 --- 0.493 D to Z i1_3_lut_4_lut_adj_9
Route 2 e 1.141 n2199
LUT4 --- 0.493 B to Z i92_4_lut
Route 1 e 0.941 n53
LUT4 --- 0.493 C to Z i3106_3_lut_3_lut
Route 1 e 0.020 n1_adj_6
MUXL5 --- 0.233 ALUT to Z i29
Route 1 e 0.941 n14_adj_3
LUT4 --- 0.493 C to Z i1_2_lut_2_lut_3_lut
Route 2 e 1.141 n12_adj_8
LUT4 --- 0.493 C to Z i1_3_lut_4_lut_adj_11
Route 2 e 1.141 n14_adj_7
LUT4 --- 0.493 A to Z i28_3_lut
Route 1 e 0.941 wb_adr_7__N_60[4]
--------
Path Details: FS_725__i9 to n8MEGEN_557
15.062 (30.7% logic, 69.3% route), 10 logic levels.
Name Fanout Delay (ns) Pins Resource(Cell.Net)
Error: The following path violates requirements by 10.222ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
@@ -278,16 +302,16 @@ Constraint | Constraint| Actual|Levels
Delay: 15.062ns (30.7% logic, 69.3% route), 10 logic levels.
Route 1 e 0.020 n2385
Constraint Details:
15.062ns data_path FS_972__i8 to wb_adr_i6 violates
--------
5.000ns delay constraint less
0.160ns L_S requirement (totaling 4.840ns) by 10.222ns
Path Details: FS_972__i8 to wb_adr_i6
Name Fanout Delay (ns) Pins Resource(Cell.Net)
Logical Details: Cell type Pin type Cell name (clock net +/-)
L_CO --- 0.444 CK to Q FS_972__i8 (from RCLK_c)
Route 23 e 1.894 FS[8]
LUT4 --- 0.493 B to Z i1_2_lut_rep_75
Route 4 e 1.340 n4924
@@ -297,39 +321,13 @@ clk0 [get_nets RCLK_c] | 5.000 ns| 8.233 ns| 6 *
Route 2 e 1.141 n2199
LUT4 --- 0.493 B to Z i92_4_lut
Route 1 e 0.941 n53
5.000ns delay constraint less
LUT4 --- 0.493 C to Z i3106_3_lut_3_lut
Route 1 e 0.020 n1_adj_6
MUXL5 --- 0.233 ALUT to Z i29
Route 1 e 0.941 n14_adj_3
LUT4 --- 0.493 C to Z i1_2_lut_2_lut_3_lut
Route 2 e 1.141 n12_adj_8
L_CO --- 0.444 CK to Q FS_725__i9 (from RCLK_c)
Route 3 e 1.315 FS[9]
LUT4 --- 0.493 A to Z i1847_4_lut
Route 1 e 0.941 n2455
LUT4 --- 0.493 B to Z i1855_4_lut
Route 1 e 0.941 n2463
LUT4 --- 0.493 B to Z i14_4_lut
Route 1 e 0.941 n2384
LUT4 --- 0.493 D to Z i3_4_lut_adj_13
Route 1 e 0.020 n2385
MUXL5 --- 0.233 BLUT to Z i26
Route 2 e 1.141 RCLK_c_enable_10
--------
7.948 (33.3% logic, 66.7% route), 6 logic levels.
Error: The following path violates requirements by 3.233ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1S3AX CK FS_725__i8 (from RCLK_c +)
Destination: FD1P3IX SP n8MEGEN_557 (to RCLK_c +)
Delay: 7.948ns (33.3% logic, 66.7% route), 6 logic levels.
Constraint Details:
LUT4 --- 0.493 C to Z i1_3_lut_4_lut_adj_11
Route 2 e 1.141 n14_adj_7
LUT4 --- 0.493 A to Z i29_3_lut
Route 1 e 0.941 wb_adr_7__N_60[6]
@@ -337,12 +335,12 @@ n2453 | 2| 28| 10.22%
15.062 (30.7% logic, 69.3% route), 10 logic levels.
L_CO --- 0.444 CK to Q FS_725__i8 (from RCLK_c)
Error: The following path violates requirements by 10.216ns
LUT4 --- 0.493 B to Z i1821_2_lut
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1S3AX CK FS_972__i6 (from RCLK_c +)
Route 1 e 0.941 n2463
Destination: FD1S3AX D wb_adr_i4 (to RCLK_c +)
Delay: 15.056ns (30.7% logic, 69.3% route), 10 logic levels.
CPLD/LCMXO2/LCMXO2-640HC/impl1/RAM2GS_prim.v
+387 -387
View File
File diff suppressed because it is too large Load Diff
CPLD/LCMXO2/LCMXO2-640HC/impl1/automake.log
+324 -686
View File
File diff suppressed because it is too large Load Diff
CPLD/LCMXO2/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html
+6 -6
View File
File diff suppressed because one or more lines are too long
CPLD/LCMXO2/LCMXO2-640HC/impl1/ram2gs_lcmxo2_640hc_impl1.ior
+2 -2
View File
@@ -29,9 +29,9 @@ Performance Hardware Data Status: Final Version 34.4.
// Package: TQFP100
// ncd File: ram2gs_lcmxo2_640hc_impl1.ncd
// Version: Diamond (64-bit) 3.12.0.240.2
// Written on Tue Aug 17 06:21:03 2021
// Written on Sat Oct 09 01:19:25 2021
// M: Minimum Performance Grade
// iotiming RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml
// iotiming RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf -gui
I/O Timing Report (All units are in ns)
CPLD/LCMXO2/LCMXO2-640HC/impl1/synthesis.log
+14 -14
View File
@@ -5,10 +5,10 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Tue Aug 17 06:19:45 2021
Sat Oct 09 01:19:13 2021
Command Line: synthesis -f RAM2GS_LCMXO2_640HC_impl1_lattice.synproj -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml
Command Line: synthesis -f RAM2GS_LCMXO2_640HC_impl1_lattice.synproj -gui
Synthesis options:
The -a option is MachXO2.
@@ -61,11 +61,11 @@ ROM style = auto
RAM style = auto
The -comp option is FALSE.
The -syn option is FALSE.
-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC (searchpath added)
-p C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC (searchpath added)
-p C:/lscc/diamond/3.12/ispfpga/xo2c00/data (searchpath added)
-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1 (searchpath added)
-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC (searchpath added)
Verilog design file = C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v
-p C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1 (searchpath added)
-p C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC (searchpath added)
Verilog design file = C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v
NGD file = RAM2GS_LCMXO2_640HC_impl1.ngd
-sdc option: SDC file input not used.
-lpf option: Output file option is ON.
@@ -76,15 +76,15 @@ Technology check ok...
Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
Compile design.
Compile Design Begin
Analyzing Verilog file c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v. VERI-1482
Analyzing Verilog file c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v. VERI-1482
Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
Top module name (Verilog): RAM2GS
INFO - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(1): compiling module RAM2GS. VERI-1018
WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(123): expression size 32 truncated to fit in target size 2. VERI-1209
WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128): expression size 32 truncated to fit in target size 18. VERI-1209
WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255): expression size 32 truncated to fit in target size 4. VERI-1209
INFO - synthesis: c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(1): compiling module RAM2GS. VERI-1018
WARNING - synthesis: c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(123): expression size 32 truncated to fit in target size 2. VERI-1209
WARNING - synthesis: c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128): expression size 32 truncated to fit in target size 18. VERI-1209
WARNING - synthesis: c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255): expression size 32 truncated to fit in target size 4. VERI-1209
INFO - synthesis: C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1800): compiling module EFB. VERI-1018
WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(348): input port PLL0DATI7 is not connected on this instance. VDB-1013
WARNING - synthesis: c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(348): input port PLL0DATI7 is not connected on this instance. VDB-1013
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
@@ -264,8 +264,8 @@ clk0 [get_nets RCLK_c] | 200.000 MHz| 65.694 MHz| 10 *
2 constraints not met.
Peak Memory Usage: 57.273 MB
Peak Memory Usage: 58.262 MB
--------------------------------------------------------------
Elapsed CPU time for LSE flow : 0.952 secs
Elapsed CPU time for LSE flow : 0.813 secs
--------------------------------------------------------------
CPLD/LCMXO2/LCMXO2-640HC/impl1/synthesis_lse.html
+14 -14
View File
@@ -14,10 +14,10 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Tue Aug 17 06:19:45 2021
Sat Oct 09 01:19:13 2021
Command Line: synthesis -f RAM2GS_LCMXO2_640HC_impl1_lattice.synproj -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/promote.xml
Command Line: synthesis -f RAM2GS_LCMXO2_640HC_impl1_lattice.synproj -gui
Synthesis options:
The -a option is MachXO2.
@@ -70,11 +70,11 @@ ROM style = auto
RAM style = auto
The -comp option is FALSE.
The -syn option is FALSE.
-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC (searchpath added)
-p C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC (searchpath added)
-p C:/lscc/diamond/3.12/ispfpga/xo2c00/data (searchpath added)
-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1 (searchpath added)
-p C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC (searchpath added)
Verilog design file = C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v
-p C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC/impl1 (searchpath added)
-p C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/LCMXO2-640HC (searchpath added)
Verilog design file = C:/Users/zanek/Documents/GitHub/RAM2GS/CPLD/LCMXO2/RAM2GS-LCMXO2.v
NGD file = RAM2GS_LCMXO2_640HC_impl1.ngd
-sdc option: SDC file input not used.
-lpf option: Output file option is ON.
@@ -85,15 +85,15 @@ Technology check ok...
Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
Compile design.
Compile Design Begin
Analyzing Verilog file c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v. VERI-1482
Analyzing Verilog file c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v. VERI-1482
Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
Top module name (Verilog): RAM2GS
INFO - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(1): compiling module RAM2GS. VERI-1018
WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(123): expression size 32 truncated to fit in target size 2. VERI-1209
WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128): expression size 32 truncated to fit in target size 18. VERI-1209
WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255): expression size 32 truncated to fit in target size 4. VERI-1209
INFO - synthesis: c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(1): compiling module RAM2GS. VERI-1018
WARNING - synthesis: c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(123): expression size 32 truncated to fit in target size 2. VERI-1209
WARNING - synthesis: c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(128): expression size 32 truncated to fit in target size 18. VERI-1209
WARNING - synthesis: c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(255): expression size 32 truncated to fit in target size 4. VERI-1209
INFO - synthesis: C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1800): compiling module EFB. VERI-1018
WARNING - synthesis: c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(348): input port PLL0DATI7 is not connected on this instance. VDB-1013
WARNING - synthesis: c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v(348): input port PLL0DATI7 is not connected on this instance. VDB-1013
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
@@ -273,10 +273,10 @@ clk0 [get_nets RCLK_c] | 200.000 MHz| 65.694 MHz| 10 *
2 constraints not met.
Peak Memory Usage: 57.273 MB
Peak Memory Usage: 58.262 MB
--------------------------------------------------------------
Elapsed CPU time for LSE flow : 0.952 secs
Elapsed CPU time for LSE flow : 0.813 secs
--------------------------------------------------------------
CPLD/LCMXO2/LCMXO2-640HC/impl1/xxx_lse_cp_file_list
+350 -350
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@@ -1,350 +1,350 @@
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
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3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
3 c:/users/dog/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v
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LSE_CPS_ID_285 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:91[22:51]"
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LSE_CPS_ID_291 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:54[19:54]"
LSE_CPS_ID_292 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:54[19:54]"
LSE_CPS_ID_293 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:54[19:54]"
LSE_CPS_ID_294 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
LSE_CPS_ID_295 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
LSE_CPS_ID_296 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
LSE_CPS_ID_297 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
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LSE_CPS_ID_300 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:54[19:54]"
LSE_CPS_ID_301 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
LSE_CPS_ID_302 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:54[19:54]"
LSE_CPS_ID_303 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:54[19:54]"
LSE_CPS_ID_304 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
LSE_CPS_ID_305 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:128[9:13]"
LSE_CPS_ID_306 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:684[12] 729[6]"
LSE_CPS_ID_307 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:717[16:47]"
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LSE_CPS_ID_310 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:135[40:46]"
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LSE_CPS_ID_319 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:710[16:26]"
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LSE_CPS_ID_334 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:717[16:47]"
LSE_CPS_ID_335 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:717[16:47]"
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LSE_CPS_ID_340 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:123[13:16]"
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LSE_CPS_ID_344 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:717[16:47]"
LSE_CPS_ID_345 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:717[16:47]"
LSE_CPS_ID_346 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:717[16:47]"
LSE_CPS_ID_347 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:54[19:54]"
LSE_CPS_ID_348 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:717[16:47]"
LSE_CPS_ID_349 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:7[8:12]"
LSE_CPS_ID_350 "c:/users/zanek/documents/github/ram2gs/cpld/lcmxo2/ram2gs-lcmxo2.v:15[15:20]"
CPLD/MAX/RAM2GS-MAX.v
+15 -2
View File
@@ -340,13 +340,17 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
// Submit command
if (CMDWR & CmdEnable) begin
if (Din[7:4]==4'h0) begin
if (Din[7:4]==4'h0 && Din[3:2]==2'b01) begin
// LCMXO, LCMXO2, iCE40 ignore this unless Din[2] and Din[1] set
// MAX w/ LED ignores this unless Din[2] set
// MAX w/o LED does not check Din[3:1].
XOR8MEG <= Din[0];
end else if (Din[7:4]==4'h1) begin
CmdLEDEN <= ~Din[1];
Cmdn8MEGEN <= ~Din[0];
CmdSubmitted <= 1'b1;
end else if (Din[7:4]==4'h2 && Din[3]==1'b0) begin
end else if (Din[7:4]==4'h2) begin
// MAX commands
CmdLEDEN <= LEDEN;
Cmdn8MEGEN <= n8MEGEN;
CmdUFMErase <= Din[3];
@@ -354,6 +358,15 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
CmdDRCLK <= Din[1];
CmdDRDIn <= Din[0];
CmdSubmitted <= 1'b1;
end else if (Din[7:4]==4'h3 && ~Din[3]) begin
// Reserved for LCMXO2 commands
// Din[1] - Shift when high, execute when low
// Din[0] - Shift data
end else if (Din[7:4]==4'h3 && Din[3]) begin
// Reserved for SPI (LCMXO, iCE40) commands
// Din[2] - CS
// Din[1] - SCK
// Din[0] - SDI
end
end
end