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RAM2GS
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Gate LED with Ready signal

This commit is contained in:
Zane Kaminski 2023-09-29 15:18:46 -04:00
parent 97fe10f40a
commit 84f33af9c0
31 changed files with 1575 additions and 1579 deletions
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2
CPLD/MAXII/RAM2GS.qsf
View File

@ -42,7 +42,7 @@ set_global_assignment -name DEVICE EPM240T100C5
set_global_assignment -name TOP_LEVEL_ENTITY RAM2GS
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 19.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:27:39 AUGUST 12, 2023"
set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"
set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 SP0.02std Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85

BIN
CPLD/MAXII/RAM2GS.qws
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Binary file not shown.

48
CPLD/MAXII/output_files/RAM2GS.asm.rpt
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@ -1,6 +1,6 @@
Assembler report for RAM2GS
Fri Sep 29 09:33:25 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Fri Sep 29 15:18:00 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
---------------------
@ -10,7 +10,7 @@ Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pof
5. Assembler Device Options: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pof
6. Assembler Messages
@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Fri Sep 29 09:33:25 2023 ;
; Assembler Status ; Successful - Fri Sep 29 15:18:00 2023 ;
; Revision Name ; RAM2GS ;
; Top-level Entity Name ; RAM2GS ;
; Family ; MAX II ;
@ -53,23 +53,23 @@ https://fpgasoftware.intel.com/eula.
+--------+---------+---------------+
+--------------------------------------------------+
; Assembler Generated Files ;
+--------------------------------------------------+
; File Name ;
+--------------------------------------------------+
; /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pof ;
+--------------------------------------------------+
+---------------------------------------------------------------------------+
; Assembler Generated Files ;
+---------------------------------------------------------------------------+
; File Name ;
+---------------------------------------------------------------------------+
; C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pof ;
+---------------------------------------------------------------------------+
+----------------------------------------------------------------------------+
; Assembler Device Options: /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pof ;
+----------------+-----------------------------------------------------------+
; Option ; Setting ;
+----------------+-----------------------------------------------------------+
; JTAG usercode ; 0x001726D4 ;
; Checksum ; 0x00172A4C ;
+----------------+-----------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------+
; Assembler Device Options: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pof ;
+----------------+------------------------------------------------------------------------------------+
; Option ; Setting ;
+----------------+------------------------------------------------------------------------------------+
; JTAG usercode ; 0x00171B9B ;
; Checksum ; 0x00171E13 ;
+----------------+------------------------------------------------------------------------------------+
+--------------------+
@ -77,15 +77,15 @@ https://fpgasoftware.intel.com/eula.
+--------------------+
Info: *******************************************************************
Info: Running Quartus Prime Assembler
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Info: Processing started: Fri Sep 29 09:33:24 2023
Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Info: Processing started: Fri Sep 29 15:18:00 2023
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 13094 megabytes
Info: Processing ended: Fri Sep 29 09:33:25 2023
Info: Elapsed time: 00:00:01
Info: Peak virtual memory: 534 megabytes
Info: Processing ended: Fri Sep 29 15:18:00 2023
Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:01

2
CPLD/MAXII/output_files/RAM2GS.done
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@ -1 +1 @@
Fri Sep 29 09:33:28 2023
Fri Sep 29 15:18:03 2023

256
CPLD/MAXII/output_files/RAM2GS.fit.rpt
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@ -1,6 +1,6 @@
Fitter report for RAM2GS
Fri Sep 29 09:33:23 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Fri Sep 29 15:17:59 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
---------------------
@ -56,21 +56,21 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+---------------------------------------------+
; Fitter Status ; Successful - Fri Sep 29 09:33:23 2023 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
; Revision Name ; RAM2GS ;
; Top-level Entity Name ; RAM2GS ;
; Family ; MAX II ;
; Device ; EPM240T100C5 ;
; Timing Models ; Final ;
; Total logic elements ; 185 / 240 ( 77 % ) ;
; Total pins ; 63 / 80 ( 79 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
+-----------------------+---------------------------------------------+
+-------------------------------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+-------------------------------------------------------------+
; Fitter Status ; Successful - Fri Sep 29 15:17:59 2023 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
; Revision Name ; RAM2GS ;
; Top-level Entity Name ; RAM2GS ;
; Family ; MAX II ;
; Device ; EPM240T100C5 ;
; Timing Models ; Final ;
; Total logic elements ; 184 / 240 ( 77 % ) ;
; Total pins ; 63 / 80 ( 79 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
+-----------------------+-------------------------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------+
@ -128,23 +128,23 @@ https://fpgasoftware.intel.com/eula.
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 4 ;
; Number detected on machine ; 8 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.06 ;
; Average used ; 1.04 ;
; Maximum used ; 4 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processor 2 ; 2.8% ;
; Processors 3-4 ; 1.8% ;
; Processor 2 ; 1.5% ;
; Processors 3-4 ; 1.4% ;
+----------------------------+-------------+
+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pin.
The pin-out file can be found in C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pin.
+---------------------------------------------------------------------+
@ -152,28 +152,28 @@ The pin-out file can be found in /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pi
+---------------------------------------------+-----------------------+
; Resource ; Usage ;
+---------------------------------------------+-----------------------+
; Total logic elements ; 185 / 240 ( 77 % ) ;
; -- Combinational with no register ; 81 ;
; Total logic elements ; 184 / 240 ( 77 % ) ;
; -- Combinational with no register ; 80 ;
; -- Register only ; 22 ;
; -- Combinational with a register ; 82 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 62 ;
; -- 3 input functions ; 50 ;
; -- 2 input functions ; 42 ;
; -- 4 input functions ; 64 ;
; -- 3 input functions ; 46 ;
; -- 2 input functions ; 43 ;
; -- 1 input functions ; 8 ;
; -- 0 input functions ; 1 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 169 ;
; -- normal mode ; 168 ;
; -- arithmetic mode ; 16 ;
; -- qfbk mode ; 11 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 33 ;
; -- synchronous clear/load mode ; 35 ;
; -- asynchronous clear/load mode ; 0 ;
; ; ;
; Total registers ; 104 / 240 ( 43 % ) ;
; Total LABs ; 23 / 24 ( 96 % ) ;
; Total LABs ; 21 / 24 ( 88 % ) ;
; Logic elements in carry chains ; 17 ;
; Virtual pins ; 0 ;
; I/O pins ; 63 / 80 ( 79 % ) ;
@ -187,11 +187,11 @@ The pin-out file can be found in /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pi
; Global signals ; 4 ;
; -- Global clocks ; 4 / 4 ( 100 % ) ;
; JTAGs ; 0 / 1 ( 0 % ) ;
; Average interconnect usage (total/H/V) ; 20.9% / 20.7% / 21.2% ;
; Peak interconnect usage (total/H/V) ; 20.9% / 20.7% / 21.2% ;
; Average interconnect usage (total/H/V) ; 23.0% / 24.7% / 21.2% ;
; Peak interconnect usage (total/H/V) ; 23.0% / 24.7% / 21.2% ;
; Maximum fan-out ; 61 ;
; Highest non-global fan-out ; 42 ;
; Total fan-out ; 701 ;
; Highest non-global fan-out ; 43 ;
; Total fan-out ; 699 ;
; Average fan-out ; 2.82 ;
+---------------------------------------------+-----------------------+
@ -225,7 +225,7 @@ The pin-out file can be found in /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pi
; RCLK ; 12 ; 1 ; 1 ; 3 ; 3 ; 61 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; nCCAS ; 53 ; 2 ; 8 ; 1 ; 3 ; 11 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; nCRAS ; 67 ; 2 ; 8 ; 3 ; 2 ; 16 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; nFWE ; 48 ; 1 ; 6 ; 0 ; 0 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; nFWE ; 48 ; 1 ; 6 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+----------------+
@ -242,7 +242,7 @@ The pin-out file can be found in /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pi
; Dout[5] ; 28 ; 1 ; 2 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; Dout[6] ; 34 ; 1 ; 3 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; Dout[7] ; 43 ; 1 ; 6 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; LED ; 88 ; 2 ; 5 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; - ; - ;
; LED ; 88 ; 2 ; 5 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; RA[0] ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RA[10] ; 16 ; 1 ; 1 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RA[11] ; 7 ; 1 ; 1 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
@ -263,7 +263,7 @@ The pin-out file can be found in /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pi
; nRCAS ; 4 ; 1 ; 1 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; nRCS ; 3 ; 1 ; 1 ; 4 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; nRRAS ; 6 ; 1 ; 1 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; nRWE ; 100 ; 2 ; 2 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; nRWE ; 100 ; 2 ; 2 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
@ -423,7 +423,7 @@ Note: User assignments will override these defaults. The user specified values a
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
; |RAM2GS ; 185 (185) ; 104 ; 1 ; 63 ; 0 ; 81 (81) ; 22 (22) ; 82 (82) ; 17 (17) ; 11 (11) ; |RAM2GS ; RAM2GS ; work ;
; |RAM2GS ; 184 (184) ; 104 ; 1 ; 63 ; 0 ; 80 (80) ; 22 (22) ; 82 (82) ; 17 (17) ; 11 (11) ; |RAM2GS ; RAM2GS ; work ;
; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst ; UFM ; work ;
; |UFM_altufm_none_unv:UFM_altufm_none_unv_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component ; UFM_altufm_none_unv ; work ;
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
@ -490,10 +490,10 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; CROW[1] ; Input ; (1) ;
; PHI2 ; Input ; (0) ;
; Din[6] ; Input ; (1) ;
; nFWE ; Input ; (1) ;
; Din[7] ; Input ; (1) ;
; Din[1] ; Input ; (1) ;
; Din[4] ; Input ; (1) ;
; nFWE ; Input ; (1) ;
; Din[3] ; Input ; (1) ;
; Din[5] ; Input ; (1) ;
; Din[0] ; Input ; (1) ;
@ -506,15 +506,15 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+---------------+-------------+---------+-------------------------+--------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
+---------------+-------------+---------+-------------------------+--------+----------------------+------------------+
; CmdDRDIn~1 ; LC_X6_Y3_N7 ; 2 ; Clock enable ; no ; -- ; -- ;
; CmdLEDEN~1 ; LC_X5_Y2_N7 ; 3 ; Clock enable ; no ; -- ; -- ;
; CmdUFMErase~0 ; LC_X6_Y3_N5 ; 2 ; Clock enable ; no ; -- ; -- ;
; DRDIn~1 ; LC_X5_Y1_N9 ; 2 ; Clock enable ; no ; -- ; -- ;
; CmdDRDIn~1 ; LC_X5_Y2_N5 ; 2 ; Clock enable ; no ; -- ; -- ;
; CmdLEDEN~1 ; LC_X4_Y2_N2 ; 3 ; Clock enable ; no ; -- ; -- ;
; CmdUFMErase~0 ; LC_X7_Y3_N4 ; 2 ; Clock enable ; no ; -- ; -- ;
; DRDIn~1 ; LC_X3_Y1_N4 ; 2 ; Clock enable ; no ; -- ; -- ;
; PHI2 ; PIN_52 ; 22 ; Clock ; yes ; Global Clock ; GCLK3 ;
; RCLK ; PIN_12 ; 61 ; Clock ; yes ; Global Clock ; GCLK0 ;
; RD~16 ; LC_X4_Y4_N4 ; 8 ; Output enable ; no ; -- ; -- ;
; Ready ; LC_X3_Y2_N8 ; 41 ; Sync. clear, Sync. load ; no ; -- ; -- ;
; always11~8 ; LC_X6_Y4_N8 ; 3 ; Clock enable ; no ; -- ; -- ;
; RD~16 ; LC_X4_Y4_N7 ; 8 ; Output enable ; no ; -- ; -- ;
; Ready ; LC_X3_Y2_N8 ; 42 ; Sync. clear, Sync. load ; no ; -- ; -- ;
; always11~7 ; LC_X6_Y2_N2 ; 3 ; Clock enable ; no ; -- ; -- ;
; nCCAS ; PIN_53 ; 11 ; Clock ; yes ; Global Clock ; GCLK1 ;
; nCRAS ; PIN_67 ; 16 ; Clock ; yes ; Global Clock ; GCLK2 ;
+---------------+-------------+---------+-------------------------+--------+----------------------+------------------+
@ -537,43 +537,42 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+-----------------------+--------------------+
; Routing Resource Type ; Usage ;
+-----------------------+--------------------+
; C4s ; 143 / 784 ( 18 % ) ;
; Direct links ; 42 / 888 ( 5 % ) ;
; C4s ; 134 / 784 ( 17 % ) ;
; Direct links ; 53 / 888 ( 6 % ) ;
; Global clocks ; 4 / 4 ( 100 % ) ;
; LAB clocks ; 14 / 32 ( 44 % ) ;
; LAB clocks ; 17 / 32 ( 53 % ) ;
; LUT chains ; 13 / 216 ( 6 % ) ;
; Local interconnects ; 254 / 888 ( 29 % ) ;
; R4s ; 129 / 704 ( 18 % ) ;
; Local interconnects ; 259 / 888 ( 29 % ) ;
; R4s ; 137 / 704 ( 19 % ) ;
+-----------------------+--------------------+
+---------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+------------------------------+
; Number of Logic Elements (Average = 8.04) ; Number of LABs (Total = 23) ;
; Number of Logic Elements (Average = 8.76) ; Number of LABs (Total = 21) ;
+--------------------------------------------+------------------------------+
; 1 ; 0 ;
; 2 ; 2 ;
; 3 ; 1 ;
; 2 ; 1 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 2 ;
; 6 ; 0 ;
; 7 ; 3 ;
; 8 ; 1 ;
; 9 ; 1 ;
; 10 ; 13 ;
; 5 ; 0 ;
; 6 ; 2 ;
; 7 ; 1 ;
; 8 ; 2 ;
; 9 ; 3 ;
; 10 ; 12 ;
+--------------------------------------------+------------------------------+
+-------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+------------------------------+
; LAB-wide Signals (Average = 1.39) ; Number of LABs (Total = 23) ;
; LAB-wide Signals (Average = 1.29) ; Number of LABs (Total = 21) ;
+------------------------------------+------------------------------+
; 1 Clock ; 14 ;
; 1 Clock enable ; 4 ;
; 1 Clock ; 12 ;
; 1 Clock enable ; 3 ;
; 1 Sync. clear ; 3 ;
; 1 Sync. load ; 2 ;
; 2 Clocks ; 9 ;
+------------------------------------+------------------------------+
@ -581,18 +580,18 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+------------------------------+
; Number of Signals Sourced (Average = 8.35) ; Number of LABs (Total = 23) ;
; Number of Signals Sourced (Average = 9.10) ; Number of LABs (Total = 21) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 2 ;
; 3 ; 1 ;
; 2 ; 1 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 2 ;
; 6 ; 0 ;
; 7 ; 2 ;
; 5 ; 0 ;
; 6 ; 2 ;
; 7 ; 1 ;
; 8 ; 1 ;
; 9 ; 2 ;
; 9 ; 3 ;
; 10 ; 9 ;
; 11 ; 3 ;
; 12 ; 1 ;
@ -602,46 +601,47 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out (Average = 5.52) ; Number of LABs (Total = 23) ;
; Number of Signals Sourced Out (Average = 5.95) ; Number of LABs (Total = 21) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 2 ;
; 2 ; 1 ;
; 3 ; 1 ;
; 4 ; 3 ;
; 5 ; 4 ;
; 6 ; 6 ;
; 7 ; 5 ;
; 8 ; 1 ;
; 9 ; 1 ;
; 4 ; 4 ;
; 5 ; 2 ;
; 6 ; 4 ;
; 7 ; 4 ;
; 8 ; 3 ;
; 9 ; 2 ;
+-------------------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 9.48) ; Number of LABs (Total = 23) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 2 ;
; 3 ; 1 ;
; 4 ; 1 ;
; 5 ; 1 ;
; 6 ; 0 ;
; 7 ; 2 ;
; 8 ; 1 ;
; 9 ; 4 ;
; 10 ; 1 ;
; 11 ; 2 ;
; 12 ; 1 ;
; 13 ; 5 ;
; 14 ; 0 ;
; 15 ; 0 ;
; 16 ; 0 ;
; 17 ; 1 ;
; 18 ; 1 ;
+---------------------------------------------+------------------------------+
+-----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+----------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 10.33) ; Number of LABs (Total = 21) ;
+----------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 2 ;
; 3 ; 1 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 2 ;
; 7 ; 2 ;
; 8 ; 0 ;
; 9 ; 1 ;
; 10 ; 1 ;
; 11 ; 3 ;
; 12 ; 2 ;
; 13 ; 1 ;
; 14 ; 0 ;
; 15 ; 4 ;
; 16 ; 1 ;
; 17 ; 0 ;
; 18 ; 0 ;
; 19 ; 1 ;
+----------------------------------------------+------------------------------+
+-------------------------------------------------------------------------+
@ -664,7 +664,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
+-----------------+----------------------+-------------------+
; I/O ; RCLK ; 4.0 ;
; I/O ; nCRAS ; 3.0 ;
; I/O ; nCRAS ; 2.5 ;
+-----------------+----------------------+-------------------+
Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
This will disable optimization of problematic paths and expose them for further analysis using the Timing Analyzer.
@ -675,7 +675,7 @@ This will disable optimization of problematic paths and expose them for further
+-----------------+----------------------+-------------------+
; Source Register ; Destination Register ; Delay Added in ns ;
+-----------------+----------------------+-------------------+
; nCCAS ; CBR ; 3.041 ;
; nCCAS ; CBR ; 2.469 ;
; PHI2 ; PHI2r ; 1.523 ;
; nCRAS ; RASr ; 1.214 ;
+-----------------+----------------------+-------------------+
@ -710,19 +710,19 @@ Info (332111): Found 6 clocks
Info (332111): 350.000 PHI2
Info (332111): 16.000 RCLK
Info (186079): Completed User Assigned Global Signals Promotion Operation
Info (186215): Automatically promoted signal "RCLK" to use Global clock in PIN 12 File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 41
Info (186216): Automatically promoted some destinations of signal "PHI2" to use Global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 8
Info (186217): Destination "PHI2r" may be non-global or may not use global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 14
Info (186228): Pin "PHI2" drives global clock, but is not placed in a dedicated clock pin position File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 8
Info (186216): Automatically promoted some destinations of signal "nCRAS" to use Global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11
Info (186217): Destination "LED~0" may be non-global or may not use global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 22
Info (186217): Destination "RASr" may be non-global or may not use global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 15
Info (186228): Pin "nCRAS" drives global clock, but is not placed in a dedicated clock pin position File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11
Info (186216): Automatically promoted some destinations of signal "nCCAS" to use Global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11
Info (186217): Destination "CBR" may be non-global or may not use global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 18
Info (186217): Destination "RD~16" may be non-global or may not use global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 60
Info (186217): Destination "CASr" may be non-global or may not use global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 16
Info (186228): Pin "nCCAS" drives global clock, but is not placed in a dedicated clock pin position File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11
Info (186215): Automatically promoted signal "RCLK" to use Global clock in PIN 12 File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 41
Info (186216): Automatically promoted some destinations of signal "PHI2" to use Global clock File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 8
Info (186217): Destination "PHI2r" may be non-global or may not use global clock File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 14
Info (186228): Pin "PHI2" drives global clock, but is not placed in a dedicated clock pin position File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 8
Info (186216): Automatically promoted some destinations of signal "nCRAS" to use Global clock File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11
Info (186217): Destination "LED~0" may be non-global or may not use global clock File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 22
Info (186217): Destination "RASr" may be non-global or may not use global clock File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 15
Info (186228): Pin "nCRAS" drives global clock, but is not placed in a dedicated clock pin position File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11
Info (186216): Automatically promoted some destinations of signal "nCCAS" to use Global clock File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11
Info (186217): Destination "CBR" may be non-global or may not use global clock File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 18
Info (186217): Destination "RD~16" may be non-global or may not use global clock File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 60
Info (186217): Destination "CASr" may be non-global or may not use global clock File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 16
Info (186228): Pin "nCCAS" drives global clock, but is not placed in a dedicated clock pin position File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11
Info (186079): Completed Auto Global Promotion Operation
Info (176234): Starting register packing
Info (186468): Started processing fast register assignments
@ -734,26 +734,26 @@ Info (170189): Fitter placement preparation operations beginning
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
Info (170191): Fitter placement operations beginning
Info (170137): Fitter placement was successful
Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
Info (170193): Fitter routing operations beginning
Info (170195): Router estimated average interconnect usage is 19% of the available device resources
Info (170196): Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
Info (170195): Router estimated average interconnect usage is 20% of the available device resources
Info (170196): Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info (170201): Optimizations that may affect the design's routability were skipped
Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
Info (11888): Total time spent on timing analysis during the Fitter is 0.46 seconds.
Info (11888): Total time spent on timing analysis during the Fitter is 0.28 seconds.
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
Info (144001): Generated suppressed messages file /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg
Info (144001): Generated suppressed messages file C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg
Info: Quartus Prime Fitter was successful. 0 errors, 1 warning
Info: Peak virtual memory: 13771 megabytes
Info: Processing ended: Fri Sep 29 09:33:23 2023
Info: Peak virtual memory: 1156 megabytes
Info: Processing ended: Fri Sep 29 15:17:59 2023
Info: Elapsed time: 00:00:03
Info: Total CPU time (on all processors): 00:00:04
Info: Total CPU time (on all processors): 00:00:03
+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg.
The suppressed messages can be found in C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg.

6
CPLD/MAXII/output_files/RAM2GS.fit.summary
View File

@ -1,11 +1,11 @@
Fitter Status : Successful - Fri Sep 29 09:33:23 2023
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Fitter Status : Successful - Fri Sep 29 15:17:59 2023
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Revision Name : RAM2GS
Top-level Entity Name : RAM2GS
Family : MAX II
Device : EPM240T100C5
Timing Models : Final
Total logic elements : 185 / 240 ( 77 % )
Total logic elements : 184 / 240 ( 77 % )
Total pins : 63 / 80 ( 79 % )
Total virtual pins : 0
UFM blocks : 1 / 1 ( 100 % )

92
CPLD/MAXII/output_files/RAM2GS.flow.rpt
View File

@ -1,6 +1,6 @@
Flow report for RAM2GS
Fri Sep 29 09:33:27 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Fri Sep 29 15:18:02 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
---------------------
@ -38,21 +38,21 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------------+
; Flow Summary ;
+-----------------------+---------------------------------------------+
; Flow Status ; Successful - Fri Sep 29 09:33:25 2023 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
; Revision Name ; RAM2GS ;
; Top-level Entity Name ; RAM2GS ;
; Family ; MAX II ;
; Device ; EPM240T100C5 ;
; Timing Models ; Final ;
; Total logic elements ; 185 / 240 ( 77 % ) ;
; Total pins ; 63 / 80 ( 79 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
+-----------------------+---------------------------------------------+
+-------------------------------------------------------------------------------------+
; Flow Summary ;
+-----------------------+-------------------------------------------------------------+
; Flow Status ; Successful - Fri Sep 29 15:18:00 2023 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
; Revision Name ; RAM2GS ;
; Top-level Entity Name ; RAM2GS ;
; Family ; MAX II ;
; Device ; EPM240T100C5 ;
; Timing Models ; Final ;
; Total logic elements ; 184 / 240 ( 77 % ) ;
; Total pins ; 63 / 80 ( 79 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
+-----------------------+-------------------------------------------------------------+
+-----------------------------------------+
@ -60,25 +60,25 @@ https://fpgasoftware.intel.com/eula.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 09/29/2023 09:32:59 ;
; Start date & time ; 09/29/2023 15:17:44 ;
; Main task ; Compilation ;
; Revision Name ; RAM2GS ;
+-------------------+---------------------+
+-----------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+---------------------------------------+------------------------------+---------------+-------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+---------------------------------------+------------------------------+---------------+-------------+------------+
; COMPILER_SIGNATURE_ID ; 121381084694.169599437907024 ; -- ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; NUM_PARALLEL_PROCESSORS ; 4 ; -- ; -- ; -- ;
; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 3.3V ; -- ; -- ; -- ;
; POWER_PRESET_COOLING_SOLUTION ; No Heat Sink With Still Air ; -- ; -- ; -- ;
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
+---------------------------------------+------------------------------+---------------+-------------+------------+
+--------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+---------------------------------------+---------------------------------+---------------+-------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+---------------------------------------+---------------------------------+---------------+-------------+------------+
; COMPILER_SIGNATURE_ID ; 123745752457129.169601506401636 ; -- ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; NUM_PARALLEL_PROCESSORS ; 4 ; -- ; -- ; -- ;
; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 3.3V ; -- ; -- ; -- ;
; POWER_PRESET_COOLING_SOLUTION ; No Heat Sink With Still Air ; -- ; -- ; -- ;
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
+---------------------------------------+---------------------------------+---------------+-------------+------------+
+--------------------------------------------------------------------------------------------------------------------------+
@ -86,24 +86,24 @@ https://fpgasoftware.intel.com/eula.
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:21 ; 1.0 ; 13133 MB ; 00:00:47 ;
; Fitter ; 00:00:03 ; 1.1 ; 13771 MB ; 00:00:04 ;
; Assembler ; 00:00:01 ; 1.0 ; 13094 MB ; 00:00:01 ;
; Timing Analyzer ; 00:00:01 ; 1.0 ; 13090 MB ; 00:00:01 ;
; Total ; 00:00:26 ; -- ; -- ; 00:00:53 ;
; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 562 MB ; 00:00:30 ;
; Fitter ; 00:00:03 ; 1.0 ; 1156 MB ; 00:00:03 ;
; Assembler ; 00:00:00 ; 1.0 ; 534 MB ; 00:00:01 ;
; Timing Analyzer ; 00:00:01 ; 1.0 ; 533 MB ; 00:00:01 ;
; Total ; 00:00:15 ; -- ; -- ; 00:00:35 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
+------------------------------------------------------------------------------------+
; Flow OS Summary ;
+----------------------+------------------+------------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+----------------------+------------------+------------+------------+----------------+
; Analysis & Synthesis ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ;
; Fitter ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ;
; Assembler ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ;
; Timing Analyzer ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ;
+----------------------+------------------+------------+------------+----------------+
+-----------------------------------------------------------------------------------+
; Flow OS Summary ;
+----------------------+------------------+-----------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+----------------------+------------------+-----------+------------+----------------+
; Analysis & Synthesis ; LabWin7 ; Windows 7 ; 6.1 ; x86_64 ;
; Fitter ; LabWin7 ; Windows 7 ; 6.1 ; x86_64 ;
; Assembler ; LabWin7 ; Windows 7 ; 6.1 ; x86_64 ;
; Timing Analyzer ; LabWin7 ; Windows 7 ; 6.1 ; x86_64 ;
+----------------------+------------------+-----------+------------+----------------+
------------

2
CPLD/MAXII/output_files/RAM2GS.jdi
View File

@ -1,6 +1,6 @@
<sld_project_info>
<project>
<hash md5_digest_80b="5a47e54f307a3a9998ad"/>
<hash md5_digest_80b="73cb99ca7f0139ffc2c9"/>
</project>
<file_info>
<file device="EPM240T100C5" path="RAM2GS.sof" usercode="0xFFFFFFFF"/>

116
CPLD/MAXII/output_files/RAM2GS.map.rpt
View File

@ -1,6 +1,6 @@
Analysis & Synthesis report for RAM2GS
Fri Sep 29 09:33:19 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Fri Sep 29 15:17:55 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
---------------------
@ -43,19 +43,19 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+---------------------------------------------+
; Analysis & Synthesis Status ; Successful - Fri Sep 29 09:33:19 2023 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
; Revision Name ; RAM2GS ;
; Top-level Entity Name ; RAM2GS ;
; Family ; MAX II ;
; Total logic elements ; 197 ;
; Total pins ; 63 ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
+-----------------------------+---------------------------------------------+
+-------------------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+-------------------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Fri Sep 29 15:17:55 2023 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
; Revision Name ; RAM2GS ;
; Top-level Entity Name ; RAM2GS ;
; Family ; MAX II ;
; Total logic elements ; 196 ;
; Total pins ; 63 ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
+-----------------------------+-------------------------------------------------------------+
+------------------------------------------------------------------------------------------------------------+
@ -135,7 +135,7 @@ https://fpgasoftware.intel.com/eula.
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 4 ;
; Number detected on machine ; 8 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.00 ;
@ -146,15 +146,15 @@ https://fpgasoftware.intel.com/eula.
+----------------------------+-------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+----------------------------------+-------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+----------------------------------+-------------------------------------------------+---------+
; ../RAM2GS-MAX.v ; yes ; User Verilog HDL File ; //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v ; ;
; UFM.v ; yes ; User Wizard-Generated File ; //Mac/iCloud/Repos/RAM2GS/CPLD/MAXII/UFM.v ; ;
; ../RAM2GS.mif ; yes ; User Memory Initialization File ; //Mac/iCloud/Repos/RAM2GS/CPLD/MAXII/RAM2GS.mif ; ;
+----------------------------------+-----------------+----------------------------------+-------------------------------------------------+---------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+----------------------------------+--------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+----------------------------------+--------------------------------------------------------------+---------+
; ../RAM2GS-MAX.v ; yes ; User Verilog HDL File ; C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v ; ;
; UFM.v ; yes ; User Wizard-Generated File ; C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v ; ;
; ../RAM2GS.mif ; yes ; User Memory Initialization File ; C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXII/RAM2GS.mif ; ;
+----------------------------------+-----------------+----------------------------------+--------------------------------------------------------------+---------+
+-----------------------------------------------------+
@ -162,20 +162,20 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------+-------+
; Resource ; Usage ;
+---------------------------------------------+-------+
; Total logic elements ; 197 ;
; -- Combinational with no register ; 93 ;
; Total logic elements ; 196 ;
; -- Combinational with no register ; 92 ;
; -- Register only ; 34 ;
; -- Combinational with a register ; 70 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 62 ;
; -- 3 input functions ; 50 ;
; -- 2 input functions ; 42 ;
; -- 4 input functions ; 64 ;
; -- 3 input functions ; 46 ;
; -- 2 input functions ; 43 ;
; -- 1 input functions ; 8 ;
; -- 0 input functions ; 1 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 181 ;
; -- normal mode ; 180 ;
; -- arithmetic mode ; 16 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
@ -188,7 +188,7 @@ https://fpgasoftware.intel.com/eula.
; UFM blocks ; 1 ;
; Maximum fan-out node ; RCLK ;
; Maximum fan-out ; 61 ;
; Total fan-out ; 705 ;
; Total fan-out ; 703 ;
; Average fan-out ; 2.70 ;
+---------------------------------------------+-------+
@ -198,7 +198,7 @@ https://fpgasoftware.intel.com/eula.
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
; |RAM2GS ; 197 (197) ; 104 ; 1 ; 63 ; 0 ; 93 (93) ; 34 (34) ; 70 (70) ; 17 (17) ; 0 (0) ; |RAM2GS ; RAM2GS ; work ;
; |RAM2GS ; 196 (196) ; 104 ; 1 ; 63 ; 0 ; 92 (92) ; 34 (34) ; 70 (70) ; 17 (17) ; 0 (0) ; |RAM2GS ; RAM2GS ; work ;
; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst ; UFM ; work ;
; |UFM_altufm_none_unv:UFM_altufm_none_unv_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component ; UFM_altufm_none_unv ; work ;
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
@ -247,7 +247,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |RAM2GS|S[0] ;
; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |RAM2GS|S[1] ;
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |RAM2GS|CmdLEDEN ;
; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |RAM2GS|C1Submitted ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
@ -268,43 +268,43 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Info: Processing started: Fri Sep 29 09:32:58 2023
Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Info: Processing started: Fri Sep 29 15:17:44 2023
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS
Info (20032): Parallel compilation is enabled and will use up to 4 processors
Info (12021): Found 1 design units, including 1 entities, in source file //mac/icloud/repos/ram2gs/cpld/ram2gs-max.v
Info (12023): Found entity 1: RAM2GS File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file /users/gwolf/documents/github/ram2gs/cpld/ram2gs-max.v
Info (12023): Found entity 1: RAM2GS File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 1
Info (12021): Found 2 design units, including 2 entities, in source file ufm.v
Info (12023): Found entity 1: UFM_altufm_none_unv File: //Mac/iCloud/Repos/RAM2GS/CPLD/MAXII/UFM.v Line: 47
Info (12023): Found entity 2: UFM File: //Mac/iCloud/Repos/RAM2GS/CPLD/MAXII/UFM.v Line: 150
Info (12023): Found entity 1: UFM_altufm_none_unv File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v Line: 47
Info (12023): Found entity 2: UFM File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v Line: 150
Info (12127): Elaborating entity "RAM2GS" for the top level hierarchy
Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst" File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 92
Info (12128): Elaborating entity "UFM_altufm_none_unv" for hierarchy "UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component" File: //Mac/iCloud/Repos/RAM2GS/CPLD/MAXII/UFM.v Line: 201
Warning (14632): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
Warning (14632): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
Warning (14632): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
Warning (14632): Output pin "Dout[3]" driven by bidirectional pin "RD[3]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
Warning (14632): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
Warning (14632): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
Warning (14632): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
Warning (14632): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
Info (21057): Implemented 261 device resources after synthesis - the final resource count might be different
Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst" File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 92
Info (12128): Elaborating entity "UFM_altufm_none_unv" for hierarchy "UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component" File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v Line: 201
Warning (14632): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
Warning (14632): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
Warning (14632): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
Warning (14632): Output pin "Dout[3]" driven by bidirectional pin "RD[3]" cannot be tri-stated File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
Warning (14632): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot be tri-stated File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
Warning (14632): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
Warning (14632): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
Warning (14632): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
Info (21057): Implemented 260 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 25 input pins
Info (21059): Implemented 30 output pins
Info (21060): Implemented 8 bidirectional pins
Info (21061): Implemented 197 logic cells
Info (21061): Implemented 196 logic cells
Info (21070): Implemented 1 User Flash Memory blocks
Info (144001): Generated suppressed messages file /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg
Info (144001): Generated suppressed messages file C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 8 warnings
Info: Peak virtual memory: 13133 megabytes
Info: Processing ended: Fri Sep 29 09:33:19 2023
Info: Elapsed time: 00:00:21
Info: Total CPU time (on all processors): 00:00:47
Info: Peak virtual memory: 562 megabytes
Info: Processing ended: Fri Sep 29 15:17:55 2023
Info: Elapsed time: 00:00:11
Info: Total CPU time (on all processors): 00:00:30
+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg.
The suppressed messages can be found in C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg.

6
CPLD/MAXII/output_files/RAM2GS.map.smsg
View File

@ -1,3 +1,3 @@
Warning (10273): Verilog HDL warning at RAM2GS-MAX.v(61): extended using "x" or "z" File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 61
Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: //Mac/iCloud/Repos/RAM2GS/CPLD/MAXII/UFM.v Line: 73
Warning (10463): Verilog HDL Declaration warning at UFM.v(173): "program" is SystemVerilog-2005 keyword File: //Mac/iCloud/Repos/RAM2GS/CPLD/MAXII/UFM.v Line: 173
Warning (10273): Verilog HDL warning at RAM2GS-MAX.v(61): extended using "x" or "z" File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 61
Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v Line: 73
Warning (10463): Verilog HDL Declaration warning at UFM.v(173): "program" is SystemVerilog-2005 keyword File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXII/UFM.v Line: 173

6
CPLD/MAXII/output_files/RAM2GS.map.summary
View File

@ -1,9 +1,9 @@
Analysis & Synthesis Status : Successful - Fri Sep 29 09:33:19 2023
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Analysis & Synthesis Status : Successful - Fri Sep 29 15:17:55 2023
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Revision Name : RAM2GS
Top-level Entity Name : RAM2GS
Family : MAX II
Total logic elements : 197
Total logic elements : 196
Total pins : 63
Total virtual pins : 0
UFM blocks : 1 / 1 ( 100 % )

2
CPLD/MAXII/output_files/RAM2GS.pin
View File

@ -58,7 +58,7 @@
-- Pin directions (input, output or bidir) are based on device operating in user mode.
---------------------------------------------------------------------------------
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
CHIP "RAM2GS" ASSIGNED TO AN: EPM240T100C5
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment

BIN
CPLD/MAXII/output_files/RAM2GS.pof
View File

Binary file not shown.

918
CPLD/MAXII/output_files/RAM2GS.sta.rpt
View File

File diff suppressed because it is too large Load Diff

32
CPLD/MAXII/output_files/RAM2GS.sta.summary
View File

@ -3,43 +3,43 @@ Timing Analyzer Summary
------------------------------------------------------------
Type : Setup 'ARCLK'
Slack : -15.724
TNS : -15.724
Slack : -15.739
TNS : -15.739
Type : Setup 'DRCLK'
Slack : -15.649
TNS : -15.649
Slack : -15.716
TNS : -15.716
Type : Setup 'RCLK'
Slack : -7.823
TNS : -68.940
Slack : -7.070
TNS : -66.746
Type : Setup 'nCRAS'
Slack : 0.324
Slack : 0.330
TNS : 0.000
Type : Setup 'PHI2'
Slack : 0.552
Slack : 0.519
TNS : 0.000
Type : Hold 'DRCLK'
Slack : -16.401
TNS : -16.401
Slack : -16.296
TNS : -16.296
Type : Hold 'ARCLK'
Slack : -16.276
TNS : -16.276
Slack : -16.261
TNS : -16.261
Type : Hold 'PHI2'
Slack : -0.482
TNS : -1.385
Slack : -0.480
TNS : -1.135
Type : Hold 'nCRAS'
Slack : 0.180
Slack : 0.160
TNS : 0.000
Type : Hold 'RCLK'
Slack : 1.108
Slack : 1.109
TNS : 0.000
Type : Minimum Pulse Width 'RCLK'

2
CPLD/MAXV/RAM2GS.qsf
View File

@ -42,7 +42,7 @@ set_global_assignment -name DEVICE 5M240ZT100C5
set_global_assignment -name TOP_LEVEL_ENTITY RAM2GS
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 19.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:28:29 AUGUST 12, 2023"
set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition"
set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 SP0.02std Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85

BIN
CPLD/MAXV/RAM2GS.qws
View File

Binary file not shown.

48
CPLD/MAXV/output_files/RAM2GS.asm.rpt
View File

@ -1,6 +1,6 @@
Assembler report for RAM2GS
Thu Sep 21 05:38:26 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Fri Sep 29 15:17:55 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
---------------------
@ -10,7 +10,7 @@ Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: /Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.pof
5. Assembler Device Options: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.pof
6. Assembler Messages
@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Thu Sep 21 05:38:26 2023 ;
; Assembler Status ; Successful - Fri Sep 29 15:17:55 2023 ;
; Revision Name ; RAM2GS ;
; Top-level Entity Name ; RAM2GS ;
; Family ; MAX V ;
@ -53,23 +53,23 @@ https://fpgasoftware.intel.com/eula.
+--------+---------+---------------+
+-------------------------------------------------+
; Assembler Generated Files ;
+-------------------------------------------------+
; File Name ;
+-------------------------------------------------+
; /Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.pof ;
+-------------------------------------------------+
+--------------------------------------------------------------------------+
; Assembler Generated Files ;
+--------------------------------------------------------------------------+
; File Name ;
+--------------------------------------------------------------------------+
; C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.pof ;
+--------------------------------------------------------------------------+
+---------------------------------------------------------------------------+
; Assembler Device Options: /Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.pof ;
+----------------+----------------------------------------------------------+
; Option ; Setting ;
+----------------+----------------------------------------------------------+
; JTAG usercode ; 0x00174623 ;
; Checksum ; 0x00174A1B ;
+----------------+----------------------------------------------------------+
+----------------------------------------------------------------------------------------------------+
; Assembler Device Options: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.pof ;
+----------------+-----------------------------------------------------------------------------------+
; Option ; Setting ;
+----------------+-----------------------------------------------------------------------------------+
; JTAG usercode ; 0x00172723 ;
; Checksum ; 0x00172A9B ;
+----------------+-----------------------------------------------------------------------------------+
+--------------------+
@ -77,15 +77,15 @@ https://fpgasoftware.intel.com/eula.
+--------------------+
Info: *******************************************************************
Info: Running Quartus Prime Assembler
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Info: Processing started: Thu Sep 21 05:38:25 2023
Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Info: Processing started: Fri Sep 29 15:17:55 2023
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXV -c RAM2GS
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 13096 megabytes
Info: Processing ended: Thu Sep 21 05:38:27 2023
Info: Elapsed time: 00:00:02
Info: Peak virtual memory: 534 megabytes
Info: Processing ended: Fri Sep 29 15:17:55 2023
Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:01

2
CPLD/MAXV/output_files/RAM2GS.done
View File

@ -1 +1 @@
Thu Sep 21 05:38:32 2023
Fri Sep 29 15:17:58 2023

278
CPLD/MAXV/output_files/RAM2GS.fit.rpt
View File

@ -1,6 +1,6 @@
Fitter report for RAM2GS
Thu Sep 21 05:38:24 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Fri Sep 29 15:17:53 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
---------------------
@ -56,21 +56,21 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+---------------------------------------------+
; Fitter Status ; Successful - Thu Sep 21 05:38:24 2023 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
; Revision Name ; RAM2GS ;
; Top-level Entity Name ; RAM2GS ;
; Family ; MAX V ;
; Device ; 5M240ZT100C5 ;
; Timing Models ; Final ;
; Total logic elements ; 175 / 240 ( 73 % ) ;
; Total pins ; 63 / 79 ( 80 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
+-----------------------+---------------------------------------------+
+-------------------------------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+-------------------------------------------------------------+
; Fitter Status ; Successful - Fri Sep 29 15:17:53 2023 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
; Revision Name ; RAM2GS ;
; Top-level Entity Name ; RAM2GS ;
; Family ; MAX V ;
; Device ; 5M240ZT100C5 ;
; Timing Models ; Final ;
; Total logic elements ; 184 / 240 ( 77 % ) ;
; Total pins ; 63 / 79 ( 80 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
+-----------------------+-------------------------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------+
@ -128,7 +128,7 @@ https://fpgasoftware.intel.com/eula.
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 4 ;
; Number detected on machine ; 8 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.03 ;
@ -136,15 +136,15 @@ https://fpgasoftware.intel.com/eula.
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
; Processor 2 ; 1.0% ;
; Processors 3-4 ; 0.8% ;
; Processor 2 ; 1.3% ;
; Processors 3-4 ; 1.1% ;
+----------------------------+-------------+
+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in /Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.pin.
The pin-out file can be found in C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.pin.
+---------------------------------------------------------------------+
@ -152,28 +152,28 @@ The pin-out file can be found in /Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.pin
+---------------------------------------------+-----------------------+
; Resource ; Usage ;
+---------------------------------------------+-----------------------+
; Total logic elements ; 175 / 240 ( 73 % ) ;
; -- Combinational with no register ; 77 ;
; -- Register only ; 21 ;
; -- Combinational with a register ; 77 ;
; Total logic elements ; 184 / 240 ( 77 % ) ;
; -- Combinational with no register ; 80 ;
; -- Register only ; 22 ;
; -- Combinational with a register ; 82 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 57 ;
; -- 4 input functions ; 64 ;
; -- 3 input functions ; 46 ;
; -- 2 input functions ; 42 ;
; -- 2 input functions ; 43 ;
; -- 1 input functions ; 8 ;
; -- 0 input functions ; 1 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 159 ;
; -- normal mode ; 168 ;
; -- arithmetic mode ; 16 ;
; -- qfbk mode ; 8 ;
; -- qfbk mode ; 11 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 29 ;
; -- synchronous clear/load mode ; 33 ;
; -- asynchronous clear/load mode ; 0 ;
; ; ;
; Total registers ; 98 / 240 ( 41 % ) ;
; Total LABs ; 22 / 24 ( 92 % ) ;
; Total registers ; 104 / 240 ( 43 % ) ;
; Total LABs ; 24 / 24 ( 100 % ) ;
; Logic elements in carry chains ; 17 ;
; Virtual pins ; 0 ;
; I/O pins ; 63 / 79 ( 80 % ) ;
@ -187,12 +187,12 @@ The pin-out file can be found in /Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.pin
; Global signals ; 4 ;
; -- Global clocks ; 4 / 4 ( 100 % ) ;
; JTAGs ; 0 / 1 ( 0 % ) ;
; Average interconnect usage (total/H/V) ; 20.2% / 22.0% / 18.3% ;
; Peak interconnect usage (total/H/V) ; 20.2% / 22.0% / 18.3% ;
; Maximum fan-out ; 55 ;
; Highest non-global fan-out ; 41 ;
; Total fan-out ; 661 ;
; Average fan-out ; 2.77 ;
; Average interconnect usage (total/H/V) ; 23.0% / 25.2% / 20.7% ;
; Peak interconnect usage (total/H/V) ; 23.0% / 25.2% / 20.7% ;
; Maximum fan-out ; 61 ;
; Highest non-global fan-out ; 43 ;
; Total fan-out ; 699 ;
; Average fan-out ; 2.82 ;
+---------------------------------------------+-----------------------+
@ -203,12 +203,12 @@ The pin-out file can be found in /Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.pin
+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+----------------+
; CROW[0] ; 54 ; 2 ; 8 ; 1 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; CROW[1] ; 55 ; 2 ; 8 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[0] ; 42 ; 1 ; 5 ; 0 ; 0 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[0] ; 42 ; 1 ; 5 ; 0 ; 0 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[1] ; 36 ; 1 ; 4 ; 0 ; 2 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[2] ; 35 ; 1 ; 3 ; 0 ; 0 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[3] ; 37 ; 1 ; 4 ; 0 ; 1 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[4] ; 39 ; 1 ; 5 ; 0 ; 3 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[5] ; 38 ; 1 ; 4 ; 0 ; 0 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[4] ; 39 ; 1 ; 5 ; 0 ; 3 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[5] ; 38 ; 1 ; 4 ; 0 ; 0 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[6] ; 41 ; 1 ; 5 ; 0 ; 1 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; Din[7] ; 40 ; 1 ; 5 ; 0 ; 2 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; MAin[0] ; 49 ; 1 ; 7 ; 0 ; 2 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
@ -222,7 +222,7 @@ The pin-out file can be found in /Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.pin
; MAin[8] ; 73 ; 2 ; 8 ; 4 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; MAin[9] ; 74 ; 2 ; 8 ; 4 ; 0 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; PHI2 ; 52 ; 2 ; 8 ; 1 ; 4 ; 22 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; RCLK ; 12 ; 1 ; 1 ; 3 ; 3 ; 55 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; RCLK ; 12 ; 1 ; 1 ; 3 ; 3 ; 61 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; nCCAS ; 53 ; 2 ; 8 ; 1 ; 3 ; 11 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; nCRAS ; 67 ; 2 ; 8 ; 3 ; 2 ; 16 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
; nFWE ; 48 ; 1 ; 6 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
@ -245,7 +245,7 @@ The pin-out file can be found in /Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.pin
; LED ; 88 ; 2 ; 5 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
; RA[0] ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RA[10] ; 16 ; 1 ; 1 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RA[11] ; 7 ; 1 ; 1 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RA[11] ; 7 ; 1 ; 1 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; RA[1] ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RA[2] ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RA[3] ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
@ -253,14 +253,14 @@ The pin-out file can be found in /Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.pin
; RA[5] ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RA[6] ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RA[7] ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RA[8] ; 17 ; 1 ; 1 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; RA[8] ; 17 ; 1 ; 1 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RA[9] ; 15 ; 1 ; 1 ; 2 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RBA[0] ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RBA[1] ; 14 ; 1 ; 1 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; RCKE ; 8 ; 1 ; 1 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; RCKE ; 8 ; 1 ; 1 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RDQMH ; 2 ; 1 ; 1 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; RDQML ; 98 ; 2 ; 2 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; nRCAS ; 4 ; 1 ; 1 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; nRCAS ; 4 ; 1 ; 1 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; nRCS ; 3 ; 1 ; 1 ; 4 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; nRRAS ; 6 ; 1 ; 1 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; nRWE ; 100 ; 2 ; 2 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
@ -273,7 +273,7 @@ The pin-out file can be found in /Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.pin
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
; RD[0] ; 96 ; 2 ; 3 ; 5 ; 2 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RD~16 ; - ;
; RD[1] ; 90 ; 2 ; 4 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RD~16 ; - ;
; RD[1] ; 90 ; 2 ; 4 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; RD~16 ; - ;
; RD[2] ; 89 ; 2 ; 4 ; 5 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RD~16 ; - ;
; RD[3] ; 99 ; 2 ; 2 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RD~16 ; - ;
; RD[4] ; 92 ; 2 ; 3 ; 5 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RD~16 ; - ;
@ -426,7 +426,7 @@ Note: User assignments will override these defaults. The user specified values a
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
; |RAM2GS ; 175 (175) ; 98 ; 1 ; 63 ; 0 ; 77 (77) ; 21 (21) ; 77 (77) ; 17 (17) ; 8 (8) ; |RAM2GS ; RAM2GS ; work ;
; |RAM2GS ; 184 (184) ; 104 ; 1 ; 63 ; 0 ; 80 (80) ; 22 (22) ; 82 (82) ; 17 (17) ; 11 (11) ; |RAM2GS ; RAM2GS ; work ;
; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst ; UFM ; work ;
; |UFM_altufm_none_38r:UFM_altufm_none_38r_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component ; UFM_altufm_none_38r ; work ;
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
@ -494,32 +494,33 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; PHI2 ; Input ; (0) ;
; Din[6] ; Input ; (1) ;
; nFWE ; Input ; (1) ;
; Din[0] ; Input ; (1) ;
; Din[7] ; Input ; (1) ;
; Din[1] ; Input ; (1) ;
; Din[4] ; Input ; (1) ;
; Din[2] ; Input ; (1) ;
; Din[3] ; Input ; (1) ;
; Din[5] ; Input ; (1) ;
; Din[0] ; Input ; (1) ;
; Din[2] ; Input ; (1) ;
+---------+----------+---------------+
+-----------------------------------------------------------------------------------------------------------------+
; Control Signals ;
+------------+-------------+---------+-------------------------+--------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
+------------+-------------+---------+-------------------------+--------+----------------------+------------------+
; CmdDRDIn~1 ; LC_X5_Y1_N5 ; 4 ; Clock enable ; no ; -- ; -- ;
; CmdLEDEN~1 ; LC_X5_Y1_N3 ; 3 ; Clock enable ; no ; -- ; -- ;
; DRDIn~1 ; LC_X7_Y1_N7 ; 2 ; Clock enable ; no ; -- ; -- ;
; PHI2 ; PIN_52 ; 22 ; Clock ; yes ; Global Clock ; GCLK3 ;
; RCLK ; PIN_12 ; 55 ; Clock ; yes ; Global Clock ; GCLK0 ;
; RD~16 ; LC_X3_Y4_N5 ; 8 ; Output enable ; no ; -- ; -- ;
; Ready ; LC_X3_Y2_N8 ; 40 ; Sync. clear, Sync. load ; no ; -- ; -- ;
; always8~6 ; LC_X4_Y2_N2 ; 3 ; Clock enable ; no ; -- ; -- ;
; nCCAS ; PIN_53 ; 11 ; Clock ; yes ; Global Clock ; GCLK2 ;
; nCRAS ; PIN_67 ; 16 ; Clock ; yes ; Global Clock ; GCLK1 ;
+------------+-------------+---------+-------------------------+--------+----------------------+------------------+
+--------------------------------------------------------------------------------------------------------------------+
; Control Signals ;
+---------------+-------------+---------+-------------------------+--------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
+---------------+-------------+---------+-------------------------+--------+----------------------+------------------+
; CmdDRDIn~1 ; LC_X4_Y2_N3 ; 2 ; Clock enable ; no ; -- ; -- ;
; CmdLEDEN~1 ; LC_X4_Y1_N7 ; 3 ; Clock enable ; no ; -- ; -- ;
; CmdUFMErase~0 ; LC_X4_Y2_N6 ; 2 ; Clock enable ; no ; -- ; -- ;
; DRDIn~1 ; LC_X3_Y1_N6 ; 2 ; Clock enable ; no ; -- ; -- ;
; PHI2 ; PIN_52 ; 22 ; Clock ; yes ; Global Clock ; GCLK3 ;
; RCLK ; PIN_12 ; 61 ; Clock ; yes ; Global Clock ; GCLK0 ;
; RD~16 ; LC_X4_Y4_N4 ; 8 ; Output enable ; no ; -- ; -- ;
; Ready ; LC_X3_Y3_N6 ; 42 ; Sync. clear, Sync. load ; no ; -- ; -- ;
; always11~7 ; LC_X7_Y4_N3 ; 3 ; Clock enable ; no ; -- ; -- ;
; nCCAS ; PIN_53 ; 11 ; Clock ; yes ; Global Clock ; GCLK2 ;
; nCRAS ; PIN_67 ; 16 ; Clock ; yes ; Global Clock ; GCLK1 ;
+---------------+-------------+---------+-------------------------+--------+----------------------+------------------+
+----------------------------------------------------------------------+
@ -528,7 +529,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
+-------+----------+---------+----------------------+------------------+
; PHI2 ; PIN_52 ; 22 ; Global Clock ; GCLK3 ;
; RCLK ; PIN_12 ; 55 ; Global Clock ; GCLK0 ;
; RCLK ; PIN_12 ; 61 ; Global Clock ; GCLK0 ;
; nCCAS ; PIN_53 ; 11 ; Global Clock ; GCLK2 ;
; nCRAS ; PIN_67 ; 16 ; Global Clock ; GCLK1 ;
+-------+----------+---------+----------------------+------------------+
@ -539,109 +540,106 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+-----------------------+--------------------+
; Routing Resource Type ; Usage ;
+-----------------------+--------------------+
; C4s ; 128 / 784 ( 16 % ) ;
; Direct links ; 37 / 888 ( 4 % ) ;
; C4s ; 138 / 784 ( 18 % ) ;
; Direct links ; 41 / 888 ( 5 % ) ;
; Global clocks ; 4 / 4 ( 100 % ) ;
; LAB clocks ; 15 / 32 ( 47 % ) ;
; LUT chains ; 15 / 216 ( 7 % ) ;
; Local interconnects ; 239 / 888 ( 27 % ) ;
; R4s ; 117 / 704 ( 17 % ) ;
; LAB clocks ; 17 / 32 ( 53 % ) ;
; LUT chains ; 18 / 216 ( 8 % ) ;
; Local interconnects ; 262 / 888 ( 30 % ) ;
; R4s ; 139 / 704 ( 20 % ) ;
+-----------------------+--------------------+
+---------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+------------------------------+
; Number of Logic Elements (Average = 7.95) ; Number of LABs (Total = 22) ;
; Number of Logic Elements (Average = 7.67) ; Number of LABs (Total = 24) ;
+--------------------------------------------+------------------------------+
; 1 ; 1 ;
; 2 ; 1 ;
; 1 ; 2 ;
; 2 ; 2 ;
; 3 ; 1 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 2 ;
; 6 ; 1 ;
; 7 ; 1 ;
; 8 ; 4 ;
; 9 ; 2 ;
; 10 ; 10 ;
; 8 ; 2 ;
; 9 ; 4 ;
; 10 ; 11 ;
+--------------------------------------------+------------------------------+
+-------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+------------------------------+
; LAB-wide Signals (Average = 1.50) ; Number of LABs (Total = 22) ;
; LAB-wide Signals (Average = 1.21) ; Number of LABs (Total = 24) ;
+------------------------------------+------------------------------+
; 1 Clock ; 13 ;
; 1 Clock enable ; 6 ;
; 1 Clock ; 18 ;
; 1 Clock enable ; 2 ;
; 1 Sync. clear ; 3 ;
; 1 Sync. load ; 2 ;
; 2 Clocks ; 9 ;
; 2 Clocks ; 6 ;
+------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+------------------------------+
; Number of Signals Sourced (Average = 8.18) ; Number of LABs (Total = 22) ;
; Number of Signals Sourced (Average = 7.96) ; Number of LABs (Total = 24) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 1 ;
; 2 ; 1 ;
; 1 ; 2 ;
; 2 ; 2 ;
; 3 ; 1 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 1 ;
; 7 ; 2 ;
; 8 ; 3 ;
; 9 ; 3 ;
; 10 ; 7 ;
; 11 ; 3 ;
; 7 ; 0 ;
; 8 ; 1 ;
; 9 ; 4 ;
; 10 ; 11 ;
; 11 ; 2 ;
+---------------------------------------------+------------------------------+
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out (Average = 5.45) ; Number of LABs (Total = 22) ;
; Number of Signals Sourced Out (Average = 5.21) ; Number of LABs (Total = 24) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 1 ;
; 1 ; 3 ;
; 2 ; 1 ;
; 3 ; 2 ;
; 4 ; 2 ;
; 5 ; 4 ;
; 6 ; 4 ;
; 7 ; 5 ;
; 8 ; 3 ;
; 3 ; 3 ;
; 4 ; 1 ;
; 5 ; 3 ;
; 6 ; 3 ;
; 7 ; 7 ;
; 8 ; 2 ;
; 9 ; 1 ;
+-------------------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 9.32) ; Number of LABs (Total = 22) ;
; Number of Distinct Inputs (Average = 8.79) ; Number of LABs (Total = 24) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 3 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 1 ;
; 6 ; 1 ;
; 2 ; 4 ;
; 3 ; 2 ;
; 4 ; 1 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 1 ;
; 8 ; 4 ;
; 9 ; 3 ;
; 10 ; 0 ;
; 8 ; 1 ;
; 9 ; 2 ;
; 10 ; 3 ;
; 11 ; 2 ;
; 12 ; 1 ;
; 13 ; 3 ;
; 14 ; 1 ;
; 15 ; 0 ;
; 12 ; 3 ;
; 13 ; 1 ;
; 14 ; 2 ;
; 15 ; 1 ;
; 16 ; 1 ;
; 17 ; 0 ;
; 18 ; 0 ;
; 19 ; 1 ;
+---------------------------------------------+------------------------------+
@ -713,19 +711,19 @@ Info (332111): Found 6 clocks
Info (332111): 350.000 PHI2
Info (332111): 16.000 RCLK
Info (186079): Completed User Assigned Global Signals Promotion Operation
Info (186215): Automatically promoted signal "RCLK" to use Global clock in PIN 12 File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 41
Info (186216): Automatically promoted some destinations of signal "PHI2" to use Global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 8
Info (186217): Destination "PHI2r" may be non-global or may not use global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 14
Info (186228): Pin "PHI2" drives global clock, but is not placed in a dedicated clock pin position File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 8
Info (186216): Automatically promoted some destinations of signal "nCRAS" to use Global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11
Info (186217): Destination "LED~0" may be non-global or may not use global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 22
Info (186217): Destination "RASr" may be non-global or may not use global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 15
Info (186228): Pin "nCRAS" drives global clock, but is not placed in a dedicated clock pin position File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11
Info (186216): Automatically promoted some destinations of signal "nCCAS" to use Global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11
Info (186217): Destination "CBR" may be non-global or may not use global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 18
Info (186217): Destination "RD~16" may be non-global or may not use global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 60
Info (186217): Destination "CASr" may be non-global or may not use global clock File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 16
Info (186228): Pin "nCCAS" drives global clock, but is not placed in a dedicated clock pin position File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11
Info (186215): Automatically promoted signal "RCLK" to use Global clock in PIN 12 File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 41
Info (186216): Automatically promoted some destinations of signal "PHI2" to use Global clock File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 8
Info (186217): Destination "PHI2r" may be non-global or may not use global clock File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 14
Info (186228): Pin "PHI2" drives global clock, but is not placed in a dedicated clock pin position File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 8
Info (186216): Automatically promoted some destinations of signal "nCRAS" to use Global clock File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11
Info (186217): Destination "LED~0" may be non-global or may not use global clock File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 22
Info (186217): Destination "RASr" may be non-global or may not use global clock File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 15
Info (186228): Pin "nCRAS" drives global clock, but is not placed in a dedicated clock pin position File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11
Info (186216): Automatically promoted some destinations of signal "nCCAS" to use Global clock File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11
Info (186217): Destination "CBR" may be non-global or may not use global clock File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 18
Info (186217): Destination "RD~16" may be non-global or may not use global clock File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 60
Info (186217): Destination "CASr" may be non-global or may not use global clock File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 16
Info (186228): Pin "nCCAS" drives global clock, but is not placed in a dedicated clock pin position File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 11
Info (186079): Completed Auto Global Promotion Operation
Info (176234): Starting register packing
Info (186468): Started processing fast register assignments
@ -739,24 +737,24 @@ Info (170191): Fitter placement operations beginning
Info (170137): Fitter placement was successful
Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
Info (170193): Fitter routing operations beginning
Info (170195): Router estimated average interconnect usage is 16% of the available device resources
Info (170196): Router estimated peak interconnect usage is 16% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
Info (170195): Router estimated average interconnect usage is 19% of the available device resources
Info (170196): Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info (170201): Optimizations that may affect the design's routability were skipped
Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
Info (11888): Total time spent on timing analysis during the Fitter is 0.78 seconds.
Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
Info (11888): Total time spent on timing analysis during the Fitter is 0.40 seconds.
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
Info (144001): Generated suppressed messages file /Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg
Info (144001): Generated suppressed messages file C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg
Info: Quartus Prime Fitter was successful. 0 errors, 1 warning
Info: Peak virtual memory: 13770 megabytes
Info: Processing ended: Thu Sep 21 05:38:24 2023
Info: Elapsed time: 00:00:05
Info: Total CPU time (on all processors): 00:00:04
Info: Peak virtual memory: 1157 megabytes
Info: Processing ended: Fri Sep 29 15:17:54 2023
Info: Elapsed time: 00:00:03
Info: Total CPU time (on all processors): 00:00:03
+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in /Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg.
The suppressed messages can be found in C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.fit.smsg.

6
CPLD/MAXV/output_files/RAM2GS.fit.summary
View File

@ -1,11 +1,11 @@
Fitter Status : Successful - Thu Sep 21 05:38:24 2023
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Fitter Status : Successful - Fri Sep 29 15:17:53 2023
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Revision Name : RAM2GS
Top-level Entity Name : RAM2GS
Family : MAX V
Device : 5M240ZT100C5
Timing Models : Final
Total logic elements : 175 / 240 ( 73 % )
Total logic elements : 184 / 240 ( 77 % )
Total pins : 63 / 79 ( 80 % )
Total virtual pins : 0
UFM blocks : 1 / 1 ( 100 % )

92
CPLD/MAXV/output_files/RAM2GS.flow.rpt
View File

@ -1,6 +1,6 @@
Flow report for RAM2GS
Thu Sep 21 05:38:31 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Fri Sep 29 15:17:58 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
---------------------
@ -38,21 +38,21 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------------+
; Flow Summary ;
+-----------------------+---------------------------------------------+
; Flow Status ; Successful - Thu Sep 21 05:38:26 2023 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
; Revision Name ; RAM2GS ;
; Top-level Entity Name ; RAM2GS ;
; Family ; MAX V ;
; Device ; 5M240ZT100C5 ;
; Timing Models ; Final ;
; Total logic elements ; 175 / 240 ( 73 % ) ;
; Total pins ; 63 / 79 ( 80 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
+-----------------------+---------------------------------------------+
+-------------------------------------------------------------------------------------+
; Flow Summary ;
+-----------------------+-------------------------------------------------------------+
; Flow Status ; Successful - Fri Sep 29 15:17:55 2023 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
; Revision Name ; RAM2GS ;
; Top-level Entity Name ; RAM2GS ;
; Family ; MAX V ;
; Device ; 5M240ZT100C5 ;
; Timing Models ; Final ;
; Total logic elements ; 184 / 240 ( 77 % ) ;
; Total pins ; 63 / 79 ( 80 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
+-----------------------+-------------------------------------------------------------+
+-----------------------------------------+
@ -60,25 +60,25 @@ https://fpgasoftware.intel.com/eula.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 09/21/2023 05:37:48 ;
; Start date & time ; 09/29/2023 15:17:39 ;
; Main task ; Compilation ;
; Revision Name ; RAM2GS ;
+-------------------+---------------------+
+-----------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+---------------------------------------+------------------------------+---------------+-------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+---------------------------------------+------------------------------+---------------+-------------+------------+
; COMPILER_SIGNATURE_ID ; 121381084694.169528906810556 ; -- ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; NUM_PARALLEL_PROCESSORS ; 4 ; -- ; -- ; -- ;
; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 1.8V ; -- ; -- ; -- ;
; POWER_PRESET_COOLING_SOLUTION ; No Heat Sink With Still Air ; -- ; -- ; -- ;
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
+---------------------------------------+------------------------------+---------------+-------------+------------+
+--------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+---------------------------------------+---------------------------------+---------------+-------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+---------------------------------------+---------------------------------+---------------+-------------+------------+
; COMPILER_SIGNATURE_ID ; 123745752457129.169601505901700 ; -- ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; NUM_PARALLEL_PROCESSORS ; 4 ; -- ; -- ; -- ;
; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 1.8V ; -- ; -- ; -- ;
; POWER_PRESET_COOLING_SOLUTION ; No Heat Sink With Still Air ; -- ; -- ; -- ;
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
+---------------------------------------+---------------------------------+---------------+-------------+------------+
+--------------------------------------------------------------------------------------------------------------------------+
@ -86,24 +86,24 @@ https://fpgasoftware.intel.com/eula.
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:31 ; 1.0 ; 13149 MB ; 00:00:46 ;
; Fitter ; 00:00:05 ; 1.0 ; 13770 MB ; 00:00:04 ;
; Assembler ; 00:00:01 ; 1.0 ; 13092 MB ; 00:00:01 ;
; Timing Analyzer ; 00:00:03 ; 1.0 ; 13090 MB ; 00:00:02 ;
; Total ; 00:00:40 ; -- ; -- ; 00:00:53 ;
; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 560 MB ; 00:00:28 ;
; Fitter ; 00:00:02 ; 1.0 ; 1157 MB ; 00:00:03 ;
; Assembler ; 00:00:00 ; 1.0 ; 534 MB ; 00:00:01 ;
; Timing Analyzer ; 00:00:02 ; 1.0 ; 533 MB ; 00:00:01 ;
; Total ; 00:00:15 ; -- ; -- ; 00:00:33 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
+------------------------------------------------------------------------------------+
; Flow OS Summary ;
+----------------------+------------------+------------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+----------------------+------------------+------------+------------+----------------+
; Analysis & Synthesis ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ;
; Fitter ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ;
; Assembler ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ;
; Timing Analyzer ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ;
+----------------------+------------------+------------+------------+----------------+
+-----------------------------------------------------------------------------------+
; Flow OS Summary ;
+----------------------+------------------+-----------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+----------------------+------------------+-----------+------------+----------------+
; Analysis & Synthesis ; LabWin7 ; Windows 7 ; 6.1 ; x86_64 ;
; Fitter ; LabWin7 ; Windows 7 ; 6.1 ; x86_64 ;
; Assembler ; LabWin7 ; Windows 7 ; 6.1 ; x86_64 ;
; Timing Analyzer ; LabWin7 ; Windows 7 ; 6.1 ; x86_64 ;
+----------------------+------------------+-----------+------------+----------------+
------------

2
CPLD/MAXV/output_files/RAM2GS.jdi
View File

@ -1,6 +1,6 @@
<sld_project_info>
<project>
<hash md5_digest_80b="bd2f1fc6dc53c3f3eb26"/>
<hash md5_digest_80b="b20ba538bab35390d603"/>
</project>
<file_info>
<file device="5M240ZT100C5" path="RAM2GS.sof" usercode="0xFFFFFFFF"/>

146
CPLD/MAXV/output_files/RAM2GS.map.rpt
View File

@ -1,6 +1,6 @@
Analysis & Synthesis report for RAM2GS
Thu Sep 21 05:38:18 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Fri Sep 29 15:17:50 2023
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
---------------------
@ -43,19 +43,19 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+---------------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu Sep 21 05:38:18 2023 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
; Revision Name ; RAM2GS ;
; Top-level Entity Name ; RAM2GS ;
; Family ; MAX V ;
; Total logic elements ; 184 ;
; Total pins ; 63 ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
+-----------------------------+---------------------------------------------+
+-------------------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+-------------------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Fri Sep 29 15:17:50 2023 ;
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ;
; Revision Name ; RAM2GS ;
; Top-level Entity Name ; RAM2GS ;
; Family ; MAX V ;
; Total logic elements ; 196 ;
; Total pins ; 63 ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
+-----------------------------+-------------------------------------------------------------+
+------------------------------------------------------------------------------------------------------------+
@ -135,7 +135,7 @@ https://fpgasoftware.intel.com/eula.
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 4 ;
; Number detected on machine ; 8 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.00 ;
@ -146,15 +146,15 @@ https://fpgasoftware.intel.com/eula.
+----------------------------+-------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+----------------------------------+------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+----------------------------------+------------------------------------------------+---------+
; ../RAM2GS-MAX.v ; yes ; User Verilog HDL File ; //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v ; ;
; UFM.v ; yes ; User Wizard-Generated File ; //Mac/iCloud/Repos/RAM2GS/CPLD/MAXV/UFM.v ; ;
; ../RAM2GS.mif ; yes ; User Memory Initialization File ; //Mac/iCloud/Repos/RAM2GS/CPLD/MAXV/RAM2GS.mif ; ;
+----------------------------------+-----------------+----------------------------------+------------------------------------------------+---------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+----------------------------------+-------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+----------------------------------+-------------------------------------------------------------+---------+
; ../RAM2GS-MAX.v ; yes ; User Verilog HDL File ; C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v ; ;
; UFM.v ; yes ; User Wizard-Generated File ; C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v ; ;
; ../RAM2GS.mif ; yes ; User Memory Initialization File ; C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXV/RAM2GS.mif ; ;
+----------------------------------+-----------------+----------------------------------+-------------------------------------------------------------+---------+
+-----------------------------------------------------+
@ -162,34 +162,34 @@ https://fpgasoftware.intel.com/eula.
+---------------------------------------------+-------+
; Resource ; Usage ;
+---------------------------------------------+-------+
; Total logic elements ; 184 ;
; -- Combinational with no register ; 86 ;
; -- Register only ; 30 ;
; -- Combinational with a register ; 68 ;
; Total logic elements ; 196 ;
; -- Combinational with no register ; 92 ;
; -- Register only ; 34 ;
; -- Combinational with a register ; 70 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 57 ;
; -- 4 input functions ; 64 ;
; -- 3 input functions ; 46 ;
; -- 2 input functions ; 42 ;
; -- 2 input functions ; 43 ;
; -- 1 input functions ; 8 ;
; -- 0 input functions ; 1 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 168 ;
; -- normal mode ; 180 ;
; -- arithmetic mode ; 16 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 10 ;
; -- synchronous clear/load mode ; 11 ;
; -- asynchronous clear/load mode ; 0 ;
; ; ;
; Total registers ; 98 ;
; Total registers ; 104 ;
; Total logic cells in carry chains ; 17 ;
; I/O pins ; 63 ;
; UFM blocks ; 1 ;
; Maximum fan-out node ; RCLK ;
; Maximum fan-out ; 55 ;
; Total fan-out ; 662 ;
; Average fan-out ; 2.67 ;
; Maximum fan-out ; 61 ;
; Total fan-out ; 703 ;
; Average fan-out ; 2.70 ;
+---------------------------------------------+-------+
@ -198,7 +198,7 @@ https://fpgasoftware.intel.com/eula.
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
; |RAM2GS ; 184 (184) ; 98 ; 1 ; 63 ; 0 ; 86 (86) ; 30 (30) ; 68 (68) ; 17 (17) ; 0 (0) ; |RAM2GS ; RAM2GS ; work ;
; |RAM2GS ; 196 (196) ; 104 ; 1 ; 63 ; 0 ; 92 (92) ; 34 (34) ; 70 (70) ; 17 (17) ; 0 (0) ; |RAM2GS ; RAM2GS ; work ;
; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst ; UFM ; work ;
; |UFM_altufm_none_38r:UFM_altufm_none_38r_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component ; UFM_altufm_none_38r ; work ;
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
@ -219,8 +219,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 98 ;
; Number of registers using Synchronous Clear ; 6 ;
; Total registers ; 104 ;
; Number of registers using Synchronous Clear ; 7 ;
; Number of registers using Synchronous Load ; 4 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
@ -253,16 +253,14 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
+-------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "UFM:UFM_inst" ;
+---------+--------+----------+-------------------------------------------------------------------------------------+
; Port ; Type ; Severity ; Details ;
+---------+--------+----------+-------------------------------------------------------------------------------------+
; ardin ; Input ; Info ; Stuck at GND ;
; busy ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; osc ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; rtpbusy ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+---------+--------+----------+-------------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "UFM:UFM_inst" ;
+-------+--------+----------+-------------------------------------------------------------------------------------+
; Port ; Type ; Severity ; Details ;
+-------+--------+----------+-------------------------------------------------------------------------------------+
; ardin ; Input ; Info ; Stuck at GND ;
; osc ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+-------+--------+----------+-------------------------------------------------------------------------------------+
+-------------------------------+
@ -270,43 +268,43 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Info: Processing started: Thu Sep 21 05:37:47 2023
Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Info: Processing started: Fri Sep 29 15:17:39 2023
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXV -c RAM2GS
Info (20032): Parallel compilation is enabled and will use up to 4 processors
Info (12021): Found 1 design units, including 1 entities, in source file //mac/icloud/repos/ram2gs/cpld/ram2gs-max.v
Info (12023): Found entity 1: RAM2GS File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 1
Info (12021): Found 1 design units, including 1 entities, in source file /users/gwolf/documents/github/ram2gs/cpld/ram2gs-max.v
Info (12023): Found entity 1: RAM2GS File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 1
Info (12021): Found 2 design units, including 2 entities, in source file ufm.v
Info (12023): Found entity 1: UFM_altufm_none_38r File: //Mac/iCloud/Repos/RAM2GS/CPLD/MAXV/UFM.v Line: 47
Info (12023): Found entity 2: UFM File: //Mac/iCloud/Repos/RAM2GS/CPLD/MAXV/UFM.v Line: 150
Info (12023): Found entity 1: UFM_altufm_none_38r File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v Line: 47
Info (12023): Found entity 2: UFM File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v Line: 150
Info (12127): Elaborating entity "RAM2GS" for the top level hierarchy
Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst" File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 92
Info (12128): Elaborating entity "UFM_altufm_none_38r" for hierarchy "UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component" File: //Mac/iCloud/Repos/RAM2GS/CPLD/MAXV/UFM.v Line: 201
Warning (14632): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
Warning (14632): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
Warning (14632): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
Warning (14632): Output pin "Dout[3]" driven by bidirectional pin "RD[3]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
Warning (14632): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
Warning (14632): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
Warning (14632): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
Warning (14632): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
Info (21057): Implemented 248 device resources after synthesis - the final resource count might be different
Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst" File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 92
Info (12128): Elaborating entity "UFM_altufm_none_38r" for hierarchy "UFM:UFM_inst|UFM_altufm_none_38r:UFM_altufm_none_38r_component" File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v Line: 201
Warning (14632): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
Warning (14632): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
Warning (14632): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
Warning (14632): Output pin "Dout[3]" driven by bidirectional pin "RD[3]" cannot be tri-stated File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
Warning (14632): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot be tri-stated File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
Warning (14632): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
Warning (14632): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
Warning (14632): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
Info (21057): Implemented 260 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 25 input pins
Info (21059): Implemented 30 output pins
Info (21060): Implemented 8 bidirectional pins
Info (21061): Implemented 184 logic cells
Info (21061): Implemented 196 logic cells
Info (21070): Implemented 1 User Flash Memory blocks
Info (144001): Generated suppressed messages file /Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg
Info (144001): Generated suppressed messages file C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 8 warnings
Info: Peak virtual memory: 13149 megabytes
Info: Processing ended: Thu Sep 21 05:38:18 2023
Info: Elapsed time: 00:00:31
Info: Total CPU time (on all processors): 00:00:46
Info: Peak virtual memory: 560 megabytes
Info: Processing ended: Fri Sep 29 15:17:50 2023
Info: Elapsed time: 00:00:11
Info: Total CPU time (on all processors): 00:00:28
+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in /Repos/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg.
The suppressed messages can be found in C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXV/output_files/RAM2GS.map.smsg.

6
CPLD/MAXV/output_files/RAM2GS.map.smsg
View File

@ -1,3 +1,3 @@
Warning (10273): Verilog HDL warning at RAM2GS-MAX.v(61): extended using "x" or "z" File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 61
Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: //Mac/iCloud/Repos/RAM2GS/CPLD/MAXV/UFM.v Line: 73
Warning (10463): Verilog HDL Declaration warning at UFM.v(173): "program" is SystemVerilog-2005 keyword File: //Mac/iCloud/Repos/RAM2GS/CPLD/MAXV/UFM.v Line: 173
Warning (10273): Verilog HDL warning at RAM2GS-MAX.v(61): extended using "x" or "z" File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/RAM2GS-MAX.v Line: 61
Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v Line: 73
Warning (10463): Verilog HDL Declaration warning at UFM.v(173): "program" is SystemVerilog-2005 keyword File: C:/Users/GWolf/Documents/GitHub/RAM2GS/CPLD/MAXV/UFM.v Line: 173

6
CPLD/MAXV/output_files/RAM2GS.map.summary
View File

@ -1,9 +1,9 @@
Analysis & Synthesis Status : Successful - Thu Sep 21 05:38:18 2023
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Analysis & Synthesis Status : Successful - Fri Sep 29 15:17:50 2023
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
Revision Name : RAM2GS
Top-level Entity Name : RAM2GS
Family : MAX V
Total logic elements : 184
Total logic elements : 196
Total pins : 63
Total virtual pins : 0
UFM blocks : 1 / 1 ( 100 % )

2
CPLD/MAXV/output_files/RAM2GS.pin
View File

@ -58,7 +58,7 @@
-- Pin directions (input, output or bidir) are based on device operating in user mode.
---------------------------------------------------------------------------------
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition
CHIP "RAM2GS" ASSIGNED TO AN: 5M240ZT100C5
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment

BIN
CPLD/MAXV/output_files/RAM2GS.pof
View File

Binary file not shown.

1032
CPLD/MAXV/output_files/RAM2GS.sta.rpt
View File

File diff suppressed because it is too large Load Diff

40
CPLD/MAXV/output_files/RAM2GS.sta.summary
View File

@ -2,44 +2,44 @@
Timing Analyzer Summary
------------------------------------------------------------
Type : Setup 'RCLK'
Slack : -19.199
TNS : -193.279
Type : Setup 'DRCLK'
Slack : -17.454
TNS : -17.454
Type : Setup 'ARCLK'
Slack : -17.440
TNS : -17.440
Type : Setup 'ARCLK'
Slack : -17.423
TNS : -17.423
Type : Setup 'RCLK'
Slack : -15.806
TNS : -201.988
Type : Setup 'nCRAS'
Slack : -0.922
TNS : -0.922
Slack : -1.413
TNS : -2.367
Type : Setup 'PHI2'
Slack : 0.616
Slack : 2.092
TNS : 0.000
Type : Hold 'DRCLK'
Slack : -14.753
TNS : -14.753
Type : Hold 'ARCLK'
Slack : -14.577
TNS : -14.577
Type : Hold 'DRCLK'
Slack : -14.560
TNS : -14.560
Type : Hold 'PHI2'
Slack : -2.450
TNS : -5.440
Slack : -1.628
TNS : -4.762
Type : Hold 'nCRAS'
Slack : -0.233
TNS : -0.929
Slack : 0.169
TNS : 0.000
Type : Hold 'RCLK'
Slack : 2.155
Slack : 2.126
TNS : 0.000
Type : Minimum Pulse Width 'RCLK'

4
CPLD/RAM2GS-MAX.v
View File

@ -20,7 +20,7 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
/* Activity LED */
reg LEDEN = 0;
output LED;
assign LED = !(!nCRAS && !CBR && LEDEN);
assign LED = !(!nCRAS && !CBR && LEDEN && Ready);
/* 65816 Data */
input [7:0] Din;
@ -170,7 +170,7 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
always @(posedge RCLK) begin
// Wait ~4.178ms (at 62.5 MHz) before starting init sequence
FS <= FS+18'h1;
if (FS[17:10] == 8'hFF) InitReady <= 1'b1;
if (FS[17:10]==8'hFF) InitReady <= 1'b1;
end
/* SDRAM CKE */