Fixed failure to rewrite settings after UFM erase
This commit is contained in:
Zane Kaminski
parent
926fac8bbe
commit
97fe10f40a
Binary file not shown.
|
|
@ -1,5 +1,5 @@
|
|||
Assembler report for RAM2GS
|
||||
Thu Sep 21 05:38:25 2023
|
||||
Fri Sep 29 09:33:25 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
|
||||
|
||||
|
|
@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula.
|
|||
+---------------------------------------------------------------+
|
||||
; Assembler Summary ;
|
||||
+-----------------------+---------------------------------------+
|
||||
; Assembler Status ; Successful - Thu Sep 21 05:38:25 2023 ;
|
||||
; Assembler Status ; Successful - Fri Sep 29 09:33:25 2023 ;
|
||||
; Revision Name ; RAM2GS ;
|
||||
; Top-level Entity Name ; RAM2GS ;
|
||||
; Family ; MAX II ;
|
||||
|
|
@ -67,8 +67,8 @@ https://fpgasoftware.intel.com/eula.
|
|||
+----------------+-----------------------------------------------------------+
|
||||
; Option ; Setting ;
|
||||
+----------------+-----------------------------------------------------------+
|
||||
; JTAG usercode ; 0x00172E3B ;
|
||||
; Checksum ; 0x0017312B ;
|
||||
; JTAG usercode ; 0x001726D4 ;
|
||||
; Checksum ; 0x00172A4C ;
|
||||
+----------------+-----------------------------------------------------------+
|
||||
|
||||
|
||||
|
|
@ -78,13 +78,13 @@ https://fpgasoftware.intel.com/eula.
|
|||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime Assembler
|
||||
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Info: Processing started: Thu Sep 21 05:38:24 2023
|
||||
Info: Processing started: Fri Sep 29 09:33:24 2023
|
||||
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2GS-MAXII -c RAM2GS
|
||||
Info (115031): Writing out detailed assembly data for power analysis
|
||||
Info (115030): Assembler is generating device programming files
|
||||
Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings
|
||||
Info: Peak virtual memory: 13095 megabytes
|
||||
Info: Processing ended: Thu Sep 21 05:38:25 2023
|
||||
Info: Peak virtual memory: 13094 megabytes
|
||||
Info: Processing ended: Fri Sep 29 09:33:25 2023
|
||||
Info: Elapsed time: 00:00:01
|
||||
Info: Total CPU time (on all processors): 00:00:01
|
||||
|
||||
|
|
|
|||
|
|
@ -1 +1 @@
|
|||
Thu Sep 21 05:38:31 2023
|
||||
Fri Sep 29 09:33:28 2023
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
Fitter report for RAM2GS
|
||||
Thu Sep 21 05:38:22 2023
|
||||
Fri Sep 29 09:33:23 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
|
||||
|
||||
|
|
@ -59,14 +59,14 @@ https://fpgasoftware.intel.com/eula.
|
|||
+---------------------------------------------------------------------+
|
||||
; Fitter Summary ;
|
||||
+-----------------------+---------------------------------------------+
|
||||
; Fitter Status ; Successful - Thu Sep 21 05:38:22 2023 ;
|
||||
; Fitter Status ; Successful - Fri Sep 29 09:33:23 2023 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
||||
; Revision Name ; RAM2GS ;
|
||||
; Top-level Entity Name ; RAM2GS ;
|
||||
; Family ; MAX II ;
|
||||
; Device ; EPM240T100C5 ;
|
||||
; Timing Models ; Final ;
|
||||
; Total logic elements ; 175 / 240 ( 73 % ) ;
|
||||
; Total logic elements ; 185 / 240 ( 77 % ) ;
|
||||
; Total pins ; 63 / 80 ( 79 % ) ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 1 / 1 ( 100 % ) ;
|
||||
|
|
@ -131,13 +131,13 @@ https://fpgasoftware.intel.com/eula.
|
|||
; Number detected on machine ; 4 ;
|
||||
; Maximum allowed ; 4 ;
|
||||
; ; ;
|
||||
; Average used ; 1.03 ;
|
||||
; Average used ; 1.06 ;
|
||||
; Maximum used ; 4 ;
|
||||
; ; ;
|
||||
; Usage by Processor ; % Time Used ;
|
||||
; Processor 1 ; 100.0% ;
|
||||
; Processor 2 ; 1.2% ;
|
||||
; Processors 3-4 ; 1.1% ;
|
||||
; Processor 2 ; 2.8% ;
|
||||
; Processors 3-4 ; 1.8% ;
|
||||
+----------------------------+-------------+
|
||||
|
||||
|
||||
|
|
@ -152,28 +152,28 @@ The pin-out file can be found in /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pi
|
|||
+---------------------------------------------+-----------------------+
|
||||
; Resource ; Usage ;
|
||||
+---------------------------------------------+-----------------------+
|
||||
; Total logic elements ; 175 / 240 ( 73 % ) ;
|
||||
; -- Combinational with no register ; 77 ;
|
||||
; -- Register only ; 21 ;
|
||||
; -- Combinational with a register ; 77 ;
|
||||
; Total logic elements ; 185 / 240 ( 77 % ) ;
|
||||
; -- Combinational with no register ; 81 ;
|
||||
; -- Register only ; 22 ;
|
||||
; -- Combinational with a register ; 82 ;
|
||||
; ; ;
|
||||
; Logic element usage by number of LUT inputs ; ;
|
||||
; -- 4 input functions ; 57 ;
|
||||
; -- 3 input functions ; 46 ;
|
||||
; -- 4 input functions ; 62 ;
|
||||
; -- 3 input functions ; 50 ;
|
||||
; -- 2 input functions ; 42 ;
|
||||
; -- 1 input functions ; 8 ;
|
||||
; -- 0 input functions ; 1 ;
|
||||
; ; ;
|
||||
; Logic elements by mode ; ;
|
||||
; -- normal mode ; 159 ;
|
||||
; -- normal mode ; 169 ;
|
||||
; -- arithmetic mode ; 16 ;
|
||||
; -- qfbk mode ; 8 ;
|
||||
; -- qfbk mode ; 11 ;
|
||||
; -- register cascade mode ; 0 ;
|
||||
; -- synchronous clear/load mode ; 27 ;
|
||||
; -- synchronous clear/load mode ; 33 ;
|
||||
; -- asynchronous clear/load mode ; 0 ;
|
||||
; ; ;
|
||||
; Total registers ; 98 / 240 ( 41 % ) ;
|
||||
; Total LABs ; 21 / 24 ( 88 % ) ;
|
||||
; Total registers ; 104 / 240 ( 43 % ) ;
|
||||
; Total LABs ; 23 / 24 ( 96 % ) ;
|
||||
; Logic elements in carry chains ; 17 ;
|
||||
; Virtual pins ; 0 ;
|
||||
; I/O pins ; 63 / 80 ( 79 % ) ;
|
||||
|
|
@ -187,12 +187,12 @@ The pin-out file can be found in /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pi
|
|||
; Global signals ; 4 ;
|
||||
; -- Global clocks ; 4 / 4 ( 100 % ) ;
|
||||
; JTAGs ; 0 / 1 ( 0 % ) ;
|
||||
; Average interconnect usage (total/H/V) ; 19.4% / 20.4% / 18.3% ;
|
||||
; Peak interconnect usage (total/H/V) ; 19.4% / 20.4% / 18.3% ;
|
||||
; Maximum fan-out ; 55 ;
|
||||
; Highest non-global fan-out ; 41 ;
|
||||
; Total fan-out ; 661 ;
|
||||
; Average fan-out ; 2.77 ;
|
||||
; Average interconnect usage (total/H/V) ; 20.9% / 20.7% / 21.2% ;
|
||||
; Peak interconnect usage (total/H/V) ; 20.9% / 20.7% / 21.2% ;
|
||||
; Maximum fan-out ; 61 ;
|
||||
; Highest non-global fan-out ; 42 ;
|
||||
; Total fan-out ; 701 ;
|
||||
; Average fan-out ; 2.82 ;
|
||||
+---------------------------------------------+-----------------------+
|
||||
|
||||
|
||||
|
|
@ -203,12 +203,12 @@ The pin-out file can be found in /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pi
|
|||
+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+----------------+
|
||||
; CROW[0] ; 54 ; 2 ; 8 ; 1 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; CROW[1] ; 55 ; 2 ; 8 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[0] ; 42 ; 1 ; 5 ; 0 ; 0 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[0] ; 42 ; 1 ; 5 ; 0 ; 0 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[1] ; 36 ; 1 ; 4 ; 0 ; 2 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[2] ; 35 ; 1 ; 3 ; 0 ; 0 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[3] ; 37 ; 1 ; 4 ; 0 ; 1 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[4] ; 39 ; 1 ; 5 ; 0 ; 3 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[5] ; 38 ; 1 ; 4 ; 0 ; 0 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[4] ; 39 ; 1 ; 5 ; 0 ; 3 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[5] ; 38 ; 1 ; 4 ; 0 ; 0 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[6] ; 41 ; 1 ; 5 ; 0 ; 1 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; Din[7] ; 40 ; 1 ; 5 ; 0 ; 2 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; MAin[0] ; 49 ; 1 ; 7 ; 0 ; 2 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
|
|
@ -222,10 +222,10 @@ The pin-out file can be found in /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pi
|
|||
; MAin[8] ; 73 ; 2 ; 8 ; 4 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; MAin[9] ; 74 ; 2 ; 8 ; 4 ; 0 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; PHI2 ; 52 ; 2 ; 8 ; 1 ; 4 ; 22 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; RCLK ; 12 ; 1 ; 1 ; 3 ; 3 ; 55 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; RCLK ; 12 ; 1 ; 1 ; 3 ; 3 ; 61 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; nCCAS ; 53 ; 2 ; 8 ; 1 ; 3 ; 11 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; nCRAS ; 67 ; 2 ; 8 ; 3 ; 2 ; 16 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; nFWE ; 48 ; 1 ; 6 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
; nFWE ; 48 ; 1 ; 6 ; 0 ; 0 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ;
|
||||
+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+----------------+
|
||||
|
||||
|
||||
|
|
@ -242,8 +242,8 @@ The pin-out file can be found in /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pi
|
|||
; Dout[5] ; 28 ; 1 ; 2 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; Dout[6] ; 34 ; 1 ; 3 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; Dout[7] ; 43 ; 1 ; 6 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; LED ; 88 ; 2 ; 5 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; RA[0] ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; LED ; 88 ; 2 ; 5 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RA[0] ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; RA[10] ; 16 ; 1 ; 1 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; RA[11] ; 7 ; 1 ; 1 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; RA[1] ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
|
|
@ -251,8 +251,8 @@ The pin-out file can be found in /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pi
|
|||
; RA[3] ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; RA[4] ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; RA[5] ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; RA[6] ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RA[7] ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RA[6] ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; RA[7] ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; RA[8] ; 17 ; 1 ; 1 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
|
||||
; RA[9] ; 15 ; 1 ; 1 ; 2 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
; RBA[0] ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
|
||||
|
|
@ -273,7 +273,7 @@ The pin-out file can be found in /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.pi
|
|||
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
|
||||
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
|
||||
; RD[0] ; 96 ; 2 ; 3 ; 5 ; 2 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RD~16 ; - ;
|
||||
; RD[1] ; 90 ; 2 ; 4 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; RD~16 ; - ;
|
||||
; RD[1] ; 90 ; 2 ; 4 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RD~16 ; - ;
|
||||
; RD[2] ; 89 ; 2 ; 4 ; 5 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RD~16 ; - ;
|
||||
; RD[3] ; 99 ; 2 ; 2 ; 5 ; 1 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RD~16 ; - ;
|
||||
; RD[4] ; 92 ; 2 ; 3 ; 5 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RD~16 ; - ;
|
||||
|
|
@ -423,7 +423,7 @@ Note: User assignments will override these defaults. The user specified values a
|
|||
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
|
||||
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
|
||||
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
|
||||
; |RAM2GS ; 175 (175) ; 98 ; 1 ; 63 ; 0 ; 77 (77) ; 21 (21) ; 77 (77) ; 17 (17) ; 8 (8) ; |RAM2GS ; RAM2GS ; work ;
|
||||
; |RAM2GS ; 185 (185) ; 104 ; 1 ; 63 ; 0 ; 81 (81) ; 22 (22) ; 82 (82) ; 17 (17) ; 11 (11) ; |RAM2GS ; RAM2GS ; work ;
|
||||
; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst ; UFM ; work ;
|
||||
; |UFM_altufm_none_unv:UFM_altufm_none_unv_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component ; UFM_altufm_none_unv ; work ;
|
||||
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
|
||||
|
|
@ -490,33 +490,34 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|||
; CROW[1] ; Input ; (1) ;
|
||||
; PHI2 ; Input ; (0) ;
|
||||
; Din[6] ; Input ; (1) ;
|
||||
; nFWE ; Input ; (1) ;
|
||||
; Din[0] ; Input ; (1) ;
|
||||
; Din[7] ; Input ; (1) ;
|
||||
; Din[1] ; Input ; (1) ;
|
||||
; Din[4] ; Input ; (1) ;
|
||||
; Din[2] ; Input ; (1) ;
|
||||
; nFWE ; Input ; (1) ;
|
||||
; Din[3] ; Input ; (1) ;
|
||||
; Din[5] ; Input ; (1) ;
|
||||
; Din[0] ; Input ; (1) ;
|
||||
; Din[2] ; Input ; (1) ;
|
||||
+---------+----------+---------------+
|
||||
|
||||
|
||||
+-----------------------------------------------------------------------------------------------------------------+
|
||||
; Control Signals ;
|
||||
+------------+-------------+---------+-------------------------+--------+----------------------+------------------+
|
||||
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
|
||||
+------------+-------------+---------+-------------------------+--------+----------------------+------------------+
|
||||
; CmdDRDIn~1 ; LC_X4_Y1_N0 ; 4 ; Clock enable ; no ; -- ; -- ;
|
||||
; CmdLEDEN~1 ; LC_X4_Y1_N8 ; 3 ; Clock enable ; no ; -- ; -- ;
|
||||
; DRDIn~1 ; LC_X3_Y1_N4 ; 2 ; Clock enable ; no ; -- ; -- ;
|
||||
; PHI2 ; PIN_52 ; 22 ; Clock ; yes ; Global Clock ; GCLK3 ;
|
||||
; RCLK ; PIN_12 ; 55 ; Clock ; yes ; Global Clock ; GCLK0 ;
|
||||
; RD~16 ; LC_X3_Y4_N0 ; 8 ; Output enable ; no ; -- ; -- ;
|
||||
; Ready ; LC_X3_Y2_N8 ; 40 ; Sync. clear, Sync. load ; no ; -- ; -- ;
|
||||
; always8~6 ; LC_X4_Y2_N7 ; 3 ; Clock enable ; no ; -- ; -- ;
|
||||
; nCCAS ; PIN_53 ; 11 ; Clock ; yes ; Global Clock ; GCLK1 ;
|
||||
; nCRAS ; PIN_67 ; 16 ; Clock ; yes ; Global Clock ; GCLK2 ;
|
||||
+------------+-------------+---------+-------------------------+--------+----------------------+------------------+
|
||||
+--------------------------------------------------------------------------------------------------------------------+
|
||||
; Control Signals ;
|
||||
+---------------+-------------+---------+-------------------------+--------+----------------------+------------------+
|
||||
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
|
||||
+---------------+-------------+---------+-------------------------+--------+----------------------+------------------+
|
||||
; CmdDRDIn~1 ; LC_X6_Y3_N7 ; 2 ; Clock enable ; no ; -- ; -- ;
|
||||
; CmdLEDEN~1 ; LC_X5_Y2_N7 ; 3 ; Clock enable ; no ; -- ; -- ;
|
||||
; CmdUFMErase~0 ; LC_X6_Y3_N5 ; 2 ; Clock enable ; no ; -- ; -- ;
|
||||
; DRDIn~1 ; LC_X5_Y1_N9 ; 2 ; Clock enable ; no ; -- ; -- ;
|
||||
; PHI2 ; PIN_52 ; 22 ; Clock ; yes ; Global Clock ; GCLK3 ;
|
||||
; RCLK ; PIN_12 ; 61 ; Clock ; yes ; Global Clock ; GCLK0 ;
|
||||
; RD~16 ; LC_X4_Y4_N4 ; 8 ; Output enable ; no ; -- ; -- ;
|
||||
; Ready ; LC_X3_Y2_N8 ; 41 ; Sync. clear, Sync. load ; no ; -- ; -- ;
|
||||
; always11~8 ; LC_X6_Y4_N8 ; 3 ; Clock enable ; no ; -- ; -- ;
|
||||
; nCCAS ; PIN_53 ; 11 ; Clock ; yes ; Global Clock ; GCLK1 ;
|
||||
; nCRAS ; PIN_67 ; 16 ; Clock ; yes ; Global Clock ; GCLK2 ;
|
||||
+---------------+-------------+---------+-------------------------+--------+----------------------+------------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------+
|
||||
|
|
@ -525,7 +526,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|||
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
|
||||
+-------+----------+---------+----------------------+------------------+
|
||||
; PHI2 ; PIN_52 ; 22 ; Global Clock ; GCLK3 ;
|
||||
; RCLK ; PIN_12 ; 55 ; Global Clock ; GCLK0 ;
|
||||
; RCLK ; PIN_12 ; 61 ; Global Clock ; GCLK0 ;
|
||||
; nCCAS ; PIN_53 ; 11 ; Global Clock ; GCLK1 ;
|
||||
; nCRAS ; PIN_67 ; 16 ; Global Clock ; GCLK2 ;
|
||||
+-------+----------+---------+----------------------+------------------+
|
||||
|
|
@ -536,112 +537,110 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|||
+-----------------------+--------------------+
|
||||
; Routing Resource Type ; Usage ;
|
||||
+-----------------------+--------------------+
|
||||
; C4s ; 120 / 784 ( 15 % ) ;
|
||||
; Direct links ; 34 / 888 ( 4 % ) ;
|
||||
; C4s ; 143 / 784 ( 18 % ) ;
|
||||
; Direct links ; 42 / 888 ( 5 % ) ;
|
||||
; Global clocks ; 4 / 4 ( 100 % ) ;
|
||||
; LAB clocks ; 12 / 32 ( 38 % ) ;
|
||||
; LUT chains ; 11 / 216 ( 5 % ) ;
|
||||
; Local interconnects ; 232 / 888 ( 26 % ) ;
|
||||
; R4s ; 117 / 704 ( 17 % ) ;
|
||||
; LAB clocks ; 14 / 32 ( 44 % ) ;
|
||||
; LUT chains ; 13 / 216 ( 6 % ) ;
|
||||
; Local interconnects ; 254 / 888 ( 29 % ) ;
|
||||
; R4s ; 129 / 704 ( 18 % ) ;
|
||||
+-----------------------+--------------------+
|
||||
|
||||
|
||||
+---------------------------------------------------------------------------+
|
||||
; LAB Logic Elements ;
|
||||
+--------------------------------------------+------------------------------+
|
||||
; Number of Logic Elements (Average = 8.33) ; Number of LABs (Total = 21) ;
|
||||
; Number of Logic Elements (Average = 8.04) ; Number of LABs (Total = 23) ;
|
||||
+--------------------------------------------+------------------------------+
|
||||
; 1 ; 0 ;
|
||||
; 2 ; 3 ;
|
||||
; 3 ; 0 ;
|
||||
; 2 ; 2 ;
|
||||
; 3 ; 1 ;
|
||||
; 4 ; 0 ;
|
||||
; 5 ; 1 ;
|
||||
; 5 ; 2 ;
|
||||
; 6 ; 0 ;
|
||||
; 7 ; 2 ;
|
||||
; 8 ; 0 ;
|
||||
; 9 ; 0 ;
|
||||
; 10 ; 15 ;
|
||||
; 7 ; 3 ;
|
||||
; 8 ; 1 ;
|
||||
; 9 ; 1 ;
|
||||
; 10 ; 13 ;
|
||||
+--------------------------------------------+------------------------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------+
|
||||
; LAB-wide Signals ;
|
||||
+------------------------------------+------------------------------+
|
||||
; LAB-wide Signals (Average = 1.24) ; Number of LABs (Total = 21) ;
|
||||
; LAB-wide Signals (Average = 1.39) ; Number of LABs (Total = 23) ;
|
||||
+------------------------------------+------------------------------+
|
||||
; 1 Clock ; 12 ;
|
||||
; 1 Clock enable ; 3 ;
|
||||
; 1 Clock ; 14 ;
|
||||
; 1 Clock enable ; 4 ;
|
||||
; 1 Sync. clear ; 3 ;
|
||||
; 2 Clocks ; 8 ;
|
||||
; 1 Sync. load ; 2 ;
|
||||
; 2 Clocks ; 9 ;
|
||||
+------------------------------------+------------------------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------+
|
||||
; LAB Signals Sourced ;
|
||||
+---------------------------------------------+------------------------------+
|
||||
; Number of Signals Sourced (Average = 8.57) ; Number of LABs (Total = 21) ;
|
||||
+---------------------------------------------+------------------------------+
|
||||
; 0 ; 0 ;
|
||||
; 1 ; 0 ;
|
||||
; 2 ; 3 ;
|
||||
; 3 ; 0 ;
|
||||
; 4 ; 0 ;
|
||||
; 5 ; 1 ;
|
||||
; 6 ; 0 ;
|
||||
; 7 ; 2 ;
|
||||
; 8 ; 0 ;
|
||||
; 9 ; 0 ;
|
||||
; 10 ; 12 ;
|
||||
; 11 ; 1 ;
|
||||
; 12 ; 2 ;
|
||||
+---------------------------------------------+------------------------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------+
|
||||
; LAB Signals Sourced Out ;
|
||||
+-------------------------------------------------+------------------------------+
|
||||
; Number of Signals Sourced Out (Average = 5.62) ; Number of LABs (Total = 21) ;
|
||||
+-------------------------------------------------+------------------------------+
|
||||
; 0 ; 0 ;
|
||||
; 1 ; 1 ;
|
||||
; 2 ; 2 ;
|
||||
; 3 ; 1 ;
|
||||
; 4 ; 2 ;
|
||||
; 5 ; 2 ;
|
||||
; 6 ; 5 ;
|
||||
; 7 ; 5 ;
|
||||
; 8 ; 2 ;
|
||||
; 9 ; 0 ;
|
||||
; 10 ; 0 ;
|
||||
; 11 ; 1 ;
|
||||
+-------------------------------------------------+------------------------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------+
|
||||
; LAB Distinct Inputs ;
|
||||
+---------------------------------------------+------------------------------+
|
||||
; Number of Distinct Inputs (Average = 9.43) ; Number of LABs (Total = 21) ;
|
||||
; Number of Signals Sourced (Average = 8.35) ; Number of LABs (Total = 23) ;
|
||||
+---------------------------------------------+------------------------------+
|
||||
; 0 ; 0 ;
|
||||
; 1 ; 0 ;
|
||||
; 2 ; 2 ;
|
||||
; 3 ; 1 ;
|
||||
; 4 ; 0 ;
|
||||
; 5 ; 1 ;
|
||||
; 6 ; 2 ;
|
||||
; 7 ; 0 ;
|
||||
; 8 ; 2 ;
|
||||
; 5 ; 2 ;
|
||||
; 6 ; 0 ;
|
||||
; 7 ; 2 ;
|
||||
; 8 ; 1 ;
|
||||
; 9 ; 2 ;
|
||||
; 10 ; 2 ;
|
||||
; 10 ; 9 ;
|
||||
; 11 ; 3 ;
|
||||
; 12 ; 1 ;
|
||||
+---------------------------------------------+------------------------------+
|
||||
|
||||
|
||||
+--------------------------------------------------------------------------------+
|
||||
; LAB Signals Sourced Out ;
|
||||
+-------------------------------------------------+------------------------------+
|
||||
; Number of Signals Sourced Out (Average = 5.52) ; Number of LABs (Total = 23) ;
|
||||
+-------------------------------------------------+------------------------------+
|
||||
; 0 ; 0 ;
|
||||
; 1 ; 0 ;
|
||||
; 2 ; 2 ;
|
||||
; 3 ; 1 ;
|
||||
; 4 ; 3 ;
|
||||
; 5 ; 4 ;
|
||||
; 6 ; 6 ;
|
||||
; 7 ; 5 ;
|
||||
; 8 ; 1 ;
|
||||
; 9 ; 1 ;
|
||||
+-------------------------------------------------+------------------------------+
|
||||
|
||||
|
||||
+----------------------------------------------------------------------------+
|
||||
; LAB Distinct Inputs ;
|
||||
+---------------------------------------------+------------------------------+
|
||||
; Number of Distinct Inputs (Average = 9.48) ; Number of LABs (Total = 23) ;
|
||||
+---------------------------------------------+------------------------------+
|
||||
; 0 ; 0 ;
|
||||
; 1 ; 0 ;
|
||||
; 2 ; 2 ;
|
||||
; 3 ; 1 ;
|
||||
; 4 ; 1 ;
|
||||
; 5 ; 1 ;
|
||||
; 6 ; 0 ;
|
||||
; 7 ; 2 ;
|
||||
; 8 ; 1 ;
|
||||
; 9 ; 4 ;
|
||||
; 10 ; 1 ;
|
||||
; 11 ; 2 ;
|
||||
; 12 ; 3 ;
|
||||
; 13 ; 2 ;
|
||||
; 12 ; 1 ;
|
||||
; 13 ; 5 ;
|
||||
; 14 ; 0 ;
|
||||
; 15 ; 0 ;
|
||||
; 16 ; 0 ;
|
||||
; 17 ; 1 ;
|
||||
; 18 ; 0 ;
|
||||
; 19 ; 1 ;
|
||||
; 18 ; 1 ;
|
||||
+---------------------------------------------+------------------------------+
|
||||
|
||||
|
||||
|
|
@ -729,7 +728,7 @@ Info (176234): Starting register packing
|
|||
Info (186468): Started processing fast register assignments
|
||||
Info (186469): Finished processing fast register assignments
|
||||
Info (176235): Finished register packing
|
||||
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
|
||||
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00
|
||||
Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
|
||||
Info (170189): Fitter placement preparation operations beginning
|
||||
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
|
||||
|
|
@ -737,18 +736,18 @@ Info (170191): Fitter placement operations beginning
|
|||
Info (170137): Fitter placement was successful
|
||||
Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
|
||||
Info (170193): Fitter routing operations beginning
|
||||
Info (170195): Router estimated average interconnect usage is 17% of the available device resources
|
||||
Info (170196): Router estimated peak interconnect usage is 17% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
|
||||
Info (170195): Router estimated average interconnect usage is 19% of the available device resources
|
||||
Info (170196): Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
|
||||
Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
|
||||
Info (170201): Optimizations that may affect the design's routability were skipped
|
||||
Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
|
||||
Info (11888): Total time spent on timing analysis during the Fitter is 1.10 seconds.
|
||||
Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
|
||||
Info (11888): Total time spent on timing analysis during the Fitter is 0.46 seconds.
|
||||
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
|
||||
Info (144001): Generated suppressed messages file /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.fit.smsg
|
||||
Info: Quartus Prime Fitter was successful. 0 errors, 1 warning
|
||||
Info: Peak virtual memory: 13770 megabytes
|
||||
Info: Processing ended: Thu Sep 21 05:38:23 2023
|
||||
Info: Elapsed time: 00:00:05
|
||||
Info: Peak virtual memory: 13771 megabytes
|
||||
Info: Processing ended: Fri Sep 29 09:33:23 2023
|
||||
Info: Elapsed time: 00:00:03
|
||||
Info: Total CPU time (on all processors): 00:00:04
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,11 +1,11 @@
|
|||
Fitter Status : Successful - Thu Sep 21 05:38:22 2023
|
||||
Fitter Status : Successful - Fri Sep 29 09:33:23 2023
|
||||
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Revision Name : RAM2GS
|
||||
Top-level Entity Name : RAM2GS
|
||||
Family : MAX II
|
||||
Device : EPM240T100C5
|
||||
Timing Models : Final
|
||||
Total logic elements : 175 / 240 ( 73 % )
|
||||
Total logic elements : 185 / 240 ( 77 % )
|
||||
Total pins : 63 / 80 ( 79 % )
|
||||
Total virtual pins : 0
|
||||
UFM blocks : 1 / 1 ( 100 % )
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
Flow report for RAM2GS
|
||||
Thu Sep 21 05:38:29 2023
|
||||
Fri Sep 29 09:33:27 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
|
||||
|
||||
|
|
@ -41,14 +41,14 @@ https://fpgasoftware.intel.com/eula.
|
|||
+---------------------------------------------------------------------+
|
||||
; Flow Summary ;
|
||||
+-----------------------+---------------------------------------------+
|
||||
; Flow Status ; Successful - Thu Sep 21 05:38:25 2023 ;
|
||||
; Flow Status ; Successful - Fri Sep 29 09:33:25 2023 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
||||
; Revision Name ; RAM2GS ;
|
||||
; Top-level Entity Name ; RAM2GS ;
|
||||
; Family ; MAX II ;
|
||||
; Device ; EPM240T100C5 ;
|
||||
; Timing Models ; Final ;
|
||||
; Total logic elements ; 175 / 240 ( 73 % ) ;
|
||||
; Total logic elements ; 185 / 240 ( 77 % ) ;
|
||||
; Total pins ; 63 / 80 ( 79 % ) ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 1 / 1 ( 100 % ) ;
|
||||
|
|
@ -60,7 +60,7 @@ https://fpgasoftware.intel.com/eula.
|
|||
+-------------------+---------------------+
|
||||
; Option ; Setting ;
|
||||
+-------------------+---------------------+
|
||||
; Start date & time ; 09/21/2023 05:37:46 ;
|
||||
; Start date & time ; 09/29/2023 09:32:59 ;
|
||||
; Main task ; Compilation ;
|
||||
; Revision Name ; RAM2GS ;
|
||||
+-------------------+---------------------+
|
||||
|
|
@ -71,7 +71,7 @@ https://fpgasoftware.intel.com/eula.
|
|||
+---------------------------------------+------------------------------+---------------+-------------+------------+
|
||||
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
|
||||
+---------------------------------------+------------------------------+---------------+-------------+------------+
|
||||
; COMPILER_SIGNATURE_ID ; 121381084694.169528906604732 ; -- ; -- ; -- ;
|
||||
; COMPILER_SIGNATURE_ID ; 121381084694.169599437907024 ; -- ; -- ; -- ;
|
||||
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
|
||||
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
|
||||
; NUM_PARALLEL_PROCESSORS ; 4 ; -- ; -- ; -- ;
|
||||
|
|
@ -86,11 +86,11 @@ https://fpgasoftware.intel.com/eula.
|
|||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
; Analysis & Synthesis ; 00:00:31 ; 1.0 ; 13149 MB ; 00:00:47 ;
|
||||
; Fitter ; 00:00:04 ; 1.0 ; 13770 MB ; 00:00:04 ;
|
||||
; Assembler ; 00:00:01 ; 1.0 ; 13095 MB ; 00:00:01 ;
|
||||
; Timing Analyzer ; 00:00:02 ; 1.0 ; 13089 MB ; 00:00:02 ;
|
||||
; Total ; 00:00:38 ; -- ; -- ; 00:00:54 ;
|
||||
; Analysis & Synthesis ; 00:00:21 ; 1.0 ; 13133 MB ; 00:00:47 ;
|
||||
; Fitter ; 00:00:03 ; 1.1 ; 13771 MB ; 00:00:04 ;
|
||||
; Assembler ; 00:00:01 ; 1.0 ; 13094 MB ; 00:00:01 ;
|
||||
; Timing Analyzer ; 00:00:01 ; 1.0 ; 13090 MB ; 00:00:01 ;
|
||||
; Total ; 00:00:26 ; -- ; -- ; 00:00:53 ;
|
||||
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
Analysis & Synthesis report for RAM2GS
|
||||
Thu Sep 21 05:38:17 2023
|
||||
Fri Sep 29 09:33:19 2023
|
||||
Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
|
||||
|
||||
|
|
@ -46,12 +46,12 @@ https://fpgasoftware.intel.com/eula.
|
|||
+---------------------------------------------------------------------------+
|
||||
; Analysis & Synthesis Summary ;
|
||||
+-----------------------------+---------------------------------------------+
|
||||
; Analysis & Synthesis Status ; Successful - Thu Sep 21 05:38:17 2023 ;
|
||||
; Analysis & Synthesis Status ; Successful - Fri Sep 29 09:33:19 2023 ;
|
||||
; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
|
||||
; Revision Name ; RAM2GS ;
|
||||
; Top-level Entity Name ; RAM2GS ;
|
||||
; Family ; MAX II ;
|
||||
; Total logic elements ; 184 ;
|
||||
; Total logic elements ; 197 ;
|
||||
; Total pins ; 63 ;
|
||||
; Total virtual pins ; 0 ;
|
||||
; UFM blocks ; 1 / 1 ( 100 % ) ;
|
||||
|
|
@ -162,34 +162,34 @@ https://fpgasoftware.intel.com/eula.
|
|||
+---------------------------------------------+-------+
|
||||
; Resource ; Usage ;
|
||||
+---------------------------------------------+-------+
|
||||
; Total logic elements ; 184 ;
|
||||
; -- Combinational with no register ; 86 ;
|
||||
; -- Register only ; 30 ;
|
||||
; -- Combinational with a register ; 68 ;
|
||||
; Total logic elements ; 197 ;
|
||||
; -- Combinational with no register ; 93 ;
|
||||
; -- Register only ; 34 ;
|
||||
; -- Combinational with a register ; 70 ;
|
||||
; ; ;
|
||||
; Logic element usage by number of LUT inputs ; ;
|
||||
; -- 4 input functions ; 57 ;
|
||||
; -- 3 input functions ; 46 ;
|
||||
; -- 4 input functions ; 62 ;
|
||||
; -- 3 input functions ; 50 ;
|
||||
; -- 2 input functions ; 42 ;
|
||||
; -- 1 input functions ; 8 ;
|
||||
; -- 0 input functions ; 1 ;
|
||||
; ; ;
|
||||
; Logic elements by mode ; ;
|
||||
; -- normal mode ; 168 ;
|
||||
; -- normal mode ; 181 ;
|
||||
; -- arithmetic mode ; 16 ;
|
||||
; -- qfbk mode ; 0 ;
|
||||
; -- register cascade mode ; 0 ;
|
||||
; -- synchronous clear/load mode ; 10 ;
|
||||
; -- synchronous clear/load mode ; 11 ;
|
||||
; -- asynchronous clear/load mode ; 0 ;
|
||||
; ; ;
|
||||
; Total registers ; 98 ;
|
||||
; Total registers ; 104 ;
|
||||
; Total logic cells in carry chains ; 17 ;
|
||||
; I/O pins ; 63 ;
|
||||
; UFM blocks ; 1 ;
|
||||
; Maximum fan-out node ; RCLK ;
|
||||
; Maximum fan-out ; 55 ;
|
||||
; Total fan-out ; 662 ;
|
||||
; Average fan-out ; 2.67 ;
|
||||
; Maximum fan-out ; 61 ;
|
||||
; Total fan-out ; 705 ;
|
||||
; Average fan-out ; 2.70 ;
|
||||
+---------------------------------------------+-------+
|
||||
|
||||
|
||||
|
|
@ -198,7 +198,7 @@ https://fpgasoftware.intel.com/eula.
|
|||
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
|
||||
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
|
||||
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
|
||||
; |RAM2GS ; 184 (184) ; 98 ; 1 ; 63 ; 0 ; 86 (86) ; 30 (30) ; 68 (68) ; 17 (17) ; 0 (0) ; |RAM2GS ; RAM2GS ; work ;
|
||||
; |RAM2GS ; 197 (197) ; 104 ; 1 ; 63 ; 0 ; 93 (93) ; 34 (34) ; 70 (70) ; 17 (17) ; 0 (0) ; |RAM2GS ; RAM2GS ; work ;
|
||||
; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst ; UFM ; work ;
|
||||
; |UFM_altufm_none_unv:UFM_altufm_none_unv_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2GS|UFM:UFM_inst|UFM_altufm_none_unv:UFM_altufm_none_unv_component ; UFM_altufm_none_unv ; work ;
|
||||
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------+---------------------+--------------+
|
||||
|
|
@ -219,8 +219,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|||
+----------------------------------------------+-------+
|
||||
; Statistic ; Value ;
|
||||
+----------------------------------------------+-------+
|
||||
; Total registers ; 98 ;
|
||||
; Number of registers using Synchronous Clear ; 6 ;
|
||||
; Total registers ; 104 ;
|
||||
; Number of registers using Synchronous Clear ; 7 ;
|
||||
; Number of registers using Synchronous Load ; 4 ;
|
||||
; Number of registers using Asynchronous Clear ; 0 ;
|
||||
; Number of registers using Asynchronous Load ; 0 ;
|
||||
|
|
@ -247,22 +247,20 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|||
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
|
||||
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
|
||||
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
|
||||
; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |RAM2GS|S[1] ;
|
||||
; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |RAM2GS|S[0] ;
|
||||
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |RAM2GS|CmdLEDEN ;
|
||||
; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |RAM2GS|C1Submitted ;
|
||||
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
|
||||
|
||||
|
||||
+-------------------------------------------------------------------------------------------------------------------+
|
||||
; Port Connectivity Checks: "UFM:UFM_inst" ;
|
||||
+---------+--------+----------+-------------------------------------------------------------------------------------+
|
||||
; Port ; Type ; Severity ; Details ;
|
||||
+---------+--------+----------+-------------------------------------------------------------------------------------+
|
||||
; ardin ; Input ; Info ; Stuck at GND ;
|
||||
; busy ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
|
||||
; osc ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
|
||||
; rtpbusy ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
|
||||
+---------+--------+----------+-------------------------------------------------------------------------------------+
|
||||
+-----------------------------------------------------------------------------------------------------------------+
|
||||
; Port Connectivity Checks: "UFM:UFM_inst" ;
|
||||
+-------+--------+----------+-------------------------------------------------------------------------------------+
|
||||
; Port ; Type ; Severity ; Details ;
|
||||
+-------+--------+----------+-------------------------------------------------------------------------------------+
|
||||
; ardin ; Input ; Info ; Stuck at GND ;
|
||||
; osc ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
|
||||
+-------+--------+----------+-------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
+-------------------------------+
|
||||
|
|
@ -271,7 +269,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
|
|||
Info: *******************************************************************
|
||||
Info: Running Quartus Prime Analysis & Synthesis
|
||||
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Info: Processing started: Thu Sep 21 05:37:46 2023
|
||||
Info: Processing started: Fri Sep 29 09:32:58 2023
|
||||
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2GS-MAXII -c RAM2GS
|
||||
Info (20032): Parallel compilation is enabled and will use up to 4 processors
|
||||
Info (12021): Found 1 design units, including 1 entities, in source file //mac/icloud/repos/ram2gs/cpld/ram2gs-max.v
|
||||
|
|
@ -290,17 +288,17 @@ Warning (14632): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot
|
|||
Warning (14632): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
|
||||
Warning (14632): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
|
||||
Warning (14632): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated File: //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-MAX.v Line: 27
|
||||
Info (21057): Implemented 248 device resources after synthesis - the final resource count might be different
|
||||
Info (21057): Implemented 261 device resources after synthesis - the final resource count might be different
|
||||
Info (21058): Implemented 25 input pins
|
||||
Info (21059): Implemented 30 output pins
|
||||
Info (21060): Implemented 8 bidirectional pins
|
||||
Info (21061): Implemented 184 logic cells
|
||||
Info (21061): Implemented 197 logic cells
|
||||
Info (21070): Implemented 1 User Flash Memory blocks
|
||||
Info (144001): Generated suppressed messages file /Repos/RAM2GS/CPLD/MAXII/output_files/RAM2GS.map.smsg
|
||||
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 8 warnings
|
||||
Info: Peak virtual memory: 13149 megabytes
|
||||
Info: Processing ended: Thu Sep 21 05:38:17 2023
|
||||
Info: Elapsed time: 00:00:31
|
||||
Info: Peak virtual memory: 13133 megabytes
|
||||
Info: Processing ended: Fri Sep 29 09:33:19 2023
|
||||
Info: Elapsed time: 00:00:21
|
||||
Info: Total CPU time (on all processors): 00:00:47
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
Analysis & Synthesis Status : Successful - Thu Sep 21 05:38:17 2023
|
||||
Analysis & Synthesis Status : Successful - Fri Sep 29 09:33:19 2023
|
||||
Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
||||
Revision Name : RAM2GS
|
||||
Top-level Entity Name : RAM2GS
|
||||
Family : MAX II
|
||||
Total logic elements : 184
|
||||
Total logic elements : 197
|
||||
Total pins : 63
|
||||
Total virtual pins : 0
|
||||
UFM blocks : 1 / 1 ( 100 % )
|
||||
|
|
|
|||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
|
|
@ -2,44 +2,44 @@
|
|||
Timing Analyzer Summary
|
||||
------------------------------------------------------------
|
||||
|
||||
Type : Setup 'DRCLK'
|
||||
Slack : -15.744
|
||||
TNS : -15.744
|
||||
|
||||
Type : Setup 'ARCLK'
|
||||
Slack : -15.723
|
||||
TNS : -15.723
|
||||
Slack : -15.724
|
||||
TNS : -15.724
|
||||
|
||||
Type : Setup 'DRCLK'
|
||||
Slack : -15.649
|
||||
TNS : -15.649
|
||||
|
||||
Type : Setup 'RCLK'
|
||||
Slack : -7.153
|
||||
TNS : -69.927
|
||||
Slack : -7.823
|
||||
TNS : -68.940
|
||||
|
||||
Type : Setup 'nCRAS'
|
||||
Slack : 0.358
|
||||
Slack : 0.324
|
||||
TNS : 0.000
|
||||
|
||||
Type : Setup 'PHI2'
|
||||
Slack : 0.545
|
||||
Slack : 0.552
|
||||
TNS : 0.000
|
||||
|
||||
Type : Hold 'ARCLK'
|
||||
Slack : -16.277
|
||||
TNS : -16.277
|
||||
|
||||
Type : Hold 'DRCLK'
|
||||
Slack : -16.401
|
||||
TNS : -16.401
|
||||
|
||||
Type : Hold 'ARCLK'
|
||||
Slack : -16.276
|
||||
TNS : -16.276
|
||||
|
||||
Type : Hold 'PHI2'
|
||||
Slack : -0.517
|
||||
TNS : -1.433
|
||||
Slack : -0.482
|
||||
TNS : -1.385
|
||||
|
||||
Type : Hold 'nCRAS'
|
||||
Slack : 0.177
|
||||
Slack : 0.180
|
||||
TNS : 0.000
|
||||
|
||||
Type : Hold 'RCLK'
|
||||
Slack : 1.111
|
||||
Slack : 1.108
|
||||
TNS : 0.000
|
||||
|
||||
Type : Minimum Pulse Width 'RCLK'
|
||||
|
|
|
|||
|
|
@ -71,8 +71,8 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
|
|||
reg UFMErase = 0; // Rising edge starts erase. UFM+RTP must not be busy
|
||||
reg UFMProgram = 0; // Rising edge starts program. UFM+RTP must not be busy
|
||||
reg UFMOscEN = 0; // UFM oscillator enable
|
||||
wire UFMBusy; // 1 if UFM is doing user operation. Asynchronous
|
||||
wire RTPBusy; // 1 if real-time programming in progress. Asynchronous
|
||||
wire UFMBusyAsync; // 1 if UFM is doing user operation. Asynchronous
|
||||
wire RTPBusyAsync; // 1 if real-time programming in progress. Asynchronous
|
||||
wire DRDOut; // UFM data output
|
||||
// UFM oscillator always enabled
|
||||
wire UFMOsc; // UFM oscillator output (3.3-5.5 MHz)
|
||||
|
|
@ -86,12 +86,16 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
|
|||
.erase (UFMErase),
|
||||
.oscena (UFMOscEN),
|
||||
.program (UFMProgram),
|
||||
.busy (UFMBusy),
|
||||
.busy (UFMBusyAsync),
|
||||
.drdout (DRDOut),
|
||||
.osc (UFMOsc),
|
||||
.rtpbusy (RTPBusy));
|
||||
reg UFMBusyReg = 0; // UFMBusy registered to sync with RCLK
|
||||
reg RTPBusyReg = 0; // RTPBusy registered to sync with RCLK
|
||||
.rtpbusy (RTPBusyAsync));
|
||||
// UFMBusy registered to sync with RCLK
|
||||
reg UFMBusyReg0; always @(posedge RCLK) UFMBusyReg0 <= UFMBusyAsync;
|
||||
// RTPBusy registered to sync with RCLK
|
||||
reg RTPBusyReg0; always @(posedge RCLK) RTPBusyReg0 <= RTPBusyAsync;
|
||||
// UFMRTPBusy ORs both
|
||||
reg UFMRTPBusy; always @(posedge RCLK) UFMRTPBusy <= UFMBusyReg0 || RTPBusyReg0;
|
||||
|
||||
/* UFM State */
|
||||
reg UFMInitDone = 0; // 1 if UFM initialization finished
|
||||
|
|
@ -356,8 +360,10 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
|
|||
// MAX commands
|
||||
CmdLEDEN <= LEDEN;
|
||||
Cmdn8MEGEN <= n8MEGEN;
|
||||
CmdUFMErase <= Din[3];
|
||||
CmdUFMPrgm <= Din[2];
|
||||
if (!CmdUFMPrgm && !CmdUFMErase) begin
|
||||
CmdUFMErase <= Din[3];
|
||||
CmdUFMPrgm <= Din[2];
|
||||
end
|
||||
CmdDRCLK <= Din[1];
|
||||
CmdDRDIn <= Din[0];
|
||||
CmdSubmitted <= 1'b1;
|
||||
|
|
@ -374,7 +380,12 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
|
|||
end
|
||||
end
|
||||
|
||||
/* UFM command synchronization */
|
||||
reg CmdUFMPrgmSync; always @(posedge RCLK) CmdUFMPrgmSync <= CmdUFMPrgm;
|
||||
reg CmdUFMEraseSync; always @(posedge RCLK) CmdUFMEraseSync <= CmdUFMErase;
|
||||
|
||||
/* UFM Control */
|
||||
reg UFMProgStart;
|
||||
always @(posedge RCLK) begin
|
||||
if (!Ready) begin
|
||||
if (!UFMInitDone && FS[17:16]==2'b00) begin
|
||||
|
|
@ -445,6 +456,7 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
|
|||
// Don't erase or program UFM during initialization
|
||||
UFMErase <= 1'b0;
|
||||
UFMProgram <= 1'b0;
|
||||
UFMProgStart <= 1'b0;
|
||||
end else begin
|
||||
// Can only shift UFM data register now
|
||||
ARCLK <= 1'b0;
|
||||
|
|
@ -460,11 +472,16 @@ module RAM2GS(PHI2, MAin, CROW, Din, Dout,
|
|||
end
|
||||
|
||||
// UFM programming sequence
|
||||
if (CmdUFMPrgm || CmdUFMErase) begin
|
||||
if (!UFMBusyReg && !RTPBusyReg) begin
|
||||
if (UFMReqErase || CmdUFMErase) UFMErase <= 1'b1;
|
||||
else if (CmdUFMPrgm) UFMProgram <= 1'b1;
|
||||
end else if (UFMBusyReg) UFMReqErase <= 1'b0;
|
||||
if (FS[6:0]==0) begin
|
||||
if (!UFMProgStart && !UFMRTPBusy) begin
|
||||
if (CmdUFMPrgmSync) begin
|
||||
UFMErase <= UFMReqErase || CmdUFMEraseSync;
|
||||
UFMProgStart <= 1'b1;
|
||||
end else if (CmdUFMEraseSync) UFMErase <= 1'b1;
|
||||
end else if (UFMProgStart && !UFMRTPBusy) begin
|
||||
UFMErase <= 1'b0;
|
||||
if (!UFMErase) UFMProgram <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
|
|||
Loading…
Reference in New Issue