This commit is contained in:
Zane Kaminski
parent
f094702a69
commit
926fac8bbe
|
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@ -14,20 +14,41 @@ _autosave-*
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*-save.pro
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*-save.kicad_pcb
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fp-info-cache
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Hardware/*/*-backups
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# Netlist files (exported from Eeschema)
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*.net
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# Autorouter files (exported from Pcbnew)
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*.dsn
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*.ses
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# Exported BOM files
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*.xml
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# Mac
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*.DS_Store
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Documentation/~$4201DManual.docx
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cpld/db/RAM4GS.db_info
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cpld/db/RAM4GS.tmw_info
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cpld/RAM4GS.qws
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Documentation/Thumbs.db
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# Altera MAX II/V
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CPLD/MAX*/db
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CPLD/MAX*/incremental_db
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CPLD/MAX*/greybox_tmp
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# Lattice Diamond
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CPLD/LCMXO*/*.dir
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CPLD/LCMXO*/.build_status
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CPLD/LCMXO*/.run_manager.ini
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CPLD/LCMXO*/.recovery
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CPLD/LCMXO*/.spread_sheet.ini
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CPLD/LCMXO*/.spreadsheet_view.ini
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CPLD/LCMXO*/impl1/*
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!CPLD/LCMXO*/impl1/*.jed
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!CPLD/LCMXO*/impl1/*.bit
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!CPLD/LCMXO*/impl1/*.html
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!CPLD/LCMXO*/impl1/*.rpt
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!CPLD/LCMXO*/impl1/*.sdf
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!CPLD/LCMXO*/impl1/*.vo
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!CPLD/LCMXO*/impl1/*.alt
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!CPLD/LCMXO*/impl1/*.areasrr
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!CPLD/LCMXO*/impl1/*.bgn
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!CPLD/LCMXO*/impl1/*.edi
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!CPLD/LCMXO*/impl1/*.ior
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!CPLD/LCMXO*/impl1/*.mrp
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!CPLD/LCMXO*/impl1/*.pad
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!CPLD/LCMXO*/impl1/*.prf
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!CPLD/LCMXO*/impl1/*.srr
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!CPLD/LCMXO*/impl1/*.twr
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!CPLD/LCMXO*/impl1/*.tw1
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@ -0,0 +1,4 @@
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[General]
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Map.auto_tasks=MapTrace, MapVerilogSimFile
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PAR.auto_tasks=PARTrace, IOTiming
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Export.auto_tasks=IBIS, TimingSimFileVlg, Bitgen, Jedecgen
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@ -1,5 +1,5 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<BaliProject version="3.2" title="LCMXO2_640HC" device="LCMXO2-640HC-4TG100C" default_implementation="impl1">
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<BaliProject version="3.2" title="RAM2GS_LCMXO2_1200HC" device="LCMXO2-1200HC-4TG100C" default_implementation="impl1">
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<Options/>
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<Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
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<Options def_top="RAM2GS"/>
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@ -9,9 +9,6 @@
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<Source name="REFB.v" type="Verilog" type_short="Verilog">
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<Options/>
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</Source>
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<Source name="impl1/impl1.xcf" type="Programming Project File" type_short="Programming">
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<Options/>
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</Source>
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<Source name="../RAM2GS-LCMXO2.lpf" type="Logic Preference" type_short="LPF">
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<Options/>
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</Source>
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@ -19,5 +16,5 @@
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<Options/>
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</Source>
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</Implementation>
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<Strategy name="Strategy1" file="LCMXO2_640HC1.sty"/>
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<Strategy name="Strategy1" file="RAM2GS_LCMXO2_1200HC1.sty"/>
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</BaliProject>
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@ -0,0 +1,550 @@
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(edif REFB
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(edifVersion 2 0 0)
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(edifLevel 0)
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(keywordMap (keywordLevel 0))
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(status
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(written
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(timestamp 2023 9 21 4 34 49)
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(program "SCUBA" (version "Diamond (64-bit) 3.12.1.454"))))
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(comment "C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 66.7 -ufm -ufm_ebr 190 -mem_size 321 -memfile ../RAM2GS-LCMXO2.mem -memformat hex -wb -dev 1200 ")
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(library ORCLIB
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(edifLevel 0)
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(technology
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(numberDefinition))
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(cell VHI
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(cellType GENERIC)
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(view view1
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(viewType NETLIST)
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(interface
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(port Z
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(direction OUTPUT)))))
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(cell VLO
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(cellType GENERIC)
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(view view1
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(viewType NETLIST)
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(interface
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(port Z
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(direction OUTPUT)))))
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(cell EFB
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(cellType GENERIC)
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(view view1
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(viewType NETLIST)
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(interface
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(port WBCLKI
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(direction INPUT))
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(port WBRSTI
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(direction INPUT))
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(port WBCYCI
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(direction INPUT))
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(port WBSTBI
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(direction INPUT))
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(port WBWEI
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(direction INPUT))
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(port WBADRI7
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(direction INPUT))
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(port WBADRI6
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(direction INPUT))
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(port WBADRI5
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(direction INPUT))
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(port WBADRI4
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(direction INPUT))
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(port WBADRI3
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(direction INPUT))
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(port WBADRI2
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(direction INPUT))
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(port WBADRI1
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(direction INPUT))
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(port WBADRI0
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(direction INPUT))
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(port WBDATI7
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(direction INPUT))
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(port WBDATI6
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(direction INPUT))
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(port WBDATI5
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(direction INPUT))
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(port WBDATI4
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(direction INPUT))
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(port WBDATI3
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(direction INPUT))
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(port WBDATI2
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(direction INPUT))
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(port WBDATI1
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(direction INPUT))
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(port WBDATI0
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(direction INPUT))
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(port PLL0DATI7
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(direction INPUT))
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(port PLL0DATI6
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(direction INPUT))
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(port PLL0DATI5
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(direction INPUT))
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(port PLL0DATI4
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(direction INPUT))
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(port PLL0DATI3
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(direction INPUT))
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(port PLL0DATI2
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(direction INPUT))
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(port PLL0DATI1
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(direction INPUT))
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(port PLL0DATI0
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(direction INPUT))
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(port PLL0ACKI
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(direction INPUT))
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(port PLL1DATI7
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(direction INPUT))
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(port PLL1DATI6
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(direction INPUT))
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(port PLL1DATI5
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(direction INPUT))
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(port PLL1DATI4
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(direction INPUT))
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(port PLL1DATI3
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(direction INPUT))
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(port PLL1DATI2
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(direction INPUT))
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(port PLL1DATI1
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(direction INPUT))
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(port PLL1DATI0
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(direction INPUT))
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(port PLL1ACKI
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(direction INPUT))
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(port I2C1SCLI
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(direction INPUT))
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(port I2C1SDAI
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(direction INPUT))
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(port I2C2SCLI
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(direction INPUT))
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(port I2C2SDAI
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(direction INPUT))
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(port SPISCKI
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(direction INPUT))
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(port SPIMISOI
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(direction INPUT))
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(port SPIMOSII
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(direction INPUT))
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(port SPISCSN
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(direction INPUT))
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(port TCCLKI
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(direction INPUT))
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(port TCRSTN
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(direction INPUT))
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(port TCIC
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(direction INPUT))
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(port UFMSN
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(direction INPUT))
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(port WBDATO7
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(direction OUTPUT))
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(port WBDATO6
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(direction OUTPUT))
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(port WBDATO5
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(direction OUTPUT))
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(port WBDATO4
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(direction OUTPUT))
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(port WBDATO3
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(direction OUTPUT))
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(port WBDATO2
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(direction OUTPUT))
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(port WBDATO1
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(direction OUTPUT))
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(port WBDATO0
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(direction OUTPUT))
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(port WBACKO
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(direction OUTPUT))
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(port PLLCLKO
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(direction OUTPUT))
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(port PLLRSTO
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(direction OUTPUT))
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(port PLL0STBO
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(direction OUTPUT))
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(port PLL1STBO
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(direction OUTPUT))
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(port PLLWEO
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(direction OUTPUT))
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(port PLLADRO4
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(direction OUTPUT))
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(port PLLADRO3
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(direction OUTPUT))
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(port PLLADRO2
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(direction OUTPUT))
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(port PLLADRO1
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(direction OUTPUT))
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(port PLLADRO0
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(direction OUTPUT))
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(port PLLDATO7
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(direction OUTPUT))
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(port PLLDATO6
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(direction OUTPUT))
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(port PLLDATO5
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(direction OUTPUT))
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(port PLLDATO4
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(direction OUTPUT))
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(port PLLDATO3
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(direction OUTPUT))
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(port PLLDATO2
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(direction OUTPUT))
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(port PLLDATO1
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(direction OUTPUT))
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(port PLLDATO0
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(direction OUTPUT))
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(port I2C1SCLO
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(direction OUTPUT))
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(port I2C1SCLOEN
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(direction OUTPUT))
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(port I2C1SDAO
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(direction OUTPUT))
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(port I2C1SDAOEN
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(direction OUTPUT))
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(port I2C2SCLO
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(direction OUTPUT))
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(port I2C2SCLOEN
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(direction OUTPUT))
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(port I2C2SDAO
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||||
(direction OUTPUT))
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(port I2C2SDAOEN
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(direction OUTPUT))
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(port I2C1IRQO
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||||
(direction OUTPUT))
|
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(port I2C2IRQO
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||||
(direction OUTPUT))
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(port SPISCKO
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(direction OUTPUT))
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(port SPISCKEN
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||||
(direction OUTPUT))
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(port SPIMISOO
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||||
(direction OUTPUT))
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(port SPIMISOEN
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||||
(direction OUTPUT))
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(port SPIMOSIO
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||||
(direction OUTPUT))
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(port SPIMOSIEN
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||||
(direction OUTPUT))
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(port SPIMCSN7
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(direction OUTPUT))
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(port SPIMCSN6
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||||
(direction OUTPUT))
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(port SPIMCSN5
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||||
(direction OUTPUT))
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||||
(port SPIMCSN4
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||||
(direction OUTPUT))
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||||
(port SPIMCSN3
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||||
(direction OUTPUT))
|
||||
(port SPIMCSN2
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||||
(direction OUTPUT))
|
||||
(port SPIMCSN1
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||||
(direction OUTPUT))
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||||
(port SPIMCSN0
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||||
(direction OUTPUT))
|
||||
(port SPICSNEN
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||||
(direction OUTPUT))
|
||||
(port SPIIRQO
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||||
(direction OUTPUT))
|
||||
(port TCINT
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||||
(direction OUTPUT))
|
||||
(port TCOC
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||||
(direction OUTPUT))
|
||||
(port WBCUFMIRQ
|
||||
(direction OUTPUT))
|
||||
(port CFGWAKE
|
||||
(direction OUTPUT))
|
||||
(port CFGSTDBY
|
||||
(direction OUTPUT)))))
|
||||
(cell REFB
|
||||
(cellType GENERIC)
|
||||
(view view1
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||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port wb_clk_i
|
||||
(direction INPUT))
|
||||
(port wb_rst_i
|
||||
(direction INPUT))
|
||||
(port wb_cyc_i
|
||||
(direction INPUT))
|
||||
(port wb_stb_i
|
||||
(direction INPUT))
|
||||
(port wb_we_i
|
||||
(direction INPUT))
|
||||
(port (array (rename wb_adr_i "wb_adr_i(7:0)") 8)
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||||
(direction INPUT))
|
||||
(port (array (rename wb_dat_i "wb_dat_i(7:0)") 8)
|
||||
(direction INPUT))
|
||||
(port (array (rename wb_dat_o "wb_dat_o(7:0)") 8)
|
||||
(direction OUTPUT))
|
||||
(port wb_ack_o
|
||||
(direction OUTPUT))
|
||||
(port wbc_ufm_irq
|
||||
(direction OUTPUT)))
|
||||
(property NGD_DRC_MASK (integer 1))
|
||||
(contents
|
||||
(instance scuba_vhi_inst
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||||
(viewRef view1
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||||
(cellRef VHI)))
|
||||
(instance scuba_vlo_inst
|
||||
(viewRef view1
|
||||
(cellRef VLO)))
|
||||
(instance EFBInst_0
|
||||
(viewRef view1
|
||||
(cellRef EFB))
|
||||
(property UFM_INIT_FILE_FORMAT
|
||||
(string "HEX"))
|
||||
(property UFM_INIT_FILE_NAME
|
||||
(string "../RAM2GS-LCMXO2.mem"))
|
||||
(property UFM_INIT_ALL_ZEROS
|
||||
(string "DISABLED"))
|
||||
(property UFM_INIT_START_PAGE
|
||||
(string "190"))
|
||||
(property UFM_INIT_PAGES
|
||||
(string "321"))
|
||||
(property DEV_DENSITY
|
||||
(string "1200L"))
|
||||
(property EFB_UFM
|
||||
(string "ENABLED"))
|
||||
(property TC_ICAPTURE
|
||||
(string "DISABLED"))
|
||||
(property TC_OVERFLOW
|
||||
(string "DISABLED"))
|
||||
(property TC_ICR_INT
|
||||
(string "OFF"))
|
||||
(property TC_OCR_INT
|
||||
(string "OFF"))
|
||||
(property TC_OV_INT
|
||||
(string "OFF"))
|
||||
(property TC_TOP_SEL
|
||||
(string "OFF"))
|
||||
(property TC_RESETN
|
||||
(string "ENABLED"))
|
||||
(property TC_OC_MODE
|
||||
(string "TOGGLE"))
|
||||
(property TC_OCR_SET
|
||||
(string "32767"))
|
||||
(property TC_TOP_SET
|
||||
(string "65535"))
|
||||
(property GSR
|
||||
(string "ENABLED"))
|
||||
(property TC_CCLK_SEL
|
||||
(string "1"))
|
||||
(property TC_MODE
|
||||
(string "CTCM"))
|
||||
(property TC_SCLK_SEL
|
||||
(string "PCLOCK"))
|
||||
(property EFB_TC_PORTMODE
|
||||
(string "WB"))
|
||||
(property EFB_TC
|
||||
(string "DISABLED"))
|
||||
(property SPI_WAKEUP
|
||||
(string "DISABLED"))
|
||||
(property SPI_INTR_RXOVR
|
||||
(string "DISABLED"))
|
||||
(property SPI_INTR_TXOVR
|
||||
(string "DISABLED"))
|
||||
(property SPI_INTR_RXRDY
|
||||
(string "DISABLED"))
|
||||
(property SPI_INTR_TXRDY
|
||||
(string "DISABLED"))
|
||||
(property SPI_SLAVE_HANDSHAKE
|
||||
(string "DISABLED"))
|
||||
(property SPI_PHASE_ADJ
|
||||
(string "DISABLED"))
|
||||
(property SPI_CLK_INV
|
||||
(string "DISABLED"))
|
||||
(property SPI_LSB_FIRST
|
||||
(string "DISABLED"))
|
||||
(property SPI_CLK_DIVIDER
|
||||
(string "1"))
|
||||
(property SPI_MODE
|
||||
(string "MASTER"))
|
||||
(property EFB_SPI
|
||||
(string "DISABLED"))
|
||||
(property I2C2_WAKEUP
|
||||
(string "DISABLED"))
|
||||
(property I2C2_GEN_CALL
|
||||
(string "DISABLED"))
|
||||
(property I2C2_CLK_DIVIDER
|
||||
(string "1"))
|
||||
(property I2C2_BUS_PERF
|
||||
(string "100kHz"))
|
||||
(property I2C2_SLAVE_ADDR
|
||||
(string "0b1000010"))
|
||||
(property I2C2_ADDRESSING
|
||||
(string "7BIT"))
|
||||
(property EFB_I2C2
|
||||
(string "DISABLED"))
|
||||
(property I2C1_WAKEUP
|
||||
(string "DISABLED"))
|
||||
(property I2C1_GEN_CALL
|
||||
(string "DISABLED"))
|
||||
(property I2C1_CLK_DIVIDER
|
||||
(string "1"))
|
||||
(property I2C1_BUS_PERF
|
||||
(string "100kHz"))
|
||||
(property I2C1_SLAVE_ADDR
|
||||
(string "0b1000001"))
|
||||
(property I2C1_ADDRESSING
|
||||
(string "7BIT"))
|
||||
(property EFB_I2C1
|
||||
(string "DISABLED"))
|
||||
(property EFB_WB_CLK_FREQ
|
||||
(string "66.7")))
|
||||
(net scuba_vhi
|
||||
(joined
|
||||
(portRef Z (instanceRef scuba_vhi_inst))
|
||||
(portRef UFMSN (instanceRef EFBInst_0))))
|
||||
(net scuba_vlo
|
||||
(joined
|
||||
(portRef Z (instanceRef scuba_vlo_inst))
|
||||
(portRef PLL1DATI7 (instanceRef EFBInst_0))
|
||||
(portRef PLL1DATI6 (instanceRef EFBInst_0))
|
||||
(portRef PLL1DATI5 (instanceRef EFBInst_0))
|
||||
(portRef PLL1DATI4 (instanceRef EFBInst_0))
|
||||
(portRef PLL1DATI3 (instanceRef EFBInst_0))
|
||||
(portRef PLL1DATI2 (instanceRef EFBInst_0))
|
||||
(portRef PLL1DATI1 (instanceRef EFBInst_0))
|
||||
(portRef PLL1DATI0 (instanceRef EFBInst_0))
|
||||
(portRef PLL1ACKI (instanceRef EFBInst_0))
|
||||
(portRef PLL0DATI7 (instanceRef EFBInst_0))
|
||||
(portRef PLL0DATI6 (instanceRef EFBInst_0))
|
||||
(portRef PLL0DATI5 (instanceRef EFBInst_0))
|
||||
(portRef PLL0DATI4 (instanceRef EFBInst_0))
|
||||
(portRef PLL0DATI3 (instanceRef EFBInst_0))
|
||||
(portRef PLL0DATI2 (instanceRef EFBInst_0))
|
||||
(portRef PLL0DATI1 (instanceRef EFBInst_0))
|
||||
(portRef PLL0DATI0 (instanceRef EFBInst_0))
|
||||
(portRef PLL0ACKI (instanceRef EFBInst_0))
|
||||
(portRef TCIC (instanceRef EFBInst_0))
|
||||
(portRef TCRSTN (instanceRef EFBInst_0))
|
||||
(portRef TCCLKI (instanceRef EFBInst_0))
|
||||
(portRef SPISCSN (instanceRef EFBInst_0))
|
||||
(portRef SPIMOSII (instanceRef EFBInst_0))
|
||||
(portRef SPIMISOI (instanceRef EFBInst_0))
|
||||
(portRef SPISCKI (instanceRef EFBInst_0))
|
||||
(portRef I2C2SDAI (instanceRef EFBInst_0))
|
||||
(portRef I2C2SCLI (instanceRef EFBInst_0))
|
||||
(portRef I2C1SDAI (instanceRef EFBInst_0))
|
||||
(portRef I2C1SCLI (instanceRef EFBInst_0))))
|
||||
(net wbc_ufm_irq
|
||||
(joined
|
||||
(portRef wbc_ufm_irq)
|
||||
(portRef WBCUFMIRQ (instanceRef EFBInst_0))))
|
||||
(net wb_ack_o
|
||||
(joined
|
||||
(portRef wb_ack_o)
|
||||
(portRef WBACKO (instanceRef EFBInst_0))))
|
||||
(net wb_dat_o7
|
||||
(joined
|
||||
(portRef (member wb_dat_o 0))
|
||||
(portRef WBDATO7 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_o6
|
||||
(joined
|
||||
(portRef (member wb_dat_o 1))
|
||||
(portRef WBDATO6 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_o5
|
||||
(joined
|
||||
(portRef (member wb_dat_o 2))
|
||||
(portRef WBDATO5 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_o4
|
||||
(joined
|
||||
(portRef (member wb_dat_o 3))
|
||||
(portRef WBDATO4 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_o3
|
||||
(joined
|
||||
(portRef (member wb_dat_o 4))
|
||||
(portRef WBDATO3 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_o2
|
||||
(joined
|
||||
(portRef (member wb_dat_o 5))
|
||||
(portRef WBDATO2 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_o1
|
||||
(joined
|
||||
(portRef (member wb_dat_o 6))
|
||||
(portRef WBDATO1 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_o0
|
||||
(joined
|
||||
(portRef (member wb_dat_o 7))
|
||||
(portRef WBDATO0 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_i7
|
||||
(joined
|
||||
(portRef (member wb_dat_i 0))
|
||||
(portRef WBDATI7 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_i6
|
||||
(joined
|
||||
(portRef (member wb_dat_i 1))
|
||||
(portRef WBDATI6 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_i5
|
||||
(joined
|
||||
(portRef (member wb_dat_i 2))
|
||||
(portRef WBDATI5 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_i4
|
||||
(joined
|
||||
(portRef (member wb_dat_i 3))
|
||||
(portRef WBDATI4 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_i3
|
||||
(joined
|
||||
(portRef (member wb_dat_i 4))
|
||||
(portRef WBDATI3 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_i2
|
||||
(joined
|
||||
(portRef (member wb_dat_i 5))
|
||||
(portRef WBDATI2 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_i1
|
||||
(joined
|
||||
(portRef (member wb_dat_i 6))
|
||||
(portRef WBDATI1 (instanceRef EFBInst_0))))
|
||||
(net wb_dat_i0
|
||||
(joined
|
||||
(portRef (member wb_dat_i 7))
|
||||
(portRef WBDATI0 (instanceRef EFBInst_0))))
|
||||
(net wb_adr_i7
|
||||
(joined
|
||||
(portRef (member wb_adr_i 0))
|
||||
(portRef WBADRI7 (instanceRef EFBInst_0))))
|
||||
(net wb_adr_i6
|
||||
(joined
|
||||
(portRef (member wb_adr_i 1))
|
||||
(portRef WBADRI6 (instanceRef EFBInst_0))))
|
||||
(net wb_adr_i5
|
||||
(joined
|
||||
(portRef (member wb_adr_i 2))
|
||||
(portRef WBADRI5 (instanceRef EFBInst_0))))
|
||||
(net wb_adr_i4
|
||||
(joined
|
||||
(portRef (member wb_adr_i 3))
|
||||
(portRef WBADRI4 (instanceRef EFBInst_0))))
|
||||
(net wb_adr_i3
|
||||
(joined
|
||||
(portRef (member wb_adr_i 4))
|
||||
(portRef WBADRI3 (instanceRef EFBInst_0))))
|
||||
(net wb_adr_i2
|
||||
(joined
|
||||
(portRef (member wb_adr_i 5))
|
||||
(portRef WBADRI2 (instanceRef EFBInst_0))))
|
||||
(net wb_adr_i1
|
||||
(joined
|
||||
(portRef (member wb_adr_i 6))
|
||||
(portRef WBADRI1 (instanceRef EFBInst_0))))
|
||||
(net wb_adr_i0
|
||||
(joined
|
||||
(portRef (member wb_adr_i 7))
|
||||
(portRef WBADRI0 (instanceRef EFBInst_0))))
|
||||
(net wb_we_i
|
||||
(joined
|
||||
(portRef wb_we_i)
|
||||
(portRef WBWEI (instanceRef EFBInst_0))))
|
||||
(net wb_stb_i
|
||||
(joined
|
||||
(portRef wb_stb_i)
|
||||
(portRef WBSTBI (instanceRef EFBInst_0))))
|
||||
(net wb_cyc_i
|
||||
(joined
|
||||
(portRef wb_cyc_i)
|
||||
(portRef WBCYCI (instanceRef EFBInst_0))))
|
||||
(net wb_rst_i
|
||||
(joined
|
||||
(portRef wb_rst_i)
|
||||
(portRef WBRSTI (instanceRef EFBInst_0))))
|
||||
(net wb_clk_i
|
||||
(joined
|
||||
(portRef wb_clk_i)
|
||||
(portRef WBCLKI (instanceRef EFBInst_0))))))))
|
||||
(design REFB
|
||||
(cellRef REFB
|
||||
(libraryRef ORCLIB)))
|
||||
)
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<DiamondModule name="REFB" module="EFB" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2023 09 21 04:34:51.977" version="1.2" type="Module" synthesis="synplify" source_format="Verilog">
|
||||
<Package>
|
||||
<File name="REFB.lpc" type="lpc" modified="2023 09 21 04:34:49.038"/>
|
||||
<File name="REFB.v" type="top_level_verilog" modified="2023 09 21 04:34:49.107"/>
|
||||
<File name="REFB_tmpl.v" type="template_verilog" modified="2023 09 21 04:34:49.108"/>
|
||||
</Package>
|
||||
</DiamondModule>
|
||||
|
|
@ -0,0 +1,141 @@
|
|||
[Device]
|
||||
Family=machxo2
|
||||
PartType=LCMXO2-1200HC
|
||||
PartName=LCMXO2-1200HC-4TG100C
|
||||
SpeedGrade=4
|
||||
Package=TQFP100
|
||||
OperatingCondition=COM
|
||||
Status=S
|
||||
|
||||
[IP]
|
||||
VendorName=Lattice Semiconductor Corporation
|
||||
CoreType=LPM
|
||||
CoreStatus=Demo
|
||||
CoreName=EFB
|
||||
CoreRevision=1.2
|
||||
ModuleName=REFB
|
||||
SourceFormat=Verilog HDL
|
||||
ParameterFileVersion=1.0
|
||||
Date=09/21/2023
|
||||
Time=04:34:49
|
||||
|
||||
[Parameters]
|
||||
Verilog=1
|
||||
VHDL=0
|
||||
EDIF=1
|
||||
Destination=Synplicity
|
||||
Expression=BusA(0 to 7)
|
||||
Order=Big Endian [MSB:LSB]
|
||||
IO=0
|
||||
freq=
|
||||
i2c1=0
|
||||
i2c1config=0
|
||||
i2c1_addr=7-Bit Addressing
|
||||
i2c1_ce=0
|
||||
i2c1_freq=100
|
||||
i2c1_sa=10000
|
||||
i2c1_we=0
|
||||
i2c2=0
|
||||
i2c2_addr=7-Bit Addressing
|
||||
i2c2_ce=0
|
||||
i2c2_freq=100
|
||||
i2c2_sa=10000
|
||||
i2c2_we=0
|
||||
ufm_addr=7-Bit Addressing
|
||||
ufm_sa=10000
|
||||
pll=0
|
||||
pll_cnt=1
|
||||
spi=0
|
||||
spi_clkinv=0
|
||||
spi_cs=1
|
||||
spi_en=0
|
||||
spi_freq=1
|
||||
spi_lsb=0
|
||||
spi_mode=Slave
|
||||
spi_ib=0
|
||||
spi_ph=0
|
||||
spi_hs=0
|
||||
spi_rxo=0
|
||||
spi_rxr=0
|
||||
spi_txo=0
|
||||
spi_txr=0
|
||||
spi_we=0
|
||||
static_tc=Static
|
||||
tc=0
|
||||
tc_clkinv=Positive
|
||||
tc_ctr=1
|
||||
tc_div=1
|
||||
tc_ipcap=0
|
||||
tc_mode=CTCM
|
||||
tc_ocr=32767
|
||||
tc_oflow=1
|
||||
tc_o=TOGGLE
|
||||
tc_opcomp=0
|
||||
tc_osc=0
|
||||
tc_sa_oflow=0
|
||||
tc_top=65535
|
||||
ufm=1
|
||||
ufm0=0
|
||||
ufm1=0
|
||||
ufm2=0
|
||||
ufm3=0
|
||||
ufm_cfg0=0
|
||||
ufm_cfg1=0
|
||||
wb_clk_freq=66.7
|
||||
ufm_usage=SHARED_EBR_TAG
|
||||
ufm_ebr=190
|
||||
ufm_remain=
|
||||
mem_size=321
|
||||
ufm_start=
|
||||
ufm_init=mem
|
||||
memfile=../RAM2GS-LCMXO2.mem
|
||||
ufm_dt=hex
|
||||
ufm0_ebr=
|
||||
mem_size0=1
|
||||
ufm0_init=0
|
||||
memfile0=
|
||||
ufm0_dt=hex
|
||||
ufm1_ebr=
|
||||
mem_size1=1
|
||||
ufm1_init=0
|
||||
memfile1=
|
||||
ufm1_dt=hex
|
||||
ufm2_ebr=
|
||||
mem_size2=1
|
||||
ufm2_init=0
|
||||
memfile2=
|
||||
ufm2_dt=hex
|
||||
ufm3_ebr=
|
||||
mem_size3=1
|
||||
ufm3_init=0
|
||||
memfile3=
|
||||
ufm3_dt=hex
|
||||
ufm_cfg0_ebr=
|
||||
mem_size_cfg0=1
|
||||
ufm_cfg0_init=0
|
||||
memfile_cfg0=
|
||||
ufm_cfg0_dt=hex
|
||||
ufm_cfg1_ebr=
|
||||
mem_size_cfg1=1
|
||||
ufm_cfg1_init=0
|
||||
memfile_cfg1=
|
||||
ufm_cfg1_dt=hex
|
||||
wb=1
|
||||
boot_option=Internal
|
||||
efb_ufm=0
|
||||
boot_option_internal=Single Boot
|
||||
internal_ufm0=0
|
||||
internal_ufm1=0
|
||||
efb_ufm_boot=
|
||||
tamperdr=0
|
||||
t_pwd=0
|
||||
t_lockflash=0
|
||||
t_manmode=0
|
||||
t_jtagport=0
|
||||
t_sspiport=0
|
||||
t_sic2port=0
|
||||
t_wbport=0
|
||||
t_portlock=0
|
||||
|
||||
[Command]
|
||||
cmd_line= -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 66.7 -ufm -ufm_ebr 190 -mem_size 321 -memfile ../RAM2GS-LCMXO2.mem -memformat hex -wb -dev 1200
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
wb_clk_i i
|
||||
wb_rst_i i
|
||||
wb_cyc_i i
|
||||
wb_stb_i i
|
||||
wb_we_i i
|
||||
wb_adr_i[7] i
|
||||
wb_adr_i[6] i
|
||||
wb_adr_i[5] i
|
||||
wb_adr_i[4] i
|
||||
wb_adr_i[3] i
|
||||
wb_adr_i[2] i
|
||||
wb_adr_i[1] i
|
||||
wb_adr_i[0] i
|
||||
wb_dat_i[7] i
|
||||
wb_dat_i[6] i
|
||||
wb_dat_i[5] i
|
||||
wb_dat_i[4] i
|
||||
wb_dat_i[3] i
|
||||
wb_dat_i[2] i
|
||||
wb_dat_i[1] i
|
||||
wb_dat_i[0] i
|
||||
wb_dat_o[7] o
|
||||
wb_dat_o[6] o
|
||||
wb_dat_o[5] o
|
||||
wb_dat_o[4] o
|
||||
wb_dat_o[3] o
|
||||
wb_dat_o[2] o
|
||||
wb_dat_o[1] o
|
||||
wb_dat_o[0] o
|
||||
wb_ack_o o
|
||||
wbc_ufm_irq o
|
||||
|
|
@ -0,0 +1 @@
|
|||
REFB.v
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
SCUBA, Version Diamond (64-bit) 3.12.1.454
|
||||
Thu Sep 21 04:34:49 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 66.7 -ufm -ufm_ebr 190 -mem_size 321 -memfile ../RAM2GS-LCMXO2.mem -memformat hex -wb -dev 1200
|
||||
Circuit name : REFB
|
||||
Module type : efb
|
||||
Module Version : 1.2
|
||||
Ports :
|
||||
Inputs : wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i[7:0], wb_dat_i[7:0]
|
||||
Outputs : wb_dat_o[7:0], wb_ack_o, wbc_ufm_irq
|
||||
I/O buffer : not inserted
|
||||
EDIF output : REFB.edn
|
||||
Verilog output : REFB.v
|
||||
Verilog template : REFB_tmpl.v
|
||||
Verilog purpose : for synthesis and simulation
|
||||
Bus notation : big endian
|
||||
Report output : REFB.srp
|
||||
Element Usage :
|
||||
EFB : 1
|
||||
Estimated Resource Usage:
|
||||
Binary file not shown.
|
|
@ -0,0 +1,113 @@
|
|||
/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 */
|
||||
/* Module Version: 1.2 */
|
||||
/* C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 66.7 -ufm -ufm_ebr 190 -mem_size 321 -memfile ../RAM2GS-LCMXO2.mem -memformat hex -wb -dev 1200 */
|
||||
/* Thu Sep 21 04:34:49 2023 */
|
||||
|
||||
|
||||
`timescale 1 ns / 1 ps
|
||||
module REFB (wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i,
|
||||
wb_dat_i, wb_dat_o, wb_ack_o, wbc_ufm_irq)/* synthesis NGD_DRC_MASK=1 */;
|
||||
input wire wb_clk_i;
|
||||
input wire wb_rst_i;
|
||||
input wire wb_cyc_i;
|
||||
input wire wb_stb_i;
|
||||
input wire wb_we_i;
|
||||
input wire [7:0] wb_adr_i;
|
||||
input wire [7:0] wb_dat_i;
|
||||
output wire [7:0] wb_dat_o;
|
||||
output wire wb_ack_o;
|
||||
output wire wbc_ufm_irq;
|
||||
|
||||
wire scuba_vhi;
|
||||
wire scuba_vlo;
|
||||
|
||||
VHI scuba_vhi_inst (.Z(scuba_vhi));
|
||||
|
||||
VLO scuba_vlo_inst (.Z(scuba_vlo));
|
||||
|
||||
defparam EFBInst_0.UFM_INIT_FILE_FORMAT = "HEX" ;
|
||||
defparam EFBInst_0.UFM_INIT_FILE_NAME = "../RAM2GS-LCMXO2.mem" ;
|
||||
defparam EFBInst_0.UFM_INIT_ALL_ZEROS = "DISABLED" ;
|
||||
defparam EFBInst_0.UFM_INIT_START_PAGE = 190 ;
|
||||
defparam EFBInst_0.UFM_INIT_PAGES = 321 ;
|
||||
defparam EFBInst_0.DEV_DENSITY = "1200L" ;
|
||||
defparam EFBInst_0.EFB_UFM = "ENABLED" ;
|
||||
defparam EFBInst_0.TC_ICAPTURE = "DISABLED" ;
|
||||
defparam EFBInst_0.TC_OVERFLOW = "DISABLED" ;
|
||||
defparam EFBInst_0.TC_ICR_INT = "OFF" ;
|
||||
defparam EFBInst_0.TC_OCR_INT = "OFF" ;
|
||||
defparam EFBInst_0.TC_OV_INT = "OFF" ;
|
||||
defparam EFBInst_0.TC_TOP_SEL = "OFF" ;
|
||||
defparam EFBInst_0.TC_RESETN = "ENABLED" ;
|
||||
defparam EFBInst_0.TC_OC_MODE = "TOGGLE" ;
|
||||
defparam EFBInst_0.TC_OCR_SET = 32767 ;
|
||||
defparam EFBInst_0.TC_TOP_SET = 65535 ;
|
||||
defparam EFBInst_0.GSR = "ENABLED" ;
|
||||
defparam EFBInst_0.TC_CCLK_SEL = 1 ;
|
||||
defparam EFBInst_0.TC_MODE = "CTCM" ;
|
||||
defparam EFBInst_0.TC_SCLK_SEL = "PCLOCK" ;
|
||||
defparam EFBInst_0.EFB_TC_PORTMODE = "WB" ;
|
||||
defparam EFBInst_0.EFB_TC = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_WAKEUP = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_INTR_RXOVR = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_INTR_TXOVR = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_INTR_RXRDY = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_INTR_TXRDY = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_SLAVE_HANDSHAKE = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_PHASE_ADJ = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_CLK_INV = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_LSB_FIRST = "DISABLED" ;
|
||||
defparam EFBInst_0.SPI_CLK_DIVIDER = 1 ;
|
||||
defparam EFBInst_0.SPI_MODE = "MASTER" ;
|
||||
defparam EFBInst_0.EFB_SPI = "DISABLED" ;
|
||||
defparam EFBInst_0.I2C2_WAKEUP = "DISABLED" ;
|
||||
defparam EFBInst_0.I2C2_GEN_CALL = "DISABLED" ;
|
||||
defparam EFBInst_0.I2C2_CLK_DIVIDER = 1 ;
|
||||
defparam EFBInst_0.I2C2_BUS_PERF = "100kHz" ;
|
||||
defparam EFBInst_0.I2C2_SLAVE_ADDR = "0b1000010" ;
|
||||
defparam EFBInst_0.I2C2_ADDRESSING = "7BIT" ;
|
||||
defparam EFBInst_0.EFB_I2C2 = "DISABLED" ;
|
||||
defparam EFBInst_0.I2C1_WAKEUP = "DISABLED" ;
|
||||
defparam EFBInst_0.I2C1_GEN_CALL = "DISABLED" ;
|
||||
defparam EFBInst_0.I2C1_CLK_DIVIDER = 1 ;
|
||||
defparam EFBInst_0.I2C1_BUS_PERF = "100kHz" ;
|
||||
defparam EFBInst_0.I2C1_SLAVE_ADDR = "0b1000001" ;
|
||||
defparam EFBInst_0.I2C1_ADDRESSING = "7BIT" ;
|
||||
defparam EFBInst_0.EFB_I2C1 = "DISABLED" ;
|
||||
defparam EFBInst_0.EFB_WB_CLK_FREQ = "66.7" ;
|
||||
EFB EFBInst_0 (.WBCLKI(wb_clk_i), .WBRSTI(wb_rst_i), .WBCYCI(wb_cyc_i),
|
||||
.WBSTBI(wb_stb_i), .WBWEI(wb_we_i), .WBADRI7(wb_adr_i[7]), .WBADRI6(wb_adr_i[6]),
|
||||
.WBADRI5(wb_adr_i[5]), .WBADRI4(wb_adr_i[4]), .WBADRI3(wb_adr_i[3]),
|
||||
.WBADRI2(wb_adr_i[2]), .WBADRI1(wb_adr_i[1]), .WBADRI0(wb_adr_i[0]),
|
||||
.WBDATI7(wb_dat_i[7]), .WBDATI6(wb_dat_i[6]), .WBDATI5(wb_dat_i[5]),
|
||||
.WBDATI4(wb_dat_i[4]), .WBDATI3(wb_dat_i[3]), .WBDATI2(wb_dat_i[2]),
|
||||
.WBDATI1(wb_dat_i[1]), .WBDATI0(wb_dat_i[0]), .PLL0DATI7(scuba_vlo),
|
||||
.PLL0DATI6(scuba_vlo), .PLL0DATI5(scuba_vlo), .PLL0DATI4(scuba_vlo),
|
||||
.PLL0DATI3(scuba_vlo), .PLL0DATI2(scuba_vlo), .PLL0DATI1(scuba_vlo),
|
||||
.PLL0DATI0(scuba_vlo), .PLL0ACKI(scuba_vlo), .PLL1DATI7(scuba_vlo),
|
||||
.PLL1DATI6(scuba_vlo), .PLL1DATI5(scuba_vlo), .PLL1DATI4(scuba_vlo),
|
||||
.PLL1DATI3(scuba_vlo), .PLL1DATI2(scuba_vlo), .PLL1DATI1(scuba_vlo),
|
||||
.PLL1DATI0(scuba_vlo), .PLL1ACKI(scuba_vlo), .I2C1SCLI(scuba_vlo),
|
||||
.I2C1SDAI(scuba_vlo), .I2C2SCLI(scuba_vlo), .I2C2SDAI(scuba_vlo),
|
||||
.SPISCKI(scuba_vlo), .SPIMISOI(scuba_vlo), .SPIMOSII(scuba_vlo),
|
||||
.SPISCSN(scuba_vlo), .TCCLKI(scuba_vlo), .TCRSTN(scuba_vlo), .TCIC(scuba_vlo),
|
||||
.UFMSN(scuba_vhi), .WBDATO7(wb_dat_o[7]), .WBDATO6(wb_dat_o[6]),
|
||||
.WBDATO5(wb_dat_o[5]), .WBDATO4(wb_dat_o[4]), .WBDATO3(wb_dat_o[3]),
|
||||
.WBDATO2(wb_dat_o[2]), .WBDATO1(wb_dat_o[1]), .WBDATO0(wb_dat_o[0]),
|
||||
.WBACKO(wb_ack_o), .PLLCLKO(), .PLLRSTO(), .PLL0STBO(), .PLL1STBO(),
|
||||
.PLLWEO(), .PLLADRO4(), .PLLADRO3(), .PLLADRO2(), .PLLADRO1(), .PLLADRO0(),
|
||||
.PLLDATO7(), .PLLDATO6(), .PLLDATO5(), .PLLDATO4(), .PLLDATO3(),
|
||||
.PLLDATO2(), .PLLDATO1(), .PLLDATO0(), .I2C1SCLO(), .I2C1SCLOEN(),
|
||||
.I2C1SDAO(), .I2C1SDAOEN(), .I2C2SCLO(), .I2C2SCLOEN(), .I2C2SDAO(),
|
||||
.I2C2SDAOEN(), .I2C1IRQO(), .I2C2IRQO(), .SPISCKO(), .SPISCKEN(),
|
||||
.SPIMISOO(), .SPIMISOEN(), .SPIMOSIO(), .SPIMOSIEN(), .SPIMCSN7(),
|
||||
.SPIMCSN6(), .SPIMCSN5(), .SPIMCSN4(), .SPIMCSN3(), .SPIMCSN2(),
|
||||
.SPIMCSN1(), .SPIMCSN0(), .SPICSNEN(), .SPIIRQO(), .TCINT(), .TCOC(),
|
||||
.WBCUFMIRQ(wbc_ufm_irq), .CFGWAKE(), .CFGSTDBY());
|
||||
|
||||
|
||||
|
||||
// exemplar begin
|
||||
// exemplar end
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
Starting process: Module
|
||||
|
||||
Starting process:
|
||||
|
||||
SCUBA, Version Diamond (64-bit) 3.12.1.454
|
||||
Thu Sep 21 04:34:49 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
BEGIN SCUBA Module Synthesis
|
||||
|
||||
Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 66.7 -ufm -ufm_ebr 190 -mem_size 321 -memfile ../RAM2GS-LCMXO2.mem -memformat hex -wb -dev 1200
|
||||
Circuit name : REFB
|
||||
Module type : efb
|
||||
Module Version : 1.2
|
||||
Ports :
|
||||
Inputs : wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i[7:0], wb_dat_i[7:0]
|
||||
Outputs : wb_dat_o[7:0], wb_ack_o, wbc_ufm_irq
|
||||
I/O buffer : not inserted
|
||||
EDIF output : REFB.edn
|
||||
Verilog output : REFB.v
|
||||
Verilog template : REFB_tmpl.v
|
||||
Verilog purpose : for synthesis and simulation
|
||||
Bus notation : big endian
|
||||
Report output : REFB.srp
|
||||
Estimated Resource Usage:
|
||||
|
||||
END SCUBA Module Synthesis
|
||||
|
||||
File: REFB.lpc created.
|
||||
|
||||
|
||||
End process: completed successfully.
|
||||
|
||||
|
||||
Total Warnings: 0
|
||||
|
||||
Total Errors: 0
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.12.1.454 */
|
||||
/* Module Version: 1.2 */
|
||||
/* Thu Sep 21 04:34:49 2023 */
|
||||
|
||||
/* parameterized module instance */
|
||||
REFB __ (.wb_clk_i( ), .wb_rst_i( ), .wb_cyc_i( ), .wb_stb_i( ),
|
||||
.wb_we_i( ), .wb_adr_i( ), .wb_dat_i( ), .wb_dat_o( ), .wb_ack_o( ),
|
||||
.wbc_ufm_irq( ));
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,100 @@
|
|||
#!/usr/local/bin/wish
|
||||
|
||||
proc GetPlatform {} {
|
||||
global tcl_platform
|
||||
|
||||
set cpu $tcl_platform(machine)
|
||||
|
||||
switch $cpu {
|
||||
intel -
|
||||
i*86* {
|
||||
set cpu ix86
|
||||
}
|
||||
x86_64 {
|
||||
if {$tcl_platform(wordSize) == 4} {
|
||||
set cpu ix86
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
switch $tcl_platform(platform) {
|
||||
windows {
|
||||
if {$cpu == "amd64"} {
|
||||
# Do not check wordSize, win32-x64 is an IL32P64 platform.
|
||||
set cpu x86_64
|
||||
}
|
||||
if {$cpu == "x86_64"} {
|
||||
return "nt64"
|
||||
} else {
|
||||
return "nt"
|
||||
}
|
||||
}
|
||||
unix {
|
||||
if {$tcl_platform(os) == "Linux"} {
|
||||
if {$cpu == "x86_64"} {
|
||||
return "lin64"
|
||||
} else {
|
||||
return "lin"
|
||||
}
|
||||
} else {
|
||||
return "sol"
|
||||
}
|
||||
}
|
||||
}
|
||||
return "nt"
|
||||
}
|
||||
|
||||
proc GetCmdLine {lpcfile} {
|
||||
global Para
|
||||
|
||||
if [catch {open $lpcfile r} fileid] {
|
||||
puts "Cannot open $para_file file!"
|
||||
exit -1
|
||||
}
|
||||
|
||||
seek $fileid 0 start
|
||||
set default_match 0
|
||||
while {[gets $fileid line] >= 0} {
|
||||
if {[string first "\[Command\]" $line] == 0} {
|
||||
set default_match 1
|
||||
continue
|
||||
}
|
||||
if {[string first "\[" $line] == 0} {
|
||||
set default_match 0
|
||||
}
|
||||
if {$default_match == 1} {
|
||||
if [regexp {([^=]*)=(.*)} $line match parameter value] {
|
||||
if [regexp {([ |\t]*;)} $parameter match] {continue}
|
||||
if [regexp {(.*)[ |\t]*;} $value match temp] {
|
||||
set Para($parameter) $temp
|
||||
} else {
|
||||
set Para($parameter) $value
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
set default_match 0
|
||||
close $fileid
|
||||
|
||||
return $Para(cmd_line)
|
||||
}
|
||||
|
||||
set platformpath [GetPlatform]
|
||||
set Para(sbp_path) [file dirname [info script]]
|
||||
set Para(install_dir) $env(TOOLRTF)
|
||||
set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
|
||||
|
||||
set scuba "$Para(FPGAPath)/scuba"
|
||||
set modulename "REFB"
|
||||
set lang "verilog"
|
||||
set lpcfile "$Para(sbp_path)/$modulename.lpc"
|
||||
set arch "xo2c00"
|
||||
set cmd_line [GetCmdLine $lpcfile]
|
||||
set fdcfile "$Para(sbp_path)/$modulename.fdc"
|
||||
if {[file exists $fdcfile] == 0} {
|
||||
append scuba " " $cmd_line
|
||||
} else {
|
||||
append scuba " " $cmd_line " " -fdc " " \"$fdcfile\"
|
||||
}
|
||||
set Para(result) [catch {eval exec "$scuba"} msg]
|
||||
#puts $msg
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
#!/usr/local/bin/wish
|
||||
|
||||
proc GetPlatform {} {
|
||||
global tcl_platform
|
||||
|
||||
set cpu $tcl_platform(machine)
|
||||
|
||||
switch $cpu {
|
||||
intel -
|
||||
i*86* {
|
||||
set cpu ix86
|
||||
}
|
||||
x86_64 {
|
||||
if {$tcl_platform(wordSize) == 4} {
|
||||
set cpu ix86
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
switch $tcl_platform(platform) {
|
||||
windows {
|
||||
if {$cpu == "amd64"} {
|
||||
# Do not check wordSize, win32-x64 is an IL32P64 platform.
|
||||
set cpu x86_64
|
||||
}
|
||||
if {$cpu == "x86_64"} {
|
||||
return "nt64"
|
||||
} else {
|
||||
return "nt"
|
||||
}
|
||||
}
|
||||
unix {
|
||||
if {$tcl_platform(os) == "Linux"} {
|
||||
if {$cpu == "x86_64"} {
|
||||
return "lin64"
|
||||
} else {
|
||||
return "lin"
|
||||
}
|
||||
} else {
|
||||
return "sol"
|
||||
}
|
||||
}
|
||||
}
|
||||
return "nt"
|
||||
}
|
||||
|
||||
set platformpath [GetPlatform]
|
||||
set Para(sbp_path) [file dirname [info script]]
|
||||
set Para(install_dir) $env(TOOLRTF)
|
||||
set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]"
|
||||
set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]"
|
||||
|
||||
set Para(ModuleName) "REFB"
|
||||
set Para(Module) "EFB"
|
||||
set Para(libname) machxo2
|
||||
set Para(arch_name) xo2c00
|
||||
set Para(PartType) "LCMXO2-1200HC"
|
||||
|
||||
set Para(tech_syn) machxo2
|
||||
set Para(tech_cae) machxo2
|
||||
set Para(Package) "TQFP100"
|
||||
set Para(SpeedGrade) "4"
|
||||
set Para(FMax) "100"
|
||||
set fdcfile "$Para(sbp_path)/$Para(ModuleName).fdc"
|
||||
|
||||
#edif2ngd
|
||||
set edif2ngd "$Para(FPGAPath)/edif2ngd"
|
||||
set Para(result) [catch {eval exec $edif2ngd -l $Para(libname) -d $Para(PartType) -nopropwarn $Para(ModuleName).edn $Para(ModuleName).ngo} msg]
|
||||
#puts $msg
|
||||
|
||||
#ngdbuild
|
||||
set ngdbuild "$Para(FPGAPath)/ngdbuild"
|
||||
set Para(result) [catch {eval exec $ngdbuild -addiobuf -dt -a $Para(arch_name) $Para(ModuleName).ngo $Para(ModuleName).ngd} msg]
|
||||
#puts $msg
|
||||
|
|
@ -0,0 +1,71 @@
|
|||
NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
|
||||
NOTE All Rights Reserved *
|
||||
NOTE DATE CREATED: Thu Sep 21 05:40:22 2023 *
|
||||
NOTE DESIGN NAME: RAM2GS *
|
||||
NOTE DEVICE NAME: LCMXO2-1200HC-4TQFP100 *
|
||||
NOTE PIN ASSIGNMENTS *
|
||||
NOTE PINS RD[0] : 36 : inout *
|
||||
NOTE PINS Dout[0] : 76 : out *
|
||||
NOTE PINS PHI2 : 8 : in *
|
||||
NOTE PINS RDQML : 48 : out *
|
||||
NOTE PINS RDQMH : 51 : out *
|
||||
NOTE PINS nRCAS : 52 : out *
|
||||
NOTE PINS nRRAS : 54 : out *
|
||||
NOTE PINS nRWE : 49 : out *
|
||||
NOTE PINS RCKE : 53 : out *
|
||||
NOTE PINS RCLK : 63 : in *
|
||||
NOTE PINS nRCS : 57 : out *
|
||||
NOTE PINS RD[7] : 43 : inout *
|
||||
NOTE PINS RD[6] : 42 : inout *
|
||||
NOTE PINS RD[5] : 41 : inout *
|
||||
NOTE PINS RD[4] : 40 : inout *
|
||||
NOTE PINS RD[3] : 39 : inout *
|
||||
NOTE PINS RD[2] : 38 : inout *
|
||||
NOTE PINS RD[1] : 37 : inout *
|
||||
NOTE PINS RA[11] : 59 : out *
|
||||
NOTE PINS RA[10] : 64 : out *
|
||||
NOTE PINS RA[9] : 62 : out *
|
||||
NOTE PINS RA[8] : 65 : out *
|
||||
NOTE PINS RA[7] : 75 : out *
|
||||
NOTE PINS RA[6] : 68 : out *
|
||||
NOTE PINS RA[5] : 70 : out *
|
||||
NOTE PINS RA[4] : 74 : out *
|
||||
NOTE PINS RA[3] : 71 : out *
|
||||
NOTE PINS RA[2] : 69 : out *
|
||||
NOTE PINS RA[1] : 67 : out *
|
||||
NOTE PINS RA[0] : 66 : out *
|
||||
NOTE PINS RBA[1] : 60 : out *
|
||||
NOTE PINS RBA[0] : 58 : out *
|
||||
NOTE PINS LED : 34 : out *
|
||||
NOTE PINS nFWE : 15 : in *
|
||||
NOTE PINS nCRAS : 17 : in *
|
||||
NOTE PINS nCCAS : 9 : in *
|
||||
NOTE PINS Dout[7] : 82 : out *
|
||||
NOTE PINS Dout[6] : 78 : out *
|
||||
NOTE PINS Dout[5] : 84 : out *
|
||||
NOTE PINS Dout[4] : 83 : out *
|
||||
NOTE PINS Dout[3] : 85 : out *
|
||||
NOTE PINS Dout[2] : 87 : out *
|
||||
NOTE PINS Dout[1] : 86 : out *
|
||||
NOTE PINS Din[7] : 1 : in *
|
||||
NOTE PINS Din[6] : 2 : in *
|
||||
NOTE PINS Din[5] : 98 : in *
|
||||
NOTE PINS Din[4] : 99 : in *
|
||||
NOTE PINS Din[3] : 97 : in *
|
||||
NOTE PINS Din[2] : 88 : in *
|
||||
NOTE PINS Din[1] : 96 : in *
|
||||
NOTE PINS Din[0] : 3 : in *
|
||||
NOTE PINS CROW[1] : 16 : in *
|
||||
NOTE PINS CROW[0] : 10 : in *
|
||||
NOTE PINS MAin[9] : 32 : in *
|
||||
NOTE PINS MAin[8] : 25 : in *
|
||||
NOTE PINS MAin[7] : 18 : in *
|
||||
NOTE PINS MAin[6] : 24 : in *
|
||||
NOTE PINS MAin[5] : 19 : in *
|
||||
NOTE PINS MAin[4] : 20 : in *
|
||||
NOTE PINS MAin[3] : 21 : in *
|
||||
NOTE PINS MAin[2] : 13 : in *
|
||||
NOTE PINS MAin[1] : 12 : in *
|
||||
NOTE PINS MAin[0] : 14 : in *
|
||||
NOTE CONFIGURATION MODE: NONE *
|
||||
NOTE COMPRESSION: on *
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
----------------------------------------------------------------------
|
||||
Report for cell RAM2GS.verilog
|
||||
|
||||
Register bits: 111 of 640 (17%)
|
||||
Register bits: 109 of 1280 (9%)
|
||||
PIC Latch: 0
|
||||
I/O cells: 63
|
||||
Cell usage:
|
||||
|
|
@ -9,35 +9,35 @@ I/O cells: 63
|
|||
BB 8 100.0
|
||||
CCU2D 10 100.0
|
||||
EFB 1 100.0
|
||||
FD1P3AX 28 100.0
|
||||
FD1P3AX 25 100.0
|
||||
FD1P3IX 2 100.0
|
||||
FD1S3AX 52 100.0
|
||||
FD1S3AX 53 100.0
|
||||
FD1S3IX 4 100.0
|
||||
GSR 1 100.0
|
||||
IB 25 100.0
|
||||
IFS1P3DX 9 100.0
|
||||
INV 6 100.0
|
||||
INV 7 100.0
|
||||
OB 30 100.0
|
||||
OFS1P3BX 4 100.0
|
||||
OFS1P3DX 11 100.0
|
||||
OFS1P3JX 1 100.0
|
||||
ORCALUT4 199 100.0
|
||||
PFUMX 3 100.0
|
||||
ORCALUT4 213 100.0
|
||||
PFUMX 1 100.0
|
||||
PUR 1 100.0
|
||||
VHI 2 100.0
|
||||
VLO 2 100.0
|
||||
SUB MODULES
|
||||
REFB 1 100.0
|
||||
|
||||
TOTAL 400
|
||||
TOTAL 411
|
||||
----------------------------------------------------------------------
|
||||
Report for cell REFB.netlist
|
||||
Instance path: ufmefb
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
EFB 1 100.0
|
||||
ORCALUT4 1 0.5
|
||||
ORCALUT4 2 0.9
|
||||
VHI 1 50.0
|
||||
VLO 1 50.0
|
||||
|
||||
TOTAL 4
|
||||
TOTAL 5
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Thu Sep 21 05:40:18 2023
|
||||
|
||||
|
||||
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC -w -jedec -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
|
||||
|
||||
Loading design for application Bitgen from file RAM2GS_LCMXO2_1200HC_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-1200HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application Bitgen from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.44.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
|
||||
Running DRC.
|
||||
DRC detected 0 errors and 0 warnings.
|
||||
Reading Preference File from RAM2GS_LCMXO2_1200HC_impl1.prf.
|
||||
|
||||
Preference Summary:
|
||||
+---------------------------------+---------------------------------+
|
||||
| Preference | Current Setting |
|
||||
+---------------------------------+---------------------------------+
|
||||
| RamCfg | Reset** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MCCLK_FREQ | 2.08** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| CONFIG_SECURE | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| INBUF | ON** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| JTAG_PORT | ENABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SDM_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SLAVE_SPI_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MASTER_SPI_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| I2C_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MUX_CONFIGURATION_PORTS | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| CONFIGURATION | CFG** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| COMPRESS_CONFIG | ON** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MY_ASSP | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| ONE_TIME_PROGRAM | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| ENABLE_TRANSFR | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SHAREDEBRINIT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| BACKGROUND_RECONFIG | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
* Default setting.
|
||||
** The specified setting matches the default setting.
|
||||
|
||||
|
||||
Creating bit map...
|
||||
|
||||
Bitstream Status: Final Version 1.95.
|
||||
|
||||
Saving bit stream in "RAM2GS_LCMXO2_1200HC_impl1.jed".
|
||||
|
||||
===========
|
||||
UFM Summary.
|
||||
===========
|
||||
UFM Size: 511 Pages (128*511 Bits).
|
||||
UFM Utilization: General Purpose Flash Memory.
|
||||
|
||||
Available General Purpose Flash Memory: 511 Pages (Page 0 to Page 510).
|
||||
Initialized UFM Pages: 321 Pages (Page 190 to Page 510).
|
||||
|
||||
Total CPU Time: 3 secs
|
||||
Total REAL Time: 4 secs
|
||||
Peak Memory Usage: 274 MB
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,468 @@
|
|||
|
||||
Lattice Mapping Report File for Design Module 'RAM2GS'
|
||||
|
||||
|
||||
Design Information
|
||||
------------------
|
||||
|
||||
Command line: map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 4 -oc Commercial
|
||||
RAM2GS_LCMXO2_1200HC_impl1.ngd -o RAM2GS_LCMXO2_1200HC_impl1_map.ncd -pr
|
||||
RAM2GS_LCMXO2_1200HC_impl1.prf -mp RAM2GS_LCMXO2_1200HC_impl1.mrp -lpf //Ma
|
||||
c/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_s
|
||||
ynplify.lpf -lpf //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.lpf -c 0 -gui
|
||||
-msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml
|
||||
Target Vendor: LATTICE
|
||||
Target Device: LCMXO2-1200HCTQFP100
|
||||
Target Performance: 4
|
||||
Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454
|
||||
Mapped on: 09/21/23 05:39:45
|
||||
|
||||
Design Summary
|
||||
--------------
|
||||
|
||||
Number of registers: 109 out of 1520 (7%)
|
||||
PFU registers: 84 out of 1280 (7%)
|
||||
PIO registers: 25 out of 240 (10%)
|
||||
Number of SLICEs: 120 out of 640 (19%)
|
||||
SLICEs as Logic/ROM: 120 out of 640 (19%)
|
||||
SLICEs as RAM: 0 out of 480 (0%)
|
||||
SLICEs as Carry: 10 out of 640 (2%)
|
||||
Number of LUT4s: 237 out of 1280 (19%)
|
||||
Number used as logic LUTs: 217
|
||||
Number used as distributed RAM: 0
|
||||
Number used as ripple logic: 20
|
||||
Number used as shift registers: 0
|
||||
Number of PIO sites used: 63 + 4(JTAG) out of 80 (84%)
|
||||
Number of block RAMs: 0 out of 7 (0%)
|
||||
Number of GSRs: 0 out of 1 (0%)
|
||||
EFB used : Yes
|
||||
JTAG used : No
|
||||
Readback used : No
|
||||
Oscillator used : No
|
||||
Startup used : No
|
||||
POR : On
|
||||
Bandgap : On
|
||||
Number of Power Controller: 0 out of 1 (0%)
|
||||
Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
|
||||
Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%)
|
||||
Number of DCCA: 0 out of 8 (0%)
|
||||
Number of DCMA: 0 out of 2 (0%)
|
||||
Number of PLLs: 0 out of 1 (0%)
|
||||
Number of DQSDLLs: 0 out of 2 (0%)
|
||||
Number of CLKDIVC: 0 out of 4 (0%)
|
||||
Number of ECLKSYNCA: 0 out of 4 (0%)
|
||||
Number of ECLKBRIDGECS: 0 out of 2 (0%)
|
||||
Notes:-
|
||||
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
|
||||
distributed RAMs) + 2*(Number of ripple logic)
|
||||
2. Number of logic LUT4s does not include count of distributed RAM and
|
||||
ripple logic.
|
||||
Number of clocks: 4
|
||||
Net PHI2_c: 20 loads, 9 rising, 11 falling (Driver: PIO PHI2 )
|
||||
Net RCLK_c: 47 loads, 47 rising, 0 falling (Driver: PIO RCLK )
|
||||
|
||||
Page 1
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 09/21/23 05:39:45
|
||||
|
||||
Design Summary (cont)
|
||||
---------------------
|
||||
Net nCRAS_c: 9 loads, 0 rising, 9 falling (Driver: PIO nCRAS )
|
||||
Net nCCAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCCAS )
|
||||
Number of Clock Enables: 5
|
||||
Net N_178: 1 loads, 1 LSLICEs
|
||||
Net XOR8MEG18: 5 loads, 5 LSLICEs
|
||||
Net N_360_i: 2 loads, 2 LSLICEs
|
||||
Net un1_wb_rst14_i_0: 9 loads, 9 LSLICEs
|
||||
Net CmdUFMData_1_sqmuxa: 1 loads, 1 LSLICEs
|
||||
Number of LSRs: 5
|
||||
Net RA10s_i: 1 loads, 0 LSLICEs
|
||||
Net wb_rst10: 3 loads, 3 LSLICEs
|
||||
Net wb_rst: 1 loads, 0 LSLICEs
|
||||
Net nRRAS_0_sqmuxa: 1 loads, 1 LSLICEs
|
||||
Net RASr2: 2 loads, 2 LSLICEs
|
||||
Number of nets driven by tri-state buffers: 0
|
||||
Top 10 highest fanout non-clock nets:
|
||||
Net InitReady: 41 loads
|
||||
Net FS[11]: 23 loads
|
||||
Net FS[13]: 22 loads
|
||||
Net FS[10]: 21 loads
|
||||
Net FS[12]: 21 loads
|
||||
Net FS[9]: 20 loads
|
||||
Net FS[14]: 18 loads
|
||||
Net CO0: 15 loads
|
||||
Net Ready_fast: 14 loads
|
||||
Net N_214: 13 loads
|
||||
|
||||
|
||||
|
||||
|
||||
Number of warnings: 1
|
||||
Number of errors: 0
|
||||
|
||||
|
||||
Design Errors/Warnings
|
||||
----------------------
|
||||
|
||||
WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
||||
temporarily disable certain features of the device including Power
|
||||
Controller, GSR, Hardened User SPI Port, Hardened Primary User I2C Port.
|
||||
Functionality is restored after the Flash Memory (UFM/Configuration)
|
||||
Interface is disabled using Disable Configuration Interface command 0x26
|
||||
followed by Bypass command 0xFF.
|
||||
|
||||
IO (PIO) Attributes
|
||||
-------------------
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| IO Name | Direction | Levelmode | IO |
|
||||
| | | IO_TYPE | Register |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[0] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[0] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| PHI2 | INPUT | LVCMOS33 | IN |
|
||||
|
||||
Page 2
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 09/21/23 05:39:45
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RDQML | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RDQMH | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRCAS | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRRAS | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRWE | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RCKE | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RCLK | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRCS | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[7] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[6] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[5] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[4] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[3] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[2] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[1] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[11] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[10] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[9] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[8] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[7] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[6] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[5] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[4] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[3] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[2] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[1] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[0] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RBA[1] | OUTPUT | LVCMOS33 | OUT |
|
||||
|
||||
Page 3
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 09/21/23 05:39:45
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RBA[0] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| LED | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nFWE | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nCRAS | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nCCAS | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[7] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[6] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[5] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[4] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[3] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[2] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[1] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[7] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[6] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[5] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[4] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[3] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[2] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[1] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[0] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| CROW[1] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| CROW[0] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[9] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[8] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[7] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[6] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[5] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[4] | INPUT | LVCMOS33 | |
|
||||
|
||||
Page 4
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 09/21/23 05:39:45
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[3] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[2] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[1] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[0] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
Removed logic
|
||||
-------------
|
||||
|
||||
Block GSR_INST undriven or does not drive anything - clipped.
|
||||
Signal nCRAS_c_i was merged into signal nCRAS_c
|
||||
Signal RASr2_i was merged into signal RASr2
|
||||
Signal XOR8MEG.CN was merged into signal PHI2_c
|
||||
Signal GND undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/VCC undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/GND undriven or does not drive anything - clipped.
|
||||
Signal FS_s_0_S1[17] undriven or does not drive anything - clipped.
|
||||
Signal FS_s_0_COUT[17] undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/CFGWAKE undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wbc_ufm_irq undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/TCOC undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/TCINT undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIIRQO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPICSNEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMOSIEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMOSIO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMISOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMISOO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPISCKEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPISCKO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SDAOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SCLOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SDAOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SCLOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
|
||||
|
||||
Page 5
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 09/21/23 05:39:45
|
||||
|
||||
Removed logic (cont)
|
||||
--------------------
|
||||
Signal ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO4 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLWEO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLL1STBO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLL0STBO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLRSTO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLCLKO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wb_dat_o_1[2] undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wb_dat_o_1[3] undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wb_dat_o_1[4] undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wb_dat_o_1[5] undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wb_dat_o_1[6] undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wb_dat_o_1[7] undriven or does not drive anything - clipped.
|
||||
Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped.
|
||||
Signal N_1 undriven or does not drive anything - clipped.
|
||||
Block nCRAS_pad_RNIBPVB was optimized away.
|
||||
Block RASr2_RNIAFR1 was optimized away.
|
||||
Block XOR8MEG.CN was optimized away.
|
||||
Block GND was optimized away.
|
||||
Block ufmefb/VCC was optimized away.
|
||||
Block ufmefb/GND was optimized away.
|
||||
|
||||
|
||||
|
||||
Embedded Functional Block Connection Summary
|
||||
--------------------------------------------
|
||||
|
||||
Desired WISHBONE clock frequency: 66.7 MHz
|
||||
Clock source: RCLK_c
|
||||
Reset source: wb_rst
|
||||
Functions mode:
|
||||
I2C #1 (Primary) Function: DISABLED
|
||||
I2C #2 (Secondary) Function: DISABLED
|
||||
SPI Function: DISABLED
|
||||
Timer/Counter Function: DISABLED
|
||||
Timer/Counter Mode: WB
|
||||
UFM Connection: ENABLED
|
||||
PLL0 Connection: DISABLED
|
||||
PLL1 Connection: DISABLED
|
||||
I2C Function Summary:
|
||||
--------------------
|
||||
None
|
||||
SPI Function Summary:
|
||||
--------------------
|
||||
None
|
||||
Timer/Counter Function Summary:
|
||||
------------------------------
|
||||
None
|
||||
|
||||
Page 6
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 09/21/23 05:39:45
|
||||
|
||||
Embedded Functional Block Connection Summary (cont)
|
||||
---------------------------------------------------
|
||||
UFM Function Summary:
|
||||
--------------------
|
||||
UFM Utilization: General Purpose Flash Memory
|
||||
Initialized UFM Pages: 321 Pages (321*128 Bits)
|
||||
Available General
|
||||
Purpose Flash Memory: 511 Pages (511*128 Bits)
|
||||
|
||||
EBR Blocks with Unique
|
||||
Initialization Data: 0
|
||||
|
||||
WID EBR Instance
|
||||
--- ------------
|
||||
|
||||
|
||||
ASIC Components
|
||||
---------------
|
||||
|
||||
Instance Name: ufmefb/EFBInst_0
|
||||
Type: EFB
|
||||
|
||||
Run Time and Memory Usage
|
||||
-------------------------
|
||||
|
||||
Total CPU Time: 0 secs
|
||||
Total REAL Time: 0 secs
|
||||
Peak Memory Usage: 63 MB
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Page 7
|
||||
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights
|
||||
reserved.
|
||||
|
|
@ -0,0 +1,301 @@
|
|||
PAD Specification File
|
||||
***************************
|
||||
|
||||
PART TYPE: LCMXO2-1200HC
|
||||
Performance Grade: 4
|
||||
PACKAGE: TQFP100
|
||||
Package Status: Final Version 1.44
|
||||
|
||||
Thu Sep 21 05:39:56 2023
|
||||
|
||||
Pinout by Port Name:
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties |
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
| CROW[0] | 10/3 | LVCMOS33_IN | PL4B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| CROW[1] | 16/3 | LVCMOS33_IN | PL8A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[0] | 3/3 | LVCMOS33_IN | PL3A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[1] | 96/0 | LVCMOS33_IN | PT10B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[2] | 88/0 | LVCMOS33_IN | PT12A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[3] | 97/0 | LVCMOS33_IN | PT10A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[4] | 99/0 | LVCMOS33_IN | PT9A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[5] | 98/0 | LVCMOS33_IN | PT9B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[6] | 2/3 | LVCMOS33_IN | PL2D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[7] | 1/3 | LVCMOS33_IN | PL2C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Dout[0] | 76/0 | LVCMOS33_OUT | PT17D | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[1] | 86/0 | LVCMOS33_OUT | PT12C | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[2] | 87/0 | LVCMOS33_OUT | PT12B | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[3] | 85/0 | LVCMOS33_OUT | PT12D | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[4] | 83/0 | LVCMOS33_OUT | PT15B | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[5] | 84/0 | LVCMOS33_OUT | PT15A | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[6] | 78/0 | LVCMOS33_OUT | PT16C | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[7] | 82/0 | LVCMOS33_OUT | PT15C | | | DRIVE:4mA SLEW:FAST |
|
||||
| LED | 34/2 | LVCMOS33_OUT | PB9A | | | DRIVE:24mA SLEW:SLOW |
|
||||
| MAin[0] | 14/3 | LVCMOS33_IN | PL5C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[1] | 12/3 | LVCMOS33_IN | PL5A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[2] | 13/3 | LVCMOS33_IN | PL5B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[3] | 21/3 | LVCMOS33_IN | PL9B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[4] | 20/3 | LVCMOS33_IN | PL9A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[5] | 19/3 | LVCMOS33_IN | PL8D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[6] | 24/3 | LVCMOS33_IN | PL10C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[7] | 18/3 | LVCMOS33_IN | PL8C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[8] | 25/3 | LVCMOS33_IN | PL10D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[9] | 32/2 | LVCMOS33_IN | PB6D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| PHI2 | 8/3 | LVCMOS33_IN | PL3D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| RA[0] | 66/1 | LVCMOS33_OUT | PR4D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[10] | 64/1 | LVCMOS33_OUT | PR5B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[11] | 59/1 | LVCMOS33_OUT | PR8D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[1] | 67/1 | LVCMOS33_OUT | PR4C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[2] | 69/1 | LVCMOS33_OUT | PR4A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[3] | 71/1 | LVCMOS33_OUT | PR3A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[4] | 74/1 | LVCMOS33_OUT | PR2B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[5] | 70/1 | LVCMOS33_OUT | PR3B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[6] | 68/1 | LVCMOS33_OUT | PR4B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[7] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[9] | 62/1 | LVCMOS33_OUT | PR5D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RBA[0] | 58/1 | LVCMOS33_OUT | PR9A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RBA[1] | 60/1 | LVCMOS33_OUT | PR8C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RCKE | 53/1 | LVCMOS33_OUT | PR9D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RCLK | 63/1 | LVCMOS33_IN | PR5C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| RDQMH | 51/1 | LVCMOS33_OUT | PR10D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RDQML | 48/2 | LVCMOS33_OUT | PB20C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RD[0] | 36/2 | LVCMOS33_BIDI | PB11C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[1] | 37/2 | LVCMOS33_BIDI | PB11D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[2] | 38/2 | LVCMOS33_BIDI | PB11A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[3] | 39/2 | LVCMOS33_BIDI | PB11B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[4] | 40/2 | LVCMOS33_BIDI | PB15A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[5] | 41/2 | LVCMOS33_BIDI | PB15B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[6] | 42/2 | LVCMOS33_BIDI | PB18A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[7] | 43/2 | LVCMOS33_BIDI | PB18B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| nCCAS | 9/3 | LVCMOS33_IN | PL4A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nCRAS | 17/3 | LVCMOS33_IN | PL8B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nFWE | 15/3 | LVCMOS33_IN | PL5D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nRCAS | 52/1 | LVCMOS33_OUT | PR10C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nRCS | 57/1 | LVCMOS33_OUT | PR9B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nRRAS | 54/1 | LVCMOS33_OUT | PR9C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nRWE | 49/2 | LVCMOS33_OUT | PB20D | | | DRIVE:4mA SLEW:SLOW |
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
|
||||
Vccio by Bank:
|
||||
+------+-------+
|
||||
| Bank | Vccio |
|
||||
+------+-------+
|
||||
| 0 | 3.3V |
|
||||
| 1 | 3.3V |
|
||||
| 2 | 3.3V |
|
||||
| 3 | 3.3V |
|
||||
+------+-------+
|
||||
|
||||
Vref by Bank:
|
||||
+------+-----+-----------------+---------+
|
||||
| Vref | Pin | Bank # / Vref # | Load(s) |
|
||||
+------+-----+-----------------+---------+
|
||||
+------+-----+-----------------+---------+
|
||||
|
||||
Pinout by Pin Number:
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable |
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
| 1/3 | Din[7] | LOCATED | LVCMOS33_IN | PL2C | L_GPLLT_IN | | |
|
||||
| 2/3 | Din[6] | LOCATED | LVCMOS33_IN | PL2D | L_GPLLC_IN | | |
|
||||
| 3/3 | Din[0] | LOCATED | LVCMOS33_IN | PL3A | PCLKT3_2 | | |
|
||||
| 4/3 | unused, PULL:DOWN | | | PL3B | PCLKC3_2 | | |
|
||||
| 7/3 | unused, PULL:DOWN | | | PL3C | | | |
|
||||
| 8/3 | PHI2 | LOCATED | LVCMOS33_IN | PL3D | | | |
|
||||
| 9/3 | nCCAS | LOCATED | LVCMOS33_IN | PL4A | | | |
|
||||
| 10/3 | CROW[0] | LOCATED | LVCMOS33_IN | PL4B | | | |
|
||||
| 12/3 | MAin[1] | LOCATED | LVCMOS33_IN | PL5A | PCLKT3_1 | | |
|
||||
| 13/3 | MAin[2] | LOCATED | LVCMOS33_IN | PL5B | PCLKC3_1 | | |
|
||||
| 14/3 | MAin[0] | LOCATED | LVCMOS33_IN | PL5C | | | |
|
||||
| 15/3 | nFWE | LOCATED | LVCMOS33_IN | PL5D | | | |
|
||||
| 16/3 | CROW[1] | LOCATED | LVCMOS33_IN | PL8A | | | |
|
||||
| 17/3 | nCRAS | LOCATED | LVCMOS33_IN | PL8B | | | |
|
||||
| 18/3 | MAin[7] | LOCATED | LVCMOS33_IN | PL8C | | | |
|
||||
| 19/3 | MAin[5] | LOCATED | LVCMOS33_IN | PL8D | | | |
|
||||
| 20/3 | MAin[4] | LOCATED | LVCMOS33_IN | PL9A | PCLKT3_0 | | |
|
||||
| 21/3 | MAin[3] | LOCATED | LVCMOS33_IN | PL9B | PCLKC3_0 | | |
|
||||
| 24/3 | MAin[6] | LOCATED | LVCMOS33_IN | PL10C | | | |
|
||||
| 25/3 | MAin[8] | LOCATED | LVCMOS33_IN | PL10D | | | |
|
||||
| 27/2 | unused, PULL:DOWN | | | PB4C | CSSPIN | | |
|
||||
| 28/2 | unused, PULL:DOWN | | | PB4D | | | |
|
||||
| 29/2 | unused, PULL:DOWN | | | PB6A | | | |
|
||||
| 30/2 | unused, PULL:DOWN | | | PB6B | | | |
|
||||
| 31/2 | unused, PULL:DOWN | | | PB6C | MCLK/CCLK | | |
|
||||
| 32/2 | MAin[9] | LOCATED | LVCMOS33_IN | PB6D | SO/SPISO | | |
|
||||
| 34/2 | LED | LOCATED | LVCMOS33_OUT | PB9A | PCLKT2_0 | | |
|
||||
| 35/2 | unused, PULL:DOWN | | | PB9B | PCLKC2_0 | | |
|
||||
| 36/2 | RD[0] | LOCATED | LVCMOS33_BIDI | PB11C | | | |
|
||||
| 37/2 | RD[1] | LOCATED | LVCMOS33_BIDI | PB11D | | | |
|
||||
| 38/2 | RD[2] | LOCATED | LVCMOS33_BIDI | PB11A | PCLKT2_1 | | |
|
||||
| 39/2 | RD[3] | LOCATED | LVCMOS33_BIDI | PB11B | PCLKC2_1 | | |
|
||||
| 40/2 | RD[4] | LOCATED | LVCMOS33_BIDI | PB15A | | | |
|
||||
| 41/2 | RD[5] | LOCATED | LVCMOS33_BIDI | PB15B | | | |
|
||||
| 42/2 | RD[6] | LOCATED | LVCMOS33_BIDI | PB18A | | | |
|
||||
| 43/2 | RD[7] | LOCATED | LVCMOS33_BIDI | PB18B | | | |
|
||||
| 45/2 | unused, PULL:DOWN | | | PB18C | | | |
|
||||
| 47/2 | unused, PULL:DOWN | | | PB18D | | | |
|
||||
| 48/2 | RDQML | LOCATED | LVCMOS33_OUT | PB20C | SN | | |
|
||||
| 49/2 | nRWE | LOCATED | LVCMOS33_OUT | PB20D | SI/SISPI | | |
|
||||
| 51/1 | RDQMH | LOCATED | LVCMOS33_OUT | PR10D | DQ1 | | |
|
||||
| 52/1 | nRCAS | LOCATED | LVCMOS33_OUT | PR10C | DQ1 | | |
|
||||
| 53/1 | RCKE | LOCATED | LVCMOS33_OUT | PR9D | DQ1 | | |
|
||||
| 54/1 | nRRAS | LOCATED | LVCMOS33_OUT | PR9C | DQ1 | | |
|
||||
| 57/1 | nRCS | LOCATED | LVCMOS33_OUT | PR9B | DQ1 | | |
|
||||
| 58/1 | RBA[0] | LOCATED | LVCMOS33_OUT | PR9A | DQ1 | | |
|
||||
| 59/1 | RA[11] | LOCATED | LVCMOS33_OUT | PR8D | DQ1 | | |
|
||||
| 60/1 | RBA[1] | LOCATED | LVCMOS33_OUT | PR8C | DQ1 | | |
|
||||
| 61/1 | unused, PULL:DOWN | | | PR8A | DQS1 | | |
|
||||
| 62/1 | RA[9] | LOCATED | LVCMOS33_OUT | PR5D | PCLKC1_0/DQ0 | | |
|
||||
| 63/1 | RCLK | LOCATED | LVCMOS33_IN | PR5C | PCLKT1_0/DQ0 | | |
|
||||
| 64/1 | RA[10] | LOCATED | LVCMOS33_OUT | PR5B | DQS0N | | |
|
||||
| 65/1 | RA[8] | LOCATED | LVCMOS33_OUT | PR5A | DQS0 | | |
|
||||
| 66/1 | RA[0] | LOCATED | LVCMOS33_OUT | PR4D | DQ0 | | |
|
||||
| 67/1 | RA[1] | LOCATED | LVCMOS33_OUT | PR4C | DQ0 | | |
|
||||
| 68/1 | RA[6] | LOCATED | LVCMOS33_OUT | PR4B | DQ0 | | |
|
||||
| 69/1 | RA[2] | LOCATED | LVCMOS33_OUT | PR4A | DQ0 | | |
|
||||
| 70/1 | RA[5] | LOCATED | LVCMOS33_OUT | PR3B | DQ0 | | |
|
||||
| 71/1 | RA[3] | LOCATED | LVCMOS33_OUT | PR3A | DQ0 | | |
|
||||
| 74/1 | RA[4] | LOCATED | LVCMOS33_OUT | PR2B | DQ0 | | |
|
||||
| 75/1 | RA[7] | LOCATED | LVCMOS33_OUT | PR2A | DQ0 | | |
|
||||
| 76/0 | Dout[0] | LOCATED | LVCMOS33_OUT | PT17D | DONE | | |
|
||||
| 77/0 | unused, PULL:DOWN | | | PT17C | INITN | | |
|
||||
| 78/0 | Dout[6] | LOCATED | LVCMOS33_OUT | PT16C | | | |
|
||||
| 81/0 | unused, PULL:DOWN | | | PT15D | PROGRAMN | | |
|
||||
| 82/0 | Dout[7] | LOCATED | LVCMOS33_OUT | PT15C | JTAGENB | | |
|
||||
| 83/0 | Dout[4] | LOCATED | LVCMOS33_OUT | PT15B | | | |
|
||||
| 84/0 | Dout[5] | LOCATED | LVCMOS33_OUT | PT15A | | | |
|
||||
| 85/0 | Dout[3] | LOCATED | LVCMOS33_OUT | PT12D | SDA/PCLKC0_0 | | |
|
||||
| 86/0 | Dout[1] | LOCATED | LVCMOS33_OUT | PT12C | SCL/PCLKT0_0 | | |
|
||||
| 87/0 | Dout[2] | LOCATED | LVCMOS33_OUT | PT12B | PCLKC0_1 | | |
|
||||
| 88/0 | Din[2] | LOCATED | LVCMOS33_IN | PT12A | PCLKT0_1 | | |
|
||||
| 90/0 | Reserved: sysCONFIG | | | PT11D | TMS | | |
|
||||
| 91/0 | Reserved: sysCONFIG | | | PT11C | TCK | | |
|
||||
| 94/0 | Reserved: sysCONFIG | | | PT10D | TDI | | |
|
||||
| 95/0 | Reserved: sysCONFIG | | | PT10C | TDO | | |
|
||||
| 96/0 | Din[1] | LOCATED | LVCMOS33_IN | PT10B | | | |
|
||||
| 97/0 | Din[3] | LOCATED | LVCMOS33_IN | PT10A | | | |
|
||||
| 98/0 | Din[5] | LOCATED | LVCMOS33_IN | PT9B | | | |
|
||||
| 99/0 | Din[4] | LOCATED | LVCMOS33_IN | PT9A | | | |
|
||||
| PB4A/2 | unused, PULL:DOWN | | | PB4A | | | |
|
||||
| PB4B/2 | unused, PULL:DOWN | | | PB4B | | | |
|
||||
| PB9C/2 | unused, PULL:DOWN | | | PB9C | | | |
|
||||
| PB9D/2 | unused, PULL:DOWN | | | PB9D | | | |
|
||||
| PB15C/2 | unused, PULL:DOWN | | | PB15C | | | |
|
||||
| PB15D/2 | unused, PULL:DOWN | | | PB15D | | | |
|
||||
| PB20A/2 | unused, PULL:DOWN | | | PB20A | | | |
|
||||
| PB20B/2 | unused, PULL:DOWN | | | PB20B | | | |
|
||||
| PL2A/3 | unused, PULL:DOWN | | | PL2A | L_GPLLT_FB | | |
|
||||
| PL2B/3 | unused, PULL:DOWN | | | PL2B | L_GPLLC_FB | | |
|
||||
| PL4C/3 | unused, PULL:DOWN | | | PL4C | | | |
|
||||
| PL4D/3 | unused, PULL:DOWN | | | PL4D | | | |
|
||||
| PL10A/3 | unused, PULL:DOWN | | | PL10A | | | |
|
||||
| PL10B/3 | unused, PULL:DOWN | | | PL10B | | | |
|
||||
| PR2C/1 | unused, PULL:DOWN | | | PR2C | DQ0 | | |
|
||||
| PR2D/1 | unused, PULL:DOWN | | | PR2D | DQ0 | | |
|
||||
| PR8B/1 | unused, PULL:DOWN | | | PR8B | DQS1N | | |
|
||||
| PR10A/1 | unused, PULL:DOWN | | | PR10A | DQ1 | | |
|
||||
| PR10B/1 | unused, PULL:DOWN | | | PR10B | DQ1 | | |
|
||||
| PT9C/0 | unused, PULL:DOWN | | | PT9C | | | |
|
||||
| PT9D/0 | unused, PULL:DOWN | | | PT9D | | | |
|
||||
| PT11A/0 | unused, PULL:DOWN | | | PT11A | | | |
|
||||
| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | |
|
||||
| PT16A/0 | unused, PULL:DOWN | | | PT16A | | | |
|
||||
| PT16B/0 | unused, PULL:DOWN | | | PT16B | | | |
|
||||
| PT16D/0 | unused, PULL:DOWN | | | PT16D | | | |
|
||||
| PT17A/0 | unused, PULL:DOWN | | | PT17A | | | |
|
||||
| PT17B/0 | unused, PULL:DOWN | | | PT17B | | | |
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
|
||||
sysCONFIG Pins:
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode |
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
| PT11D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP |
|
||||
| PT11C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down |
|
||||
| PT10D | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP |
|
||||
| PT10C | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP |
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
|
||||
Dedicated sysCONFIG Pins:
|
||||
|
||||
|
||||
List of All Pins' Locate Preferences Based on Final Placement After PAR
|
||||
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste):
|
||||
|
||||
LOCATE COMP "CROW[0]" SITE "10";
|
||||
LOCATE COMP "CROW[1]" SITE "16";
|
||||
LOCATE COMP "Din[0]" SITE "3";
|
||||
LOCATE COMP "Din[1]" SITE "96";
|
||||
LOCATE COMP "Din[2]" SITE "88";
|
||||
LOCATE COMP "Din[3]" SITE "97";
|
||||
LOCATE COMP "Din[4]" SITE "99";
|
||||
LOCATE COMP "Din[5]" SITE "98";
|
||||
LOCATE COMP "Din[6]" SITE "2";
|
||||
LOCATE COMP "Din[7]" SITE "1";
|
||||
LOCATE COMP "Dout[0]" SITE "76";
|
||||
LOCATE COMP "Dout[1]" SITE "86";
|
||||
LOCATE COMP "Dout[2]" SITE "87";
|
||||
LOCATE COMP "Dout[3]" SITE "85";
|
||||
LOCATE COMP "Dout[4]" SITE "83";
|
||||
LOCATE COMP "Dout[5]" SITE "84";
|
||||
LOCATE COMP "Dout[6]" SITE "78";
|
||||
LOCATE COMP "Dout[7]" SITE "82";
|
||||
LOCATE COMP "LED" SITE "34";
|
||||
LOCATE COMP "MAin[0]" SITE "14";
|
||||
LOCATE COMP "MAin[1]" SITE "12";
|
||||
LOCATE COMP "MAin[2]" SITE "13";
|
||||
LOCATE COMP "MAin[3]" SITE "21";
|
||||
LOCATE COMP "MAin[4]" SITE "20";
|
||||
LOCATE COMP "MAin[5]" SITE "19";
|
||||
LOCATE COMP "MAin[6]" SITE "24";
|
||||
LOCATE COMP "MAin[7]" SITE "18";
|
||||
LOCATE COMP "MAin[8]" SITE "25";
|
||||
LOCATE COMP "MAin[9]" SITE "32";
|
||||
LOCATE COMP "PHI2" SITE "8";
|
||||
LOCATE COMP "RA[0]" SITE "66";
|
||||
LOCATE COMP "RA[10]" SITE "64";
|
||||
LOCATE COMP "RA[11]" SITE "59";
|
||||
LOCATE COMP "RA[1]" SITE "67";
|
||||
LOCATE COMP "RA[2]" SITE "69";
|
||||
LOCATE COMP "RA[3]" SITE "71";
|
||||
LOCATE COMP "RA[4]" SITE "74";
|
||||
LOCATE COMP "RA[5]" SITE "70";
|
||||
LOCATE COMP "RA[6]" SITE "68";
|
||||
LOCATE COMP "RA[7]" SITE "75";
|
||||
LOCATE COMP "RA[8]" SITE "65";
|
||||
LOCATE COMP "RA[9]" SITE "62";
|
||||
LOCATE COMP "RBA[0]" SITE "58";
|
||||
LOCATE COMP "RBA[1]" SITE "60";
|
||||
LOCATE COMP "RCKE" SITE "53";
|
||||
LOCATE COMP "RCLK" SITE "63";
|
||||
LOCATE COMP "RDQMH" SITE "51";
|
||||
LOCATE COMP "RDQML" SITE "48";
|
||||
LOCATE COMP "RD[0]" SITE "36";
|
||||
LOCATE COMP "RD[1]" SITE "37";
|
||||
LOCATE COMP "RD[2]" SITE "38";
|
||||
LOCATE COMP "RD[3]" SITE "39";
|
||||
LOCATE COMP "RD[4]" SITE "40";
|
||||
LOCATE COMP "RD[5]" SITE "41";
|
||||
LOCATE COMP "RD[6]" SITE "42";
|
||||
LOCATE COMP "RD[7]" SITE "43";
|
||||
LOCATE COMP "nCCAS" SITE "9";
|
||||
LOCATE COMP "nCRAS" SITE "17";
|
||||
LOCATE COMP "nFWE" SITE "15";
|
||||
LOCATE COMP "nRCAS" SITE "52";
|
||||
LOCATE COMP "nRCS" SITE "57";
|
||||
LOCATE COMP "nRRAS" SITE "54";
|
||||
LOCATE COMP "nRWE" SITE "49";
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Thu Sep 21 05:39:59 2023
|
||||
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
SCHEMATIC START ;
|
||||
# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Sat Aug 19 21:54:57 2023
|
||||
# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Thu Sep 21 05:39:45 2023
|
||||
|
||||
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
|
||||
LOCATE COMP "RD[0]" SITE "36" ;
|
||||
|
|
@ -11,7 +11,7 @@ LOCATE COMP "nRCAS" SITE "52" ;
|
|||
LOCATE COMP "nRRAS" SITE "54" ;
|
||||
LOCATE COMP "nRWE" SITE "49" ;
|
||||
LOCATE COMP "RCKE" SITE "53" ;
|
||||
LOCATE COMP "RCLK" SITE "62" ;
|
||||
LOCATE COMP "RCLK" SITE "63" ;
|
||||
LOCATE COMP "nRCS" SITE "57" ;
|
||||
LOCATE COMP "RD[7]" SITE "43" ;
|
||||
LOCATE COMP "RD[6]" SITE "42" ;
|
||||
|
|
@ -22,7 +22,7 @@ LOCATE COMP "RD[2]" SITE "38" ;
|
|||
LOCATE COMP "RD[1]" SITE "37" ;
|
||||
LOCATE COMP "RA[11]" SITE "59" ;
|
||||
LOCATE COMP "RA[10]" SITE "64" ;
|
||||
LOCATE COMP "RA[9]" SITE "63" ;
|
||||
LOCATE COMP "RA[9]" SITE "62" ;
|
||||
LOCATE COMP "RA[8]" SITE "65" ;
|
||||
LOCATE COMP "RA[7]" SITE "75" ;
|
||||
LOCATE COMP "RA[6]" SITE "68" ;
|
||||
|
|
@ -72,4 +72,42 @@ FREQUENCY PORT "RCLK" 62.500000 MHz ;
|
|||
SCHEMATIC END ;
|
||||
BLOCK RESETPATHS ;
|
||||
BLOCK ASYNCPATHS ;
|
||||
OUTPUT PORT "Dout[0]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Dout[1]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Dout[2]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Dout[3]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Dout[4]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Dout[5]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Dout[6]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "Dout[7]" LOAD 15.000000 pF ;
|
||||
OUTPUT PORT "LED" LOAD 10.000000 pF ;
|
||||
OUTPUT PORT "RA[0]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[1]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[2]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[3]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[4]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[5]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[6]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[7]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[8]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[9]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[10]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RA[11]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RBA[0]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RBA[1]" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RCKE" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RDQMH" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RDQML" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "nRCAS" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "nRCS" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "nRRAS" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "nRWE" LOAD 5.000000 pF ;
|
||||
OUTPUT PORT "RD[0]" LOAD 9.000000 pF ;
|
||||
OUTPUT PORT "RD[1]" LOAD 9.000000 pF ;
|
||||
OUTPUT PORT "RD[2]" LOAD 9.000000 pF ;
|
||||
OUTPUT PORT "RD[3]" LOAD 9.000000 pF ;
|
||||
OUTPUT PORT "RD[4]" LOAD 9.000000 pF ;
|
||||
OUTPUT PORT "RD[5]" LOAD 9.000000 pF ;
|
||||
OUTPUT PORT "RD[6]" LOAD 9.000000 pF ;
|
||||
OUTPUT PORT "RD[7]" LOAD 9.000000 pF ;
|
||||
COMMERCIAL ;
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,415 @@
|
|||
|
||||
Loading design for application trce from file ram2gs_lcmxo2_1200hc_impl1_map.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-1200HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.44.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
Setup and Hold Report
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
|
||||
Thu Sep 21 05:39:46 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
Report Information
|
||||
------------------
|
||||
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_1200HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
|
||||
Design file: ram2gs_lcmxo2_1200hc_impl1_map.ncd
|
||||
Preference file: ram2gs_lcmxo2_1200hc_impl1.prf
|
||||
Device,speed: LCMXO2-1200HC,4
|
||||
Report level: verbose report, limited to 1 item per preference
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
BLOCK ASYNCPATHS
|
||||
BLOCK RESETPATHS
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
================================================================================
|
||||
Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
|
||||
147 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 163.025ns (weighted slack = 326.050ns)
|
||||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q Bank_0io[0] (from PHI2_c +)
|
||||
Destination: FF Data in CmdEnable (to PHI2_c -)
|
||||
|
||||
Delay: 9.223ns (33.1% logic, 66.9% route), 6 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
9.223ns physical path delay Din[0]_MGIOL to SLICE_17 meets
|
||||
172.414ns delay constraint less
|
||||
0.166ns DIN_SET requirement (totaling 172.248ns) by 163.025ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path Din[0]_MGIOL to SLICE_17:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
C2INP_DEL --- 0.577 *[0]_MGIOL.CLK to *n[0]_MGIOL.IN Din[0]_MGIOL (from PHI2_c)
|
||||
ROUTE 1 e 1.234 *n[0]_MGIOL.IN to SLICE_93.A0 Bank[0]
|
||||
CTOF_DEL --- 0.495 SLICE_93.A0 to SLICE_93.F0 SLICE_93
|
||||
ROUTE 1 e 1.234 SLICE_93.F0 to SLICE_84.C0 un1_CmdEnable20_0_0_o3_10
|
||||
CTOF_DEL --- 0.495 SLICE_84.C0 to SLICE_84.F0 SLICE_84
|
||||
ROUTE 6 e 1.234 SLICE_84.F0 to SLICE_11.C1 un1_CmdEnable20_0_0_o3
|
||||
CTOF_DEL --- 0.495 SLICE_11.C1 to SLICE_11.F1 SLICE_11
|
||||
ROUTE 3 e 1.234 SLICE_11.F1 to SLICE_33.B0 CmdEnable16
|
||||
CTOF_DEL --- 0.495 SLICE_33.B0 to SLICE_33.F0 SLICE_33
|
||||
ROUTE 1 e 1.234 SLICE_33.F0 to SLICE_17.D0 CmdEnable_0_sqmuxa
|
||||
CTOF_DEL --- 0.495 SLICE_17.D0 to SLICE_17.F0 SLICE_17
|
||||
ROUTE 1 e 0.001 SLICE_17.F0 to SLICE_17.DI0 CmdEnable_s (to PHI2_c)
|
||||
--------
|
||||
9.223 (33.1% logic, 66.9% route), 6 logic levels.
|
||||
|
||||
Report: 53.254MHz is the maximum frequency for this preference.
|
||||
|
||||
|
||||
================================================================================
|
||||
Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
|
||||
0 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 338.168ns
|
||||
The internal maximum frequency of the following component is 150.150 MHz
|
||||
|
||||
Logical Details: Cell type Pin name Component name
|
||||
|
||||
Destination: PIO PAD nCCAS
|
||||
|
||||
Delay: 6.660ns -- based on Minimum Pulse Width
|
||||
|
||||
Report: 150.150MHz is the maximum frequency for this preference.
|
||||
|
||||
|
||||
================================================================================
|
||||
Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
|
||||
0 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 338.168ns
|
||||
The internal maximum frequency of the following component is 150.150 MHz
|
||||
|
||||
Logical Details: Cell type Pin name Component name
|
||||
|
||||
Destination: PIO PAD nCRAS
|
||||
|
||||
Delay: 6.660ns -- based on Minimum Pulse Width
|
||||
|
||||
Report: 150.150MHz is the maximum frequency for this preference.
|
||||
|
||||
|
||||
================================================================================
|
||||
Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
|
||||
878 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 6.049ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q IS[1] (from RCLK_c +)
|
||||
Destination: FF Data in nRCAS_0io (to RCLK_c +)
|
||||
|
||||
Delay: 9.798ns (34.9% logic, 65.1% route), 7 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
9.798ns physical path delay SLICE_27 to nRCAS_MGIOL meets
|
||||
16.000ns delay constraint less
|
||||
0.153ns DO_SET requirement (totaling 15.847ns) by 6.049ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path SLICE_27 to nRCAS_MGIOL:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.452 SLICE_27.CLK to SLICE_27.Q0 SLICE_27 (from RCLK_c)
|
||||
ROUTE 7 e 1.234 SLICE_27.Q0 to SLICE_74.A1 IS[1]
|
||||
CTOF_DEL --- 0.495 SLICE_74.A1 to SLICE_74.F1 SLICE_74
|
||||
ROUTE 2 e 0.480 SLICE_74.F1 to SLICE_74.B0 un1_nRCAS_6_sqmuxa_i_0_0_o2_0
|
||||
CTOF_DEL --- 0.495 SLICE_74.B0 to SLICE_74.F0 SLICE_74
|
||||
ROUTE 2 e 1.234 SLICE_74.F0 to SLICE_61.B1 N_408
|
||||
CTOF_DEL --- 0.495 SLICE_61.B1 to SLICE_61.F1 SLICE_61
|
||||
ROUTE 1 e 0.480 SLICE_61.F1 to SLICE_61.A0 un1_nRCAS_6_sqmuxa_i_0_0
|
||||
CTOF_DEL --- 0.495 SLICE_61.A0 to SLICE_61.F0 SLICE_61
|
||||
ROUTE 1 e 1.234 SLICE_61.F0 to SLICE_94.D0 nRCAS_r_i_0_o2_0_0
|
||||
CTOF_DEL --- 0.495 SLICE_94.D0 to SLICE_94.F0 SLICE_94
|
||||
ROUTE 1 e 0.480 SLICE_94.F0 to SLICE_94.A1 N_248_i_1
|
||||
CTOF_DEL --- 0.495 SLICE_94.A1 to SLICE_94.F1 SLICE_94
|
||||
ROUTE 1 e 1.234 SLICE_94.F1 to *AS_MGIOL.OPOS N_248_i (to RCLK_c)
|
||||
--------
|
||||
9.798 (34.9% logic, 65.1% route), 7 logic levels.
|
||||
|
||||
Report: 100.492MHz is the maximum frequency for this preference.
|
||||
|
||||
Report Summary
|
||||
--------------
|
||||
----------------------------------------------------------------------------
|
||||
Preference | Constraint| Actual|Levels
|
||||
----------------------------------------------------------------------------
|
||||
| | |
|
||||
FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 53.254 MHz| 6
|
||||
| | |
|
||||
FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
|
||||
| | |
|
||||
FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
|
||||
| | |
|
||||
FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 100.492 MHz| 7
|
||||
| | |
|
||||
----------------------------------------------------------------------------
|
||||
|
||||
|
||||
All preferences were met.
|
||||
|
||||
|
||||
Clock Domains Analysis
|
||||
------------------------
|
||||
|
||||
Found 4 clocks:
|
||||
|
||||
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11
|
||||
No transfer within this clock domain is found
|
||||
|
||||
Data transfers from:
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD
|
||||
Not reported because source and destination domains are unrelated.
|
||||
To report these transfers please refer to preference CLKSKEWDIFF to define
|
||||
external clock skew between clock ports.
|
||||
|
||||
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
|
||||
No transfer within this clock domain is found
|
||||
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47
|
||||
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
|
||||
|
||||
Data transfers from:
|
||||
Clock Domain: nCRAS_c Source: nCRAS.PAD
|
||||
Not reported because source and destination domains are unrelated.
|
||||
To report these transfers please refer to preference CLKSKEWDIFF to define
|
||||
external clock skew between clock ports.
|
||||
|
||||
Clock Domain: PHI2_c Source: PHI2.PAD
|
||||
Not reported because source and destination domains are unrelated.
|
||||
To report these transfers please refer to preference CLKSKEWDIFF to define
|
||||
external clock skew between clock ports.
|
||||
|
||||
Clock Domain: PHI2_c Source: PHI2.PAD Loads: 21
|
||||
Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
|
||||
|
||||
Data transfers from:
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD
|
||||
Not reported because source and destination domains are unrelated.
|
||||
To report these transfers please refer to preference CLKSKEWDIFF to define
|
||||
external clock skew between clock ports.
|
||||
|
||||
|
||||
Timing summary (Setup):
|
||||
---------------
|
||||
|
||||
Timing errors: 0 Score: 0
|
||||
Cumulative negative slack: 0
|
||||
|
||||
Constraints cover 1025 paths, 4 nets, and 741 connections (72.86% coverage)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
|
||||
Thu Sep 21 05:39:46 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
Report Information
|
||||
------------------
|
||||
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_1200HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
|
||||
Design file: ram2gs_lcmxo2_1200hc_impl1_map.ncd
|
||||
Preference file: ram2gs_lcmxo2_1200hc_impl1.prf
|
||||
Device,speed: LCMXO2-1200HC,M
|
||||
Report level: verbose report, limited to 1 item per preference
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
BLOCK ASYNCPATHS
|
||||
BLOCK RESETPATHS
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
================================================================================
|
||||
Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
|
||||
147 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 0.447ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q ADSubmitted (from PHI2_c -)
|
||||
Destination: FF Data in ADSubmitted (to PHI2_c -)
|
||||
|
||||
Delay: 0.434ns (53.9% logic, 46.1% route), 2 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
0.434ns physical path delay SLICE_10 to SLICE_10 meets
|
||||
-0.013ns DIN_HLD and
|
||||
0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path SLICE_10 to SLICE_10:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.133 SLICE_10.CLK to SLICE_10.Q0 SLICE_10 (from PHI2_c)
|
||||
ROUTE 2 e 0.199 SLICE_10.Q0 to SLICE_10.A0 ADSubmitted
|
||||
CTOF_DEL --- 0.101 SLICE_10.A0 to SLICE_10.F0 SLICE_10
|
||||
ROUTE 1 e 0.001 SLICE_10.F0 to SLICE_10.DI0 ADSubmitted_r_0_0 (to PHI2_c)
|
||||
--------
|
||||
0.434 (53.9% logic, 46.1% route), 2 logic levels.
|
||||
|
||||
|
||||
================================================================================
|
||||
Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
|
||||
0 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
================================================================================
|
||||
Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
|
||||
0 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
================================================================================
|
||||
Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
|
||||
878 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 0.351ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q CASr (from RCLK_c +)
|
||||
Destination: FF Data in CASr2 (to RCLK_c +)
|
||||
|
||||
Delay: 0.332ns (40.1% logic, 59.9% route), 1 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
0.332ns physical path delay SLICE_12 to SLICE_12 meets
|
||||
-0.019ns M_HLD and
|
||||
0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path SLICE_12 to SLICE_12:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.133 SLICE_12.CLK to SLICE_12.Q0 SLICE_12 (from RCLK_c)
|
||||
ROUTE 1 e 0.199 SLICE_12.Q0 to SLICE_12.M1 CASr (to RCLK_c)
|
||||
--------
|
||||
0.332 (40.1% logic, 59.9% route), 1 logic levels.
|
||||
|
||||
Report Summary
|
||||
--------------
|
||||
----------------------------------------------------------------------------
|
||||
Preference(MIN Delays) | Constraint| Actual|Levels
|
||||
----------------------------------------------------------------------------
|
||||
| | |
|
||||
FREQUENCY PORT "PHI2" 2.900000 MHz ; | -| -| 2
|
||||
| | |
|
||||
FREQUENCY PORT "nCCAS" 2.900000 MHz ; | -| -| 0
|
||||
| | |
|
||||
FREQUENCY PORT "nCRAS" 2.900000 MHz ; | -| -| 0
|
||||
| | |
|
||||
FREQUENCY PORT "RCLK" 62.500000 MHz ; | -| -| 1
|
||||
| | |
|
||||
----------------------------------------------------------------------------
|
||||
|
||||
|
||||
All preferences were met.
|
||||
|
||||
|
||||
Clock Domains Analysis
|
||||
------------------------
|
||||
|
||||
Found 4 clocks:
|
||||
|
||||
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11
|
||||
No transfer within this clock domain is found
|
||||
|
||||
Data transfers from:
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD
|
||||
Not reported because source and destination domains are unrelated.
|
||||
To report these transfers please refer to preference CLKSKEWDIFF to define
|
||||
external clock skew between clock ports.
|
||||
|
||||
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
|
||||
No transfer within this clock domain is found
|
||||
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47
|
||||
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
|
||||
|
||||
Data transfers from:
|
||||
Clock Domain: nCRAS_c Source: nCRAS.PAD
|
||||
Not reported because source and destination domains are unrelated.
|
||||
To report these transfers please refer to preference CLKSKEWDIFF to define
|
||||
external clock skew between clock ports.
|
||||
|
||||
Clock Domain: PHI2_c Source: PHI2.PAD
|
||||
Not reported because source and destination domains are unrelated.
|
||||
To report these transfers please refer to preference CLKSKEWDIFF to define
|
||||
external clock skew between clock ports.
|
||||
|
||||
Clock Domain: PHI2_c Source: PHI2.PAD Loads: 21
|
||||
Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
|
||||
|
||||
Data transfers from:
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD
|
||||
Not reported because source and destination domains are unrelated.
|
||||
To report these transfers please refer to preference CLKSKEWDIFF to define
|
||||
external clock skew between clock ports.
|
||||
|
||||
|
||||
Timing summary (Hold):
|
||||
---------------
|
||||
|
||||
Timing errors: 0 Score: 0
|
||||
Cumulative negative slack: 0
|
||||
|
||||
Constraints cover 1025 paths, 4 nets, and 741 connections (72.86% coverage)
|
||||
|
||||
|
||||
|
||||
Timing summary (Setup and Hold):
|
||||
---------------
|
||||
|
||||
Timing errors: 0 (setup), 0 (hold)
|
||||
Score: 0 (setup), 0 (hold)
|
||||
Cumulative negative slack: 0 (0+0)
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,142 @@
|
|||
<HTML>
|
||||
<HEAD><TITLE>Bitgen Report</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Bgn"></A>BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Thu Sep 21 05:40:13 2023
|
||||
|
||||
|
||||
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC -w -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
|
||||
|
||||
Loading design for application Bitgen from file RAM2GS_LCMXO2_1200HC_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-1200HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application Bitgen from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.44.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
|
||||
Running DRC.
|
||||
DRC detected 0 errors and 0 warnings.
|
||||
Reading Preference File from RAM2GS_LCMXO2_1200HC_impl1.prf.
|
||||
|
||||
<A name="bgn_ps"></A>
|
||||
<B><U><big>Preference Summary:</big></U></B>
|
||||
|
||||
+---------------------------------+---------------------------------+
|
||||
| Preference | Current Setting |
|
||||
+---------------------------------+---------------------------------+
|
||||
| RamCfg | Reset** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MCCLK_FREQ | 2.08** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| CONFIG_SECURE | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| INBUF | ON** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| JTAG_PORT | ENABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SDM_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SLAVE_SPI_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MASTER_SPI_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| I2C_PORT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MUX_CONFIGURATION_PORTS | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| CONFIGURATION | CFG** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| COMPRESS_CONFIG | ON** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| MY_ASSP | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| ONE_TIME_PROGRAM | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| ENABLE_TRANSFR | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| SHAREDEBRINIT | DISABLE** |
|
||||
+---------------------------------+---------------------------------+
|
||||
| BACKGROUND_RECONFIG | OFF** |
|
||||
+---------------------------------+---------------------------------+
|
||||
* Default setting.
|
||||
** The specified setting matches the default setting.
|
||||
|
||||
|
||||
Creating bit map...
|
||||
|
||||
Bitstream Status: Final Version 1.95.
|
||||
|
||||
Saving bit stream in "RAM2GS_LCMXO2_1200HC_impl1.bit".
|
||||
Total CPU Time: 4 secs
|
||||
Total REAL Time: 4 secs
|
||||
Peak Memory Usage: 274 MB
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
|
|
@ -13,12 +13,12 @@ Hostname: ZANEMACWIN11
|
|||
|
||||
Implementation : impl1
|
||||
|
||||
# Written on Sat Aug 19 21:54:51 2023
|
||||
# Written on Thu Sep 21 05:39:38 2023
|
||||
|
||||
##### DESIGN INFO #######################################################
|
||||
|
||||
Top View: "RAM2GS"
|
||||
Constraint File(s): "Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc"
|
||||
Constraint File(s): "\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS.sdc"
|
||||
|
||||
|
||||
|
||||
|
|
@ -50,11 +50,11 @@ nCRAS RCLK | No paths | No paths | No p
|
|||
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
|
||||
|
||||
|
||||
@W:"y:/repos/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.
|
||||
@W:"y:/repos/ram2gs/cpld/ram2gs.sdc":3:0:3:0|Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.
|
||||
@W:"y:/repos/ram2gs/cpld/ram2gs.sdc":2:0:2:0|Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.
|
||||
@W:"y:/repos/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.
|
||||
@W:"y:/repos/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.
|
||||
@W:"//mac/icloud/repos/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.
|
||||
@W:"//mac/icloud/repos/ram2gs/cpld/ram2gs.sdc":3:0:3:0|Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.
|
||||
@W:"//mac/icloud/repos/ram2gs/cpld/ram2gs.sdc":2:0:2:0|Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.
|
||||
@W:"//mac/icloud/repos/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.
|
||||
@W:"//mac/icloud/repos/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.
|
||||
|
||||
|
||||
Unconstrained Start/End Points
|
||||
|
|
@ -0,0 +1,199 @@
|
|||
<HTML>
|
||||
<HEAD><TITLE>I/O Timing Report</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Top"></A><B><U><big>I/O Timing Report</big></U></B>
|
||||
Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-1200HC
|
||||
Package: TQFP100
|
||||
Performance: 5
|
||||
Package Status: Final Version 1.44.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-1200HC
|
||||
Package: TQFP100
|
||||
Performance: 6
|
||||
Package Status: Final Version 1.44.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-1200HC
|
||||
Package: TQFP100
|
||||
Performance: M
|
||||
Package Status: Final Version 1.44.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
// Design: RAM2GS
|
||||
// Package: TQFP100
|
||||
// ncd File: ram2gs_lcmxo2_1200hc_impl1.ncd
|
||||
// Version: Diamond (64-bit) 3.12.1.454
|
||||
// Written on Thu Sep 21 05:40:06 2023
|
||||
// M: Minimum Performance Grade
|
||||
// iotiming RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml
|
||||
|
||||
I/O Timing Report (All units are in ns)
|
||||
|
||||
Worst Case Results across Performance Grades (M, 6, 5, 4):
|
||||
|
||||
// Input Setup and Hold Times
|
||||
|
||||
Port Clock Edge Setup Performance_Grade Hold Performance_Grade
|
||||
----------------------------------------------------------------------
|
||||
CROW[0] nCRAS F 2.913 4 -0.274 M
|
||||
CROW[1] nCRAS F 2.475 4 -0.161 M
|
||||
Din[0] PHI2 F 5.366 4 4.293 4
|
||||
Din[0] nCCAS F 1.448 4 -0.034 M
|
||||
Din[1] PHI2 F 4.971 4 4.173 4
|
||||
Din[1] nCCAS F 0.519 4 0.708 4
|
||||
Din[2] PHI2 F 5.192 4 4.173 4
|
||||
Din[2] nCCAS F 1.948 4 -0.142 M
|
||||
Din[3] PHI2 F 5.298 4 4.173 4
|
||||
Din[3] nCCAS F 1.974 4 -0.157 M
|
||||
Din[4] PHI2 F 4.281 4 4.173 4
|
||||
Din[4] nCCAS F 1.060 4 0.217 4
|
||||
Din[5] PHI2 F 5.059 4 4.173 4
|
||||
Din[5] nCCAS F 1.956 4 -0.150 M
|
||||
Din[6] PHI2 F 4.644 4 4.293 4
|
||||
Din[6] nCCAS F 2.886 4 -0.382 M
|
||||
Din[7] PHI2 F 5.316 4 4.293 4
|
||||
Din[7] nCCAS F 2.381 4 -0.244 M
|
||||
MAin[0] PHI2 F 4.362 4 1.145 4
|
||||
MAin[0] nCRAS F 1.189 4 0.362 4
|
||||
MAin[1] PHI2 F 4.386 4 0.999 4
|
||||
MAin[1] nCRAS F 1.884 4 -0.024 M
|
||||
MAin[2] PHI2 F 9.426 4 -0.750 M
|
||||
MAin[2] nCRAS F 1.136 4 0.453 4
|
||||
MAin[3] PHI2 F 10.458 4 -0.997 M
|
||||
MAin[3] nCRAS F 1.564 4 0.067 4
|
||||
MAin[4] PHI2 F 11.109 4 -1.209 M
|
||||
MAin[4] nCRAS F 1.390 4 0.207 4
|
||||
MAin[5] PHI2 F 9.884 4 -0.896 M
|
||||
MAin[5] nCRAS F 1.269 4 0.218 4
|
||||
MAin[6] PHI2 F 9.859 4 -0.845 M
|
||||
MAin[6] nCRAS F 0.889 4 0.653 4
|
||||
MAin[7] PHI2 F 10.678 4 -1.070 M
|
||||
MAin[7] nCRAS F 1.186 4 0.309 4
|
||||
MAin[8] nCRAS F 1.639 4 0.014 M
|
||||
MAin[9] nCRAS F 1.097 4 0.457 4
|
||||
PHI2 RCLK R -0.133 M 2.360 4
|
||||
nCCAS RCLK R 2.943 4 -0.337 M
|
||||
nCCAS nCRAS F 2.967 4 -0.214 M
|
||||
nCRAS RCLK R 3.047 4 -0.402 M
|
||||
nFWE PHI2 F 11.116 4 -1.189 M
|
||||
nFWE nCRAS F 1.394 4 0.225 4
|
||||
|
||||
|
||||
// Clock to Output Delay
|
||||
|
||||
Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
|
||||
------------------------------------------------------------------------
|
||||
LED RCLK R 11.046 4 3.298 M
|
||||
LED nCRAS F 11.710 4 3.359 M
|
||||
RA[0] RCLK R 11.397 4 3.516 M
|
||||
RA[0] nCRAS F 11.476 4 3.432 M
|
||||
RA[10] RCLK R 7.888 4 2.711 M
|
||||
RA[11] PHI2 R 9.755 4 3.200 M
|
||||
RA[1] RCLK R 11.272 4 3.469 M
|
||||
RA[1] nCRAS F 11.238 4 3.348 M
|
||||
RA[2] RCLK R 11.235 4 3.468 M
|
||||
RA[2] nCRAS F 11.665 4 3.453 M
|
||||
RA[3] RCLK R 11.390 4 3.512 M
|
||||
RA[3] nCRAS F 11.922 4 3.539 M
|
||||
RA[4] RCLK R 11.662 4 3.573 M
|
||||
RA[4] nCRAS F 11.818 4 3.505 M
|
||||
RA[5] RCLK R 11.744 4 3.584 M
|
||||
RA[5] nCRAS F 11.779 4 3.513 M
|
||||
RA[6] RCLK R 11.738 4 3.607 M
|
||||
RA[6] nCRAS F 11.836 4 3.531 M
|
||||
RA[7] RCLK R 12.475 4 3.797 M
|
||||
RA[7] nCRAS F 11.420 4 3.426 M
|
||||
RA[8] RCLK R 11.122 4 3.431 M
|
||||
RA[8] nCRAS F 11.667 4 3.471 M
|
||||
RA[9] RCLK R 11.935 4 3.649 M
|
||||
RA[9] nCRAS F 11.401 4 3.424 M
|
||||
RBA[0] nCRAS F 8.903 4 2.891 M
|
||||
RBA[1] nCRAS F 8.903 4 2.891 M
|
||||
RCKE RCLK R 10.011 4 3.215 M
|
||||
RDQMH RCLK R 10.790 4 3.354 M
|
||||
RDQML RCLK R 11.053 4 3.450 M
|
||||
RD[0] nCCAS F 8.977 4 3.012 M
|
||||
RD[1] nCCAS F 8.977 4 3.012 M
|
||||
RD[2] nCCAS F 8.977 4 3.012 M
|
||||
RD[3] nCCAS F 8.977 4 3.012 M
|
||||
RD[4] nCCAS F 8.977 4 3.012 M
|
||||
RD[5] nCCAS F 8.977 4 3.012 M
|
||||
RD[6] nCCAS F 8.977 4 3.012 M
|
||||
RD[7] nCCAS F 8.977 4 3.012 M
|
||||
nRCAS RCLK R 7.822 4 2.706 M
|
||||
nRCS RCLK R 7.822 4 2.706 M
|
||||
nRRAS RCLK R 7.822 4 2.706 M
|
||||
nRWE RCLK R 7.803 4 2.713 M
|
||||
WARNING: you must also run trce with hold speed: 4
|
||||
WARNING: you must also run trce with setup speed: M
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<BR>
|
||||
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|
||||
<BR>
|
||||
<BR>
|
||||
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|
||||
<BR>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
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|
||||
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|
||||
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|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,485 @@
|
|||
<HTML>
|
||||
<HEAD><TITLE>Project Summary</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Mrp"></A>
|
||||
Lattice Mapping Report File for Design Module 'RAM2GS'
|
||||
|
||||
|
||||
|
||||
<A name="mrp_di"></A><B><U><big>Design Information</big></U></B>
|
||||
|
||||
Command line: map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 4 -oc Commercial
|
||||
RAM2GS_LCMXO2_1200HC_impl1.ngd -o RAM2GS_LCMXO2_1200HC_impl1_map.ncd -pr
|
||||
RAM2GS_LCMXO2_1200HC_impl1.prf -mp RAM2GS_LCMXO2_1200HC_impl1.mrp -lpf //Ma
|
||||
c/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/impl1/RAM2GS_LCMXO2_1200HC_impl1_s
|
||||
ynplify.lpf -lpf //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.lpf -c 0 -gui
|
||||
-msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml
|
||||
Target Vendor: LATTICE
|
||||
Target Device: LCMXO2-1200HCTQFP100
|
||||
Target Performance: 4
|
||||
Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454
|
||||
Mapped on: 09/21/23 05:39:45
|
||||
|
||||
|
||||
<A name="mrp_ds"></A><B><U><big>Design Summary</big></U></B>
|
||||
Number of registers: 109 out of 1520 (7%)
|
||||
PFU registers: 84 out of 1280 (7%)
|
||||
PIO registers: 25 out of 240 (10%)
|
||||
Number of SLICEs: 120 out of 640 (19%)
|
||||
SLICEs as Logic/ROM: 120 out of 640 (19%)
|
||||
SLICEs as RAM: 0 out of 480 (0%)
|
||||
SLICEs as Carry: 10 out of 640 (2%)
|
||||
Number of LUT4s: 237 out of 1280 (19%)
|
||||
Number used as logic LUTs: 217
|
||||
Number used as distributed RAM: 0
|
||||
Number used as ripple logic: 20
|
||||
Number used as shift registers: 0
|
||||
Number of PIO sites used: 63 + 4(JTAG) out of 80 (84%)
|
||||
Number of block RAMs: 0 out of 7 (0%)
|
||||
Number of GSRs: 0 out of 1 (0%)
|
||||
EFB used : Yes
|
||||
JTAG used : No
|
||||
Readback used : No
|
||||
Oscillator used : No
|
||||
Startup used : No
|
||||
POR : On
|
||||
Bandgap : On
|
||||
Number of Power Controller: 0 out of 1 (0%)
|
||||
Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
|
||||
Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%)
|
||||
Number of DCCA: 0 out of 8 (0%)
|
||||
Number of DCMA: 0 out of 2 (0%)
|
||||
Number of PLLs: 0 out of 1 (0%)
|
||||
Number of DQSDLLs: 0 out of 2 (0%)
|
||||
Number of CLKDIVC: 0 out of 4 (0%)
|
||||
Number of ECLKSYNCA: 0 out of 4 (0%)
|
||||
Number of ECLKBRIDGECS: 0 out of 2 (0%)
|
||||
Notes:-
|
||||
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
|
||||
distributed RAMs) + 2*(Number of ripple logic)
|
||||
2. Number of logic LUT4s does not include count of distributed RAM and
|
||||
ripple logic.
|
||||
Number of clocks: 4
|
||||
Net PHI2_c: 20 loads, 9 rising, 11 falling (Driver: PIO PHI2 )
|
||||
Net RCLK_c: 47 loads, 47 rising, 0 falling (Driver: PIO RCLK )
|
||||
|
||||
Net nCRAS_c: 9 loads, 0 rising, 9 falling (Driver: PIO nCRAS )
|
||||
Net nCCAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCCAS )
|
||||
Number of Clock Enables: 5
|
||||
Net N_178: 1 loads, 1 LSLICEs
|
||||
Net XOR8MEG18: 5 loads, 5 LSLICEs
|
||||
Net N_360_i: 2 loads, 2 LSLICEs
|
||||
Net un1_wb_rst14_i_0: 9 loads, 9 LSLICEs
|
||||
Net CmdUFMData_1_sqmuxa: 1 loads, 1 LSLICEs
|
||||
Number of LSRs: 5
|
||||
Net RA10s_i: 1 loads, 0 LSLICEs
|
||||
Net wb_rst10: 3 loads, 3 LSLICEs
|
||||
Net wb_rst: 1 loads, 0 LSLICEs
|
||||
Net nRRAS_0_sqmuxa: 1 loads, 1 LSLICEs
|
||||
Net RASr2: 2 loads, 2 LSLICEs
|
||||
Number of nets driven by tri-state buffers: 0
|
||||
Top 10 highest fanout non-clock nets:
|
||||
Net InitReady: 41 loads
|
||||
Net FS[11]: 23 loads
|
||||
Net FS[13]: 22 loads
|
||||
Net FS[10]: 21 loads
|
||||
Net FS[12]: 21 loads
|
||||
Net FS[9]: 20 loads
|
||||
Net FS[14]: 18 loads
|
||||
Net CO0: 15 loads
|
||||
Net Ready_fast: 14 loads
|
||||
Net N_214: 13 loads
|
||||
|
||||
|
||||
|
||||
|
||||
Number of warnings: 1
|
||||
Number of errors: 0
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<A name="mrp_dwe"></A><B><U><big>Design Errors/Warnings</big></U></B>
|
||||
|
||||
WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
||||
temporarily disable certain features of the device including Power
|
||||
Controller, GSR, Hardened User SPI Port, Hardened Primary User I2C Port.
|
||||
Functionality is restored after the Flash Memory (UFM/Configuration)
|
||||
Interface is disabled using Disable Configuration Interface command 0x26
|
||||
followed by Bypass command 0xFF.
|
||||
|
||||
|
||||
|
||||
<A name="mrp_ioa"></A><B><U><big>IO (PIO) Attributes</big></U></B>
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| IO Name | Direction | Levelmode | IO |
|
||||
| | | IO_TYPE | Register |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[0] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[0] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| PHI2 | INPUT | LVCMOS33 | IN |
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RDQML | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RDQMH | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRCAS | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRRAS | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRWE | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RCKE | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RCLK | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRCS | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[7] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[6] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[5] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[4] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[3] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[2] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[1] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[11] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[10] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[9] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[8] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[7] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[6] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[5] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[4] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[3] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[2] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[1] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[0] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RBA[1] | OUTPUT | LVCMOS33 | OUT |
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RBA[0] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| LED | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nFWE | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nCRAS | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nCCAS | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[7] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[6] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[5] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[4] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[3] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[2] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Dout[1] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[7] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[6] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[5] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[4] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[3] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[2] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[1] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| Din[0] | INPUT | LVCMOS33 | IN |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| CROW[1] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| CROW[0] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[9] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[8] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[7] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[6] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[5] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[4] | INPUT | LVCMOS33 | |
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[3] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[2] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[1] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[0] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
||||
|
||||
|
||||
<A name="mrp_rm"></A><B><U><big>Removed logic</big></U></B>
|
||||
|
||||
Block GSR_INST undriven or does not drive anything - clipped.
|
||||
Signal nCRAS_c_i was merged into signal nCRAS_c
|
||||
Signal RASr2_i was merged into signal RASr2
|
||||
Signal XOR8MEG.CN was merged into signal PHI2_c
|
||||
Signal GND undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/VCC undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/GND undriven or does not drive anything - clipped.
|
||||
Signal FS_s_0_S1[17] undriven or does not drive anything - clipped.
|
||||
Signal FS_s_0_COUT[17] undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/CFGWAKE undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wbc_ufm_irq undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/TCOC undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/TCINT undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIIRQO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPICSNEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMOSIEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMOSIO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMISOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPIMISOO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPISCKEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/SPISCKO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SDAOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SCLOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SDAOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SCLOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
|
||||
|
||||
Signal ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO4 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLWEO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLL1STBO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLL0STBO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLRSTO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLCLKO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wb_dat_o_1[2] undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wb_dat_o_1[3] undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wb_dat_o_1[4] undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wb_dat_o_1[5] undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wb_dat_o_1[6] undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/wb_dat_o_1[7] undriven or does not drive anything - clipped.
|
||||
Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped.
|
||||
Signal N_1 undriven or does not drive anything - clipped.
|
||||
Block nCRAS_pad_RNIBPVB was optimized away.
|
||||
Block RASr2_RNIAFR1 was optimized away.
|
||||
Block XOR8MEG.CN was optimized away.
|
||||
Block GND was optimized away.
|
||||
Block ufmefb/VCC was optimized away.
|
||||
Block ufmefb/GND was optimized away.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<A name="mrp_efb"></A><B><U><big>Embedded Functional Block Connection Summary</big></U></B>
|
||||
|
||||
Desired WISHBONE clock frequency: 66.7 MHz
|
||||
Clock source: RCLK_c
|
||||
Reset source: wb_rst
|
||||
Functions mode:
|
||||
I2C #1 (Primary) Function: DISABLED
|
||||
I2C #2 (Secondary) Function: DISABLED
|
||||
SPI Function: DISABLED
|
||||
Timer/Counter Function: DISABLED
|
||||
Timer/Counter Mode: WB
|
||||
UFM Connection: ENABLED
|
||||
PLL0 Connection: DISABLED
|
||||
PLL1 Connection: DISABLED
|
||||
I2C Function Summary:
|
||||
--------------------
|
||||
None
|
||||
SPI Function Summary:
|
||||
--------------------
|
||||
None
|
||||
Timer/Counter Function Summary:
|
||||
------------------------------
|
||||
None
|
||||
|
||||
UFM Function Summary:
|
||||
--------------------
|
||||
UFM Utilization: General Purpose Flash Memory
|
||||
Initialized UFM Pages: 321 Pages (321*128 Bits)
|
||||
Available General
|
||||
Purpose Flash Memory: 511 Pages (511*128 Bits)
|
||||
|
||||
EBR Blocks with Unique
|
||||
Initialization Data: 0
|
||||
|
||||
WID EBR Instance
|
||||
--- ------------
|
||||
|
||||
|
||||
|
||||
|
||||
<A name="mrp_asic"></A><B><U><big>ASIC Components</big></U></B>
|
||||
---------------
|
||||
|
||||
Instance Name: ufmefb/EFBInst_0
|
||||
Type: EFB
|
||||
|
||||
|
||||
|
||||
<A name="mrp_runtime"></A><B><U><big>Run Time and Memory Usage</big></U></B>
|
||||
-------------------------
|
||||
|
||||
Total CPU Time: 0 secs
|
||||
Total REAL Time: 0 secs
|
||||
Peak Memory Usage: 63 MB
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights
|
||||
reserved.
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
|
|
@ -0,0 +1,366 @@
|
|||
<HTML>
|
||||
<HEAD><TITLE>PAD Specification File</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Pad"></A>PAD Specification File
|
||||
***************************
|
||||
|
||||
PART TYPE: LCMXO2-1200HC
|
||||
Performance Grade: 4
|
||||
PACKAGE: TQFP100
|
||||
Package Status: Final Version 1.44
|
||||
|
||||
Thu Sep 21 05:39:56 2023
|
||||
|
||||
Pinout by Port Name:
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties |
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
| CROW[0] | 10/3 | LVCMOS33_IN | PL4B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| CROW[1] | 16/3 | LVCMOS33_IN | PL8A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[0] | 3/3 | LVCMOS33_IN | PL3A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[1] | 96/0 | LVCMOS33_IN | PT10B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[2] | 88/0 | LVCMOS33_IN | PT12A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[3] | 97/0 | LVCMOS33_IN | PT10A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[4] | 99/0 | LVCMOS33_IN | PT9A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[5] | 98/0 | LVCMOS33_IN | PT9B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[6] | 2/3 | LVCMOS33_IN | PL2D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[7] | 1/3 | LVCMOS33_IN | PL2C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Dout[0] | 76/0 | LVCMOS33_OUT | PT17D | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[1] | 86/0 | LVCMOS33_OUT | PT12C | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[2] | 87/0 | LVCMOS33_OUT | PT12B | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[3] | 85/0 | LVCMOS33_OUT | PT12D | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[4] | 83/0 | LVCMOS33_OUT | PT15B | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[5] | 84/0 | LVCMOS33_OUT | PT15A | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[6] | 78/0 | LVCMOS33_OUT | PT16C | | | DRIVE:4mA SLEW:FAST |
|
||||
| Dout[7] | 82/0 | LVCMOS33_OUT | PT15C | | | DRIVE:4mA SLEW:FAST |
|
||||
| LED | 34/2 | LVCMOS33_OUT | PB9A | | | DRIVE:24mA SLEW:SLOW |
|
||||
| MAin[0] | 14/3 | LVCMOS33_IN | PL5C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[1] | 12/3 | LVCMOS33_IN | PL5A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[2] | 13/3 | LVCMOS33_IN | PL5B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[3] | 21/3 | LVCMOS33_IN | PL9B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[4] | 20/3 | LVCMOS33_IN | PL9A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[5] | 19/3 | LVCMOS33_IN | PL8D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[6] | 24/3 | LVCMOS33_IN | PL10C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[7] | 18/3 | LVCMOS33_IN | PL8C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[8] | 25/3 | LVCMOS33_IN | PL10D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[9] | 32/2 | LVCMOS33_IN | PB6D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| PHI2 | 8/3 | LVCMOS33_IN | PL3D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| RA[0] | 66/1 | LVCMOS33_OUT | PR4D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[10] | 64/1 | LVCMOS33_OUT | PR5B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[11] | 59/1 | LVCMOS33_OUT | PR8D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[1] | 67/1 | LVCMOS33_OUT | PR4C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[2] | 69/1 | LVCMOS33_OUT | PR4A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[3] | 71/1 | LVCMOS33_OUT | PR3A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[4] | 74/1 | LVCMOS33_OUT | PR2B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[5] | 70/1 | LVCMOS33_OUT | PR3B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[6] | 68/1 | LVCMOS33_OUT | PR4B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[7] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[9] | 62/1 | LVCMOS33_OUT | PR5D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RBA[0] | 58/1 | LVCMOS33_OUT | PR9A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RBA[1] | 60/1 | LVCMOS33_OUT | PR8C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RCKE | 53/1 | LVCMOS33_OUT | PR9D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RCLK | 63/1 | LVCMOS33_IN | PR5C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| RDQMH | 51/1 | LVCMOS33_OUT | PR10D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RDQML | 48/2 | LVCMOS33_OUT | PB20C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RD[0] | 36/2 | LVCMOS33_BIDI | PB11C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[1] | 37/2 | LVCMOS33_BIDI | PB11D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[2] | 38/2 | LVCMOS33_BIDI | PB11A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[3] | 39/2 | LVCMOS33_BIDI | PB11B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[4] | 40/2 | LVCMOS33_BIDI | PB15A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[5] | 41/2 | LVCMOS33_BIDI | PB15B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[6] | 42/2 | LVCMOS33_BIDI | PB18A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[7] | 43/2 | LVCMOS33_BIDI | PB18B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| nCCAS | 9/3 | LVCMOS33_IN | PL4A | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nCRAS | 17/3 | LVCMOS33_IN | PL8B | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nFWE | 15/3 | LVCMOS33_IN | PL5D | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nRCAS | 52/1 | LVCMOS33_OUT | PR10C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nRCS | 57/1 | LVCMOS33_OUT | PR9B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nRRAS | 54/1 | LVCMOS33_OUT | PR9C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| nRWE | 49/2 | LVCMOS33_OUT | PB20D | | | DRIVE:4mA SLEW:SLOW |
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
|
||||
Vccio by Bank:
|
||||
+------+-------+
|
||||
| Bank | Vccio |
|
||||
+------+-------+
|
||||
| 0 | 3.3V |
|
||||
| 1 | 3.3V |
|
||||
| 2 | 3.3V |
|
||||
| 3 | 3.3V |
|
||||
+------+-------+
|
||||
|
||||
|
||||
<A name="pad_vref"></A><B><U><big>Vref by Bank:</big></U></B>
|
||||
+------+-----+-----------------+---------+
|
||||
| Vref | Pin | Bank # / Vref # | Load(s) |
|
||||
+------+-----+-----------------+---------+
|
||||
+------+-----+-----------------+---------+
|
||||
|
||||
<A name="pad_pin"></A><B><U><big>Pinout by Pin Number:</big></U></B>
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable |
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
| 1/3 | Din[7] | LOCATED | LVCMOS33_IN | PL2C | L_GPLLT_IN | | |
|
||||
| 2/3 | Din[6] | LOCATED | LVCMOS33_IN | PL2D | L_GPLLC_IN | | |
|
||||
| 3/3 | Din[0] | LOCATED | LVCMOS33_IN | PL3A | PCLKT3_2 | | |
|
||||
| 4/3 | unused, PULL:DOWN | | | PL3B | PCLKC3_2 | | |
|
||||
| 7/3 | unused, PULL:DOWN | | | PL3C | | | |
|
||||
| 8/3 | PHI2 | LOCATED | LVCMOS33_IN | PL3D | | | |
|
||||
| 9/3 | nCCAS | LOCATED | LVCMOS33_IN | PL4A | | | |
|
||||
| 10/3 | CROW[0] | LOCATED | LVCMOS33_IN | PL4B | | | |
|
||||
| 12/3 | MAin[1] | LOCATED | LVCMOS33_IN | PL5A | PCLKT3_1 | | |
|
||||
| 13/3 | MAin[2] | LOCATED | LVCMOS33_IN | PL5B | PCLKC3_1 | | |
|
||||
| 14/3 | MAin[0] | LOCATED | LVCMOS33_IN | PL5C | | | |
|
||||
| 15/3 | nFWE | LOCATED | LVCMOS33_IN | PL5D | | | |
|
||||
| 16/3 | CROW[1] | LOCATED | LVCMOS33_IN | PL8A | | | |
|
||||
| 17/3 | nCRAS | LOCATED | LVCMOS33_IN | PL8B | | | |
|
||||
| 18/3 | MAin[7] | LOCATED | LVCMOS33_IN | PL8C | | | |
|
||||
| 19/3 | MAin[5] | LOCATED | LVCMOS33_IN | PL8D | | | |
|
||||
| 20/3 | MAin[4] | LOCATED | LVCMOS33_IN | PL9A | PCLKT3_0 | | |
|
||||
| 21/3 | MAin[3] | LOCATED | LVCMOS33_IN | PL9B | PCLKC3_0 | | |
|
||||
| 24/3 | MAin[6] | LOCATED | LVCMOS33_IN | PL10C | | | |
|
||||
| 25/3 | MAin[8] | LOCATED | LVCMOS33_IN | PL10D | | | |
|
||||
| 27/2 | unused, PULL:DOWN | | | PB4C | CSSPIN | | |
|
||||
| 28/2 | unused, PULL:DOWN | | | PB4D | | | |
|
||||
| 29/2 | unused, PULL:DOWN | | | PB6A | | | |
|
||||
| 30/2 | unused, PULL:DOWN | | | PB6B | | | |
|
||||
| 31/2 | unused, PULL:DOWN | | | PB6C | MCLK/CCLK | | |
|
||||
| 32/2 | MAin[9] | LOCATED | LVCMOS33_IN | PB6D | SO/SPISO | | |
|
||||
| 34/2 | LED | LOCATED | LVCMOS33_OUT | PB9A | PCLKT2_0 | | |
|
||||
| 35/2 | unused, PULL:DOWN | | | PB9B | PCLKC2_0 | | |
|
||||
| 36/2 | RD[0] | LOCATED | LVCMOS33_BIDI | PB11C | | | |
|
||||
| 37/2 | RD[1] | LOCATED | LVCMOS33_BIDI | PB11D | | | |
|
||||
| 38/2 | RD[2] | LOCATED | LVCMOS33_BIDI | PB11A | PCLKT2_1 | | |
|
||||
| 39/2 | RD[3] | LOCATED | LVCMOS33_BIDI | PB11B | PCLKC2_1 | | |
|
||||
| 40/2 | RD[4] | LOCATED | LVCMOS33_BIDI | PB15A | | | |
|
||||
| 41/2 | RD[5] | LOCATED | LVCMOS33_BIDI | PB15B | | | |
|
||||
| 42/2 | RD[6] | LOCATED | LVCMOS33_BIDI | PB18A | | | |
|
||||
| 43/2 | RD[7] | LOCATED | LVCMOS33_BIDI | PB18B | | | |
|
||||
| 45/2 | unused, PULL:DOWN | | | PB18C | | | |
|
||||
| 47/2 | unused, PULL:DOWN | | | PB18D | | | |
|
||||
| 48/2 | RDQML | LOCATED | LVCMOS33_OUT | PB20C | SN | | |
|
||||
| 49/2 | nRWE | LOCATED | LVCMOS33_OUT | PB20D | SI/SISPI | | |
|
||||
| 51/1 | RDQMH | LOCATED | LVCMOS33_OUT | PR10D | DQ1 | | |
|
||||
| 52/1 | nRCAS | LOCATED | LVCMOS33_OUT | PR10C | DQ1 | | |
|
||||
| 53/1 | RCKE | LOCATED | LVCMOS33_OUT | PR9D | DQ1 | | |
|
||||
| 54/1 | nRRAS | LOCATED | LVCMOS33_OUT | PR9C | DQ1 | | |
|
||||
| 57/1 | nRCS | LOCATED | LVCMOS33_OUT | PR9B | DQ1 | | |
|
||||
| 58/1 | RBA[0] | LOCATED | LVCMOS33_OUT | PR9A | DQ1 | | |
|
||||
| 59/1 | RA[11] | LOCATED | LVCMOS33_OUT | PR8D | DQ1 | | |
|
||||
| 60/1 | RBA[1] | LOCATED | LVCMOS33_OUT | PR8C | DQ1 | | |
|
||||
| 61/1 | unused, PULL:DOWN | | | PR8A | DQS1 | | |
|
||||
| 62/1 | RA[9] | LOCATED | LVCMOS33_OUT | PR5D | PCLKC1_0/DQ0 | | |
|
||||
| 63/1 | RCLK | LOCATED | LVCMOS33_IN | PR5C | PCLKT1_0/DQ0 | | |
|
||||
| 64/1 | RA[10] | LOCATED | LVCMOS33_OUT | PR5B | DQS0N | | |
|
||||
| 65/1 | RA[8] | LOCATED | LVCMOS33_OUT | PR5A | DQS0 | | |
|
||||
| 66/1 | RA[0] | LOCATED | LVCMOS33_OUT | PR4D | DQ0 | | |
|
||||
| 67/1 | RA[1] | LOCATED | LVCMOS33_OUT | PR4C | DQ0 | | |
|
||||
| 68/1 | RA[6] | LOCATED | LVCMOS33_OUT | PR4B | DQ0 | | |
|
||||
| 69/1 | RA[2] | LOCATED | LVCMOS33_OUT | PR4A | DQ0 | | |
|
||||
| 70/1 | RA[5] | LOCATED | LVCMOS33_OUT | PR3B | DQ0 | | |
|
||||
| 71/1 | RA[3] | LOCATED | LVCMOS33_OUT | PR3A | DQ0 | | |
|
||||
| 74/1 | RA[4] | LOCATED | LVCMOS33_OUT | PR2B | DQ0 | | |
|
||||
| 75/1 | RA[7] | LOCATED | LVCMOS33_OUT | PR2A | DQ0 | | |
|
||||
| 76/0 | Dout[0] | LOCATED | LVCMOS33_OUT | PT17D | DONE | | |
|
||||
| 77/0 | unused, PULL:DOWN | | | PT17C | INITN | | |
|
||||
| 78/0 | Dout[6] | LOCATED | LVCMOS33_OUT | PT16C | | | |
|
||||
| 81/0 | unused, PULL:DOWN | | | PT15D | PROGRAMN | | |
|
||||
| 82/0 | Dout[7] | LOCATED | LVCMOS33_OUT | PT15C | JTAGENB | | |
|
||||
| 83/0 | Dout[4] | LOCATED | LVCMOS33_OUT | PT15B | | | |
|
||||
| 84/0 | Dout[5] | LOCATED | LVCMOS33_OUT | PT15A | | | |
|
||||
| 85/0 | Dout[3] | LOCATED | LVCMOS33_OUT | PT12D | SDA/PCLKC0_0 | | |
|
||||
| 86/0 | Dout[1] | LOCATED | LVCMOS33_OUT | PT12C | SCL/PCLKT0_0 | | |
|
||||
| 87/0 | Dout[2] | LOCATED | LVCMOS33_OUT | PT12B | PCLKC0_1 | | |
|
||||
| 88/0 | Din[2] | LOCATED | LVCMOS33_IN | PT12A | PCLKT0_1 | | |
|
||||
| 90/0 | Reserved: sysCONFIG | | | PT11D | TMS | | |
|
||||
| 91/0 | Reserved: sysCONFIG | | | PT11C | TCK | | |
|
||||
| 94/0 | Reserved: sysCONFIG | | | PT10D | TDI | | |
|
||||
| 95/0 | Reserved: sysCONFIG | | | PT10C | TDO | | |
|
||||
| 96/0 | Din[1] | LOCATED | LVCMOS33_IN | PT10B | | | |
|
||||
| 97/0 | Din[3] | LOCATED | LVCMOS33_IN | PT10A | | | |
|
||||
| 98/0 | Din[5] | LOCATED | LVCMOS33_IN | PT9B | | | |
|
||||
| 99/0 | Din[4] | LOCATED | LVCMOS33_IN | PT9A | | | |
|
||||
| PB4A/2 | unused, PULL:DOWN | | | PB4A | | | |
|
||||
| PB4B/2 | unused, PULL:DOWN | | | PB4B | | | |
|
||||
| PB9C/2 | unused, PULL:DOWN | | | PB9C | | | |
|
||||
| PB9D/2 | unused, PULL:DOWN | | | PB9D | | | |
|
||||
| PB15C/2 | unused, PULL:DOWN | | | PB15C | | | |
|
||||
| PB15D/2 | unused, PULL:DOWN | | | PB15D | | | |
|
||||
| PB20A/2 | unused, PULL:DOWN | | | PB20A | | | |
|
||||
| PB20B/2 | unused, PULL:DOWN | | | PB20B | | | |
|
||||
| PL2A/3 | unused, PULL:DOWN | | | PL2A | L_GPLLT_FB | | |
|
||||
| PL2B/3 | unused, PULL:DOWN | | | PL2B | L_GPLLC_FB | | |
|
||||
| PL4C/3 | unused, PULL:DOWN | | | PL4C | | | |
|
||||
| PL4D/3 | unused, PULL:DOWN | | | PL4D | | | |
|
||||
| PL10A/3 | unused, PULL:DOWN | | | PL10A | | | |
|
||||
| PL10B/3 | unused, PULL:DOWN | | | PL10B | | | |
|
||||
| PR2C/1 | unused, PULL:DOWN | | | PR2C | DQ0 | | |
|
||||
| PR2D/1 | unused, PULL:DOWN | | | PR2D | DQ0 | | |
|
||||
| PR8B/1 | unused, PULL:DOWN | | | PR8B | DQS1N | | |
|
||||
| PR10A/1 | unused, PULL:DOWN | | | PR10A | DQ1 | | |
|
||||
| PR10B/1 | unused, PULL:DOWN | | | PR10B | DQ1 | | |
|
||||
| PT9C/0 | unused, PULL:DOWN | | | PT9C | | | |
|
||||
| PT9D/0 | unused, PULL:DOWN | | | PT9D | | | |
|
||||
| PT11A/0 | unused, PULL:DOWN | | | PT11A | | | |
|
||||
| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | |
|
||||
| PT16A/0 | unused, PULL:DOWN | | | PT16A | | | |
|
||||
| PT16B/0 | unused, PULL:DOWN | | | PT16B | | | |
|
||||
| PT16D/0 | unused, PULL:DOWN | | | PT16D | | | |
|
||||
| PT17A/0 | unused, PULL:DOWN | | | PT17A | | | |
|
||||
| PT17B/0 | unused, PULL:DOWN | | | PT17B | | | |
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
|
||||
sysCONFIG Pins:
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode |
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
| PT11D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP |
|
||||
| PT11C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down |
|
||||
| PT10D | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP |
|
||||
| PT10C | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP |
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
|
||||
Dedicated sysCONFIG Pins:
|
||||
|
||||
|
||||
List of All Pins' Locate Preferences Based on Final Placement After PAR
|
||||
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste):
|
||||
|
||||
LOCATE COMP "CROW[0]" SITE "10";
|
||||
LOCATE COMP "CROW[1]" SITE "16";
|
||||
LOCATE COMP "Din[0]" SITE "3";
|
||||
LOCATE COMP "Din[1]" SITE "96";
|
||||
LOCATE COMP "Din[2]" SITE "88";
|
||||
LOCATE COMP "Din[3]" SITE "97";
|
||||
LOCATE COMP "Din[4]" SITE "99";
|
||||
LOCATE COMP "Din[5]" SITE "98";
|
||||
LOCATE COMP "Din[6]" SITE "2";
|
||||
LOCATE COMP "Din[7]" SITE "1";
|
||||
LOCATE COMP "Dout[0]" SITE "76";
|
||||
LOCATE COMP "Dout[1]" SITE "86";
|
||||
LOCATE COMP "Dout[2]" SITE "87";
|
||||
LOCATE COMP "Dout[3]" SITE "85";
|
||||
LOCATE COMP "Dout[4]" SITE "83";
|
||||
LOCATE COMP "Dout[5]" SITE "84";
|
||||
LOCATE COMP "Dout[6]" SITE "78";
|
||||
LOCATE COMP "Dout[7]" SITE "82";
|
||||
LOCATE COMP "LED" SITE "34";
|
||||
LOCATE COMP "MAin[0]" SITE "14";
|
||||
LOCATE COMP "MAin[1]" SITE "12";
|
||||
LOCATE COMP "MAin[2]" SITE "13";
|
||||
LOCATE COMP "MAin[3]" SITE "21";
|
||||
LOCATE COMP "MAin[4]" SITE "20";
|
||||
LOCATE COMP "MAin[5]" SITE "19";
|
||||
LOCATE COMP "MAin[6]" SITE "24";
|
||||
LOCATE COMP "MAin[7]" SITE "18";
|
||||
LOCATE COMP "MAin[8]" SITE "25";
|
||||
LOCATE COMP "MAin[9]" SITE "32";
|
||||
LOCATE COMP "PHI2" SITE "8";
|
||||
LOCATE COMP "RA[0]" SITE "66";
|
||||
LOCATE COMP "RA[10]" SITE "64";
|
||||
LOCATE COMP "RA[11]" SITE "59";
|
||||
LOCATE COMP "RA[1]" SITE "67";
|
||||
LOCATE COMP "RA[2]" SITE "69";
|
||||
LOCATE COMP "RA[3]" SITE "71";
|
||||
LOCATE COMP "RA[4]" SITE "74";
|
||||
LOCATE COMP "RA[5]" SITE "70";
|
||||
LOCATE COMP "RA[6]" SITE "68";
|
||||
LOCATE COMP "RA[7]" SITE "75";
|
||||
LOCATE COMP "RA[8]" SITE "65";
|
||||
LOCATE COMP "RA[9]" SITE "62";
|
||||
LOCATE COMP "RBA[0]" SITE "58";
|
||||
LOCATE COMP "RBA[1]" SITE "60";
|
||||
LOCATE COMP "RCKE" SITE "53";
|
||||
LOCATE COMP "RCLK" SITE "63";
|
||||
LOCATE COMP "RDQMH" SITE "51";
|
||||
LOCATE COMP "RDQML" SITE "48";
|
||||
LOCATE COMP "RD[0]" SITE "36";
|
||||
LOCATE COMP "RD[1]" SITE "37";
|
||||
LOCATE COMP "RD[2]" SITE "38";
|
||||
LOCATE COMP "RD[3]" SITE "39";
|
||||
LOCATE COMP "RD[4]" SITE "40";
|
||||
LOCATE COMP "RD[5]" SITE "41";
|
||||
LOCATE COMP "RD[6]" SITE "42";
|
||||
LOCATE COMP "RD[7]" SITE "43";
|
||||
LOCATE COMP "nCCAS" SITE "9";
|
||||
LOCATE COMP "nCRAS" SITE "17";
|
||||
LOCATE COMP "nFWE" SITE "15";
|
||||
LOCATE COMP "nRCAS" SITE "52";
|
||||
LOCATE COMP "nRCS" SITE "57";
|
||||
LOCATE COMP "nRRAS" SITE "54";
|
||||
LOCATE COMP "nRWE" SITE "49";
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Thu Sep 21 05:39:59 2023
|
||||
|
||||
|
||||
|
||||
|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
|
|
@ -0,0 +1,313 @@
|
|||
<HTML>
|
||||
<HEAD><TITLE>Place & Route Report</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
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P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
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}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
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border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
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.comment
{
font-size: 90%;
font-style: italic;
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|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Par"></A>PAR: Place And Route Diamond (64-bit) 3.12.1.454.
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Thu Sep 21 05:39:49 2023
|
||||
|
||||
C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_1200HC_impl1.p2t
|
||||
RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.dir
|
||||
RAM2GS_LCMXO2_1200HC_impl1.prf -gui -msgset
|
||||
//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml
|
||||
|
||||
|
||||
Preference file: RAM2GS_LCMXO2_1200HC_impl1.prf.
|
||||
|
||||
<A name="par_cts"></A><B><U><big>Cost Table Summary</big></U></B>
|
||||
Level/ Number Worst Timing Worst Timing Run NCD
|
||||
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
|
||||
---------- -------- ----- ------ ----------- ----------- ---- ------
|
||||
5_1 * 0 5.578 0 0.304 0 13 Completed
|
||||
* : Design saved.
|
||||
|
||||
Total (real) run time for 1-seed: 13 secs
|
||||
|
||||
par done!
|
||||
|
||||
Note: user must run 'Trace' for timing closure signoff.
|
||||
|
||||
Lattice Place and Route Report for Design "RAM2GS_LCMXO2_1200HC_impl1_map.ncd"
|
||||
Thu Sep 21 05:39:49 2023
|
||||
|
||||
|
||||
<A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
|
||||
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
|
||||
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
|
||||
Preference file: RAM2GS_LCMXO2_1200HC_impl1.prf.
|
||||
Placement level-cost: 5-1.
|
||||
Routing Iterations: 6
|
||||
|
||||
Loading design for application par from file RAM2GS_LCMXO2_1200HC_impl1_map.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-1200HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.44.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
License checked out.
|
||||
|
||||
|
||||
Ignore Preference Error(s): True
|
||||
|
||||
<A name="par_dus"></A><B><U><big>Device utilization summary:</big></U></B>
|
||||
|
||||
PIO (prelim) 63+4(JTAG)/108 62% used
|
||||
63+4(JTAG)/80 84% bonded
|
||||
IOLOGIC 25/108 23% used
|
||||
|
||||
SLICE 120/640 18% used
|
||||
|
||||
EFB 1/1 100% used
|
||||
|
||||
|
||||
Number of Signals: 388
|
||||
Number of Connections: 1017
|
||||
|
||||
Pin Constraint Summary:
|
||||
63 out of 63 pins locked (100% locked).
|
||||
|
||||
The following 2 signals are selected to use the primary clock routing resources:
|
||||
RCLK_c (driver: RCLK, clk load #: 47)
|
||||
PHI2_c (driver: PHI2, clk load #: 20)
|
||||
|
||||
WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
|
||||
The following 2 signals are selected to use the secondary clock routing resources:
|
||||
nCRAS_c (driver: nCRAS, clk load #: 9, sr load #: 0, ce load #: 0)
|
||||
nCCAS_c (driver: nCCAS, clk load #: 8, sr load #: 0, ce load #: 0)
|
||||
|
||||
WARNING - par: Signal "nCRAS_c" is selected to use Secondary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
WARNING - par: Signal "nCCAS_c" is selected to use Secondary clock resources. However, its driver comp "nCCAS" is located at "9", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
No signal is selected as Global Set/Reset.
|
||||
Starting Placer Phase 0.
|
||||
.........
|
||||
Finished Placer Phase 0. REAL time: 0 secs
|
||||
|
||||
Starting Placer Phase 1.
|
||||
....................
|
||||
Placer score = 68062.
|
||||
Finished Placer Phase 1. REAL time: 7 secs
|
||||
|
||||
Starting Placer Phase 2.
|
||||
.
|
||||
Placer score = 67096
|
||||
Finished Placer Phase 2. REAL time: 7 secs
|
||||
|
||||
|
||||
|
||||
<A name="par_clk"></A><B><U><big>Clock Report</big></U></B>
|
||||
|
||||
Global Clock Resources:
|
||||
CLK_PIN : 1 out of 8 (12%)
|
||||
General PIO: 3 out of 108 (2%)
|
||||
PLL : 0 out of 1 (0%)
|
||||
DCM : 0 out of 2 (0%)
|
||||
DCC : 0 out of 8 (0%)
|
||||
|
||||
Global Clocks:
|
||||
PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "63 (PR5C)", clk load = 47
|
||||
PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3D)", clk load = 20
|
||||
SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL8B)", clk load = 9, ce load = 0, sr load = 0
|
||||
SECONDARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL4A)", clk load = 8, ce load = 0, sr load = 0
|
||||
|
||||
PRIMARY : 2 out of 8 (25%)
|
||||
SECONDARY: 2 out of 8 (25%)
|
||||
|
||||
Edge Clocks:
|
||||
No edge clock selected.
|
||||
|
||||
|
||||
|
||||
|
||||
I/O Usage Summary (final):
|
||||
63 + 4(JTAG) out of 108 (62.0%) PIO sites used.
|
||||
63 + 4(JTAG) out of 80 (83.8%) bonded PIO sites used.
|
||||
Number of PIO comps: 63; differential: 0.
|
||||
Number of Vref pins used: 0.
|
||||
|
||||
I/O Bank Usage Summary:
|
||||
+----------+----------------+------------+-----------+
|
||||
| I/O Bank | Usage | Bank Vccio | Bank Vref |
|
||||
+----------+----------------+------------+-----------+
|
||||
| 0 | 13 / 19 ( 68%) | 3.3V | - |
|
||||
| 1 | 20 / 21 ( 95%) | 3.3V | - |
|
||||
| 2 | 12 / 20 ( 60%) | 3.3V | - |
|
||||
| 3 | 18 / 20 ( 90%) | 3.3V | - |
|
||||
+----------+----------------+------------+-----------+
|
||||
|
||||
Total placer CPU time: 6 secs
|
||||
|
||||
Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd.
|
||||
|
||||
0 connections routed; 1017 unrouted.
|
||||
Starting router resource preassignment
|
||||
|
||||
Completed router resource preassignment. Real time: 11 secs
|
||||
|
||||
Start NBR router at 05:40:00 09/21/23
|
||||
|
||||
*****************************************************************
|
||||
Info: NBR allows conflicts(one node used by more than one signal)
|
||||
in the earlier iterations. In each iteration, it tries to
|
||||
solve the conflicts while keeping the critical connections
|
||||
routed as short as possible. The routing process is said to
|
||||
be completed when no conflicts exist and all connections
|
||||
are routed.
|
||||
Note: NBR uses a different method to calculate timing slacks. The
|
||||
worst slack and total negative slack may not be the same as
|
||||
that in TRCE report. You should always run TRCE to verify
|
||||
your design.
|
||||
*****************************************************************
|
||||
|
||||
Start NBR special constraint process at 05:40:00 09/21/23
|
||||
|
||||
Start NBR section for initial routing at 05:40:01 09/21/23
|
||||
Level 1, iteration 1
|
||||
0(0.00%) conflict; 822(80.83%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 6.089ns/0.000ns; real time: 12 secs
|
||||
Level 2, iteration 1
|
||||
0(0.00%) conflict; 822(80.83%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 6.089ns/0.000ns; real time: 12 secs
|
||||
Level 3, iteration 1
|
||||
0(0.00%) conflict; 822(80.83%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 6.089ns/0.000ns; real time: 12 secs
|
||||
Level 4, iteration 1
|
||||
5(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 5.578ns/0.000ns; real time: 12 secs
|
||||
|
||||
Info: Initial congestion level at 75% usage is 0
|
||||
Info: Initial congestion area at 75% usage is 0 (0.00%)
|
||||
|
||||
Start NBR section for normal routing at 05:40:01 09/21/23
|
||||
Level 4, iteration 1
|
||||
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 5.578ns/0.000ns; real time: 12 secs
|
||||
Level 4, iteration 2
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 5.578ns/0.000ns; real time: 12 secs
|
||||
|
||||
Start NBR section for setup/hold timing optimization with effort level 3 at 05:40:01 09/21/23
|
||||
|
||||
Start NBR section for re-routing at 05:40:01 09/21/23
|
||||
Level 4, iteration 1
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 5.578ns/0.000ns; real time: 12 secs
|
||||
|
||||
Start NBR section for post-routing at 05:40:01 09/21/23
|
||||
|
||||
End NBR router with 0 unrouted connection
|
||||
|
||||
NBR Summary
|
||||
-----------
|
||||
Number of unrouted connections : 0 (0.00%)
|
||||
Number of connections with timing violations : 0 (0.00%)
|
||||
Estimated worst slack<setup> : 5.578ns
|
||||
Timing score<setup> : 0
|
||||
-----------
|
||||
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
|
||||
|
||||
|
||||
|
||||
Total CPU time 12 secs
|
||||
Total REAL time: 13 secs
|
||||
Completely routed.
|
||||
End of route. 1017 routed (100.00%); 0 unrouted.
|
||||
|
||||
Hold time timing score: 0, hold timing errors: 0
|
||||
|
||||
Timing score: 0
|
||||
|
||||
Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd.
|
||||
|
||||
|
||||
All signals are completely routed.
|
||||
|
||||
|
||||
PAR_SUMMARY::Run status = Completed
|
||||
PAR_SUMMARY::Number of unrouted conns = 0
|
||||
PAR_SUMMARY::Worst slack<setup/<ns>> = 5.578
|
||||
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
|
||||
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.304
|
||||
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
|
||||
PAR_SUMMARY::Number of errors = 0
|
||||
|
||||
Total CPU time to completion: 13 secs
|
||||
Total REAL time to completion: 13 secs
|
||||
|
||||
par done!
|
||||
|
||||
Note: user must run 'Trace' for timing closure signoff.
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
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|
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|
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|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
</PRE></FONT>
|
||||
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|
||||
</HTML>
|
||||
|
|
@ -13,10 +13,10 @@ Hostname: ZANEMACWIN11
|
|||
|
||||
Implementation : impl1
|
||||
|
||||
# Written on Sat Aug 19 21:54:50 2023
|
||||
# Written on Thu Sep 21 05:39:37 2023
|
||||
|
||||
##### FILES SYNTAX CHECKED ##############################################
|
||||
Constraint File(s): "Y:\Repos\RAM2GS\CPLD\RAM2GS.sdc"
|
||||
Constraint File(s): "\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS.sdc"
|
||||
|
||||
#Run constraint checker to find more issues with constraints.
|
||||
#########################################################################
|
||||
|
|
@ -0,0 +1,83 @@
|
|||
<HTML>
|
||||
<HEAD><TITLE>Project Summary</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><TABLE border=1 width=100% cellspacing=0 cellpadding=2><small>
|
||||
<TR>
|
||||
<TD align='center' BGCOLOR='#000099' COLSPAN='4'><SPAN style="COLOR: #FFFFFF"><B>RAM2GS_LCMXO2_1200HC project summary</B></SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Module Name:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">RAM2GS_LCMXO2_1200HC</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Synthesis:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">SynplifyPro</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Name:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">impl1</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Strategy Name:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">Strategy1</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Last Process:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">JEDEC File</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">State:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">Passed</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Target Device:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">LCMXO2-1200HC-4TG100C</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Device Family:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">MachXO2</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Device Type:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">LCMXO2-1200HC</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Package Type:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">TQFP100</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Performance grade:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">4</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Operating conditions:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">COM</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Logic preference file:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">RAM2GS-LCMXO2.lpf</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Physical Preference file:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">impl1/RAM2GS_LCMXO2_1200HC_impl1.prf</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Product Version:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">3.12.1.454</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Patch Version:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000"></SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Updated:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2023/09/21 05:40:22</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Location:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/impl1</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Project File:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.ldf</SPAN></TD>
|
||||
</TR>
|
||||
</small></TABLE>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,504 @@
|
|||
<HTML>
|
||||
<HEAD><TITLE>Lattice Map TRACE Report</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="Map_Twr"></A><B><U><big>Map TRACE Report</big></U></B>
|
||||
|
||||
Loading design for application trce from file ram2gs_lcmxo2_1200hc_impl1_map.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-1200HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.44.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
Setup and Hold Report
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
<A name="Map_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454</big></U></B>
|
||||
Thu Sep 21 05:39:46 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
<A name="mtw1_set_ri"></A><B><U><big>Report Information</big></U></B>
|
||||
------------------
|
||||
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_1200HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
|
||||
Design file: ram2gs_lcmxo2_1200hc_impl1_map.ncd
|
||||
Preference file: ram2gs_lcmxo2_1200hc_impl1.prf
|
||||
Device,speed: LCMXO2-1200HC,4
|
||||
Report level: verbose report, limited to 1 item per preference
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
<A name="mtw1_set_ps"></A><B><U><big>Preference Summary</big></U></B>
|
||||
|
||||
<LI><A href='#map_twr_pref_0_0' Target='right'>FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)</A></LI> 147 items scored, 0 timing errors detected.
|
||||
Report: 53.254MHz is the maximum frequency for this preference.
|
||||
|
||||
<LI><A href='#map_twr_pref_0_1' Target='right'>FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
|
||||
Report: 150.150MHz is the maximum frequency for this preference.
|
||||
|
||||
<LI><A href='#map_twr_pref_0_2' Target='right'>FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
|
||||
Report: 150.150MHz is the maximum frequency for this preference.
|
||||
|
||||
<LI><A href='#map_twr_pref_0_3' Target='right'>FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)</A></LI> 878 items scored, 0 timing errors detected.
|
||||
Report: 100.492MHz is the maximum frequency for this preference.
|
||||
|
||||
BLOCK ASYNCPATHS
|
||||
BLOCK RESETPATHS
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
================================================================================
|
||||
<A name="map_twr_pref_0_0"></A>Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
|
||||
147 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 163.025ns (weighted slack = 326.050ns)
|
||||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q Bank_0io[0] (from PHI2_c +)
|
||||
Destination: FF Data in CmdEnable (to PHI2_c -)
|
||||
|
||||
Delay: 9.223ns (33.1% logic, 66.9% route), 6 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
9.223ns physical path delay Din[0]_MGIOL to SLICE_17 meets
|
||||
172.414ns delay constraint less
|
||||
0.166ns DIN_SET requirement (totaling 172.248ns) by 163.025ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path Din[0]_MGIOL to SLICE_17:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
C2INP_DEL --- 0.577 *[0]_MGIOL.CLK to *n[0]_MGIOL.IN Din[0]_MGIOL (from PHI2_c)
|
||||
ROUTE 1 e 1.234 *n[0]_MGIOL.IN to SLICE_93.A0 Bank[0]
|
||||
CTOF_DEL --- 0.495 SLICE_93.A0 to SLICE_93.F0 SLICE_93
|
||||
ROUTE 1 e 1.234 SLICE_93.F0 to SLICE_84.C0 un1_CmdEnable20_0_0_o3_10
|
||||
CTOF_DEL --- 0.495 SLICE_84.C0 to SLICE_84.F0 SLICE_84
|
||||
ROUTE 6 e 1.234 SLICE_84.F0 to SLICE_11.C1 un1_CmdEnable20_0_0_o3
|
||||
CTOF_DEL --- 0.495 SLICE_11.C1 to SLICE_11.F1 SLICE_11
|
||||
ROUTE 3 e 1.234 SLICE_11.F1 to SLICE_33.B0 CmdEnable16
|
||||
CTOF_DEL --- 0.495 SLICE_33.B0 to SLICE_33.F0 SLICE_33
|
||||
ROUTE 1 e 1.234 SLICE_33.F0 to SLICE_17.D0 CmdEnable_0_sqmuxa
|
||||
CTOF_DEL --- 0.495 SLICE_17.D0 to SLICE_17.F0 SLICE_17
|
||||
ROUTE 1 e 0.001 SLICE_17.F0 to SLICE_17.DI0 CmdEnable_s (to PHI2_c)
|
||||
--------
|
||||
9.223 (33.1% logic, 66.9% route), 6 logic levels.
|
||||
|
||||
Report: 53.254MHz is the maximum frequency for this preference.
|
||||
|
||||
|
||||
================================================================================
|
||||
<A name="map_twr_pref_0_1"></A>Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
|
||||
0 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 338.168ns
|
||||
The internal maximum frequency of the following component is 150.150 MHz
|
||||
|
||||
Logical Details: Cell type Pin name Component name
|
||||
|
||||
Destination: PIO PAD nCCAS
|
||||
|
||||
Delay: 6.660ns -- based on Minimum Pulse Width
|
||||
|
||||
Report: 150.150MHz is the maximum frequency for this preference.
|
||||
|
||||
|
||||
================================================================================
|
||||
<A name="map_twr_pref_0_2"></A>Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
|
||||
0 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 338.168ns
|
||||
The internal maximum frequency of the following component is 150.150 MHz
|
||||
|
||||
Logical Details: Cell type Pin name Component name
|
||||
|
||||
Destination: PIO PAD nCRAS
|
||||
|
||||
Delay: 6.660ns -- based on Minimum Pulse Width
|
||||
|
||||
Report: 150.150MHz is the maximum frequency for this preference.
|
||||
|
||||
|
||||
================================================================================
|
||||
<A name="map_twr_pref_0_3"></A>Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
|
||||
878 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 6.049ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q IS[1] (from RCLK_c +)
|
||||
Destination: FF Data in nRCAS_0io (to RCLK_c +)
|
||||
|
||||
Delay: 9.798ns (34.9% logic, 65.1% route), 7 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
9.798ns physical path delay SLICE_27 to nRCAS_MGIOL meets
|
||||
16.000ns delay constraint less
|
||||
0.153ns DO_SET requirement (totaling 15.847ns) by 6.049ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path SLICE_27 to nRCAS_MGIOL:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.452 SLICE_27.CLK to SLICE_27.Q0 SLICE_27 (from RCLK_c)
|
||||
ROUTE 7 e 1.234 SLICE_27.Q0 to SLICE_74.A1 IS[1]
|
||||
CTOF_DEL --- 0.495 SLICE_74.A1 to SLICE_74.F1 SLICE_74
|
||||
ROUTE 2 e 0.480 SLICE_74.F1 to SLICE_74.B0 un1_nRCAS_6_sqmuxa_i_0_0_o2_0
|
||||
CTOF_DEL --- 0.495 SLICE_74.B0 to SLICE_74.F0 SLICE_74
|
||||
ROUTE 2 e 1.234 SLICE_74.F0 to SLICE_61.B1 N_408
|
||||
CTOF_DEL --- 0.495 SLICE_61.B1 to SLICE_61.F1 SLICE_61
|
||||
ROUTE 1 e 0.480 SLICE_61.F1 to SLICE_61.A0 un1_nRCAS_6_sqmuxa_i_0_0
|
||||
CTOF_DEL --- 0.495 SLICE_61.A0 to SLICE_61.F0 SLICE_61
|
||||
ROUTE 1 e 1.234 SLICE_61.F0 to SLICE_94.D0 nRCAS_r_i_0_o2_0_0
|
||||
CTOF_DEL --- 0.495 SLICE_94.D0 to SLICE_94.F0 SLICE_94
|
||||
ROUTE 1 e 0.480 SLICE_94.F0 to SLICE_94.A1 N_248_i_1
|
||||
CTOF_DEL --- 0.495 SLICE_94.A1 to SLICE_94.F1 SLICE_94
|
||||
ROUTE 1 e 1.234 SLICE_94.F1 to *AS_MGIOL.OPOS N_248_i (to RCLK_c)
|
||||
--------
|
||||
9.798 (34.9% logic, 65.1% route), 7 logic levels.
|
||||
|
||||
Report: 100.492MHz is the maximum frequency for this preference.
|
||||
|
||||
<A name="mtw1_set_rs"></A><B><U><big>Report Summary</big></U></B>
|
||||
--------------
|
||||
----------------------------------------------------------------------------
|
||||
Preference | Constraint| Actual|Levels
|
||||
----------------------------------------------------------------------------
|
||||
| | |
|
||||
FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 53.254 MHz| 6
|
||||
| | |
|
||||
FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
|
||||
| | |
|
||||
FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
|
||||
| | |
|
||||
FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 100.492 MHz| 7
|
||||
| | |
|
||||
----------------------------------------------------------------------------
|
||||
|
||||
|
||||
All preferences were met.
|
||||
|
||||
|
||||
<A name="mtw1_set_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
|
||||
------------------------
|
||||
|
||||
Found 4 clocks:
|
||||
|
||||
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11
|
||||
No transfer within this clock domain is found
|
||||
|
||||
Data transfers from:
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD
|
||||
Not reported because source and destination domains are unrelated.
|
||||
To report these transfers please refer to preference CLKSKEWDIFF to define
|
||||
external clock skew between clock ports.
|
||||
|
||||
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
|
||||
No transfer within this clock domain is found
|
||||
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47
|
||||
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
|
||||
|
||||
Data transfers from:
|
||||
Clock Domain: nCRAS_c Source: nCRAS.PAD
|
||||
Not reported because source and destination domains are unrelated.
|
||||
To report these transfers please refer to preference CLKSKEWDIFF to define
|
||||
external clock skew between clock ports.
|
||||
|
||||
Clock Domain: PHI2_c Source: PHI2.PAD
|
||||
Not reported because source and destination domains are unrelated.
|
||||
To report these transfers please refer to preference CLKSKEWDIFF to define
|
||||
external clock skew between clock ports.
|
||||
|
||||
Clock Domain: PHI2_c Source: PHI2.PAD Loads: 21
|
||||
Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
|
||||
|
||||
Data transfers from:
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD
|
||||
Not reported because source and destination domains are unrelated.
|
||||
To report these transfers please refer to preference CLKSKEWDIFF to define
|
||||
external clock skew between clock ports.
|
||||
|
||||
|
||||
<A name="mtw1_set_ts"></A><B><U><big>Timing summary (Setup):</big></U></B>
|
||||
---------------
|
||||
|
||||
Timing errors: 0 Score: 0
|
||||
Cumulative negative slack: 0
|
||||
|
||||
Constraints cover 1025 paths, 4 nets, and 741 connections (72.86% coverage)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
<A name="Map_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454</big></U></B>
|
||||
Thu Sep 21 05:39:46 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
<A name="mtw1_hold_ri"></A><B><U><big>Report Information</big></U></B>
|
||||
------------------
|
||||
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO2_1200HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
|
||||
Design file: ram2gs_lcmxo2_1200hc_impl1_map.ncd
|
||||
Preference file: ram2gs_lcmxo2_1200hc_impl1.prf
|
||||
Device,speed: LCMXO2-1200HC,M
|
||||
Report level: verbose report, limited to 1 item per preference
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
<A name="mtw1_hold_ps"></A><B><U><big>Preference Summary</big></U></B>
|
||||
|
||||
<LI><A href='#map_twr_pref_1_0' Target='right'>FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)</A></LI> 147 items scored, 0 timing errors detected.
|
||||
|
||||
<LI><A href='#map_twr_pref_1_1' Target='right'>FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
|
||||
|
||||
<LI><A href='#map_twr_pref_1_2' Target='right'>FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
|
||||
|
||||
<LI><A href='#map_twr_pref_1_3' Target='right'>FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)</A></LI> 878 items scored, 0 timing errors detected.
|
||||
|
||||
BLOCK ASYNCPATHS
|
||||
BLOCK RESETPATHS
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
================================================================================
|
||||
<A name="map_twr_pref_1_0"></A>Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
|
||||
147 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 0.447ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q ADSubmitted (from PHI2_c -)
|
||||
Destination: FF Data in ADSubmitted (to PHI2_c -)
|
||||
|
||||
Delay: 0.434ns (53.9% logic, 46.1% route), 2 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
0.434ns physical path delay SLICE_10 to SLICE_10 meets
|
||||
-0.013ns DIN_HLD and
|
||||
0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path SLICE_10 to SLICE_10:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.133 SLICE_10.CLK to SLICE_10.Q0 SLICE_10 (from PHI2_c)
|
||||
ROUTE 2 e 0.199 SLICE_10.Q0 to SLICE_10.A0 ADSubmitted
|
||||
CTOF_DEL --- 0.101 SLICE_10.A0 to SLICE_10.F0 SLICE_10
|
||||
ROUTE 1 e 0.001 SLICE_10.F0 to SLICE_10.DI0 ADSubmitted_r_0_0 (to PHI2_c)
|
||||
--------
|
||||
0.434 (53.9% logic, 46.1% route), 2 logic levels.
|
||||
|
||||
|
||||
================================================================================
|
||||
<A name="map_twr_pref_1_1"></A>Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
|
||||
0 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
================================================================================
|
||||
<A name="map_twr_pref_1_2"></A>Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
|
||||
0 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
================================================================================
|
||||
<A name="map_twr_pref_1_3"></A>Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
|
||||
878 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 0.351ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q CASr (from RCLK_c +)
|
||||
Destination: FF Data in CASr2 (to RCLK_c +)
|
||||
|
||||
Delay: 0.332ns (40.1% logic, 59.9% route), 1 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
0.332ns physical path delay SLICE_12 to SLICE_12 meets
|
||||
-0.019ns M_HLD and
|
||||
0.000ns delay constraint requirement (totaling -0.019ns) by 0.351ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path SLICE_12 to SLICE_12:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.133 SLICE_12.CLK to SLICE_12.Q0 SLICE_12 (from RCLK_c)
|
||||
ROUTE 1 e 0.199 SLICE_12.Q0 to SLICE_12.M1 CASr (to RCLK_c)
|
||||
--------
|
||||
0.332 (40.1% logic, 59.9% route), 1 logic levels.
|
||||
|
||||
<A name="mtw1_hold_rs"></A><B><U><big>Report Summary</big></U></B>
|
||||
--------------
|
||||
----------------------------------------------------------------------------
|
||||
Preference(MIN Delays) | Constraint| Actual|Levels
|
||||
----------------------------------------------------------------------------
|
||||
| | |
|
||||
FREQUENCY PORT "PHI2" 2.900000 MHz ; | -| -| 2
|
||||
| | |
|
||||
FREQUENCY PORT "nCCAS" 2.900000 MHz ; | -| -| 0
|
||||
| | |
|
||||
FREQUENCY PORT "nCRAS" 2.900000 MHz ; | -| -| 0
|
||||
| | |
|
||||
FREQUENCY PORT "RCLK" 62.500000 MHz ; | -| -| 1
|
||||
| | |
|
||||
----------------------------------------------------------------------------
|
||||
|
||||
|
||||
All preferences were met.
|
||||
|
||||
|
||||
<A name="mtw1_hold_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
|
||||
------------------------
|
||||
|
||||
Found 4 clocks:
|
||||
|
||||
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11
|
||||
No transfer within this clock domain is found
|
||||
|
||||
Data transfers from:
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD
|
||||
Not reported because source and destination domains are unrelated.
|
||||
To report these transfers please refer to preference CLKSKEWDIFF to define
|
||||
external clock skew between clock ports.
|
||||
|
||||
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
|
||||
No transfer within this clock domain is found
|
||||
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47
|
||||
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
|
||||
|
||||
Data transfers from:
|
||||
Clock Domain: nCRAS_c Source: nCRAS.PAD
|
||||
Not reported because source and destination domains are unrelated.
|
||||
To report these transfers please refer to preference CLKSKEWDIFF to define
|
||||
external clock skew between clock ports.
|
||||
|
||||
Clock Domain: PHI2_c Source: PHI2.PAD
|
||||
Not reported because source and destination domains are unrelated.
|
||||
To report these transfers please refer to preference CLKSKEWDIFF to define
|
||||
external clock skew between clock ports.
|
||||
|
||||
Clock Domain: PHI2_c Source: PHI2.PAD Loads: 21
|
||||
Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
|
||||
|
||||
Data transfers from:
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD
|
||||
Not reported because source and destination domains are unrelated.
|
||||
To report these transfers please refer to preference CLKSKEWDIFF to define
|
||||
external clock skew between clock ports.
|
||||
|
||||
|
||||
<A name="mtw1_hold_ts"></A><B><U><big>Timing summary (Hold):</big></U></B>
|
||||
---------------
|
||||
|
||||
Timing errors: 0 Score: 0
|
||||
Cumulative negative slack: 0
|
||||
|
||||
Constraints cover 1025 paths, 4 nets, and 741 connections (72.86% coverage)
|
||||
|
||||
|
||||
|
||||
<A name="mtw1_ts"></A><B><U><big>Timing summary (Setup and Hold):</big></U></B>
|
||||
---------------
|
||||
|
||||
Timing errors: 0 (setup), 0 (hold)
|
||||
Score: 0 (setup), 0 (hold)
|
||||
Cumulative negative slack: 0 (0+0)
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
|
||||
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|
||||
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|
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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||||
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|
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
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File diff suppressed because one or more lines are too long
|
|
@ -0,0 +1,134 @@
|
|||
Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-1200HC
|
||||
Package: TQFP100
|
||||
Performance: 5
|
||||
Package Status: Final Version 1.44.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-1200HC
|
||||
Package: TQFP100
|
||||
Performance: 6
|
||||
Package Status: Final Version 1.44.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
Loading design for application iotiming from file ram2gs_lcmxo2_1200hc_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-1200HC
|
||||
Package: TQFP100
|
||||
Performance: M
|
||||
Package Status: Final Version 1.44.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
// Design: RAM2GS
|
||||
// Package: TQFP100
|
||||
// ncd File: ram2gs_lcmxo2_1200hc_impl1.ncd
|
||||
// Version: Diamond (64-bit) 3.12.1.454
|
||||
// Written on Thu Sep 21 05:40:06 2023
|
||||
// M: Minimum Performance Grade
|
||||
// iotiming RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml
|
||||
|
||||
I/O Timing Report (All units are in ns)
|
||||
|
||||
Worst Case Results across Performance Grades (M, 6, 5, 4):
|
||||
|
||||
// Input Setup and Hold Times
|
||||
|
||||
Port Clock Edge Setup Performance_Grade Hold Performance_Grade
|
||||
----------------------------------------------------------------------
|
||||
CROW[0] nCRAS F 2.913 4 -0.274 M
|
||||
CROW[1] nCRAS F 2.475 4 -0.161 M
|
||||
Din[0] PHI2 F 5.366 4 4.293 4
|
||||
Din[0] nCCAS F 1.448 4 -0.034 M
|
||||
Din[1] PHI2 F 4.971 4 4.173 4
|
||||
Din[1] nCCAS F 0.519 4 0.708 4
|
||||
Din[2] PHI2 F 5.192 4 4.173 4
|
||||
Din[2] nCCAS F 1.948 4 -0.142 M
|
||||
Din[3] PHI2 F 5.298 4 4.173 4
|
||||
Din[3] nCCAS F 1.974 4 -0.157 M
|
||||
Din[4] PHI2 F 4.281 4 4.173 4
|
||||
Din[4] nCCAS F 1.060 4 0.217 4
|
||||
Din[5] PHI2 F 5.059 4 4.173 4
|
||||
Din[5] nCCAS F 1.956 4 -0.150 M
|
||||
Din[6] PHI2 F 4.644 4 4.293 4
|
||||
Din[6] nCCAS F 2.886 4 -0.382 M
|
||||
Din[7] PHI2 F 5.316 4 4.293 4
|
||||
Din[7] nCCAS F 2.381 4 -0.244 M
|
||||
MAin[0] PHI2 F 4.362 4 1.145 4
|
||||
MAin[0] nCRAS F 1.189 4 0.362 4
|
||||
MAin[1] PHI2 F 4.386 4 0.999 4
|
||||
MAin[1] nCRAS F 1.884 4 -0.024 M
|
||||
MAin[2] PHI2 F 9.426 4 -0.750 M
|
||||
MAin[2] nCRAS F 1.136 4 0.453 4
|
||||
MAin[3] PHI2 F 10.458 4 -0.997 M
|
||||
MAin[3] nCRAS F 1.564 4 0.067 4
|
||||
MAin[4] PHI2 F 11.109 4 -1.209 M
|
||||
MAin[4] nCRAS F 1.390 4 0.207 4
|
||||
MAin[5] PHI2 F 9.884 4 -0.896 M
|
||||
MAin[5] nCRAS F 1.269 4 0.218 4
|
||||
MAin[6] PHI2 F 9.859 4 -0.845 M
|
||||
MAin[6] nCRAS F 0.889 4 0.653 4
|
||||
MAin[7] PHI2 F 10.678 4 -1.070 M
|
||||
MAin[7] nCRAS F 1.186 4 0.309 4
|
||||
MAin[8] nCRAS F 1.639 4 0.014 M
|
||||
MAin[9] nCRAS F 1.097 4 0.457 4
|
||||
PHI2 RCLK R -0.133 M 2.360 4
|
||||
nCCAS RCLK R 2.943 4 -0.337 M
|
||||
nCCAS nCRAS F 2.967 4 -0.214 M
|
||||
nCRAS RCLK R 3.047 4 -0.402 M
|
||||
nFWE PHI2 F 11.116 4 -1.189 M
|
||||
nFWE nCRAS F 1.394 4 0.225 4
|
||||
|
||||
|
||||
// Clock to Output Delay
|
||||
|
||||
Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
|
||||
------------------------------------------------------------------------
|
||||
LED RCLK R 11.046 4 3.298 M
|
||||
LED nCRAS F 11.710 4 3.359 M
|
||||
RA[0] RCLK R 11.397 4 3.516 M
|
||||
RA[0] nCRAS F 11.476 4 3.432 M
|
||||
RA[10] RCLK R 7.888 4 2.711 M
|
||||
RA[11] PHI2 R 9.755 4 3.200 M
|
||||
RA[1] RCLK R 11.272 4 3.469 M
|
||||
RA[1] nCRAS F 11.238 4 3.348 M
|
||||
RA[2] RCLK R 11.235 4 3.468 M
|
||||
RA[2] nCRAS F 11.665 4 3.453 M
|
||||
RA[3] RCLK R 11.390 4 3.512 M
|
||||
RA[3] nCRAS F 11.922 4 3.539 M
|
||||
RA[4] RCLK R 11.662 4 3.573 M
|
||||
RA[4] nCRAS F 11.818 4 3.505 M
|
||||
RA[5] RCLK R 11.744 4 3.584 M
|
||||
RA[5] nCRAS F 11.779 4 3.513 M
|
||||
RA[6] RCLK R 11.738 4 3.607 M
|
||||
RA[6] nCRAS F 11.836 4 3.531 M
|
||||
RA[7] RCLK R 12.475 4 3.797 M
|
||||
RA[7] nCRAS F 11.420 4 3.426 M
|
||||
RA[8] RCLK R 11.122 4 3.431 M
|
||||
RA[8] nCRAS F 11.667 4 3.471 M
|
||||
RA[9] RCLK R 11.935 4 3.649 M
|
||||
RA[9] nCRAS F 11.401 4 3.424 M
|
||||
RBA[0] nCRAS F 8.903 4 2.891 M
|
||||
RBA[1] nCRAS F 8.903 4 2.891 M
|
||||
RCKE RCLK R 10.011 4 3.215 M
|
||||
RDQMH RCLK R 10.790 4 3.354 M
|
||||
RDQML RCLK R 11.053 4 3.450 M
|
||||
RD[0] nCCAS F 8.977 4 3.012 M
|
||||
RD[1] nCCAS F 8.977 4 3.012 M
|
||||
RD[2] nCCAS F 8.977 4 3.012 M
|
||||
RD[3] nCCAS F 8.977 4 3.012 M
|
||||
RD[4] nCCAS F 8.977 4 3.012 M
|
||||
RD[5] nCCAS F 8.977 4 3.012 M
|
||||
RD[6] nCCAS F 8.977 4 3.012 M
|
||||
RD[7] nCCAS F 8.977 4 3.012 M
|
||||
nRCAS RCLK R 7.822 4 2.706 M
|
||||
nRCS RCLK R 7.822 4 2.706 M
|
||||
nRRAS RCLK R 7.822 4 2.706 M
|
||||
nRWE RCLK R 7.803 4 2.713 M
|
||||
WARNING: you must also run trce with hold speed: 4
|
||||
WARNING: you must also run trce with setup speed: M
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
SCUBA, Version Diamond (64-bit) 3.12.1.454
|
||||
Thu Sep 21 04:34:49 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
BEGIN SCUBA Module Synthesis
|
||||
|
||||
Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 66.7 -ufm -ufm_ebr 190 -mem_size 321 -memfile ../RAM2GS-LCMXO2.mem -memformat hex -wb -dev 1200
|
||||
Circuit name : REFB
|
||||
Module type : efb
|
||||
Module Version : 1.2
|
||||
Ports :
|
||||
Inputs : wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i[7:0], wb_dat_i[7:0]
|
||||
Outputs : wb_dat_o[7:0], wb_ack_o, wbc_ufm_irq
|
||||
I/O buffer : not inserted
|
||||
EDIF output : REFB.edn
|
||||
Verilog output : REFB.v
|
||||
Verilog template : REFB_tmpl.v
|
||||
Verilog purpose : for synthesis and simulation
|
||||
Bus notation : big endian
|
||||
Report output : REFB.srp
|
||||
Estimated Resource Usage:
|
||||
|
||||
END SCUBA Module Synthesis
|
||||
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<userSetting name="//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml" version="Diamond (64-bit) 3.12.1.454" date="Thu Sep 21 05:40:51 2023" vendor="Lattice Semiconductor Corporation" >
|
||||
</userSetting>
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!DOCTYPE Report>
|
||||
<ReportView version="2.0">
|
||||
<Implement name="impl1">
|
||||
<ToolReport id="tooldec" path="" status="0"/>
|
||||
<ToolReport id="toolhle_genhierarchy" path="Y:/Repos/RAM2GS/CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html" status="1"/>
|
||||
<ToolReport id="toolpio" path="" status="0"/>
|
||||
<ToolReport id="toolsso" path="" status="0"/>
|
||||
</Implement>
|
||||
</ReportView>
|
||||
|
|
@ -1,9 +0,0 @@
|
|||
[Runmanager]
|
||||
Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1c\0\0\0\xd8\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0)
|
||||
windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)
|
||||
headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0)
|
||||
|
||||
[impl1%3CStrategy1%3E]
|
||||
isChecked=false
|
||||
isHidden=false
|
||||
isExpanded=false
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
[General]
|
||||
Export.auto_tasks=IBIS, TimingSimFileVlg, TimingSimFileVHD, Bitgen, Jedecgen
|
||||
Export.auto_tasks=IBIS, TimingSimFileVlg, Bitgen, Jedecgen
|
||||
PAR.auto_tasks=PARTrace, IOTiming
|
||||
Map.auto_tasks=MapTrace, MapVerilogSimFile, MapVHDLSimFile
|
||||
Map.auto_tasks=MapTrace, MapVerilogSimFile
|
||||
|
|
|
|||
|
|
@ -1,3 +0,0 @@
|
|||
[General]
|
||||
COLUMN_POS_INFO_NAME_-1_0=Prioritize
|
||||
COLUMN_POS_INFO_NAME_-1_1=PIO Register
|
||||
|
|
@ -1,76 +0,0 @@
|
|||
[General]
|
||||
pin_sort_type=0
|
||||
pin_sort_ascending=true
|
||||
sig_sort_type=0
|
||||
sig_sort_ascending=true
|
||||
active_Sheet=Port Assignments
|
||||
|
||||
[Port%20Assignments]
|
||||
Name="160,0"
|
||||
Group%20By="84,1"
|
||||
Pin="50,2"
|
||||
BANK="62,3"
|
||||
BANK_VCC="90,4"
|
||||
VREF="60,5"
|
||||
IO_TYPE="147,6"
|
||||
PULLMODE="119,7"
|
||||
DRIVE="67,8"
|
||||
SLEWRATE="92,9"
|
||||
CLAMP="71,10"
|
||||
OPENDRAIN="97,11"
|
||||
DIFFRESISTOR="114,12"
|
||||
DIFFDRIVE="92,13"
|
||||
HYSTERESIS="101,14"
|
||||
Outload%20%28pF%29="103,15"
|
||||
MaxSkew="87,16"
|
||||
Clock%20Load%20Only="121,17"
|
||||
SwitchingID="100,18"
|
||||
Ground%20plane%20PCB%20noise%20%28mV%29="196,19"
|
||||
Power%20plane%20PCB%20noise%20%28mV%29="190,20"
|
||||
SSO%20Allowance%28%25%29="138,21"
|
||||
sort_columns="Name,Ascending"
|
||||
|
||||
[Pin%20Assignments]
|
||||
Pin="90,0"
|
||||
Pad%20Name="89,1"
|
||||
Dual%20Function="158,2"
|
||||
Polarity="77,3"
|
||||
BANK="0,4"
|
||||
BANK_VCC="90,5"
|
||||
IO_TYPE="147,6"
|
||||
Signal%20Name="123,7"
|
||||
Signal%20Type="115,8"
|
||||
sort_columns="Pin,Ascending"
|
||||
|
||||
[Clock%20Resource]
|
||||
Clock%20Type="100,ELLIPSIS"
|
||||
Clock%20Name="100,ELLIPSIS"
|
||||
Selection="100,ELLIPSIS"
|
||||
|
||||
[Global%20Preferences]
|
||||
Preference%20Name="231,ELLIPSIS"
|
||||
Preference%20Value="236,ELLIPSIS"
|
||||
|
||||
[Cell%20Mapping]
|
||||
Type="100,ELLIPSIS"
|
||||
Name="100,ELLIPSIS"
|
||||
Din\Dout="100,ELLIPSIS"
|
||||
PIO%20Register="100,ELLIPSIS"
|
||||
|
||||
[Route%20Priority]
|
||||
Type="100,ELLIPSIS"
|
||||
Name="100,ELLIPSIS"
|
||||
Prioritize="100,ELLIPSIS"
|
||||
|
||||
[Timing%20Preferences]
|
||||
Preference%20Name="158,ELLIPSIS"
|
||||
Preference%20Value="105,ELLIPSIS"
|
||||
Preference%20Unit="98,ELLIPSIS"
|
||||
|
||||
[Group]
|
||||
Group%20Type\Name="134,ELLIPSIS"
|
||||
Value="39,ELLIPSIS"
|
||||
|
||||
[Misc%20Preferences]
|
||||
Preference%20Name="117,ELLIPSIS"
|
||||
Preference%20Value="105,ELLIPSIS"
|
||||
|
|
@ -1,208 +0,0 @@
|
|||
<HTML>
|
||||
<HEAD><TITLE>Lattice TCL Log</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="pn230816203441"></A><B><U><big>pn230816203441</big></U></B>
|
||||
#Start recording tcl command: 8/16/2023 20:34:10
|
||||
#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
|
||||
prj_project new -name "LCMXO2_640HC" -impl "impl1" -dev LCMXO2-640HC-4TG100C -synthesis "synplify"
|
||||
prj_src add "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.v"
|
||||
prj_project save
|
||||
prj_src add -exclude "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.lpf"
|
||||
#Stop recording: 8/16/2023 20:34:41
|
||||
|
||||
|
||||
|
||||
<A name="pn230816210353"></A><B><U><big>pn230816210353</big></U></B>
|
||||
#Start recording tcl command: 8/16/2023 20:34:55
|
||||
#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
|
||||
prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Synthesis -impl impl1
|
||||
prj_run Map -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run PAR -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_src add "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/REFB.v"
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_src add "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS.sdc"
|
||||
prj_run Export -impl impl1
|
||||
#Stop recording: 8/16/2023 21:03:53
|
||||
|
||||
|
||||
|
||||
<A name="pn230819062748"></A><B><U><big>pn230819062748</big></U></B>
|
||||
#Start recording tcl command: 8/18/2023 08:16:23
|
||||
#Project Location: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
|
||||
prj_project open "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Synthesis -impl impl1
|
||||
#Stop recording: 8/19/2023 06:27:48
|
||||
|
||||
|
||||
|
||||
<A name="pn230819062826"></A><B><U><big>pn230819062826</big></U></B>
|
||||
#Start recording tcl command: 8/19/2023 06:27:54
|
||||
#Project Location: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
|
||||
prj_project open "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
|
||||
prj_run Synthesis -impl impl1 -task Synplify_Synthesis
|
||||
#Stop recording: 8/19/2023 06:28:26
|
||||
|
||||
|
||||
|
||||
<A name="pn230819062853"></A><B><U><big>pn230819062853</big></U></B>
|
||||
#Start recording tcl command: 8/19/2023 06:28:30
|
||||
#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
|
||||
prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
|
||||
prj_run Synthesis -impl impl1
|
||||
prj_project close
|
||||
#Stop recording: 8/19/2023 06:28:53
|
||||
|
||||
|
||||
|
||||
<A name="pn230819062900"></A><B><U><big>pn230819062900</big></U></B>
|
||||
#Start recording tcl command: 8/19/2023 06:28:53
|
||||
#Project Location: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
|
||||
prj_project open "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
|
||||
prj_project close
|
||||
#Stop recording: 8/19/2023 06:29:00
|
||||
|
||||
|
||||
|
||||
<A name="pn230819063021"></A><B><U><big>pn230819063021</big></U></B>
|
||||
#Start recording tcl command: 8/19/2023 06:29:00
|
||||
#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
|
||||
prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
|
||||
#Stop recording: 8/19/2023 06:30:21
|
||||
|
||||
|
||||
|
||||
<A name="pn230819205234"></A><B><U><big>pn230819205234</big></U></B>
|
||||
#Start recording tcl command: 8/19/2023 06:30:42
|
||||
#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
|
||||
prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
pgr_project save "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
|
||||
prj_src add -exclude "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
|
||||
prj_src enable "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
|
||||
pgr_program run
|
||||
pgr_program run
|
||||
pgr_program set -cable USB2
|
||||
pgr_program set -port FTUSB-0
|
||||
pgr_program run
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
pgr_project save "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
pgr_project close
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1 -forceOne
|
||||
prj_run Export -impl impl1 -forceOne
|
||||
prj_run Export -impl impl1 -forceOne
|
||||
prj_run Export -impl impl1 -forceOne
|
||||
prj_project save
|
||||
prj_project close
|
||||
#Stop recording: 8/19/2023 20:52:34
|
||||
|
||||
|
||||
|
||||
<A name="pn230820055534"></A><B><U><big>pn230820055534</big></U></B>
|
||||
#Start recording tcl command: 8/19/2023 21:54:38
|
||||
#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
|
||||
prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_project close
|
||||
#Stop recording: 8/20/2023 05:55:34
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
||||
|
|
@ -1,7 +0,0 @@
|
|||
#Start recording tcl command: 8/16/2023 20:34:10
|
||||
#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
|
||||
prj_project new -name "LCMXO2_640HC" -impl "impl1" -dev LCMXO2-640HC-4TG100C -synthesis "synplify"
|
||||
prj_src add "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.v"
|
||||
prj_project save
|
||||
prj_src add -exclude "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS-LCMXO2.lpf"
|
||||
#Stop recording: 8/16/2023 20:34:41
|
||||
|
|
@ -1,24 +0,0 @@
|
|||
#Start recording tcl command: 8/16/2023 20:34:55
|
||||
#Project Location: D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
|
||||
prj_project open "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Synthesis -impl impl1
|
||||
prj_run Map -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run PAR -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_src add "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/REFB.v"
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_src add "D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/RAM2GS.sdc"
|
||||
prj_run Export -impl impl1
|
||||
#Stop recording: 8/16/2023 21:03:53
|
||||
|
|
@ -1,7 +0,0 @@
|
|||
#Start recording tcl command: 8/18/2023 08:16:23
|
||||
#Project Location: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
|
||||
prj_project open "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Synthesis -impl impl1
|
||||
#Stop recording: 8/19/2023 06:27:48
|
||||
|
|
@ -1,5 +0,0 @@
|
|||
#Start recording tcl command: 8/19/2023 06:27:54
|
||||
#Project Location: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
|
||||
prj_project open "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
|
||||
prj_run Synthesis -impl impl1 -task Synplify_Synthesis
|
||||
#Stop recording: 8/19/2023 06:28:26
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
#Start recording tcl command: 8/19/2023 06:28:30
|
||||
#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
|
||||
prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
|
||||
prj_run Synthesis -impl impl1
|
||||
prj_project close
|
||||
#Stop recording: 8/19/2023 06:28:53
|
||||
|
|
@ -1,5 +0,0 @@
|
|||
#Start recording tcl command: 8/19/2023 06:28:53
|
||||
#Project Location: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
|
||||
prj_project open "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
|
||||
prj_project close
|
||||
#Stop recording: 8/19/2023 06:29:00
|
||||
|
|
@ -1,4 +0,0 @@
|
|||
#Start recording tcl command: 8/19/2023 06:29:00
|
||||
#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
|
||||
prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
|
||||
#Stop recording: 8/19/2023 06:30:21
|
||||
|
|
@ -1,47 +0,0 @@
|
|||
#Start recording tcl command: 8/19/2023 06:30:42
|
||||
#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
|
||||
prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
pgr_project save "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
|
||||
prj_src add -exclude "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
|
||||
prj_src enable "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
|
||||
pgr_program run
|
||||
pgr_program run
|
||||
pgr_program set -cable USB2
|
||||
pgr_program set -port FTUSB-0
|
||||
pgr_program run
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
pgr_project save "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/impl1.xcf"
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
pgr_project close
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1 -forceOne
|
||||
prj_run Export -impl impl1 -forceOne
|
||||
prj_run Export -impl impl1 -forceOne
|
||||
prj_run Export -impl impl1 -forceOne
|
||||
prj_project save
|
||||
prj_project close
|
||||
#Stop recording: 8/19/2023 20:52:34
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
#Start recording tcl command: 8/19/2023 21:54:38
|
||||
#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
|
||||
prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_project close
|
||||
#Stop recording: 8/20/2023 05:55:34
|
||||
|
|
@ -1,4 +0,0 @@
|
|||
#Start recording tcl command: 8/20/2023 05:55:58
|
||||
#Project Location: Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: LCMXO2_640HC
|
||||
prj_project open "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/LCMXO2_640HC.ldf"
|
||||
#Stop recording: 8/20/2023 05:56:26
|
||||
|
|
@ -1 +0,0 @@
|
|||
VERSION=20110520
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<BaliProject version="3.2" title="RAM2GS_LCMXO2_640HC" device="LCMXO2-640HC-4TG100C" default_implementation="impl1">
|
||||
<Options/>
|
||||
<Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
|
||||
<Options def_top="RAM2GS"/>
|
||||
<Source name="../RAM2GS-LCMXO2.v" type="Verilog" type_short="Verilog">
|
||||
<Options top_module="RAM2GS"/>
|
||||
</Source>
|
||||
<Source name="REFB.v" type="Verilog" type_short="Verilog">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="../RAM2GS-LCMXO2.lpf" type="Logic Preference" type_short="LPF">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="../RAM2GS.sdc" type="Synplify Design Constraints File" type_short="SDC">
|
||||
<Options/>
|
||||
</Source>
|
||||
</Implementation>
|
||||
<Strategy name="Strategy1" file="RAM2GS_LCMXO2_640HC1.sty"/>
|
||||
</BaliProject>
|
||||
|
|
@ -0,0 +1,205 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!DOCTYPE strategy>
|
||||
<Strategy version="1.0" predefined="0" description="" label="Strategy1">
|
||||
<Property name="PROP_BD_CmdLineArgs" value="" time="0"/>
|
||||
<Property name="PROP_BD_EdfHardtimer" value="Enable" time="0"/>
|
||||
<Property name="PROP_BD_EdfInBusNameConv" value="None" time="0"/>
|
||||
<Property name="PROP_BD_EdfInLibPath" value="" time="0"/>
|
||||
<Property name="PROP_BD_EdfInRemLoc" value="Off" time="0"/>
|
||||
<Property name="PROP_BD_EdfMemPath" value="" time="0"/>
|
||||
<Property name="PROP_BD_ParSearchPath" value="" time="0"/>
|
||||
<Property name="PROP_BIT_AddressBitGen" value="Increment" time="0"/>
|
||||
<Property name="PROP_BIT_AllowReadBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_ByteWideBitMirror" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_CapReadBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_ConModBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_CreateBitFile" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_DisRAMResBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_DisableUESBitgen" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_DonePinBitGen" value="Pullup" time="0"/>
|
||||
<Property name="PROP_BIT_DoneSigBitGen" value="4" time="0"/>
|
||||
<Property name="PROP_BIT_EnIOBitGen" value="TriStateDuringReConfig" time="0"/>
|
||||
<Property name="PROP_BIT_EnIntOscBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_ExtClockBitGen" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_GSREnableBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_GSRRelOnBitGen" value="DoneIn" time="0"/>
|
||||
<Property name="PROP_BIT_GranTimBitGen" value="0" time="0"/>
|
||||
<Property name="PROP_BIT_IOTriRelBitGen" value="Cycle 2" time="0"/>
|
||||
<Property name="PROP_BIT_JTAGEnableBitGen" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_LenBitsBitGen" value="24" time="0"/>
|
||||
<Property name="PROP_BIT_MIFFileBitGen" value="" time="0"/>
|
||||
<Property name="PROP_BIT_NoHeader" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_OutFormatBitGen" value="Bit File (Binary)" time="0"/>
|
||||
<Property name="PROP_BIT_OutFormatBitGen_REF" value="" time="0"/>
|
||||
<Property name="PROP_BIT_OutFormatPromGen" value="Intel Hex 32-bit" time="0"/>
|
||||
<Property name="PROP_BIT_ParityCheckBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_ReadBackBitGen" value="Flash" time="0"/>
|
||||
<Property name="PROP_BIT_ReadCaptureBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_RemZeroFramesBitGen" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_RunDRCBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_SearchPthBitGen" value="" time="0"/>
|
||||
<Property name="PROP_BIT_StartUpClkBitGen" value="Cclk" time="0"/>
|
||||
<Property name="PROP_BIT_SynchIOBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_SysClockConBitGen" value="Reset" time="0"/>
|
||||
<Property name="PROP_BIT_SysConBitGen" value="Reset" time="0"/>
|
||||
<Property name="PROP_BIT_WaitStTimBitGen" value="5" time="0"/>
|
||||
<Property name="PROP_IOTIMING_AllSpeed" value="False" time="0"/>
|
||||
<Property name="PROP_LST_AllowDUPMod" value="False" time="0"/>
|
||||
<Property name="PROP_LST_CarryChain" value="True" time="0"/>
|
||||
<Property name="PROP_LST_CarryChainLength" value="0" time="0"/>
|
||||
<Property name="PROP_LST_CmdLineArgs" value="" time="0"/>
|
||||
<Property name="PROP_LST_DSPStyle" value="DSP" time="0"/>
|
||||
<Property name="PROP_LST_DSPUtil" value="100" time="0"/>
|
||||
<Property name="PROP_LST_DecodeUnreachableStates" value="False" time="0"/>
|
||||
<Property name="PROP_LST_DisableDistRam" value="False" time="0"/>
|
||||
<Property name="PROP_LST_EBRUtil" value="100" time="0"/>
|
||||
<Property name="PROP_LST_EdfFrequency" value="200" time="0"/>
|
||||
<Property name="PROP_LST_EdfHardtimer" value="Enable" time="0"/>
|
||||
<Property name="PROP_LST_EdfInLibPath" value="" time="0"/>
|
||||
<Property name="PROP_LST_EdfInRemLoc" value="Off" time="0"/>
|
||||
<Property name="PROP_LST_EdfMemPath" value="" time="0"/>
|
||||
<Property name="PROP_LST_FIXGATEDCLKS" value="True" time="0"/>
|
||||
<Property name="PROP_LST_FSMEncodeStyle" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_ForceGSRInfer" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_IOInsertion" value="True" time="0"/>
|
||||
<Property name="PROP_LST_InterFileDump" value="False" time="0"/>
|
||||
<Property name="PROP_LST_LoopLimit" value="1950" time="0"/>
|
||||
<Property name="PROP_LST_MaxFanout" value="1000" time="0"/>
|
||||
<Property name="PROP_LST_MuxStyle" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_NumCriticalPaths" value="3" time="0"/>
|
||||
<Property name="PROP_LST_OptimizeGoal" value="Balanced" time="0"/>
|
||||
<Property name="PROP_LST_PropagatConst" value="True" time="0"/>
|
||||
<Property name="PROP_LST_RAMStyle" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_ROMStyle" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_RemoveDupRegs" value="True" time="0"/>
|
||||
<Property name="PROP_LST_ResolvedMixedDrivers" value="False" time="0"/>
|
||||
<Property name="PROP_LST_ResourceShare" value="True" time="0"/>
|
||||
<Property name="PROP_LST_UseIOReg" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_UseLPF" value="True" time="0"/>
|
||||
<Property name="PROP_LST_VHDL2008" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
|
||||
<Property name="PROP_MAPSTA_AutoTiming" value="True" time="0"/>
|
||||
<Property name="PROP_MAPSTA_CheckUnconstrainedConns" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_CheckUnconstrainedPaths" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_FullName" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_NumUnconstrainedPaths" value="0" time="0"/>
|
||||
<Property name="PROP_MAPSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
|
||||
<Property name="PROP_MAPSTA_RouteEstAlogtithm" value="0" time="0"/>
|
||||
<Property name="PROP_MAPSTA_RptAsynTimLoop" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_WordCasePaths" value="1" time="0"/>
|
||||
<Property name="PROP_MAP_IgnorePreErr" value="True" time="0"/>
|
||||
<Property name="PROP_MAP_MAPIORegister" value="Auto" time="0"/>
|
||||
<Property name="PROP_MAP_MAPInferGSR" value="True" time="0"/>
|
||||
<Property name="PROP_MAP_MapModArgs" value="" time="0"/>
|
||||
<Property name="PROP_MAP_OvermapDevice" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_PackLogMapDes" value="0" time="0"/>
|
||||
<Property name="PROP_MAP_RegRetiming" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_SigCrossRef" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_SymCrossRef" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_TimingDriven" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_TimingDrivenNodeRep" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_TimingDrivenPack" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
|
||||
<Property name="PROP_PARSTA_AutoTiming" value="True" time="0"/>
|
||||
<Property name="PROP_PARSTA_CheckUnconstrainedConns" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_CheckUnconstrainedPaths" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_FullName" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_NumUnconstrainedPaths" value="0" time="0"/>
|
||||
<Property name="PROP_PARSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
|
||||
<Property name="PROP_PARSTA_RptAsynTimLoop" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_SpeedForHoldAnalysis" value="m" time="0"/>
|
||||
<Property name="PROP_PARSTA_SpeedForSetupAnalysis" value="default" time="0"/>
|
||||
<Property name="PROP_PARSTA_WordCasePaths" value="10" time="0"/>
|
||||
<Property name="PROP_PAR_CrDlyStFileParDes" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_DisableTDParDes" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_EffortParDes" value="5" time="0"/>
|
||||
<Property name="PROP_PAR_MultiSeedSortMode" value="Worst Slack" time="0"/>
|
||||
<Property name="PROP_PAR_NewRouteParDes" value="NBR" time="0"/>
|
||||
<Property name="PROP_PAR_PARClockSkew" value="Off" time="0"/>
|
||||
<Property name="PROP_PAR_PARModArgs" value="" time="0"/>
|
||||
<Property name="PROP_PAR_ParMultiNodeList" value="" time="0"/>
|
||||
<Property name="PROP_PAR_ParRunPlaceOnly" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_PlcIterParDes" value="1" time="0"/>
|
||||
<Property name="PROP_PAR_PlcStCostTblParDes" value="1" time="0"/>
|
||||
<Property name="PROP_PAR_PrefErrorOut" value="True" time="0"/>
|
||||
<Property name="PROP_PAR_RemoveDir" value="True" time="0"/>
|
||||
<Property name="PROP_PAR_RouteDlyRedParDes" value="0" time="0"/>
|
||||
<Property name="PROP_PAR_RoutePassParDes" value="6" time="0"/>
|
||||
<Property name="PROP_PAR_RouteResOptParDes" value="0" time="0"/>
|
||||
<Property name="PROP_PAR_RoutingCDP" value="0" time="0"/>
|
||||
<Property name="PROP_PAR_RoutingCDR" value="0" time="0"/>
|
||||
<Property name="PROP_PAR_RunParWithTrce" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_RunTimeReduction" value="True" time="0"/>
|
||||
<Property name="PROP_PAR_SaveBestRsltParDes" value="1" time="0"/>
|
||||
<Property name="PROP_PAR_StopZero" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_parHold" value="On" time="0"/>
|
||||
<Property name="PROP_PAR_parPathBased" value="Off" time="0"/>
|
||||
<Property name="PROP_PRE_CmdLineArgs" value="" time="0"/>
|
||||
<Property name="PROP_PRE_EdfArrayBoundsCase" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfAutoResOfRam" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfClockDomainCross" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfDSPAcrossHie" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfFullCase" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfIgnoreRamRWCol" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfMissConstraint" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfNetFanout" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfParaCase" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfReencodeFSM" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfResSharing" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfTimingViolation" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfUseSafeFSM" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfVlog2001" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynComArea" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynCritcal" value="3" time="0"/>
|
||||
<Property name="PROP_PRE_VSynFSM" value="Auto" time="0"/>
|
||||
<Property name="PROP_PRE_VSynFreq" value="200" time="0"/>
|
||||
<Property name="PROP_PRE_VSynGSR" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_VSynGatedClk" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_VSynIOPad" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_VSynOutNetForm" value="None" time="0"/>
|
||||
<Property name="PROP_PRE_VSynOutPref" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynRepClkFreq" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynRetime" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynTimSum" value="10" time="0"/>
|
||||
<Property name="PROP_PRE_VSynTransform" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSyninpd" value="0" time="0"/>
|
||||
<Property name="PROP_PRE_VSynoutd" value="0" time="0"/>
|
||||
<Property name="PROP_SYN_ClockConversion" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_CmdLineArgs" value="" time="0"/>
|
||||
<Property name="PROP_SYN_DisableRegisterRep" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfAllowDUPMod" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfArea" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfArrangeVHDLFiles" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfDefEnumEncode" value="Default" time="0"/>
|
||||
<Property name="PROP_SYN_EdfFanout" value="1000" time="0"/>
|
||||
<Property name="PROP_SYN_EdfFrequency" value="100" time="0"/>
|
||||
<Property name="PROP_SYN_EdfGSR" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfInsertIO" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfNumCritPath" value="" time="0"/>
|
||||
<Property name="PROP_SYN_EdfNumStartEnd" value="" time="0"/>
|
||||
<Property name="PROP_SYN_EdfOutNetForm" value="None" time="0"/>
|
||||
<Property name="PROP_SYN_EdfPushTirstates" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfResSharing" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfRunRetiming" value="Pipelining Only" time="0"/>
|
||||
<Property name="PROP_SYN_EdfSymFSM" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfUnconsClk" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfVerilogInput" value="Verilog 2001" time="0"/>
|
||||
<Property name="PROP_SYN_ExportSetting" value="No" time="0"/>
|
||||
<Property name="PROP_SYN_LibPath" value="" time="0"/>
|
||||
<Property name="PROP_SYN_ResolvedMixedDrivers" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_UpdateCompilePtTimData" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_UseLPF" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_VHDL2008" value="False" time="0"/>
|
||||
<Property name="PROP_THERMAL_DefaultFreq" value="0" time="0"/>
|
||||
<Property name="PROP_TIM_MaxDelSimDes" value="" time="0"/>
|
||||
<Property name="PROP_TIM_MinSpeedGrade" value="False" time="0"/>
|
||||
<Property name="PROP_TIM_ModPreSimDes" value="" time="0"/>
|
||||
<Property name="PROP_TIM_NegStupHldTim" value="True" time="0"/>
|
||||
<Property name="PROP_TIM_TimSimGenPUR" value="True" time="0"/>
|
||||
<Property name="PROP_TIM_TimSimGenX" value="False" time="0"/>
|
||||
<Property name="PROP_TIM_TimSimHierSep" value="" time="0"/>
|
||||
<Property name="PROP_TIM_TransportModeOfPathDelay" value="False" time="0"/>
|
||||
<Property name="PROP_TIM_TrgtSpeedGrade" value="" time="0"/>
|
||||
<Property name="PROP_TIM_WriteVerboseNetlist" value="False" time="0"/>
|
||||
<Property name="PROP_TMCHK_EnableCheck" value="True" time="0"/>
|
||||
</Strategy>
|
||||
|
|
@ -4,7 +4,7 @@
|
|||
(keywordMap (keywordLevel 0))
|
||||
(status
|
||||
(written
|
||||
(timestamp 2023 8 19 7 25 4)
|
||||
(timestamp 2023 8 23 4 27 49)
|
||||
(program "SCUBA" (version "Diamond (64-bit) 3.12.1.454"))))
|
||||
(comment "C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 66.7 -ufm -ufm_ebr 190 -mem_size 1 -memfile ../RAM2GS-LCMXO2.mem -memformat hex -wb -dev 640 ")
|
||||
(library ORCLIB
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<DiamondModule name="REFB" module="EFB" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2023 08 19 07:25:06.194" version="1.2" type="Module" synthesis="synplify" source_format="Verilog">
|
||||
<DiamondModule name="REFB" module="EFB" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2023 08 23 04:27:50.897" version="1.2" type="Module" synthesis="synplify" source_format="Verilog">
|
||||
<Package>
|
||||
<File name="REFB.lpc" type="lpc" modified="2023 08 19 07:25:04.117"/>
|
||||
<File name="REFB.v" type="top_level_verilog" modified="2023 08 19 07:25:04.191"/>
|
||||
<File name="REFB_tmpl.v" type="template_verilog" modified="2023 08 19 07:25:04.191"/>
|
||||
<File name="REFB.lpc" type="lpc" modified="2023 08 23 04:27:49.186"/>
|
||||
<File name="REFB.v" type="top_level_verilog" modified="2023 08 23 04:27:49.262"/>
|
||||
<File name="REFB_tmpl.v" type="template_verilog" modified="2023 08 23 04:27:49.262"/>
|
||||
</Package>
|
||||
</DiamondModule>
|
||||
|
|
|
|||
|
|
@ -16,8 +16,8 @@ CoreRevision=1.2
|
|||
ModuleName=REFB
|
||||
SourceFormat=Verilog HDL
|
||||
ParameterFileVersion=1.0
|
||||
Date=08/19/2023
|
||||
Time=07:25:04
|
||||
Date=08/23/2023
|
||||
Time=04:27:49
|
||||
|
||||
[Parameters]
|
||||
Verilog=1
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
SCUBA, Version Diamond (64-bit) 3.12.1.454
|
||||
Sat Aug 19 07:25:04 2023
|
||||
Wed Aug 23 04:27:49 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 */
|
||||
/* Module Version: 1.2 */
|
||||
/* C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 66.7 -ufm -ufm_ebr 190 -mem_size 1 -memfile ../RAM2GS-LCMXO2.mem -memformat hex -wb -dev 640 */
|
||||
/* Sat Aug 19 07:25:04 2023 */
|
||||
/* Wed Aug 23 04:27:49 2023 */
|
||||
|
||||
|
||||
`timescale 1 ns / 1 ps
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@ Starting process: Module
|
|||
Starting process:
|
||||
|
||||
SCUBA, Version Diamond (64-bit) 3.12.1.454
|
||||
Sat Aug 19 07:25:04 2023
|
||||
Wed Aug 23 04:27:49 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.12.1.454 */
|
||||
/* Module Version: 1.2 */
|
||||
/* Sat Aug 19 07:25:04 2023 */
|
||||
/* Wed Aug 23 04:27:49 2023 */
|
||||
|
||||
/* parameterized module instance */
|
||||
REFB __ (.wb_clk_i( ), .wb_rst_i( ), .wb_cyc_i( ), .wb_stb_i( ),
|
||||
|
|
|
|||
|
|
@ -1,55 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<BuildStatus>
|
||||
<Strategy name="Strategy1">
|
||||
<Milestone name="Export" build_result="0" build_time="0">
|
||||
<Task name="IBIS" build_result="2" update_result="0" update_time="1692496517"/>
|
||||
<Task name="TimingSimFileVlg" build_result="2" update_result="0" update_time="1692496519"/>
|
||||
<Task name="TimingSimFileVHD" build_result="2" update_result="0" update_time="1692496520"/>
|
||||
<Task name="Bitgen" build_result="2" update_result="0" update_time="1692496523"/>
|
||||
<Task name="Jedecgen" build_result="2" update_result="0" update_time="1692496527"/>
|
||||
</Milestone>
|
||||
<Milestone name="Map" build_result="2" build_time="1692496497">
|
||||
<Task name="Map" build_result="2" update_result="0" update_time="1692496497"/>
|
||||
<Task name="MapTrace" build_result="2" update_result="0" update_time="1692496498"/>
|
||||
<Task name="MapVerilogSimFile" build_result="2" update_result="0" update_time="1692496499"/>
|
||||
<Task name="MapVHDLSimFile" build_result="2" update_result="0" update_time="1692496501"/>
|
||||
</Milestone>
|
||||
<Milestone name="PAR" build_result="2" build_time="1692496511">
|
||||
<Task name="PAR" build_result="2" update_result="0" update_time="1692496511"/>
|
||||
<Task name="PARTrace" build_result="2" update_result="0" update_time="1692496511"/>
|
||||
<Task name="IOTiming" build_result="2" update_result="0" update_time="1692496513"/>
|
||||
</Milestone>
|
||||
<Milestone name="Synthesis" build_result="2" build_time="1692496496">
|
||||
<Task name="Synplify_Synthesis" build_result="2" update_result="0" update_time="1692496496"/>
|
||||
</Milestone>
|
||||
<Milestone name="TOOL_Report" build_result="0" build_time="0">
|
||||
<Task name="HDLE" build_result="2" update_result="0" update_time="1692444754"/>
|
||||
<Task name="BKM" build_result="0" update_result="2" update_time="1692444754"/>
|
||||
<Task name="SSO" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="PIODRC" build_result="0" update_result="3" update_time="0"/>
|
||||
<Task name="DEC" build_result="0" update_result="3" update_time="0"/>
|
||||
</Milestone>
|
||||
<Milestone name="Translate" build_result="2" build_time="1692496497">
|
||||
<Task name="Translate" build_result="2" update_result="0" update_time="1692496497"/>
|
||||
</Milestone>
|
||||
<Report name="IBIS/LCMXO2_640HC_impl1.ibs" last_build_time="1692496517" last_build_size="184928"/>
|
||||
<Report name="LCMXO2_640HC_impl1.bgn" last_build_time="1692496527" last_build_size="4359"/>
|
||||
<Report name="LCMXO2_640HC_impl1.bit" last_build_time="1692496523" last_build_size="6185"/>
|
||||
<Report name="LCMXO2_640HC_impl1.edi" last_build_time="1692496494" last_build_size="198884"/>
|
||||
<Report name="LCMXO2_640HC_impl1.ior" last_build_time="1692496513" last_build_size="6573"/>
|
||||
<Report name="LCMXO2_640HC_impl1.jed" last_build_time="1692496527" last_build_size="177085"/>
|
||||
<Report name="LCMXO2_640HC_impl1.ncd" last_build_time="1692496511" last_build_size="268674"/>
|
||||
<Report name="LCMXO2_640HC_impl1.ngd" last_build_time="1692496497" last_build_size="204730"/>
|
||||
<Report name="LCMXO2_640HC_impl1.tw1" last_build_time="1692496498" last_build_size="17550"/>
|
||||
<Report name="LCMXO2_640HC_impl1.twr" last_build_time="1692496511" last_build_size="90277"/>
|
||||
<Report name="LCMXO2_640HC_impl1_map.ncd" last_build_time="1692496497" last_build_size="193033"/>
|
||||
<Report name="LCMXO2_640HC_impl1_mapvho.sdf" last_build_time="1692496501" last_build_size="164487"/>
|
||||
<Report name="LCMXO2_640HC_impl1_mapvho.vho" last_build_time="1692496501" last_build_size="1365291"/>
|
||||
<Report name="LCMXO2_640HC_impl1_mapvo.sdf" last_build_time="1692496499" last_build_size="163556"/>
|
||||
<Report name="LCMXO2_640HC_impl1_mapvo.vo" last_build_time="1692496499" last_build_size="201461"/>
|
||||
<Report name="LCMXO2_640HC_impl1_vho.sdf" last_build_time="1692496520" last_build_size="181438"/>
|
||||
<Report name="LCMXO2_640HC_impl1_vho.vho" last_build_time="1692496520" last_build_size="1408234"/>
|
||||
<Report name="LCMXO2_640HC_impl1_vo.sdf" last_build_time="1692496519" last_build_size="180465"/>
|
||||
<Report name="LCMXO2_640HC_impl1_vo.vo" last_build_time="1692496519" last_build_size="212142"/>
|
||||
</Strategy>
|
||||
</BuildStatus>
|
||||
File diff suppressed because it is too large
Load Diff
Binary file not shown.
Binary file not shown.
|
|
@ -1,216 +0,0 @@
|
|||
|
||||
Lattice Place and Route Report for Design "LCMXO2_640HC_impl1_map.ncd"
|
||||
Sat Aug 19 21:55:01 2023
|
||||
|
||||
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
|
||||
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir/5_1.ncd LCMXO2_640HC_impl1.prf
|
||||
Preference file: LCMXO2_640HC_impl1.prf.
|
||||
Placement level-cost: 5-1.
|
||||
Routing Iterations: 6
|
||||
|
||||
Loading design for application par from file LCMXO2_640HC_impl1_map.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-640HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application par from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.39.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
License checked out.
|
||||
|
||||
|
||||
Ignore Preference Error(s): True
|
||||
Device utilization summary:
|
||||
|
||||
PIO (prelim) 63+4(JTAG)/80 84% used
|
||||
63+4(JTAG)/79 85% bonded
|
||||
IOLOGIC 25/80 31% used
|
||||
|
||||
SLICE 113/320 35% used
|
||||
|
||||
EFB 1/1 100% used
|
||||
|
||||
|
||||
Number of Signals: 374
|
||||
Number of Connections: 978
|
||||
|
||||
Pin Constraint Summary:
|
||||
63 out of 63 pins locked (100% locked).
|
||||
|
||||
The following 3 signals are selected to use the primary clock routing resources:
|
||||
RCLK_c (driver: RCLK, clk load #: 47)
|
||||
PHI2_c (driver: PHI2, clk load #: 21)
|
||||
nCRAS_c (driver: nCRAS, clk load #: 10)
|
||||
|
||||
WARNING - par: Signal "RCLK_c" is selected to use Primary clock resources. However, its driver comp "RCLK" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
WARNING - par: Signal "nCRAS_c" is selected to use Primary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
|
||||
The following 1 signal is selected to use the secondary clock routing resources:
|
||||
nCCAS_c (driver: nCCAS, clk load #: 8, sr load #: 0, ce load #: 0)
|
||||
|
||||
WARNING - par: Signal "nCCAS_c" is selected to use Secondary clock resources. However, its driver comp "nCCAS" is located at "9", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
No signal is selected as Global Set/Reset.
|
||||
Starting Placer Phase 0.
|
||||
............
|
||||
Finished Placer Phase 0. REAL time: 0 secs
|
||||
|
||||
Starting Placer Phase 1.
|
||||
....................
|
||||
Placer score = 53481.
|
||||
Finished Placer Phase 1. REAL time: 5 secs
|
||||
|
||||
Starting Placer Phase 2.
|
||||
.
|
||||
Placer score = 53406
|
||||
Finished Placer Phase 2. REAL time: 5 secs
|
||||
|
||||
|
||||
------------------ Clock Report ------------------
|
||||
|
||||
Global Clock Resources:
|
||||
CLK_PIN : 0 out of 8 (0%)
|
||||
General PIO: 4 out of 80 (5%)
|
||||
DCM : 0 out of 2 (0%)
|
||||
DCC : 0 out of 8 (0%)
|
||||
|
||||
Global Clocks:
|
||||
PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 47
|
||||
PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 21
|
||||
PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 10
|
||||
SECONDARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 8, ce load = 0, sr load = 0
|
||||
|
||||
PRIMARY : 3 out of 8 (37%)
|
||||
SECONDARY: 1 out of 8 (12%)
|
||||
|
||||
--------------- End of Clock Report ---------------
|
||||
|
||||
|
||||
I/O Usage Summary (final):
|
||||
63 + 4(JTAG) out of 80 (83.8%) PIO sites used.
|
||||
63 + 4(JTAG) out of 79 (84.8%) bonded PIO sites used.
|
||||
Number of PIO comps: 63; differential: 0.
|
||||
Number of Vref pins used: 0.
|
||||
|
||||
I/O Bank Usage Summary:
|
||||
+----------+----------------+------------+-----------+
|
||||
| I/O Bank | Usage | Bank Vccio | Bank Vref |
|
||||
+----------+----------------+------------+-----------+
|
||||
| 0 | 13 / 19 ( 68%) | 3.3V | - |
|
||||
| 1 | 20 / 20 (100%) | 3.3V | - |
|
||||
| 2 | 12 / 20 ( 60%) | 3.3V | - |
|
||||
| 3 | 18 / 20 ( 90%) | 3.3V | - |
|
||||
+----------+----------------+------------+-----------+
|
||||
|
||||
Total placer CPU time: 5 secs
|
||||
|
||||
Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd.
|
||||
|
||||
0 connections routed; 978 unrouted.
|
||||
Starting router resource preassignment
|
||||
WARNING - par: The driver of primary clock net RCLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
|
||||
WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
|
||||
|
||||
Completed router resource preassignment. Real time: 8 secs
|
||||
|
||||
Start NBR router at 21:55:09 08/19/23
|
||||
|
||||
*****************************************************************
|
||||
Info: NBR allows conflicts(one node used by more than one signal)
|
||||
in the earlier iterations. In each iteration, it tries to
|
||||
solve the conflicts while keeping the critical connections
|
||||
routed as short as possible. The routing process is said to
|
||||
be completed when no conflicts exist and all connections
|
||||
are routed.
|
||||
Note: NBR uses a different method to calculate timing slacks. The
|
||||
worst slack and total negative slack may not be the same as
|
||||
that in TRCE report. You should always run TRCE to verify
|
||||
your design.
|
||||
*****************************************************************
|
||||
|
||||
Start NBR special constraint process at 21:55:09 08/19/23
|
||||
|
||||
Start NBR section for initial routing at 21:55:10 08/19/23
|
||||
Level 1, iteration 1
|
||||
0(0.00%) conflict; 776(79.35%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 7.085ns/0.000ns; real time: 9 secs
|
||||
Level 2, iteration 1
|
||||
0(0.00%) conflict; 771(78.83%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 7.138ns/0.000ns; real time: 9 secs
|
||||
Level 3, iteration 1
|
||||
0(0.00%) conflict; 765(78.22%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 7.276ns/0.000ns; real time: 9 secs
|
||||
Level 4, iteration 1
|
||||
10(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 6.966ns/0.000ns; real time: 9 secs
|
||||
|
||||
Info: Initial congestion level at 75% usage is 0
|
||||
Info: Initial congestion area at 75% usage is 0 (0.00%)
|
||||
|
||||
Start NBR section for normal routing at 21:55:10 08/19/23
|
||||
Level 4, iteration 1
|
||||
3(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 6.966ns/0.000ns; real time: 9 secs
|
||||
Level 4, iteration 2
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 6.966ns/0.000ns; real time: 9 secs
|
||||
|
||||
Start NBR section for setup/hold timing optimization with effort level 3 at 21:55:10 08/19/23
|
||||
|
||||
Start NBR section for re-routing at 21:55:10 08/19/23
|
||||
Level 4, iteration 1
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 6.966ns/0.000ns; real time: 9 secs
|
||||
|
||||
Start NBR section for post-routing at 21:55:10 08/19/23
|
||||
|
||||
End NBR router with 0 unrouted connection
|
||||
|
||||
NBR Summary
|
||||
-----------
|
||||
Number of unrouted connections : 0 (0.00%)
|
||||
Number of connections with timing violations : 0 (0.00%)
|
||||
Estimated worst slack<setup> : 6.966ns
|
||||
Timing score<setup> : 0
|
||||
-----------
|
||||
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
|
||||
|
||||
|
||||
|
||||
Total CPU time 9 secs
|
||||
Total REAL time: 9 secs
|
||||
Completely routed.
|
||||
End of route. 978 routed (100.00%); 0 unrouted.
|
||||
|
||||
Hold time timing score: 0, hold timing errors: 0
|
||||
|
||||
Timing score: 0
|
||||
|
||||
Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd.
|
||||
|
||||
|
||||
All signals are completely routed.
|
||||
|
||||
|
||||
PAR_SUMMARY::Run status = Completed
|
||||
PAR_SUMMARY::Number of unrouted conns = 0
|
||||
PAR_SUMMARY::Worst slack<setup/<ns>> = 6.966
|
||||
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
|
||||
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.304
|
||||
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
|
||||
PAR_SUMMARY::Number of errors = 0
|
||||
|
||||
Total CPU time to completion: 9 secs
|
||||
Total REAL time to completion: 10 secs
|
||||
|
||||
par done!
|
||||
|
||||
Note: user must run 'Trace' for timing closure signoff.
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
|
@ -1,42 +0,0 @@
|
|||
[ActiveSupport PAR]
|
||||
; Global primary clocks
|
||||
GLOBAL_PRIMARY_USED = 3;
|
||||
; Global primary clock #0
|
||||
GLOBAL_PRIMARY_0_SIGNALNAME = RCLK_c;
|
||||
GLOBAL_PRIMARY_0_DRIVERTYPE = PIO;
|
||||
GLOBAL_PRIMARY_0_LOADNUM = 47;
|
||||
; Global primary clock #1
|
||||
GLOBAL_PRIMARY_1_SIGNALNAME = PHI2_c;
|
||||
GLOBAL_PRIMARY_1_DRIVERTYPE = PIO;
|
||||
GLOBAL_PRIMARY_1_LOADNUM = 21;
|
||||
; Global primary clock #2
|
||||
GLOBAL_PRIMARY_2_SIGNALNAME = nCRAS_c;
|
||||
GLOBAL_PRIMARY_2_DRIVERTYPE = PIO;
|
||||
GLOBAL_PRIMARY_2_LOADNUM = 10;
|
||||
; # of global secondary clocks
|
||||
GLOBAL_SECONDARY_USED = 1;
|
||||
; Global secondary clock #0
|
||||
GLOBAL_SECONDARY_0_SIGNALNAME = nCCAS_c;
|
||||
GLOBAL_SECONDARY_0_DRIVERTYPE = PIO;
|
||||
GLOBAL_SECONDARY_0_LOADNUM = 10;
|
||||
GLOBAL_SECONDARY_0_SIGTYPE = CLK;
|
||||
; I/O Bank 0 Usage
|
||||
BANK_0_USED = 13;
|
||||
BANK_0_AVAIL = 19;
|
||||
BANK_0_VCCIO = 3.3V;
|
||||
BANK_0_VREF1 = NA;
|
||||
; I/O Bank 1 Usage
|
||||
BANK_1_USED = 20;
|
||||
BANK_1_AVAIL = 20;
|
||||
BANK_1_VCCIO = 3.3V;
|
||||
BANK_1_VREF1 = NA;
|
||||
; I/O Bank 2 Usage
|
||||
BANK_2_USED = 12;
|
||||
BANK_2_AVAIL = 20;
|
||||
BANK_2_VCCIO = 3.3V;
|
||||
BANK_2_VREF1 = NA;
|
||||
; I/O Bank 3 Usage
|
||||
BANK_3_USED = 18;
|
||||
BANK_3_AVAIL = 20;
|
||||
BANK_3_VCCIO = 3.3V;
|
||||
BANK_3_VREF1 = NA;
|
||||
|
|
@ -1,27 +0,0 @@
|
|||
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Sat Aug 19 21:55:01 2023
|
||||
|
||||
C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f LCMXO2_640HC_impl1.p2t
|
||||
LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir LCMXO2_640HC_impl1.prf -gui
|
||||
-msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
|
||||
|
||||
|
||||
Preference file: LCMXO2_640HC_impl1.prf.
|
||||
|
||||
Level/ Number Worst Timing Worst Timing Run NCD
|
||||
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
|
||||
---------- -------- ----- ------ ----------- ----------- ---- ------
|
||||
5_1 * 0 6.966 0 0.304 0 10 Completed
|
||||
|
||||
* : Design saved.
|
||||
|
||||
Total (real) run time for 1-seed: 10 secs
|
||||
|
||||
par done!
|
||||
|
||||
Note: user must run 'Trace' for timing closure signoff.
|
||||
|
|
@ -1 +0,0 @@
|
|||
DRC detected 0 errors and 0 warnings.
|
||||
|
|
@ -1,9 +0,0 @@
|
|||
<html>
|
||||
<head>
|
||||
<title>syntmp/LCMXO2_640HC_impl1_srr.htm log file</title>
|
||||
</head>
|
||||
<frameset cols="20%, 80%">
|
||||
<frame src="syntmp/LCMXO2_640HC_impl1_toc.htm" name="tocFrame" />
|
||||
<frame src="syntmp/LCMXO2_640HC_impl1_srr.htm" name="srrFrame"/>
|
||||
</frameset>
|
||||
</html>
|
||||
|
|
@ -1,4 +0,0 @@
|
|||
---- MParTrce Tool Log File ----
|
||||
|
||||
==== Par Standard Out ====
|
||||
==== End of Par Standard Out ====
|
||||
|
|
@ -1,9 +0,0 @@
|
|||
-v
|
||||
1
|
||||
|
||||
|
||||
-gt
|
||||
|
||||
|
||||
-mapchkpnt 0
|
||||
-sethld
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -1,9 +0,0 @@
|
|||
-w
|
||||
-l 5
|
||||
-i 6
|
||||
-n 1
|
||||
-t 1
|
||||
-s 1
|
||||
-c 0
|
||||
-e 0
|
||||
-exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1
|
||||
|
|
@ -1,5 +0,0 @@
|
|||
-rem
|
||||
-distrce
|
||||
-log "LCMXO2_640HC_impl1.log"
|
||||
-o "LCMXO2_640HC_impl1.csv"
|
||||
-pr "LCMXO2_640HC_impl1.prf"
|
||||
|
|
@ -1,273 +0,0 @@
|
|||
PAD Specification File
|
||||
***************************
|
||||
|
||||
PART TYPE: LCMXO2-640HC
|
||||
Performance Grade: 4
|
||||
PACKAGE: TQFP100
|
||||
Package Status: Final Version 1.39
|
||||
|
||||
Sat Aug 19 21:55:06 2023
|
||||
|
||||
Pinout by Port Name:
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties |
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
| CROW[0] | 10/3 | LVCMOS33_IN | PL3D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| CROW[1] | 16/3 | LVCMOS33_IN | PL6A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[0] | 3/3 | LVCMOS33_IN | PL2C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[1] | 96/0 | LVCMOS33_IN | PT6D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[2] | 88/0 | LVCMOS33_IN | PT9A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[3] | 97/0 | LVCMOS33_IN | PT6C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[4] | 99/0 | LVCMOS33_IN | PT6A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[5] | 98/0 | LVCMOS33_IN | PT6B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[6] | 2/3 | LVCMOS33_IN | PL2B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Din[7] | 1/3 | LVCMOS33_IN | PL2A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| Dout[0] | 76/0 | LVCMOS33_OUT | PT11D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| Dout[1] | 86/0 | LVCMOS33_OUT | PT9C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| Dout[2] | 87/0 | LVCMOS33_OUT | PT9B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| Dout[3] | 85/0 | LVCMOS33_OUT | PT9D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| Dout[4] | 83/0 | LVCMOS33_OUT | PT10B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| Dout[5] | 84/0 | LVCMOS33_OUT | PT10A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| Dout[6] | 78/0 | LVCMOS33_OUT | PT11A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| Dout[7] | 82/0 | LVCMOS33_OUT | PT10C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| LED | 34/2 | LVCMOS33_OUT | PB6C | | | DRIVE:24mA PULL:KEEPER SLEW:SLOW |
|
||||
| MAin[0] | 14/3 | LVCMOS33_IN | PL5C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[1] | 12/3 | LVCMOS33_IN | PL5A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[2] | 13/3 | LVCMOS33_IN | PL5B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[3] | 21/3 | LVCMOS33_IN | PL7B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[4] | 20/3 | LVCMOS33_IN | PL7A | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[5] | 19/3 | LVCMOS33_IN | PL6D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[6] | 24/3 | LVCMOS33_IN | PL7C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[7] | 18/3 | LVCMOS33_IN | PL6C | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[8] | 25/3 | LVCMOS33_IN | PL7D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| MAin[9] | 32/2 | LVCMOS33_IN | PB6B | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| PHI2 | 8/3 | LVCMOS33_IN | PL3B | | | PULL:DOWN CLAMP:ON HYSTERESIS:SMALL |
|
||||
| RA[0] | 66/1 | LVCMOS33_OUT | PR3D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[10] | 64/1 | LVCMOS33_OUT | PR5B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[11] | 59/1 | LVCMOS33_OUT | PR6B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[1] | 67/1 | LVCMOS33_OUT | PR3C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[2] | 69/1 | LVCMOS33_OUT | PR3A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[3] | 71/1 | LVCMOS33_OUT | PR2C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[4] | 74/1 | LVCMOS33_OUT | PR2B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[5] | 70/1 | LVCMOS33_OUT | PR2D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[6] | 68/1 | LVCMOS33_OUT | PR3B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[7] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RA[9] | 63/1 | LVCMOS33_OUT | PR5C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RBA[0] | 58/1 | LVCMOS33_OUT | PR6C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RBA[1] | 60/1 | LVCMOS33_OUT | PR6A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RCKE | 53/1 | LVCMOS33_OUT | PR7B | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RCLK | 62/1 | LVCMOS33_IN | PR5D | | | PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL |
|
||||
| RDQMH | 51/1 | LVCMOS33_OUT | PR7D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RDQML | 48/2 | LVCMOS33_OUT | PB14C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| RD[0] | 36/2 | LVCMOS33_BIDI | PB10A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[1] | 37/2 | LVCMOS33_BIDI | PB10B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[2] | 38/2 | LVCMOS33_BIDI | PB10C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[3] | 39/2 | LVCMOS33_BIDI | PB10D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[4] | 40/2 | LVCMOS33_BIDI | PB12A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[5] | 41/2 | LVCMOS33_BIDI | PB12B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[6] | 42/2 | LVCMOS33_BIDI | PB12C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| RD[7] | 43/2 | LVCMOS33_BIDI | PB12D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
| nCCAS | 9/3 | LVCMOS33_IN | PL3C | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nCRAS | 17/3 | LVCMOS33_IN | PL6B | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nFWE | 15/3 | LVCMOS33_IN | PL5D | | | PULL:UP CLAMP:ON HYSTERESIS:SMALL |
|
||||
| nRCAS | 52/1 | LVCMOS33_OUT | PR7C | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| nRCS | 57/1 | LVCMOS33_OUT | PR6D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| nRRAS | 54/1 | LVCMOS33_OUT | PR7A | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
| nRWE | 49/2 | LVCMOS33_OUT | PB14D | | | DRIVE:4mA PULL:KEEPER SLEW:SLOW |
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
|
||||
Vccio by Bank:
|
||||
+------+-------+
|
||||
| Bank | Vccio |
|
||||
+------+-------+
|
||||
| 0 | 3.3V |
|
||||
| 1 | 3.3V |
|
||||
| 2 | 3.3V |
|
||||
| 3 | 3.3V |
|
||||
+------+-------+
|
||||
|
||||
Vref by Bank:
|
||||
+------+-----+-----------------+---------+
|
||||
| Vref | Pin | Bank # / Vref # | Load(s) |
|
||||
+------+-----+-----------------+---------+
|
||||
+------+-----+-----------------+---------+
|
||||
|
||||
Pinout by Pin Number:
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable |
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
| 1/3 | Din[7] | LOCATED | LVCMOS33_IN | PL2A | | | |
|
||||
| 2/3 | Din[6] | LOCATED | LVCMOS33_IN | PL2B | | | |
|
||||
| 3/3 | Din[0] | LOCATED | LVCMOS33_IN | PL2C | PCLKT3_2 | | |
|
||||
| 4/3 | unused, PULL:DOWN | | | PL2D | PCLKC3_2 | | |
|
||||
| 7/3 | unused, PULL:DOWN | | | PL3A | | | |
|
||||
| 8/3 | PHI2 | LOCATED | LVCMOS33_IN | PL3B | | | |
|
||||
| 9/3 | nCCAS | LOCATED | LVCMOS33_IN | PL3C | | | |
|
||||
| 10/3 | CROW[0] | LOCATED | LVCMOS33_IN | PL3D | | | |
|
||||
| 12/3 | MAin[1] | LOCATED | LVCMOS33_IN | PL5A | PCLKT3_1 | | |
|
||||
| 13/3 | MAin[2] | LOCATED | LVCMOS33_IN | PL5B | PCLKC3_1 | | |
|
||||
| 14/3 | MAin[0] | LOCATED | LVCMOS33_IN | PL5C | | | |
|
||||
| 15/3 | nFWE | LOCATED | LVCMOS33_IN | PL5D | | | |
|
||||
| 16/3 | CROW[1] | LOCATED | LVCMOS33_IN | PL6A | | | |
|
||||
| 17/3 | nCRAS | LOCATED | LVCMOS33_IN | PL6B | | | |
|
||||
| 18/3 | MAin[7] | LOCATED | LVCMOS33_IN | PL6C | | | |
|
||||
| 19/3 | MAin[5] | LOCATED | LVCMOS33_IN | PL6D | | | |
|
||||
| 20/3 | MAin[4] | LOCATED | LVCMOS33_IN | PL7A | PCLKT3_0 | | |
|
||||
| 21/3 | MAin[3] | LOCATED | LVCMOS33_IN | PL7B | PCLKC3_0 | | |
|
||||
| 24/3 | MAin[6] | LOCATED | LVCMOS33_IN | PL7C | | | |
|
||||
| 25/3 | MAin[8] | LOCATED | LVCMOS33_IN | PL7D | | | |
|
||||
| 27/2 | unused, PULL:DOWN | | | PB4A | CSSPIN | | |
|
||||
| 28/2 | unused, PULL:DOWN | | | PB4B | | | |
|
||||
| 29/2 | unused, PULL:DOWN | | | PB4C | | | |
|
||||
| 30/2 | unused, PULL:DOWN | | | PB4D | | | |
|
||||
| 31/2 | unused, PULL:DOWN | | | PB6A | MCLK/CCLK | | |
|
||||
| 32/2 | MAin[9] | LOCATED | LVCMOS33_IN | PB6B | SO/SPISO | | |
|
||||
| 34/2 | LED | LOCATED | LVCMOS33_OUT | PB6C | PCLKT2_0 | | |
|
||||
| 35/2 | unused, PULL:DOWN | | | PB6D | PCLKC2_0 | | |
|
||||
| 36/2 | RD[0] | LOCATED | LVCMOS33_BIDI | PB10A | | | |
|
||||
| 37/2 | RD[1] | LOCATED | LVCMOS33_BIDI | PB10B | | | |
|
||||
| 38/2 | RD[2] | LOCATED | LVCMOS33_BIDI | PB10C | PCLKT2_1 | | |
|
||||
| 39/2 | RD[3] | LOCATED | LVCMOS33_BIDI | PB10D | PCLKC2_1 | | |
|
||||
| 40/2 | RD[4] | LOCATED | LVCMOS33_BIDI | PB12A | | | |
|
||||
| 41/2 | RD[5] | LOCATED | LVCMOS33_BIDI | PB12B | | | |
|
||||
| 42/2 | RD[6] | LOCATED | LVCMOS33_BIDI | PB12C | | | |
|
||||
| 43/2 | RD[7] | LOCATED | LVCMOS33_BIDI | PB12D | | | |
|
||||
| 45/2 | unused, PULL:DOWN | | | PB14A | | | |
|
||||
| 47/2 | unused, PULL:DOWN | | | PB14B | | | |
|
||||
| 48/2 | RDQML | LOCATED | LVCMOS33_OUT | PB14C | SN | | |
|
||||
| 49/2 | nRWE | LOCATED | LVCMOS33_OUT | PB14D | SI/SISPI | | |
|
||||
| 51/1 | RDQMH | LOCATED | LVCMOS33_OUT | PR7D | | | |
|
||||
| 52/1 | nRCAS | LOCATED | LVCMOS33_OUT | PR7C | | | |
|
||||
| 53/1 | RCKE | LOCATED | LVCMOS33_OUT | PR7B | | | |
|
||||
| 54/1 | nRRAS | LOCATED | LVCMOS33_OUT | PR7A | | | |
|
||||
| 57/1 | nRCS | LOCATED | LVCMOS33_OUT | PR6D | | | |
|
||||
| 58/1 | RBA[0] | LOCATED | LVCMOS33_OUT | PR6C | | | |
|
||||
| 59/1 | RA[11] | LOCATED | LVCMOS33_OUT | PR6B | | | |
|
||||
| 60/1 | RBA[1] | LOCATED | LVCMOS33_OUT | PR6A | | | |
|
||||
| 62/1 | RCLK | LOCATED | LVCMOS33_IN | PR5D | PCLKC1_0 | | |
|
||||
| 63/1 | RA[9] | LOCATED | LVCMOS33_OUT | PR5C | PCLKT1_0 | | |
|
||||
| 64/1 | RA[10] | LOCATED | LVCMOS33_OUT | PR5B | | | |
|
||||
| 65/1 | RA[8] | LOCATED | LVCMOS33_OUT | PR5A | | | |
|
||||
| 66/1 | RA[0] | LOCATED | LVCMOS33_OUT | PR3D | | | |
|
||||
| 67/1 | RA[1] | LOCATED | LVCMOS33_OUT | PR3C | | | |
|
||||
| 68/1 | RA[6] | LOCATED | LVCMOS33_OUT | PR3B | | | |
|
||||
| 69/1 | RA[2] | LOCATED | LVCMOS33_OUT | PR3A | | | |
|
||||
| 70/1 | RA[5] | LOCATED | LVCMOS33_OUT | PR2D | | | |
|
||||
| 71/1 | RA[3] | LOCATED | LVCMOS33_OUT | PR2C | | | |
|
||||
| 74/1 | RA[4] | LOCATED | LVCMOS33_OUT | PR2B | | | |
|
||||
| 75/1 | RA[7] | LOCATED | LVCMOS33_OUT | PR2A | | | |
|
||||
| 76/0 | Dout[0] | LOCATED | LVCMOS33_OUT | PT11D | DONE | | |
|
||||
| 77/0 | unused, PULL:DOWN | | | PT11C | INITN | | |
|
||||
| 78/0 | Dout[6] | LOCATED | LVCMOS33_OUT | PT11A | | | |
|
||||
| 81/0 | unused, PULL:DOWN | | | PT10D | PROGRAMN | | |
|
||||
| 82/0 | Dout[7] | LOCATED | LVCMOS33_OUT | PT10C | JTAGENB | | |
|
||||
| 83/0 | Dout[4] | LOCATED | LVCMOS33_OUT | PT10B | | | |
|
||||
| 84/0 | Dout[5] | LOCATED | LVCMOS33_OUT | PT10A | | | |
|
||||
| 85/0 | Dout[3] | LOCATED | LVCMOS33_OUT | PT9D | SDA/PCLKC0_0 | | |
|
||||
| 86/0 | Dout[1] | LOCATED | LVCMOS33_OUT | PT9C | SCL/PCLKT0_0 | | |
|
||||
| 87/0 | Dout[2] | LOCATED | LVCMOS33_OUT | PT9B | PCLKC0_1 | | |
|
||||
| 88/0 | Din[2] | LOCATED | LVCMOS33_IN | PT9A | PCLKT0_1 | | |
|
||||
| 90/0 | Reserved: sysCONFIG | | | PT7D | TMS | | |
|
||||
| 91/0 | Reserved: sysCONFIG | | | PT7C | TCK | | |
|
||||
| 94/0 | Reserved: sysCONFIG | | | PT7B | TDI | | |
|
||||
| 95/0 | Reserved: sysCONFIG | | | PT7A | TDO | | |
|
||||
| 96/0 | Din[1] | LOCATED | LVCMOS33_IN | PT6D | | | |
|
||||
| 97/0 | Din[3] | LOCATED | LVCMOS33_IN | PT6C | | | |
|
||||
| 98/0 | Din[5] | LOCATED | LVCMOS33_IN | PT6B | | | |
|
||||
| 99/0 | Din[4] | LOCATED | LVCMOS33_IN | PT6A | | | |
|
||||
| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | |
|
||||
+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
|
||||
|
||||
sysCONFIG Pins:
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode |
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
| PT7D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP |
|
||||
| PT7C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down |
|
||||
| PT7B | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP |
|
||||
| PT7A | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP |
|
||||
+----------+--------------------+--------------------+----------+-------------+-------------------+
|
||||
|
||||
Dedicated sysCONFIG Pins:
|
||||
|
||||
|
||||
List of All Pins' Locate Preferences Based on Final Placement After PAR
|
||||
to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste):
|
||||
|
||||
LOCATE COMP "CROW[0]" SITE "10";
|
||||
LOCATE COMP "CROW[1]" SITE "16";
|
||||
LOCATE COMP "Din[0]" SITE "3";
|
||||
LOCATE COMP "Din[1]" SITE "96";
|
||||
LOCATE COMP "Din[2]" SITE "88";
|
||||
LOCATE COMP "Din[3]" SITE "97";
|
||||
LOCATE COMP "Din[4]" SITE "99";
|
||||
LOCATE COMP "Din[5]" SITE "98";
|
||||
LOCATE COMP "Din[6]" SITE "2";
|
||||
LOCATE COMP "Din[7]" SITE "1";
|
||||
LOCATE COMP "Dout[0]" SITE "76";
|
||||
LOCATE COMP "Dout[1]" SITE "86";
|
||||
LOCATE COMP "Dout[2]" SITE "87";
|
||||
LOCATE COMP "Dout[3]" SITE "85";
|
||||
LOCATE COMP "Dout[4]" SITE "83";
|
||||
LOCATE COMP "Dout[5]" SITE "84";
|
||||
LOCATE COMP "Dout[6]" SITE "78";
|
||||
LOCATE COMP "Dout[7]" SITE "82";
|
||||
LOCATE COMP "LED" SITE "34";
|
||||
LOCATE COMP "MAin[0]" SITE "14";
|
||||
LOCATE COMP "MAin[1]" SITE "12";
|
||||
LOCATE COMP "MAin[2]" SITE "13";
|
||||
LOCATE COMP "MAin[3]" SITE "21";
|
||||
LOCATE COMP "MAin[4]" SITE "20";
|
||||
LOCATE COMP "MAin[5]" SITE "19";
|
||||
LOCATE COMP "MAin[6]" SITE "24";
|
||||
LOCATE COMP "MAin[7]" SITE "18";
|
||||
LOCATE COMP "MAin[8]" SITE "25";
|
||||
LOCATE COMP "MAin[9]" SITE "32";
|
||||
LOCATE COMP "PHI2" SITE "8";
|
||||
LOCATE COMP "RA[0]" SITE "66";
|
||||
LOCATE COMP "RA[10]" SITE "64";
|
||||
LOCATE COMP "RA[11]" SITE "59";
|
||||
LOCATE COMP "RA[1]" SITE "67";
|
||||
LOCATE COMP "RA[2]" SITE "69";
|
||||
LOCATE COMP "RA[3]" SITE "71";
|
||||
LOCATE COMP "RA[4]" SITE "74";
|
||||
LOCATE COMP "RA[5]" SITE "70";
|
||||
LOCATE COMP "RA[6]" SITE "68";
|
||||
LOCATE COMP "RA[7]" SITE "75";
|
||||
LOCATE COMP "RA[8]" SITE "65";
|
||||
LOCATE COMP "RA[9]" SITE "63";
|
||||
LOCATE COMP "RBA[0]" SITE "58";
|
||||
LOCATE COMP "RBA[1]" SITE "60";
|
||||
LOCATE COMP "RCKE" SITE "53";
|
||||
LOCATE COMP "RCLK" SITE "62";
|
||||
LOCATE COMP "RDQMH" SITE "51";
|
||||
LOCATE COMP "RDQML" SITE "48";
|
||||
LOCATE COMP "RD[0]" SITE "36";
|
||||
LOCATE COMP "RD[1]" SITE "37";
|
||||
LOCATE COMP "RD[2]" SITE "38";
|
||||
LOCATE COMP "RD[3]" SITE "39";
|
||||
LOCATE COMP "RD[4]" SITE "40";
|
||||
LOCATE COMP "RD[5]" SITE "41";
|
||||
LOCATE COMP "RD[6]" SITE "42";
|
||||
LOCATE COMP "RD[7]" SITE "43";
|
||||
LOCATE COMP "nCCAS" SITE "9";
|
||||
LOCATE COMP "nCRAS" SITE "17";
|
||||
LOCATE COMP "nFWE" SITE "15";
|
||||
LOCATE COMP "nRCAS" SITE "52";
|
||||
LOCATE COMP "nRCS" SITE "57";
|
||||
LOCATE COMP "nRRAS" SITE "54";
|
||||
LOCATE COMP "nRWE" SITE "49";
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Sat Aug 19 21:55:09 2023
|
||||
|
||||
|
|
@ -1,243 +0,0 @@
|
|||
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Sat Aug 19 21:55:01 2023
|
||||
|
||||
C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f LCMXO2_640HC_impl1.p2t
|
||||
LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir LCMXO2_640HC_impl1.prf -gui
|
||||
-msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
|
||||
|
||||
|
||||
Preference file: LCMXO2_640HC_impl1.prf.
|
||||
|
||||
Level/ Number Worst Timing Worst Timing Run NCD
|
||||
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
|
||||
---------- -------- ----- ------ ----------- ----------- ---- ------
|
||||
5_1 * 0 6.966 0 0.304 0 10 Completed
|
||||
|
||||
* : Design saved.
|
||||
|
||||
Total (real) run time for 1-seed: 10 secs
|
||||
|
||||
par done!
|
||||
|
||||
Note: user must run 'Trace' for timing closure signoff.
|
||||
|
||||
Lattice Place and Route Report for Design "LCMXO2_640HC_impl1_map.ncd"
|
||||
Sat Aug 19 21:55:01 2023
|
||||
|
||||
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
|
||||
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 LCMXO2_640HC_impl1_map.ncd LCMXO2_640HC_impl1.dir/5_1.ncd LCMXO2_640HC_impl1.prf
|
||||
Preference file: LCMXO2_640HC_impl1.prf.
|
||||
Placement level-cost: 5-1.
|
||||
Routing Iterations: 6
|
||||
|
||||
Loading design for application par from file LCMXO2_640HC_impl1_map.ncd.
|
||||
Design name: RAM2GS
|
||||
NCD version: 3.3
|
||||
Vendor: LATTICE
|
||||
Device: LCMXO2-640HC
|
||||
Package: TQFP100
|
||||
Performance: 4
|
||||
Loading device for application par from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
|
||||
Package Status: Final Version 1.39.
|
||||
Performance Hardware Data Status: Final Version 34.4.
|
||||
License checked out.
|
||||
|
||||
|
||||
Ignore Preference Error(s): True
|
||||
Device utilization summary:
|
||||
|
||||
PIO (prelim) 63+4(JTAG)/80 84% used
|
||||
63+4(JTAG)/79 85% bonded
|
||||
IOLOGIC 25/80 31% used
|
||||
|
||||
SLICE 113/320 35% used
|
||||
|
||||
EFB 1/1 100% used
|
||||
|
||||
|
||||
Number of Signals: 374
|
||||
Number of Connections: 978
|
||||
|
||||
Pin Constraint Summary:
|
||||
63 out of 63 pins locked (100% locked).
|
||||
|
||||
The following 3 signals are selected to use the primary clock routing resources:
|
||||
RCLK_c (driver: RCLK, clk load #: 47)
|
||||
PHI2_c (driver: PHI2, clk load #: 21)
|
||||
nCRAS_c (driver: nCRAS, clk load #: 10)
|
||||
|
||||
WARNING - par: Signal "RCLK_c" is selected to use Primary clock resources. However, its driver comp "RCLK" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
WARNING - par: Signal "nCRAS_c" is selected to use Primary clock resources. However, its driver comp "nCRAS" is located at "17", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
|
||||
The following 1 signal is selected to use the secondary clock routing resources:
|
||||
nCCAS_c (driver: nCCAS, clk load #: 8, sr load #: 0, ce load #: 0)
|
||||
|
||||
WARNING - par: Signal "nCCAS_c" is selected to use Secondary clock resources. However, its driver comp "nCCAS" is located at "9", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
No signal is selected as Global Set/Reset.
|
||||
Starting Placer Phase 0.
|
||||
............
|
||||
Finished Placer Phase 0. REAL time: 0 secs
|
||||
|
||||
Starting Placer Phase 1.
|
||||
....................
|
||||
Placer score = 53481.
|
||||
Finished Placer Phase 1. REAL time: 5 secs
|
||||
|
||||
Starting Placer Phase 2.
|
||||
.
|
||||
Placer score = 53406
|
||||
Finished Placer Phase 2. REAL time: 5 secs
|
||||
|
||||
|
||||
------------------ Clock Report ------------------
|
||||
|
||||
Global Clock Resources:
|
||||
CLK_PIN : 0 out of 8 (0%)
|
||||
General PIO: 4 out of 80 (5%)
|
||||
DCM : 0 out of 2 (0%)
|
||||
DCC : 0 out of 8 (0%)
|
||||
|
||||
Global Clocks:
|
||||
PRIMARY "RCLK_c" from comp "RCLK" on PIO site "62 (PR5D)", clk load = 47
|
||||
PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 21
|
||||
PRIMARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 10
|
||||
SECONDARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 8, ce load = 0, sr load = 0
|
||||
|
||||
PRIMARY : 3 out of 8 (37%)
|
||||
SECONDARY: 1 out of 8 (12%)
|
||||
|
||||
--------------- End of Clock Report ---------------
|
||||
|
||||
|
||||
I/O Usage Summary (final):
|
||||
63 + 4(JTAG) out of 80 (83.8%) PIO sites used.
|
||||
63 + 4(JTAG) out of 79 (84.8%) bonded PIO sites used.
|
||||
Number of PIO comps: 63; differential: 0.
|
||||
Number of Vref pins used: 0.
|
||||
|
||||
I/O Bank Usage Summary:
|
||||
+----------+----------------+------------+-----------+
|
||||
| I/O Bank | Usage | Bank Vccio | Bank Vref |
|
||||
+----------+----------------+------------+-----------+
|
||||
| 0 | 13 / 19 ( 68%) | 3.3V | - |
|
||||
| 1 | 20 / 20 (100%) | 3.3V | - |
|
||||
| 2 | 12 / 20 ( 60%) | 3.3V | - |
|
||||
| 3 | 18 / 20 ( 90%) | 3.3V | - |
|
||||
+----------+----------------+------------+-----------+
|
||||
|
||||
Total placer CPU time: 5 secs
|
||||
|
||||
Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd.
|
||||
|
||||
0 connections routed; 978 unrouted.
|
||||
Starting router resource preassignment
|
||||
WARNING - par: The driver of primary clock net RCLK_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
|
||||
WARNING - par: The driver of primary clock net nCRAS_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
|
||||
|
||||
Completed router resource preassignment. Real time: 8 secs
|
||||
|
||||
Start NBR router at 21:55:09 08/19/23
|
||||
|
||||
*****************************************************************
|
||||
Info: NBR allows conflicts(one node used by more than one signal)
|
||||
in the earlier iterations. In each iteration, it tries to
|
||||
solve the conflicts while keeping the critical connections
|
||||
routed as short as possible. The routing process is said to
|
||||
be completed when no conflicts exist and all connections
|
||||
are routed.
|
||||
Note: NBR uses a different method to calculate timing slacks. The
|
||||
worst slack and total negative slack may not be the same as
|
||||
that in TRCE report. You should always run TRCE to verify
|
||||
your design.
|
||||
*****************************************************************
|
||||
|
||||
Start NBR special constraint process at 21:55:09 08/19/23
|
||||
|
||||
Start NBR section for initial routing at 21:55:10 08/19/23
|
||||
Level 1, iteration 1
|
||||
0(0.00%) conflict; 776(79.35%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 7.085ns/0.000ns; real time: 9 secs
|
||||
Level 2, iteration 1
|
||||
0(0.00%) conflict; 771(78.83%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 7.138ns/0.000ns; real time: 9 secs
|
||||
Level 3, iteration 1
|
||||
0(0.00%) conflict; 765(78.22%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 7.276ns/0.000ns; real time: 9 secs
|
||||
Level 4, iteration 1
|
||||
10(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 6.966ns/0.000ns; real time: 9 secs
|
||||
|
||||
Info: Initial congestion level at 75% usage is 0
|
||||
Info: Initial congestion area at 75% usage is 0 (0.00%)
|
||||
|
||||
Start NBR section for normal routing at 21:55:10 08/19/23
|
||||
Level 4, iteration 1
|
||||
3(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 6.966ns/0.000ns; real time: 9 secs
|
||||
Level 4, iteration 2
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 6.966ns/0.000ns; real time: 9 secs
|
||||
|
||||
Start NBR section for setup/hold timing optimization with effort level 3 at 21:55:10 08/19/23
|
||||
|
||||
Start NBR section for re-routing at 21:55:10 08/19/23
|
||||
Level 4, iteration 1
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 6.966ns/0.000ns; real time: 9 secs
|
||||
|
||||
Start NBR section for post-routing at 21:55:10 08/19/23
|
||||
|
||||
End NBR router with 0 unrouted connection
|
||||
|
||||
NBR Summary
|
||||
-----------
|
||||
Number of unrouted connections : 0 (0.00%)
|
||||
Number of connections with timing violations : 0 (0.00%)
|
||||
Estimated worst slack<setup> : 6.966ns
|
||||
Timing score<setup> : 0
|
||||
-----------
|
||||
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
|
||||
|
||||
|
||||
|
||||
Total CPU time 9 secs
|
||||
Total REAL time: 9 secs
|
||||
Completely routed.
|
||||
End of route. 978 routed (100.00%); 0 unrouted.
|
||||
|
||||
Hold time timing score: 0, hold timing errors: 0
|
||||
|
||||
Timing score: 0
|
||||
|
||||
Dumping design to file LCMXO2_640HC_impl1.dir/5_1.ncd.
|
||||
|
||||
|
||||
All signals are completely routed.
|
||||
|
||||
|
||||
PAR_SUMMARY::Run status = Completed
|
||||
PAR_SUMMARY::Number of unrouted conns = 0
|
||||
PAR_SUMMARY::Worst slack<setup/<ns>> = 6.966
|
||||
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
|
||||
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.304
|
||||
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
|
||||
PAR_SUMMARY::Number of errors = 0
|
||||
|
||||
Total CPU time to completion: 9 secs
|
||||
Total REAL time to completion: 10 secs
|
||||
|
||||
par done!
|
||||
|
||||
Note: user must run 'Trace' for timing closure signoff.
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
|
@ -1,10 +0,0 @@
|
|||
-v
|
||||
10
|
||||
|
||||
|
||||
|
||||
|
||||
-gt
|
||||
-sethld
|
||||
-sp 4
|
||||
-sphld m
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -1,5 +0,0 @@
|
|||
|
||||
|
||||
-g RamCfg:Reset
|
||||
|
||||
-path "Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC"
|
||||
File diff suppressed because it is too large
Load Diff
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Reference in New Issue