Merge branch 'RC-GW4201D' into release-GW4201D
This commit is contained in:
commit
a385e3b51f
|
@ -1,20 +1,7 @@
|
|||
# For PCBs designed using KiCad: http://www.kicad-pcb.org/
|
||||
# Format documentation: http://kicad-pcb.org/help/file-formats/
|
||||
|
||||
# Temporary files
|
||||
*.000
|
||||
*.bak
|
||||
*.bck
|
||||
*.kicad_pcb-bak
|
||||
*.sch-bak
|
||||
*~
|
||||
_autosave-*
|
||||
*.tmp
|
||||
*-rescue.lib
|
||||
*-save.pro
|
||||
*-save.kicad_pcb
|
||||
fp-info-cache
|
||||
# KiCAD
|
||||
*.kicad_prl
|
||||
Hardware/*/*-backups
|
||||
fp-info-cache
|
||||
|
||||
|
||||
# Mac
|
||||
|
|
|
@ -0,0 +1 @@
|
|||
VERSION=20110520
|
|
@ -0,0 +1,88 @@
|
|||
<HTML>
|
||||
<HEAD><TITLE>Lattice TCL Log</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="pn231117190458"></A><B><U><big>pn231117190458</big></U></B>
|
||||
#Start recording tcl command: 11/17/2023 18:14:50
|
||||
#Project Location: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC; Project name: RAM2GS_LCMXO2_1200HC
|
||||
prj_project open "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.ldf"
|
||||
#Stop recording: 11/17/2023 19:04:58
|
||||
|
||||
|
||||
|
||||
<A name="pn231118021829"></A><B><U><big>pn231118021829</big></U></B>
|
||||
#Start recording tcl command: 11/17/2023 20:00:00
|
||||
#Project Location: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC; Project name: RAM2GS_LCMXO2_1200HC
|
||||
prj_project open "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.ldf"
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
#Stop recording: 11/18/2023 02:18:29
|
||||
|
||||
|
||||
|
||||
<A name="pn231118021905"></A><B><U><big>pn231118021905</big></U></B>
|
||||
#Start recording tcl command: 11/18/2023 02:18:52
|
||||
#Project Location: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC; Project name: RAM2GS_LCMXO2_1200HC
|
||||
prj_project open "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/RAM2GS_LCMXO2_1200HC.ldf"
|
||||
prj_project close
|
||||
#Stop recording: 11/18/2023 02:19:05
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
|
@ -1,6 +1,6 @@
|
|||
NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
|
||||
NOTE All Rights Reserved *
|
||||
NOTE DATE CREATED: Thu Sep 21 05:40:22 2023 *
|
||||
NOTE DATE CREATED: Sat Nov 18 02:06:32 2023 *
|
||||
NOTE DESIGN NAME: RAM2GS *
|
||||
NOTE DEVICE NAME: LCMXO2-1200HC-4TQFP100 *
|
||||
NOTE PIN ASSIGNMENTS *
|
||||
|
@ -13,6 +13,7 @@ NOTE PINS nRCAS : 52 : out *
|
|||
NOTE PINS nRRAS : 54 : out *
|
||||
NOTE PINS nRWE : 49 : out *
|
||||
NOTE PINS RCKE : 53 : out *
|
||||
NOTE PINS RCLKout : 60 : out *
|
||||
NOTE PINS RCLK : 63 : in *
|
||||
NOTE PINS nRCS : 57 : out *
|
||||
NOTE PINS RD[7] : 43 : inout *
|
||||
|
@ -34,7 +35,7 @@ NOTE PINS RA[3] : 71 : out *
|
|||
NOTE PINS RA[2] : 69 : out *
|
||||
NOTE PINS RA[1] : 67 : out *
|
||||
NOTE PINS RA[0] : 66 : out *
|
||||
NOTE PINS RBA[1] : 60 : out *
|
||||
NOTE PINS RBA[1] : 47 : out *
|
||||
NOTE PINS RBA[0] : 58 : out *
|
||||
NOTE PINS LED : 34 : out *
|
||||
NOTE PINS nFWE : 15 : in *
|
||||
|
|
|
@ -3,7 +3,7 @@ Report for cell RAM2GS.verilog
|
|||
|
||||
Register bits: 109 of 1280 (9%)
|
||||
PIC Latch: 0
|
||||
I/O cells: 63
|
||||
I/O cells: 64
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
BB 8 100.0
|
||||
|
@ -17,19 +17,20 @@ I/O cells: 63
|
|||
IB 25 100.0
|
||||
IFS1P3DX 9 100.0
|
||||
INV 7 100.0
|
||||
OB 30 100.0
|
||||
OB 31 100.0
|
||||
ODDRXE 1 100.0
|
||||
OFS1P3BX 4 100.0
|
||||
OFS1P3DX 11 100.0
|
||||
OFS1P3JX 1 100.0
|
||||
ORCALUT4 213 100.0
|
||||
PFUMX 1 100.0
|
||||
ORCALUT4 212 100.0
|
||||
PFUMX 2 100.0
|
||||
PUR 1 100.0
|
||||
VHI 2 100.0
|
||||
VLO 2 100.0
|
||||
SUB MODULES
|
||||
REFB 1 100.0
|
||||
|
||||
TOTAL 411
|
||||
TOTAL 413
|
||||
----------------------------------------------------------------------
|
||||
Report for cell REFB.netlist
|
||||
Instance path: ufmefb
|
||||
|
|
|
@ -4,7 +4,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Thu Sep 21 05:40:18 2023
|
||||
Sat Nov 18 02:06:29 2023
|
||||
|
||||
|
||||
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC -w -jedec -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
|
||||
|
@ -82,5 +82,5 @@ Available General Purpose Flash Memory: 511 Pages (Page 0 to Page 510).
|
|||
Initialized UFM Pages: 321 Pages (Page 190 to Page 510).
|
||||
|
||||
Total CPU Time: 3 secs
|
||||
Total REAL Time: 4 secs
|
||||
Total REAL Time: 3 secs
|
||||
Peak Memory Usage: 274 MB
|
||||
|
|
Binary file not shown.
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
@ -15,7 +15,7 @@ Target Vendor: LATTICE
|
|||
Target Device: LCMXO2-1200HCTQFP100
|
||||
Target Performance: 4
|
||||
Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454
|
||||
Mapped on: 09/21/23 05:39:45
|
||||
Mapped on: 11/18/23 02:05:52
|
||||
|
||||
Design Summary
|
||||
--------------
|
||||
|
@ -27,12 +27,24 @@ Design Summary
|
|||
SLICEs as Logic/ROM: 120 out of 640 (19%)
|
||||
SLICEs as RAM: 0 out of 480 (0%)
|
||||
SLICEs as Carry: 10 out of 640 (2%)
|
||||
Number of LUT4s: 237 out of 1280 (19%)
|
||||
Number used as logic LUTs: 217
|
||||
Number of LUT4s: 238 out of 1280 (19%)
|
||||
Number used as logic LUTs: 218
|
||||
Number used as distributed RAM: 0
|
||||
Number used as ripple logic: 20
|
||||
Number used as shift registers: 0
|
||||
Number of PIO sites used: 63 + 4(JTAG) out of 80 (84%)
|
||||
Number of PIO sites used: 64 + 4(JTAG) out of 80 (85%)
|
||||
Number of IDDR/ODDR/TDDR cells used: 1 out of 240 (0%)
|
||||
Number of IDDR cells: 0
|
||||
Number of ODDR cells: 1
|
||||
Number of TDDR cells: 0
|
||||
Number of PIO using at least one IDDR/ODDR/TDDR: 1 (0 differential)
|
||||
Number of PIO using IDDR only: 0 (0 differential)
|
||||
Number of PIO using ODDR only: 1 (0 differential)
|
||||
Number of PIO using TDDR only: 0 (0 differential)
|
||||
Number of PIO using IDDR/ODDR: 0 (0 differential)
|
||||
Number of PIO using IDDR/TDDR: 0 (0 differential)
|
||||
Number of PIO using ODDR/TDDR: 0 (0 differential)
|
||||
Number of PIO using IDDR/ODDR/TDDR: 0 (0 differential)
|
||||
Number of block RAMs: 0 out of 7 (0%)
|
||||
Number of GSRs: 0 out of 1 (0%)
|
||||
EFB used : Yes
|
||||
|
@ -48,6 +60,16 @@ Design Summary
|
|||
Number of DCCA: 0 out of 8 (0%)
|
||||
Number of DCMA: 0 out of 2 (0%)
|
||||
Number of PLLs: 0 out of 1 (0%)
|
||||
|
||||
Page 1
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 11/18/23 02:05:52
|
||||
|
||||
Design Summary (cont)
|
||||
---------------------
|
||||
Number of DQSDLLs: 0 out of 2 (0%)
|
||||
Number of CLKDIVC: 0 out of 4 (0%)
|
||||
Number of ECLKSYNCA: 0 out of 4 (0%)
|
||||
|
@ -59,24 +81,14 @@ Design Summary
|
|||
ripple logic.
|
||||
Number of clocks: 4
|
||||
Net PHI2_c: 20 loads, 9 rising, 11 falling (Driver: PIO PHI2 )
|
||||
Net RCLK_c: 47 loads, 47 rising, 0 falling (Driver: PIO RCLK )
|
||||
|
||||
Page 1
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 09/21/23 05:39:45
|
||||
|
||||
Design Summary (cont)
|
||||
---------------------
|
||||
Net RCLK_c: 48 loads, 48 rising, 0 falling (Driver: PIO RCLK )
|
||||
Net nCRAS_c: 9 loads, 0 rising, 9 falling (Driver: PIO nCRAS )
|
||||
Net nCCAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCCAS )
|
||||
Number of Clock Enables: 5
|
||||
Net N_178: 1 loads, 1 LSLICEs
|
||||
Net wb_cyc_stb_2_sqmuxa_i_0_0: 1 loads, 1 LSLICEs
|
||||
Net XOR8MEG18: 5 loads, 5 LSLICEs
|
||||
Net N_360_i: 2 loads, 2 LSLICEs
|
||||
Net un1_wb_rst14_i_0: 9 loads, 9 LSLICEs
|
||||
Net N_126_i: 9 loads, 9 LSLICEs
|
||||
Net N_261_i: 2 loads, 2 LSLICEs
|
||||
Net CmdUFMData_1_sqmuxa: 1 loads, 1 LSLICEs
|
||||
Number of LSRs: 5
|
||||
Net RA10s_i: 1 loads, 0 LSLICEs
|
||||
|
@ -86,16 +98,16 @@ Design Summary (cont)
|
|||
Net RASr2: 2 loads, 2 LSLICEs
|
||||
Number of nets driven by tri-state buffers: 0
|
||||
Top 10 highest fanout non-clock nets:
|
||||
Net InitReady: 41 loads
|
||||
Net FS[11]: 23 loads
|
||||
Net InitReady: 40 loads
|
||||
Net FS[13]: 22 loads
|
||||
Net FS[10]: 21 loads
|
||||
Net FS[12]: 21 loads
|
||||
Net FS[9]: 20 loads
|
||||
Net FS[14]: 18 loads
|
||||
Net CO0: 15 loads
|
||||
Net FS[11]: 21 loads
|
||||
Net FS[12]: 19 loads
|
||||
Net FS[14]: 19 loads
|
||||
Net FS[10]: 18 loads
|
||||
Net FS[9]: 17 loads
|
||||
Net Ready: 14 loads
|
||||
Net Ready_fast: 14 loads
|
||||
Net N_214: 13 loads
|
||||
Net CO0: 12 loads
|
||||
|
||||
|
||||
|
||||
|
@ -114,6 +126,14 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
|||
Interface is disabled using Disable Configuration Interface command 0x26
|
||||
followed by Bypass command 0xFF.
|
||||
|
||||
|
||||
Page 2
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 11/18/23 02:05:52
|
||||
|
||||
IO (PIO) Attributes
|
||||
-------------------
|
||||
|
||||
|
@ -126,16 +146,6 @@ IO (PIO) Attributes
|
|||
| Dout[0] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| PHI2 | INPUT | LVCMOS33 | IN |
|
||||
|
||||
Page 2
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 09/21/23 05:39:45
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RDQML | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
@ -149,6 +159,8 @@ IO (PIO) Attributes (cont)
|
|||
+---------------------+-----------+-----------+------------+
|
||||
| RCKE | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RCLKout | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RCLK | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRCS | OUTPUT | LVCMOS33 | OUT |
|
||||
|
@ -180,6 +192,16 @@ IO (PIO) Attributes (cont)
|
|||
| RA[6] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[5] | OUTPUT | LVCMOS33 | |
|
||||
|
||||
Page 3
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 11/18/23 02:05:52
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[4] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
@ -192,16 +214,6 @@ IO (PIO) Attributes (cont)
|
|||
| RA[0] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RBA[1] | OUTPUT | LVCMOS33 | OUT |
|
||||
|
||||
Page 3
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 09/21/23 05:39:45
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RBA[0] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
@ -246,6 +258,16 @@ IO (PIO) Attributes (cont)
|
|||
| CROW[1] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| CROW[0] | INPUT | LVCMOS33 | |
|
||||
|
||||
Page 4
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 11/18/23 02:05:52
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[9] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
@ -258,16 +280,6 @@ IO (PIO) Attributes (cont)
|
|||
| MAin[5] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[4] | INPUT | LVCMOS33 | |
|
||||
|
||||
Page 4
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 09/21/23 05:39:45
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[3] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
@ -285,7 +297,6 @@ Block GSR_INST undriven or does not drive anything - clipped.
|
|||
Signal nCRAS_c_i was merged into signal nCRAS_c
|
||||
Signal RASr2_i was merged into signal RASr2
|
||||
Signal XOR8MEG.CN was merged into signal PHI2_c
|
||||
Signal GND undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/VCC undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/GND undriven or does not drive anything - clipped.
|
||||
Signal FS_s_0_S1[17] undriven or does not drive anything - clipped.
|
||||
|
@ -313,6 +324,16 @@ Signal ufmefb/SPISCKEN undriven or does not drive anything - clipped.
|
|||
Signal ufmefb/SPISCKO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
|
||||
|
||||
Page 5
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 11/18/23 02:05:52
|
||||
|
||||
Removed logic (cont)
|
||||
--------------------
|
||||
Signal ufmefb/I2C2SDAOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SCLOEN undriven or does not drive anything - clipped.
|
||||
|
@ -324,16 +345,6 @@ Signal ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
|
|||
Signal ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
|
||||
|
||||
Page 5
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 09/21/23 05:39:45
|
||||
|
||||
Removed logic (cont)
|
||||
--------------------
|
||||
Signal ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
|
||||
|
@ -360,7 +371,6 @@ Signal N_1 undriven or does not drive anything - clipped.
|
|||
Block nCRAS_pad_RNIBPVB was optimized away.
|
||||
Block RASr2_RNIAFR1 was optimized away.
|
||||
Block XOR8MEG.CN was optimized away.
|
||||
Block GND was optimized away.
|
||||
Block ufmefb/VCC was optimized away.
|
||||
Block ufmefb/GND was optimized away.
|
||||
|
||||
|
@ -380,6 +390,16 @@ Embedded Functional Block Connection Summary
|
|||
Timer/Counter Mode: WB
|
||||
UFM Connection: ENABLED
|
||||
PLL0 Connection: DISABLED
|
||||
|
||||
Page 6
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 11/18/23 02:05:52
|
||||
|
||||
Embedded Functional Block Connection Summary (cont)
|
||||
---------------------------------------------------
|
||||
PLL1 Connection: DISABLED
|
||||
I2C Function Summary:
|
||||
--------------------
|
||||
|
@ -390,16 +410,6 @@ Embedded Functional Block Connection Summary
|
|||
Timer/Counter Function Summary:
|
||||
------------------------------
|
||||
None
|
||||
|
||||
Page 6
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 09/21/23 05:39:45
|
||||
|
||||
Embedded Functional Block Connection Summary (cont)
|
||||
---------------------------------------------------
|
||||
UFM Function Summary:
|
||||
--------------------
|
||||
UFM Utilization: General Purpose Flash Memory
|
||||
|
@ -425,7 +435,7 @@ Run Time and Memory Usage
|
|||
|
||||
Total CPU Time: 0 secs
|
||||
Total REAL Time: 0 secs
|
||||
Peak Memory Usage: 63 MB
|
||||
Peak Memory Usage: 64 MB
|
||||
|
||||
|
||||
|
||||
|
@ -436,16 +446,6 @@ Run Time and Memory Usage
|
|||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
|
@ -6,7 +6,7 @@ Performance Grade: 4
|
|||
PACKAGE: TQFP100
|
||||
Package Status: Final Version 1.44
|
||||
|
||||
Thu Sep 21 05:39:56 2023
|
||||
Sat Nov 18 02:06:05 2023
|
||||
|
||||
Pinout by Port Name:
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
|
@ -55,9 +55,10 @@ Pinout by Port Name:
|
|||
| RA[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[9] | 62/1 | LVCMOS33_OUT | PR5D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RBA[0] | 58/1 | LVCMOS33_OUT | PR9A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RBA[1] | 60/1 | LVCMOS33_OUT | PR8C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RBA[1] | 47/2 | LVCMOS33_OUT | PB18D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RCKE | 53/1 | LVCMOS33_OUT | PR9D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RCLK | 63/1 | LVCMOS33_IN | PR5C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| RCLKout | 60/1 | LVCMOS33_OUT | PR8C | | | DRIVE:24mA SLEW:FAST |
|
||||
| RDQMH | 51/1 | LVCMOS33_OUT | PR10D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RDQML | 48/2 | LVCMOS33_OUT | PB20C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RD[0] | 36/2 | LVCMOS33_BIDI | PB11C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
|
@ -134,7 +135,7 @@ Pinout by Pin Number:
|
|||
| 42/2 | RD[6] | LOCATED | LVCMOS33_BIDI | PB18A | | | |
|
||||
| 43/2 | RD[7] | LOCATED | LVCMOS33_BIDI | PB18B | | | |
|
||||
| 45/2 | unused, PULL:DOWN | | | PB18C | | | |
|
||||
| 47/2 | unused, PULL:DOWN | | | PB18D | | | |
|
||||
| 47/2 | RBA[1] | LOCATED | LVCMOS33_OUT | PB18D | | | |
|
||||
| 48/2 | RDQML | LOCATED | LVCMOS33_OUT | PB20C | SN | | |
|
||||
| 49/2 | nRWE | LOCATED | LVCMOS33_OUT | PB20D | SI/SISPI | | |
|
||||
| 51/1 | RDQMH | LOCATED | LVCMOS33_OUT | PR10D | DQ1 | | |
|
||||
|
@ -144,7 +145,7 @@ Pinout by Pin Number:
|
|||
| 57/1 | nRCS | LOCATED | LVCMOS33_OUT | PR9B | DQ1 | | |
|
||||
| 58/1 | RBA[0] | LOCATED | LVCMOS33_OUT | PR9A | DQ1 | | |
|
||||
| 59/1 | RA[11] | LOCATED | LVCMOS33_OUT | PR8D | DQ1 | | |
|
||||
| 60/1 | RBA[1] | LOCATED | LVCMOS33_OUT | PR8C | DQ1 | | |
|
||||
| 60/1 | RCLKout | LOCATED | LVCMOS33_OUT | PR8C | DQ1 | | |
|
||||
| 61/1 | unused, PULL:DOWN | | | PR8A | DQS1 | | |
|
||||
| 62/1 | RA[9] | LOCATED | LVCMOS33_OUT | PR5D | PCLKC1_0/DQ0 | | |
|
||||
| 63/1 | RCLK | LOCATED | LVCMOS33_IN | PR5C | PCLKT1_0/DQ0 | | |
|
||||
|
@ -266,9 +267,10 @@ LOCATE COMP "RA[7]" SITE "75";
|
|||
LOCATE COMP "RA[8]" SITE "65";
|
||||
LOCATE COMP "RA[9]" SITE "62";
|
||||
LOCATE COMP "RBA[0]" SITE "58";
|
||||
LOCATE COMP "RBA[1]" SITE "60";
|
||||
LOCATE COMP "RBA[1]" SITE "47";
|
||||
LOCATE COMP "RCKE" SITE "53";
|
||||
LOCATE COMP "RCLK" SITE "63";
|
||||
LOCATE COMP "RCLKout" SITE "60";
|
||||
LOCATE COMP "RDQMH" SITE "51";
|
||||
LOCATE COMP "RDQML" SITE "48";
|
||||
LOCATE COMP "RD[0]" SITE "36";
|
||||
|
@ -297,5 +299,5 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Thu Sep 21 05:39:59 2023
|
||||
Sat Nov 18 02:06:09 2023
|
||||
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
SCHEMATIC START ;
|
||||
# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Thu Sep 21 05:39:45 2023
|
||||
# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Sat Nov 18 02:05:53 2023
|
||||
|
||||
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
|
||||
LOCATE COMP "RD[0]" SITE "36" ;
|
||||
|
@ -11,6 +11,7 @@ LOCATE COMP "nRCAS" SITE "52" ;
|
|||
LOCATE COMP "nRRAS" SITE "54" ;
|
||||
LOCATE COMP "nRWE" SITE "49" ;
|
||||
LOCATE COMP "RCKE" SITE "53" ;
|
||||
LOCATE COMP "RCLKout" SITE "60" ;
|
||||
LOCATE COMP "RCLK" SITE "63" ;
|
||||
LOCATE COMP "nRCS" SITE "57" ;
|
||||
LOCATE COMP "RD[7]" SITE "43" ;
|
||||
|
@ -32,7 +33,7 @@ LOCATE COMP "RA[3]" SITE "71" ;
|
|||
LOCATE COMP "RA[2]" SITE "69" ;
|
||||
LOCATE COMP "RA[1]" SITE "67" ;
|
||||
LOCATE COMP "RA[0]" SITE "66" ;
|
||||
LOCATE COMP "RBA[1]" SITE "60" ;
|
||||
LOCATE COMP "RBA[1]" SITE "47" ;
|
||||
LOCATE COMP "RBA[0]" SITE "58" ;
|
||||
LOCATE COMP "LED" SITE "34" ;
|
||||
LOCATE COMP "nFWE" SITE "15" ;
|
||||
|
@ -110,4 +111,5 @@ OUTPUT PORT "RD[4]" LOAD 9.000000 pF ;
|
|||
OUTPUT PORT "RD[5]" LOAD 9.000000 pF ;
|
||||
OUTPUT PORT "RD[6]" LOAD 9.000000 pF ;
|
||||
OUTPUT PORT "RD[7]" LOAD 9.000000 pF ;
|
||||
OUTPUT PORT "RCLKout" LOAD 5.000000 pF ;
|
||||
COMMERCIAL ;
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
#OS: Windows 8 6.2
|
||||
#Hostname: ZANEMACWIN11
|
||||
|
||||
# Thu Sep 21 05:39:34 2023
|
||||
# Sat Nov 18 02:05:40 2023
|
||||
|
||||
#Implementation: impl1
|
||||
|
||||
|
@ -51,13 +51,17 @@ Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 202
|
|||
@I::"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v" (library work)
|
||||
@I::"\\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC\REFB.v" (library work)
|
||||
Verilog syntax check successful!
|
||||
File \\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v changed - recompiling
|
||||
Selecting top level module RAM2GS
|
||||
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1601:7:1601:12|Synthesizing module ODDRXE in library work.
|
||||
Running optimization stage 1 on ODDRXE .......
|
||||
Finished optimization stage 1 on ODDRXE (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
|
||||
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
|
||||
Running optimization stage 1 on VHI .......
|
||||
Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 98MB)
|
||||
Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
|
||||
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
|
||||
Running optimization stage 1 on VLO .......
|
||||
Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
|
||||
Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
|
||||
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
|
||||
Running optimization stage 1 on EFB .......
|
||||
Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
|
||||
|
@ -77,13 +81,15 @@ Running optimization stage 2 on VLO .......
|
|||
Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
|
||||
Running optimization stage 2 on VHI .......
|
||||
Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
|
||||
Running optimization stage 2 on ODDRXE .......
|
||||
Finished optimization stage 2 on ODDRXE (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
|
||||
|
||||
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)
|
||||
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 102MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:39:35 2023
|
||||
# Sat Nov 18 02:05:41 2023
|
||||
|
||||
###########################################################]
|
||||
###########################################################[
|
||||
|
@ -110,7 +116,7 @@ At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s;
|
|||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:39:35 2023
|
||||
# Sat Nov 18 02:05:41 2023
|
||||
|
||||
###########################################################]
|
||||
|
||||
|
@ -125,7 +131,7 @@ At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory
|
|||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:39:35 2023
|
||||
# Sat Nov 18 02:05:41 2023
|
||||
|
||||
###########################################################]
|
||||
###########################################################[
|
||||
|
@ -146,18 +152,17 @@ Implementation : impl1
|
|||
Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
File \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2GS_LCMXO2_1200HC_impl1_comp.srs changed - recompiling
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:39:36 2023
|
||||
# Sat Nov 18 02:05:43 2023
|
||||
|
||||
###########################################################]
|
||||
Premap Report
|
||||
|
||||
# Thu Sep 21 05:39:37 2023
|
||||
# Sat Nov 18 02:05:43 2023
|
||||
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
|
@ -176,10 +181,10 @@ Implementation : impl1
|
|||
Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @
|
||||
|
||||
|
||||
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
|
||||
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
|
||||
|
||||
|
||||
Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 140MB)
|
||||
Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 140MB)
|
||||
|
||||
Reading constraint file: \\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS.sdc
|
||||
@L: \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC\impl1\RAM2GS_LCMXO2_1200HC_impl1_scck.rpt
|
||||
|
@ -203,7 +208,6 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h
|
|||
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
|
||||
@N: FX493 |Applying initial value "0" on instance Ready.
|
||||
@N: FX493 |Applying initial value "0" on instance RCKE.
|
||||
@N: FX493 |Applying initial value "0" on instance LEDEN.
|
||||
@N: FX493 |Applying initial value "0" on instance n8MEGEN.
|
||||
@N: FX493 |Applying initial value "1" on instance nRCAS.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdLEDEN.
|
||||
|
@ -223,17 +227,17 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h
|
|||
Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
|
||||
|
||||
|
||||
Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
|
||||
Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
|
||||
|
||||
|
||||
Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 181MB peak: 182MB)
|
||||
Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
|
||||
|
||||
|
||||
Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
|
||||
Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
|
||||
|
||||
@N: FX1184 |Applying syn_allowed_resources blockrams=7 on top level netlist RAM2GS
|
||||
|
||||
Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
|
||||
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
|
||||
|
||||
|
||||
|
||||
|
@ -314,15 +318,13 @@ Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:0
|
|||
|
||||
Pre-mapping successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 103MB peak: 185MB)
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 99MB peak: 185MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Thu Sep 21 05:39:38 2023
|
||||
# Sat Nov 18 02:05:44 2023
|
||||
|
||||
###########################################################]
|
||||
Map & Optimize Report
|
||||
|
||||
# Thu Sep 21 05:39:39 2023
|
||||
# Sat Nov 18 02:05:44 2023
|
||||
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
|
@ -363,10 +365,10 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h
|
|||
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 179MB peak: 179MB)
|
||||
|
||||
|
||||
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB)
|
||||
Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB)
|
||||
|
||||
@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":163:4:163:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0]
|
||||
@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":150:4:150:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0]
|
||||
@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":166:4:166:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0]
|
||||
@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":153:4:153:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0]
|
||||
@N: FX493 |Applying initial value "0" on instance IS[0].
|
||||
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
|
||||
@N: FX493 |Applying initial value "0" on instance IS[1].
|
||||
|
@ -376,7 +378,7 @@ Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00
|
|||
Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 185MB peak: 185MB)
|
||||
|
||||
|
||||
Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 187MB peak: 187MB)
|
||||
Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB)
|
||||
|
||||
|
||||
Available hyper_sources - for debug and ip models
|
||||
|
@ -398,16 +400,16 @@ Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CP
|
|||
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
|
||||
|
||||
|
||||
Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 197MB peak: 197MB)
|
||||
Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 197MB peak: 197MB)
|
||||
|
||||
Pass CPU time Worst Slack Luts / Registers
|
||||
------------------------------------------------------------
|
||||
1 0h:00m:01s -2.98ns 201 / 106
|
||||
2 0h:00m:01s -2.98ns 217 / 106
|
||||
3 0h:00m:01s -2.76ns 215 / 106
|
||||
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":121:4:121:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 6 loads 1 time to improve timing.
|
||||
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":304:4:304:9|Replicating instance CmdValid (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.
|
||||
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":163:4:163:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 11 loads 1 time to improve timing.
|
||||
1 0h:00m:02s -2.98ns 202 / 106
|
||||
2 0h:00m:02s -2.98ns 215 / 106
|
||||
3 0h:00m:02s -2.76ns 215 / 106
|
||||
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":124:4:124:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 6 loads 1 time to improve timing.
|
||||
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":307:4:307:9|Replicating instance CmdValid (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.
|
||||
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":166:4:166:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 12 loads 1 time to improve timing.
|
||||
Timing driven replication report
|
||||
Added 3 Registers via timing driven replication
|
||||
Added 1 LUTs via timing driven replication
|
||||
|
@ -424,7 +426,7 @@ Finished technology timing optimizations and critical path resynthesis (Real Tim
|
|||
Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 198MB peak: 198MB)
|
||||
|
||||
|
||||
Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 160MB peak: 198MB)
|
||||
Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 160MB peak: 198MB)
|
||||
|
||||
Writing Analyst data base \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2GS_LCMXO2_1200HC_impl1_m.srm
|
||||
|
||||
|
@ -434,14 +436,15 @@ Writing EDIF Netlist and constraint files
|
|||
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC\impl1\RAM2GS_LCMXO2_1200HC_impl1.edi
|
||||
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
|
||||
|
||||
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 203MB peak: 203MB)
|
||||
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 203MB peak: 203MB)
|
||||
|
||||
|
||||
Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 203MB peak: 203MB)
|
||||
Finished Writing Netlists (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 203MB peak: 203MB)
|
||||
|
||||
|
||||
Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 201MB peak: 203MB)
|
||||
|
||||
@W: MT246 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":43:11:43:19|Blackbox ODDRXE is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
|
||||
@W: MT246 :"\\mac\icloud\repos\ram2gs\cpld\lcmxo2-1200hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
|
||||
@N: MT615 |Found clock RCLK with period 16.00ns
|
||||
@N: MT615 |Found clock PHI2 with period 350.00ns
|
||||
|
@ -450,7 +453,7 @@ Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:0
|
|||
|
||||
|
||||
##### START OF TIMING REPORT #####[
|
||||
# Timing report written on Thu Sep 21 05:39:43 2023
|
||||
# Timing report written on Sat Nov 18 02:05:49 2023
|
||||
#
|
||||
|
||||
|
||||
|
@ -501,7 +504,7 @@ Starting Ending | constraint slack | constraint slack | constraint
|
|||
---------------------------------------------------------------------------------------------------------------
|
||||
System RCLK | 16.000 12.918 | No paths - | No paths - | No paths -
|
||||
RCLK System | 16.000 14.956 | No paths - | No paths - | No paths -
|
||||
RCLK RCLK | 16.000 9.040 | No paths - | No paths - | No paths -
|
||||
RCLK RCLK | 16.000 9.237 | No paths - | No paths - | No paths -
|
||||
RCLK PHI2 | 2.000 0.216 | No paths - | 1.000 -0.676 | No paths -
|
||||
RCLK nCRAS | No paths - | No paths - | 1.000 -0.784 | No paths -
|
||||
PHI2 RCLK | No paths - | No paths - | No paths - | 1.000 -1.828
|
||||
|
@ -540,30 +543,30 @@ CmdLEDEN PHI2 FD1P3AX Q CmdLEDEN 1.044
|
|||
Cmdn8MEGEN PHI2 FD1P3AX Q Cmdn8MEGEN 1.044 -1.589
|
||||
CmdUFMWrite PHI2 FD1P3AX Q CmdUFMWrite 1.044 -0.572
|
||||
CmdUFMData PHI2 FD1P3AX Q CmdUFMData 0.972 -0.500
|
||||
Bank_0io[0] PHI2 IFS1P3DX Q Bank[0] 0.972 169.081
|
||||
Bank_0io[1] PHI2 IFS1P3DX Q Bank[1] 0.972 169.081
|
||||
Bank_0io[2] PHI2 IFS1P3DX Q Bank[2] 0.972 169.081
|
||||
Bank_0io[3] PHI2 IFS1P3DX Q Bank[3] 0.972 169.081
|
||||
==========================================================================================
|
||||
|
||||
|
||||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
-----------------------------------------------------------------------------------------
|
||||
wb_adr[0] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
|
||||
wb_adr[1] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
|
||||
wb_adr[2] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
|
||||
wb_adr[3] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
|
||||
wb_adr[4] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
|
||||
wb_adr[5] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
|
||||
wb_adr[6] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
|
||||
wb_adr[7] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
|
||||
wb_dati[0] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
|
||||
wb_dati[1] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
|
||||
=========================================================================================
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
--------------------------------------------------------------------------------
|
||||
wb_adr[0] PHI2 FD1P3AX SP N_126_i 0.528 -1.828
|
||||
wb_adr[1] PHI2 FD1P3AX SP N_126_i 0.528 -1.828
|
||||
wb_adr[2] PHI2 FD1P3AX SP N_126_i 0.528 -1.828
|
||||
wb_adr[3] PHI2 FD1P3AX SP N_126_i 0.528 -1.828
|
||||
wb_adr[4] PHI2 FD1P3AX SP N_126_i 0.528 -1.828
|
||||
wb_adr[5] PHI2 FD1P3AX SP N_126_i 0.528 -1.828
|
||||
wb_adr[6] PHI2 FD1P3AX SP N_126_i 0.528 -1.828
|
||||
wb_adr[7] PHI2 FD1P3AX SP N_126_i 0.528 -1.828
|
||||
wb_dati[0] PHI2 FD1P3AX SP N_126_i 0.528 -1.828
|
||||
wb_dati[1] PHI2 FD1P3AX SP N_126_i 0.528 -1.828
|
||||
================================================================================
|
||||
|
||||
|
||||
|
||||
|
@ -594,7 +597,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r -
|
|||
CmdUFMShift Net - - - - 2
|
||||
CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r -
|
||||
CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r -
|
||||
un1_wb_rst14_i_0 Net - - - - 17
|
||||
N_126_i Net - - - - 17
|
||||
wb_adr[0] FD1P3AX SP In 0.000 2.357 r -
|
||||
=========================================================================================
|
||||
|
||||
|
@ -622,7 +625,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r -
|
|||
CmdUFMShift Net - - - - 2
|
||||
CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r -
|
||||
CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r -
|
||||
un1_wb_rst14_i_0 Net - - - - 17
|
||||
N_126_i Net - - - - 17
|
||||
wb_adr[7] FD1P3AX SP In 0.000 2.357 r -
|
||||
=========================================================================================
|
||||
|
||||
|
@ -650,7 +653,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r -
|
|||
CmdUFMShift Net - - - - 2
|
||||
CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r -
|
||||
CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r -
|
||||
un1_wb_rst14_i_0 Net - - - - 17
|
||||
N_126_i Net - - - - 17
|
||||
wb_adr[6] FD1P3AX SP In 0.000 2.357 r -
|
||||
=========================================================================================
|
||||
|
||||
|
@ -678,7 +681,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r -
|
|||
CmdUFMShift Net - - - - 2
|
||||
CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r -
|
||||
CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r -
|
||||
un1_wb_rst14_i_0 Net - - - - 17
|
||||
N_126_i Net - - - - 17
|
||||
wb_adr[5] FD1P3AX SP In 0.000 2.357 r -
|
||||
=========================================================================================
|
||||
|
||||
|
@ -706,7 +709,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r -
|
|||
CmdUFMShift Net - - - - 2
|
||||
CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r -
|
||||
CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r -
|
||||
un1_wb_rst14_i_0 Net - - - - 17
|
||||
N_126_i Net - - - - 17
|
||||
wb_adr[4] FD1P3AX SP In 0.000 2.357 r -
|
||||
=========================================================================================
|
||||
|
||||
|
@ -729,13 +732,13 @@ Instance Reference Type Pin Net Time Slac
|
|||
Ready_fast RCLK FD1S3AX Q Ready_fast 1.256 -0.784
|
||||
LEDEN RCLK FD1S3AX Q LEDEN 1.148 -0.676
|
||||
n8MEGEN RCLK FD1S3AX Q n8MEGEN 1.108 -0.636
|
||||
IS[1] RCLK FD1P3AX Q IS[1] 1.204 9.040
|
||||
IS[2] RCLK FD1P3AX Q IS[2] 1.188 9.056
|
||||
IS[3] RCLK FD1P3AX Q IS[3] 1.148 9.096
|
||||
InitReady RCLK FD1S3AX Q InitReady 1.339 9.228
|
||||
FS[15] RCLK FD1S3AX Q FS[15] 1.228 9.339
|
||||
FS[16] RCLK FD1S3AX Q FS[16] 1.188 9.379
|
||||
FS[17] RCLK FD1S3AX Q FS[17] 1.188 9.379
|
||||
InitReady RCLK FD1S3AX Q InitReady 1.337 9.237
|
||||
FS[16] RCLK FD1S3AX Q FS[16] 1.204 9.371
|
||||
FS[17] RCLK FD1S3AX Q FS[17] 1.204 9.371
|
||||
FS[15] RCLK FD1S3AX Q FS[15] 1.188 9.387
|
||||
S[0] RCLK FD1S3IX Q CO0 1.244 9.873
|
||||
S[1] RCLK FD1S3IX Q S[1] 1.236 9.881
|
||||
RASr2 RCLK FD1S3AX Q RASr2 1.228 9.889
|
||||
==================================================================================
|
||||
|
||||
|
||||
|
@ -832,7 +835,35 @@ Path information for path number 3:
|
|||
|
||||
Number of logic level(s): 1
|
||||
Starting point: Ready_fast / Q
|
||||
Ending point: RowA[0] / D
|
||||
Ending point: RBA_0io[1] / D
|
||||
The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
|
||||
The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin SCLK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
---------------------------------------------------------------------------------
|
||||
Ready_fast FD1S3AX Q Out 1.256 1.256 r -
|
||||
Ready_fast Net - - - - 14
|
||||
RBAd[1] ORCALUT4 B In 0.000 1.256 r -
|
||||
RBAd[1] ORCALUT4 Z Out 0.617 1.873 r -
|
||||
RBAd_0[1] Net - - - - 1
|
||||
RBA_0io[1] OFS1P3DX D In 0.000 1.873 r -
|
||||
=================================================================================
|
||||
|
||||
|
||||
Path information for path number 4:
|
||||
Requested Period: 1.000
|
||||
- Setup time: -0.089
|
||||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
= Required time: 1.089
|
||||
|
||||
- Propagation time: 1.873
|
||||
- Clock delay at starting point: 0.000 (ideal)
|
||||
= Slack (non-critical) : -0.784
|
||||
|
||||
Number of logic level(s): 1
|
||||
Starting point: Ready_fast / Q
|
||||
Ending point: RowA[1] / D
|
||||
The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
|
||||
The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
|
||||
|
||||
|
@ -841,14 +872,14 @@ Name Type Name Dir Delay Time Fan Out(s
|
|||
---------------------------------------------------------------------------------
|
||||
Ready_fast FD1S3AX Q Out 1.256 1.256 r -
|
||||
Ready_fast Net - - - - 14
|
||||
RowAd[0] ORCALUT4 B In 0.000 1.256 r -
|
||||
RowAd[0] ORCALUT4 Z Out 0.617 1.873 r -
|
||||
RowAd_0[0] Net - - - - 1
|
||||
RowA[0] FD1S3AX D In 0.000 1.873 r -
|
||||
RowAd[1] ORCALUT4 B In 0.000 1.256 r -
|
||||
RowAd[1] ORCALUT4 Z Out 0.617 1.873 r -
|
||||
RowAd_0[1] Net - - - - 1
|
||||
RowA[1] FD1S3AX D In 0.000 1.873 r -
|
||||
=================================================================================
|
||||
|
||||
|
||||
Path information for path number 4:
|
||||
Path information for path number 5:
|
||||
Requested Period: 1.000
|
||||
- Setup time: -0.089
|
||||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
|
@ -876,34 +907,6 @@ RowA[5] FD1S3AX D In 0.000 1.873 f -
|
|||
=================================================================================
|
||||
|
||||
|
||||
Path information for path number 5:
|
||||
Requested Period: 1.000
|
||||
- Setup time: -0.089
|
||||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
= Required time: 1.089
|
||||
|
||||
- Propagation time: 1.873
|
||||
- Clock delay at starting point: 0.000 (ideal)
|
||||
= Slack (non-critical) : -0.784
|
||||
|
||||
Number of logic level(s): 1
|
||||
Starting point: Ready_fast / Q
|
||||
Ending point: RowA[8] / D
|
||||
The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
|
||||
The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
---------------------------------------------------------------------------------
|
||||
Ready_fast FD1S3AX Q Out 1.256 1.256 r -
|
||||
Ready_fast Net - - - - 14
|
||||
RowAd[8] ORCALUT4 B In 0.000 1.256 r -
|
||||
RowAd[8] ORCALUT4 Z Out 0.617 1.873 r -
|
||||
RowAd_0[8] Net - - - - 1
|
||||
RowA[8] FD1S3AX D In 0.000 1.873 r -
|
||||
=================================================================================
|
||||
|
||||
|
||||
|
||||
|
||||
====================================
|
||||
|
@ -928,16 +931,16 @@ FWEr nCRAS FD1S3AX Q FWEr 1.180 -1.797
|
|||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
------------------------------------------------------------------------------------------
|
||||
nRCAS_0io nCRAS OFS1P3BX D N_248_i 1.089 -2.605
|
||||
nRCS_0io nCRAS OFS1P3BX D N_247_i 1.089 -1.797
|
||||
nRWE_0io nCRAS OFS1P3BX D N_49_i 1.089 -1.797
|
||||
nRowColSel nCRAS FD1S3IX D nRowColSel_0_0_0 1.089 -1.797
|
||||
RCKEEN nCRAS FD1S3AX D RCKEEN_8 1.089 -1.725
|
||||
==========================================================================================
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------------------
|
||||
nRCAS_0io nCRAS OFS1P3BX D N_251_i 1.089 -2.605
|
||||
nRCS_0io nCRAS OFS1P3BX D N_37_i 1.089 -1.797
|
||||
nRWE_0io nCRAS OFS1P3BX D N_252_i 1.089 -1.797
|
||||
nRowColSel nCRAS FD1S3IX D nRowColSel_0_0 1.089 -1.797
|
||||
RCKEEN nCRAS FD1S3AX D RCKEEN_8 1.089 -1.725
|
||||
========================================================================================
|
||||
|
||||
|
||||
|
||||
|
@ -971,10 +974,10 @@ CBR_fast_RNIQ31K1 ORCALUT4 Z Out 1.089 2.061 r -
|
|||
nRCAS_0_sqmuxa_1 Net - - - - 2
|
||||
nRCAS_0io_RNO_0 ORCALUT4 B In 0.000 2.061 r -
|
||||
nRCAS_0io_RNO_0 ORCALUT4 Z Out 1.017 3.077 r -
|
||||
N_248_i_sx Net - - - - 1
|
||||
nRCAS_0io_RNO ORCALUT4 D In 0.000 3.077 r -
|
||||
N_251_i_sx Net - - - - 1
|
||||
nRCAS_0io_RNO ORCALUT4 C In 0.000 3.077 r -
|
||||
nRCAS_0io_RNO ORCALUT4 Z Out 0.617 3.694 f -
|
||||
N_248_i Net - - - - 1
|
||||
N_251_i Net - - - - 1
|
||||
nRCAS_0io OFS1P3BX D In 0.000 3.694 f -
|
||||
====================================================================================
|
||||
|
||||
|
@ -995,19 +998,19 @@ Path information for path number 2:
|
|||
The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
|
||||
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
--------------------------------------------------------------------------------------
|
||||
CBR FD1S3AX Q Out 1.180 1.180 r -
|
||||
CBR Net - - - - 5
|
||||
RCKEEN_8_u_0_0_a2_2 ORCALUT4 A In 0.000 1.180 r -
|
||||
RCKEEN_8_u_0_0_a2_2 ORCALUT4 Z Out 1.089 2.269 f -
|
||||
N_590 Net - - - - 2
|
||||
nRCS_0io_RNO ORCALUT4 C In 0.000 2.269 f -
|
||||
nRCS_0io_RNO ORCALUT4 Z Out 0.617 2.885 r -
|
||||
N_247_i Net - - - - 1
|
||||
nRCS_0io OFS1P3BX D In 0.000 2.885 r -
|
||||
======================================================================================
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
------------------------------------------------------------------------------------
|
||||
CBR FD1S3AX Q Out 1.180 1.180 r -
|
||||
CBR Net - - - - 5
|
||||
RCKEEN_8_u_0_a2_2 ORCALUT4 A In 0.000 1.180 r -
|
||||
RCKEEN_8_u_0_a2_2 ORCALUT4 Z Out 1.089 2.269 f -
|
||||
N_141 Net - - - - 2
|
||||
nRCS_0io_RNO ORCALUT4 A In 0.000 2.269 f -
|
||||
nRCS_0io_RNO ORCALUT4 Z Out 0.617 2.885 r -
|
||||
N_37_i Net - - - - 1
|
||||
nRCS_0io OFS1P3BX D In 0.000 2.885 r -
|
||||
====================================================================================
|
||||
|
||||
|
||||
Path information for path number 3:
|
||||
|
@ -1026,19 +1029,19 @@ Path information for path number 3:
|
|||
The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
|
||||
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
---------------------------------------------------------------------------------
|
||||
FWEr FD1S3AX Q Out 1.180 1.180 r -
|
||||
FWEr Net - - - - 5
|
||||
nRCAS_r_i_0_a2 ORCALUT4 B In 0.000 1.180 r -
|
||||
nRCAS_r_i_0_a2 ORCALUT4 Z Out 1.089 2.269 f -
|
||||
N_248_i_1_0 Net - - - - 2
|
||||
nRCAS_0io_RNO ORCALUT4 C In 0.000 2.269 f -
|
||||
nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.885 r -
|
||||
N_248_i Net - - - - 1
|
||||
nRCAS_0io OFS1P3BX D In 0.000 2.885 r -
|
||||
=================================================================================
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
----------------------------------------------------------------------------------
|
||||
FWEr FD1S3AX Q Out 1.180 1.180 r -
|
||||
FWEr Net - - - - 5
|
||||
nRCS_9_u_i_a2_0 ORCALUT4 B In 0.000 1.180 r -
|
||||
nRCS_9_u_i_a2_0 ORCALUT4 Z Out 1.089 2.269 f -
|
||||
N_251_i_1 Net - - - - 2
|
||||
nRCAS_0io_RNO ORCALUT4 A In 0.000 2.269 f -
|
||||
nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.885 r -
|
||||
N_251_i Net - - - - 1
|
||||
nRCAS_0io OFS1P3BX D In 0.000 2.885 r -
|
||||
==================================================================================
|
||||
|
||||
|
||||
Path information for path number 4:
|
||||
|
@ -1057,19 +1060,19 @@ Path information for path number 4:
|
|||
The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
|
||||
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
--------------------------------------------------------------------------------------
|
||||
CBR FD1S3AX Q Out 1.180 1.180 r -
|
||||
CBR Net - - - - 5
|
||||
RCKEEN_8_u_0_0_a2_2 ORCALUT4 A In 0.000 1.180 r -
|
||||
RCKEEN_8_u_0_0_a2_2 ORCALUT4 Z Out 1.089 2.269 f -
|
||||
N_590 Net - - - - 2
|
||||
nRWE_0io_RNO ORCALUT4 B In 0.000 2.269 f -
|
||||
nRWE_0io_RNO ORCALUT4 Z Out 0.617 2.885 r -
|
||||
N_49_i Net - - - - 1
|
||||
nRWE_0io OFS1P3BX D In 0.000 2.885 r -
|
||||
======================================================================================
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
------------------------------------------------------------------------------------
|
||||
CBR FD1S3AX Q Out 1.180 1.180 r -
|
||||
CBR Net - - - - 5
|
||||
RCKEEN_8_u_0_a2_2 ORCALUT4 A In 0.000 1.180 r -
|
||||
RCKEEN_8_u_0_a2_2 ORCALUT4 Z Out 1.089 2.269 f -
|
||||
N_141 Net - - - - 2
|
||||
nRWE_0io_RNO ORCALUT4 B In 0.000 2.269 f -
|
||||
nRWE_0io_RNO ORCALUT4 Z Out 0.617 2.885 r -
|
||||
N_252_i Net - - - - 1
|
||||
nRWE_0io OFS1P3BX D In 0.000 2.885 r -
|
||||
====================================================================================
|
||||
|
||||
|
||||
Path information for path number 5:
|
||||
|
@ -1093,12 +1096,12 @@ Name Type Name Dir Delay Time Fan
|
|||
--------------------------------------------------------------------------------------
|
||||
FWEr FD1S3AX Q Out 1.180 1.180 r -
|
||||
FWEr Net - - - - 5
|
||||
nRowColSel_0_0_0_a2 ORCALUT4 B In 0.000 1.180 r -
|
||||
nRowColSel_0_0_0_a2 ORCALUT4 Z Out 1.089 2.269 r -
|
||||
N_248_i_1_1 Net - - - - 2
|
||||
nRowColSel_0_0_a2_1 ORCALUT4 B In 0.000 1.180 r -
|
||||
nRowColSel_0_0_a2_1 ORCALUT4 Z Out 1.089 2.269 r -
|
||||
N_251_i_1_0 Net - - - - 2
|
||||
nRCAS_0io_RNO ORCALUT4 B In 0.000 2.269 r -
|
||||
nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.885 f -
|
||||
N_248_i Net - - - - 1
|
||||
N_251_i Net - - - - 1
|
||||
nRCAS_0io OFS1P3BX D In 0.000 2.885 f -
|
||||
======================================================================================
|
||||
|
||||
|
@ -1127,14 +1130,14 @@ ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000
|
|||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
-----------------------------------------------------------------------------------
|
||||
LEDEN System FD1S3AX D LEDENe_0 16.089 12.918
|
||||
n8MEGEN System FD1S3AX D n8MEGENe_0 16.089 12.918
|
||||
wb_cyc_stb System FD1P3IX SP N_178 15.528 14.912
|
||||
===================================================================================
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
--------------------------------------------------------------------------------------------------
|
||||
LEDEN System FD1S3AX D LEDENe_0 16.089 12.918
|
||||
n8MEGEN System FD1S3AX D n8MEGENe_0 16.089 12.918
|
||||
wb_cyc_stb System FD1P3IX SP wb_cyc_stb_2_sqmuxa_i_0_0 15.528 14.912
|
||||
==================================================================================================
|
||||
|
||||
|
||||
|
||||
|
@ -1172,8 +1175,8 @@ ufmefb.EFBInst_0_RNISI191 ORCALUT4 Z Out 0.449 1.466 r
|
|||
N_4 Net - - - - 1
|
||||
CmdValid_RNIOOBE2 ORCALUT4 C In 0.000 1.466 r -
|
||||
CmdValid_RNIOOBE2 ORCALUT4 Z Out 1.089 2.554 r -
|
||||
CmdValid_RNIOOBE2 Net - - - - 2
|
||||
LEDENe ORCALUT4 B In 0.000 2.554 r -
|
||||
un1_FS_38_i Net - - - - 2
|
||||
LEDENe ORCALUT4 C In 0.000 2.554 r -
|
||||
LEDENe ORCALUT4 Z Out 0.617 3.171 r -
|
||||
LEDENe_0 Net - - - - 1
|
||||
LEDEN FD1S3AX D In 0.000 3.171 r -
|
||||
|
@ -1196,7 +1199,7 @@ Part: lcmxo2_1200hc-4
|
|||
|
||||
Register bits: 109 of 1280 (9%)
|
||||
PIC Latch: 0
|
||||
I/O cells: 63
|
||||
I/O cells: 64
|
||||
|
||||
|
||||
Details:
|
||||
|
@ -1211,12 +1214,13 @@ GSR: 1
|
|||
IB: 25
|
||||
IFS1P3DX: 9
|
||||
INV: 7
|
||||
OB: 30
|
||||
OB: 31
|
||||
ODDRXE: 1
|
||||
OFS1P3BX: 4
|
||||
OFS1P3DX: 11
|
||||
OFS1P3JX: 1
|
||||
ORCALUT4: 213
|
||||
PFUMX: 1
|
||||
ORCALUT4: 212
|
||||
PFUMX: 2
|
||||
PUR: 1
|
||||
VHI: 2
|
||||
VLO: 2
|
||||
|
@ -1225,6 +1229,6 @@ Mapper successful!
|
|||
At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 78MB peak: 203MB)
|
||||
|
||||
Process took 0h:00m:04s realtime, 0h:00m:04s cputime
|
||||
# Thu Sep 21 05:39:43 2023
|
||||
# Sat Nov 18 02:05:49 2023
|
||||
|
||||
###########################################################]
|
||||
|
|
|
@ -13,7 +13,7 @@ Setup and Hold Report
|
|||
|
||||
--------------------------------------------------------------------------------
|
||||
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
|
||||
Thu Sep 21 05:39:46 2023
|
||||
Sat Nov 18 02:05:54 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
|
@ -46,28 +46,28 @@ Passed: The following path meets requirements by 163.025ns (weighted slack = 326
|
|||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q Bank_0io[0] (from PHI2_c +)
|
||||
Source: FF Q Bank_0io[1] (from PHI2_c +)
|
||||
Destination: FF Data in CmdEnable (to PHI2_c -)
|
||||
|
||||
Delay: 9.223ns (33.1% logic, 66.9% route), 6 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
9.223ns physical path delay Din[0]_MGIOL to SLICE_17 meets
|
||||
9.223ns physical path delay Din[1]_MGIOL to SLICE_17 meets
|
||||
172.414ns delay constraint less
|
||||
0.166ns DIN_SET requirement (totaling 172.248ns) by 163.025ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path Din[0]_MGIOL to SLICE_17:
|
||||
Data path Din[1]_MGIOL to SLICE_17:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
C2INP_DEL --- 0.577 *[0]_MGIOL.CLK to *n[0]_MGIOL.IN Din[0]_MGIOL (from PHI2_c)
|
||||
ROUTE 1 e 1.234 *n[0]_MGIOL.IN to SLICE_93.A0 Bank[0]
|
||||
CTOF_DEL --- 0.495 SLICE_93.A0 to SLICE_93.F0 SLICE_93
|
||||
ROUTE 1 e 1.234 SLICE_93.F0 to SLICE_84.C0 un1_CmdEnable20_0_0_o3_10
|
||||
CTOF_DEL --- 0.495 SLICE_84.C0 to SLICE_84.F0 SLICE_84
|
||||
ROUTE 6 e 1.234 SLICE_84.F0 to SLICE_11.C1 un1_CmdEnable20_0_0_o3
|
||||
C2INP_DEL --- 0.577 *[1]_MGIOL.CLK to *n[1]_MGIOL.IN Din[1]_MGIOL (from PHI2_c)
|
||||
ROUTE 1 e 1.234 *n[1]_MGIOL.IN to SLICE_90.A0 Bank[1]
|
||||
CTOF_DEL --- 0.495 SLICE_90.A0 to SLICE_90.F0 SLICE_90
|
||||
ROUTE 1 e 1.234 SLICE_90.F0 to SLICE_80.C0 un1_CmdEnable20_0_0_o2_10
|
||||
CTOF_DEL --- 0.495 SLICE_80.C0 to SLICE_80.F0 SLICE_80
|
||||
ROUTE 6 e 1.234 SLICE_80.F0 to SLICE_11.C1 N_367
|
||||
CTOF_DEL --- 0.495 SLICE_11.C1 to SLICE_11.F1 SLICE_11
|
||||
ROUTE 3 e 1.234 SLICE_11.F1 to SLICE_33.B0 CmdEnable16
|
||||
CTOF_DEL --- 0.495 SLICE_33.B0 to SLICE_33.F0 SLICE_33
|
||||
|
@ -118,48 +118,46 @@ Report: 150.150MHz is the maximum frequency for this preference.
|
|||
|
||||
================================================================================
|
||||
Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
|
||||
878 items scored, 0 timing errors detected.
|
||||
891 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 6.049ns
|
||||
Passed: The following path meets requirements by 5.516ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q IS[1] (from RCLK_c +)
|
||||
Destination: FF Data in nRCAS_0io (to RCLK_c +)
|
||||
Source: FF Q S[0] (from RCLK_c +)
|
||||
Destination: FF Data in nRWE_0io (to RCLK_c +)
|
||||
|
||||
Delay: 9.798ns (34.9% logic, 65.1% route), 7 logic levels.
|
||||
Delay: 10.331ns (28.3% logic, 71.7% route), 6 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
9.798ns physical path delay SLICE_27 to nRCAS_MGIOL meets
|
||||
10.331ns physical path delay SLICE_16 to nRWE_MGIOL meets
|
||||
16.000ns delay constraint less
|
||||
0.153ns DO_SET requirement (totaling 15.847ns) by 6.049ns
|
||||
0.153ns DO_SET requirement (totaling 15.847ns) by 5.516ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path SLICE_27 to nRCAS_MGIOL:
|
||||
Data path SLICE_16 to nRWE_MGIOL:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.452 SLICE_27.CLK to SLICE_27.Q0 SLICE_27 (from RCLK_c)
|
||||
ROUTE 7 e 1.234 SLICE_27.Q0 to SLICE_74.A1 IS[1]
|
||||
CTOF_DEL --- 0.495 SLICE_74.A1 to SLICE_74.F1 SLICE_74
|
||||
ROUTE 2 e 0.480 SLICE_74.F1 to SLICE_74.B0 un1_nRCAS_6_sqmuxa_i_0_0_o2_0
|
||||
CTOF_DEL --- 0.495 SLICE_74.B0 to SLICE_74.F0 SLICE_74
|
||||
ROUTE 2 e 1.234 SLICE_74.F0 to SLICE_61.B1 N_408
|
||||
CTOF_DEL --- 0.495 SLICE_61.B1 to SLICE_61.F1 SLICE_61
|
||||
ROUTE 1 e 0.480 SLICE_61.F1 to SLICE_61.A0 un1_nRCAS_6_sqmuxa_i_0_0
|
||||
CTOF_DEL --- 0.495 SLICE_61.A0 to SLICE_61.F0 SLICE_61
|
||||
ROUTE 1 e 1.234 SLICE_61.F0 to SLICE_94.D0 nRCAS_r_i_0_o2_0_0
|
||||
CTOF_DEL --- 0.495 SLICE_94.D0 to SLICE_94.F0 SLICE_94
|
||||
ROUTE 1 e 0.480 SLICE_94.F0 to SLICE_94.A1 N_248_i_1
|
||||
CTOF_DEL --- 0.495 SLICE_94.A1 to SLICE_94.F1 SLICE_94
|
||||
ROUTE 1 e 1.234 SLICE_94.F1 to *AS_MGIOL.OPOS N_248_i (to RCLK_c)
|
||||
REG_DEL --- 0.452 SLICE_16.CLK to SLICE_16.Q0 SLICE_16 (from RCLK_c)
|
||||
ROUTE 12 e 1.234 SLICE_16.Q0 to SLICE_62.D1 CO0
|
||||
CTOF_DEL --- 0.495 SLICE_62.D1 to SLICE_62.F1 SLICE_62
|
||||
ROUTE 6 e 1.234 SLICE_62.F1 to SLICE_79.A1 IS_0_sqmuxa_0_o2
|
||||
CTOF_DEL --- 0.495 SLICE_79.A1 to SLICE_79.F1 SLICE_79
|
||||
ROUTE 2 e 1.234 SLICE_79.F1 to SLICE_28.D1 IS_0_sqmuxa_0_o3
|
||||
CTOF_DEL --- 0.495 SLICE_28.D1 to SLICE_28.F1 SLICE_28
|
||||
ROUTE 1 e 1.234 SLICE_28.F1 to SLICE_68.D1 nRWE_s_i_a2_1_0
|
||||
CTOF_DEL --- 0.495 SLICE_68.D1 to SLICE_68.F1 SLICE_68
|
||||
ROUTE 1 e 1.234 SLICE_68.F1 to SLICE_75.D0 nRWE_s_i_tz_0
|
||||
CTOF_DEL --- 0.495 SLICE_75.D0 to SLICE_75.F0 SLICE_75
|
||||
ROUTE 1 e 1.234 SLICE_75.F0 to *WE_MGIOL.OPOS N_252_i (to RCLK_c)
|
||||
--------
|
||||
9.798 (34.9% logic, 65.1% route), 7 logic levels.
|
||||
10.331 (28.3% logic, 71.7% route), 6 logic levels.
|
||||
|
||||
Report: 100.492MHz is the maximum frequency for this preference.
|
||||
Report: 95.383MHz is the maximum frequency for this preference.
|
||||
|
||||
Report Summary
|
||||
--------------
|
||||
|
@ -173,7 +171,7 @@ FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
|
|||
| | |
|
||||
FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
|
||||
| | |
|
||||
FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 100.492 MHz| 7
|
||||
FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 95.383 MHz| 6
|
||||
| | |
|
||||
----------------------------------------------------------------------------
|
||||
|
||||
|
@ -198,7 +196,7 @@ Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11
|
|||
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
|
||||
No transfer within this clock domain is found
|
||||
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 48
|
||||
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
|
||||
|
||||
Data transfers from:
|
||||
|
@ -228,11 +226,11 @@ Timing summary (Setup):
|
|||
Timing errors: 0 Score: 0
|
||||
Cumulative negative slack: 0
|
||||
|
||||
Constraints cover 1025 paths, 4 nets, and 741 connections (72.86% coverage)
|
||||
Constraints cover 1038 paths, 4 nets, and 732 connections (72.40% coverage)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
|
||||
Thu Sep 21 05:39:46 2023
|
||||
Sat Nov 18 02:05:54 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
|
@ -303,7 +301,7 @@ Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
|
|||
|
||||
================================================================================
|
||||
Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
|
||||
878 items scored, 0 timing errors detected.
|
||||
891 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
@ -369,7 +367,7 @@ Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11
|
|||
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
|
||||
No transfer within this clock domain is found
|
||||
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 48
|
||||
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
|
||||
|
||||
Data transfers from:
|
||||
|
@ -399,7 +397,7 @@ Timing summary (Hold):
|
|||
Timing errors: 0 Score: 0
|
||||
Cumulative negative slack: 0
|
||||
|
||||
Constraints cover 1025 paths, 4 nets, and 741 connections (72.86% coverage)
|
||||
Constraints cover 1038 paths, 4 nets, and 732 connections (72.40% coverage)
|
||||
|
||||
|
||||
|
||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -12,10 +12,10 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Thu Sep 21 05:40:13 2023
|
||||
Sat Nov 18 02:06:29 2023
|
||||
|
||||
|
||||
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC -w -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
|
||||
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC -w -jedec -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf
|
||||
|
||||
Loading design for application Bitgen from file RAM2GS_LCMXO2_1200HC_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
|
@ -80,9 +80,19 @@ Creating bit map...
|
|||
|
||||
Bitstream Status: Final Version 1.95.
|
||||
|
||||
Saving bit stream in "RAM2GS_LCMXO2_1200HC_impl1.bit".
|
||||
Total CPU Time: 4 secs
|
||||
Total REAL Time: 4 secs
|
||||
Saving bit stream in "RAM2GS_LCMXO2_1200HC_impl1.jed".
|
||||
|
||||
===========
|
||||
UFM Summary.
|
||||
===========
|
||||
UFM Size: 511 Pages (128*511 Bits).
|
||||
UFM Utilization: General Purpose Flash Memory.
|
||||
|
||||
Available General Purpose Flash Memory: 511 Pages (Page 0 to Page 510).
|
||||
Initialized UFM Pages: 321 Pages (Page 190 to Page 510).
|
||||
|
||||
Total CPU Time: 3 secs
|
||||
Total REAL Time: 3 secs
|
||||
Peak Memory Usage: 274 MB
|
||||
|
||||
|
||||
|
|
|
@ -13,7 +13,7 @@ Hostname: ZANEMACWIN11
|
|||
|
||||
Implementation : impl1
|
||||
|
||||
# Written on Thu Sep 21 05:39:38 2023
|
||||
# Written on Sat Nov 18 02:05:44 2023
|
||||
|
||||
##### DESIGN INFO #######################################################
|
||||
|
||||
|
@ -103,6 +103,7 @@ p:RA[11]
|
|||
p:RBA[0]
|
||||
p:RBA[1]
|
||||
p:RCKE
|
||||
p:RCLKout
|
||||
p:RDQMH
|
||||
p:RDQML
|
||||
p:RD[0] (bidir end point)
|
||||
|
|
|
@ -38,7 +38,7 @@ Performance Hardware Data Status: Final Version 34.4.
|
|||
// Package: TQFP100
|
||||
// ncd File: ram2gs_lcmxo2_1200hc_impl1.ncd
|
||||
// Version: Diamond (64-bit) 3.12.1.454
|
||||
// Written on Thu Sep 21 05:40:06 2023
|
||||
// Written on Sat Nov 18 02:06:17 2023
|
||||
// M: Minimum Performance Grade
|
||||
// iotiming RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml
|
||||
|
||||
|
@ -50,95 +50,96 @@ Worst Case Results across Performance Grades (M, 6, 5, 4):
|
|||
|
||||
Port Clock Edge Setup Performance_Grade Hold Performance_Grade
|
||||
----------------------------------------------------------------------
|
||||
CROW[0] nCRAS F 2.913 4 -0.274 M
|
||||
CROW[1] nCRAS F 2.475 4 -0.161 M
|
||||
Din[0] PHI2 F 5.366 4 4.293 4
|
||||
Din[0] nCCAS F 1.448 4 -0.034 M
|
||||
Din[1] PHI2 F 4.971 4 4.173 4
|
||||
Din[1] nCCAS F 0.519 4 0.708 4
|
||||
Din[2] PHI2 F 5.192 4 4.173 4
|
||||
Din[2] nCCAS F 1.948 4 -0.142 M
|
||||
Din[3] PHI2 F 5.298 4 4.173 4
|
||||
Din[3] nCCAS F 1.974 4 -0.157 M
|
||||
Din[4] PHI2 F 4.281 4 4.173 4
|
||||
Din[4] nCCAS F 1.060 4 0.217 4
|
||||
Din[5] PHI2 F 5.059 4 4.173 4
|
||||
Din[5] nCCAS F 1.956 4 -0.150 M
|
||||
Din[6] PHI2 F 4.644 4 4.293 4
|
||||
Din[6] nCCAS F 2.886 4 -0.382 M
|
||||
Din[7] PHI2 F 5.316 4 4.293 4
|
||||
Din[7] nCCAS F 2.381 4 -0.244 M
|
||||
MAin[0] PHI2 F 4.362 4 1.145 4
|
||||
MAin[0] nCRAS F 1.189 4 0.362 4
|
||||
MAin[1] PHI2 F 4.386 4 0.999 4
|
||||
MAin[1] nCRAS F 1.884 4 -0.024 M
|
||||
MAin[2] PHI2 F 9.426 4 -0.750 M
|
||||
MAin[2] nCRAS F 1.136 4 0.453 4
|
||||
MAin[3] PHI2 F 10.458 4 -0.997 M
|
||||
MAin[3] nCRAS F 1.564 4 0.067 4
|
||||
MAin[4] PHI2 F 11.109 4 -1.209 M
|
||||
CROW[0] nCRAS F 3.288 4 -0.390 M
|
||||
CROW[1] nCRAS F 2.823 4 -0.285 M
|
||||
Din[0] PHI2 F 6.398 4 4.293 4
|
||||
Din[0] nCCAS F 1.411 4 -0.004 M
|
||||
Din[1] PHI2 F 3.916 4 4.173 4
|
||||
Din[1] nCCAS F 1.877 4 -0.123 M
|
||||
Din[2] PHI2 F 6.180 4 4.173 4
|
||||
Din[2] nCCAS F 1.548 4 -0.062 M
|
||||
Din[3] PHI2 F 5.536 4 4.173 4
|
||||
Din[3] nCCAS F 0.467 4 0.734 4
|
||||
Din[4] PHI2 F 3.611 4 4.173 4
|
||||
Din[4] nCCAS F 1.533 4 -0.043 M
|
||||
Din[5] PHI2 F 5.673 4 4.173 4
|
||||
Din[5] nCCAS F 1.663 4 -0.072 M
|
||||
Din[6] PHI2 F 5.355 4 4.293 4
|
||||
Din[6] nCCAS F 2.807 4 -0.352 M
|
||||
Din[7] PHI2 F 5.296 4 4.293 4
|
||||
Din[7] nCCAS F 1.914 4 -0.136 M
|
||||
MAin[0] PHI2 F 4.091 4 1.414 4
|
||||
MAin[0] nCRAS F 1.207 4 0.347 4
|
||||
MAin[1] PHI2 F 3.273 4 1.759 4
|
||||
MAin[1] nCRAS F 1.077 4 0.460 4
|
||||
MAin[2] PHI2 F 8.126 4 -0.351 M
|
||||
MAin[2] nCRAS F 0.671 4 0.850 4
|
||||
MAin[3] PHI2 F 8.831 4 -0.579 M
|
||||
MAin[3] nCRAS F 1.100 4 0.463 4
|
||||
MAin[4] PHI2 F 8.415 4 -0.447 M
|
||||
MAin[4] nCRAS F 1.390 4 0.207 4
|
||||
MAin[5] PHI2 F 9.884 4 -0.896 M
|
||||
MAin[5] PHI2 F 9.742 4 -0.803 M
|
||||
MAin[5] nCRAS F 1.269 4 0.218 4
|
||||
MAin[6] PHI2 F 9.859 4 -0.845 M
|
||||
MAin[6] nCRAS F 0.889 4 0.653 4
|
||||
MAin[7] PHI2 F 10.678 4 -1.070 M
|
||||
MAin[7] nCRAS F 1.186 4 0.309 4
|
||||
MAin[8] nCRAS F 1.639 4 0.014 M
|
||||
MAin[9] nCRAS F 1.097 4 0.457 4
|
||||
MAin[6] PHI2 F 7.970 4 -0.325 M
|
||||
MAin[6] nCRAS F 1.165 4 0.337 4
|
||||
MAin[7] PHI2 F 8.481 4 -0.438 M
|
||||
MAin[7] nCRAS F 0.761 4 0.673 4
|
||||
MAin[8] nCRAS F 1.261 4 0.223 4
|
||||
MAin[9] nCRAS F 0.756 4 0.667 4
|
||||
PHI2 RCLK R -0.133 M 2.360 4
|
||||
nCCAS RCLK R 2.943 4 -0.337 M
|
||||
nCCAS nCRAS F 2.967 4 -0.214 M
|
||||
nCRAS RCLK R 3.047 4 -0.402 M
|
||||
nFWE PHI2 F 11.116 4 -1.189 M
|
||||
nFWE nCRAS F 1.394 4 0.225 4
|
||||
nCCAS RCLK R 4.128 4 -0.675 M
|
||||
nCCAS nCRAS F 4.568 4 -0.666 M
|
||||
nCRAS RCLK R 3.070 4 -0.412 M
|
||||
nFWE PHI2 F 8.979 4 -0.603 M
|
||||
nFWE nCRAS F 1.467 4 0.144 4
|
||||
|
||||
|
||||
// Clock to Output Delay
|
||||
|
||||
Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
|
||||
Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
|
||||
------------------------------------------------------------------------
|
||||
LED RCLK R 11.046 4 3.298 M
|
||||
LED nCRAS F 11.710 4 3.359 M
|
||||
RA[0] RCLK R 11.397 4 3.516 M
|
||||
RA[0] nCRAS F 11.476 4 3.432 M
|
||||
RA[10] RCLK R 7.888 4 2.711 M
|
||||
RA[11] PHI2 R 9.755 4 3.200 M
|
||||
RA[1] RCLK R 11.272 4 3.469 M
|
||||
RA[1] nCRAS F 11.238 4 3.348 M
|
||||
RA[2] RCLK R 11.235 4 3.468 M
|
||||
RA[2] nCRAS F 11.665 4 3.453 M
|
||||
RA[3] RCLK R 11.390 4 3.512 M
|
||||
RA[3] nCRAS F 11.922 4 3.539 M
|
||||
RA[4] RCLK R 11.662 4 3.573 M
|
||||
RA[4] nCRAS F 11.818 4 3.505 M
|
||||
RA[5] RCLK R 11.744 4 3.584 M
|
||||
RA[5] nCRAS F 11.779 4 3.513 M
|
||||
RA[6] RCLK R 11.738 4 3.607 M
|
||||
RA[6] nCRAS F 11.836 4 3.531 M
|
||||
RA[7] RCLK R 12.475 4 3.797 M
|
||||
RA[7] nCRAS F 11.420 4 3.426 M
|
||||
RA[8] RCLK R 11.122 4 3.431 M
|
||||
RA[8] nCRAS F 11.667 4 3.471 M
|
||||
RA[9] RCLK R 11.935 4 3.649 M
|
||||
RA[9] nCRAS F 11.401 4 3.424 M
|
||||
RBA[0] nCRAS F 8.903 4 2.891 M
|
||||
RBA[1] nCRAS F 8.903 4 2.891 M
|
||||
RCKE RCLK R 10.011 4 3.215 M
|
||||
RDQMH RCLK R 10.790 4 3.354 M
|
||||
RDQML RCLK R 11.053 4 3.450 M
|
||||
RD[0] nCCAS F 8.977 4 3.012 M
|
||||
RD[1] nCCAS F 8.977 4 3.012 M
|
||||
RD[2] nCCAS F 8.977 4 3.012 M
|
||||
RD[3] nCCAS F 8.977 4 3.012 M
|
||||
RD[4] nCCAS F 8.977 4 3.012 M
|
||||
RD[5] nCCAS F 8.977 4 3.012 M
|
||||
RD[6] nCCAS F 8.977 4 3.012 M
|
||||
RD[7] nCCAS F 8.977 4 3.012 M
|
||||
nRCAS RCLK R 7.822 4 2.706 M
|
||||
nRCS RCLK R 7.822 4 2.706 M
|
||||
nRRAS RCLK R 7.822 4 2.706 M
|
||||
nRWE RCLK R 7.803 4 2.713 M
|
||||
LED RCLK R 11.034 4 3.119 M
|
||||
LED nCRAS F 11.531 4 3.339 M
|
||||
RA[0] RCLK R 11.682 4 3.586 M
|
||||
RA[0] nCRAS F 11.704 4 3.483 M
|
||||
RA[10] RCLK R 7.888 4 2.711 M
|
||||
RA[11] PHI2 R 9.755 4 3.200 M
|
||||
RA[1] RCLK R 11.454 4 3.535 M
|
||||
RA[1] nCRAS F 11.216 4 3.347 M
|
||||
RA[2] RCLK R 12.084 4 3.693 M
|
||||
RA[2] nCRAS F 11.742 4 3.501 M
|
||||
RA[3] RCLK R 12.131 4 3.715 M
|
||||
RA[3] nCRAS F 11.857 4 3.533 M
|
||||
RA[4] RCLK R 11.966 4 3.684 M
|
||||
RA[4] nCRAS F 12.319 4 3.650 M
|
||||
RA[5] RCLK R 11.928 4 3.670 M
|
||||
RA[5] nCRAS F 11.637 4 3.446 M
|
||||
RA[6] RCLK R 11.419 4 3.523 M
|
||||
RA[6] nCRAS F 11.718 4 3.486 M
|
||||
RA[7] RCLK R 11.988 4 3.651 M
|
||||
RA[7] nCRAS F 12.274 4 3.636 M
|
||||
RA[8] RCLK R 11.660 4 3.582 M
|
||||
RA[8] nCRAS F 11.098 4 3.343 M
|
||||
RA[9] RCLK R 11.454 4 3.547 M
|
||||
RA[9] nCRAS F 11.134 4 3.314 M
|
||||
RBA[0] nCRAS F 8.903 4 2.891 M
|
||||
RBA[1] nCRAS F 8.883 4 2.898 M
|
||||
RCKE RCLK R 9.774 4 3.159 M
|
||||
RCLKout RCLK R 7.101 4 2.108 M
|
||||
RDQMH RCLK R 10.733 4 3.351 M
|
||||
RDQML RCLK R 10.683 4 3.364 M
|
||||
RD[0] nCCAS F 8.977 4 3.012 M
|
||||
RD[1] nCCAS F 8.977 4 3.012 M
|
||||
RD[2] nCCAS F 8.977 4 3.012 M
|
||||
RD[3] nCCAS F 8.977 4 3.012 M
|
||||
RD[4] nCCAS F 8.977 4 3.012 M
|
||||
RD[5] nCCAS F 8.977 4 3.012 M
|
||||
RD[6] nCCAS F 8.977 4 3.012 M
|
||||
RD[7] nCCAS F 8.977 4 3.012 M
|
||||
nRCAS RCLK R 7.822 4 2.706 M
|
||||
nRCS RCLK R 7.822 4 2.706 M
|
||||
nRRAS RCLK R 7.822 4 2.706 M
|
||||
nRWE RCLK R 7.803 4 2.713 M
|
||||
WARNING: you must also run trce with hold speed: 4
|
||||
WARNING: you must also run trce with setup speed: M
|
||||
|
||||
|
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
@ -23,7 +23,7 @@ Target Vendor: LATTICE
|
|||
Target Device: LCMXO2-1200HCTQFP100
|
||||
Target Performance: 4
|
||||
Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454
|
||||
Mapped on: 09/21/23 05:39:45
|
||||
Mapped on: 11/18/23 02:05:52
|
||||
|
||||
|
||||
<A name="mrp_ds"></A><B><U><big>Design Summary</big></U></B>
|
||||
|
@ -34,12 +34,24 @@ Mapped on: 09/21/23 05:39:45
|
|||
SLICEs as Logic/ROM: 120 out of 640 (19%)
|
||||
SLICEs as RAM: 0 out of 480 (0%)
|
||||
SLICEs as Carry: 10 out of 640 (2%)
|
||||
Number of LUT4s: 237 out of 1280 (19%)
|
||||
Number used as logic LUTs: 217
|
||||
Number of LUT4s: 238 out of 1280 (19%)
|
||||
Number used as logic LUTs: 218
|
||||
Number used as distributed RAM: 0
|
||||
Number used as ripple logic: 20
|
||||
Number used as shift registers: 0
|
||||
Number of PIO sites used: 63 + 4(JTAG) out of 80 (84%)
|
||||
Number of PIO sites used: 64 + 4(JTAG) out of 80 (85%)
|
||||
Number of IDDR/ODDR/TDDR cells used: 1 out of 240 (0%)
|
||||
Number of IDDR cells: 0
|
||||
Number of ODDR cells: 1
|
||||
Number of TDDR cells: 0
|
||||
Number of PIO using at least one IDDR/ODDR/TDDR: 1 (0 differential)
|
||||
Number of PIO using IDDR only: 0 (0 differential)
|
||||
Number of PIO using ODDR only: 1 (0 differential)
|
||||
Number of PIO using TDDR only: 0 (0 differential)
|
||||
Number of PIO using IDDR/ODDR: 0 (0 differential)
|
||||
Number of PIO using IDDR/TDDR: 0 (0 differential)
|
||||
Number of PIO using ODDR/TDDR: 0 (0 differential)
|
||||
Number of PIO using IDDR/ODDR/TDDR: 0 (0 differential)
|
||||
Number of block RAMs: 0 out of 7 (0%)
|
||||
Number of GSRs: 0 out of 1 (0%)
|
||||
EFB used : Yes
|
||||
|
@ -55,6 +67,7 @@ Mapped on: 09/21/23 05:39:45
|
|||
Number of DCCA: 0 out of 8 (0%)
|
||||
Number of DCMA: 0 out of 2 (0%)
|
||||
Number of PLLs: 0 out of 1 (0%)
|
||||
|
||||
Number of DQSDLLs: 0 out of 2 (0%)
|
||||
Number of CLKDIVC: 0 out of 4 (0%)
|
||||
Number of ECLKSYNCA: 0 out of 4 (0%)
|
||||
|
@ -66,15 +79,14 @@ Mapped on: 09/21/23 05:39:45
|
|||
ripple logic.
|
||||
Number of clocks: 4
|
||||
Net PHI2_c: 20 loads, 9 rising, 11 falling (Driver: PIO PHI2 )
|
||||
Net RCLK_c: 47 loads, 47 rising, 0 falling (Driver: PIO RCLK )
|
||||
|
||||
Net RCLK_c: 48 loads, 48 rising, 0 falling (Driver: PIO RCLK )
|
||||
Net nCRAS_c: 9 loads, 0 rising, 9 falling (Driver: PIO nCRAS )
|
||||
Net nCCAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCCAS )
|
||||
Number of Clock Enables: 5
|
||||
Net N_178: 1 loads, 1 LSLICEs
|
||||
Net wb_cyc_stb_2_sqmuxa_i_0_0: 1 loads, 1 LSLICEs
|
||||
Net XOR8MEG18: 5 loads, 5 LSLICEs
|
||||
Net N_360_i: 2 loads, 2 LSLICEs
|
||||
Net un1_wb_rst14_i_0: 9 loads, 9 LSLICEs
|
||||
Net N_126_i: 9 loads, 9 LSLICEs
|
||||
Net N_261_i: 2 loads, 2 LSLICEs
|
||||
Net CmdUFMData_1_sqmuxa: 1 loads, 1 LSLICEs
|
||||
Number of LSRs: 5
|
||||
Net RA10s_i: 1 loads, 0 LSLICEs
|
||||
|
@ -84,16 +96,16 @@ Mapped on: 09/21/23 05:39:45
|
|||
Net RASr2: 2 loads, 2 LSLICEs
|
||||
Number of nets driven by tri-state buffers: 0
|
||||
Top 10 highest fanout non-clock nets:
|
||||
Net InitReady: 41 loads
|
||||
Net FS[11]: 23 loads
|
||||
Net InitReady: 40 loads
|
||||
Net FS[13]: 22 loads
|
||||
Net FS[10]: 21 loads
|
||||
Net FS[12]: 21 loads
|
||||
Net FS[9]: 20 loads
|
||||
Net FS[14]: 18 loads
|
||||
Net CO0: 15 loads
|
||||
Net FS[11]: 21 loads
|
||||
Net FS[12]: 19 loads
|
||||
Net FS[14]: 19 loads
|
||||
Net FS[10]: 18 loads
|
||||
Net FS[9]: 17 loads
|
||||
Net Ready: 14 loads
|
||||
Net Ready_fast: 14 loads
|
||||
Net N_214: 13 loads
|
||||
Net CO0: 12 loads
|
||||
|
||||
|
||||
|
||||
|
@ -116,6 +128,7 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
|||
|
||||
|
||||
|
||||
|
||||
<A name="mrp_ioa"></A><B><U><big>IO (PIO) Attributes</big></U></B>
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
@ -127,7 +140,6 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
|||
| Dout[0] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| PHI2 | INPUT | LVCMOS33 | IN |
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RDQML | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
@ -141,6 +153,8 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
|||
+---------------------+-----------+-----------+------------+
|
||||
| RCKE | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RCLKout | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RCLK | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRCS | OUTPUT | LVCMOS33 | OUT |
|
||||
|
@ -172,6 +186,7 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
|||
| RA[6] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[5] | OUTPUT | LVCMOS33 | |
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[4] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
@ -184,7 +199,6 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
|||
| RA[0] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RBA[1] | OUTPUT | LVCMOS33 | OUT |
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RBA[0] | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
@ -229,6 +243,7 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
|||
| CROW[1] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| CROW[0] | INPUT | LVCMOS33 | |
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[9] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
@ -241,7 +256,6 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
|||
| MAin[5] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[4] | INPUT | LVCMOS33 | |
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[3] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
@ -260,7 +274,6 @@ Block GSR_INST undriven or does not drive anything - clipped.
|
|||
Signal nCRAS_c_i was merged into signal nCRAS_c
|
||||
Signal RASr2_i was merged into signal RASr2
|
||||
Signal XOR8MEG.CN was merged into signal PHI2_c
|
||||
Signal GND undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/VCC undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/GND undriven or does not drive anything - clipped.
|
||||
Signal FS_s_0_S1[17] undriven or does not drive anything - clipped.
|
||||
|
@ -288,6 +301,7 @@ Signal ufmefb/SPISCKEN undriven or does not drive anything - clipped.
|
|||
Signal ufmefb/SPISCKO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
|
||||
|
||||
Signal ufmefb/I2C2SDAOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SCLOEN undriven or does not drive anything - clipped.
|
||||
|
@ -299,7 +313,6 @@ Signal ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
|
|||
Signal ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
|
||||
|
||||
Signal ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
|
||||
|
@ -326,7 +339,6 @@ Signal N_1 undriven or does not drive anything - clipped.
|
|||
Block nCRAS_pad_RNIBPVB was optimized away.
|
||||
Block RASr2_RNIAFR1 was optimized away.
|
||||
Block XOR8MEG.CN was optimized away.
|
||||
Block GND was optimized away.
|
||||
Block ufmefb/VCC was optimized away.
|
||||
Block ufmefb/GND was optimized away.
|
||||
|
||||
|
@ -347,6 +359,7 @@ Block ufmefb/GND was optimized away.
|
|||
Timer/Counter Mode: WB
|
||||
UFM Connection: ENABLED
|
||||
PLL0 Connection: DISABLED
|
||||
|
||||
PLL1 Connection: DISABLED
|
||||
I2C Function Summary:
|
||||
--------------------
|
||||
|
@ -357,7 +370,6 @@ Block ufmefb/GND was optimized away.
|
|||
Timer/Counter Function Summary:
|
||||
------------------------------
|
||||
None
|
||||
|
||||
UFM Function Summary:
|
||||
--------------------
|
||||
UFM Utilization: General Purpose Flash Memory
|
||||
|
@ -387,7 +399,7 @@ Instance Name: ufmefb/EFBInst_0
|
|||
|
||||
Total CPU Time: 0 secs
|
||||
Total REAL Time: 0 secs
|
||||
Peak Memory Usage: 63 MB
|
||||
Peak Memory Usage: 64 MB
|
||||
|
||||
|
||||
|
||||
|
@ -400,16 +412,6 @@ Instance Name: ufmefb/EFBInst_0
|
|||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
|
@ -14,7 +14,7 @@ Performance Grade: 4
|
|||
PACKAGE: TQFP100
|
||||
Package Status: Final Version 1.44
|
||||
|
||||
Thu Sep 21 05:39:56 2023
|
||||
Sat Nov 18 02:06:05 2023
|
||||
|
||||
Pinout by Port Name:
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
|
@ -63,9 +63,10 @@ Pinout by Port Name:
|
|||
| RA[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[9] | 62/1 | LVCMOS33_OUT | PR5D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RBA[0] | 58/1 | LVCMOS33_OUT | PR9A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RBA[1] | 60/1 | LVCMOS33_OUT | PR8C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RBA[1] | 47/2 | LVCMOS33_OUT | PB18D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RCKE | 53/1 | LVCMOS33_OUT | PR9D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RCLK | 63/1 | LVCMOS33_IN | PR5C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| RCLKout | 60/1 | LVCMOS33_OUT | PR8C | | | DRIVE:24mA SLEW:FAST |
|
||||
| RDQMH | 51/1 | LVCMOS33_OUT | PR10D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RDQML | 48/2 | LVCMOS33_OUT | PB20C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RD[0] | 36/2 | LVCMOS33_BIDI | PB11C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
|
@ -143,7 +144,7 @@ Vccio by Bank:
|
|||
| 42/2 | RD[6] | LOCATED | LVCMOS33_BIDI | PB18A | | | |
|
||||
| 43/2 | RD[7] | LOCATED | LVCMOS33_BIDI | PB18B | | | |
|
||||
| 45/2 | unused, PULL:DOWN | | | PB18C | | | |
|
||||
| 47/2 | unused, PULL:DOWN | | | PB18D | | | |
|
||||
| 47/2 | RBA[1] | LOCATED | LVCMOS33_OUT | PB18D | | | |
|
||||
| 48/2 | RDQML | LOCATED | LVCMOS33_OUT | PB20C | SN | | |
|
||||
| 49/2 | nRWE | LOCATED | LVCMOS33_OUT | PB20D | SI/SISPI | | |
|
||||
| 51/1 | RDQMH | LOCATED | LVCMOS33_OUT | PR10D | DQ1 | | |
|
||||
|
@ -153,7 +154,7 @@ Vccio by Bank:
|
|||
| 57/1 | nRCS | LOCATED | LVCMOS33_OUT | PR9B | DQ1 | | |
|
||||
| 58/1 | RBA[0] | LOCATED | LVCMOS33_OUT | PR9A | DQ1 | | |
|
||||
| 59/1 | RA[11] | LOCATED | LVCMOS33_OUT | PR8D | DQ1 | | |
|
||||
| 60/1 | RBA[1] | LOCATED | LVCMOS33_OUT | PR8C | DQ1 | | |
|
||||
| 60/1 | RCLKout | LOCATED | LVCMOS33_OUT | PR8C | DQ1 | | |
|
||||
| 61/1 | unused, PULL:DOWN | | | PR8A | DQS1 | | |
|
||||
| 62/1 | RA[9] | LOCATED | LVCMOS33_OUT | PR5D | PCLKC1_0/DQ0 | | |
|
||||
| 63/1 | RCLK | LOCATED | LVCMOS33_IN | PR5C | PCLKT1_0/DQ0 | | |
|
||||
|
@ -275,9 +276,10 @@ LOCATE COMP "RA[7]" SITE "75";
|
|||
LOCATE COMP "RA[8]" SITE "65";
|
||||
LOCATE COMP "RA[9]" SITE "62";
|
||||
LOCATE COMP "RBA[0]" SITE "58";
|
||||
LOCATE COMP "RBA[1]" SITE "60";
|
||||
LOCATE COMP "RBA[1]" SITE "47";
|
||||
LOCATE COMP "RCKE" SITE "53";
|
||||
LOCATE COMP "RCLK" SITE "63";
|
||||
LOCATE COMP "RCLKout" SITE "60";
|
||||
LOCATE COMP "RDQMH" SITE "51";
|
||||
LOCATE COMP "RDQML" SITE "48";
|
||||
LOCATE COMP "RD[0]" SITE "36";
|
||||
|
@ -306,7 +308,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Thu Sep 21 05:39:59 2023
|
||||
Sat Nov 18 02:06:09 2023
|
||||
|
||||
|
||||
|
||||
|
|
|
@ -12,7 +12,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Thu Sep 21 05:39:49 2023
|
||||
Sat Nov 18 02:05:57 2023
|
||||
|
||||
C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_1200HC_impl1.p2t
|
||||
RAM2GS_LCMXO2_1200HC_impl1_map.ncd RAM2GS_LCMXO2_1200HC_impl1.dir
|
||||
|
@ -26,17 +26,17 @@ Preference file: RAM2GS_LCMXO2_1200HC_impl1.prf.
|
|||
Level/ Number Worst Timing Worst Timing Run NCD
|
||||
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
|
||||
---------- -------- ----- ------ ----------- ----------- ---- ------
|
||||
5_1 * 0 5.578 0 0.304 0 13 Completed
|
||||
5_1 * 0 6.215 0 0.304 0 15 Completed
|
||||
* : Design saved.
|
||||
|
||||
Total (real) run time for 1-seed: 13 secs
|
||||
Total (real) run time for 1-seed: 15 secs
|
||||
|
||||
par done!
|
||||
|
||||
Note: user must run 'Trace' for timing closure signoff.
|
||||
|
||||
Lattice Place and Route Report for Design "RAM2GS_LCMXO2_1200HC_impl1_map.ncd"
|
||||
Thu Sep 21 05:39:49 2023
|
||||
Sat Nov 18 02:05:57 2023
|
||||
|
||||
|
||||
<A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
|
||||
|
@ -63,23 +63,23 @@ Ignore Preference Error(s): True
|
|||
|
||||
<A name="par_dus"></A><B><U><big>Device utilization summary:</big></U></B>
|
||||
|
||||
PIO (prelim) 63+4(JTAG)/108 62% used
|
||||
63+4(JTAG)/80 84% bonded
|
||||
IOLOGIC 25/108 23% used
|
||||
PIO (prelim) 64+4(JTAG)/108 63% used
|
||||
64+4(JTAG)/80 85% bonded
|
||||
IOLOGIC 26/108 24% used
|
||||
|
||||
SLICE 120/640 18% used
|
||||
|
||||
EFB 1/1 100% used
|
||||
|
||||
|
||||
Number of Signals: 388
|
||||
Number of Connections: 1017
|
||||
Number of Signals: 389
|
||||
Number of Connections: 1011
|
||||
|
||||
Pin Constraint Summary:
|
||||
63 out of 63 pins locked (100% locked).
|
||||
64 out of 64 pins locked (100% locked).
|
||||
|
||||
The following 2 signals are selected to use the primary clock routing resources:
|
||||
RCLK_c (driver: RCLK, clk load #: 47)
|
||||
RCLK_c (driver: RCLK, clk load #: 48)
|
||||
PHI2_c (driver: PHI2, clk load #: 20)
|
||||
|
||||
WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
|
@ -97,13 +97,13 @@ Finished Placer Phase 0. REAL time: 0 secs
|
|||
|
||||
Starting Placer Phase 1.
|
||||
....................
|
||||
Placer score = 68062.
|
||||
Finished Placer Phase 1. REAL time: 7 secs
|
||||
Placer score = 71673.
|
||||
Finished Placer Phase 1. REAL time: 8 secs
|
||||
|
||||
Starting Placer Phase 2.
|
||||
.
|
||||
Placer score = 67096
|
||||
Finished Placer Phase 2. REAL time: 7 secs
|
||||
Placer score = 70957
|
||||
Finished Placer Phase 2. REAL time: 8 secs
|
||||
|
||||
|
||||
|
||||
|
@ -117,7 +117,7 @@ Global Clock Resources:
|
|||
DCC : 0 out of 8 (0%)
|
||||
|
||||
Global Clocks:
|
||||
PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "63 (PR5C)", clk load = 47
|
||||
PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "63 (PR5C)", clk load = 48
|
||||
PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3D)", clk load = 20
|
||||
SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL8B)", clk load = 9, ce load = 0, sr load = 0
|
||||
SECONDARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL4A)", clk load = 8, ce load = 0, sr load = 0
|
||||
|
@ -132,9 +132,9 @@ Edge Clocks:
|
|||
|
||||
|
||||
I/O Usage Summary (final):
|
||||
63 + 4(JTAG) out of 108 (62.0%) PIO sites used.
|
||||
63 + 4(JTAG) out of 80 (83.8%) bonded PIO sites used.
|
||||
Number of PIO comps: 63; differential: 0.
|
||||
64 + 4(JTAG) out of 108 (63.0%) PIO sites used.
|
||||
64 + 4(JTAG) out of 80 (85.0%) bonded PIO sites used.
|
||||
Number of PIO comps: 64; differential: 0.
|
||||
Number of Vref pins used: 0.
|
||||
|
||||
I/O Bank Usage Summary:
|
||||
|
@ -143,20 +143,20 @@ I/O Bank Usage Summary:
|
|||
+----------+----------------+------------+-----------+
|
||||
| 0 | 13 / 19 ( 68%) | 3.3V | - |
|
||||
| 1 | 20 / 21 ( 95%) | 3.3V | - |
|
||||
| 2 | 12 / 20 ( 60%) | 3.3V | - |
|
||||
| 2 | 13 / 20 ( 65%) | 3.3V | - |
|
||||
| 3 | 18 / 20 ( 90%) | 3.3V | - |
|
||||
+----------+----------------+------------+-----------+
|
||||
|
||||
Total placer CPU time: 6 secs
|
||||
Total placer CPU time: 8 secs
|
||||
|
||||
Dumping design to file RAM2GS_LCMXO2_1200HC_impl1.dir/5_1.ncd.
|
||||
|
||||
0 connections routed; 1017 unrouted.
|
||||
0 connections routed; 1011 unrouted.
|
||||
Starting router resource preassignment
|
||||
|
||||
Completed router resource preassignment. Real time: 11 secs
|
||||
Completed router resource preassignment. Real time: 13 secs
|
||||
|
||||
Start NBR router at 05:40:00 09/21/23
|
||||
Start NBR router at 02:06:10 11/18/23
|
||||
|
||||
*****************************************************************
|
||||
Info: NBR allows conflicts(one node used by more than one signal)
|
||||
|
@ -171,41 +171,41 @@ Note: NBR uses a different method to calculate timing slacks. The
|
|||
your design.
|
||||
*****************************************************************
|
||||
|
||||
Start NBR special constraint process at 05:40:00 09/21/23
|
||||
Start NBR special constraint process at 02:06:10 11/18/23
|
||||
|
||||
Start NBR section for initial routing at 05:40:01 09/21/23
|
||||
Start NBR section for initial routing at 02:06:11 11/18/23
|
||||
Level 1, iteration 1
|
||||
0(0.00%) conflict; 822(80.83%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 6.089ns/0.000ns; real time: 12 secs
|
||||
0(0.00%) conflict; 814(80.51%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 5.987ns/0.000ns; real time: 14 secs
|
||||
Level 2, iteration 1
|
||||
0(0.00%) conflict; 822(80.83%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 6.089ns/0.000ns; real time: 12 secs
|
||||
0(0.00%) conflict; 803(79.43%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 6.236ns/0.000ns; real time: 14 secs
|
||||
Level 3, iteration 1
|
||||
0(0.00%) conflict; 822(80.83%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 6.089ns/0.000ns; real time: 12 secs
|
||||
0(0.00%) conflict; 803(79.43%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 5.836ns/0.000ns; real time: 14 secs
|
||||
Level 4, iteration 1
|
||||
5(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 5.578ns/0.000ns; real time: 12 secs
|
||||
16(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 6.236ns/0.000ns; real time: 14 secs
|
||||
|
||||
Info: Initial congestion level at 75% usage is 0
|
||||
Info: Initial congestion area at 75% usage is 0 (0.00%)
|
||||
|
||||
Start NBR section for normal routing at 05:40:01 09/21/23
|
||||
Start NBR section for normal routing at 02:06:11 11/18/23
|
||||
Level 4, iteration 1
|
||||
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 5.578ns/0.000ns; real time: 12 secs
|
||||
3(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 6.222ns/0.000ns; real time: 14 secs
|
||||
Level 4, iteration 2
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 5.578ns/0.000ns; real time: 12 secs
|
||||
Estimated worst slack/total negative slack<setup>: 6.215ns/0.000ns; real time: 14 secs
|
||||
|
||||
Start NBR section for setup/hold timing optimization with effort level 3 at 05:40:01 09/21/23
|
||||
Start NBR section for setup/hold timing optimization with effort level 3 at 02:06:11 11/18/23
|
||||
|
||||
Start NBR section for re-routing at 05:40:01 09/21/23
|
||||
Start NBR section for re-routing at 02:06:11 11/18/23
|
||||
Level 4, iteration 1
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 5.578ns/0.000ns; real time: 12 secs
|
||||
Estimated worst slack/total negative slack<setup>: 6.215ns/0.000ns; real time: 14 secs
|
||||
|
||||
Start NBR section for post-routing at 05:40:01 09/21/23
|
||||
Start NBR section for post-routing at 02:06:11 11/18/23
|
||||
|
||||
End NBR router with 0 unrouted connection
|
||||
|
||||
|
@ -213,17 +213,17 @@ NBR Summary
|
|||
-----------
|
||||
Number of unrouted connections : 0 (0.00%)
|
||||
Number of connections with timing violations : 0 (0.00%)
|
||||
Estimated worst slack<setup> : 5.578ns
|
||||
Estimated worst slack<setup> : 6.215ns
|
||||
Timing score<setup> : 0
|
||||
-----------
|
||||
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
|
||||
|
||||
|
||||
|
||||
Total CPU time 12 secs
|
||||
Total REAL time: 13 secs
|
||||
Total CPU time 14 secs
|
||||
Total REAL time: 15 secs
|
||||
Completely routed.
|
||||
End of route. 1017 routed (100.00%); 0 unrouted.
|
||||
End of route. 1011 routed (100.00%); 0 unrouted.
|
||||
|
||||
Hold time timing score: 0, hold timing errors: 0
|
||||
|
||||
|
@ -237,14 +237,14 @@ All signals are completely routed.
|
|||
|
||||
PAR_SUMMARY::Run status = Completed
|
||||
PAR_SUMMARY::Number of unrouted conns = 0
|
||||
PAR_SUMMARY::Worst slack<setup/<ns>> = 5.578
|
||||
PAR_SUMMARY::Worst slack<setup/<ns>> = 6.215
|
||||
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
|
||||
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.304
|
||||
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
|
||||
PAR_SUMMARY::Number of errors = 0
|
||||
|
||||
Total CPU time to completion: 13 secs
|
||||
Total REAL time to completion: 13 secs
|
||||
Total CPU time to completion: 15 secs
|
||||
Total REAL time to completion: 15 secs
|
||||
|
||||
par done!
|
||||
|
||||
|
|
|
@ -13,7 +13,7 @@ Hostname: ZANEMACWIN11
|
|||
|
||||
Implementation : impl1
|
||||
|
||||
# Written on Thu Sep 21 05:39:37 2023
|
||||
# Written on Sat Nov 18 02:05:43 2023
|
||||
|
||||
##### FILES SYNTAX CHECKED ##############################################
|
||||
Constraint File(s): "\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS.sdc"
|
||||
|
|
|
@ -24,9 +24,9 @@
|
|||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Last Process:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">JEDEC File</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000"></SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">State:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">Passed</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000"></SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Target Device:</SPAN></TD>
|
||||
|
@ -62,7 +62,7 @@
|
|||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Updated:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2023/09/21 05:40:22</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2023/11/18 02:59:50</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Location:</SPAN></TD>
|
||||
|
|
|
@ -12,7 +12,7 @@
|
|||
#OS: Windows 8 6.2
|
||||
#Hostname: ZANEMACWIN11
|
||||
|
||||
# Thu Sep 21 05:39:34 2023
|
||||
# Sat Nov 18 02:05:40 2023
|
||||
|
||||
#Implementation: impl1
|
||||
|
||||
|
@ -60,13 +60,17 @@ Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 202
|
|||
@I::"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v" (library work)
|
||||
@I::"\\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC\REFB.v" (library work)
|
||||
Verilog syntax check successful!
|
||||
File \\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v changed - recompiling
|
||||
Selecting top level module RAM2GS
|
||||
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1601:7:1601:12|Synthesizing module ODDRXE in library work.
|
||||
Running optimization stage 1 on ODDRXE .......
|
||||
Finished optimization stage 1 on ODDRXE (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
|
||||
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
|
||||
Running optimization stage 1 on VHI .......
|
||||
Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 98MB)
|
||||
Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
|
||||
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
|
||||
Running optimization stage 1 on VLO .......
|
||||
Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
|
||||
Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
|
||||
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
|
||||
Running optimization stage 1 on EFB .......
|
||||
Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
|
||||
|
@ -86,13 +90,15 @@ Running optimization stage 2 on VLO .......
|
|||
Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
|
||||
Running optimization stage 2 on VHI .......
|
||||
Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
|
||||
Running optimization stage 2 on ODDRXE .......
|
||||
Finished optimization stage 2 on ODDRXE (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
|
||||
|
||||
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)
|
||||
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 102MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:39:35 2023
|
||||
# Sat Nov 18 02:05:41 2023
|
||||
|
||||
###########################################################]
|
||||
###########################################################[
|
||||
|
@ -119,7 +125,7 @@ At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s;
|
|||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:39:35 2023
|
||||
# Sat Nov 18 02:05:41 2023
|
||||
|
||||
###########################################################]
|
||||
|
||||
|
@ -134,7 +140,7 @@ At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory
|
|||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:39:35 2023
|
||||
# Sat Nov 18 02:05:41 2023
|
||||
|
||||
###########################################################]
|
||||
###########################################################[
|
||||
|
@ -155,18 +161,17 @@ Implementation : impl1
|
|||
Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
File \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2GS_LCMXO2_1200HC_impl1_comp.srs changed - recompiling
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:39:36 2023
|
||||
# Sat Nov 18 02:05:43 2023
|
||||
|
||||
###########################################################]
|
||||
Premap Report
|
||||
|
||||
# Thu Sep 21 05:39:37 2023
|
||||
# Sat Nov 18 02:05:43 2023
|
||||
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
|
@ -185,10 +190,10 @@ Implementation : impl1
|
|||
Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @
|
||||
|
||||
|
||||
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
|
||||
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
|
||||
|
||||
|
||||
Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 140MB)
|
||||
Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 140MB)
|
||||
|
||||
Reading constraint file: \\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS.sdc
|
||||
@L: \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC\impl1\RAM2GS_LCMXO2_1200HC_impl1_scck.rpt
|
||||
|
@ -212,7 +217,6 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h
|
|||
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
|
||||
@N: FX493 |Applying initial value "0" on instance Ready.
|
||||
@N: FX493 |Applying initial value "0" on instance RCKE.
|
||||
@N: FX493 |Applying initial value "0" on instance LEDEN.
|
||||
@N: FX493 |Applying initial value "0" on instance n8MEGEN.
|
||||
@N: FX493 |Applying initial value "1" on instance nRCAS.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdLEDEN.
|
||||
|
@ -232,17 +236,17 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h
|
|||
Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
|
||||
|
||||
|
||||
Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
|
||||
Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
|
||||
|
||||
|
||||
Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 181MB peak: 182MB)
|
||||
Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
|
||||
|
||||
|
||||
Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
|
||||
Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
|
||||
|
||||
@N: FX1184 |Applying syn_allowed_resources blockrams=7 on top level netlist RAM2GS
|
||||
|
||||
Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
|
||||
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
|
||||
|
||||
|
||||
|
||||
|
@ -323,15 +327,13 @@ Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:0
|
|||
|
||||
Pre-mapping successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 103MB peak: 185MB)
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 99MB peak: 185MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Thu Sep 21 05:39:38 2023
|
||||
# Sat Nov 18 02:05:44 2023
|
||||
|
||||
###########################################################]
|
||||
Map & Optimize Report
|
||||
|
||||
# Thu Sep 21 05:39:39 2023
|
||||
# Sat Nov 18 02:05:44 2023
|
||||
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
|
@ -372,10 +374,10 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h
|
|||
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 179MB peak: 179MB)
|
||||
|
||||
|
||||
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB)
|
||||
Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB)
|
||||
|
||||
@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":163:4:163:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0]
|
||||
@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":150:4:150:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0]
|
||||
@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":166:4:166:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0]
|
||||
@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":153:4:153:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0]
|
||||
@N: FX493 |Applying initial value "0" on instance IS[0].
|
||||
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
|
||||
@N: FX493 |Applying initial value "0" on instance IS[1].
|
||||
|
@ -385,7 +387,7 @@ Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00
|
|||
Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 185MB peak: 185MB)
|
||||
|
||||
|
||||
Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 187MB peak: 187MB)
|
||||
Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB)
|
||||
|
||||
|
||||
Available hyper_sources - for debug and ip models
|
||||
|
@ -407,16 +409,16 @@ Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CP
|
|||
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
|
||||
|
||||
|
||||
Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 197MB peak: 197MB)
|
||||
Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 197MB peak: 197MB)
|
||||
|
||||
Pass CPU time Worst Slack Luts / Registers
|
||||
------------------------------------------------------------
|
||||
1 0h:00m:01s -2.98ns 201 / 106
|
||||
2 0h:00m:01s -2.98ns 217 / 106
|
||||
3 0h:00m:01s -2.76ns 215 / 106
|
||||
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":121:4:121:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 6 loads 1 time to improve timing.
|
||||
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":304:4:304:9|Replicating instance CmdValid (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.
|
||||
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":163:4:163:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 11 loads 1 time to improve timing.
|
||||
1 0h:00m:02s -2.98ns 202 / 106
|
||||
2 0h:00m:02s -2.98ns 215 / 106
|
||||
3 0h:00m:02s -2.76ns 215 / 106
|
||||
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":124:4:124:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 6 loads 1 time to improve timing.
|
||||
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":307:4:307:9|Replicating instance CmdValid (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.
|
||||
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":166:4:166:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 12 loads 1 time to improve timing.
|
||||
Timing driven replication report
|
||||
Added 3 Registers via timing driven replication
|
||||
Added 1 LUTs via timing driven replication
|
||||
|
@ -433,7 +435,7 @@ Finished technology timing optimizations and critical path resynthesis (Real Tim
|
|||
Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 198MB peak: 198MB)
|
||||
|
||||
|
||||
Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 160MB peak: 198MB)
|
||||
Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 160MB peak: 198MB)
|
||||
|
||||
Writing Analyst data base \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2GS_LCMXO2_1200HC_impl1_m.srm
|
||||
|
||||
|
@ -443,14 +445,15 @@ Writing EDIF Netlist and constraint files
|
|||
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-1200HC\impl1\RAM2GS_LCMXO2_1200HC_impl1.edi
|
||||
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
|
||||
|
||||
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 203MB peak: 203MB)
|
||||
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 203MB peak: 203MB)
|
||||
|
||||
|
||||
Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 203MB peak: 203MB)
|
||||
Finished Writing Netlists (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 203MB peak: 203MB)
|
||||
|
||||
|
||||
Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 201MB peak: 203MB)
|
||||
|
||||
@W: MT246 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":43:11:43:19|Blackbox ODDRXE is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
|
||||
@W: MT246 :"\\mac\icloud\repos\ram2gs\cpld\lcmxo2-1200hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
|
||||
@N: MT615 |Found clock RCLK with period 16.00ns
|
||||
@N: MT615 |Found clock PHI2 with period 350.00ns
|
||||
|
@ -459,7 +462,7 @@ Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:0
|
|||
|
||||
|
||||
##### START OF TIMING REPORT #####[
|
||||
# Timing report written on Thu Sep 21 05:39:43 2023
|
||||
# Timing report written on Sat Nov 18 02:05:49 2023
|
||||
#
|
||||
|
||||
|
||||
|
@ -510,7 +513,7 @@ Starting Ending | constraint slack | constraint slack | constraint
|
|||
---------------------------------------------------------------------------------------------------------------
|
||||
System RCLK | 16.000 12.918 | No paths - | No paths - | No paths -
|
||||
RCLK System | 16.000 14.956 | No paths - | No paths - | No paths -
|
||||
RCLK RCLK | 16.000 9.040 | No paths - | No paths - | No paths -
|
||||
RCLK RCLK | 16.000 9.237 | No paths - | No paths - | No paths -
|
||||
RCLK PHI2 | 2.000 0.216 | No paths - | 1.000 -0.676 | No paths -
|
||||
RCLK nCRAS | No paths - | No paths - | 1.000 -0.784 | No paths -
|
||||
PHI2 RCLK | No paths - | No paths - | No paths - | 1.000 -1.828
|
||||
|
@ -549,30 +552,30 @@ CmdLEDEN PHI2 FD1P3AX Q CmdLEDEN 1.044
|
|||
Cmdn8MEGEN PHI2 FD1P3AX Q Cmdn8MEGEN 1.044 -1.589
|
||||
CmdUFMWrite PHI2 FD1P3AX Q CmdUFMWrite 1.044 -0.572
|
||||
CmdUFMData PHI2 FD1P3AX Q CmdUFMData 0.972 -0.500
|
||||
Bank_0io[0] PHI2 IFS1P3DX Q Bank[0] 0.972 169.081
|
||||
Bank_0io[1] PHI2 IFS1P3DX Q Bank[1] 0.972 169.081
|
||||
Bank_0io[2] PHI2 IFS1P3DX Q Bank[2] 0.972 169.081
|
||||
Bank_0io[3] PHI2 IFS1P3DX Q Bank[3] 0.972 169.081
|
||||
==========================================================================================
|
||||
|
||||
|
||||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
-----------------------------------------------------------------------------------------
|
||||
wb_adr[0] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
|
||||
wb_adr[1] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
|
||||
wb_adr[2] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
|
||||
wb_adr[3] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
|
||||
wb_adr[4] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
|
||||
wb_adr[5] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
|
||||
wb_adr[6] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
|
||||
wb_adr[7] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
|
||||
wb_dati[0] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
|
||||
wb_dati[1] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
|
||||
=========================================================================================
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
--------------------------------------------------------------------------------
|
||||
wb_adr[0] PHI2 FD1P3AX SP N_126_i 0.528 -1.828
|
||||
wb_adr[1] PHI2 FD1P3AX SP N_126_i 0.528 -1.828
|
||||
wb_adr[2] PHI2 FD1P3AX SP N_126_i 0.528 -1.828
|
||||
wb_adr[3] PHI2 FD1P3AX SP N_126_i 0.528 -1.828
|
||||
wb_adr[4] PHI2 FD1P3AX SP N_126_i 0.528 -1.828
|
||||
wb_adr[5] PHI2 FD1P3AX SP N_126_i 0.528 -1.828
|
||||
wb_adr[6] PHI2 FD1P3AX SP N_126_i 0.528 -1.828
|
||||
wb_adr[7] PHI2 FD1P3AX SP N_126_i 0.528 -1.828
|
||||
wb_dati[0] PHI2 FD1P3AX SP N_126_i 0.528 -1.828
|
||||
wb_dati[1] PHI2 FD1P3AX SP N_126_i 0.528 -1.828
|
||||
================================================================================
|
||||
|
||||
|
||||
|
||||
|
@ -603,7 +606,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r -
|
|||
CmdUFMShift Net - - - - 2
|
||||
CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r -
|
||||
CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r -
|
||||
un1_wb_rst14_i_0 Net - - - - 17
|
||||
N_126_i Net - - - - 17
|
||||
wb_adr[0] FD1P3AX SP In 0.000 2.357 r -
|
||||
=========================================================================================
|
||||
|
||||
|
@ -631,7 +634,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r -
|
|||
CmdUFMShift Net - - - - 2
|
||||
CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r -
|
||||
CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r -
|
||||
un1_wb_rst14_i_0 Net - - - - 17
|
||||
N_126_i Net - - - - 17
|
||||
wb_adr[7] FD1P3AX SP In 0.000 2.357 r -
|
||||
=========================================================================================
|
||||
|
||||
|
@ -659,7 +662,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r -
|
|||
CmdUFMShift Net - - - - 2
|
||||
CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r -
|
||||
CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r -
|
||||
un1_wb_rst14_i_0 Net - - - - 17
|
||||
N_126_i Net - - - - 17
|
||||
wb_adr[6] FD1P3AX SP In 0.000 2.357 r -
|
||||
=========================================================================================
|
||||
|
||||
|
@ -687,7 +690,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r -
|
|||
CmdUFMShift Net - - - - 2
|
||||
CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r -
|
||||
CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r -
|
||||
un1_wb_rst14_i_0 Net - - - - 17
|
||||
N_126_i Net - - - - 17
|
||||
wb_adr[5] FD1P3AX SP In 0.000 2.357 r -
|
||||
=========================================================================================
|
||||
|
||||
|
@ -715,7 +718,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r -
|
|||
CmdUFMShift Net - - - - 2
|
||||
CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r -
|
||||
CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r -
|
||||
un1_wb_rst14_i_0 Net - - - - 17
|
||||
N_126_i Net - - - - 17
|
||||
wb_adr[4] FD1P3AX SP In 0.000 2.357 r -
|
||||
=========================================================================================
|
||||
|
||||
|
@ -738,13 +741,13 @@ Instance Reference Type Pin Net Time Slac
|
|||
Ready_fast RCLK FD1S3AX Q Ready_fast 1.256 -0.784
|
||||
LEDEN RCLK FD1S3AX Q LEDEN 1.148 -0.676
|
||||
n8MEGEN RCLK FD1S3AX Q n8MEGEN 1.108 -0.636
|
||||
IS[1] RCLK FD1P3AX Q IS[1] 1.204 9.040
|
||||
IS[2] RCLK FD1P3AX Q IS[2] 1.188 9.056
|
||||
IS[3] RCLK FD1P3AX Q IS[3] 1.148 9.096
|
||||
InitReady RCLK FD1S3AX Q InitReady 1.339 9.228
|
||||
FS[15] RCLK FD1S3AX Q FS[15] 1.228 9.339
|
||||
FS[16] RCLK FD1S3AX Q FS[16] 1.188 9.379
|
||||
FS[17] RCLK FD1S3AX Q FS[17] 1.188 9.379
|
||||
InitReady RCLK FD1S3AX Q InitReady 1.337 9.237
|
||||
FS[16] RCLK FD1S3AX Q FS[16] 1.204 9.371
|
||||
FS[17] RCLK FD1S3AX Q FS[17] 1.204 9.371
|
||||
FS[15] RCLK FD1S3AX Q FS[15] 1.188 9.387
|
||||
S[0] RCLK FD1S3IX Q CO0 1.244 9.873
|
||||
S[1] RCLK FD1S3IX Q S[1] 1.236 9.881
|
||||
RASr2 RCLK FD1S3AX Q RASr2 1.228 9.889
|
||||
==================================================================================
|
||||
|
||||
|
||||
|
@ -841,7 +844,35 @@ Path information for path number 3:
|
|||
|
||||
Number of logic level(s): 1
|
||||
Starting point: Ready_fast / Q
|
||||
Ending point: RowA[0] / D
|
||||
Ending point: RBA_0io[1] / D
|
||||
The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
|
||||
The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin SCLK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
---------------------------------------------------------------------------------
|
||||
Ready_fast FD1S3AX Q Out 1.256 1.256 r -
|
||||
Ready_fast Net - - - - 14
|
||||
RBAd[1] ORCALUT4 B In 0.000 1.256 r -
|
||||
RBAd[1] ORCALUT4 Z Out 0.617 1.873 r -
|
||||
RBAd_0[1] Net - - - - 1
|
||||
RBA_0io[1] OFS1P3DX D In 0.000 1.873 r -
|
||||
=================================================================================
|
||||
|
||||
|
||||
Path information for path number 4:
|
||||
Requested Period: 1.000
|
||||
- Setup time: -0.089
|
||||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
= Required time: 1.089
|
||||
|
||||
- Propagation time: 1.873
|
||||
- Clock delay at starting point: 0.000 (ideal)
|
||||
= Slack (non-critical) : -0.784
|
||||
|
||||
Number of logic level(s): 1
|
||||
Starting point: Ready_fast / Q
|
||||
Ending point: RowA[1] / D
|
||||
The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
|
||||
The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
|
||||
|
||||
|
@ -850,14 +881,14 @@ Name Type Name Dir Delay Time Fan Out(s
|
|||
---------------------------------------------------------------------------------
|
||||
Ready_fast FD1S3AX Q Out 1.256 1.256 r -
|
||||
Ready_fast Net - - - - 14
|
||||
RowAd[0] ORCALUT4 B In 0.000 1.256 r -
|
||||
RowAd[0] ORCALUT4 Z Out 0.617 1.873 r -
|
||||
RowAd_0[0] Net - - - - 1
|
||||
RowA[0] FD1S3AX D In 0.000 1.873 r -
|
||||
RowAd[1] ORCALUT4 B In 0.000 1.256 r -
|
||||
RowAd[1] ORCALUT4 Z Out 0.617 1.873 r -
|
||||
RowAd_0[1] Net - - - - 1
|
||||
RowA[1] FD1S3AX D In 0.000 1.873 r -
|
||||
=================================================================================
|
||||
|
||||
|
||||
Path information for path number 4:
|
||||
Path information for path number 5:
|
||||
Requested Period: 1.000
|
||||
- Setup time: -0.089
|
||||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
|
@ -885,34 +916,6 @@ RowA[5] FD1S3AX D In 0.000 1.873 f -
|
|||
=================================================================================
|
||||
|
||||
|
||||
Path information for path number 5:
|
||||
Requested Period: 1.000
|
||||
- Setup time: -0.089
|
||||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
= Required time: 1.089
|
||||
|
||||
- Propagation time: 1.873
|
||||
- Clock delay at starting point: 0.000 (ideal)
|
||||
= Slack (non-critical) : -0.784
|
||||
|
||||
Number of logic level(s): 1
|
||||
Starting point: Ready_fast / Q
|
||||
Ending point: RowA[8] / D
|
||||
The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
|
||||
The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
---------------------------------------------------------------------------------
|
||||
Ready_fast FD1S3AX Q Out 1.256 1.256 r -
|
||||
Ready_fast Net - - - - 14
|
||||
RowAd[8] ORCALUT4 B In 0.000 1.256 r -
|
||||
RowAd[8] ORCALUT4 Z Out 0.617 1.873 r -
|
||||
RowAd_0[8] Net - - - - 1
|
||||
RowA[8] FD1S3AX D In 0.000 1.873 r -
|
||||
=================================================================================
|
||||
|
||||
|
||||
|
||||
|
||||
====================================
|
||||
|
@ -937,16 +940,16 @@ FWEr nCRAS FD1S3AX Q FWEr 1.180 -1.797
|
|||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
------------------------------------------------------------------------------------------
|
||||
nRCAS_0io nCRAS OFS1P3BX D N_248_i 1.089 -2.605
|
||||
nRCS_0io nCRAS OFS1P3BX D N_247_i 1.089 -1.797
|
||||
nRWE_0io nCRAS OFS1P3BX D N_49_i 1.089 -1.797
|
||||
nRowColSel nCRAS FD1S3IX D nRowColSel_0_0_0 1.089 -1.797
|
||||
RCKEEN nCRAS FD1S3AX D RCKEEN_8 1.089 -1.725
|
||||
==========================================================================================
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------------------
|
||||
nRCAS_0io nCRAS OFS1P3BX D N_251_i 1.089 -2.605
|
||||
nRCS_0io nCRAS OFS1P3BX D N_37_i 1.089 -1.797
|
||||
nRWE_0io nCRAS OFS1P3BX D N_252_i 1.089 -1.797
|
||||
nRowColSel nCRAS FD1S3IX D nRowColSel_0_0 1.089 -1.797
|
||||
RCKEEN nCRAS FD1S3AX D RCKEEN_8 1.089 -1.725
|
||||
========================================================================================
|
||||
|
||||
|
||||
|
||||
|
@ -980,10 +983,10 @@ CBR_fast_RNIQ31K1 ORCALUT4 Z Out 1.089 2.061 r -
|
|||
nRCAS_0_sqmuxa_1 Net - - - - 2
|
||||
nRCAS_0io_RNO_0 ORCALUT4 B In 0.000 2.061 r -
|
||||
nRCAS_0io_RNO_0 ORCALUT4 Z Out 1.017 3.077 r -
|
||||
N_248_i_sx Net - - - - 1
|
||||
nRCAS_0io_RNO ORCALUT4 D In 0.000 3.077 r -
|
||||
N_251_i_sx Net - - - - 1
|
||||
nRCAS_0io_RNO ORCALUT4 C In 0.000 3.077 r -
|
||||
nRCAS_0io_RNO ORCALUT4 Z Out 0.617 3.694 f -
|
||||
N_248_i Net - - - - 1
|
||||
N_251_i Net - - - - 1
|
||||
nRCAS_0io OFS1P3BX D In 0.000 3.694 f -
|
||||
====================================================================================
|
||||
|
||||
|
@ -1004,19 +1007,19 @@ Path information for path number 2:
|
|||
The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
|
||||
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
--------------------------------------------------------------------------------------
|
||||
CBR FD1S3AX Q Out 1.180 1.180 r -
|
||||
CBR Net - - - - 5
|
||||
RCKEEN_8_u_0_0_a2_2 ORCALUT4 A In 0.000 1.180 r -
|
||||
RCKEEN_8_u_0_0_a2_2 ORCALUT4 Z Out 1.089 2.269 f -
|
||||
N_590 Net - - - - 2
|
||||
nRCS_0io_RNO ORCALUT4 C In 0.000 2.269 f -
|
||||
nRCS_0io_RNO ORCALUT4 Z Out 0.617 2.885 r -
|
||||
N_247_i Net - - - - 1
|
||||
nRCS_0io OFS1P3BX D In 0.000 2.885 r -
|
||||
======================================================================================
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
------------------------------------------------------------------------------------
|
||||
CBR FD1S3AX Q Out 1.180 1.180 r -
|
||||
CBR Net - - - - 5
|
||||
RCKEEN_8_u_0_a2_2 ORCALUT4 A In 0.000 1.180 r -
|
||||
RCKEEN_8_u_0_a2_2 ORCALUT4 Z Out 1.089 2.269 f -
|
||||
N_141 Net - - - - 2
|
||||
nRCS_0io_RNO ORCALUT4 A In 0.000 2.269 f -
|
||||
nRCS_0io_RNO ORCALUT4 Z Out 0.617 2.885 r -
|
||||
N_37_i Net - - - - 1
|
||||
nRCS_0io OFS1P3BX D In 0.000 2.885 r -
|
||||
====================================================================================
|
||||
|
||||
|
||||
Path information for path number 3:
|
||||
|
@ -1035,19 +1038,19 @@ Path information for path number 3:
|
|||
The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
|
||||
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
---------------------------------------------------------------------------------
|
||||
FWEr FD1S3AX Q Out 1.180 1.180 r -
|
||||
FWEr Net - - - - 5
|
||||
nRCAS_r_i_0_a2 ORCALUT4 B In 0.000 1.180 r -
|
||||
nRCAS_r_i_0_a2 ORCALUT4 Z Out 1.089 2.269 f -
|
||||
N_248_i_1_0 Net - - - - 2
|
||||
nRCAS_0io_RNO ORCALUT4 C In 0.000 2.269 f -
|
||||
nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.885 r -
|
||||
N_248_i Net - - - - 1
|
||||
nRCAS_0io OFS1P3BX D In 0.000 2.885 r -
|
||||
=================================================================================
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
----------------------------------------------------------------------------------
|
||||
FWEr FD1S3AX Q Out 1.180 1.180 r -
|
||||
FWEr Net - - - - 5
|
||||
nRCS_9_u_i_a2_0 ORCALUT4 B In 0.000 1.180 r -
|
||||
nRCS_9_u_i_a2_0 ORCALUT4 Z Out 1.089 2.269 f -
|
||||
N_251_i_1 Net - - - - 2
|
||||
nRCAS_0io_RNO ORCALUT4 A In 0.000 2.269 f -
|
||||
nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.885 r -
|
||||
N_251_i Net - - - - 1
|
||||
nRCAS_0io OFS1P3BX D In 0.000 2.885 r -
|
||||
==================================================================================
|
||||
|
||||
|
||||
Path information for path number 4:
|
||||
|
@ -1066,19 +1069,19 @@ Path information for path number 4:
|
|||
The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
|
||||
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
--------------------------------------------------------------------------------------
|
||||
CBR FD1S3AX Q Out 1.180 1.180 r -
|
||||
CBR Net - - - - 5
|
||||
RCKEEN_8_u_0_0_a2_2 ORCALUT4 A In 0.000 1.180 r -
|
||||
RCKEEN_8_u_0_0_a2_2 ORCALUT4 Z Out 1.089 2.269 f -
|
||||
N_590 Net - - - - 2
|
||||
nRWE_0io_RNO ORCALUT4 B In 0.000 2.269 f -
|
||||
nRWE_0io_RNO ORCALUT4 Z Out 0.617 2.885 r -
|
||||
N_49_i Net - - - - 1
|
||||
nRWE_0io OFS1P3BX D In 0.000 2.885 r -
|
||||
======================================================================================
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
------------------------------------------------------------------------------------
|
||||
CBR FD1S3AX Q Out 1.180 1.180 r -
|
||||
CBR Net - - - - 5
|
||||
RCKEEN_8_u_0_a2_2 ORCALUT4 A In 0.000 1.180 r -
|
||||
RCKEEN_8_u_0_a2_2 ORCALUT4 Z Out 1.089 2.269 f -
|
||||
N_141 Net - - - - 2
|
||||
nRWE_0io_RNO ORCALUT4 B In 0.000 2.269 f -
|
||||
nRWE_0io_RNO ORCALUT4 Z Out 0.617 2.885 r -
|
||||
N_252_i Net - - - - 1
|
||||
nRWE_0io OFS1P3BX D In 0.000 2.885 r -
|
||||
====================================================================================
|
||||
|
||||
|
||||
Path information for path number 5:
|
||||
|
@ -1102,12 +1105,12 @@ Name Type Name Dir Delay Time Fan
|
|||
--------------------------------------------------------------------------------------
|
||||
FWEr FD1S3AX Q Out 1.180 1.180 r -
|
||||
FWEr Net - - - - 5
|
||||
nRowColSel_0_0_0_a2 ORCALUT4 B In 0.000 1.180 r -
|
||||
nRowColSel_0_0_0_a2 ORCALUT4 Z Out 1.089 2.269 r -
|
||||
N_248_i_1_1 Net - - - - 2
|
||||
nRowColSel_0_0_a2_1 ORCALUT4 B In 0.000 1.180 r -
|
||||
nRowColSel_0_0_a2_1 ORCALUT4 Z Out 1.089 2.269 r -
|
||||
N_251_i_1_0 Net - - - - 2
|
||||
nRCAS_0io_RNO ORCALUT4 B In 0.000 2.269 r -
|
||||
nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.885 f -
|
||||
N_248_i Net - - - - 1
|
||||
N_251_i Net - - - - 1
|
||||
nRCAS_0io OFS1P3BX D In 0.000 2.885 f -
|
||||
======================================================================================
|
||||
|
||||
|
@ -1136,14 +1139,14 @@ ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000
|
|||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
-----------------------------------------------------------------------------------
|
||||
LEDEN System FD1S3AX D LEDENe_0 16.089 12.918
|
||||
n8MEGEN System FD1S3AX D n8MEGENe_0 16.089 12.918
|
||||
wb_cyc_stb System FD1P3IX SP N_178 15.528 14.912
|
||||
===================================================================================
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
--------------------------------------------------------------------------------------------------
|
||||
LEDEN System FD1S3AX D LEDENe_0 16.089 12.918
|
||||
n8MEGEN System FD1S3AX D n8MEGENe_0 16.089 12.918
|
||||
wb_cyc_stb System FD1P3IX SP wb_cyc_stb_2_sqmuxa_i_0_0 15.528 14.912
|
||||
==================================================================================================
|
||||
|
||||
|
||||
|
||||
|
@ -1181,8 +1184,8 @@ ufmefb.EFBInst_0_RNISI191 ORCALUT4 Z Out 0.449 1.466 r
|
|||
N_4 Net - - - - 1
|
||||
CmdValid_RNIOOBE2 ORCALUT4 C In 0.000 1.466 r -
|
||||
CmdValid_RNIOOBE2 ORCALUT4 Z Out 1.089 2.554 r -
|
||||
CmdValid_RNIOOBE2 Net - - - - 2
|
||||
LEDENe ORCALUT4 B In 0.000 2.554 r -
|
||||
un1_FS_38_i Net - - - - 2
|
||||
LEDENe ORCALUT4 C In 0.000 2.554 r -
|
||||
LEDENe ORCALUT4 Z Out 0.617 3.171 r -
|
||||
LEDENe_0 Net - - - - 1
|
||||
LEDEN FD1S3AX D In 0.000 3.171 r -
|
||||
|
@ -1205,7 +1208,7 @@ Part: lcmxo2_1200hc-4
|
|||
|
||||
Register bits: 109 of 1280 (9%)
|
||||
PIC Latch: 0
|
||||
I/O cells: 63
|
||||
I/O cells: 64
|
||||
|
||||
|
||||
Details:
|
||||
|
@ -1220,12 +1223,13 @@ GSR: 1
|
|||
IB: 25
|
||||
IFS1P3DX: 9
|
||||
INV: 7
|
||||
OB: 30
|
||||
OB: 31
|
||||
ODDRXE: 1
|
||||
OFS1P3BX: 4
|
||||
OFS1P3DX: 11
|
||||
OFS1P3JX: 1
|
||||
ORCALUT4: 213
|
||||
PFUMX: 1
|
||||
ORCALUT4: 212
|
||||
PFUMX: 2
|
||||
PUR: 1
|
||||
VHI: 2
|
||||
VLO: 2
|
||||
|
@ -1234,7 +1238,7 @@ Mapper successful!
|
|||
At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 78MB peak: 203MB)
|
||||
|
||||
Process took 0h:00m:04s realtime, 0h:00m:04s cputime
|
||||
# Thu Sep 21 05:39:43 2023
|
||||
# Sat Nov 18 02:05:49 2023
|
||||
|
||||
###########################################################]
|
||||
|
||||
|
|
|
@ -22,7 +22,7 @@ Setup and Hold Report
|
|||
|
||||
--------------------------------------------------------------------------------
|
||||
<A name="Map_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454</big></U></B>
|
||||
Thu Sep 21 05:39:46 2023
|
||||
Sat Nov 18 02:05:54 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
|
@ -50,8 +50,8 @@ Report: 150.150MHz is the maximum frequency for this preference.
|
|||
<LI><A href='#map_twr_pref_0_2' Target='right'>FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
|
||||
Report: 150.150MHz is the maximum frequency for this preference.
|
||||
|
||||
<LI><A href='#map_twr_pref_0_3' Target='right'>FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)</A></LI> 878 items scored, 0 timing errors detected.
|
||||
Report: 100.492MHz is the maximum frequency for this preference.
|
||||
<LI><A href='#map_twr_pref_0_3' Target='right'>FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)</A></LI> 891 items scored, 0 timing errors detected.
|
||||
Report: 95.383MHz is the maximum frequency for this preference.
|
||||
|
||||
BLOCK ASYNCPATHS
|
||||
BLOCK RESETPATHS
|
||||
|
@ -69,28 +69,28 @@ Passed: The following path meets requirements by 163.025ns (weighted slack = 326
|
|||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q Bank_0io[0] (from PHI2_c +)
|
||||
Source: FF Q Bank_0io[1] (from PHI2_c +)
|
||||
Destination: FF Data in CmdEnable (to PHI2_c -)
|
||||
|
||||
Delay: 9.223ns (33.1% logic, 66.9% route), 6 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
9.223ns physical path delay Din[0]_MGIOL to SLICE_17 meets
|
||||
9.223ns physical path delay Din[1]_MGIOL to SLICE_17 meets
|
||||
172.414ns delay constraint less
|
||||
0.166ns DIN_SET requirement (totaling 172.248ns) by 163.025ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path Din[0]_MGIOL to SLICE_17:
|
||||
Data path Din[1]_MGIOL to SLICE_17:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
C2INP_DEL --- 0.577 *[0]_MGIOL.CLK to *n[0]_MGIOL.IN Din[0]_MGIOL (from PHI2_c)
|
||||
ROUTE 1 e 1.234 *n[0]_MGIOL.IN to SLICE_93.A0 Bank[0]
|
||||
CTOF_DEL --- 0.495 SLICE_93.A0 to SLICE_93.F0 SLICE_93
|
||||
ROUTE 1 e 1.234 SLICE_93.F0 to SLICE_84.C0 un1_CmdEnable20_0_0_o3_10
|
||||
CTOF_DEL --- 0.495 SLICE_84.C0 to SLICE_84.F0 SLICE_84
|
||||
ROUTE 6 e 1.234 SLICE_84.F0 to SLICE_11.C1 un1_CmdEnable20_0_0_o3
|
||||
C2INP_DEL --- 0.577 *[1]_MGIOL.CLK to *n[1]_MGIOL.IN Din[1]_MGIOL (from PHI2_c)
|
||||
ROUTE 1 e 1.234 *n[1]_MGIOL.IN to SLICE_90.A0 Bank[1]
|
||||
CTOF_DEL --- 0.495 SLICE_90.A0 to SLICE_90.F0 SLICE_90
|
||||
ROUTE 1 e 1.234 SLICE_90.F0 to SLICE_80.C0 un1_CmdEnable20_0_0_o2_10
|
||||
CTOF_DEL --- 0.495 SLICE_80.C0 to SLICE_80.F0 SLICE_80
|
||||
ROUTE 6 e 1.234 SLICE_80.F0 to SLICE_11.C1 N_367
|
||||
CTOF_DEL --- 0.495 SLICE_11.C1 to SLICE_11.F1 SLICE_11
|
||||
ROUTE 3 e 1.234 SLICE_11.F1 to SLICE_33.B0 CmdEnable16
|
||||
CTOF_DEL --- 0.495 SLICE_33.B0 to SLICE_33.F0 SLICE_33
|
||||
|
@ -141,48 +141,46 @@ Report: 150.150MHz is the maximum frequency for this preference.
|
|||
|
||||
================================================================================
|
||||
<A name="map_twr_pref_0_3"></A>Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
|
||||
878 items scored, 0 timing errors detected.
|
||||
891 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 6.049ns
|
||||
Passed: The following path meets requirements by 5.516ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q IS[1] (from RCLK_c +)
|
||||
Destination: FF Data in nRCAS_0io (to RCLK_c +)
|
||||
Source: FF Q S[0] (from RCLK_c +)
|
||||
Destination: FF Data in nRWE_0io (to RCLK_c +)
|
||||
|
||||
Delay: 9.798ns (34.9% logic, 65.1% route), 7 logic levels.
|
||||
Delay: 10.331ns (28.3% logic, 71.7% route), 6 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
9.798ns physical path delay SLICE_27 to nRCAS_MGIOL meets
|
||||
10.331ns physical path delay SLICE_16 to nRWE_MGIOL meets
|
||||
16.000ns delay constraint less
|
||||
0.153ns DO_SET requirement (totaling 15.847ns) by 6.049ns
|
||||
0.153ns DO_SET requirement (totaling 15.847ns) by 5.516ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path SLICE_27 to nRCAS_MGIOL:
|
||||
Data path SLICE_16 to nRWE_MGIOL:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.452 SLICE_27.CLK to SLICE_27.Q0 SLICE_27 (from RCLK_c)
|
||||
ROUTE 7 e 1.234 SLICE_27.Q0 to SLICE_74.A1 IS[1]
|
||||
CTOF_DEL --- 0.495 SLICE_74.A1 to SLICE_74.F1 SLICE_74
|
||||
ROUTE 2 e 0.480 SLICE_74.F1 to SLICE_74.B0 un1_nRCAS_6_sqmuxa_i_0_0_o2_0
|
||||
CTOF_DEL --- 0.495 SLICE_74.B0 to SLICE_74.F0 SLICE_74
|
||||
ROUTE 2 e 1.234 SLICE_74.F0 to SLICE_61.B1 N_408
|
||||
CTOF_DEL --- 0.495 SLICE_61.B1 to SLICE_61.F1 SLICE_61
|
||||
ROUTE 1 e 0.480 SLICE_61.F1 to SLICE_61.A0 un1_nRCAS_6_sqmuxa_i_0_0
|
||||
CTOF_DEL --- 0.495 SLICE_61.A0 to SLICE_61.F0 SLICE_61
|
||||
ROUTE 1 e 1.234 SLICE_61.F0 to SLICE_94.D0 nRCAS_r_i_0_o2_0_0
|
||||
CTOF_DEL --- 0.495 SLICE_94.D0 to SLICE_94.F0 SLICE_94
|
||||
ROUTE 1 e 0.480 SLICE_94.F0 to SLICE_94.A1 N_248_i_1
|
||||
CTOF_DEL --- 0.495 SLICE_94.A1 to SLICE_94.F1 SLICE_94
|
||||
ROUTE 1 e 1.234 SLICE_94.F1 to *AS_MGIOL.OPOS N_248_i (to RCLK_c)
|
||||
REG_DEL --- 0.452 SLICE_16.CLK to SLICE_16.Q0 SLICE_16 (from RCLK_c)
|
||||
ROUTE 12 e 1.234 SLICE_16.Q0 to SLICE_62.D1 CO0
|
||||
CTOF_DEL --- 0.495 SLICE_62.D1 to SLICE_62.F1 SLICE_62
|
||||
ROUTE 6 e 1.234 SLICE_62.F1 to SLICE_79.A1 IS_0_sqmuxa_0_o2
|
||||
CTOF_DEL --- 0.495 SLICE_79.A1 to SLICE_79.F1 SLICE_79
|
||||
ROUTE 2 e 1.234 SLICE_79.F1 to SLICE_28.D1 IS_0_sqmuxa_0_o3
|
||||
CTOF_DEL --- 0.495 SLICE_28.D1 to SLICE_28.F1 SLICE_28
|
||||
ROUTE 1 e 1.234 SLICE_28.F1 to SLICE_68.D1 nRWE_s_i_a2_1_0
|
||||
CTOF_DEL --- 0.495 SLICE_68.D1 to SLICE_68.F1 SLICE_68
|
||||
ROUTE 1 e 1.234 SLICE_68.F1 to SLICE_75.D0 nRWE_s_i_tz_0
|
||||
CTOF_DEL --- 0.495 SLICE_75.D0 to SLICE_75.F0 SLICE_75
|
||||
ROUTE 1 e 1.234 SLICE_75.F0 to *WE_MGIOL.OPOS N_252_i (to RCLK_c)
|
||||
--------
|
||||
9.798 (34.9% logic, 65.1% route), 7 logic levels.
|
||||
10.331 (28.3% logic, 71.7% route), 6 logic levels.
|
||||
|
||||
Report: 100.492MHz is the maximum frequency for this preference.
|
||||
Report: 95.383MHz is the maximum frequency for this preference.
|
||||
|
||||
<A name="mtw1_set_rs"></A><B><U><big>Report Summary</big></U></B>
|
||||
--------------
|
||||
|
@ -196,7 +194,7 @@ FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
|
|||
| | |
|
||||
FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
|
||||
| | |
|
||||
FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 100.492 MHz| 7
|
||||
FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 95.383 MHz| 6
|
||||
| | |
|
||||
----------------------------------------------------------------------------
|
||||
|
||||
|
@ -221,7 +219,7 @@ Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11
|
|||
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
|
||||
No transfer within this clock domain is found
|
||||
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 48
|
||||
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
|
||||
|
||||
Data transfers from:
|
||||
|
@ -251,11 +249,11 @@ Clock Domain: PHI2_c Source: PHI2.PAD Loads: 21
|
|||
Timing errors: 0 Score: 0
|
||||
Cumulative negative slack: 0
|
||||
|
||||
Constraints cover 1025 paths, 4 nets, and 741 connections (72.86% coverage)
|
||||
Constraints cover 1038 paths, 4 nets, and 732 connections (72.40% coverage)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
<A name="Map_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454</big></U></B>
|
||||
Thu Sep 21 05:39:46 2023
|
||||
Sat Nov 18 02:05:54 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
|
@ -280,7 +278,7 @@ Report level: verbose report, limited to 1 item per preference
|
|||
|
||||
<LI><A href='#map_twr_pref_1_2' Target='right'>FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
|
||||
|
||||
<LI><A href='#map_twr_pref_1_3' Target='right'>FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)</A></LI> 878 items scored, 0 timing errors detected.
|
||||
<LI><A href='#map_twr_pref_1_3' Target='right'>FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)</A></LI> 891 items scored, 0 timing errors detected.
|
||||
|
||||
BLOCK ASYNCPATHS
|
||||
BLOCK RESETPATHS
|
||||
|
@ -336,7 +334,7 @@ ROUTE 1 e 0.001 SLICE_10.F0 to SLICE_10.DI0 ADSubmitted_r_0_0 (to
|
|||
|
||||
================================================================================
|
||||
<A name="map_twr_pref_1_3"></A>Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
|
||||
878 items scored, 0 timing errors detected.
|
||||
891 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
@ -402,7 +400,7 @@ Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11
|
|||
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
|
||||
No transfer within this clock domain is found
|
||||
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 48
|
||||
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
|
||||
|
||||
Data transfers from:
|
||||
|
@ -432,7 +430,7 @@ Clock Domain: PHI2_c Source: PHI2.PAD Loads: 21
|
|||
Timing errors: 0 Score: 0
|
||||
Cumulative negative slack: 0
|
||||
|
||||
Constraints cover 1025 paths, 4 nets, and 741 connections (72.86% coverage)
|
||||
Constraints cover 1038 paths, 4 nets, and 732 connections (72.40% coverage)
|
||||
|
||||
|
||||
|
||||
|
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
@ -2,13 +2,15 @@
|
|||
Starting: parse design source files
|
||||
(VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v'
|
||||
(VERI-1482) Analyzing Verilog file '//Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v'
|
||||
WARNING - //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v(23,47-23,52) (VERI-1875) identifier 'Ready' is used before its declaration
|
||||
(VERI-1482) Analyzing Verilog file '//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/REFB.v'
|
||||
INFO - //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v(1,8-1,14) (VERI-1018) compiling module 'RAM2GS'
|
||||
INFO - //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v(1,1-615,10) (VERI-9000) elaborating module 'RAM2GS'
|
||||
INFO - //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v(1,1-618,10) (VERI-9000) elaborating module 'RAM2GS'
|
||||
INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1601,1-1606,10) (VERI-9000) elaborating module 'ODDRXE_uniq_1'
|
||||
INFO - //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/REFB.v(8,1-113,10) (VERI-9000) elaborating module 'REFB_uniq_1'
|
||||
INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_1'
|
||||
INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_1'
|
||||
INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1800,1-1872,10) (VERI-9000) elaborating module 'EFB_uniq_1'
|
||||
Done: design load finished with (0) errors, and (0) warnings
|
||||
Done: design load finished with (0) errors, and (1) warnings
|
||||
|
||||
</PRE></BODY></HTML>
|
|
@ -29,7 +29,7 @@ Performance Hardware Data Status: Final Version 34.4.
|
|||
// Package: TQFP100
|
||||
// ncd File: ram2gs_lcmxo2_1200hc_impl1.ncd
|
||||
// Version: Diamond (64-bit) 3.12.1.454
|
||||
// Written on Thu Sep 21 05:40:06 2023
|
||||
// Written on Sat Nov 18 02:06:17 2023
|
||||
// M: Minimum Performance Grade
|
||||
// iotiming RAM2GS_LCMXO2_1200HC_impl1.ncd RAM2GS_LCMXO2_1200HC_impl1.prf -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml
|
||||
|
||||
|
@ -41,94 +41,95 @@ Worst Case Results across Performance Grades (M, 6, 5, 4):
|
|||
|
||||
Port Clock Edge Setup Performance_Grade Hold Performance_Grade
|
||||
----------------------------------------------------------------------
|
||||
CROW[0] nCRAS F 2.913 4 -0.274 M
|
||||
CROW[1] nCRAS F 2.475 4 -0.161 M
|
||||
Din[0] PHI2 F 5.366 4 4.293 4
|
||||
Din[0] nCCAS F 1.448 4 -0.034 M
|
||||
Din[1] PHI2 F 4.971 4 4.173 4
|
||||
Din[1] nCCAS F 0.519 4 0.708 4
|
||||
Din[2] PHI2 F 5.192 4 4.173 4
|
||||
Din[2] nCCAS F 1.948 4 -0.142 M
|
||||
Din[3] PHI2 F 5.298 4 4.173 4
|
||||
Din[3] nCCAS F 1.974 4 -0.157 M
|
||||
Din[4] PHI2 F 4.281 4 4.173 4
|
||||
Din[4] nCCAS F 1.060 4 0.217 4
|
||||
Din[5] PHI2 F 5.059 4 4.173 4
|
||||
Din[5] nCCAS F 1.956 4 -0.150 M
|
||||
Din[6] PHI2 F 4.644 4 4.293 4
|
||||
Din[6] nCCAS F 2.886 4 -0.382 M
|
||||
Din[7] PHI2 F 5.316 4 4.293 4
|
||||
Din[7] nCCAS F 2.381 4 -0.244 M
|
||||
MAin[0] PHI2 F 4.362 4 1.145 4
|
||||
MAin[0] nCRAS F 1.189 4 0.362 4
|
||||
MAin[1] PHI2 F 4.386 4 0.999 4
|
||||
MAin[1] nCRAS F 1.884 4 -0.024 M
|
||||
MAin[2] PHI2 F 9.426 4 -0.750 M
|
||||
MAin[2] nCRAS F 1.136 4 0.453 4
|
||||
MAin[3] PHI2 F 10.458 4 -0.997 M
|
||||
MAin[3] nCRAS F 1.564 4 0.067 4
|
||||
MAin[4] PHI2 F 11.109 4 -1.209 M
|
||||
CROW[0] nCRAS F 3.288 4 -0.390 M
|
||||
CROW[1] nCRAS F 2.823 4 -0.285 M
|
||||
Din[0] PHI2 F 6.398 4 4.293 4
|
||||
Din[0] nCCAS F 1.411 4 -0.004 M
|
||||
Din[1] PHI2 F 3.916 4 4.173 4
|
||||
Din[1] nCCAS F 1.877 4 -0.123 M
|
||||
Din[2] PHI2 F 6.180 4 4.173 4
|
||||
Din[2] nCCAS F 1.548 4 -0.062 M
|
||||
Din[3] PHI2 F 5.536 4 4.173 4
|
||||
Din[3] nCCAS F 0.467 4 0.734 4
|
||||
Din[4] PHI2 F 3.611 4 4.173 4
|
||||
Din[4] nCCAS F 1.533 4 -0.043 M
|
||||
Din[5] PHI2 F 5.673 4 4.173 4
|
||||
Din[5] nCCAS F 1.663 4 -0.072 M
|
||||
Din[6] PHI2 F 5.355 4 4.293 4
|
||||
Din[6] nCCAS F 2.807 4 -0.352 M
|
||||
Din[7] PHI2 F 5.296 4 4.293 4
|
||||
Din[7] nCCAS F 1.914 4 -0.136 M
|
||||
MAin[0] PHI2 F 4.091 4 1.414 4
|
||||
MAin[0] nCRAS F 1.207 4 0.347 4
|
||||
MAin[1] PHI2 F 3.273 4 1.759 4
|
||||
MAin[1] nCRAS F 1.077 4 0.460 4
|
||||
MAin[2] PHI2 F 8.126 4 -0.351 M
|
||||
MAin[2] nCRAS F 0.671 4 0.850 4
|
||||
MAin[3] PHI2 F 8.831 4 -0.579 M
|
||||
MAin[3] nCRAS F 1.100 4 0.463 4
|
||||
MAin[4] PHI2 F 8.415 4 -0.447 M
|
||||
MAin[4] nCRAS F 1.390 4 0.207 4
|
||||
MAin[5] PHI2 F 9.884 4 -0.896 M
|
||||
MAin[5] PHI2 F 9.742 4 -0.803 M
|
||||
MAin[5] nCRAS F 1.269 4 0.218 4
|
||||
MAin[6] PHI2 F 9.859 4 -0.845 M
|
||||
MAin[6] nCRAS F 0.889 4 0.653 4
|
||||
MAin[7] PHI2 F 10.678 4 -1.070 M
|
||||
MAin[7] nCRAS F 1.186 4 0.309 4
|
||||
MAin[8] nCRAS F 1.639 4 0.014 M
|
||||
MAin[9] nCRAS F 1.097 4 0.457 4
|
||||
MAin[6] PHI2 F 7.970 4 -0.325 M
|
||||
MAin[6] nCRAS F 1.165 4 0.337 4
|
||||
MAin[7] PHI2 F 8.481 4 -0.438 M
|
||||
MAin[7] nCRAS F 0.761 4 0.673 4
|
||||
MAin[8] nCRAS F 1.261 4 0.223 4
|
||||
MAin[9] nCRAS F 0.756 4 0.667 4
|
||||
PHI2 RCLK R -0.133 M 2.360 4
|
||||
nCCAS RCLK R 2.943 4 -0.337 M
|
||||
nCCAS nCRAS F 2.967 4 -0.214 M
|
||||
nCRAS RCLK R 3.047 4 -0.402 M
|
||||
nFWE PHI2 F 11.116 4 -1.189 M
|
||||
nFWE nCRAS F 1.394 4 0.225 4
|
||||
nCCAS RCLK R 4.128 4 -0.675 M
|
||||
nCCAS nCRAS F 4.568 4 -0.666 M
|
||||
nCRAS RCLK R 3.070 4 -0.412 M
|
||||
nFWE PHI2 F 8.979 4 -0.603 M
|
||||
nFWE nCRAS F 1.467 4 0.144 4
|
||||
|
||||
|
||||
// Clock to Output Delay
|
||||
|
||||
Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
|
||||
Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
|
||||
------------------------------------------------------------------------
|
||||
LED RCLK R 11.046 4 3.298 M
|
||||
LED nCRAS F 11.710 4 3.359 M
|
||||
RA[0] RCLK R 11.397 4 3.516 M
|
||||
RA[0] nCRAS F 11.476 4 3.432 M
|
||||
RA[10] RCLK R 7.888 4 2.711 M
|
||||
RA[11] PHI2 R 9.755 4 3.200 M
|
||||
RA[1] RCLK R 11.272 4 3.469 M
|
||||
RA[1] nCRAS F 11.238 4 3.348 M
|
||||
RA[2] RCLK R 11.235 4 3.468 M
|
||||
RA[2] nCRAS F 11.665 4 3.453 M
|
||||
RA[3] RCLK R 11.390 4 3.512 M
|
||||
RA[3] nCRAS F 11.922 4 3.539 M
|
||||
RA[4] RCLK R 11.662 4 3.573 M
|
||||
RA[4] nCRAS F 11.818 4 3.505 M
|
||||
RA[5] RCLK R 11.744 4 3.584 M
|
||||
RA[5] nCRAS F 11.779 4 3.513 M
|
||||
RA[6] RCLK R 11.738 4 3.607 M
|
||||
RA[6] nCRAS F 11.836 4 3.531 M
|
||||
RA[7] RCLK R 12.475 4 3.797 M
|
||||
RA[7] nCRAS F 11.420 4 3.426 M
|
||||
RA[8] RCLK R 11.122 4 3.431 M
|
||||
RA[8] nCRAS F 11.667 4 3.471 M
|
||||
RA[9] RCLK R 11.935 4 3.649 M
|
||||
RA[9] nCRAS F 11.401 4 3.424 M
|
||||
RBA[0] nCRAS F 8.903 4 2.891 M
|
||||
RBA[1] nCRAS F 8.903 4 2.891 M
|
||||
RCKE RCLK R 10.011 4 3.215 M
|
||||
RDQMH RCLK R 10.790 4 3.354 M
|
||||
RDQML RCLK R 11.053 4 3.450 M
|
||||
RD[0] nCCAS F 8.977 4 3.012 M
|
||||
RD[1] nCCAS F 8.977 4 3.012 M
|
||||
RD[2] nCCAS F 8.977 4 3.012 M
|
||||
RD[3] nCCAS F 8.977 4 3.012 M
|
||||
RD[4] nCCAS F 8.977 4 3.012 M
|
||||
RD[5] nCCAS F 8.977 4 3.012 M
|
||||
RD[6] nCCAS F 8.977 4 3.012 M
|
||||
RD[7] nCCAS F 8.977 4 3.012 M
|
||||
nRCAS RCLK R 7.822 4 2.706 M
|
||||
nRCS RCLK R 7.822 4 2.706 M
|
||||
nRRAS RCLK R 7.822 4 2.706 M
|
||||
nRWE RCLK R 7.803 4 2.713 M
|
||||
LED RCLK R 11.034 4 3.119 M
|
||||
LED nCRAS F 11.531 4 3.339 M
|
||||
RA[0] RCLK R 11.682 4 3.586 M
|
||||
RA[0] nCRAS F 11.704 4 3.483 M
|
||||
RA[10] RCLK R 7.888 4 2.711 M
|
||||
RA[11] PHI2 R 9.755 4 3.200 M
|
||||
RA[1] RCLK R 11.454 4 3.535 M
|
||||
RA[1] nCRAS F 11.216 4 3.347 M
|
||||
RA[2] RCLK R 12.084 4 3.693 M
|
||||
RA[2] nCRAS F 11.742 4 3.501 M
|
||||
RA[3] RCLK R 12.131 4 3.715 M
|
||||
RA[3] nCRAS F 11.857 4 3.533 M
|
||||
RA[4] RCLK R 11.966 4 3.684 M
|
||||
RA[4] nCRAS F 12.319 4 3.650 M
|
||||
RA[5] RCLK R 11.928 4 3.670 M
|
||||
RA[5] nCRAS F 11.637 4 3.446 M
|
||||
RA[6] RCLK R 11.419 4 3.523 M
|
||||
RA[6] nCRAS F 11.718 4 3.486 M
|
||||
RA[7] RCLK R 11.988 4 3.651 M
|
||||
RA[7] nCRAS F 12.274 4 3.636 M
|
||||
RA[8] RCLK R 11.660 4 3.582 M
|
||||
RA[8] nCRAS F 11.098 4 3.343 M
|
||||
RA[9] RCLK R 11.454 4 3.547 M
|
||||
RA[9] nCRAS F 11.134 4 3.314 M
|
||||
RBA[0] nCRAS F 8.903 4 2.891 M
|
||||
RBA[1] nCRAS F 8.883 4 2.898 M
|
||||
RCKE RCLK R 9.774 4 3.159 M
|
||||
RCLKout RCLK R 7.101 4 2.108 M
|
||||
RDQMH RCLK R 10.733 4 3.351 M
|
||||
RDQML RCLK R 10.683 4 3.364 M
|
||||
RD[0] nCCAS F 8.977 4 3.012 M
|
||||
RD[1] nCCAS F 8.977 4 3.012 M
|
||||
RD[2] nCCAS F 8.977 4 3.012 M
|
||||
RD[3] nCCAS F 8.977 4 3.012 M
|
||||
RD[4] nCCAS F 8.977 4 3.012 M
|
||||
RD[5] nCCAS F 8.977 4 3.012 M
|
||||
RD[6] nCCAS F 8.977 4 3.012 M
|
||||
RD[7] nCCAS F 8.977 4 3.012 M
|
||||
nRCAS RCLK R 7.822 4 2.706 M
|
||||
nRCS RCLK R 7.822 4 2.706 M
|
||||
nRRAS RCLK R 7.822 4 2.706 M
|
||||
nRWE RCLK R 7.803 4 2.713 M
|
||||
WARNING: you must also run trce with hold speed: 4
|
||||
WARNING: you must also run trce with setup speed: M
|
||||
|
|
|
@ -1,3 +1,3 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<userSetting name="//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml" version="Diamond (64-bit) 3.12.1.454" date="Thu Sep 21 05:40:51 2023" vendor="Lattice Semiconductor Corporation" >
|
||||
<userSetting name="//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/promote.xml" version="Diamond (64-bit) 3.12.1.454" date="Sun Nov 19 19:55:57 2023" vendor="Lattice Semiconductor Corporation" >
|
||||
</userSetting>
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
<ReportView version="2.0">
|
||||
<Implement name="impl1">
|
||||
<ToolReport id="tooldec" path="" status="0"/>
|
||||
<ToolReport id="toolhle_genhierarchy" path="Y:/Repos/RAM2GS/CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html" status="1"/>
|
||||
<ToolReport id="toolhle_genhierarchy" path="//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html" status="1"/>
|
||||
<ToolReport id="toolpio" path="" status="0"/>
|
||||
<ToolReport id="toolsso" path="" status="0"/>
|
||||
</Implement>
|
||||
|
|
|
@ -0,0 +1 @@
|
|||
VERSION=20110520
|
|
@ -0,0 +1,90 @@
|
|||
<HTML>
|
||||
<HEAD><TITLE>Lattice TCL Log</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="pn231117181450"></A><B><U><big>pn231117181450</big></U></B>
|
||||
#Start recording tcl command: 11/16/2023 13:08:29
|
||||
#Project Location: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
|
||||
prj_project open "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf"
|
||||
prj_project close
|
||||
#Stop recording: 11/17/2023 18:14:50
|
||||
|
||||
|
||||
|
||||
<A name="pn231118021827"></A><B><U><big>pn231118021827</big></U></B>
|
||||
#Start recording tcl command: 11/17/2023 18:14:55
|
||||
#Project Location: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC; Project name: RAM2GS_LCMXO2_640HC
|
||||
prj_project open "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/RAM2GS_LCMXO2_640HC.ldf"
|
||||
prj_run Export -impl impl1
|
||||
prj_run PAR -impl impl1
|
||||
prj_run Export -impl impl1
|
||||
prj_run PAR -impl impl1 -forceAll
|
||||
prj_run PAR -impl impl1 -forceAll
|
||||
prj_run PAR -impl impl1 -forceAll
|
||||
prj_run PAR -impl impl1 -forceAll
|
||||
prj_run PAR -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
prj_run Export -impl impl1 -forceAll
|
||||
#Stop recording: 11/18/2023 02:18:27
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
|
@ -1,6 +1,6 @@
|
|||
NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
|
||||
NOTE All Rights Reserved *
|
||||
NOTE DATE CREATED: Thu Sep 21 05:40:18 2023 *
|
||||
NOTE DATE CREATED: Sat Nov 18 02:06:30 2023 *
|
||||
NOTE DESIGN NAME: RAM2GS *
|
||||
NOTE DEVICE NAME: LCMXO2-640HC-4TQFP100 *
|
||||
NOTE PIN ASSIGNMENTS *
|
||||
|
@ -13,6 +13,7 @@ NOTE PINS nRCAS : 52 : out *
|
|||
NOTE PINS nRRAS : 54 : out *
|
||||
NOTE PINS nRWE : 49 : out *
|
||||
NOTE PINS RCKE : 53 : out *
|
||||
NOTE PINS RCLKout : 60 : out *
|
||||
NOTE PINS RCLK : 63 : in *
|
||||
NOTE PINS nRCS : 57 : out *
|
||||
NOTE PINS RD[7] : 43 : inout *
|
||||
|
@ -34,7 +35,7 @@ NOTE PINS RA[3] : 71 : out *
|
|||
NOTE PINS RA[2] : 69 : out *
|
||||
NOTE PINS RA[1] : 67 : out *
|
||||
NOTE PINS RA[0] : 66 : out *
|
||||
NOTE PINS RBA[1] : 60 : out *
|
||||
NOTE PINS RBA[1] : 47 : out *
|
||||
NOTE PINS RBA[0] : 58 : out *
|
||||
NOTE PINS LED : 34 : out *
|
||||
NOTE PINS nFWE : 15 : in *
|
||||
|
|
|
@ -3,7 +3,7 @@ Report for cell RAM2GS.verilog
|
|||
|
||||
Register bits: 109 of 640 (17%)
|
||||
PIC Latch: 0
|
||||
I/O cells: 63
|
||||
I/O cells: 64
|
||||
Cell usage:
|
||||
cell count Res Usage(%)
|
||||
BB 8 100.0
|
||||
|
@ -17,19 +17,20 @@ I/O cells: 63
|
|||
IB 25 100.0
|
||||
IFS1P3DX 9 100.0
|
||||
INV 7 100.0
|
||||
OB 30 100.0
|
||||
OB 31 100.0
|
||||
ODDRXE 1 100.0
|
||||
OFS1P3BX 4 100.0
|
||||
OFS1P3DX 11 100.0
|
||||
OFS1P3JX 1 100.0
|
||||
ORCALUT4 213 100.0
|
||||
PFUMX 1 100.0
|
||||
ORCALUT4 212 100.0
|
||||
PFUMX 2 100.0
|
||||
PUR 1 100.0
|
||||
VHI 2 100.0
|
||||
VLO 2 100.0
|
||||
SUB MODULES
|
||||
REFB 1 100.0
|
||||
|
||||
TOTAL 411
|
||||
TOTAL 413
|
||||
----------------------------------------------------------------------
|
||||
Report for cell REFB.netlist
|
||||
Instance path: ufmefb
|
||||
|
|
|
@ -4,7 +4,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Thu Sep 21 05:40:14 2023
|
||||
Sat Nov 18 02:06:26 2023
|
||||
|
||||
|
||||
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC -w -jedec -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
|
||||
|
@ -81,6 +81,6 @@ UFM Utilization: General Purpose Flash Memory.
|
|||
Available General Purpose Flash Memory: 191 Pages (Page 0 to Page 190).
|
||||
Initialized UFM Pages: 1 Page (Page 190).
|
||||
|
||||
Total CPU Time: 3 secs
|
||||
Total CPU Time: 4 secs
|
||||
Total REAL Time: 4 secs
|
||||
Peak Memory Usage: 266 MB
|
||||
Peak Memory Usage: 267 MB
|
||||
|
|
Binary file not shown.
File diff suppressed because it is too large
Load Diff
|
@ -2,7 +2,7 @@
|
|||
NOTE Diamond (64-bit) 3.12.1.454 JEDEC Compatible Fuse File.*
|
||||
NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation.*
|
||||
NOTE All Rights Reserved.*
|
||||
NOTE DATE CREATED: Thu Sep 21 05:40:14 2023*
|
||||
NOTE DATE CREATED: Sat Nov 18 02:06:26 2023*
|
||||
NOTE DESIGN NAME: RAM2GS_LCMXO2_640HC_impl1.ncd*
|
||||
NOTE DEVICE NAME: LCMXO2-640HC-4TQFP100*
|
||||
NOTE JEDEC FILE STATUS: Final Version 1.95*
|
||||
|
@ -16,6 +16,7 @@ NOTE PINS nRCAS : 52 : out*
|
|||
NOTE PINS nRRAS : 54 : out*
|
||||
NOTE PINS nRWE : 49 : out*
|
||||
NOTE PINS RCKE : 53 : out*
|
||||
NOTE PINS RCLKout : 60 : out*
|
||||
NOTE PINS RCLK : 63 : in*
|
||||
NOTE PINS nRCS : 57 : out*
|
||||
NOTE PINS RD[7] : 43 : inout*
|
||||
|
@ -37,7 +38,7 @@ NOTE PINS RA[3] : 71 : out*
|
|||
NOTE PINS RA[2] : 69 : out*
|
||||
NOTE PINS RA[1] : 67 : out*
|
||||
NOTE PINS RA[0] : 66 : out*
|
||||
NOTE PINS RBA[1] : 60 : out*
|
||||
NOTE PINS RBA[1] : 47 : out*
|
||||
NOTE PINS RBA[0] : 58 : out*
|
||||
NOTE PINS LED : 34 : out*
|
||||
NOTE PINS nFWE : 15 : in*
|
||||
|
@ -75,382 +76,382 @@ QF171904*
|
|||
G0*
|
||||
F0*
|
||||
L000000
|
||||
11111111111111111011110110110011111111111111111100111011000000000000000000000000000000100000000000000000000000000000101000001001
|
||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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00110000111100000000000000000010001100000000000000110001010010000010010010000110101001110100100101100001011010100000100001000000
|
||||
00010010000000000001000010000000000000000000000000000100001100101010011001000110001001100100011000000000000000000010000100010010
|
||||
10000000000000000001110000001100111001001001000011001001001011000011100001110000000000100101000000000010001000000000010110100000
|
||||
01001010000100010010001000000101101101001100011010011011110010101011011010011000110100110101001100010000000000000000000000000000
|
||||
00000000000001011011101001010001010111000100110000101010101100001001010000000000000101011000000000000000000000000000001001110000
|
||||
00001001000110010001001001010100100010010100000001100001111000000011111000000010111001000100000000000000000000100011010110001001
|
||||
10000110001100110011100100011000110110000000000000000000000000000000000000000000000000000100111000100010010011100010001001001110
|
||||
00000000001001110100011100010100111100110100111000000000000000000000100101100101000010010110001100000000000000000000010000010111
|
||||
10000000000000000000000000000100110010001101000010100110010001110000000100110000000000000010010100001000110000000000000000000100
|
||||
11110011110000010011001000011000100100000001000011001000000000000000000000000000100010000000000101100000000000001000100100011010
|
||||
01100100010101001100011011010001001001111001000100011010001010011100000000000000001100011000010011010110101110001000000000000000
|
||||
00000001001100100110110000101011100010000100110100111110010010001001110100000010101000000000000000000100000010101100010010100101
|
||||
01100000000000000000001001110010010100010010001001010001001000100101000000000000001110010000000000000000000000000000111111000011
|
||||
00010011011001100111010000110000111111110011110111100110011101110110011000100010111111101111111100000000000000000000011110111010
|
||||
00100001101000000000000000000000000010010011011111111111111110110100100111101111111111111101111001001011011111111111111110110100
|
||||
10011110111111111111110111100100101101111111111111111010100100000000000000000000000000000000000000010100010100010010011001100011
|
||||
11111101110001111111100001111011111100100110101000111101110110011000100011001001111111011010101000000000000000001111011101100011
|
||||
00100100101000000000000000000000000010010011011111001100111110110000110111101111001100111101111011000011011111001100111110110000
|
||||
11011110111100110011110111101100001101111100110011111010001100000000000000000000000000000000000000011111111101101001100011111011
|
||||
11110001100101011111111001111010100011111111001000110110010001001000111100001111100011000000000000000011111011000001001001010000
|
||||
00000000000000000000010010011111111101100111110110000110111101111001100111101111011000011011111001100111110110000110111101111001
|
||||
10011110111101100001101111100110011111110001100000000000000000000000000000000000000111010101011010011000111110111110110001011111
|
||||
10000111101110111111111101110010011001100100010001100001111100110000000000000000011110111110001000010000000000000000000000010000
|
||||
11100111111111111111011010000011110111111111111110111100000101101111111111111111011010000011110111111111111110111100000101101111
|
||||
11110100000000000000000000111101000000000000000000000000000100000001001110010000000100111000001001110010010000000000000000000000
|
||||
10110100000000000000000000000100010110110100010000011110100111001001000111111000100110110100010000011110100111001001000111111000
|
||||
10011011010001000001111010000000000000000000000000000000000000000000010000100000000000100101100010111000010000000000010010110000
|
||||
00000010000100000000000100010000000000000000000000000000000000000101001100101000001001100010011100000000000000000000001000010000
|
||||
00000001000010010000000000000100001010000100000000000001000110001000001000111000110000100011100011000000000000000000000000000001
|
||||
00100000001101100000000000000000000000000000001100100100000000000000010011110011100000000010000000000100000000000000000100101000
|
||||
00100101000000000000000000000000000001001101000110000000001110010000010000000000000000000000000000000000000000100000100101100001
|
||||
10000100000000100000100101100001000000000000010011000000100101000001001010000000000000000000000000000100100100110000000000000000
|
||||
00000000000000000000000000000000010010100000011000001100000100101000000100001000000000000000000000000000000000000000000000000000
|
||||
01100111100000100111000000000000000000000010000100000000000100001000100110000010011100100001000000000000000000000000000000000000
|
||||
00000000000000000000000001100111100100111000000000000000000000000001001110000000000000000001000000000000000010000000000000000000
|
||||
00000000000000000000000000000000000011000011110001000011001110100000000000000000000000000000000000000001000001001010010001100000
|
||||
00100000100101000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011101000001100001
|
||||
10010101001110100000000000010010001000100100111000001000010000000000000000010000100000000000000000000000000000000000000001100111
|
||||
10011000100010000000000000000000000010000000000100001000000000011000000110000001000010010010101001000000000000000000000000000000
|
||||
00000000000000000000000000000000011001111000000000000000000000000000000001001110000010001110011010010100110110000000000000010001
|
||||
10100110000000100101000000000000010001010011100000000000000000000000000000000011000011110000000000000000000000000000000100001000
|
||||
00010010110010001111000100000000000100111010010101001000000010000010010000000000000000001000000000000000000000000000000000000000
|
||||
01100111100000000000000000000000000000000001000110000000000000010000100100101000000001000010000000000000000000000000000000000000
|
||||
00000000000011000011110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000010010100101101001010110000000010000000100100000000000000000000000000001011010000000000
|
||||
00000000000000000000000000100111000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000
|
||||
00000000000000000000000000111100100000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000011000011110001001000000000000010001100000000000100011000000000000000000000001000111001010000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000100101000000000000000000000001001010000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000100101000000000000000000000000010001000000000001001110000101011010
|
||||
11010000000000000000000000000000000000000000000000000000110000111100000000101111000000000000000000000000010001110001001010010000
|
||||
00000001001100000000001001000101011000000000000000000000000000000000000000000000000000000000000000100111001101100100010100100000
|
||||
00000000000000000000000000100101010001100000000010010110111011000101000000000000000000000000000100001100111000000000000000000000
|
||||
00000000000000000000000100111000000000000000000001001011101101000000000001000001011000100010000000001100000011100100010001100000
|
||||
00000000000000000010011000000000000000000000000000000000000000000010010000100010010001100000000000000000000000000000000011011000
|
||||
00011010110000000000000011101000000000000000000000000001000110000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100111000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011110010000000000000000000010010000000
|
||||
00000000000000000000000000100000000000000000000000000000000001001010000000000000000000000000000110000111100000000010010000000000
|
||||
00000000000000000000000000000000000000000000000000000010011100000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000010000100000000000000000000000000000000000000000000000000000000000000000000001001
|
||||
10000000000000000000000000000000010001000000000000000000000000000000100100000000000000000000000000000011000011110011110000000000
|
||||
00000000000000000000010001110001100000000100000000010010000000001001110110100010001001100000000000000000000100000000000100110000
|
||||
00000000000000000000000000000000001001110011011010000101001000000000000000000000100100000000000100101011001001000100111000000010
|
||||
01010000000000000000000000000000001001000000000000000000000000000000000000000100010000000000000000000000010010110001100000000010
|
||||
11100101001010010000000010000010010001001100100011000000000000000000010001001001100000100110000000000000000000000000000000000000
|
||||
00100100000011101000000000000000000000000001001000000000000000100111000000000100010011100010000000000000000000000001000100000100
|
||||
10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000100001000000000000000000000001000010000000000000000010
|
||||
00010000010000100000000000000000000000000000000000000000000000000000000000000100001000001100110010000000000000000001000010000010
|
||||
11100000000000000000011001100100000011001100100000000000000000010000100000100001000000000000000001000010000010000100000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000001000010000000000000000000000010000100000000000000000100001000001000010000000000000000000000000000000000000000000000000
|
||||
00000000000001000010000011001100100000000000000000010000100000101011000000000000000001100110010000001100110010000000000000000001
|
||||
00001000001000010000000000000000010000100000100001000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000010000000000000100000111000010011100010001010011001011000010
|
||||
00000100000111000010011100010001010011001011000010000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000010011000000000001110011010111110100100100010000000011100110101111101001001000100000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000010000011100000101000000000000001000001110000010111010000110011000000000100000
|
||||
11100000101110100001100110000000000000000000000100111000000000000000000000000000000000000000000000000000000000000010000001001111
|
||||
00100000000001000001000101110000001110101000000000000100000100010111000000111010100000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000011000100011101000001100110000000011000001101100011000100000111111100111111000000000
|
||||
00011000001101100011000100000111111100111111000000000000000000000000001100010100100010000000000000000000000000000000000000000000
|
||||
00000000000000000000011000100011101000001100110000000011000001101100011000100000111111100111111000000000000110000011011000110001
|
||||
00000111111100111111000000000000000000000000100001100011100011100111100111000000000000000000000000000000000000000000000000000100
|
||||
11100000000000000000100111000000000000001000001100010001110100000110011000011100010001110100000111010000000100000111001100111111
|
||||
00001111110000000000000000001100000110110001100011000110011110000001100111000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000001110001000111010000011101000000010000011100110011111100001111110000001000011011101100011001111100
|
||||
00011111000000000000000000011000001101100011000110001100111100000011001110000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000001001110000000000001000110100111100011010011100000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000001001100000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000001001110001000110010001101001111000110100111100011010011110010010011100000000000100000100011
|
||||
10010011100000011000111001001001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000100110100111000000000001000011000110111000010010001110011010011100000000010010100000000000000011100010100000000000010111001
|
||||
10010011111111111111111111111111111111111111111111111111111111111111111111000010100000000000000000000000000000000000000000000000
|
||||
00000000001010101010011100100010000000000000000000000000010000000000000000000000000000001111111101011110000000000000000000000000
|
||||
00011100001000100000100101000000010000011100001001110001000101001100101100001000000100000111000010011100010001010011001011000010
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000111001001010011000000000001110011010111110100
|
||||
10010001000000001110011010111110100100100010000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00010000011100000101000001001100000000010000011100000101110100001100110000000001000001110000010111010000110011000000000000000000
|
||||
00001001110000000000000000000000000000000000000000000000000000000000000000100000100010100111100100000000001000001000101110000001
|
||||
10101100000000100000100010111000000110101100000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000110001000111010000011001100000000110000011011000110001000001111111001111110000000000001100000110110001100010000011111110011
|
||||
11110000000000000000000000000011000101001000100000000000000000000000000000000000000000000000000000000000000001100011001111110000
|
||||
11111100000000000011000001101100011000100000111111100111111000000000000110000011011000110001000001111111001111110000000000000000
|
||||
00000000100001100011100011100111100111000000000000000000000000000000000000000000000001001110000000000000000010011100000000000000
|
||||
10000011000100011101000001100110000111000100011101000001110100000001000001110011001111110000111111000000000000000000110000011011
|
||||
00011000110001100111100000011001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000111000100
|
||||
01110100000111010000000100000111001100111111000011111100000010000110110011000110011111000001101111000000000000011000001101100011
|
||||
00011000110011110000001100111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010
|
||||
01110000000000001000110100111100011010011100000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000001001100000000000000000000000000000000000000000000000000000000000000000000000000000000000010011100010
|
||||
00110010001101001111000110100111100011010011110010010011100000000000100000100011100100111000000110001110010010011100000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000001001101001110000000000010000110001101110000
|
||||
10010001110011010011100000000010010100000000000000011100010100000000000001000100110110111111111111111111111111111111111111111111
|
||||
11111111111111111111111111000010100000000000000000000000000000000000000000000000000000000010101010100111001000100000000000000000
|
||||
00000000010000000000000000000000000000001111111111111111111111111111111111111111111111111111111101011110000000000000000000000000
|
||||
11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
*
|
||||
NOTE END CONFIG DATA*
|
||||
L47744
|
||||
L47488
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
|
@ -1425,10 +1426,10 @@ L171648
|
|||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
*
|
||||
C374D*
|
||||
C1984*
|
||||
NOTE FEATURE_ROW*
|
||||
E0000000000000000000000000000000000000000000000000000000000000000
|
||||
0000010001100000*
|
||||
NOTE User Electronic Signature Data*
|
||||
UH00000000*
|
||||
00B7
|
||||
0872
|
||||
|
|
|
@ -15,7 +15,7 @@ Target Vendor: LATTICE
|
|||
Target Device: LCMXO2-640HCTQFP100
|
||||
Target Performance: 4
|
||||
Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454
|
||||
Mapped on: 09/21/23 05:39:43
|
||||
Mapped on: 11/18/23 02:05:52
|
||||
|
||||
Design Summary
|
||||
--------------
|
||||
|
@ -27,12 +27,24 @@ Design Summary
|
|||
SLICEs as Logic/ROM: 120 out of 320 (38%)
|
||||
SLICEs as RAM: 0 out of 240 (0%)
|
||||
SLICEs as Carry: 10 out of 320 (3%)
|
||||
Number of LUT4s: 237 out of 640 (37%)
|
||||
Number used as logic LUTs: 217
|
||||
Number of LUT4s: 238 out of 640 (37%)
|
||||
Number used as logic LUTs: 218
|
||||
Number used as distributed RAM: 0
|
||||
Number used as ripple logic: 20
|
||||
Number used as shift registers: 0
|
||||
Number of PIO sites used: 63 + 4(JTAG) out of 79 (85%)
|
||||
Number of PIO sites used: 64 + 4(JTAG) out of 79 (86%)
|
||||
Number of IDDR/ODDR/TDDR cells used: 1 out of 237 (0%)
|
||||
Number of IDDR cells: 0
|
||||
Number of ODDR cells: 1
|
||||
Number of TDDR cells: 0
|
||||
Number of PIO using at least one IDDR/ODDR/TDDR: 1 (0 differential)
|
||||
Number of PIO using IDDR only: 0 (0 differential)
|
||||
Number of PIO using ODDR only: 1 (0 differential)
|
||||
Number of PIO using TDDR only: 0 (0 differential)
|
||||
Number of PIO using IDDR/ODDR: 0 (0 differential)
|
||||
Number of PIO using IDDR/TDDR: 0 (0 differential)
|
||||
Number of PIO using ODDR/TDDR: 0 (0 differential)
|
||||
Number of PIO using IDDR/ODDR/TDDR: 0 (0 differential)
|
||||
Number of block RAMs: 0 out of 2 (0%)
|
||||
Number of GSRs: 0 out of 1 (0%)
|
||||
EFB used : Yes
|
||||
|
@ -48,29 +60,29 @@ Design Summary
|
|||
Number of DCMA: 0 out of 2 (0%)
|
||||
Notes:-
|
||||
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
|
||||
distributed RAMs) + 2*(Number of ripple logic)
|
||||
2. Number of logic LUT4s does not include count of distributed RAM and
|
||||
ripple logic.
|
||||
Number of clocks: 4
|
||||
Net PHI2_c: 20 loads, 9 rising, 11 falling (Driver: PIO PHI2 )
|
||||
Net RCLK_c: 47 loads, 47 rising, 0 falling (Driver: PIO RCLK )
|
||||
Net nCRAS_c: 9 loads, 0 rising, 9 falling (Driver: PIO nCRAS )
|
||||
Net nCCAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCCAS )
|
||||
Number of Clock Enables: 5
|
||||
Net N_178: 1 loads, 1 LSLICEs
|
||||
Net XOR8MEG18: 5 loads, 5 LSLICEs
|
||||
Net N_360_i: 2 loads, 2 LSLICEs
|
||||
|
||||
Page 1
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 09/21/23 05:39:43
|
||||
Design: RAM2GS Date: 11/18/23 02:05:52
|
||||
|
||||
Design Summary (cont)
|
||||
---------------------
|
||||
Net un1_wb_rst14_i_0: 9 loads, 9 LSLICEs
|
||||
distributed RAMs) + 2*(Number of ripple logic)
|
||||
2. Number of logic LUT4s does not include count of distributed RAM and
|
||||
ripple logic.
|
||||
Number of clocks: 4
|
||||
Net PHI2_c: 20 loads, 9 rising, 11 falling (Driver: PIO PHI2 )
|
||||
Net RCLK_c: 48 loads, 48 rising, 0 falling (Driver: PIO RCLK )
|
||||
Net nCRAS_c: 9 loads, 0 rising, 9 falling (Driver: PIO nCRAS )
|
||||
Net nCCAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCCAS )
|
||||
Number of Clock Enables: 5
|
||||
Net wb_cyc_stb_2_sqmuxa_i_0_0: 1 loads, 1 LSLICEs
|
||||
Net XOR8MEG18: 5 loads, 5 LSLICEs
|
||||
Net N_126_i: 9 loads, 9 LSLICEs
|
||||
Net N_261_i: 2 loads, 2 LSLICEs
|
||||
Net CmdUFMData_1_sqmuxa: 1 loads, 1 LSLICEs
|
||||
Number of LSRs: 5
|
||||
Net RA10s_i: 1 loads, 0 LSLICEs
|
||||
|
@ -80,16 +92,16 @@ Design Summary (cont)
|
|||
Net RASr2: 2 loads, 2 LSLICEs
|
||||
Number of nets driven by tri-state buffers: 0
|
||||
Top 10 highest fanout non-clock nets:
|
||||
Net InitReady: 41 loads
|
||||
Net FS[11]: 23 loads
|
||||
Net InitReady: 40 loads
|
||||
Net FS[13]: 22 loads
|
||||
Net FS[10]: 21 loads
|
||||
Net FS[12]: 21 loads
|
||||
Net FS[9]: 20 loads
|
||||
Net FS[14]: 18 loads
|
||||
Net CO0: 15 loads
|
||||
Net FS[11]: 21 loads
|
||||
Net FS[12]: 19 loads
|
||||
Net FS[14]: 19 loads
|
||||
Net FS[10]: 18 loads
|
||||
Net FS[9]: 17 loads
|
||||
Net Ready: 14 loads
|
||||
Net Ready_fast: 14 loads
|
||||
Net N_214: 13 loads
|
||||
Net CO0: 12 loads
|
||||
|
||||
|
||||
|
||||
|
@ -114,6 +126,16 @@ IO (PIO) Attributes
|
|||
+---------------------+-----------+-----------+------------+
|
||||
| IO Name | Direction | Levelmode | IO |
|
||||
| | | IO_TYPE | Register |
|
||||
|
||||
Page 2
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 11/18/23 02:05:52
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[0] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
@ -126,16 +148,6 @@ IO (PIO) Attributes
|
|||
| RDQMH | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRCAS | OUTPUT | LVCMOS33 | OUT |
|
||||
|
||||
Page 2
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 09/21/23 05:39:43
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRRAS | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
@ -143,6 +155,8 @@ IO (PIO) Attributes (cont)
|
|||
+---------------------+-----------+-----------+------------+
|
||||
| RCKE | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RCLKout | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RCLK | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRCS | OUTPUT | LVCMOS33 | OUT |
|
||||
|
@ -178,6 +192,16 @@ IO (PIO) Attributes (cont)
|
|||
| RA[4] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[3] | OUTPUT | LVCMOS33 | |
|
||||
|
||||
Page 3
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 11/18/23 02:05:52
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[2] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
@ -192,16 +216,6 @@ IO (PIO) Attributes (cont)
|
|||
| LED | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nFWE | INPUT | LVCMOS33 | |
|
||||
|
||||
Page 3
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 09/21/23 05:39:43
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nCRAS | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
@ -244,6 +258,16 @@ IO (PIO) Attributes (cont)
|
|||
| MAin[9] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[8] | INPUT | LVCMOS33 | |
|
||||
|
||||
Page 4
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 11/18/23 02:05:52
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[7] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
@ -258,16 +282,6 @@ IO (PIO) Attributes (cont)
|
|||
| MAin[2] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[1] | INPUT | LVCMOS33 | |
|
||||
|
||||
Page 4
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 09/21/23 05:39:43
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[0] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
@ -279,7 +293,6 @@ Block GSR_INST undriven or does not drive anything - clipped.
|
|||
Signal nCRAS_c_i was merged into signal nCRAS_c
|
||||
Signal RASr2_i was merged into signal RASr2
|
||||
Signal XOR8MEG.CN was merged into signal PHI2_c
|
||||
Signal GND undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/VCC undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/GND undriven or does not drive anything - clipped.
|
||||
Signal FS_s_0_S1[17] undriven or does not drive anything - clipped.
|
||||
|
@ -311,6 +324,16 @@ Signal ufmefb/I2C2SDAOEN undriven or does not drive anything - clipped.
|
|||
Signal ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SCLOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
|
||||
|
||||
Page 5
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 11/18/23 02:05:52
|
||||
|
||||
Removed logic (cont)
|
||||
--------------------
|
||||
Signal ufmefb/I2C1SDAOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SCLOEN undriven or does not drive anything - clipped.
|
||||
|
@ -324,16 +347,6 @@ Signal ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
|
|||
Signal ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
|
||||
|
||||
Page 5
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 09/21/23 05:39:43
|
||||
|
||||
Removed logic (cont)
|
||||
--------------------
|
||||
Signal ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
|
||||
|
@ -354,7 +367,6 @@ Signal N_1 undriven or does not drive anything - clipped.
|
|||
Block nCRAS_pad_RNIBPVB was optimized away.
|
||||
Block RASr2_RNIAFR1 was optimized away.
|
||||
Block XOR8MEG.CN was optimized away.
|
||||
Block GND was optimized away.
|
||||
Block ufmefb/VCC was optimized away.
|
||||
Block ufmefb/GND was optimized away.
|
||||
|
||||
|
@ -378,6 +390,16 @@ Embedded Functional Block Connection Summary
|
|||
I2C Function Summary:
|
||||
--------------------
|
||||
None
|
||||
|
||||
Page 6
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 11/18/23 02:05:52
|
||||
|
||||
Embedded Functional Block Connection Summary (cont)
|
||||
---------------------------------------------------
|
||||
SPI Function Summary:
|
||||
--------------------
|
||||
None
|
||||
|
@ -391,16 +413,6 @@ Embedded Functional Block Connection Summary
|
|||
Available General
|
||||
Purpose Flash Memory: 191 Pages (191*128 Bits)
|
||||
|
||||
Page 6
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 09/21/23 05:39:43
|
||||
|
||||
Embedded Functional Block Connection Summary (cont)
|
||||
---------------------------------------------------
|
||||
|
||||
EBR Blocks with Unique
|
||||
Initialization Data: 0
|
||||
|
||||
|
@ -436,18 +448,6 @@ Run Time and Memory Usage
|
|||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
|
@ -6,7 +6,7 @@ Performance Grade: 4
|
|||
PACKAGE: TQFP100
|
||||
Package Status: Final Version 1.39
|
||||
|
||||
Thu Sep 21 05:39:54 2023
|
||||
Sat Nov 18 02:06:05 2023
|
||||
|
||||
Pinout by Port Name:
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
|
@ -55,9 +55,10 @@ Pinout by Port Name:
|
|||
| RA[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[9] | 62/1 | LVCMOS33_OUT | PR5D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RBA[0] | 58/1 | LVCMOS33_OUT | PR6C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RBA[1] | 60/1 | LVCMOS33_OUT | PR6A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RBA[1] | 47/2 | LVCMOS33_OUT | PB14B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RCKE | 53/1 | LVCMOS33_OUT | PR7B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RCLK | 63/1 | LVCMOS33_IN | PR5C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| RCLKout | 60/1 | LVCMOS33_OUT | PR6A | | | DRIVE:24mA SLEW:FAST |
|
||||
| RDQMH | 51/1 | LVCMOS33_OUT | PR7D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RDQML | 48/2 | LVCMOS33_OUT | PB14C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RD[0] | 36/2 | LVCMOS33_BIDI | PB10A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
|
@ -134,7 +135,7 @@ Pinout by Pin Number:
|
|||
| 42/2 | RD[6] | LOCATED | LVCMOS33_BIDI | PB12C | | | |
|
||||
| 43/2 | RD[7] | LOCATED | LVCMOS33_BIDI | PB12D | | | |
|
||||
| 45/2 | unused, PULL:DOWN | | | PB14A | | | |
|
||||
| 47/2 | unused, PULL:DOWN | | | PB14B | | | |
|
||||
| 47/2 | RBA[1] | LOCATED | LVCMOS33_OUT | PB14B | | | |
|
||||
| 48/2 | RDQML | LOCATED | LVCMOS33_OUT | PB14C | SN | | |
|
||||
| 49/2 | nRWE | LOCATED | LVCMOS33_OUT | PB14D | SI/SISPI | | |
|
||||
| 51/1 | RDQMH | LOCATED | LVCMOS33_OUT | PR7D | | | |
|
||||
|
@ -144,7 +145,7 @@ Pinout by Pin Number:
|
|||
| 57/1 | nRCS | LOCATED | LVCMOS33_OUT | PR6D | | | |
|
||||
| 58/1 | RBA[0] | LOCATED | LVCMOS33_OUT | PR6C | | | |
|
||||
| 59/1 | RA[11] | LOCATED | LVCMOS33_OUT | PR6B | | | |
|
||||
| 60/1 | RBA[1] | LOCATED | LVCMOS33_OUT | PR6A | | | |
|
||||
| 60/1 | RCLKout | LOCATED | LVCMOS33_OUT | PR6A | | | |
|
||||
| 62/1 | RA[9] | LOCATED | LVCMOS33_OUT | PR5D | PCLKC1_0 | | |
|
||||
| 63/1 | RCLK | LOCATED | LVCMOS33_IN | PR5C | PCLKT1_0 | | |
|
||||
| 64/1 | RA[10] | LOCATED | LVCMOS33_OUT | PR5B | | | |
|
||||
|
@ -238,9 +239,10 @@ LOCATE COMP "RA[7]" SITE "75";
|
|||
LOCATE COMP "RA[8]" SITE "65";
|
||||
LOCATE COMP "RA[9]" SITE "62";
|
||||
LOCATE COMP "RBA[0]" SITE "58";
|
||||
LOCATE COMP "RBA[1]" SITE "60";
|
||||
LOCATE COMP "RBA[1]" SITE "47";
|
||||
LOCATE COMP "RCKE" SITE "53";
|
||||
LOCATE COMP "RCLK" SITE "63";
|
||||
LOCATE COMP "RCLKout" SITE "60";
|
||||
LOCATE COMP "RDQMH" SITE "51";
|
||||
LOCATE COMP "RDQML" SITE "48";
|
||||
LOCATE COMP "RD[0]" SITE "36";
|
||||
|
@ -269,5 +271,5 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Thu Sep 21 05:39:58 2023
|
||||
Sat Nov 18 02:06:08 2023
|
||||
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
SCHEMATIC START ;
|
||||
# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Thu Sep 21 05:39:44 2023
|
||||
# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Sat Nov 18 02:05:53 2023
|
||||
|
||||
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
|
||||
LOCATE COMP "RD[0]" SITE "36" ;
|
||||
|
@ -11,6 +11,7 @@ LOCATE COMP "nRCAS" SITE "52" ;
|
|||
LOCATE COMP "nRRAS" SITE "54" ;
|
||||
LOCATE COMP "nRWE" SITE "49" ;
|
||||
LOCATE COMP "RCKE" SITE "53" ;
|
||||
LOCATE COMP "RCLKout" SITE "60" ;
|
||||
LOCATE COMP "RCLK" SITE "63" ;
|
||||
LOCATE COMP "nRCS" SITE "57" ;
|
||||
LOCATE COMP "RD[7]" SITE "43" ;
|
||||
|
@ -32,7 +33,7 @@ LOCATE COMP "RA[3]" SITE "71" ;
|
|||
LOCATE COMP "RA[2]" SITE "69" ;
|
||||
LOCATE COMP "RA[1]" SITE "67" ;
|
||||
LOCATE COMP "RA[0]" SITE "66" ;
|
||||
LOCATE COMP "RBA[1]" SITE "60" ;
|
||||
LOCATE COMP "RBA[1]" SITE "47" ;
|
||||
LOCATE COMP "RBA[0]" SITE "58" ;
|
||||
LOCATE COMP "LED" SITE "34" ;
|
||||
LOCATE COMP "nFWE" SITE "15" ;
|
||||
|
@ -110,4 +111,5 @@ OUTPUT PORT "RD[4]" LOAD 9.000000 pF ;
|
|||
OUTPUT PORT "RD[5]" LOAD 9.000000 pF ;
|
||||
OUTPUT PORT "RD[6]" LOAD 9.000000 pF ;
|
||||
OUTPUT PORT "RD[7]" LOAD 9.000000 pF ;
|
||||
OUTPUT PORT "RCLKout" LOAD 5.000000 pF ;
|
||||
COMMERCIAL ;
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
#OS: Windows 8 6.2
|
||||
#Hostname: ZANEMACWIN11
|
||||
|
||||
# Thu Sep 21 05:39:33 2023
|
||||
# Sat Nov 18 02:05:39 2023
|
||||
|
||||
#Implementation: impl1
|
||||
|
||||
|
@ -51,13 +51,17 @@ Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 202
|
|||
@I::"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v" (library work)
|
||||
@I::"\\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-640HC\REFB.v" (library work)
|
||||
Verilog syntax check successful!
|
||||
File \\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v changed - recompiling
|
||||
Selecting top level module RAM2GS
|
||||
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1601:7:1601:12|Synthesizing module ODDRXE in library work.
|
||||
Running optimization stage 1 on ODDRXE .......
|
||||
Finished optimization stage 1 on ODDRXE (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
|
||||
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
|
||||
Running optimization stage 1 on VHI .......
|
||||
Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 98MB)
|
||||
Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
|
||||
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
|
||||
Running optimization stage 1 on VLO .......
|
||||
Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
|
||||
Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
|
||||
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
|
||||
Running optimization stage 1 on EFB .......
|
||||
Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
|
||||
|
@ -77,13 +81,15 @@ Running optimization stage 2 on VLO .......
|
|||
Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
|
||||
Running optimization stage 2 on VHI .......
|
||||
Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
|
||||
Running optimization stage 2 on ODDRXE .......
|
||||
Finished optimization stage 2 on ODDRXE (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
|
||||
|
||||
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)
|
||||
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 102MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:39:33 2023
|
||||
# Sat Nov 18 02:05:40 2023
|
||||
|
||||
###########################################################]
|
||||
###########################################################[
|
||||
|
@ -110,7 +116,7 @@ At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s;
|
|||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:39:34 2023
|
||||
# Sat Nov 18 02:05:40 2023
|
||||
|
||||
###########################################################]
|
||||
|
||||
|
@ -120,12 +126,12 @@ For a summary of runtime and memory usage for all design units, please see file:
|
|||
|
||||
@END
|
||||
|
||||
At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
|
||||
At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:39:34 2023
|
||||
# Sat Nov 18 02:05:40 2023
|
||||
|
||||
###########################################################]
|
||||
###########################################################[
|
||||
|
@ -146,18 +152,17 @@ Implementation : impl1
|
|||
Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
File \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_comp.srs changed - recompiling
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:39:35 2023
|
||||
# Sat Nov 18 02:05:42 2023
|
||||
|
||||
###########################################################]
|
||||
Premap Report
|
||||
|
||||
# Thu Sep 21 05:39:35 2023
|
||||
# Sat Nov 18 02:05:42 2023
|
||||
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
|
@ -176,10 +181,10 @@ Implementation : impl1
|
|||
Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @
|
||||
|
||||
|
||||
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
|
||||
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
|
||||
|
||||
|
||||
Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 140MB)
|
||||
Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 140MB)
|
||||
|
||||
Reading constraint file: \\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS.sdc
|
||||
@L: \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1_scck.rpt
|
||||
|
@ -203,7 +208,6 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h
|
|||
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
|
||||
@N: FX493 |Applying initial value "0" on instance Ready.
|
||||
@N: FX493 |Applying initial value "0" on instance RCKE.
|
||||
@N: FX493 |Applying initial value "0" on instance LEDEN.
|
||||
@N: FX493 |Applying initial value "0" on instance n8MEGEN.
|
||||
@N: FX493 |Applying initial value "1" on instance nRCAS.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdLEDEN.
|
||||
|
@ -229,11 +233,11 @@ Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapse
|
|||
Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
|
||||
|
||||
|
||||
Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
|
||||
Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
|
||||
|
||||
@N: FX1184 |Applying syn_allowed_resources blockrams=2 on top level netlist RAM2GS
|
||||
|
||||
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
|
||||
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
|
||||
|
||||
|
||||
|
||||
|
@ -317,12 +321,10 @@ Pre-mapping successful!
|
|||
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 103MB peak: 185MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Thu Sep 21 05:39:37 2023
|
||||
# Sat Nov 18 02:05:43 2023
|
||||
|
||||
###########################################################]
|
||||
Map & Optimize Report
|
||||
|
||||
# Thu Sep 21 05:39:37 2023
|
||||
# Sat Nov 18 02:05:44 2023
|
||||
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
|
@ -341,22 +343,22 @@ Implementation : impl1
|
|||
Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @
|
||||
|
||||
|
||||
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
|
||||
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
|
||||
|
||||
@N: MF916 |Option synthesis_strategy=base is enabled.
|
||||
@N: MF248 |Running in 64-bit mode.
|
||||
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
|
||||
|
||||
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 139MB)
|
||||
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
|
||||
|
||||
|
||||
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 139MB)
|
||||
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
|
||||
|
||||
|
||||
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
|
||||
|
||||
|
||||
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB)
|
||||
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB)
|
||||
|
||||
|
||||
|
||||
|
@ -365,8 +367,8 @@ Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapse
|
|||
|
||||
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB)
|
||||
|
||||
@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":163:4:163:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0]
|
||||
@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":150:4:150:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0]
|
||||
@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":166:4:166:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0]
|
||||
@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":153:4:153:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0]
|
||||
@N: FX493 |Applying initial value "0" on instance IS[0].
|
||||
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
|
||||
@N: FX493 |Applying initial value "0" on instance IS[1].
|
||||
|
@ -376,7 +378,7 @@ Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00
|
|||
Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 185MB peak: 185MB)
|
||||
|
||||
|
||||
Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 187MB peak: 187MB)
|
||||
Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB)
|
||||
|
||||
|
||||
Available hyper_sources - for debug and ip models
|
||||
|
@ -389,7 +391,7 @@ Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CP
|
|||
Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 187MB peak: 187MB)
|
||||
|
||||
|
||||
Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 187MB peak: 187MB)
|
||||
Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
|
||||
|
||||
|
||||
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
|
||||
|
@ -398,16 +400,16 @@ Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CP
|
|||
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
|
||||
|
||||
|
||||
Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 197MB peak: 197MB)
|
||||
Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 196MB peak: 196MB)
|
||||
|
||||
Pass CPU time Worst Slack Luts / Registers
|
||||
------------------------------------------------------------
|
||||
1 0h:00m:01s -2.98ns 201 / 106
|
||||
2 0h:00m:01s -2.98ns 217 / 106
|
||||
1 0h:00m:01s -2.98ns 202 / 106
|
||||
2 0h:00m:01s -2.98ns 215 / 106
|
||||
3 0h:00m:01s -2.76ns 215 / 106
|
||||
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":121:4:121:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 6 loads 1 time to improve timing.
|
||||
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":304:4:304:9|Replicating instance CmdValid (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.
|
||||
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":163:4:163:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 11 loads 1 time to improve timing.
|
||||
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":124:4:124:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 6 loads 1 time to improve timing.
|
||||
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":307:4:307:9|Replicating instance CmdValid (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.
|
||||
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":166:4:166:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 12 loads 1 time to improve timing.
|
||||
Timing driven replication report
|
||||
Added 3 Registers via timing driven replication
|
||||
Added 1 LUTs via timing driven replication
|
||||
|
@ -421,10 +423,10 @@ Finished technology timing optimizations and critical path resynthesis (Real Tim
|
|||
|
||||
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
|
||||
|
||||
Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 198MB peak: 198MB)
|
||||
Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 197MB peak: 197MB)
|
||||
|
||||
|
||||
Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 160MB peak: 198MB)
|
||||
Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 161MB peak: 198MB)
|
||||
|
||||
Writing Analyst data base \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_m.srm
|
||||
|
||||
|
@ -434,14 +436,15 @@ Writing EDIF Netlist and constraint files
|
|||
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.edi
|
||||
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
|
||||
|
||||
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 203MB peak: 203MB)
|
||||
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 202MB peak: 202MB)
|
||||
|
||||
|
||||
Finished Writing Netlists (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 203MB peak: 203MB)
|
||||
Finished Writing Netlists (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 202MB peak: 203MB)
|
||||
|
||||
|
||||
Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 201MB peak: 203MB)
|
||||
|
||||
@W: MT246 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":43:11:43:19|Blackbox ODDRXE is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
|
||||
@W: MT246 :"\\mac\icloud\repos\ram2gs\cpld\lcmxo2-640hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
|
||||
@N: MT615 |Found clock RCLK with period 16.00ns
|
||||
@N: MT615 |Found clock PHI2 with period 350.00ns
|
||||
|
@ -450,7 +453,7 @@ Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:0
|
|||
|
||||
|
||||
##### START OF TIMING REPORT #####[
|
||||
# Timing report written on Thu Sep 21 05:39:41 2023
|
||||
# Timing report written on Sat Nov 18 02:05:48 2023
|
||||
#
|
||||
|
||||
|
||||
|
@ -501,7 +504,7 @@ Starting Ending | constraint slack | constraint slack | constraint
|
|||
---------------------------------------------------------------------------------------------------------------
|
||||
System RCLK | 16.000 12.918 | No paths - | No paths - | No paths -
|
||||
RCLK System | 16.000 14.956 | No paths - | No paths - | No paths -
|
||||
RCLK RCLK | 16.000 9.040 | No paths - | No paths - | No paths -
|
||||
RCLK RCLK | 16.000 9.237 | No paths - | No paths - | No paths -
|
||||
RCLK PHI2 | 2.000 0.216 | No paths - | 1.000 -0.676 | No paths -
|
||||
RCLK nCRAS | No paths - | No paths - | 1.000 -0.784 | No paths -
|
||||
PHI2 RCLK | No paths - | No paths - | No paths - | 1.000 -1.828
|
||||
|
@ -540,30 +543,30 @@ CmdLEDEN PHI2 FD1P3AX Q CmdLEDEN 1.044
|
|||
Cmdn8MEGEN PHI2 FD1P3AX Q Cmdn8MEGEN 1.044 -1.589
|
||||
CmdUFMWrite PHI2 FD1P3AX Q CmdUFMWrite 1.044 -0.572
|
||||
CmdUFMData PHI2 FD1P3AX Q CmdUFMData 0.972 -0.500
|
||||
Bank_0io[0] PHI2 IFS1P3DX Q Bank[0] 0.972 169.081
|
||||
Bank_0io[1] PHI2 IFS1P3DX Q Bank[1] 0.972 169.081
|
||||
Bank_0io[2] PHI2 IFS1P3DX Q Bank[2] 0.972 169.081
|
||||
Bank_0io[3] PHI2 IFS1P3DX Q Bank[3] 0.972 169.081
|
||||
==========================================================================================
|
||||
|
||||
|
||||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
-----------------------------------------------------------------------------------------
|
||||
wb_adr[0] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
|
||||
wb_adr[1] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
|
||||
wb_adr[2] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
|
||||
wb_adr[3] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
|
||||
wb_adr[4] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
|
||||
wb_adr[5] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
|
||||
wb_adr[6] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
|
||||
wb_adr[7] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
|
||||
wb_dati[0] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
|
||||
wb_dati[1] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
|
||||
=========================================================================================
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
--------------------------------------------------------------------------------
|
||||
wb_adr[0] PHI2 FD1P3AX SP N_126_i 0.528 -1.828
|
||||
wb_adr[1] PHI2 FD1P3AX SP N_126_i 0.528 -1.828
|
||||
wb_adr[2] PHI2 FD1P3AX SP N_126_i 0.528 -1.828
|
||||
wb_adr[3] PHI2 FD1P3AX SP N_126_i 0.528 -1.828
|
||||
wb_adr[4] PHI2 FD1P3AX SP N_126_i 0.528 -1.828
|
||||
wb_adr[5] PHI2 FD1P3AX SP N_126_i 0.528 -1.828
|
||||
wb_adr[6] PHI2 FD1P3AX SP N_126_i 0.528 -1.828
|
||||
wb_adr[7] PHI2 FD1P3AX SP N_126_i 0.528 -1.828
|
||||
wb_dati[0] PHI2 FD1P3AX SP N_126_i 0.528 -1.828
|
||||
wb_dati[1] PHI2 FD1P3AX SP N_126_i 0.528 -1.828
|
||||
================================================================================
|
||||
|
||||
|
||||
|
||||
|
@ -594,7 +597,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r -
|
|||
CmdUFMShift Net - - - - 2
|
||||
CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r -
|
||||
CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r -
|
||||
un1_wb_rst14_i_0 Net - - - - 17
|
||||
N_126_i Net - - - - 17
|
||||
wb_adr[0] FD1P3AX SP In 0.000 2.357 r -
|
||||
=========================================================================================
|
||||
|
||||
|
@ -622,7 +625,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r -
|
|||
CmdUFMShift Net - - - - 2
|
||||
CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r -
|
||||
CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r -
|
||||
un1_wb_rst14_i_0 Net - - - - 17
|
||||
N_126_i Net - - - - 17
|
||||
wb_adr[7] FD1P3AX SP In 0.000 2.357 r -
|
||||
=========================================================================================
|
||||
|
||||
|
@ -650,7 +653,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r -
|
|||
CmdUFMShift Net - - - - 2
|
||||
CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r -
|
||||
CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r -
|
||||
un1_wb_rst14_i_0 Net - - - - 17
|
||||
N_126_i Net - - - - 17
|
||||
wb_adr[6] FD1P3AX SP In 0.000 2.357 r -
|
||||
=========================================================================================
|
||||
|
||||
|
@ -678,7 +681,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r -
|
|||
CmdUFMShift Net - - - - 2
|
||||
CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r -
|
||||
CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r -
|
||||
un1_wb_rst14_i_0 Net - - - - 17
|
||||
N_126_i Net - - - - 17
|
||||
wb_adr[5] FD1P3AX SP In 0.000 2.357 r -
|
||||
=========================================================================================
|
||||
|
||||
|
@ -706,7 +709,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r -
|
|||
CmdUFMShift Net - - - - 2
|
||||
CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r -
|
||||
CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r -
|
||||
un1_wb_rst14_i_0 Net - - - - 17
|
||||
N_126_i Net - - - - 17
|
||||
wb_adr[4] FD1P3AX SP In 0.000 2.357 r -
|
||||
=========================================================================================
|
||||
|
||||
|
@ -729,13 +732,13 @@ Instance Reference Type Pin Net Time Slac
|
|||
Ready_fast RCLK FD1S3AX Q Ready_fast 1.256 -0.784
|
||||
LEDEN RCLK FD1S3AX Q LEDEN 1.148 -0.676
|
||||
n8MEGEN RCLK FD1S3AX Q n8MEGEN 1.108 -0.636
|
||||
IS[1] RCLK FD1P3AX Q IS[1] 1.204 9.040
|
||||
IS[2] RCLK FD1P3AX Q IS[2] 1.188 9.056
|
||||
IS[3] RCLK FD1P3AX Q IS[3] 1.148 9.096
|
||||
InitReady RCLK FD1S3AX Q InitReady 1.339 9.228
|
||||
FS[15] RCLK FD1S3AX Q FS[15] 1.228 9.339
|
||||
FS[16] RCLK FD1S3AX Q FS[16] 1.188 9.379
|
||||
FS[17] RCLK FD1S3AX Q FS[17] 1.188 9.379
|
||||
InitReady RCLK FD1S3AX Q InitReady 1.337 9.237
|
||||
FS[16] RCLK FD1S3AX Q FS[16] 1.204 9.371
|
||||
FS[17] RCLK FD1S3AX Q FS[17] 1.204 9.371
|
||||
FS[15] RCLK FD1S3AX Q FS[15] 1.188 9.387
|
||||
S[0] RCLK FD1S3IX Q CO0 1.244 9.873
|
||||
S[1] RCLK FD1S3IX Q S[1] 1.236 9.881
|
||||
RASr2 RCLK FD1S3AX Q RASr2 1.228 9.889
|
||||
==================================================================================
|
||||
|
||||
|
||||
|
@ -832,7 +835,35 @@ Path information for path number 3:
|
|||
|
||||
Number of logic level(s): 1
|
||||
Starting point: Ready_fast / Q
|
||||
Ending point: RowA[0] / D
|
||||
Ending point: RBA_0io[1] / D
|
||||
The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
|
||||
The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin SCLK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
---------------------------------------------------------------------------------
|
||||
Ready_fast FD1S3AX Q Out 1.256 1.256 r -
|
||||
Ready_fast Net - - - - 14
|
||||
RBAd[1] ORCALUT4 B In 0.000 1.256 r -
|
||||
RBAd[1] ORCALUT4 Z Out 0.617 1.873 r -
|
||||
RBAd_0[1] Net - - - - 1
|
||||
RBA_0io[1] OFS1P3DX D In 0.000 1.873 r -
|
||||
=================================================================================
|
||||
|
||||
|
||||
Path information for path number 4:
|
||||
Requested Period: 1.000
|
||||
- Setup time: -0.089
|
||||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
= Required time: 1.089
|
||||
|
||||
- Propagation time: 1.873
|
||||
- Clock delay at starting point: 0.000 (ideal)
|
||||
= Slack (non-critical) : -0.784
|
||||
|
||||
Number of logic level(s): 1
|
||||
Starting point: Ready_fast / Q
|
||||
Ending point: RowA[1] / D
|
||||
The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
|
||||
The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
|
||||
|
||||
|
@ -841,14 +872,14 @@ Name Type Name Dir Delay Time Fan Out(s
|
|||
---------------------------------------------------------------------------------
|
||||
Ready_fast FD1S3AX Q Out 1.256 1.256 r -
|
||||
Ready_fast Net - - - - 14
|
||||
RowAd[0] ORCALUT4 B In 0.000 1.256 r -
|
||||
RowAd[0] ORCALUT4 Z Out 0.617 1.873 r -
|
||||
RowAd_0[0] Net - - - - 1
|
||||
RowA[0] FD1S3AX D In 0.000 1.873 r -
|
||||
RowAd[1] ORCALUT4 B In 0.000 1.256 r -
|
||||
RowAd[1] ORCALUT4 Z Out 0.617 1.873 r -
|
||||
RowAd_0[1] Net - - - - 1
|
||||
RowA[1] FD1S3AX D In 0.000 1.873 r -
|
||||
=================================================================================
|
||||
|
||||
|
||||
Path information for path number 4:
|
||||
Path information for path number 5:
|
||||
Requested Period: 1.000
|
||||
- Setup time: -0.089
|
||||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
|
@ -876,34 +907,6 @@ RowA[5] FD1S3AX D In 0.000 1.873 f -
|
|||
=================================================================================
|
||||
|
||||
|
||||
Path information for path number 5:
|
||||
Requested Period: 1.000
|
||||
- Setup time: -0.089
|
||||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
= Required time: 1.089
|
||||
|
||||
- Propagation time: 1.873
|
||||
- Clock delay at starting point: 0.000 (ideal)
|
||||
= Slack (non-critical) : -0.784
|
||||
|
||||
Number of logic level(s): 1
|
||||
Starting point: Ready_fast / Q
|
||||
Ending point: RowA[8] / D
|
||||
The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
|
||||
The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
---------------------------------------------------------------------------------
|
||||
Ready_fast FD1S3AX Q Out 1.256 1.256 r -
|
||||
Ready_fast Net - - - - 14
|
||||
RowAd[8] ORCALUT4 B In 0.000 1.256 r -
|
||||
RowAd[8] ORCALUT4 Z Out 0.617 1.873 r -
|
||||
RowAd_0[8] Net - - - - 1
|
||||
RowA[8] FD1S3AX D In 0.000 1.873 r -
|
||||
=================================================================================
|
||||
|
||||
|
||||
|
||||
|
||||
====================================
|
||||
|
@ -928,16 +931,16 @@ FWEr nCRAS FD1S3AX Q FWEr 1.180 -1.797
|
|||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
------------------------------------------------------------------------------------------
|
||||
nRCAS_0io nCRAS OFS1P3BX D N_248_i 1.089 -2.605
|
||||
nRCS_0io nCRAS OFS1P3BX D N_247_i 1.089 -1.797
|
||||
nRWE_0io nCRAS OFS1P3BX D N_49_i 1.089 -1.797
|
||||
nRowColSel nCRAS FD1S3IX D nRowColSel_0_0_0 1.089 -1.797
|
||||
RCKEEN nCRAS FD1S3AX D RCKEEN_8 1.089 -1.725
|
||||
==========================================================================================
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------------------
|
||||
nRCAS_0io nCRAS OFS1P3BX D N_251_i 1.089 -2.605
|
||||
nRCS_0io nCRAS OFS1P3BX D N_37_i 1.089 -1.797
|
||||
nRWE_0io nCRAS OFS1P3BX D N_252_i 1.089 -1.797
|
||||
nRowColSel nCRAS FD1S3IX D nRowColSel_0_0 1.089 -1.797
|
||||
RCKEEN nCRAS FD1S3AX D RCKEEN_8 1.089 -1.725
|
||||
========================================================================================
|
||||
|
||||
|
||||
|
||||
|
@ -971,10 +974,10 @@ CBR_fast_RNIQ31K1 ORCALUT4 Z Out 1.089 2.061 r -
|
|||
nRCAS_0_sqmuxa_1 Net - - - - 2
|
||||
nRCAS_0io_RNO_0 ORCALUT4 B In 0.000 2.061 r -
|
||||
nRCAS_0io_RNO_0 ORCALUT4 Z Out 1.017 3.077 r -
|
||||
N_248_i_sx Net - - - - 1
|
||||
nRCAS_0io_RNO ORCALUT4 D In 0.000 3.077 r -
|
||||
N_251_i_sx Net - - - - 1
|
||||
nRCAS_0io_RNO ORCALUT4 C In 0.000 3.077 r -
|
||||
nRCAS_0io_RNO ORCALUT4 Z Out 0.617 3.694 f -
|
||||
N_248_i Net - - - - 1
|
||||
N_251_i Net - - - - 1
|
||||
nRCAS_0io OFS1P3BX D In 0.000 3.694 f -
|
||||
====================================================================================
|
||||
|
||||
|
@ -995,19 +998,19 @@ Path information for path number 2:
|
|||
The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
|
||||
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
--------------------------------------------------------------------------------------
|
||||
CBR FD1S3AX Q Out 1.180 1.180 r -
|
||||
CBR Net - - - - 5
|
||||
RCKEEN_8_u_0_0_a2_2 ORCALUT4 A In 0.000 1.180 r -
|
||||
RCKEEN_8_u_0_0_a2_2 ORCALUT4 Z Out 1.089 2.269 f -
|
||||
N_590 Net - - - - 2
|
||||
nRCS_0io_RNO ORCALUT4 C In 0.000 2.269 f -
|
||||
nRCS_0io_RNO ORCALUT4 Z Out 0.617 2.885 r -
|
||||
N_247_i Net - - - - 1
|
||||
nRCS_0io OFS1P3BX D In 0.000 2.885 r -
|
||||
======================================================================================
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
------------------------------------------------------------------------------------
|
||||
CBR FD1S3AX Q Out 1.180 1.180 r -
|
||||
CBR Net - - - - 5
|
||||
RCKEEN_8_u_0_a2_2 ORCALUT4 A In 0.000 1.180 r -
|
||||
RCKEEN_8_u_0_a2_2 ORCALUT4 Z Out 1.089 2.269 f -
|
||||
N_141 Net - - - - 2
|
||||
nRCS_0io_RNO ORCALUT4 A In 0.000 2.269 f -
|
||||
nRCS_0io_RNO ORCALUT4 Z Out 0.617 2.885 r -
|
||||
N_37_i Net - - - - 1
|
||||
nRCS_0io OFS1P3BX D In 0.000 2.885 r -
|
||||
====================================================================================
|
||||
|
||||
|
||||
Path information for path number 3:
|
||||
|
@ -1026,19 +1029,19 @@ Path information for path number 3:
|
|||
The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
|
||||
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
---------------------------------------------------------------------------------
|
||||
FWEr FD1S3AX Q Out 1.180 1.180 r -
|
||||
FWEr Net - - - - 5
|
||||
nRCAS_r_i_0_a2 ORCALUT4 B In 0.000 1.180 r -
|
||||
nRCAS_r_i_0_a2 ORCALUT4 Z Out 1.089 2.269 f -
|
||||
N_248_i_1_0 Net - - - - 2
|
||||
nRCAS_0io_RNO ORCALUT4 C In 0.000 2.269 f -
|
||||
nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.885 r -
|
||||
N_248_i Net - - - - 1
|
||||
nRCAS_0io OFS1P3BX D In 0.000 2.885 r -
|
||||
=================================================================================
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
----------------------------------------------------------------------------------
|
||||
FWEr FD1S3AX Q Out 1.180 1.180 r -
|
||||
FWEr Net - - - - 5
|
||||
nRCS_9_u_i_a2_0 ORCALUT4 B In 0.000 1.180 r -
|
||||
nRCS_9_u_i_a2_0 ORCALUT4 Z Out 1.089 2.269 f -
|
||||
N_251_i_1 Net - - - - 2
|
||||
nRCAS_0io_RNO ORCALUT4 A In 0.000 2.269 f -
|
||||
nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.885 r -
|
||||
N_251_i Net - - - - 1
|
||||
nRCAS_0io OFS1P3BX D In 0.000 2.885 r -
|
||||
==================================================================================
|
||||
|
||||
|
||||
Path information for path number 4:
|
||||
|
@ -1057,19 +1060,19 @@ Path information for path number 4:
|
|||
The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
|
||||
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
--------------------------------------------------------------------------------------
|
||||
CBR FD1S3AX Q Out 1.180 1.180 r -
|
||||
CBR Net - - - - 5
|
||||
RCKEEN_8_u_0_0_a2_2 ORCALUT4 A In 0.000 1.180 r -
|
||||
RCKEEN_8_u_0_0_a2_2 ORCALUT4 Z Out 1.089 2.269 f -
|
||||
N_590 Net - - - - 2
|
||||
nRWE_0io_RNO ORCALUT4 B In 0.000 2.269 f -
|
||||
nRWE_0io_RNO ORCALUT4 Z Out 0.617 2.885 r -
|
||||
N_49_i Net - - - - 1
|
||||
nRWE_0io OFS1P3BX D In 0.000 2.885 r -
|
||||
======================================================================================
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
------------------------------------------------------------------------------------
|
||||
CBR FD1S3AX Q Out 1.180 1.180 r -
|
||||
CBR Net - - - - 5
|
||||
RCKEEN_8_u_0_a2_2 ORCALUT4 A In 0.000 1.180 r -
|
||||
RCKEEN_8_u_0_a2_2 ORCALUT4 Z Out 1.089 2.269 f -
|
||||
N_141 Net - - - - 2
|
||||
nRWE_0io_RNO ORCALUT4 B In 0.000 2.269 f -
|
||||
nRWE_0io_RNO ORCALUT4 Z Out 0.617 2.885 r -
|
||||
N_252_i Net - - - - 1
|
||||
nRWE_0io OFS1P3BX D In 0.000 2.885 r -
|
||||
====================================================================================
|
||||
|
||||
|
||||
Path information for path number 5:
|
||||
|
@ -1093,12 +1096,12 @@ Name Type Name Dir Delay Time Fan
|
|||
--------------------------------------------------------------------------------------
|
||||
FWEr FD1S3AX Q Out 1.180 1.180 r -
|
||||
FWEr Net - - - - 5
|
||||
nRowColSel_0_0_0_a2 ORCALUT4 B In 0.000 1.180 r -
|
||||
nRowColSel_0_0_0_a2 ORCALUT4 Z Out 1.089 2.269 r -
|
||||
N_248_i_1_1 Net - - - - 2
|
||||
nRowColSel_0_0_a2_1 ORCALUT4 B In 0.000 1.180 r -
|
||||
nRowColSel_0_0_a2_1 ORCALUT4 Z Out 1.089 2.269 r -
|
||||
N_251_i_1_0 Net - - - - 2
|
||||
nRCAS_0io_RNO ORCALUT4 B In 0.000 2.269 r -
|
||||
nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.885 f -
|
||||
N_248_i Net - - - - 1
|
||||
N_251_i Net - - - - 1
|
||||
nRCAS_0io OFS1P3BX D In 0.000 2.885 f -
|
||||
======================================================================================
|
||||
|
||||
|
@ -1127,14 +1130,14 @@ ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000
|
|||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
-----------------------------------------------------------------------------------
|
||||
LEDEN System FD1S3AX D LEDENe_0 16.089 12.918
|
||||
n8MEGEN System FD1S3AX D n8MEGENe_0 16.089 12.918
|
||||
wb_cyc_stb System FD1P3IX SP N_178 15.528 14.912
|
||||
===================================================================================
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
--------------------------------------------------------------------------------------------------
|
||||
LEDEN System FD1S3AX D LEDENe_0 16.089 12.918
|
||||
n8MEGEN System FD1S3AX D n8MEGENe_0 16.089 12.918
|
||||
wb_cyc_stb System FD1P3IX SP wb_cyc_stb_2_sqmuxa_i_0_0 15.528 14.912
|
||||
==================================================================================================
|
||||
|
||||
|
||||
|
||||
|
@ -1172,8 +1175,8 @@ ufmefb.EFBInst_0_RNISI191 ORCALUT4 Z Out 0.449 1.466 r
|
|||
N_4 Net - - - - 1
|
||||
CmdValid_RNIOOBE2 ORCALUT4 C In 0.000 1.466 r -
|
||||
CmdValid_RNIOOBE2 ORCALUT4 Z Out 1.089 2.554 r -
|
||||
CmdValid_RNIOOBE2 Net - - - - 2
|
||||
LEDENe ORCALUT4 B In 0.000 2.554 r -
|
||||
un1_FS_38_i Net - - - - 2
|
||||
LEDENe ORCALUT4 C In 0.000 2.554 r -
|
||||
LEDENe ORCALUT4 Z Out 0.617 3.171 r -
|
||||
LEDENe_0 Net - - - - 1
|
||||
LEDEN FD1S3AX D In 0.000 3.171 r -
|
||||
|
@ -1196,7 +1199,7 @@ Part: lcmxo2_640hc-4
|
|||
|
||||
Register bits: 109 of 640 (17%)
|
||||
PIC Latch: 0
|
||||
I/O cells: 63
|
||||
I/O cells: 64
|
||||
|
||||
|
||||
Details:
|
||||
|
@ -1211,12 +1214,13 @@ GSR: 1
|
|||
IB: 25
|
||||
IFS1P3DX: 9
|
||||
INV: 7
|
||||
OB: 30
|
||||
OB: 31
|
||||
ODDRXE: 1
|
||||
OFS1P3BX: 4
|
||||
OFS1P3DX: 11
|
||||
OFS1P3JX: 1
|
||||
ORCALUT4: 213
|
||||
PFUMX: 1
|
||||
ORCALUT4: 212
|
||||
PFUMX: 2
|
||||
PUR: 1
|
||||
VHI: 2
|
||||
VLO: 2
|
||||
|
@ -1225,6 +1229,6 @@ Mapper successful!
|
|||
At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 78MB peak: 203MB)
|
||||
|
||||
Process took 0h:00m:04s realtime, 0h:00m:04s cputime
|
||||
# Thu Sep 21 05:39:42 2023
|
||||
# Sat Nov 18 02:05:48 2023
|
||||
|
||||
###########################################################]
|
||||
|
|
|
@ -13,7 +13,7 @@ Setup and Hold Report
|
|||
|
||||
--------------------------------------------------------------------------------
|
||||
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
|
||||
Thu Sep 21 05:39:45 2023
|
||||
Sat Nov 18 02:05:54 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
|
@ -46,28 +46,28 @@ Passed: The following path meets requirements by 163.025ns (weighted slack = 326
|
|||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q Bank_0io[0] (from PHI2_c +)
|
||||
Source: FF Q Bank_0io[1] (from PHI2_c +)
|
||||
Destination: FF Data in CmdEnable (to PHI2_c -)
|
||||
|
||||
Delay: 9.223ns (33.1% logic, 66.9% route), 6 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
9.223ns physical path delay Din[0]_MGIOL to SLICE_17 meets
|
||||
9.223ns physical path delay Din[1]_MGIOL to SLICE_17 meets
|
||||
172.414ns delay constraint less
|
||||
0.166ns DIN_SET requirement (totaling 172.248ns) by 163.025ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path Din[0]_MGIOL to SLICE_17:
|
||||
Data path Din[1]_MGIOL to SLICE_17:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
C2INP_DEL --- 0.577 *[0]_MGIOL.CLK to *n[0]_MGIOL.IN Din[0]_MGIOL (from PHI2_c)
|
||||
ROUTE 1 e 1.234 *n[0]_MGIOL.IN to SLICE_93.A0 Bank[0]
|
||||
CTOF_DEL --- 0.495 SLICE_93.A0 to SLICE_93.F0 SLICE_93
|
||||
ROUTE 1 e 1.234 SLICE_93.F0 to SLICE_84.C0 un1_CmdEnable20_0_0_o3_10
|
||||
CTOF_DEL --- 0.495 SLICE_84.C0 to SLICE_84.F0 SLICE_84
|
||||
ROUTE 6 e 1.234 SLICE_84.F0 to SLICE_11.C1 un1_CmdEnable20_0_0_o3
|
||||
C2INP_DEL --- 0.577 *[1]_MGIOL.CLK to *n[1]_MGIOL.IN Din[1]_MGIOL (from PHI2_c)
|
||||
ROUTE 1 e 1.234 *n[1]_MGIOL.IN to SLICE_90.A0 Bank[1]
|
||||
CTOF_DEL --- 0.495 SLICE_90.A0 to SLICE_90.F0 SLICE_90
|
||||
ROUTE 1 e 1.234 SLICE_90.F0 to SLICE_80.C0 un1_CmdEnable20_0_0_o2_10
|
||||
CTOF_DEL --- 0.495 SLICE_80.C0 to SLICE_80.F0 SLICE_80
|
||||
ROUTE 6 e 1.234 SLICE_80.F0 to SLICE_11.C1 N_367
|
||||
CTOF_DEL --- 0.495 SLICE_11.C1 to SLICE_11.F1 SLICE_11
|
||||
ROUTE 3 e 1.234 SLICE_11.F1 to SLICE_33.B0 CmdEnable16
|
||||
CTOF_DEL --- 0.495 SLICE_33.B0 to SLICE_33.F0 SLICE_33
|
||||
|
@ -118,48 +118,46 @@ Report: 150.150MHz is the maximum frequency for this preference.
|
|||
|
||||
================================================================================
|
||||
Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
|
||||
878 items scored, 0 timing errors detected.
|
||||
891 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 6.049ns
|
||||
Passed: The following path meets requirements by 5.516ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q IS[1] (from RCLK_c +)
|
||||
Destination: FF Data in nRCAS_0io (to RCLK_c +)
|
||||
Source: FF Q S[0] (from RCLK_c +)
|
||||
Destination: FF Data in nRWE_0io (to RCLK_c +)
|
||||
|
||||
Delay: 9.798ns (34.9% logic, 65.1% route), 7 logic levels.
|
||||
Delay: 10.331ns (28.3% logic, 71.7% route), 6 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
9.798ns physical path delay SLICE_27 to nRCAS_MGIOL meets
|
||||
10.331ns physical path delay SLICE_16 to nRWE_MGIOL meets
|
||||
16.000ns delay constraint less
|
||||
0.153ns DO_SET requirement (totaling 15.847ns) by 6.049ns
|
||||
0.153ns DO_SET requirement (totaling 15.847ns) by 5.516ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path SLICE_27 to nRCAS_MGIOL:
|
||||
Data path SLICE_16 to nRWE_MGIOL:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.452 SLICE_27.CLK to SLICE_27.Q0 SLICE_27 (from RCLK_c)
|
||||
ROUTE 7 e 1.234 SLICE_27.Q0 to SLICE_74.A1 IS[1]
|
||||
CTOF_DEL --- 0.495 SLICE_74.A1 to SLICE_74.F1 SLICE_74
|
||||
ROUTE 2 e 0.480 SLICE_74.F1 to SLICE_74.B0 un1_nRCAS_6_sqmuxa_i_0_0_o2_0
|
||||
CTOF_DEL --- 0.495 SLICE_74.B0 to SLICE_74.F0 SLICE_74
|
||||
ROUTE 2 e 1.234 SLICE_74.F0 to SLICE_61.B1 N_408
|
||||
CTOF_DEL --- 0.495 SLICE_61.B1 to SLICE_61.F1 SLICE_61
|
||||
ROUTE 1 e 0.480 SLICE_61.F1 to SLICE_61.A0 un1_nRCAS_6_sqmuxa_i_0_0
|
||||
CTOF_DEL --- 0.495 SLICE_61.A0 to SLICE_61.F0 SLICE_61
|
||||
ROUTE 1 e 1.234 SLICE_61.F0 to SLICE_94.D0 nRCAS_r_i_0_o2_0_0
|
||||
CTOF_DEL --- 0.495 SLICE_94.D0 to SLICE_94.F0 SLICE_94
|
||||
ROUTE 1 e 0.480 SLICE_94.F0 to SLICE_94.A1 N_248_i_1
|
||||
CTOF_DEL --- 0.495 SLICE_94.A1 to SLICE_94.F1 SLICE_94
|
||||
ROUTE 1 e 1.234 SLICE_94.F1 to *AS_MGIOL.OPOS N_248_i (to RCLK_c)
|
||||
REG_DEL --- 0.452 SLICE_16.CLK to SLICE_16.Q0 SLICE_16 (from RCLK_c)
|
||||
ROUTE 12 e 1.234 SLICE_16.Q0 to SLICE_62.D1 CO0
|
||||
CTOF_DEL --- 0.495 SLICE_62.D1 to SLICE_62.F1 SLICE_62
|
||||
ROUTE 6 e 1.234 SLICE_62.F1 to SLICE_79.A1 IS_0_sqmuxa_0_o2
|
||||
CTOF_DEL --- 0.495 SLICE_79.A1 to SLICE_79.F1 SLICE_79
|
||||
ROUTE 2 e 1.234 SLICE_79.F1 to SLICE_28.D1 IS_0_sqmuxa_0_o3
|
||||
CTOF_DEL --- 0.495 SLICE_28.D1 to SLICE_28.F1 SLICE_28
|
||||
ROUTE 1 e 1.234 SLICE_28.F1 to SLICE_68.D1 nRWE_s_i_a2_1_0
|
||||
CTOF_DEL --- 0.495 SLICE_68.D1 to SLICE_68.F1 SLICE_68
|
||||
ROUTE 1 e 1.234 SLICE_68.F1 to SLICE_75.D0 nRWE_s_i_tz_0
|
||||
CTOF_DEL --- 0.495 SLICE_75.D0 to SLICE_75.F0 SLICE_75
|
||||
ROUTE 1 e 1.234 SLICE_75.F0 to *WE_MGIOL.OPOS N_252_i (to RCLK_c)
|
||||
--------
|
||||
9.798 (34.9% logic, 65.1% route), 7 logic levels.
|
||||
10.331 (28.3% logic, 71.7% route), 6 logic levels.
|
||||
|
||||
Report: 100.492MHz is the maximum frequency for this preference.
|
||||
Report: 95.383MHz is the maximum frequency for this preference.
|
||||
|
||||
Report Summary
|
||||
--------------
|
||||
|
@ -173,7 +171,7 @@ FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
|
|||
| | |
|
||||
FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
|
||||
| | |
|
||||
FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 100.492 MHz| 7
|
||||
FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 95.383 MHz| 6
|
||||
| | |
|
||||
----------------------------------------------------------------------------
|
||||
|
||||
|
@ -198,7 +196,7 @@ Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11
|
|||
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
|
||||
No transfer within this clock domain is found
|
||||
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 48
|
||||
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
|
||||
|
||||
Data transfers from:
|
||||
|
@ -228,11 +226,11 @@ Timing summary (Setup):
|
|||
Timing errors: 0 Score: 0
|
||||
Cumulative negative slack: 0
|
||||
|
||||
Constraints cover 1025 paths, 4 nets, and 741 connections (72.86% coverage)
|
||||
Constraints cover 1038 paths, 4 nets, and 732 connections (72.40% coverage)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
|
||||
Thu Sep 21 05:39:45 2023
|
||||
Sat Nov 18 02:05:54 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
|
@ -303,7 +301,7 @@ Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
|
|||
|
||||
================================================================================
|
||||
Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
|
||||
878 items scored, 0 timing errors detected.
|
||||
891 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
@ -369,7 +367,7 @@ Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11
|
|||
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
|
||||
No transfer within this clock domain is found
|
||||
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 48
|
||||
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
|
||||
|
||||
Data transfers from:
|
||||
|
@ -399,7 +397,7 @@ Timing summary (Hold):
|
|||
Timing errors: 0 Score: 0
|
||||
Cumulative negative slack: 0
|
||||
|
||||
Constraints cover 1025 paths, 4 nets, and 741 connections (72.86% coverage)
|
||||
Constraints cover 1038 paths, 4 nets, and 732 connections (72.40% coverage)
|
||||
|
||||
|
||||
|
||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -12,10 +12,10 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Thu Sep 21 05:40:10 2023
|
||||
Sat Nov 18 02:06:26 2023
|
||||
|
||||
|
||||
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC -w -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
|
||||
Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC -w -jedec -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
|
||||
|
||||
Loading design for application Bitgen from file RAM2GS_LCMXO2_640HC_impl1.ncd.
|
||||
Design name: RAM2GS
|
||||
|
@ -80,10 +80,20 @@ Creating bit map...
|
|||
|
||||
Bitstream Status: Final Version 1.95.
|
||||
|
||||
Saving bit stream in "RAM2GS_LCMXO2_640HC_impl1.bit".
|
||||
Saving bit stream in "RAM2GS_LCMXO2_640HC_impl1.jed".
|
||||
|
||||
===========
|
||||
UFM Summary.
|
||||
===========
|
||||
UFM Size: 191 Pages (128*191 Bits).
|
||||
UFM Utilization: General Purpose Flash Memory.
|
||||
|
||||
Available General Purpose Flash Memory: 191 Pages (Page 0 to Page 190).
|
||||
Initialized UFM Pages: 1 Page (Page 190).
|
||||
|
||||
Total CPU Time: 4 secs
|
||||
Total REAL Time: 5 secs
|
||||
Peak Memory Usage: 266 MB
|
||||
Total REAL Time: 4 secs
|
||||
Peak Memory Usage: 267 MB
|
||||
|
||||
|
||||
|
||||
|
|
|
@ -13,7 +13,7 @@ Hostname: ZANEMACWIN11
|
|||
|
||||
Implementation : impl1
|
||||
|
||||
# Written on Thu Sep 21 05:39:36 2023
|
||||
# Written on Sat Nov 18 02:05:43 2023
|
||||
|
||||
##### DESIGN INFO #######################################################
|
||||
|
||||
|
@ -103,6 +103,7 @@ p:RA[11]
|
|||
p:RBA[0]
|
||||
p:RBA[1]
|
||||
p:RCKE
|
||||
p:RCLKout
|
||||
p:RDQMH
|
||||
p:RDQML
|
||||
p:RD[0] (bidir end point)
|
||||
|
|
|
@ -38,7 +38,7 @@ Performance Hardware Data Status: Final Version 34.4.
|
|||
// Package: TQFP100
|
||||
// ncd File: ram2gs_lcmxo2_640hc_impl1.ncd
|
||||
// Version: Diamond (64-bit) 3.12.1.454
|
||||
// Written on Thu Sep 21 05:40:03 2023
|
||||
// Written on Sat Nov 18 02:06:14 2023
|
||||
// M: Minimum Performance Grade
|
||||
// iotiming RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
|
||||
|
||||
|
@ -50,95 +50,96 @@ Worst Case Results across Performance Grades (M, 6, 5, 4):
|
|||
|
||||
Port Clock Edge Setup Performance_Grade Hold Performance_Grade
|
||||
----------------------------------------------------------------------
|
||||
CROW[0] nCRAS F 2.429 4 -0.163 M
|
||||
CROW[1] nCRAS F 1.927 4 -0.005 M
|
||||
Din[0] PHI2 F 5.424 4 3.636 4
|
||||
Din[0] nCCAS F 1.913 4 -0.130 M
|
||||
Din[1] PHI2 F 5.162 4 3.516 4
|
||||
Din[1] nCCAS F 2.007 4 -0.156 M
|
||||
Din[2] PHI2 F 5.078 4 3.516 4
|
||||
Din[2] nCCAS F 0.876 4 0.346 4
|
||||
Din[3] PHI2 F 6.152 4 3.516 4
|
||||
Din[3] nCCAS F 0.245 4 0.869 4
|
||||
Din[4] PHI2 F 5.240 4 3.516 4
|
||||
Din[4] nCCAS F 0.714 4 0.460 4
|
||||
Din[5] PHI2 F 6.035 4 3.516 4
|
||||
Din[5] nCCAS F 0.751 4 0.419 4
|
||||
Din[6] PHI2 F 4.496 4 3.636 4
|
||||
Din[6] nCCAS F 1.518 4 -0.020 M
|
||||
Din[7] PHI2 F 4.936 4 3.636 4
|
||||
Din[7] nCCAS F 1.852 4 -0.081 M
|
||||
MAin[0] PHI2 F 5.207 4 0.531 4
|
||||
MAin[0] nCRAS F 1.658 4 0.036 M
|
||||
MAin[1] PHI2 F 3.450 4 0.460 4
|
||||
MAin[1] nCRAS F 2.014 4 -0.043 M
|
||||
MAin[2] PHI2 F 7.941 4 -0.604 M
|
||||
MAin[2] nCRAS F 1.001 4 0.498 4
|
||||
MAin[3] PHI2 F 8.770 4 -0.865 M
|
||||
MAin[3] nCRAS F 2.190 4 -0.151 M
|
||||
MAin[4] PHI2 F 9.575 4 -1.072 M
|
||||
MAin[4] nCRAS F 1.331 4 0.186 4
|
||||
MAin[5] PHI2 F 9.093 4 -0.925 M
|
||||
MAin[5] nCRAS F 1.329 4 0.186 4
|
||||
MAin[6] PHI2 F 9.450 4 -1.036 M
|
||||
MAin[6] nCRAS F 1.323 4 0.191 4
|
||||
MAin[7] PHI2 F 8.247 4 -0.706 M
|
||||
MAin[7] nCRAS F 1.258 4 0.267 4
|
||||
MAin[8] nCRAS F 0.994 4 0.504 4
|
||||
MAin[9] nCRAS F 0.614 4 0.830 4
|
||||
CROW[0] nCRAS F 2.058 4 -0.092 M
|
||||
CROW[1] nCRAS F 2.269 4 -0.117 M
|
||||
Din[0] PHI2 F 7.415 4 3.636 4
|
||||
Din[0] nCCAS F 2.760 4 -0.330 M
|
||||
Din[1] PHI2 F 6.384 4 3.516 4
|
||||
Din[1] nCCAS F 1.112 4 0.128 4
|
||||
Din[2] PHI2 F 6.717 4 3.516 4
|
||||
Din[2] nCCAS F 0.113 4 0.982 4
|
||||
Din[3] PHI2 F 5.806 4 3.516 4
|
||||
Din[3] nCCAS F 1.105 4 0.134 4
|
||||
Din[4] PHI2 F 6.853 4 3.516 4
|
||||
Din[4] nCCAS F 1.538 4 -0.010 M
|
||||
Din[5] PHI2 F 7.478 4 3.516 4
|
||||
Din[5] nCCAS F 0.714 4 0.460 4
|
||||
Din[6] PHI2 F 5.667 4 3.636 4
|
||||
Din[6] nCCAS F 1.504 4 -0.015 M
|
||||
Din[7] PHI2 F 5.567 4 3.636 4
|
||||
Din[7] nCCAS F 1.063 4 0.194 4
|
||||
MAin[0] PHI2 F 4.483 4 0.742 4
|
||||
MAin[0] nCRAS F 1.204 4 0.334 4
|
||||
MAin[1] PHI2 F 4.440 4 0.520 4
|
||||
MAin[1] nCRAS F 1.245 4 0.313 4
|
||||
MAin[2] PHI2 F 9.497 4 -0.729 M
|
||||
MAin[2] nCRAS F 0.758 4 0.714 4
|
||||
MAin[3] PHI2 F 9.534 4 -0.752 M
|
||||
MAin[3] nCRAS F 0.454 4 0.874 4
|
||||
MAin[4] PHI2 F 7.882 4 -0.326 M
|
||||
MAin[4] nCRAS F 0.832 4 0.632 4
|
||||
MAin[5] PHI2 F 10.136 4 -0.894 M
|
||||
MAin[5] nCRAS F 0.830 4 0.632 4
|
||||
MAin[6] PHI2 F 8.759 4 -0.555 M
|
||||
MAin[6] nCRAS F 1.259 4 0.268 4
|
||||
MAin[7] PHI2 F 8.430 4 -0.434 M
|
||||
MAin[7] nCRAS F 0.881 4 0.510 4
|
||||
MAin[8] nCRAS F 1.066 4 0.422 4
|
||||
MAin[9] nCRAS F 0.723 4 0.746 4
|
||||
PHI2 RCLK R -0.005 M 2.116 4
|
||||
nCCAS RCLK R 3.191 4 -0.531 M
|
||||
nCCAS nCRAS F 3.195 4 -0.341 M
|
||||
nCRAS RCLK R 2.797 4 -0.402 M
|
||||
nFWE PHI2 F 8.238 4 -0.666 M
|
||||
nFWE nCRAS F 1.140 4 0.400 4
|
||||
nCCAS RCLK R 3.614 4 -0.637 M
|
||||
nCCAS nCRAS F 3.629 4 -0.447 M
|
||||
nCRAS RCLK R 3.040 4 -0.485 M
|
||||
nFWE PHI2 F 8.830 4 -0.567 M
|
||||
nFWE nCRAS F 0.454 4 0.874 4
|
||||
|
||||
|
||||
// Clock to Output Delay
|
||||
|
||||
Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
|
||||
Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
|
||||
------------------------------------------------------------------------
|
||||
LED RCLK R 10.962 4 3.218 M
|
||||
LED nCRAS F 10.815 4 3.159 M
|
||||
RA[0] RCLK R 10.143 4 3.128 M
|
||||
RA[0] nCRAS F 11.178 4 3.358 M
|
||||
RA[10] RCLK R 7.578 4 2.578 M
|
||||
RA[11] PHI2 R 9.098 4 3.021 M
|
||||
RA[1] RCLK R 10.676 4 3.248 M
|
||||
RA[1] nCRAS F 11.215 4 3.370 M
|
||||
RA[2] RCLK R 11.199 4 3.402 M
|
||||
RA[2] nCRAS F 11.518 4 3.451 M
|
||||
RA[3] RCLK R 10.446 4 3.209 M
|
||||
RA[3] nCRAS F 11.264 4 3.364 M
|
||||
RA[4] RCLK R 10.446 4 3.209 M
|
||||
RA[4] nCRAS F 11.484 4 3.438 M
|
||||
RA[5] RCLK R 11.199 4 3.402 M
|
||||
RA[5] nCRAS F 11.264 4 3.364 M
|
||||
RA[6] RCLK R 11.424 4 3.444 M
|
||||
RA[6] nCRAS F 11.388 4 3.388 M
|
||||
RA[7] RCLK R 11.112 4 3.370 M
|
||||
RA[7] nCRAS F 11.608 4 3.487 M
|
||||
RA[8] RCLK R 10.916 4 3.308 M
|
||||
RA[8] nCRAS F 11.380 4 3.415 M
|
||||
RA[9] RCLK R 11.115 4 3.362 M
|
||||
RA[9] nCRAS F 11.201 4 3.380 M
|
||||
RBA[0] nCRAS F 8.645 4 2.828 M
|
||||
RBA[1] nCRAS F 8.645 4 2.828 M
|
||||
RCKE RCLK R 8.593 4 2.793 M
|
||||
RDQMH RCLK R 10.909 4 3.327 M
|
||||
RDQML RCLK R 10.348 4 3.207 M
|
||||
RD[0] nCCAS F 8.761 4 2.984 M
|
||||
RD[1] nCCAS F 8.761 4 2.984 M
|
||||
RD[2] nCCAS F 8.761 4 2.984 M
|
||||
RD[3] nCCAS F 8.761 4 2.984 M
|
||||
RD[4] nCCAS F 8.761 4 2.984 M
|
||||
RD[5] nCCAS F 8.761 4 2.984 M
|
||||
RD[6] nCCAS F 8.761 4 2.984 M
|
||||
RD[7] nCCAS F 8.761 4 2.984 M
|
||||
nRCAS RCLK R 7.578 4 2.578 M
|
||||
nRCS RCLK R 7.578 4 2.578 M
|
||||
nRRAS RCLK R 7.578 4 2.578 M
|
||||
nRWE RCLK R 7.558 4 2.585 M
|
||||
LED RCLK R 11.284 4 2.893 M
|
||||
LED nCRAS F 11.111 4 3.244 M
|
||||
RA[0] RCLK R 10.888 4 3.313 M
|
||||
RA[0] nCRAS F 11.968 4 3.554 M
|
||||
RA[10] RCLK R 7.578 4 2.578 M
|
||||
RA[11] PHI2 R 9.098 4 3.021 M
|
||||
RA[1] RCLK R 11.272 4 3.408 M
|
||||
RA[1] nCRAS F 11.484 4 3.438 M
|
||||
RA[2] RCLK R 11.749 4 3.528 M
|
||||
RA[2] nCRAS F 11.267 4 3.385 M
|
||||
RA[3] RCLK R 11.291 4 3.431 M
|
||||
RA[3] nCRAS F 11.596 4 3.449 M
|
||||
RA[4] RCLK R 10.696 4 3.276 M
|
||||
RA[4] nCRAS F 11.720 4 3.503 M
|
||||
RA[5] RCLK R 11.228 4 3.401 M
|
||||
RA[5] nCRAS F 11.364 4 3.427 M
|
||||
RA[6] RCLK R 10.132 4 3.112 M
|
||||
RA[6] nCRAS F 10.958 4 3.284 M
|
||||
RA[7] RCLK R 11.404 4 3.446 M
|
||||
RA[7] nCRAS F 11.918 4 3.561 M
|
||||
RA[8] RCLK R 10.488 4 3.236 M
|
||||
RA[8] nCRAS F 11.512 4 3.463 M
|
||||
RA[9] RCLK R 10.941 4 3.329 M
|
||||
RA[9] nCRAS F 11.074 4 3.356 M
|
||||
RBA[0] nCRAS F 8.645 4 2.828 M
|
||||
RBA[1] nCRAS F 8.625 4 2.835 M
|
||||
RCKE RCLK R 9.454 4 3.006 M
|
||||
RCLKout RCLK R 6.857 4 1.980 M
|
||||
RDQMH RCLK R 9.846 4 3.033 M
|
||||
RDQML RCLK R 9.741 4 3.008 M
|
||||
RD[0] nCCAS F 8.761 4 2.984 M
|
||||
RD[1] nCCAS F 8.761 4 2.984 M
|
||||
RD[2] nCCAS F 8.761 4 2.984 M
|
||||
RD[3] nCCAS F 8.761 4 2.984 M
|
||||
RD[4] nCCAS F 8.761 4 2.984 M
|
||||
RD[5] nCCAS F 8.761 4 2.984 M
|
||||
RD[6] nCCAS F 8.761 4 2.984 M
|
||||
RD[7] nCCAS F 8.761 4 2.984 M
|
||||
nRCAS RCLK R 7.578 4 2.578 M
|
||||
nRCS RCLK R 7.578 4 2.578 M
|
||||
nRRAS RCLK R 7.578 4 2.578 M
|
||||
nRWE RCLK R 7.558 4 2.585 M
|
||||
WARNING: you must also run trce with hold speed: 4
|
||||
WARNING: you must also run trce with setup speed: M
|
||||
|
||||
|
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
@ -23,7 +23,7 @@ Target Vendor: LATTICE
|
|||
Target Device: LCMXO2-640HCTQFP100
|
||||
Target Performance: 4
|
||||
Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454
|
||||
Mapped on: 09/21/23 05:39:43
|
||||
Mapped on: 11/18/23 02:05:52
|
||||
|
||||
|
||||
<A name="mrp_ds"></A><B><U><big>Design Summary</big></U></B>
|
||||
|
@ -34,12 +34,24 @@ Mapped on: 09/21/23 05:39:43
|
|||
SLICEs as Logic/ROM: 120 out of 320 (38%)
|
||||
SLICEs as RAM: 0 out of 240 (0%)
|
||||
SLICEs as Carry: 10 out of 320 (3%)
|
||||
Number of LUT4s: 237 out of 640 (37%)
|
||||
Number used as logic LUTs: 217
|
||||
Number of LUT4s: 238 out of 640 (37%)
|
||||
Number used as logic LUTs: 218
|
||||
Number used as distributed RAM: 0
|
||||
Number used as ripple logic: 20
|
||||
Number used as shift registers: 0
|
||||
Number of PIO sites used: 63 + 4(JTAG) out of 79 (85%)
|
||||
Number of PIO sites used: 64 + 4(JTAG) out of 79 (86%)
|
||||
Number of IDDR/ODDR/TDDR cells used: 1 out of 237 (0%)
|
||||
Number of IDDR cells: 0
|
||||
Number of ODDR cells: 1
|
||||
Number of TDDR cells: 0
|
||||
Number of PIO using at least one IDDR/ODDR/TDDR: 1 (0 differential)
|
||||
Number of PIO using IDDR only: 0 (0 differential)
|
||||
Number of PIO using ODDR only: 1 (0 differential)
|
||||
Number of PIO using TDDR only: 0 (0 differential)
|
||||
Number of PIO using IDDR/ODDR: 0 (0 differential)
|
||||
Number of PIO using IDDR/TDDR: 0 (0 differential)
|
||||
Number of PIO using ODDR/TDDR: 0 (0 differential)
|
||||
Number of PIO using IDDR/ODDR/TDDR: 0 (0 differential)
|
||||
Number of block RAMs: 0 out of 2 (0%)
|
||||
Number of GSRs: 0 out of 1 (0%)
|
||||
EFB used : Yes
|
||||
|
@ -55,20 +67,20 @@ Mapped on: 09/21/23 05:39:43
|
|||
Number of DCMA: 0 out of 2 (0%)
|
||||
Notes:-
|
||||
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
|
||||
|
||||
distributed RAMs) + 2*(Number of ripple logic)
|
||||
2. Number of logic LUT4s does not include count of distributed RAM and
|
||||
ripple logic.
|
||||
Number of clocks: 4
|
||||
Net PHI2_c: 20 loads, 9 rising, 11 falling (Driver: PIO PHI2 )
|
||||
Net RCLK_c: 47 loads, 47 rising, 0 falling (Driver: PIO RCLK )
|
||||
Net RCLK_c: 48 loads, 48 rising, 0 falling (Driver: PIO RCLK )
|
||||
Net nCRAS_c: 9 loads, 0 rising, 9 falling (Driver: PIO nCRAS )
|
||||
Net nCCAS_c: 8 loads, 0 rising, 8 falling (Driver: PIO nCCAS )
|
||||
Number of Clock Enables: 5
|
||||
Net N_178: 1 loads, 1 LSLICEs
|
||||
Net wb_cyc_stb_2_sqmuxa_i_0_0: 1 loads, 1 LSLICEs
|
||||
Net XOR8MEG18: 5 loads, 5 LSLICEs
|
||||
Net N_360_i: 2 loads, 2 LSLICEs
|
||||
|
||||
Net un1_wb_rst14_i_0: 9 loads, 9 LSLICEs
|
||||
Net N_126_i: 9 loads, 9 LSLICEs
|
||||
Net N_261_i: 2 loads, 2 LSLICEs
|
||||
Net CmdUFMData_1_sqmuxa: 1 loads, 1 LSLICEs
|
||||
Number of LSRs: 5
|
||||
Net RA10s_i: 1 loads, 0 LSLICEs
|
||||
|
@ -78,16 +90,16 @@ Mapped on: 09/21/23 05:39:43
|
|||
Net RASr2: 2 loads, 2 LSLICEs
|
||||
Number of nets driven by tri-state buffers: 0
|
||||
Top 10 highest fanout non-clock nets:
|
||||
Net InitReady: 41 loads
|
||||
Net FS[11]: 23 loads
|
||||
Net InitReady: 40 loads
|
||||
Net FS[13]: 22 loads
|
||||
Net FS[10]: 21 loads
|
||||
Net FS[12]: 21 loads
|
||||
Net FS[9]: 20 loads
|
||||
Net FS[14]: 18 loads
|
||||
Net CO0: 15 loads
|
||||
Net FS[11]: 21 loads
|
||||
Net FS[12]: 19 loads
|
||||
Net FS[14]: 19 loads
|
||||
Net FS[10]: 18 loads
|
||||
Net FS[9]: 17 loads
|
||||
Net Ready: 14 loads
|
||||
Net Ready_fast: 14 loads
|
||||
Net N_214: 13 loads
|
||||
Net CO0: 12 loads
|
||||
|
||||
|
||||
|
||||
|
@ -115,6 +127,7 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
|||
+---------------------+-----------+-----------+------------+
|
||||
| IO Name | Direction | Levelmode | IO |
|
||||
| | | IO_TYPE | Register |
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RD[0] | BIDIR | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
@ -127,7 +140,6 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
|||
| RDQMH | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRCAS | OUTPUT | LVCMOS33 | OUT |
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRRAS | OUTPUT | LVCMOS33 | OUT |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
@ -135,6 +147,8 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
|||
+---------------------+-----------+-----------+------------+
|
||||
| RCKE | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RCLKout | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RCLK | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nRCS | OUTPUT | LVCMOS33 | OUT |
|
||||
|
@ -170,6 +184,7 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
|||
| RA[4] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[3] | OUTPUT | LVCMOS33 | |
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| RA[2] | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
@ -184,7 +199,6 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
|||
| LED | OUTPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nFWE | INPUT | LVCMOS33 | |
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| nCRAS | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
@ -227,6 +241,7 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
|||
| MAin[9] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[8] | INPUT | LVCMOS33 | |
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[7] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
@ -241,7 +256,6 @@ WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
|
|||
| MAin[2] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[1] | INPUT | LVCMOS33 | |
|
||||
|
||||
+---------------------+-----------+-----------+------------+
|
||||
| MAin[0] | INPUT | LVCMOS33 | |
|
||||
+---------------------+-----------+-----------+------------+
|
||||
|
@ -254,7 +268,6 @@ Block GSR_INST undriven or does not drive anything - clipped.
|
|||
Signal nCRAS_c_i was merged into signal nCRAS_c
|
||||
Signal RASr2_i was merged into signal RASr2
|
||||
Signal XOR8MEG.CN was merged into signal PHI2_c
|
||||
Signal GND undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/VCC undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/GND undriven or does not drive anything - clipped.
|
||||
Signal FS_s_0_S1[17] undriven or does not drive anything - clipped.
|
||||
|
@ -286,6 +299,7 @@ Signal ufmefb/I2C2SDAOEN undriven or does not drive anything - clipped.
|
|||
Signal ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SCLOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
|
||||
|
||||
Signal ufmefb/I2C1SDAOEN undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/I2C1SCLOEN undriven or does not drive anything - clipped.
|
||||
|
@ -299,7 +313,6 @@ Signal ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
|
|||
Signal ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
|
||||
|
||||
Signal ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
|
||||
Signal ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
|
||||
|
@ -320,7 +333,6 @@ Signal N_1 undriven or does not drive anything - clipped.
|
|||
Block nCRAS_pad_RNIBPVB was optimized away.
|
||||
Block RASr2_RNIAFR1 was optimized away.
|
||||
Block XOR8MEG.CN was optimized away.
|
||||
Block GND was optimized away.
|
||||
Block ufmefb/VCC was optimized away.
|
||||
Block ufmefb/GND was optimized away.
|
||||
|
||||
|
@ -345,6 +357,7 @@ Block ufmefb/GND was optimized away.
|
|||
I2C Function Summary:
|
||||
--------------------
|
||||
None
|
||||
|
||||
SPI Function Summary:
|
||||
--------------------
|
||||
None
|
||||
|
@ -358,7 +371,6 @@ Block ufmefb/GND was optimized away.
|
|||
Available General
|
||||
Purpose Flash Memory: 191 Pages (191*128 Bits)
|
||||
|
||||
|
||||
EBR Blocks with Unique
|
||||
Initialization Data: 0
|
||||
|
||||
|
@ -400,18 +412,6 @@ Instance Name: ufmefb/EFBInst_0
|
|||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
|
@ -14,7 +14,7 @@ Performance Grade: 4
|
|||
PACKAGE: TQFP100
|
||||
Package Status: Final Version 1.39
|
||||
|
||||
Thu Sep 21 05:39:54 2023
|
||||
Sat Nov 18 02:06:05 2023
|
||||
|
||||
Pinout by Port Name:
|
||||
+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
|
||||
|
@ -63,9 +63,10 @@ Pinout by Port Name:
|
|||
| RA[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RA[9] | 62/1 | LVCMOS33_OUT | PR5D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RBA[0] | 58/1 | LVCMOS33_OUT | PR6C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RBA[1] | 60/1 | LVCMOS33_OUT | PR6A | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RBA[1] | 47/2 | LVCMOS33_OUT | PB14B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RCKE | 53/1 | LVCMOS33_OUT | PR7B | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RCLK | 63/1 | LVCMOS33_IN | PR5C | | | CLAMP:ON HYSTERESIS:SMALL |
|
||||
| RCLKout | 60/1 | LVCMOS33_OUT | PR6A | | | DRIVE:24mA SLEW:FAST |
|
||||
| RDQMH | 51/1 | LVCMOS33_OUT | PR7D | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RDQML | 48/2 | LVCMOS33_OUT | PB14C | | | DRIVE:4mA SLEW:SLOW |
|
||||
| RD[0] | 36/2 | LVCMOS33_BIDI | PB10A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW |
|
||||
|
@ -143,7 +144,7 @@ Vccio by Bank:
|
|||
| 42/2 | RD[6] | LOCATED | LVCMOS33_BIDI | PB12C | | | |
|
||||
| 43/2 | RD[7] | LOCATED | LVCMOS33_BIDI | PB12D | | | |
|
||||
| 45/2 | unused, PULL:DOWN | | | PB14A | | | |
|
||||
| 47/2 | unused, PULL:DOWN | | | PB14B | | | |
|
||||
| 47/2 | RBA[1] | LOCATED | LVCMOS33_OUT | PB14B | | | |
|
||||
| 48/2 | RDQML | LOCATED | LVCMOS33_OUT | PB14C | SN | | |
|
||||
| 49/2 | nRWE | LOCATED | LVCMOS33_OUT | PB14D | SI/SISPI | | |
|
||||
| 51/1 | RDQMH | LOCATED | LVCMOS33_OUT | PR7D | | | |
|
||||
|
@ -153,7 +154,7 @@ Vccio by Bank:
|
|||
| 57/1 | nRCS | LOCATED | LVCMOS33_OUT | PR6D | | | |
|
||||
| 58/1 | RBA[0] | LOCATED | LVCMOS33_OUT | PR6C | | | |
|
||||
| 59/1 | RA[11] | LOCATED | LVCMOS33_OUT | PR6B | | | |
|
||||
| 60/1 | RBA[1] | LOCATED | LVCMOS33_OUT | PR6A | | | |
|
||||
| 60/1 | RCLKout | LOCATED | LVCMOS33_OUT | PR6A | | | |
|
||||
| 62/1 | RA[9] | LOCATED | LVCMOS33_OUT | PR5D | PCLKC1_0 | | |
|
||||
| 63/1 | RCLK | LOCATED | LVCMOS33_IN | PR5C | PCLKT1_0 | | |
|
||||
| 64/1 | RA[10] | LOCATED | LVCMOS33_OUT | PR5B | | | |
|
||||
|
@ -247,9 +248,10 @@ LOCATE COMP "RA[7]" SITE "75";
|
|||
LOCATE COMP "RA[8]" SITE "65";
|
||||
LOCATE COMP "RA[9]" SITE "62";
|
||||
LOCATE COMP "RBA[0]" SITE "58";
|
||||
LOCATE COMP "RBA[1]" SITE "60";
|
||||
LOCATE COMP "RBA[1]" SITE "47";
|
||||
LOCATE COMP "RCKE" SITE "53";
|
||||
LOCATE COMP "RCLK" SITE "63";
|
||||
LOCATE COMP "RCLKout" SITE "60";
|
||||
LOCATE COMP "RDQMH" SITE "51";
|
||||
LOCATE COMP "RDQML" SITE "48";
|
||||
LOCATE COMP "RD[0]" SITE "36";
|
||||
|
@ -278,7 +280,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Thu Sep 21 05:39:58 2023
|
||||
Sat Nov 18 02:06:08 2023
|
||||
|
||||
|
||||
|
||||
|
|
|
@ -12,7 +12,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Thu Sep 21 05:39:47 2023
|
||||
Sat Nov 18 02:05:56 2023
|
||||
|
||||
C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO2_640HC_impl1.p2t
|
||||
RAM2GS_LCMXO2_640HC_impl1_map.ncd RAM2GS_LCMXO2_640HC_impl1.dir
|
||||
|
@ -26,17 +26,17 @@ Preference file: RAM2GS_LCMXO2_640HC_impl1.prf.
|
|||
Level/ Number Worst Timing Worst Timing Run NCD
|
||||
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
|
||||
---------- -------- ----- ------ ----------- ----------- ---- ------
|
||||
5_1 * 0 5.772 0 0.304 0 13 Completed
|
||||
5_1 * 0 6.245 0 0.304 0 15 Completed
|
||||
* : Design saved.
|
||||
|
||||
Total (real) run time for 1-seed: 13 secs
|
||||
Total (real) run time for 1-seed: 15 secs
|
||||
|
||||
par done!
|
||||
|
||||
Note: user must run 'Trace' for timing closure signoff.
|
||||
|
||||
Lattice Place and Route Report for Design "RAM2GS_LCMXO2_640HC_impl1_map.ncd"
|
||||
Thu Sep 21 05:39:47 2023
|
||||
Sat Nov 18 02:05:56 2023
|
||||
|
||||
|
||||
<A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
|
||||
|
@ -63,23 +63,23 @@ Ignore Preference Error(s): True
|
|||
|
||||
<A name="par_dus"></A><B><U><big>Device utilization summary:</big></U></B>
|
||||
|
||||
PIO (prelim) 63+4(JTAG)/80 84% used
|
||||
63+4(JTAG)/79 85% bonded
|
||||
IOLOGIC 25/80 31% used
|
||||
PIO (prelim) 64+4(JTAG)/80 85% used
|
||||
64+4(JTAG)/79 86% bonded
|
||||
IOLOGIC 26/80 32% used
|
||||
|
||||
SLICE 120/320 37% used
|
||||
|
||||
EFB 1/1 100% used
|
||||
|
||||
|
||||
Number of Signals: 388
|
||||
Number of Connections: 1017
|
||||
Number of Signals: 389
|
||||
Number of Connections: 1011
|
||||
|
||||
Pin Constraint Summary:
|
||||
63 out of 63 pins locked (100% locked).
|
||||
64 out of 64 pins locked (100% locked).
|
||||
|
||||
The following 2 signals are selected to use the primary clock routing resources:
|
||||
RCLK_c (driver: RCLK, clk load #: 47)
|
||||
RCLK_c (driver: RCLK, clk load #: 48)
|
||||
PHI2_c (driver: PHI2, clk load #: 20)
|
||||
|
||||
WARNING - par: Signal "PHI2_c" is selected to use Primary clock resources. However, its driver comp "PHI2" is located at "8", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
|
@ -92,18 +92,18 @@ WARNING - par: Signal "nCRAS_c" is selected to use Secondary clock res
|
|||
WARNING - par: Signal "nCCAS_c" is selected to use Secondary clock resources. However, its driver comp "nCCAS" is located at "9", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
|
||||
No signal is selected as Global Set/Reset.
|
||||
Starting Placer Phase 0.
|
||||
............
|
||||
Finished Placer Phase 0. REAL time: 0 secs
|
||||
...........
|
||||
Finished Placer Phase 0. REAL time: 2 secs
|
||||
|
||||
Starting Placer Phase 1.
|
||||
....................
|
||||
Placer score = 57011.
|
||||
Finished Placer Phase 1. REAL time: 7 secs
|
||||
Placer score = 59875.
|
||||
Finished Placer Phase 1. REAL time: 9 secs
|
||||
|
||||
Starting Placer Phase 2.
|
||||
.
|
||||
Placer score = 56576
|
||||
Finished Placer Phase 2. REAL time: 7 secs
|
||||
Placer score = 59374
|
||||
Finished Placer Phase 2. REAL time: 9 secs
|
||||
|
||||
|
||||
|
||||
|
@ -116,7 +116,7 @@ Global Clock Resources:
|
|||
DCC : 0 out of 8 (0%)
|
||||
|
||||
Global Clocks:
|
||||
PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "63 (PR5C)", clk load = 47
|
||||
PRIMARY "RCLK_c" from comp "RCLK" on CLK_PIN site "63 (PR5C)", clk load = 48
|
||||
PRIMARY "PHI2_c" from comp "PHI2" on PIO site "8 (PL3B)", clk load = 20
|
||||
SECONDARY "nCRAS_c" from comp "nCRAS" on PIO site "17 (PL6B)", clk load = 9, ce load = 0, sr load = 0
|
||||
SECONDARY "nCCAS_c" from comp "nCCAS" on PIO site "9 (PL3C)", clk load = 8, ce load = 0, sr load = 0
|
||||
|
@ -128,9 +128,9 @@ Global Clocks:
|
|||
|
||||
|
||||
I/O Usage Summary (final):
|
||||
63 + 4(JTAG) out of 80 (83.8%) PIO sites used.
|
||||
63 + 4(JTAG) out of 79 (84.8%) bonded PIO sites used.
|
||||
Number of PIO comps: 63; differential: 0.
|
||||
64 + 4(JTAG) out of 80 (85.0%) PIO sites used.
|
||||
64 + 4(JTAG) out of 79 (86.1%) bonded PIO sites used.
|
||||
Number of PIO comps: 64; differential: 0.
|
||||
Number of Vref pins used: 0.
|
||||
|
||||
I/O Bank Usage Summary:
|
||||
|
@ -139,20 +139,20 @@ I/O Bank Usage Summary:
|
|||
+----------+----------------+------------+-----------+
|
||||
| 0 | 13 / 19 ( 68%) | 3.3V | - |
|
||||
| 1 | 20 / 20 (100%) | 3.3V | - |
|
||||
| 2 | 12 / 20 ( 60%) | 3.3V | - |
|
||||
| 2 | 13 / 20 ( 65%) | 3.3V | - |
|
||||
| 3 | 18 / 20 ( 90%) | 3.3V | - |
|
||||
+----------+----------------+------------+-----------+
|
||||
|
||||
Total placer CPU time: 7 secs
|
||||
Total placer CPU time: 8 secs
|
||||
|
||||
Dumping design to file RAM2GS_LCMXO2_640HC_impl1.dir/5_1.ncd.
|
||||
|
||||
0 connections routed; 1017 unrouted.
|
||||
0 connections routed; 1011 unrouted.
|
||||
Starting router resource preassignment
|
||||
|
||||
Completed router resource preassignment. Real time: 11 secs
|
||||
Completed router resource preassignment. Real time: 13 secs
|
||||
|
||||
Start NBR router at 05:39:58 09/21/23
|
||||
Start NBR router at 02:06:09 11/18/23
|
||||
|
||||
*****************************************************************
|
||||
Info: NBR allows conflicts(one node used by more than one signal)
|
||||
|
@ -167,50 +167,41 @@ Note: NBR uses a different method to calculate timing slacks. The
|
|||
your design.
|
||||
*****************************************************************
|
||||
|
||||
Start NBR special constraint process at 05:39:58 09/21/23
|
||||
Start NBR special constraint process at 02:06:09 11/18/23
|
||||
|
||||
Start NBR section for initial routing at 05:39:58 09/21/23
|
||||
Start NBR section for initial routing at 02:06:09 11/18/23
|
||||
Level 1, iteration 1
|
||||
2(0.00%) conflicts; 816(80.24%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 6.163ns/0.000ns; real time: 11 secs
|
||||
0(0.00%) conflict; 814(80.51%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 6.075ns/0.000ns; real time: 13 secs
|
||||
Level 2, iteration 1
|
||||
0(0.00%) conflict; 815(80.14%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 5.772ns/0.000ns; real time: 11 secs
|
||||
0(0.00%) conflict; 808(79.92%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 6.252ns/0.000ns; real time: 13 secs
|
||||
Level 3, iteration 1
|
||||
0(0.00%) conflict; 815(80.14%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 5.772ns/0.000ns; real time: 11 secs
|
||||
0(0.00%) conflict; 808(79.92%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 6.252ns/0.000ns; real time: 13 secs
|
||||
Level 4, iteration 1
|
||||
8(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 5.772ns/0.000ns; real time: 12 secs
|
||||
6(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 6.245ns/0.000ns; real time: 14 secs
|
||||
|
||||
Info: Initial congestion level at 75% usage is 0
|
||||
Info: Initial congestion area at 75% usage is 0 (0.00%)
|
||||
|
||||
Start NBR section for normal routing at 05:39:59 09/21/23
|
||||
Start NBR section for normal routing at 02:06:10 11/18/23
|
||||
Level 4, iteration 1
|
||||
4(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 5.772ns/0.000ns; real time: 12 secs
|
||||
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 6.245ns/0.000ns; real time: 14 secs
|
||||
Level 4, iteration 2
|
||||
2(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 5.772ns/0.000ns; real time: 12 secs
|
||||
Level 4, iteration 3
|
||||
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 5.772ns/0.000ns; real time: 12 secs
|
||||
Level 4, iteration 4
|
||||
1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 5.772ns/0.000ns; real time: 12 secs
|
||||
Level 4, iteration 5
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 5.772ns/0.000ns; real time: 12 secs
|
||||
Estimated worst slack/total negative slack<setup>: 6.245ns/0.000ns; real time: 14 secs
|
||||
|
||||
Start NBR section for setup/hold timing optimization with effort level 3 at 05:39:59 09/21/23
|
||||
Start NBR section for setup/hold timing optimization with effort level 3 at 02:06:10 11/18/23
|
||||
|
||||
Start NBR section for re-routing at 05:39:59 09/21/23
|
||||
Start NBR section for re-routing at 02:06:10 11/18/23
|
||||
Level 4, iteration 1
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 5.772ns/0.000ns; real time: 12 secs
|
||||
Estimated worst slack/total negative slack<setup>: 6.245ns/0.000ns; real time: 14 secs
|
||||
|
||||
Start NBR section for post-routing at 05:39:59 09/21/23
|
||||
Start NBR section for post-routing at 02:06:10 11/18/23
|
||||
|
||||
End NBR router with 0 unrouted connection
|
||||
|
||||
|
@ -218,17 +209,17 @@ NBR Summary
|
|||
-----------
|
||||
Number of unrouted connections : 0 (0.00%)
|
||||
Number of connections with timing violations : 0 (0.00%)
|
||||
Estimated worst slack<setup> : 5.772ns
|
||||
Estimated worst slack<setup> : 6.245ns
|
||||
Timing score<setup> : 0
|
||||
-----------
|
||||
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
|
||||
|
||||
|
||||
|
||||
Total CPU time 12 secs
|
||||
Total REAL time: 13 secs
|
||||
Total CPU time 13 secs
|
||||
Total REAL time: 15 secs
|
||||
Completely routed.
|
||||
End of route. 1017 routed (100.00%); 0 unrouted.
|
||||
End of route. 1011 routed (100.00%); 0 unrouted.
|
||||
|
||||
Hold time timing score: 0, hold timing errors: 0
|
||||
|
||||
|
@ -242,14 +233,14 @@ All signals are completely routed.
|
|||
|
||||
PAR_SUMMARY::Run status = Completed
|
||||
PAR_SUMMARY::Number of unrouted conns = 0
|
||||
PAR_SUMMARY::Worst slack<setup/<ns>> = 5.772
|
||||
PAR_SUMMARY::Worst slack<setup/<ns>> = 6.245
|
||||
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
|
||||
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.304
|
||||
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
|
||||
PAR_SUMMARY::Number of errors = 0
|
||||
|
||||
Total CPU time to completion: 13 secs
|
||||
Total REAL time to completion: 13 secs
|
||||
Total REAL time to completion: 15 secs
|
||||
|
||||
par done!
|
||||
|
||||
|
|
|
@ -13,7 +13,7 @@ Hostname: ZANEMACWIN11
|
|||
|
||||
Implementation : impl1
|
||||
|
||||
# Written on Thu Sep 21 05:39:36 2023
|
||||
# Written on Sat Nov 18 02:05:42 2023
|
||||
|
||||
##### FILES SYNTAX CHECKED ##############################################
|
||||
Constraint File(s): "\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS.sdc"
|
||||
|
|
|
@ -24,9 +24,9 @@
|
|||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Last Process:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">JEDEC File</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000"></SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">State:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">Passed</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000"></SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Target Device:</SPAN></TD>
|
||||
|
@ -62,7 +62,7 @@
|
|||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Updated:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2023/09/21 05:40:18</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2023/11/18 02:59:48</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Location:</SPAN></TD>
|
||||
|
|
|
@ -12,7 +12,7 @@
|
|||
#OS: Windows 8 6.2
|
||||
#Hostname: ZANEMACWIN11
|
||||
|
||||
# Thu Sep 21 05:39:33 2023
|
||||
# Sat Nov 18 02:05:39 2023
|
||||
|
||||
#Implementation: impl1
|
||||
|
||||
|
@ -60,13 +60,17 @@ Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 202
|
|||
@I::"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v" (library work)
|
||||
@I::"\\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-640HC\REFB.v" (library work)
|
||||
Verilog syntax check successful!
|
||||
File \\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-LCMXO2.v changed - recompiling
|
||||
Selecting top level module RAM2GS
|
||||
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1601:7:1601:12|Synthesizing module ODDRXE in library work.
|
||||
Running optimization stage 1 on ODDRXE .......
|
||||
Finished optimization stage 1 on ODDRXE (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
|
||||
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
|
||||
Running optimization stage 1 on VHI .......
|
||||
Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 98MB)
|
||||
Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
|
||||
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
|
||||
Running optimization stage 1 on VLO .......
|
||||
Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
|
||||
Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
|
||||
@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
|
||||
Running optimization stage 1 on EFB .......
|
||||
Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
|
||||
|
@ -86,13 +90,15 @@ Running optimization stage 2 on VLO .......
|
|||
Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
|
||||
Running optimization stage 2 on VHI .......
|
||||
Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
|
||||
Running optimization stage 2 on ODDRXE .......
|
||||
Finished optimization stage 2 on ODDRXE (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
|
||||
|
||||
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB)
|
||||
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 102MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:39:33 2023
|
||||
# Sat Nov 18 02:05:40 2023
|
||||
|
||||
###########################################################]
|
||||
###########################################################[
|
||||
|
@ -119,7 +125,7 @@ At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s;
|
|||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:39:34 2023
|
||||
# Sat Nov 18 02:05:40 2023
|
||||
|
||||
###########################################################]
|
||||
|
||||
|
@ -129,12 +135,12 @@ For a summary of runtime and memory usage for all design units, please see file:
|
|||
|
||||
@END
|
||||
|
||||
At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
|
||||
At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:39:34 2023
|
||||
# Sat Nov 18 02:05:40 2023
|
||||
|
||||
###########################################################]
|
||||
###########################################################[
|
||||
|
@ -155,18 +161,17 @@ Implementation : impl1
|
|||
Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
File \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_comp.srs changed - recompiling
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:39:35 2023
|
||||
# Sat Nov 18 02:05:42 2023
|
||||
|
||||
###########################################################]
|
||||
Premap Report
|
||||
|
||||
# Thu Sep 21 05:39:35 2023
|
||||
# Sat Nov 18 02:05:42 2023
|
||||
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
|
@ -185,10 +190,10 @@ Implementation : impl1
|
|||
Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @
|
||||
|
||||
|
||||
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
|
||||
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
|
||||
|
||||
|
||||
Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 140MB)
|
||||
Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 140MB)
|
||||
|
||||
Reading constraint file: \\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS.sdc
|
||||
@L: \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1_scck.rpt
|
||||
|
@ -212,7 +217,6 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h
|
|||
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
|
||||
@N: FX493 |Applying initial value "0" on instance Ready.
|
||||
@N: FX493 |Applying initial value "0" on instance RCKE.
|
||||
@N: FX493 |Applying initial value "0" on instance LEDEN.
|
||||
@N: FX493 |Applying initial value "0" on instance n8MEGEN.
|
||||
@N: FX493 |Applying initial value "1" on instance nRCAS.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdLEDEN.
|
||||
|
@ -238,11 +242,11 @@ Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapse
|
|||
Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
|
||||
|
||||
|
||||
Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
|
||||
Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
|
||||
|
||||
@N: FX1184 |Applying syn_allowed_resources blockrams=2 on top level netlist RAM2GS
|
||||
|
||||
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
|
||||
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
|
||||
|
||||
|
||||
|
||||
|
@ -326,12 +330,10 @@ Pre-mapping successful!
|
|||
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 103MB peak: 185MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Thu Sep 21 05:39:37 2023
|
||||
# Sat Nov 18 02:05:43 2023
|
||||
|
||||
###########################################################]
|
||||
Map & Optimize Report
|
||||
|
||||
# Thu Sep 21 05:39:37 2023
|
||||
# Sat Nov 18 02:05:44 2023
|
||||
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
|
@ -350,22 +352,22 @@ Implementation : impl1
|
|||
Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @
|
||||
|
||||
|
||||
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
|
||||
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
|
||||
|
||||
@N: MF916 |Option synthesis_strategy=base is enabled.
|
||||
@N: MF248 |Running in 64-bit mode.
|
||||
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
|
||||
|
||||
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 139MB)
|
||||
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
|
||||
|
||||
|
||||
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 139MB)
|
||||
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
|
||||
|
||||
|
||||
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
|
||||
|
||||
|
||||
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB)
|
||||
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB)
|
||||
|
||||
|
||||
|
||||
|
@ -374,8 +376,8 @@ Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapse
|
|||
|
||||
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB)
|
||||
|
||||
@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":163:4:163:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0]
|
||||
@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":150:4:150:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0]
|
||||
@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":166:4:166:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0]
|
||||
@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":153:4:153:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0]
|
||||
@N: FX493 |Applying initial value "0" on instance IS[0].
|
||||
@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
|
||||
@N: FX493 |Applying initial value "0" on instance IS[1].
|
||||
|
@ -385,7 +387,7 @@ Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00
|
|||
Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 185MB peak: 185MB)
|
||||
|
||||
|
||||
Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 187MB peak: 187MB)
|
||||
Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB)
|
||||
|
||||
|
||||
Available hyper_sources - for debug and ip models
|
||||
|
@ -398,7 +400,7 @@ Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CP
|
|||
Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 187MB peak: 187MB)
|
||||
|
||||
|
||||
Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 187MB peak: 187MB)
|
||||
Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
|
||||
|
||||
|
||||
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
|
||||
|
@ -407,16 +409,16 @@ Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CP
|
|||
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
|
||||
|
||||
|
||||
Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 197MB peak: 197MB)
|
||||
Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 196MB peak: 196MB)
|
||||
|
||||
Pass CPU time Worst Slack Luts / Registers
|
||||
------------------------------------------------------------
|
||||
1 0h:00m:01s -2.98ns 201 / 106
|
||||
2 0h:00m:01s -2.98ns 217 / 106
|
||||
1 0h:00m:01s -2.98ns 202 / 106
|
||||
2 0h:00m:01s -2.98ns 215 / 106
|
||||
3 0h:00m:01s -2.76ns 215 / 106
|
||||
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":121:4:121:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 6 loads 1 time to improve timing.
|
||||
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":304:4:304:9|Replicating instance CmdValid (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.
|
||||
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":163:4:163:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 11 loads 1 time to improve timing.
|
||||
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":124:4:124:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 6 loads 1 time to improve timing.
|
||||
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":307:4:307:9|Replicating instance CmdValid (in view: work.RAM2GS(verilog)) with 4 loads 1 time to improve timing.
|
||||
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":166:4:166:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 12 loads 1 time to improve timing.
|
||||
Timing driven replication report
|
||||
Added 3 Registers via timing driven replication
|
||||
Added 1 LUTs via timing driven replication
|
||||
|
@ -430,10 +432,10 @@ Finished technology timing optimizations and critical path resynthesis (Real Tim
|
|||
|
||||
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
|
||||
|
||||
Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 198MB peak: 198MB)
|
||||
Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 197MB peak: 197MB)
|
||||
|
||||
|
||||
Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 160MB peak: 198MB)
|
||||
Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 161MB peak: 198MB)
|
||||
|
||||
Writing Analyst data base \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\RAM2GS_LCMXO2_640HC_impl1_m.srm
|
||||
|
||||
|
@ -443,14 +445,15 @@ Writing EDIF Netlist and constraint files
|
|||
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO2-640HC\impl1\RAM2GS_LCMXO2_640HC_impl1.edi
|
||||
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
|
||||
|
||||
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 203MB peak: 203MB)
|
||||
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 202MB peak: 202MB)
|
||||
|
||||
|
||||
Finished Writing Netlists (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 203MB peak: 203MB)
|
||||
Finished Writing Netlists (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 202MB peak: 203MB)
|
||||
|
||||
|
||||
Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 201MB peak: 203MB)
|
||||
|
||||
@W: MT246 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-lcmxo2.v":43:11:43:19|Blackbox ODDRXE is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
|
||||
@W: MT246 :"\\mac\icloud\repos\ram2gs\cpld\lcmxo2-640hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
|
||||
@N: MT615 |Found clock RCLK with period 16.00ns
|
||||
@N: MT615 |Found clock PHI2 with period 350.00ns
|
||||
|
@ -459,7 +462,7 @@ Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:0
|
|||
|
||||
|
||||
##### START OF TIMING REPORT #####[
|
||||
# Timing report written on Thu Sep 21 05:39:41 2023
|
||||
# Timing report written on Sat Nov 18 02:05:48 2023
|
||||
#
|
||||
|
||||
|
||||
|
@ -510,7 +513,7 @@ Starting Ending | constraint slack | constraint slack | constraint
|
|||
---------------------------------------------------------------------------------------------------------------
|
||||
System RCLK | 16.000 12.918 | No paths - | No paths - | No paths -
|
||||
RCLK System | 16.000 14.956 | No paths - | No paths - | No paths -
|
||||
RCLK RCLK | 16.000 9.040 | No paths - | No paths - | No paths -
|
||||
RCLK RCLK | 16.000 9.237 | No paths - | No paths - | No paths -
|
||||
RCLK PHI2 | 2.000 0.216 | No paths - | 1.000 -0.676 | No paths -
|
||||
RCLK nCRAS | No paths - | No paths - | 1.000 -0.784 | No paths -
|
||||
PHI2 RCLK | No paths - | No paths - | No paths - | 1.000 -1.828
|
||||
|
@ -549,30 +552,30 @@ CmdLEDEN PHI2 FD1P3AX Q CmdLEDEN 1.044
|
|||
Cmdn8MEGEN PHI2 FD1P3AX Q Cmdn8MEGEN 1.044 -1.589
|
||||
CmdUFMWrite PHI2 FD1P3AX Q CmdUFMWrite 1.044 -0.572
|
||||
CmdUFMData PHI2 FD1P3AX Q CmdUFMData 0.972 -0.500
|
||||
Bank_0io[0] PHI2 IFS1P3DX Q Bank[0] 0.972 169.081
|
||||
Bank_0io[1] PHI2 IFS1P3DX Q Bank[1] 0.972 169.081
|
||||
Bank_0io[2] PHI2 IFS1P3DX Q Bank[2] 0.972 169.081
|
||||
Bank_0io[3] PHI2 IFS1P3DX Q Bank[3] 0.972 169.081
|
||||
==========================================================================================
|
||||
|
||||
|
||||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
-----------------------------------------------------------------------------------------
|
||||
wb_adr[0] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
|
||||
wb_adr[1] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
|
||||
wb_adr[2] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
|
||||
wb_adr[3] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
|
||||
wb_adr[4] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
|
||||
wb_adr[5] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
|
||||
wb_adr[6] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
|
||||
wb_adr[7] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
|
||||
wb_dati[0] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
|
||||
wb_dati[1] PHI2 FD1P3AX SP un1_wb_rst14_i_0 0.528 -1.828
|
||||
=========================================================================================
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
--------------------------------------------------------------------------------
|
||||
wb_adr[0] PHI2 FD1P3AX SP N_126_i 0.528 -1.828
|
||||
wb_adr[1] PHI2 FD1P3AX SP N_126_i 0.528 -1.828
|
||||
wb_adr[2] PHI2 FD1P3AX SP N_126_i 0.528 -1.828
|
||||
wb_adr[3] PHI2 FD1P3AX SP N_126_i 0.528 -1.828
|
||||
wb_adr[4] PHI2 FD1P3AX SP N_126_i 0.528 -1.828
|
||||
wb_adr[5] PHI2 FD1P3AX SP N_126_i 0.528 -1.828
|
||||
wb_adr[6] PHI2 FD1P3AX SP N_126_i 0.528 -1.828
|
||||
wb_adr[7] PHI2 FD1P3AX SP N_126_i 0.528 -1.828
|
||||
wb_dati[0] PHI2 FD1P3AX SP N_126_i 0.528 -1.828
|
||||
wb_dati[1] PHI2 FD1P3AX SP N_126_i 0.528 -1.828
|
||||
================================================================================
|
||||
|
||||
|
||||
|
||||
|
@ -603,7 +606,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r -
|
|||
CmdUFMShift Net - - - - 2
|
||||
CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r -
|
||||
CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r -
|
||||
un1_wb_rst14_i_0 Net - - - - 17
|
||||
N_126_i Net - - - - 17
|
||||
wb_adr[0] FD1P3AX SP In 0.000 2.357 r -
|
||||
=========================================================================================
|
||||
|
||||
|
@ -631,7 +634,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r -
|
|||
CmdUFMShift Net - - - - 2
|
||||
CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r -
|
||||
CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r -
|
||||
un1_wb_rst14_i_0 Net - - - - 17
|
||||
N_126_i Net - - - - 17
|
||||
wb_adr[7] FD1P3AX SP In 0.000 2.357 r -
|
||||
=========================================================================================
|
||||
|
||||
|
@ -659,7 +662,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r -
|
|||
CmdUFMShift Net - - - - 2
|
||||
CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r -
|
||||
CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r -
|
||||
un1_wb_rst14_i_0 Net - - - - 17
|
||||
N_126_i Net - - - - 17
|
||||
wb_adr[6] FD1P3AX SP In 0.000 2.357 r -
|
||||
=========================================================================================
|
||||
|
||||
|
@ -687,7 +690,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r -
|
|||
CmdUFMShift Net - - - - 2
|
||||
CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r -
|
||||
CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r -
|
||||
un1_wb_rst14_i_0 Net - - - - 17
|
||||
N_126_i Net - - - - 17
|
||||
wb_adr[5] FD1P3AX SP In 0.000 2.357 r -
|
||||
=========================================================================================
|
||||
|
||||
|
@ -715,7 +718,7 @@ CmdUFMShift FD1P3AX Q Out 1.044 1.044 r -
|
|||
CmdUFMShift Net - - - - 2
|
||||
CmdValid_fast_RNI3K0H1 ORCALUT4 A In 0.000 1.044 r -
|
||||
CmdValid_fast_RNI3K0H1 ORCALUT4 Z Out 1.313 2.357 r -
|
||||
un1_wb_rst14_i_0 Net - - - - 17
|
||||
N_126_i Net - - - - 17
|
||||
wb_adr[4] FD1P3AX SP In 0.000 2.357 r -
|
||||
=========================================================================================
|
||||
|
||||
|
@ -738,13 +741,13 @@ Instance Reference Type Pin Net Time Slac
|
|||
Ready_fast RCLK FD1S3AX Q Ready_fast 1.256 -0.784
|
||||
LEDEN RCLK FD1S3AX Q LEDEN 1.148 -0.676
|
||||
n8MEGEN RCLK FD1S3AX Q n8MEGEN 1.108 -0.636
|
||||
IS[1] RCLK FD1P3AX Q IS[1] 1.204 9.040
|
||||
IS[2] RCLK FD1P3AX Q IS[2] 1.188 9.056
|
||||
IS[3] RCLK FD1P3AX Q IS[3] 1.148 9.096
|
||||
InitReady RCLK FD1S3AX Q InitReady 1.339 9.228
|
||||
FS[15] RCLK FD1S3AX Q FS[15] 1.228 9.339
|
||||
FS[16] RCLK FD1S3AX Q FS[16] 1.188 9.379
|
||||
FS[17] RCLK FD1S3AX Q FS[17] 1.188 9.379
|
||||
InitReady RCLK FD1S3AX Q InitReady 1.337 9.237
|
||||
FS[16] RCLK FD1S3AX Q FS[16] 1.204 9.371
|
||||
FS[17] RCLK FD1S3AX Q FS[17] 1.204 9.371
|
||||
FS[15] RCLK FD1S3AX Q FS[15] 1.188 9.387
|
||||
S[0] RCLK FD1S3IX Q CO0 1.244 9.873
|
||||
S[1] RCLK FD1S3IX Q S[1] 1.236 9.881
|
||||
RASr2 RCLK FD1S3AX Q RASr2 1.228 9.889
|
||||
==================================================================================
|
||||
|
||||
|
||||
|
@ -841,7 +844,35 @@ Path information for path number 3:
|
|||
|
||||
Number of logic level(s): 1
|
||||
Starting point: Ready_fast / Q
|
||||
Ending point: RowA[0] / D
|
||||
Ending point: RBA_0io[1] / D
|
||||
The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
|
||||
The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin SCLK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
---------------------------------------------------------------------------------
|
||||
Ready_fast FD1S3AX Q Out 1.256 1.256 r -
|
||||
Ready_fast Net - - - - 14
|
||||
RBAd[1] ORCALUT4 B In 0.000 1.256 r -
|
||||
RBAd[1] ORCALUT4 Z Out 0.617 1.873 r -
|
||||
RBAd_0[1] Net - - - - 1
|
||||
RBA_0io[1] OFS1P3DX D In 0.000 1.873 r -
|
||||
=================================================================================
|
||||
|
||||
|
||||
Path information for path number 4:
|
||||
Requested Period: 1.000
|
||||
- Setup time: -0.089
|
||||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
= Required time: 1.089
|
||||
|
||||
- Propagation time: 1.873
|
||||
- Clock delay at starting point: 0.000 (ideal)
|
||||
= Slack (non-critical) : -0.784
|
||||
|
||||
Number of logic level(s): 1
|
||||
Starting point: Ready_fast / Q
|
||||
Ending point: RowA[1] / D
|
||||
The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
|
||||
The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
|
||||
|
||||
|
@ -850,14 +881,14 @@ Name Type Name Dir Delay Time Fan Out(s
|
|||
---------------------------------------------------------------------------------
|
||||
Ready_fast FD1S3AX Q Out 1.256 1.256 r -
|
||||
Ready_fast Net - - - - 14
|
||||
RowAd[0] ORCALUT4 B In 0.000 1.256 r -
|
||||
RowAd[0] ORCALUT4 Z Out 0.617 1.873 r -
|
||||
RowAd_0[0] Net - - - - 1
|
||||
RowA[0] FD1S3AX D In 0.000 1.873 r -
|
||||
RowAd[1] ORCALUT4 B In 0.000 1.256 r -
|
||||
RowAd[1] ORCALUT4 Z Out 0.617 1.873 r -
|
||||
RowAd_0[1] Net - - - - 1
|
||||
RowA[1] FD1S3AX D In 0.000 1.873 r -
|
||||
=================================================================================
|
||||
|
||||
|
||||
Path information for path number 4:
|
||||
Path information for path number 5:
|
||||
Requested Period: 1.000
|
||||
- Setup time: -0.089
|
||||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
|
@ -885,34 +916,6 @@ RowA[5] FD1S3AX D In 0.000 1.873 f -
|
|||
=================================================================================
|
||||
|
||||
|
||||
Path information for path number 5:
|
||||
Requested Period: 1.000
|
||||
- Setup time: -0.089
|
||||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
= Required time: 1.089
|
||||
|
||||
- Propagation time: 1.873
|
||||
- Clock delay at starting point: 0.000 (ideal)
|
||||
= Slack (non-critical) : -0.784
|
||||
|
||||
Number of logic level(s): 1
|
||||
Starting point: Ready_fast / Q
|
||||
Ending point: RowA[8] / D
|
||||
The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
|
||||
The end point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
---------------------------------------------------------------------------------
|
||||
Ready_fast FD1S3AX Q Out 1.256 1.256 r -
|
||||
Ready_fast Net - - - - 14
|
||||
RowAd[8] ORCALUT4 B In 0.000 1.256 r -
|
||||
RowAd[8] ORCALUT4 Z Out 0.617 1.873 r -
|
||||
RowAd_0[8] Net - - - - 1
|
||||
RowA[8] FD1S3AX D In 0.000 1.873 r -
|
||||
=================================================================================
|
||||
|
||||
|
||||
|
||||
|
||||
====================================
|
||||
|
@ -937,16 +940,16 @@ FWEr nCRAS FD1S3AX Q FWEr 1.180 -1.797
|
|||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
------------------------------------------------------------------------------------------
|
||||
nRCAS_0io nCRAS OFS1P3BX D N_248_i 1.089 -2.605
|
||||
nRCS_0io nCRAS OFS1P3BX D N_247_i 1.089 -1.797
|
||||
nRWE_0io nCRAS OFS1P3BX D N_49_i 1.089 -1.797
|
||||
nRowColSel nCRAS FD1S3IX D nRowColSel_0_0_0 1.089 -1.797
|
||||
RCKEEN nCRAS FD1S3AX D RCKEEN_8 1.089 -1.725
|
||||
==========================================================================================
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
----------------------------------------------------------------------------------------
|
||||
nRCAS_0io nCRAS OFS1P3BX D N_251_i 1.089 -2.605
|
||||
nRCS_0io nCRAS OFS1P3BX D N_37_i 1.089 -1.797
|
||||
nRWE_0io nCRAS OFS1P3BX D N_252_i 1.089 -1.797
|
||||
nRowColSel nCRAS FD1S3IX D nRowColSel_0_0 1.089 -1.797
|
||||
RCKEEN nCRAS FD1S3AX D RCKEEN_8 1.089 -1.725
|
||||
========================================================================================
|
||||
|
||||
|
||||
|
||||
|
@ -980,10 +983,10 @@ CBR_fast_RNIQ31K1 ORCALUT4 Z Out 1.089 2.061 r -
|
|||
nRCAS_0_sqmuxa_1 Net - - - - 2
|
||||
nRCAS_0io_RNO_0 ORCALUT4 B In 0.000 2.061 r -
|
||||
nRCAS_0io_RNO_0 ORCALUT4 Z Out 1.017 3.077 r -
|
||||
N_248_i_sx Net - - - - 1
|
||||
nRCAS_0io_RNO ORCALUT4 D In 0.000 3.077 r -
|
||||
N_251_i_sx Net - - - - 1
|
||||
nRCAS_0io_RNO ORCALUT4 C In 0.000 3.077 r -
|
||||
nRCAS_0io_RNO ORCALUT4 Z Out 0.617 3.694 f -
|
||||
N_248_i Net - - - - 1
|
||||
N_251_i Net - - - - 1
|
||||
nRCAS_0io OFS1P3BX D In 0.000 3.694 f -
|
||||
====================================================================================
|
||||
|
||||
|
@ -1004,19 +1007,19 @@ Path information for path number 2:
|
|||
The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
|
||||
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
--------------------------------------------------------------------------------------
|
||||
CBR FD1S3AX Q Out 1.180 1.180 r -
|
||||
CBR Net - - - - 5
|
||||
RCKEEN_8_u_0_0_a2_2 ORCALUT4 A In 0.000 1.180 r -
|
||||
RCKEEN_8_u_0_0_a2_2 ORCALUT4 Z Out 1.089 2.269 f -
|
||||
N_590 Net - - - - 2
|
||||
nRCS_0io_RNO ORCALUT4 C In 0.000 2.269 f -
|
||||
nRCS_0io_RNO ORCALUT4 Z Out 0.617 2.885 r -
|
||||
N_247_i Net - - - - 1
|
||||
nRCS_0io OFS1P3BX D In 0.000 2.885 r -
|
||||
======================================================================================
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
------------------------------------------------------------------------------------
|
||||
CBR FD1S3AX Q Out 1.180 1.180 r -
|
||||
CBR Net - - - - 5
|
||||
RCKEEN_8_u_0_a2_2 ORCALUT4 A In 0.000 1.180 r -
|
||||
RCKEEN_8_u_0_a2_2 ORCALUT4 Z Out 1.089 2.269 f -
|
||||
N_141 Net - - - - 2
|
||||
nRCS_0io_RNO ORCALUT4 A In 0.000 2.269 f -
|
||||
nRCS_0io_RNO ORCALUT4 Z Out 0.617 2.885 r -
|
||||
N_37_i Net - - - - 1
|
||||
nRCS_0io OFS1P3BX D In 0.000 2.885 r -
|
||||
====================================================================================
|
||||
|
||||
|
||||
Path information for path number 3:
|
||||
|
@ -1035,19 +1038,19 @@ Path information for path number 3:
|
|||
The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
|
||||
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
---------------------------------------------------------------------------------
|
||||
FWEr FD1S3AX Q Out 1.180 1.180 r -
|
||||
FWEr Net - - - - 5
|
||||
nRCAS_r_i_0_a2 ORCALUT4 B In 0.000 1.180 r -
|
||||
nRCAS_r_i_0_a2 ORCALUT4 Z Out 1.089 2.269 f -
|
||||
N_248_i_1_0 Net - - - - 2
|
||||
nRCAS_0io_RNO ORCALUT4 C In 0.000 2.269 f -
|
||||
nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.885 r -
|
||||
N_248_i Net - - - - 1
|
||||
nRCAS_0io OFS1P3BX D In 0.000 2.885 r -
|
||||
=================================================================================
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
----------------------------------------------------------------------------------
|
||||
FWEr FD1S3AX Q Out 1.180 1.180 r -
|
||||
FWEr Net - - - - 5
|
||||
nRCS_9_u_i_a2_0 ORCALUT4 B In 0.000 1.180 r -
|
||||
nRCS_9_u_i_a2_0 ORCALUT4 Z Out 1.089 2.269 f -
|
||||
N_251_i_1 Net - - - - 2
|
||||
nRCAS_0io_RNO ORCALUT4 A In 0.000 2.269 f -
|
||||
nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.885 r -
|
||||
N_251_i Net - - - - 1
|
||||
nRCAS_0io OFS1P3BX D In 0.000 2.885 r -
|
||||
==================================================================================
|
||||
|
||||
|
||||
Path information for path number 4:
|
||||
|
@ -1066,19 +1069,19 @@ Path information for path number 4:
|
|||
The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
|
||||
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin SCLK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
--------------------------------------------------------------------------------------
|
||||
CBR FD1S3AX Q Out 1.180 1.180 r -
|
||||
CBR Net - - - - 5
|
||||
RCKEEN_8_u_0_0_a2_2 ORCALUT4 A In 0.000 1.180 r -
|
||||
RCKEEN_8_u_0_0_a2_2 ORCALUT4 Z Out 1.089 2.269 f -
|
||||
N_590 Net - - - - 2
|
||||
nRWE_0io_RNO ORCALUT4 B In 0.000 2.269 f -
|
||||
nRWE_0io_RNO ORCALUT4 Z Out 0.617 2.885 r -
|
||||
N_49_i Net - - - - 1
|
||||
nRWE_0io OFS1P3BX D In 0.000 2.885 r -
|
||||
======================================================================================
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
------------------------------------------------------------------------------------
|
||||
CBR FD1S3AX Q Out 1.180 1.180 r -
|
||||
CBR Net - - - - 5
|
||||
RCKEEN_8_u_0_a2_2 ORCALUT4 A In 0.000 1.180 r -
|
||||
RCKEEN_8_u_0_a2_2 ORCALUT4 Z Out 1.089 2.269 f -
|
||||
N_141 Net - - - - 2
|
||||
nRWE_0io_RNO ORCALUT4 B In 0.000 2.269 f -
|
||||
nRWE_0io_RNO ORCALUT4 Z Out 0.617 2.885 r -
|
||||
N_252_i Net - - - - 1
|
||||
nRWE_0io OFS1P3BX D In 0.000 2.885 r -
|
||||
====================================================================================
|
||||
|
||||
|
||||
Path information for path number 5:
|
||||
|
@ -1102,12 +1105,12 @@ Name Type Name Dir Delay Time Fan
|
|||
--------------------------------------------------------------------------------------
|
||||
FWEr FD1S3AX Q Out 1.180 1.180 r -
|
||||
FWEr Net - - - - 5
|
||||
nRowColSel_0_0_0_a2 ORCALUT4 B In 0.000 1.180 r -
|
||||
nRowColSel_0_0_0_a2 ORCALUT4 Z Out 1.089 2.269 r -
|
||||
N_248_i_1_1 Net - - - - 2
|
||||
nRowColSel_0_0_a2_1 ORCALUT4 B In 0.000 1.180 r -
|
||||
nRowColSel_0_0_a2_1 ORCALUT4 Z Out 1.089 2.269 r -
|
||||
N_251_i_1_0 Net - - - - 2
|
||||
nRCAS_0io_RNO ORCALUT4 B In 0.000 2.269 r -
|
||||
nRCAS_0io_RNO ORCALUT4 Z Out 0.617 2.885 f -
|
||||
N_248_i Net - - - - 1
|
||||
N_251_i Net - - - - 1
|
||||
nRCAS_0io OFS1P3BX D In 0.000 2.885 f -
|
||||
======================================================================================
|
||||
|
||||
|
@ -1136,14 +1139,14 @@ ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000
|
|||
Ending Points with Worst Slack
|
||||
******************************
|
||||
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
-----------------------------------------------------------------------------------
|
||||
LEDEN System FD1S3AX D LEDENe_0 16.089 12.918
|
||||
n8MEGEN System FD1S3AX D n8MEGENe_0 16.089 12.918
|
||||
wb_cyc_stb System FD1P3IX SP N_178 15.528 14.912
|
||||
===================================================================================
|
||||
Starting Required
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
--------------------------------------------------------------------------------------------------
|
||||
LEDEN System FD1S3AX D LEDENe_0 16.089 12.918
|
||||
n8MEGEN System FD1S3AX D n8MEGENe_0 16.089 12.918
|
||||
wb_cyc_stb System FD1P3IX SP wb_cyc_stb_2_sqmuxa_i_0_0 15.528 14.912
|
||||
==================================================================================================
|
||||
|
||||
|
||||
|
||||
|
@ -1181,8 +1184,8 @@ ufmefb.EFBInst_0_RNISI191 ORCALUT4 Z Out 0.449 1.466 r
|
|||
N_4 Net - - - - 1
|
||||
CmdValid_RNIOOBE2 ORCALUT4 C In 0.000 1.466 r -
|
||||
CmdValid_RNIOOBE2 ORCALUT4 Z Out 1.089 2.554 r -
|
||||
CmdValid_RNIOOBE2 Net - - - - 2
|
||||
LEDENe ORCALUT4 B In 0.000 2.554 r -
|
||||
un1_FS_38_i Net - - - - 2
|
||||
LEDENe ORCALUT4 C In 0.000 2.554 r -
|
||||
LEDENe ORCALUT4 Z Out 0.617 3.171 r -
|
||||
LEDENe_0 Net - - - - 1
|
||||
LEDEN FD1S3AX D In 0.000 3.171 r -
|
||||
|
@ -1205,7 +1208,7 @@ Part: lcmxo2_640hc-4
|
|||
|
||||
Register bits: 109 of 640 (17%)
|
||||
PIC Latch: 0
|
||||
I/O cells: 63
|
||||
I/O cells: 64
|
||||
|
||||
|
||||
Details:
|
||||
|
@ -1220,12 +1223,13 @@ GSR: 1
|
|||
IB: 25
|
||||
IFS1P3DX: 9
|
||||
INV: 7
|
||||
OB: 30
|
||||
OB: 31
|
||||
ODDRXE: 1
|
||||
OFS1P3BX: 4
|
||||
OFS1P3DX: 11
|
||||
OFS1P3JX: 1
|
||||
ORCALUT4: 213
|
||||
PFUMX: 1
|
||||
ORCALUT4: 212
|
||||
PFUMX: 2
|
||||
PUR: 1
|
||||
VHI: 2
|
||||
VLO: 2
|
||||
|
@ -1234,7 +1238,7 @@ Mapper successful!
|
|||
At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 78MB peak: 203MB)
|
||||
|
||||
Process took 0h:00m:04s realtime, 0h:00m:04s cputime
|
||||
# Thu Sep 21 05:39:42 2023
|
||||
# Sat Nov 18 02:05:48 2023
|
||||
|
||||
###########################################################]
|
||||
|
||||
|
|
|
@ -22,7 +22,7 @@ Setup and Hold Report
|
|||
|
||||
--------------------------------------------------------------------------------
|
||||
<A name="Map_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454</big></U></B>
|
||||
Thu Sep 21 05:39:45 2023
|
||||
Sat Nov 18 02:05:54 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
|
@ -50,8 +50,8 @@ Report: 150.150MHz is the maximum frequency for this preference.
|
|||
<LI><A href='#map_twr_pref_0_2' Target='right'>FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
|
||||
Report: 150.150MHz is the maximum frequency for this preference.
|
||||
|
||||
<LI><A href='#map_twr_pref_0_3' Target='right'>FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)</A></LI> 878 items scored, 0 timing errors detected.
|
||||
Report: 100.492MHz is the maximum frequency for this preference.
|
||||
<LI><A href='#map_twr_pref_0_3' Target='right'>FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)</A></LI> 891 items scored, 0 timing errors detected.
|
||||
Report: 95.383MHz is the maximum frequency for this preference.
|
||||
|
||||
BLOCK ASYNCPATHS
|
||||
BLOCK RESETPATHS
|
||||
|
@ -69,28 +69,28 @@ Passed: The following path meets requirements by 163.025ns (weighted slack = 326
|
|||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q Bank_0io[0] (from PHI2_c +)
|
||||
Source: FF Q Bank_0io[1] (from PHI2_c +)
|
||||
Destination: FF Data in CmdEnable (to PHI2_c -)
|
||||
|
||||
Delay: 9.223ns (33.1% logic, 66.9% route), 6 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
9.223ns physical path delay Din[0]_MGIOL to SLICE_17 meets
|
||||
9.223ns physical path delay Din[1]_MGIOL to SLICE_17 meets
|
||||
172.414ns delay constraint less
|
||||
0.166ns DIN_SET requirement (totaling 172.248ns) by 163.025ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path Din[0]_MGIOL to SLICE_17:
|
||||
Data path Din[1]_MGIOL to SLICE_17:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
C2INP_DEL --- 0.577 *[0]_MGIOL.CLK to *n[0]_MGIOL.IN Din[0]_MGIOL (from PHI2_c)
|
||||
ROUTE 1 e 1.234 *n[0]_MGIOL.IN to SLICE_93.A0 Bank[0]
|
||||
CTOF_DEL --- 0.495 SLICE_93.A0 to SLICE_93.F0 SLICE_93
|
||||
ROUTE 1 e 1.234 SLICE_93.F0 to SLICE_84.C0 un1_CmdEnable20_0_0_o3_10
|
||||
CTOF_DEL --- 0.495 SLICE_84.C0 to SLICE_84.F0 SLICE_84
|
||||
ROUTE 6 e 1.234 SLICE_84.F0 to SLICE_11.C1 un1_CmdEnable20_0_0_o3
|
||||
C2INP_DEL --- 0.577 *[1]_MGIOL.CLK to *n[1]_MGIOL.IN Din[1]_MGIOL (from PHI2_c)
|
||||
ROUTE 1 e 1.234 *n[1]_MGIOL.IN to SLICE_90.A0 Bank[1]
|
||||
CTOF_DEL --- 0.495 SLICE_90.A0 to SLICE_90.F0 SLICE_90
|
||||
ROUTE 1 e 1.234 SLICE_90.F0 to SLICE_80.C0 un1_CmdEnable20_0_0_o2_10
|
||||
CTOF_DEL --- 0.495 SLICE_80.C0 to SLICE_80.F0 SLICE_80
|
||||
ROUTE 6 e 1.234 SLICE_80.F0 to SLICE_11.C1 N_367
|
||||
CTOF_DEL --- 0.495 SLICE_11.C1 to SLICE_11.F1 SLICE_11
|
||||
ROUTE 3 e 1.234 SLICE_11.F1 to SLICE_33.B0 CmdEnable16
|
||||
CTOF_DEL --- 0.495 SLICE_33.B0 to SLICE_33.F0 SLICE_33
|
||||
|
@ -141,48 +141,46 @@ Report: 150.150MHz is the maximum frequency for this preference.
|
|||
|
||||
================================================================================
|
||||
<A name="map_twr_pref_0_3"></A>Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
|
||||
878 items scored, 0 timing errors detected.
|
||||
891 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 6.049ns
|
||||
Passed: The following path meets requirements by 5.516ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q IS[1] (from RCLK_c +)
|
||||
Destination: FF Data in nRCAS_0io (to RCLK_c +)
|
||||
Source: FF Q S[0] (from RCLK_c +)
|
||||
Destination: FF Data in nRWE_0io (to RCLK_c +)
|
||||
|
||||
Delay: 9.798ns (34.9% logic, 65.1% route), 7 logic levels.
|
||||
Delay: 10.331ns (28.3% logic, 71.7% route), 6 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
9.798ns physical path delay SLICE_27 to nRCAS_MGIOL meets
|
||||
10.331ns physical path delay SLICE_16 to nRWE_MGIOL meets
|
||||
16.000ns delay constraint less
|
||||
0.153ns DO_SET requirement (totaling 15.847ns) by 6.049ns
|
||||
0.153ns DO_SET requirement (totaling 15.847ns) by 5.516ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path SLICE_27 to nRCAS_MGIOL:
|
||||
Data path SLICE_16 to nRWE_MGIOL:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.452 SLICE_27.CLK to SLICE_27.Q0 SLICE_27 (from RCLK_c)
|
||||
ROUTE 7 e 1.234 SLICE_27.Q0 to SLICE_74.A1 IS[1]
|
||||
CTOF_DEL --- 0.495 SLICE_74.A1 to SLICE_74.F1 SLICE_74
|
||||
ROUTE 2 e 0.480 SLICE_74.F1 to SLICE_74.B0 un1_nRCAS_6_sqmuxa_i_0_0_o2_0
|
||||
CTOF_DEL --- 0.495 SLICE_74.B0 to SLICE_74.F0 SLICE_74
|
||||
ROUTE 2 e 1.234 SLICE_74.F0 to SLICE_61.B1 N_408
|
||||
CTOF_DEL --- 0.495 SLICE_61.B1 to SLICE_61.F1 SLICE_61
|
||||
ROUTE 1 e 0.480 SLICE_61.F1 to SLICE_61.A0 un1_nRCAS_6_sqmuxa_i_0_0
|
||||
CTOF_DEL --- 0.495 SLICE_61.A0 to SLICE_61.F0 SLICE_61
|
||||
ROUTE 1 e 1.234 SLICE_61.F0 to SLICE_94.D0 nRCAS_r_i_0_o2_0_0
|
||||
CTOF_DEL --- 0.495 SLICE_94.D0 to SLICE_94.F0 SLICE_94
|
||||
ROUTE 1 e 0.480 SLICE_94.F0 to SLICE_94.A1 N_248_i_1
|
||||
CTOF_DEL --- 0.495 SLICE_94.A1 to SLICE_94.F1 SLICE_94
|
||||
ROUTE 1 e 1.234 SLICE_94.F1 to *AS_MGIOL.OPOS N_248_i (to RCLK_c)
|
||||
REG_DEL --- 0.452 SLICE_16.CLK to SLICE_16.Q0 SLICE_16 (from RCLK_c)
|
||||
ROUTE 12 e 1.234 SLICE_16.Q0 to SLICE_62.D1 CO0
|
||||
CTOF_DEL --- 0.495 SLICE_62.D1 to SLICE_62.F1 SLICE_62
|
||||
ROUTE 6 e 1.234 SLICE_62.F1 to SLICE_79.A1 IS_0_sqmuxa_0_o2
|
||||
CTOF_DEL --- 0.495 SLICE_79.A1 to SLICE_79.F1 SLICE_79
|
||||
ROUTE 2 e 1.234 SLICE_79.F1 to SLICE_28.D1 IS_0_sqmuxa_0_o3
|
||||
CTOF_DEL --- 0.495 SLICE_28.D1 to SLICE_28.F1 SLICE_28
|
||||
ROUTE 1 e 1.234 SLICE_28.F1 to SLICE_68.D1 nRWE_s_i_a2_1_0
|
||||
CTOF_DEL --- 0.495 SLICE_68.D1 to SLICE_68.F1 SLICE_68
|
||||
ROUTE 1 e 1.234 SLICE_68.F1 to SLICE_75.D0 nRWE_s_i_tz_0
|
||||
CTOF_DEL --- 0.495 SLICE_75.D0 to SLICE_75.F0 SLICE_75
|
||||
ROUTE 1 e 1.234 SLICE_75.F0 to *WE_MGIOL.OPOS N_252_i (to RCLK_c)
|
||||
--------
|
||||
9.798 (34.9% logic, 65.1% route), 7 logic levels.
|
||||
10.331 (28.3% logic, 71.7% route), 6 logic levels.
|
||||
|
||||
Report: 100.492MHz is the maximum frequency for this preference.
|
||||
Report: 95.383MHz is the maximum frequency for this preference.
|
||||
|
||||
<A name="mtw1_set_rs"></A><B><U><big>Report Summary</big></U></B>
|
||||
--------------
|
||||
|
@ -196,7 +194,7 @@ FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
|
|||
| | |
|
||||
FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
|
||||
| | |
|
||||
FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 100.492 MHz| 7
|
||||
FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 95.383 MHz| 6
|
||||
| | |
|
||||
----------------------------------------------------------------------------
|
||||
|
||||
|
@ -221,7 +219,7 @@ Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11
|
|||
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
|
||||
No transfer within this clock domain is found
|
||||
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 48
|
||||
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
|
||||
|
||||
Data transfers from:
|
||||
|
@ -251,11 +249,11 @@ Clock Domain: PHI2_c Source: PHI2.PAD Loads: 21
|
|||
Timing errors: 0 Score: 0
|
||||
Cumulative negative slack: 0
|
||||
|
||||
Constraints cover 1025 paths, 4 nets, and 741 connections (72.86% coverage)
|
||||
Constraints cover 1038 paths, 4 nets, and 732 connections (72.40% coverage)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
<A name="Map_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454</big></U></B>
|
||||
Thu Sep 21 05:39:45 2023
|
||||
Sat Nov 18 02:05:54 2023
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
|
@ -280,7 +278,7 @@ Report level: verbose report, limited to 1 item per preference
|
|||
|
||||
<LI><A href='#map_twr_pref_1_2' Target='right'>FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
|
||||
|
||||
<LI><A href='#map_twr_pref_1_3' Target='right'>FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)</A></LI> 878 items scored, 0 timing errors detected.
|
||||
<LI><A href='#map_twr_pref_1_3' Target='right'>FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)</A></LI> 891 items scored, 0 timing errors detected.
|
||||
|
||||
BLOCK ASYNCPATHS
|
||||
BLOCK RESETPATHS
|
||||
|
@ -336,7 +334,7 @@ ROUTE 1 e 0.001 SLICE_10.F0 to SLICE_10.DI0 ADSubmitted_r_0_0 (to
|
|||
|
||||
================================================================================
|
||||
<A name="map_twr_pref_1_3"></A>Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
|
||||
878 items scored, 0 timing errors detected.
|
||||
891 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
@ -402,7 +400,7 @@ Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 11
|
|||
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
|
||||
No transfer within this clock domain is found
|
||||
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 47
|
||||
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 48
|
||||
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
|
||||
|
||||
Data transfers from:
|
||||
|
@ -432,7 +430,7 @@ Clock Domain: PHI2_c Source: PHI2.PAD Loads: 21
|
|||
Timing errors: 0 Score: 0
|
||||
Cumulative negative slack: 0
|
||||
|
||||
Constraints cover 1025 paths, 4 nets, and 741 connections (72.86% coverage)
|
||||
Constraints cover 1038 paths, 4 nets, and 732 connections (72.40% coverage)
|
||||
|
||||
|
||||
|
||||
|
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
@ -2,13 +2,15 @@
|
|||
Starting: parse design source files
|
||||
(VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v'
|
||||
(VERI-1482) Analyzing Verilog file '//Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v'
|
||||
WARNING - //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v(23,47-23,52) (VERI-1875) identifier 'Ready' is used before its declaration
|
||||
(VERI-1482) Analyzing Verilog file '//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/REFB.v'
|
||||
INFO - //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v(1,8-1,14) (VERI-1018) compiling module 'RAM2GS'
|
||||
INFO - //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v(1,1-615,10) (VERI-9000) elaborating module 'RAM2GS'
|
||||
INFO - //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v(1,1-618,10) (VERI-9000) elaborating module 'RAM2GS'
|
||||
INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1601,1-1606,10) (VERI-9000) elaborating module 'ODDRXE_uniq_1'
|
||||
INFO - //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/REFB.v(8,1-113,10) (VERI-9000) elaborating module 'REFB_uniq_1'
|
||||
INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_1'
|
||||
INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_1'
|
||||
INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1800,1-1872,10) (VERI-9000) elaborating module 'EFB_uniq_1'
|
||||
Done: design load finished with (0) errors, and (0) warnings
|
||||
Done: design load finished with (0) errors, and (1) warnings
|
||||
|
||||
</PRE></BODY></HTML>
|
|
@ -29,7 +29,7 @@ Performance Hardware Data Status: Final Version 34.4.
|
|||
// Package: TQFP100
|
||||
// ncd File: ram2gs_lcmxo2_640hc_impl1.ncd
|
||||
// Version: Diamond (64-bit) 3.12.1.454
|
||||
// Written on Thu Sep 21 05:40:03 2023
|
||||
// Written on Sat Nov 18 02:06:14 2023
|
||||
// M: Minimum Performance Grade
|
||||
// iotiming RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
|
||||
|
||||
|
@ -41,94 +41,95 @@ Worst Case Results across Performance Grades (M, 6, 5, 4):
|
|||
|
||||
Port Clock Edge Setup Performance_Grade Hold Performance_Grade
|
||||
----------------------------------------------------------------------
|
||||
CROW[0] nCRAS F 2.429 4 -0.163 M
|
||||
CROW[1] nCRAS F 1.927 4 -0.005 M
|
||||
Din[0] PHI2 F 5.424 4 3.636 4
|
||||
Din[0] nCCAS F 1.913 4 -0.130 M
|
||||
Din[1] PHI2 F 5.162 4 3.516 4
|
||||
Din[1] nCCAS F 2.007 4 -0.156 M
|
||||
Din[2] PHI2 F 5.078 4 3.516 4
|
||||
Din[2] nCCAS F 0.876 4 0.346 4
|
||||
Din[3] PHI2 F 6.152 4 3.516 4
|
||||
Din[3] nCCAS F 0.245 4 0.869 4
|
||||
Din[4] PHI2 F 5.240 4 3.516 4
|
||||
Din[4] nCCAS F 0.714 4 0.460 4
|
||||
Din[5] PHI2 F 6.035 4 3.516 4
|
||||
Din[5] nCCAS F 0.751 4 0.419 4
|
||||
Din[6] PHI2 F 4.496 4 3.636 4
|
||||
Din[6] nCCAS F 1.518 4 -0.020 M
|
||||
Din[7] PHI2 F 4.936 4 3.636 4
|
||||
Din[7] nCCAS F 1.852 4 -0.081 M
|
||||
MAin[0] PHI2 F 5.207 4 0.531 4
|
||||
MAin[0] nCRAS F 1.658 4 0.036 M
|
||||
MAin[1] PHI2 F 3.450 4 0.460 4
|
||||
MAin[1] nCRAS F 2.014 4 -0.043 M
|
||||
MAin[2] PHI2 F 7.941 4 -0.604 M
|
||||
MAin[2] nCRAS F 1.001 4 0.498 4
|
||||
MAin[3] PHI2 F 8.770 4 -0.865 M
|
||||
MAin[3] nCRAS F 2.190 4 -0.151 M
|
||||
MAin[4] PHI2 F 9.575 4 -1.072 M
|
||||
MAin[4] nCRAS F 1.331 4 0.186 4
|
||||
MAin[5] PHI2 F 9.093 4 -0.925 M
|
||||
MAin[5] nCRAS F 1.329 4 0.186 4
|
||||
MAin[6] PHI2 F 9.450 4 -1.036 M
|
||||
MAin[6] nCRAS F 1.323 4 0.191 4
|
||||
MAin[7] PHI2 F 8.247 4 -0.706 M
|
||||
MAin[7] nCRAS F 1.258 4 0.267 4
|
||||
MAin[8] nCRAS F 0.994 4 0.504 4
|
||||
MAin[9] nCRAS F 0.614 4 0.830 4
|
||||
CROW[0] nCRAS F 2.058 4 -0.092 M
|
||||
CROW[1] nCRAS F 2.269 4 -0.117 M
|
||||
Din[0] PHI2 F 7.415 4 3.636 4
|
||||
Din[0] nCCAS F 2.760 4 -0.330 M
|
||||
Din[1] PHI2 F 6.384 4 3.516 4
|
||||
Din[1] nCCAS F 1.112 4 0.128 4
|
||||
Din[2] PHI2 F 6.717 4 3.516 4
|
||||
Din[2] nCCAS F 0.113 4 0.982 4
|
||||
Din[3] PHI2 F 5.806 4 3.516 4
|
||||
Din[3] nCCAS F 1.105 4 0.134 4
|
||||
Din[4] PHI2 F 6.853 4 3.516 4
|
||||
Din[4] nCCAS F 1.538 4 -0.010 M
|
||||
Din[5] PHI2 F 7.478 4 3.516 4
|
||||
Din[5] nCCAS F 0.714 4 0.460 4
|
||||
Din[6] PHI2 F 5.667 4 3.636 4
|
||||
Din[6] nCCAS F 1.504 4 -0.015 M
|
||||
Din[7] PHI2 F 5.567 4 3.636 4
|
||||
Din[7] nCCAS F 1.063 4 0.194 4
|
||||
MAin[0] PHI2 F 4.483 4 0.742 4
|
||||
MAin[0] nCRAS F 1.204 4 0.334 4
|
||||
MAin[1] PHI2 F 4.440 4 0.520 4
|
||||
MAin[1] nCRAS F 1.245 4 0.313 4
|
||||
MAin[2] PHI2 F 9.497 4 -0.729 M
|
||||
MAin[2] nCRAS F 0.758 4 0.714 4
|
||||
MAin[3] PHI2 F 9.534 4 -0.752 M
|
||||
MAin[3] nCRAS F 0.454 4 0.874 4
|
||||
MAin[4] PHI2 F 7.882 4 -0.326 M
|
||||
MAin[4] nCRAS F 0.832 4 0.632 4
|
||||
MAin[5] PHI2 F 10.136 4 -0.894 M
|
||||
MAin[5] nCRAS F 0.830 4 0.632 4
|
||||
MAin[6] PHI2 F 8.759 4 -0.555 M
|
||||
MAin[6] nCRAS F 1.259 4 0.268 4
|
||||
MAin[7] PHI2 F 8.430 4 -0.434 M
|
||||
MAin[7] nCRAS F 0.881 4 0.510 4
|
||||
MAin[8] nCRAS F 1.066 4 0.422 4
|
||||
MAin[9] nCRAS F 0.723 4 0.746 4
|
||||
PHI2 RCLK R -0.005 M 2.116 4
|
||||
nCCAS RCLK R 3.191 4 -0.531 M
|
||||
nCCAS nCRAS F 3.195 4 -0.341 M
|
||||
nCRAS RCLK R 2.797 4 -0.402 M
|
||||
nFWE PHI2 F 8.238 4 -0.666 M
|
||||
nFWE nCRAS F 1.140 4 0.400 4
|
||||
nCCAS RCLK R 3.614 4 -0.637 M
|
||||
nCCAS nCRAS F 3.629 4 -0.447 M
|
||||
nCRAS RCLK R 3.040 4 -0.485 M
|
||||
nFWE PHI2 F 8.830 4 -0.567 M
|
||||
nFWE nCRAS F 0.454 4 0.874 4
|
||||
|
||||
|
||||
// Clock to Output Delay
|
||||
|
||||
Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
|
||||
Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
|
||||
------------------------------------------------------------------------
|
||||
LED RCLK R 10.962 4 3.218 M
|
||||
LED nCRAS F 10.815 4 3.159 M
|
||||
RA[0] RCLK R 10.143 4 3.128 M
|
||||
RA[0] nCRAS F 11.178 4 3.358 M
|
||||
RA[10] RCLK R 7.578 4 2.578 M
|
||||
RA[11] PHI2 R 9.098 4 3.021 M
|
||||
RA[1] RCLK R 10.676 4 3.248 M
|
||||
RA[1] nCRAS F 11.215 4 3.370 M
|
||||
RA[2] RCLK R 11.199 4 3.402 M
|
||||
RA[2] nCRAS F 11.518 4 3.451 M
|
||||
RA[3] RCLK R 10.446 4 3.209 M
|
||||
RA[3] nCRAS F 11.264 4 3.364 M
|
||||
RA[4] RCLK R 10.446 4 3.209 M
|
||||
RA[4] nCRAS F 11.484 4 3.438 M
|
||||
RA[5] RCLK R 11.199 4 3.402 M
|
||||
RA[5] nCRAS F 11.264 4 3.364 M
|
||||
RA[6] RCLK R 11.424 4 3.444 M
|
||||
RA[6] nCRAS F 11.388 4 3.388 M
|
||||
RA[7] RCLK R 11.112 4 3.370 M
|
||||
RA[7] nCRAS F 11.608 4 3.487 M
|
||||
RA[8] RCLK R 10.916 4 3.308 M
|
||||
RA[8] nCRAS F 11.380 4 3.415 M
|
||||
RA[9] RCLK R 11.115 4 3.362 M
|
||||
RA[9] nCRAS F 11.201 4 3.380 M
|
||||
RBA[0] nCRAS F 8.645 4 2.828 M
|
||||
RBA[1] nCRAS F 8.645 4 2.828 M
|
||||
RCKE RCLK R 8.593 4 2.793 M
|
||||
RDQMH RCLK R 10.909 4 3.327 M
|
||||
RDQML RCLK R 10.348 4 3.207 M
|
||||
RD[0] nCCAS F 8.761 4 2.984 M
|
||||
RD[1] nCCAS F 8.761 4 2.984 M
|
||||
RD[2] nCCAS F 8.761 4 2.984 M
|
||||
RD[3] nCCAS F 8.761 4 2.984 M
|
||||
RD[4] nCCAS F 8.761 4 2.984 M
|
||||
RD[5] nCCAS F 8.761 4 2.984 M
|
||||
RD[6] nCCAS F 8.761 4 2.984 M
|
||||
RD[7] nCCAS F 8.761 4 2.984 M
|
||||
nRCAS RCLK R 7.578 4 2.578 M
|
||||
nRCS RCLK R 7.578 4 2.578 M
|
||||
nRRAS RCLK R 7.578 4 2.578 M
|
||||
nRWE RCLK R 7.558 4 2.585 M
|
||||
LED RCLK R 11.284 4 2.893 M
|
||||
LED nCRAS F 11.111 4 3.244 M
|
||||
RA[0] RCLK R 10.888 4 3.313 M
|
||||
RA[0] nCRAS F 11.968 4 3.554 M
|
||||
RA[10] RCLK R 7.578 4 2.578 M
|
||||
RA[11] PHI2 R 9.098 4 3.021 M
|
||||
RA[1] RCLK R 11.272 4 3.408 M
|
||||
RA[1] nCRAS F 11.484 4 3.438 M
|
||||
RA[2] RCLK R 11.749 4 3.528 M
|
||||
RA[2] nCRAS F 11.267 4 3.385 M
|
||||
RA[3] RCLK R 11.291 4 3.431 M
|
||||
RA[3] nCRAS F 11.596 4 3.449 M
|
||||
RA[4] RCLK R 10.696 4 3.276 M
|
||||
RA[4] nCRAS F 11.720 4 3.503 M
|
||||
RA[5] RCLK R 11.228 4 3.401 M
|
||||
RA[5] nCRAS F 11.364 4 3.427 M
|
||||
RA[6] RCLK R 10.132 4 3.112 M
|
||||
RA[6] nCRAS F 10.958 4 3.284 M
|
||||
RA[7] RCLK R 11.404 4 3.446 M
|
||||
RA[7] nCRAS F 11.918 4 3.561 M
|
||||
RA[8] RCLK R 10.488 4 3.236 M
|
||||
RA[8] nCRAS F 11.512 4 3.463 M
|
||||
RA[9] RCLK R 10.941 4 3.329 M
|
||||
RA[9] nCRAS F 11.074 4 3.356 M
|
||||
RBA[0] nCRAS F 8.645 4 2.828 M
|
||||
RBA[1] nCRAS F 8.625 4 2.835 M
|
||||
RCKE RCLK R 9.454 4 3.006 M
|
||||
RCLKout RCLK R 6.857 4 1.980 M
|
||||
RDQMH RCLK R 9.846 4 3.033 M
|
||||
RDQML RCLK R 9.741 4 3.008 M
|
||||
RD[0] nCCAS F 8.761 4 2.984 M
|
||||
RD[1] nCCAS F 8.761 4 2.984 M
|
||||
RD[2] nCCAS F 8.761 4 2.984 M
|
||||
RD[3] nCCAS F 8.761 4 2.984 M
|
||||
RD[4] nCCAS F 8.761 4 2.984 M
|
||||
RD[5] nCCAS F 8.761 4 2.984 M
|
||||
RD[6] nCCAS F 8.761 4 2.984 M
|
||||
RD[7] nCCAS F 8.761 4 2.984 M
|
||||
nRCAS RCLK R 7.578 4 2.578 M
|
||||
nRCS RCLK R 7.578 4 2.578 M
|
||||
nRRAS RCLK R 7.578 4 2.578 M
|
||||
nRWE RCLK R 7.558 4 2.585 M
|
||||
WARNING: you must also run trce with hold speed: 4
|
||||
WARNING: you must also run trce with setup speed: M
|
||||
|
|
|
@ -1,3 +1,3 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<userSetting name="//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml" version="Diamond (64-bit) 3.12.1.454" date="Thu Sep 21 05:40:50 2023" vendor="Lattice Semiconductor Corporation" >
|
||||
<userSetting name="//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml" version="Diamond (64-bit) 3.12.1.454" date="Sun Nov 19 19:55:57 2023" vendor="Lattice Semiconductor Corporation" >
|
||||
</userSetting>
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
<ReportView version="2.0">
|
||||
<Implement name="impl1">
|
||||
<ToolReport id="tooldec" path="" status="0"/>
|
||||
<ToolReport id="toolhle_genhierarchy" path="Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html" status="1"/>
|
||||
<ToolReport id="toolhle_genhierarchy" path="//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html" status="1"/>
|
||||
<ToolReport id="toolpio" path="" status="2"/>
|
||||
<ToolReport id="toolsso" path="" status="2"/>
|
||||
</Implement>
|
||||
|
|
|
@ -0,0 +1,70 @@
|
|||
<HTML>
|
||||
<HEAD><TITLE>Lattice TCL Log</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="pn231119195558"></A><B><U><big>pn231119195558</big></U></B>
|
||||
#Start recording tcl command: 11/18/2023 02:19:05
|
||||
#Project Location: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO256C; Project name: RAM2GS_LCMXO256C
|
||||
prj_project open "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO256C/RAM2GS_LCMXO256C.ldf"
|
||||
prj_run Export -impl impl1
|
||||
#Stop recording: 11/19/2023 19:55:58
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
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|
||||
<BR>
|
||||
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|
||||
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|
||||
<BR>
|
||||
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|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
|
@ -1,6 +1,6 @@
|
|||
NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
|
||||
NOTE All Rights Reserved *
|
||||
NOTE DATE CREATED: Thu Sep 21 05:38:47 2023 *
|
||||
NOTE DATE CREATED: Sat Jan 06 06:25:16 2024 *
|
||||
NOTE DESIGN NAME: RAM2GS *
|
||||
NOTE DEVICE NAME: LCMXO256C-3TQFP100 *
|
||||
NOTE PIN ASSIGNMENTS *
|
||||
|
|
|
@ -15,12 +15,12 @@ I/O cells: 67
|
|||
FD1S3JX 3 100.0
|
||||
GSR 1 100.0
|
||||
IB 26 100.0
|
||||
INV 8 100.0
|
||||
INV 7 100.0
|
||||
OB 33 100.0
|
||||
ORCALUT4 119 100.0
|
||||
PFUMX 2 100.0
|
||||
ORCALUT4 133 100.0
|
||||
PFUMX 1 100.0
|
||||
PUR 1 100.0
|
||||
VHI 1 100.0
|
||||
VLO 1 100.0
|
||||
|
||||
TOTAL 301
|
||||
TOTAL 313
|
||||
|
|
|
@ -4,7 +4,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Thu Sep 21 05:38:46 2023
|
||||
Sat Jan 06 06:25:15 2024
|
||||
|
||||
|
||||
Command: bitgen -w -g ES:No -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf
|
||||
|
|
Binary file not shown.
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
@ -15,18 +15,18 @@ Target Vendor: LATTICE
|
|||
Target Device: LCMXO256CTQFP100
|
||||
Target Performance: 3
|
||||
Mapper: mj5g00, version: Diamond (64-bit) 3.12.1.454
|
||||
Mapped on: 09/21/23 05:38:29
|
||||
Mapped on: 01/06/24 06:24:57
|
||||
|
||||
Design Summary
|
||||
--------------
|
||||
|
||||
Number of PFU registers: 92 out of 256 (36%)
|
||||
Number of SLICEs: 69 out of 128 (54%)
|
||||
SLICEs as Logic/ROM: 69 out of 128 (54%)
|
||||
Number of SLICEs: 76 out of 128 (59%)
|
||||
SLICEs as Logic/ROM: 76 out of 128 (59%)
|
||||
SLICEs as RAM: 0 out of 64 (0%)
|
||||
SLICEs as Carry: 9 out of 128 (7%)
|
||||
Number of LUT4s: 137 out of 256 (54%)
|
||||
Number used as logic LUTs: 119
|
||||
Number of LUT4s: 151 out of 256 (59%)
|
||||
Number used as logic LUTs: 133
|
||||
Number used as distributed RAM: 0
|
||||
Number used as ripple logic: 18
|
||||
Number used as shift registers: 0
|
||||
|
@ -49,37 +49,38 @@ Design Summary
|
|||
Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
|
||||
Number of Clock Enables: 5
|
||||
Net XOR8MEG18: 3 loads, 3 LSLICEs
|
||||
Net N_31: 1 loads, 1 LSLICEs
|
||||
Net N_33: 1 loads, 1 LSLICEs
|
||||
Net N_159_i: 2 loads, 2 LSLICEs
|
||||
Net N_24: 1 loads, 1 LSLICEs
|
||||
Net N_26: 1 loads, 1 LSLICEs
|
||||
Net N_153_i: 2 loads, 2 LSLICEs
|
||||
Net CmdUFMCLK_1_sqmuxa: 2 loads, 2 LSLICEs
|
||||
Number of LSRs: 4
|
||||
Number of LSRs: 5
|
||||
Net RA10s_i: 1 loads, 1 LSLICEs
|
||||
Net nRRAS_0_sqmuxa: 1 loads, 1 LSLICEs
|
||||
Net RASr2: 2 loads, 2 LSLICEs
|
||||
Net RASr2: 1 loads, 1 LSLICEs
|
||||
Net Ready_fast: 7 loads, 7 LSLICEs
|
||||
Net RCKEEN_8_u_0_1_a1_0: 1 loads, 1 LSLICEs
|
||||
Number of nets driven by tri-state buffers: 0
|
||||
Top 10 highest fanout non-clock nets:
|
||||
|
||||
Page 1
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 09/21/23 05:38:29
|
||||
Design: RAM2GS Date: 01/06/24 06:24:57
|
||||
|
||||
Design Summary (cont)
|
||||
---------------------
|
||||
Net InitReady: 16 loads
|
||||
Net Ready: 16 loads
|
||||
Net S[1]: 13 loads
|
||||
Net CO0: 12 loads
|
||||
Top 10 highest fanout non-clock nets:
|
||||
Net Ready: 18 loads
|
||||
Net InitReady: 17 loads
|
||||
Net S[1]: 17 loads
|
||||
Net CO0: 16 loads
|
||||
Net RASr2: 13 loads
|
||||
Net nRowColSel: 12 loads
|
||||
Net RASr2: 11 loads
|
||||
Net Din_c[5]: 10 loads
|
||||
Net Din_c[3]: 9 loads
|
||||
Net IS[0]: 9 loads
|
||||
Net MAin_c[1]: 8 loads
|
||||
Net IS[1]: 8 loads
|
||||
|
||||
|
||||
|
||||
|
@ -125,17 +126,17 @@ IO (PIO) Attributes
|
|||
| nRWE | OUTPUT | LVCMOS33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| RCKE | OUTPUT | LVCMOS33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
|
||||
Page 2
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 09/21/23 05:38:29
|
||||
Design: RAM2GS Date: 01/06/24 06:24:57
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| RCLK | INPUT | LVCMOS33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| nRCS | OUTPUT | LVCMOS33 | | |
|
||||
|
@ -191,17 +192,17 @@ IO (PIO) Attributes (cont)
|
|||
| nCCAS | INPUT | LVCMOS33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| Dout[7] | OUTPUT | LVCMOS33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
|
||||
Page 3
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 09/21/23 05:38:29
|
||||
Design: RAM2GS Date: 01/06/24 06:24:57
|
||||
|
||||
IO (PIO) Attributes (cont)
|
||||
--------------------------
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| Dout[6] | OUTPUT | LVCMOS33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| Dout[5] | OUTPUT | LVCMOS33 | | |
|
||||
|
@ -258,13 +259,12 @@ IO (PIO) Attributes (cont)
|
|||
|
||||
|
||||
|
||||
|
||||
Page 4
|
||||
|
||||
|
||||
|
||||
|
||||
Design: RAM2GS Date: 09/21/23 05:38:29
|
||||
Design: RAM2GS Date: 01/06/24 06:24:57
|
||||
|
||||
Removed logic
|
||||
-------------
|
||||
|
@ -275,7 +275,6 @@ Signal nFWE_c_i was merged into signal nFWE_c
|
|||
Signal nCRAS_c_i_0 was merged into signal nCRAS_c
|
||||
Signal nCCAS_c_i was merged into signal nCCAS_c
|
||||
Signal Ready_fast_i was merged into signal Ready_fast
|
||||
Signal IS_i[0] was merged into signal IS[0]
|
||||
Signal RASr2_i was merged into signal RASr2
|
||||
Signal XOR8MEG.CN was merged into signal PHI2_c
|
||||
Signal GND undriven or does not drive anything - clipped.
|
||||
|
@ -295,8 +294,7 @@ Block nFWE_pad_RNI420B was optimized away.
|
|||
Block RASr_RNO was optimized away.
|
||||
Block nCCAS_pad_RNISUR8 was optimized away.
|
||||
Block Ready_fast_RNI29NA was optimized away.
|
||||
Block IS_i[0] was optimized away.
|
||||
Block RASr2_RNIAFR1 was optimized away.
|
||||
Block S_RNO[1] was optimized away.
|
||||
Block XOR8MEG.CN was optimized away.
|
||||
Block GND was optimized away.
|
||||
Block VCC was optimized away.
|
||||
|
@ -325,6 +323,8 @@ Run Time and Memory Usage
|
|||
|
||||
|
||||
|
||||
|
||||
|
||||
Page 5
|
||||
|
||||
|
||||
|
|
|
@ -6,7 +6,7 @@ Performance Grade: 3
|
|||
PACKAGE: TQFP100
|
||||
Package Status: Final Version 1.19
|
||||
|
||||
Thu Sep 21 05:38:42 2023
|
||||
Sat Jan 06 06:25:11 2024
|
||||
|
||||
Pinout by Port Name:
|
||||
+-----------+----------+---------------+------+----------------------------------+
|
||||
|
@ -267,5 +267,5 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Thu Sep 21 05:38:42 2023
|
||||
Sat Jan 06 06:25:11 2024
|
||||
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
SCHEMATIC START ;
|
||||
# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Thu Sep 21 05:38:29 2023
|
||||
# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Sat Jan 06 06:24:58 2024
|
||||
|
||||
SYSCONFIG INBUF=ON CONFIG_SECURE=OFF ;
|
||||
LOCATE COMP "RD[0]" SITE "64" ;
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
#OS: Windows 8 6.2
|
||||
#Hostname: ZANEMACWIN11
|
||||
|
||||
# Thu Sep 21 05:38:16 2023
|
||||
# Sat Jan 6 06:24:47 2024
|
||||
|
||||
#Implementation: impl1
|
||||
|
||||
|
@ -50,19 +50,22 @@ Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 202
|
|||
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
|
||||
@I::"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-SPI.v" (library work)
|
||||
Verilog syntax check successful!
|
||||
|
||||
Compiler output is up to date. No re-compile necessary
|
||||
|
||||
Selecting top level module RAM2GS
|
||||
@N: CG364 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-SPI.v":1:7:1:12|Synthesizing module RAM2GS in library work.
|
||||
Running optimization stage 1 on RAM2GS .......
|
||||
Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 100MB)
|
||||
Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 100MB)
|
||||
Running optimization stage 2 on RAM2GS .......
|
||||
Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB)
|
||||
|
||||
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
|
||||
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 96MB peak: 97MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:38:17 2023
|
||||
# Sat Jan 6 06:24:47 2024
|
||||
|
||||
###########################################################]
|
||||
###########################################################[
|
||||
|
@ -89,7 +92,7 @@ At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s;
|
|||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:38:17 2023
|
||||
# Sat Jan 6 06:24:48 2024
|
||||
|
||||
###########################################################]
|
||||
|
||||
|
@ -104,7 +107,7 @@ At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory
|
|||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:38:17 2023
|
||||
# Sat Jan 6 06:24:48 2024
|
||||
|
||||
###########################################################]
|
||||
###########################################################[
|
||||
|
@ -125,18 +128,17 @@ Implementation : impl1
|
|||
Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
File \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_comp.srs changed - recompiling
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:38:18 2023
|
||||
# Sat Jan 6 06:24:49 2024
|
||||
|
||||
###########################################################]
|
||||
Premap Report
|
||||
|
||||
# Thu Sep 21 05:38:19 2023
|
||||
# Sat Jan 6 06:24:49 2024
|
||||
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
|
@ -158,7 +160,7 @@ Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built
|
|||
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
|
||||
|
||||
|
||||
Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 140MB)
|
||||
Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 140MB)
|
||||
|
||||
Reading constraint file: \\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS.sdc
|
||||
@L: \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1_scck.rpt
|
||||
|
@ -186,7 +188,6 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h
|
|||
@N: FX493 |Applying initial value "0" on instance CmdLEDEN.
|
||||
@N: FX493 |Applying initial value "0" on instance Cmdn8MEGEN.
|
||||
@N: FX493 |Applying initial value "1" on instance nRCS.
|
||||
@N: FX493 |Applying initial value "0" on instance LEDEN.
|
||||
@N: FX493 |Applying initial value "0" on instance n8MEGEN.
|
||||
@N: FX493 |Applying initial value "1" on instance nRRAS.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdUFMCLK.
|
||||
|
@ -205,17 +206,17 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h
|
|||
Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
|
||||
|
||||
|
||||
Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
|
||||
Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
|
||||
|
||||
|
||||
Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
|
||||
Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
|
||||
|
||||
|
||||
Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
|
||||
Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
|
||||
|
||||
@N: FX1184 |Applying syn_allowed_resources blockrams=0 on top level netlist RAM2GS
|
||||
|
||||
Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 181MB peak: 181MB)
|
||||
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
|
||||
|
||||
|
||||
|
||||
|
@ -282,10 +283,10 @@ Clock Tree ID Driving Element Drive Element Type Fanout Sample I
|
|||
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
|
||||
Finished Pre Mapping Phase.
|
||||
|
||||
Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
|
||||
Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
|
||||
|
||||
|
||||
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
|
||||
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
|
||||
|
||||
|
||||
Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
|
||||
|
@ -294,13 +295,11 @@ Pre-mapping successful!
|
|||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 98MB peak: 184MB)
|
||||
|
||||
Process took 0h:00m:02s realtime, 0h:00m:01s cputime
|
||||
# Thu Sep 21 05:38:21 2023
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Sat Jan 6 06:24:51 2024
|
||||
|
||||
###########################################################]
|
||||
Map & Optimize Report
|
||||
|
||||
# Thu Sep 21 05:38:21 2023
|
||||
# Sat Jan 6 06:24:51 2024
|
||||
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
|
@ -319,29 +318,29 @@ Implementation : impl1
|
|||
Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @
|
||||
|
||||
|
||||
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
|
||||
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
|
||||
|
||||
@N: MF916 |Option synthesis_strategy=base is enabled.
|
||||
@N: MF248 |Running in 64-bit mode.
|
||||
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
|
||||
|
||||
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 140MB)
|
||||
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 139MB)
|
||||
|
||||
|
||||
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 140MB)
|
||||
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 139MB)
|
||||
|
||||
|
||||
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB)
|
||||
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
|
||||
|
||||
|
||||
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB)
|
||||
|
||||
|
||||
|
||||
Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 179MB peak: 179MB)
|
||||
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 178MB peak: 178MB)
|
||||
|
||||
|
||||
Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
|
||||
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
|
||||
|
||||
@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":147:4:147:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0]
|
||||
@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":134:4:134:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0]
|
||||
|
@ -351,10 +350,10 @@ Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00
|
|||
@N: FX493 |Applying initial value "0" on instance IS[2].
|
||||
@N: FX493 |Applying initial value "0" on instance IS[3].
|
||||
|
||||
Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 184MB peak: 184MB)
|
||||
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 184MB peak: 184MB)
|
||||
|
||||
|
||||
Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB)
|
||||
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 185MB peak: 185MB)
|
||||
|
||||
|
||||
Available hyper_sources - for debug and ip models
|
||||
|
@ -367,64 +366,61 @@ Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CP
|
|||
Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 187MB peak: 187MB)
|
||||
|
||||
|
||||
Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
|
||||
Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
|
||||
|
||||
|
||||
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
|
||||
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
|
||||
|
||||
|
||||
Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
|
||||
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
|
||||
|
||||
|
||||
Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
|
||||
Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
|
||||
|
||||
Pass CPU time Worst Slack Luts / Registers
|
||||
------------------------------------------------------------
|
||||
1 0h:00m:01s -3.26ns 127 / 89
|
||||
2 0h:00m:01s -3.23ns 123 / 89
|
||||
3 0h:00m:01s -3.23ns 123 / 89
|
||||
4 0h:00m:01s -3.23ns 123 / 89
|
||||
5 0h:00m:01s -3.23ns 124 / 89
|
||||
6 0h:00m:01s -3.23ns 124 / 89
|
||||
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":105:4:105:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 7 loads 1 time to improve timing.
|
||||
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":105:4:105:9|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 5 loads 1 time to improve timing.
|
||||
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":147:4:147:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 15 loads 1 time to improve timing.
|
||||
1 0h:00m:01s -4.01ns 133 / 89
|
||||
2 0h:00m:01s -3.96ns 131 / 89
|
||||
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":105:4:105:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 8 loads 1 time to improve timing.
|
||||
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":105:4:105:9|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 7 loads 1 time to improve timing.
|
||||
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":147:4:147:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 19 loads 1 time to improve timing.
|
||||
Timing driven replication report
|
||||
Added 3 Registers via timing driven replication
|
||||
Added 1 LUTs via timing driven replication
|
||||
|
||||
7 0h:00m:02s -2.99ns 128 / 92
|
||||
3 0h:00m:02s -3.08ns 143 / 92
|
||||
4 0h:00m:02s -3.08ns 141 / 92
|
||||
|
||||
|
||||
8 0h:00m:02s -2.99ns 127 / 92
|
||||
9 0h:00m:02s -3.09ns 127 / 92
|
||||
10 0h:00m:02s -3.19ns 127 / 92
|
||||
11 0h:00m:02s -3.19ns 127 / 92
|
||||
12 0h:00m:02s -3.19ns 127 / 92
|
||||
5 0h:00m:02s -3.08ns 140 / 92
|
||||
6 0h:00m:02s -3.19ns 140 / 92
|
||||
7 0h:00m:02s -3.19ns 140 / 92
|
||||
8 0h:00m:02s -3.19ns 140 / 92
|
||||
9 0h:00m:02s -3.19ns 140 / 92
|
||||
|
||||
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 190MB)
|
||||
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 191MB peak: 191MB)
|
||||
|
||||
|
||||
Finished restoring hierarchy (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 191MB peak: 191MB)
|
||||
Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 191MB peak: 191MB)
|
||||
|
||||
|
||||
Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 155MB peak: 191MB)
|
||||
Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 155MB peak: 192MB)
|
||||
|
||||
Writing Analyst data base \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_m.srm
|
||||
|
||||
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 192MB peak: 192MB)
|
||||
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 192MB)
|
||||
|
||||
Writing EDIF Netlist and constraint files
|
||||
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.edi
|
||||
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
|
||||
|
||||
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 196MB peak: 196MB)
|
||||
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 196MB peak: 196MB)
|
||||
|
||||
|
||||
Finished Writing Netlists (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 196MB peak: 196MB)
|
||||
Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 196MB peak: 197MB)
|
||||
|
||||
|
||||
Start final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 194MB peak: 196MB)
|
||||
Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 195MB peak: 197MB)
|
||||
|
||||
@N: MT615 |Found clock RCLK with period 16.00ns
|
||||
@N: MT615 |Found clock PHI2 with period 350.00ns
|
||||
|
@ -433,7 +429,7 @@ Start final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:0
|
|||
|
||||
|
||||
##### START OF TIMING REPORT #####[
|
||||
# Timing report written on Thu Sep 21 05:38:27 2023
|
||||
# Timing report written on Sat Jan 6 06:24:55 2024
|
||||
#
|
||||
|
||||
|
||||
|
@ -466,8 +462,8 @@ nCRAS 2.9 MHz 0.6 MHz 350.000 1613.150 -3.60
|
|||
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
|
||||
|
||||
|
||||
@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.
|
||||
@W: MT117 |Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.
|
||||
@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.
|
||||
@W: MT118 |Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.
|
||||
@W: MT116 |Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.
|
||||
@W: MT117 |Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.
|
||||
|
@ -481,10 +477,10 @@ Clocks | rise to rise | fall to fall | rise to
|
|||
---------------------------------------------------------------------------------------------------------------
|
||||
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
|
||||
---------------------------------------------------------------------------------------------------------------
|
||||
RCLK RCLK | 16.000 7.560 | No paths - | No paths - | No paths -
|
||||
RCLK RCLK | 16.000 7.464 | No paths - | No paths - | No paths -
|
||||
RCLK PHI2 | 2.000 -1.216 | No paths - | 1.000 -2.312 | No paths -
|
||||
PHI2 RCLK | No paths - | No paths - | No paths - | 1.000 -3.705
|
||||
PHI2 PHI2 | No paths - | 350.000 343.998 | 175.000 166.500 | 175.000 171.784
|
||||
PHI2 PHI2 | No paths - | 350.000 344.094 | 175.000 165.215 | 175.000 171.784
|
||||
nCRAS RCLK | No paths - | No paths - | No paths - | 1.000 -3.609
|
||||
===============================================================================================================
|
||||
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
|
||||
|
@ -518,10 +514,10 @@ CmdUFMCS PHI2 FD1P3AX Q CmdUFMCS 1.348
|
|||
CmdUFMSDI PHI2 FD1P3AX Q CmdUFMSDI 1.348 -3.297
|
||||
CmdLEDEN PHI2 FD1P3AX Q CmdLEDEN 1.456 -2.216
|
||||
Cmdn8MEGEN PHI2 FD1P3AX Q Cmdn8MEGEN 1.456 -2.216
|
||||
Bank[2] PHI2 FD1S3AX Q Bank[2] 1.348 166.500
|
||||
Bank[3] PHI2 FD1S3AX Q Bank[3] 1.348 166.500
|
||||
Bank[4] PHI2 FD1S3AX Q Bank[4] 1.348 166.500
|
||||
Bank[5] PHI2 FD1S3AX Q Bank[5] 1.348 166.500
|
||||
Bank[0] PHI2 FD1S3AX Q Bank[0] 1.348 165.215
|
||||
Bank[1] PHI2 FD1S3AX Q Bank[1] 1.348 165.215
|
||||
Bank[2] PHI2 FD1S3AX Q Bank[2] 1.348 165.215
|
||||
Bank[3] PHI2 FD1S3AX Q Bank[3] 1.348 165.215
|
||||
=======================================================================================
|
||||
|
||||
|
||||
|
@ -535,13 +531,13 @@ Instance Reference Type Pin Net Time
|
|||
UFMCLK PHI2 FD1S3AX D UFMCLK_RNO -0.003 -3.705
|
||||
UFMSDI PHI2 FD1S3AX D UFMSDI_RNO -0.003 -3.705
|
||||
nUFMCS PHI2 FD1S3AY D nUFMCS_s_0_N_5_i -0.003 -3.705
|
||||
LEDEN PHI2 FD1P3AX SP N_33 0.806 -2.800
|
||||
n8MEGEN PHI2 FD1P3AX SP N_31 0.806 -2.800
|
||||
LEDEN PHI2 FD1P3AX D N_70 -0.003 -2.216
|
||||
n8MEGEN PHI2 FD1P3AX D N_69 -0.003 -2.216
|
||||
CmdSubmitted PHI2 FD1S3AX D N_460_0 173.997 166.500
|
||||
ADSubmitted PHI2 FD1S3AX D ADSubmitted_r 173.997 167.797
|
||||
C1Submitted PHI2 FD1S3AX D C1Submitted_RNO 173.997 167.797
|
||||
LEDEN PHI2 FD1P3AX SP N_26 0.806 -2.800
|
||||
n8MEGEN PHI2 FD1P3AX SP N_24 0.806 -2.800
|
||||
LEDEN PHI2 FD1P3AX D N_49 -0.003 -2.216
|
||||
n8MEGEN PHI2 FD1P3AX D N_48 -0.003 -2.216
|
||||
CmdEnable PHI2 FD1S3AX D CmdEnable_s 173.997 165.215
|
||||
CmdSubmitted PHI2 FD1S3AX D N_428_0 173.997 165.311
|
||||
ADSubmitted PHI2 FD1S3AX D ADSubmitted_r 173.997 166.404
|
||||
============================================================================================
|
||||
|
||||
|
||||
|
@ -573,7 +569,7 @@ CmdSubmitted FD1S3AX Q Out 1.552 1.552 r -
|
|||
CmdSubmitted Net - - - - 3
|
||||
PHI2r3_RNITCN41 ORCALUT4 A In 0.000 1.552 r -
|
||||
PHI2r3_RNITCN41 ORCALUT4 Z Out 1.393 2.945 r -
|
||||
N_139_i Net - - - - 3
|
||||
N_137_i Net - - - - 3
|
||||
UFMCLK_RNO ORCALUT4 A In 0.000 2.945 r -
|
||||
UFMCLK_RNO ORCALUT4 Z Out 0.757 3.702 r -
|
||||
UFMCLK_RNO Net - - - - 1
|
||||
|
@ -604,7 +600,7 @@ CmdSubmitted FD1S3AX Q Out 1.552 1.552 r -
|
|||
CmdSubmitted Net - - - - 3
|
||||
PHI2r3_RNITCN41 ORCALUT4 A In 0.000 1.552 r -
|
||||
PHI2r3_RNITCN41 ORCALUT4 Z Out 1.393 2.945 r -
|
||||
N_139_i Net - - - - 3
|
||||
N_137_i Net - - - - 3
|
||||
nUFMCS_s_0_N_5_i ORCALUT4 A In 0.000 2.945 r -
|
||||
nUFMCS_s_0_N_5_i ORCALUT4 Z Out 0.757 3.702 r -
|
||||
nUFMCS_s_0_N_5_i Net - - - - 1
|
||||
|
@ -635,7 +631,7 @@ CmdSubmitted FD1S3AX Q Out 1.552 1.552 r -
|
|||
CmdSubmitted Net - - - - 3
|
||||
PHI2r3_RNITCN41 ORCALUT4 A In 0.000 1.552 r -
|
||||
PHI2r3_RNITCN41 ORCALUT4 Z Out 1.393 2.945 r -
|
||||
N_139_i Net - - - - 3
|
||||
N_137_i Net - - - - 3
|
||||
UFMSDI_RNO ORCALUT4 A In 0.000 2.945 r -
|
||||
UFMSDI_RNO ORCALUT4 Z Out 0.757 3.702 r -
|
||||
UFMSDI_RNO Net - - - - 1
|
||||
|
@ -654,21 +650,21 @@ Detailed Report for Clock: RCLK
|
|||
Starting Points with Worst Slack
|
||||
********************************
|
||||
|
||||
Starting Arrival
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
-----------------------------------------------------------------------------
|
||||
LEDEN RCLK FD1P3AX Q LEDEN 1.552 -2.312
|
||||
n8MEGEN RCLK FD1P3AX Q n8MEGEN 1.456 -2.216
|
||||
FS[13] RCLK FD1S3AX Q FS[13] 1.552 7.560
|
||||
FS[14] RCLK FD1S3AX Q FS[14] 1.552 7.560
|
||||
FS[15] RCLK FD1S3AX Q FS[15] 1.552 7.560
|
||||
FS[17] RCLK FD1S3AX Q FS[17] 1.552 7.560
|
||||
S[1] RCLK FD1S3IX Q S[1] 1.768 8.533
|
||||
S[0] RCLK FD1S3IX Q CO0 1.756 8.545
|
||||
FS[16] RCLK FD1S3AX Q FS[16] 1.612 8.689
|
||||
FS[12] RCLK FD1S3AX Q FS[12] 1.552 8.749
|
||||
=============================================================================
|
||||
Starting Arrival
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
--------------------------------------------------------------------------------
|
||||
LEDEN RCLK FD1P3AX Q LEDEN 1.552 -2.312
|
||||
n8MEGEN RCLK FD1P3AX Q n8MEGEN 1.456 -2.216
|
||||
FS[12] RCLK FD1S3AX Q FS[12] 1.552 7.464
|
||||
FS[14] RCLK FD1S3AX Q FS[14] 1.552 7.464
|
||||
FS[15] RCLK FD1S3AX Q FS[15] 1.552 7.464
|
||||
FS[17] RCLK FD1S3AX Q FS[17] 1.552 7.464
|
||||
InitReady RCLK FD1S3AX Q InitReady 1.792 8.569
|
||||
S[1] RCLK FD1S3IX Q S[1] 1.792 8.569
|
||||
S[0] RCLK FD1S3IX Q CO0 1.780 8.581
|
||||
FS[13] RCLK FD1S3AX Q FS[13] 1.612 8.593
|
||||
================================================================================
|
||||
|
||||
|
||||
Ending Points with Worst Slack
|
||||
|
@ -678,16 +674,16 @@ Ending Points with Worst Slack
|
|||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
-----------------------------------------------------------------------------------------
|
||||
CmdLEDEN RCLK FD1P3AX D N_21_i -0.003 -2.312
|
||||
CmdLEDEN RCLK FD1P3AX D N_14_i -0.003 -2.312
|
||||
XOR8MEG RCLK FD1P3AX D XOR8MEG_3 -0.003 -2.312
|
||||
Cmdn8MEGEN RCLK FD1P3AX D N_19_i -0.003 -2.216
|
||||
Cmdn8MEGEN RCLK FD1P3AX D N_12_i -0.003 -2.216
|
||||
RA11 RCLK FD1S3IX D RA11_2 0.997 -1.216
|
||||
UFMSDI RCLK FD1S3AX D UFMSDI_RNO 14.997 7.560
|
||||
UFMSDI RCLK FD1S3AX D UFMSDI_RNO 14.997 7.464
|
||||
UFMCLK RCLK FD1S3AX D UFMCLK_RNO 14.997 7.668
|
||||
LEDEN RCLK FD1P3AX SP N_33 15.806 8.261
|
||||
n8MEGEN RCLK FD1P3AX SP N_31 15.806 8.261
|
||||
nRCS RCLK FD1S3AY D N_28_i 14.997 8.533
|
||||
nRCAS RCLK FD1S3AY D N_46_i 14.997 8.569
|
||||
nUFMCS RCLK FD1S3AY D nUFMCS_s_0_N_5_i 14.997 8.653
|
||||
nRCS RCLK FD1S3AY D N_143_i 14.997 8.881
|
||||
LEDEN RCLK FD1P3AX SP N_26 15.806 9.463
|
||||
=========================================================================================
|
||||
|
||||
|
||||
|
@ -717,9 +713,9 @@ Name Type Name Dir Delay Time Fan Out(s
|
|||
---------------------------------------------------------------------------------
|
||||
LEDEN FD1P3AX Q Out 1.552 1.552 r -
|
||||
LEDEN Net - - - - 3
|
||||
CmdLEDEN_RNO ORCALUT4 A In 0.000 1.552 r -
|
||||
CmdLEDEN_RNO ORCALUT4 B In 0.000 1.552 r -
|
||||
CmdLEDEN_RNO ORCALUT4 Z Out 0.757 2.309 r -
|
||||
N_21_i Net - - - - 1
|
||||
N_14_i Net - - - - 1
|
||||
CmdLEDEN FD1P3AX D In 0.000 2.309 r -
|
||||
=================================================================================
|
||||
|
||||
|
@ -740,16 +736,16 @@ Path information for path number 2:
|
|||
The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
|
||||
The end point is clocked by PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
-------------------------------------------------------------------------------------
|
||||
LEDEN FD1P3AX Q Out 1.552 1.552 r -
|
||||
LEDEN Net - - - - 3
|
||||
XOR8MEG_3_u_0_a3_3 ORCALUT4 B In 0.000 1.552 r -
|
||||
XOR8MEG_3_u_0_a3_3 ORCALUT4 Z Out 0.757 2.309 f -
|
||||
XOR8MEG_3 Net - - - - 1
|
||||
XOR8MEG FD1P3AX D In 0.000 2.309 f -
|
||||
=====================================================================================
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
---------------------------------------------------------------------------------------
|
||||
LEDEN FD1P3AX Q Out 1.552 1.552 r -
|
||||
LEDEN Net - - - - 3
|
||||
XOR8MEG_3_u_0_a3_0_2 ORCALUT4 B In 0.000 1.552 r -
|
||||
XOR8MEG_3_u_0_a3_0_2 ORCALUT4 Z Out 0.757 2.309 f -
|
||||
XOR8MEG_3 Net - - - - 1
|
||||
XOR8MEG FD1P3AX D In 0.000 2.309 f -
|
||||
=======================================================================================
|
||||
|
||||
|
||||
Path information for path number 3:
|
||||
|
@ -775,7 +771,7 @@ n8MEGEN FD1P3AX Q Out 1.456 1.456 r -
|
|||
n8MEGEN Net - - - - 2
|
||||
Cmdn8MEGEN_RNO ORCALUT4 C In 0.000 1.456 r -
|
||||
Cmdn8MEGEN_RNO ORCALUT4 Z Out 0.757 2.213 r -
|
||||
N_19_i Net - - - - 1
|
||||
N_12_i Net - - - - 1
|
||||
Cmdn8MEGEN FD1P3AX D In 0.000 2.213 r -
|
||||
=================================================================================
|
||||
|
||||
|
@ -795,10 +791,10 @@ Starting Points with Worst Slack
|
|||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
--------------------------------------------------------------------------------
|
||||
CBR nCRAS FD1S3AX Q CBR 1.660 -3.609
|
||||
CBR_fast nCRAS FD1S3AX Q CBR_fast 1.456 -3.513
|
||||
CBR_fast nCRAS FD1S3AX Q CBR_fast 1.552 -3.609
|
||||
CBR nCRAS FD1S3AX Q CBR 1.612 -3.561
|
||||
FWEr nCRAS FD1S3AX Q FWEr 1.552 -3.501
|
||||
FWEr_fast nCRAS FD1S3AX Q FWEr_fast 1.456 -3.405
|
||||
FWEr_fast nCRAS FD1S3AX Q FWEr_fast 1.552 -3.501
|
||||
================================================================================
|
||||
|
||||
|
||||
|
@ -809,11 +805,11 @@ Ending Points with Worst Slack
|
|||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
---------------------------------------------------------------------------------------
|
||||
nRWE nCRAS FD1S3AY D N_39_i -0.003 -3.609
|
||||
nRowColSel nCRAS FD1S3IX D nRowColSel_0_0 -0.003 -3.609
|
||||
nRCAS nCRAS FD1S3AY D N_37_i -0.003 -3.513
|
||||
RCKEEN nCRAS FD1S3AX D RCKEEN_8 -0.003 -3.405
|
||||
nRCS nCRAS FD1S3AY D N_28_i -0.003 -3.405
|
||||
nRCAS nCRAS FD1S3AY D N_46_i -0.003 -3.609
|
||||
nRWE nCRAS FD1S3AY D N_144_i -0.003 -3.609
|
||||
nRowColSel nCRAS FD1S3IX D nRowColSel_0_0 -0.003 -3.561
|
||||
RCKEEN nCRAS FD1S3AX D RCKEEN_8 -0.003 -3.501
|
||||
nRCS nCRAS FD1S3AY D N_143_i -0.003 -3.501
|
||||
=======================================================================================
|
||||
|
||||
|
||||
|
@ -833,24 +829,24 @@ Path information for path number 1:
|
|||
= Slack (non-critical) : -3.609
|
||||
|
||||
Number of logic level(s): 2
|
||||
Starting point: CBR / Q
|
||||
Ending point: nRWE / D
|
||||
Starting point: CBR_fast / Q
|
||||
Ending point: nRCAS / D
|
||||
The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
|
||||
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
---------------------------------------------------------------------------------
|
||||
CBR FD1S3AX Q Out 1.660 1.660 r -
|
||||
CBR Net - - - - 5
|
||||
nRWE_RNO_0 ORCALUT4 A In 0.000 1.660 r -
|
||||
nRWE_RNO_0 ORCALUT4 Z Out 1.189 2.849 f -
|
||||
G_17_1 Net - - - - 1
|
||||
nRWE_RNO ORCALUT4 B In 0.000 2.849 f -
|
||||
nRWE_RNO ORCALUT4 Z Out 0.757 3.606 r -
|
||||
N_39_i Net - - - - 1
|
||||
nRWE FD1S3AY D In 0.000 3.606 r -
|
||||
=================================================================================
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
----------------------------------------------------------------------------------------
|
||||
CBR_fast FD1S3AX Q Out 1.552 1.552 r -
|
||||
CBR_fast Net - - - - 3
|
||||
nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 A In 0.000 1.552 r -
|
||||
nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 Z Out 1.297 2.849 r -
|
||||
nRCAS_0_sqmuxa_1 Net - - - - 2
|
||||
nRCAS_RNO ORCALUT4 C In 0.000 2.849 r -
|
||||
nRCAS_RNO ORCALUT4 Z Out 0.757 3.606 f -
|
||||
N_46_i Net - - - - 1
|
||||
nRCAS FD1S3AY D In 0.000 3.606 f -
|
||||
========================================================================================
|
||||
|
||||
|
||||
Path information for path number 2:
|
||||
|
@ -864,24 +860,24 @@ Path information for path number 2:
|
|||
= Slack (non-critical) : -3.609
|
||||
|
||||
Number of logic level(s): 2
|
||||
Starting point: CBR / Q
|
||||
Ending point: nRowColSel / D
|
||||
Starting point: CBR_fast / Q
|
||||
Ending point: nRWE / D
|
||||
The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
|
||||
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
--------------------------------------------------------------------------------------
|
||||
CBR FD1S3AX Q Out 1.660 1.660 r -
|
||||
CBR Net - - - - 5
|
||||
nRowColSel_0_0_a3_0 ORCALUT4 B In 0.000 1.660 r -
|
||||
nRowColSel_0_0_a3_0 ORCALUT4 Z Out 1.189 2.849 f -
|
||||
N_179 Net - - - - 1
|
||||
nRowColSel_0_0 ORCALUT4 B In 0.000 2.849 f -
|
||||
nRowColSel_0_0 ORCALUT4 Z Out 0.757 3.606 f -
|
||||
nRowColSel_0_0 Net - - - - 1
|
||||
nRowColSel FD1S3IX D In 0.000 3.606 f -
|
||||
======================================================================================
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
----------------------------------------------------------------------------------------
|
||||
CBR_fast FD1S3AX Q Out 1.552 1.552 r -
|
||||
CBR_fast Net - - - - 3
|
||||
nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 A In 0.000 1.552 r -
|
||||
nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 Z Out 1.297 2.849 r -
|
||||
nRCAS_0_sqmuxa_1 Net - - - - 2
|
||||
nRWE_RNO ORCALUT4 C In 0.000 2.849 r -
|
||||
nRWE_RNO ORCALUT4 Z Out 0.757 3.606 r -
|
||||
N_144_i Net - - - - 1
|
||||
nRWE FD1S3AY D In 0.000 3.606 r -
|
||||
========================================================================================
|
||||
|
||||
|
||||
Path information for path number 3:
|
||||
|
@ -890,29 +886,29 @@ Path information for path number 3:
|
|||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
= Required time: -0.003
|
||||
|
||||
- Propagation time: 3.510
|
||||
- Propagation time: 3.558
|
||||
- Clock delay at starting point: 0.000 (ideal)
|
||||
= Slack (non-critical) : -3.513
|
||||
= Slack (non-critical) : -3.561
|
||||
|
||||
Number of logic level(s): 2
|
||||
Starting point: CBR_fast / Q
|
||||
Starting point: CBR / Q
|
||||
Ending point: nRCAS / D
|
||||
The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
|
||||
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
----------------------------------------------------------------------------------------
|
||||
CBR_fast FD1S3AX Q Out 1.456 1.456 r -
|
||||
CBR_fast Net - - - - 2
|
||||
nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 A In 0.000 1.456 r -
|
||||
nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 Z Out 1.297 2.753 r -
|
||||
nRCAS_0_sqmuxa_1 Net - - - - 2
|
||||
nRCAS_RNO ORCALUT4 B In 0.000 2.753 r -
|
||||
nRCAS_RNO ORCALUT4 Z Out 0.757 3.510 f -
|
||||
N_37_i Net - - - - 1
|
||||
nRCAS FD1S3AY D In 0.000 3.510 f -
|
||||
========================================================================================
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
---------------------------------------------------------------------------------
|
||||
CBR FD1S3AX Q Out 1.612 1.612 r -
|
||||
CBR Net - - - - 4
|
||||
nRCAS_RNO_1 ORCALUT4 A In 0.000 1.612 r -
|
||||
nRCAS_RNO_1 ORCALUT4 Z Out 1.189 2.801 f -
|
||||
G_1_1 Net - - - - 1
|
||||
nRCAS_RNO ORCALUT4 B In 0.000 2.801 f -
|
||||
nRCAS_RNO ORCALUT4 Z Out 0.757 3.558 r -
|
||||
N_46_i Net - - - - 1
|
||||
nRCAS FD1S3AY D In 0.000 3.558 r -
|
||||
=================================================================================
|
||||
|
||||
|
||||
|
||||
|
@ -920,10 +916,10 @@ nRCAS FD1S3AY D In 0.000 3.510 f -
|
|||
|
||||
Timing exceptions that could not be applied
|
||||
|
||||
Finished final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 195MB peak: 196MB)
|
||||
Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 196MB peak: 197MB)
|
||||
|
||||
|
||||
Finished timing report (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 195MB peak: 196MB)
|
||||
Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 196MB peak: 197MB)
|
||||
|
||||
---------------------------------------
|
||||
Resource Usage Report
|
||||
|
@ -944,18 +940,18 @@ FD1S3IX: 14
|
|||
FD1S3JX: 3
|
||||
GSR: 1
|
||||
IB: 26
|
||||
INV: 8
|
||||
INV: 7
|
||||
OB: 33
|
||||
ORCALUT4: 119
|
||||
PFUMX: 2
|
||||
ORCALUT4: 133
|
||||
PFUMX: 1
|
||||
PUR: 1
|
||||
VHI: 1
|
||||
VLO: 1
|
||||
Mapper successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 80MB peak: 196MB)
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 78MB peak: 197MB)
|
||||
|
||||
Process took 0h:00m:05s realtime, 0h:00m:04s cputime
|
||||
# Thu Sep 21 05:38:27 2023
|
||||
Process took 0h:00m:03s realtime, 0h:00m:03s cputime
|
||||
# Sat Jan 6 06:24:55 2024
|
||||
|
||||
###########################################################]
|
||||
|
|
|
@ -13,7 +13,7 @@ Setup and Hold Report
|
|||
|
||||
--------------------------------------------------------------------------------
|
||||
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
|
||||
Thu Sep 21 05:38:30 2023
|
||||
Sat Jan 06 06:24:59 2024
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
|
@ -38,46 +38,48 @@ BLOCK RESETPATHS
|
|||
|
||||
================================================================================
|
||||
Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
|
||||
129 items scored, 0 timing errors detected.
|
||||
168 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 162.619ns (weighted slack = 325.238ns)
|
||||
Passed: The following path meets requirements by 160.807ns (weighted slack = 321.614ns)
|
||||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q Bank[2] (from PHI2_c +)
|
||||
Destination: FF Data in CmdSubmitted (to PHI2_c -)
|
||||
Source: FF Q Bank[6] (from PHI2_c +)
|
||||
Destination: FF Data in CmdEnable (to PHI2_c -)
|
||||
|
||||
Delay: 9.621ns (25.1% logic, 74.9% route), 6 logic levels.
|
||||
Delay: 11.433ns (24.4% logic, 75.6% route), 7 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
9.621ns physical path delay SLICE_71 to SLICE_22 meets
|
||||
11.433ns physical path delay SLICE_75 to SLICE_20 meets
|
||||
172.414ns delay constraint less
|
||||
0.174ns DIN_SET requirement (totaling 172.240ns) by 162.619ns
|
||||
0.174ns DIN_SET requirement (totaling 172.240ns) by 160.807ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path SLICE_71 to SLICE_22:
|
||||
Data path SLICE_75 to SLICE_20:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.560 SLICE_71.CLK to SLICE_71.Q0 SLICE_71 (from PHI2_c)
|
||||
ROUTE 1 e 1.441 SLICE_71.Q0 to SLICE_56.A1 Bank[2]
|
||||
CTOF_DEL --- 0.371 SLICE_56.A1 to SLICE_56.F1 SLICE_56
|
||||
ROUTE 1 e 1.441 SLICE_56.F1 to SLICE_70.D1 C1WR_0_a2_0_11
|
||||
CTOF_DEL --- 0.371 SLICE_70.D1 to SLICE_70.F1 SLICE_70
|
||||
ROUTE 6 e 1.441 SLICE_70.F1 to SLICE_67.D0 N_147
|
||||
CTOF_DEL --- 0.371 SLICE_67.D0 to SLICE_67.F0 SLICE_67
|
||||
ROUTE 5 e 1.441 SLICE_67.F0 to SLICE_82.A0 XOR8MEG18
|
||||
CTOF_DEL --- 0.371 SLICE_82.A0 to SLICE_82.F0 SLICE_82
|
||||
ROUTE 1 e 1.441 SLICE_82.F0 to SLICE_22.A0 CmdSubmitted_1_sqmuxa
|
||||
CTOF_DEL --- 0.371 SLICE_22.A0 to SLICE_22.F0 SLICE_22
|
||||
ROUTE 1 e 0.001 SLICE_22.F0 to SLICE_22.DI0 N_460_0 (to PHI2_c)
|
||||
REG_DEL --- 0.560 SLICE_75.CLK to SLICE_75.Q0 SLICE_75 (from PHI2_c)
|
||||
ROUTE 1 e 1.441 SLICE_75.Q0 to SLICE_77.C1 Bank[6]
|
||||
CTOF_DEL --- 0.371 SLICE_77.C1 to SLICE_77.F1 SLICE_77
|
||||
ROUTE 2 e 1.441 SLICE_77.F1 to SLICE_79.D0 un1_Bank_1_5
|
||||
CTOF_DEL --- 0.371 SLICE_79.D0 to SLICE_79.F0 SLICE_79
|
||||
ROUTE 2 e 1.441 SLICE_79.F0 to SLICE_76.B0 C1WR_7
|
||||
CTOF_DEL --- 0.371 SLICE_76.B0 to SLICE_76.F0 SLICE_76
|
||||
ROUTE 5 e 1.441 SLICE_76.F0 to SLICE_70.B0 C1WR
|
||||
CTOF_DEL --- 0.371 SLICE_70.B0 to SLICE_70.F0 SLICE_70
|
||||
ROUTE 1 e 1.441 SLICE_70.F0 to SLICE_14.C1 N_121
|
||||
CTOF_DEL --- 0.371 SLICE_14.C1 to SLICE_14.F1 SLICE_14
|
||||
ROUTE 1 e 1.441 SLICE_14.F1 to SLICE_20.C0 un1_CmdEnable20_i
|
||||
CTOF_DEL --- 0.371 SLICE_20.C0 to SLICE_20.F0 SLICE_20
|
||||
ROUTE 1 e 0.001 SLICE_20.F0 to SLICE_20.DI0 CmdEnable_s (to PHI2_c)
|
||||
--------
|
||||
9.621 (25.1% logic, 74.9% route), 6 logic levels.
|
||||
11.433 (24.4% logic, 75.6% route), 7 logic levels.
|
||||
|
||||
Report: 51.046MHz is the maximum frequency for this preference.
|
||||
Report: 43.077MHz is the maximum frequency for this preference.
|
||||
|
||||
|
||||
================================================================================
|
||||
|
@ -118,46 +120,46 @@ Report: 400.000MHz is the maximum frequency for this preference.
|
|||
|
||||
================================================================================
|
||||
Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
|
||||
388 items scored, 0 timing errors detected.
|
||||
392 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 4.695ns
|
||||
Passed: The following path meets requirements by 6.198ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q FS[17] (from RCLK_c +)
|
||||
Destination: FF Data in LEDEN (to RCLK_c +)
|
||||
Destination: FF Data in UFMSDI (to RCLK_c +)
|
||||
|
||||
Delay: 11.061ns (21.8% logic, 78.2% route), 6 logic levels.
|
||||
Delay: 9.621ns (25.1% logic, 74.9% route), 6 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
11.061ns physical path delay SLICE_1 to SLICE_33 meets
|
||||
9.621ns physical path delay SLICE_1 to SLICE_52 meets
|
||||
16.000ns delay constraint less
|
||||
0.244ns CE_SET requirement (totaling 15.756ns) by 4.695ns
|
||||
0.181ns DIN_SET requirement (totaling 15.819ns) by 6.198ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path SLICE_1 to SLICE_33:
|
||||
Data path SLICE_1 to SLICE_52:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.560 SLICE_1.CLK to SLICE_1.Q1 SLICE_1 (from RCLK_c)
|
||||
ROUTE 3 e 1.441 SLICE_1.Q1 to SLICE_81.D1 FS[17]
|
||||
CTOF_DEL --- 0.371 SLICE_81.D1 to SLICE_81.F1 SLICE_81
|
||||
ROUTE 1 e 1.441 SLICE_81.F1 to SLICE_72.C1 UFMSDI_ens2_i_o2_0_3
|
||||
CTOF_DEL --- 0.371 SLICE_72.C1 to SLICE_72.F1 SLICE_72
|
||||
ROUTE 4 e 1.441 SLICE_72.F1 to SLICE_58.C1 N_51
|
||||
ROUTE 3 e 1.441 SLICE_1.Q1 to SLICE_86.D1 FS[17]
|
||||
CTOF_DEL --- 0.371 SLICE_86.D1 to SLICE_86.F1 SLICE_86
|
||||
ROUTE 1 e 1.441 SLICE_86.F1 to SLICE_69.C1 UFMSDI_ens2_i_o2_0_3
|
||||
CTOF_DEL --- 0.371 SLICE_69.C1 to SLICE_69.F1 SLICE_69
|
||||
ROUTE 4 e 1.441 SLICE_69.F1 to SLICE_58.C1 N_128
|
||||
CTOF_DEL --- 0.371 SLICE_58.C1 to SLICE_58.F1 SLICE_58
|
||||
ROUTE 2 e 1.441 SLICE_58.F1 to SLICE_87.D0 N_151
|
||||
CTOF_DEL --- 0.371 SLICE_87.D0 to SLICE_87.F0 SLICE_87
|
||||
ROUTE 2 e 1.441 SLICE_87.F0 to SLICE_69.C0 N_137_8
|
||||
CTOF_DEL --- 0.371 SLICE_69.C0 to SLICE_69.F0 SLICE_69
|
||||
ROUTE 1 e 1.441 SLICE_69.F0 to SLICE_33.CE N_33 (to RCLK_c)
|
||||
ROUTE 3 e 1.441 SLICE_58.F1 to SLICE_55.C0 N_94
|
||||
CTOF_DEL --- 0.371 SLICE_55.C0 to SLICE_55.F0 SLICE_55
|
||||
ROUTE 1 e 1.441 SLICE_55.F0 to SLICE_52.D0 UFMSDI_r_xx_mm_1
|
||||
CTOF_DEL --- 0.371 SLICE_52.D0 to SLICE_52.F0 SLICE_52
|
||||
ROUTE 1 e 0.001 SLICE_52.F0 to SLICE_52.DI0 UFMSDI_RNO (to RCLK_c)
|
||||
--------
|
||||
11.061 (21.8% logic, 78.2% route), 6 logic levels.
|
||||
9.621 (25.1% logic, 74.9% route), 6 logic levels.
|
||||
|
||||
Report: 88.456MHz is the maximum frequency for this preference.
|
||||
Report: 102.020MHz is the maximum frequency for this preference.
|
||||
|
||||
Report Summary
|
||||
--------------
|
||||
|
@ -165,13 +167,13 @@ Report Summary
|
|||
Preference | Constraint| Actual|Levels
|
||||
----------------------------------------------------------------------------
|
||||
| | |
|
||||
FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 51.046 MHz| 6
|
||||
FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 43.077 MHz| 7
|
||||
| | |
|
||||
FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 400.000 MHz| 0
|
||||
| | |
|
||||
FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 400.000 MHz| 0
|
||||
| | |
|
||||
FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 88.456 MHz| 6
|
||||
FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 102.020 MHz| 6
|
||||
| | |
|
||||
----------------------------------------------------------------------------
|
||||
|
||||
|
@ -226,11 +228,11 @@ Timing summary (Setup):
|
|||
Timing errors: 0 Score: 0
|
||||
Cumulative negative slack: 0
|
||||
|
||||
Constraints cover 517 paths, 4 nets, and 395 connections (62.40% coverage)
|
||||
Constraints cover 560 paths, 4 nets, and 424 connections (62.26% coverage)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
|
||||
Thu Sep 21 05:38:30 2023
|
||||
Sat Jan 06 06:24:59 2024
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
|
@ -255,7 +257,7 @@ BLOCK RESETPATHS
|
|||
|
||||
================================================================================
|
||||
Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
|
||||
129 items scored, 0 timing errors detected.
|
||||
168 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
@ -301,7 +303,7 @@ Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
|
|||
|
||||
================================================================================
|
||||
Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
|
||||
388 items scored, 0 timing errors detected.
|
||||
392 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
@ -316,17 +318,17 @@ Passed: The following path meets requirements by 0.342ns
|
|||
|
||||
Constraint Details:
|
||||
|
||||
0.325ns physical path delay SLICE_75 to SLICE_75 meets
|
||||
0.325ns physical path delay SLICE_74 to SLICE_74 meets
|
||||
-0.017ns M_HLD and
|
||||
0.000ns delay constraint requirement (totaling -0.017ns) by 0.342ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path SLICE_75 to SLICE_75:
|
||||
Data path SLICE_74 to SLICE_74:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.126 SLICE_75.CLK to SLICE_75.Q0 SLICE_75 (from RCLK_c)
|
||||
ROUTE 1 e 0.199 SLICE_75.Q0 to SLICE_75.M1 CASr (to RCLK_c)
|
||||
REG_DEL --- 0.126 SLICE_74.CLK to SLICE_74.Q0 SLICE_74 (from RCLK_c)
|
||||
ROUTE 1 e 0.199 SLICE_74.Q0 to SLICE_74.M1 CASr (to RCLK_c)
|
||||
--------
|
||||
0.325 (38.8% logic, 61.2% route), 1 logic levels.
|
||||
|
||||
|
@ -397,7 +399,7 @@ Timing summary (Hold):
|
|||
Timing errors: 0 Score: 0
|
||||
Cumulative negative slack: 0
|
||||
|
||||
Constraints cover 517 paths, 4 nets, and 395 connections (62.40% coverage)
|
||||
Constraints cover 560 paths, 4 nets, and 424 connections (62.26% coverage)
|
||||
|
||||
|
||||
|
||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -12,7 +12,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Thu Sep 21 05:38:46 2023
|
||||
Sat Jan 06 06:25:15 2024
|
||||
|
||||
|
||||
Command: bitgen -w -g ES:No -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf
|
||||
|
|
|
@ -13,7 +13,7 @@ Hostname: ZANEMACWIN11
|
|||
|
||||
Implementation : impl1
|
||||
|
||||
# Written on Thu Sep 21 05:38:20 2023
|
||||
# Written on Sat Jan 6 06:24:51 2024
|
||||
|
||||
##### DESIGN INFO #######################################################
|
||||
|
||||
|
@ -48,8 +48,8 @@ nCRAS RCLK | No paths | No paths | No p
|
|||
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
|
||||
|
||||
|
||||
@W:"//mac/icloud/repos/ram2gs/cpld/ram2gs.sdc":2:0:2:0|Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.
|
||||
@W:"//mac/icloud/repos/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.
|
||||
@W:"//mac/icloud/repos/ram2gs/cpld/ram2gs.sdc":2:0:2:0|Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.
|
||||
@W:"//mac/icloud/repos/ram2gs/cpld/ram2gs.sdc":3:0:3:0|Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.
|
||||
@W:"//mac/icloud/repos/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.
|
||||
@W:"//mac/icloud/repos/ram2gs/cpld/ram2gs.sdc":1:0:1:0|Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.
|
||||
|
|
|
@ -38,7 +38,7 @@ Performance Hardware Data Status: Version 1.124.
|
|||
// Package: TQFP100
|
||||
// ncd File: ram2gs_lcmxo256c_impl1.ncd
|
||||
// Version: Diamond (64-bit) 3.12.1.454
|
||||
// Written on Thu Sep 21 05:38:44 2023
|
||||
// Written on Sat Jan 06 06:25:13 2024
|
||||
// M: Minimum Performance Grade
|
||||
// iotiming RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO256C/promote.xml
|
||||
|
||||
|
@ -50,99 +50,99 @@ Worst Case Results across Performance Grades (M, 5, 4, 3):
|
|||
|
||||
Port Clock Edge Setup Performance_Grade Hold Performance_Grade
|
||||
----------------------------------------------------------------------
|
||||
CROW[0] nCRAS F -0.006 M 1.904 3
|
||||
CROW[1] nCRAS F -0.006 M 1.904 3
|
||||
Din[0] PHI2 F 4.101 3 2.207 3
|
||||
Din[0] nCCAS F 1.552 3 -0.018 M
|
||||
Din[1] PHI2 F 2.668 3 3.026 3
|
||||
Din[1] nCCAS F 0.606 3 0.745 3
|
||||
Din[2] PHI2 F 2.073 3 2.917 3
|
||||
Din[2] nCCAS F 0.500 3 0.619 3
|
||||
Din[3] PHI2 F 2.620 3 3.334 3
|
||||
Din[3] nCCAS F -0.089 M 1.336 3
|
||||
Din[4] PHI2 F 5.116 3 2.411 3
|
||||
Din[4] nCCAS F 0.293 3 1.125 3
|
||||
Din[5] PHI2 F 5.590 3 2.084 3
|
||||
Din[5] nCCAS F 0.435 3 0.979 3
|
||||
Din[6] PHI2 F 5.951 3 1.726 3
|
||||
Din[6] nCCAS F 1.305 3 0.253 3
|
||||
Din[7] PHI2 F 4.412 3 1.404 3
|
||||
Din[7] nCCAS F 0.195 3 1.215 3
|
||||
MAin[0] PHI2 F 3.306 3 1.176 3
|
||||
MAin[0] nCRAS F -0.132 M 2.336 3
|
||||
MAin[1] PHI2 F 2.656 3 2.511 3
|
||||
MAin[1] nCRAS F -0.034 M 2.014 3
|
||||
MAin[2] PHI2 F 6.839 3 -0.310 M
|
||||
MAin[2] nCRAS F -0.154 M 2.424 3
|
||||
MAin[3] PHI2 F 6.871 3 -0.311 M
|
||||
MAin[3] nCRAS F -0.015 M 1.928 3
|
||||
MAin[4] PHI2 F 7.111 3 -0.361 M
|
||||
MAin[4] nCRAS F 0.370 3 1.590 3
|
||||
MAin[5] PHI2 F 7.075 3 -0.353 M
|
||||
MAin[5] nCRAS F -0.126 M 2.320 3
|
||||
MAin[6] PHI2 F 6.794 3 -0.295 M
|
||||
MAin[6] nCRAS F 0.010 3 1.885 3
|
||||
MAin[7] PHI2 F 6.926 3 -0.324 M
|
||||
MAin[7] nCRAS F 0.319 3 1.622 3
|
||||
MAin[8] nCRAS F -0.038 M 2.031 3
|
||||
MAin[9] nCRAS F 0.366 3 1.596 3
|
||||
PHI2 RCLK R 2.295 3 -0.174 M
|
||||
UFMSDO RCLK R 1.364 3 0.511 3
|
||||
nCCAS RCLK R 2.300 3 -0.185 M
|
||||
nCCAS nCRAS F 0.216 3 1.721 3
|
||||
nCRAS RCLK R 4.548 3 -0.507 M
|
||||
nFWE PHI2 F 6.729 3 -0.281 M
|
||||
nFWE nCRAS F -0.037 M 2.025 3
|
||||
CROW[0] nCRAS F -0.006 M 1.907 3
|
||||
CROW[1] nCRAS F -0.006 M 1.907 3
|
||||
Din[0] PHI2 F 4.304 3 2.935 3
|
||||
Din[0] nCCAS F 0.567 3 0.723 3
|
||||
Din[1] PHI2 F 4.920 3 3.034 3
|
||||
Din[1] nCCAS F 0.414 3 0.851 3
|
||||
Din[2] PHI2 F 3.171 3 3.327 3
|
||||
Din[2] nCCAS F 0.909 3 0.432 3
|
||||
Din[3] PHI2 F 4.332 3 2.525 3
|
||||
Din[3] nCCAS F 0.038 3 1.155 3
|
||||
Din[4] PHI2 F 5.624 3 2.635 3
|
||||
Din[4] nCCAS F 1.448 3 -0.041 M
|
||||
Din[5] PHI2 F 4.126 3 2.124 3
|
||||
Din[5] nCCAS F 1.046 3 0.159 3
|
||||
Din[6] PHI2 F 5.565 3 2.394 3
|
||||
Din[6] nCCAS F 0.563 3 0.729 3
|
||||
Din[7] PHI2 F 5.293 3 1.654 3
|
||||
Din[7] nCCAS F 0.719 3 0.583 3
|
||||
MAin[0] PHI2 F 8.072 3 -0.164 M
|
||||
MAin[0] nCRAS F -0.128 M 2.331 3
|
||||
MAin[1] PHI2 F 7.487 3 -0.178 M
|
||||
MAin[1] nCRAS F -0.129 M 2.331 3
|
||||
MAin[2] PHI2 F 6.793 3 -0.034 M
|
||||
MAin[2] nCRAS F -0.129 M 2.331 3
|
||||
MAin[3] PHI2 F 7.235 3 -0.226 M
|
||||
MAin[3] nCRAS F -0.035 M 2.023 3
|
||||
MAin[4] PHI2 F 7.305 3 -0.207 M
|
||||
MAin[4] nCRAS F 0.428 3 1.517 3
|
||||
MAin[5] PHI2 F 7.672 3 -0.236 M
|
||||
MAin[5] nCRAS F -0.037 M 2.028 3
|
||||
MAin[6] PHI2 F 9.015 3 -0.710 M
|
||||
MAin[6] nCRAS F -0.003 M 1.896 3
|
||||
MAin[7] PHI2 F 7.764 3 -0.441 M
|
||||
MAin[7] nCRAS F -0.126 M 2.324 3
|
||||
MAin[8] nCRAS F -0.038 M 2.034 3
|
||||
MAin[9] nCRAS F 0.206 3 1.728 3
|
||||
PHI2 RCLK R 2.769 3 -0.274 M
|
||||
UFMSDO RCLK R 1.753 3 -0.052 M
|
||||
nCCAS RCLK R 1.935 3 -0.108 M
|
||||
nCCAS nCRAS F 0.843 3 1.179 3
|
||||
nCRAS RCLK R 1.093 3 0.277 3
|
||||
nFWE PHI2 F 4.435 3 0.640 3
|
||||
nFWE nCRAS F 1.163 3 0.894 3
|
||||
|
||||
|
||||
// Clock to Output Delay
|
||||
|
||||
Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
|
||||
------------------------------------------------------------------------
|
||||
LED RCLK R 13.764 3 4.455 M
|
||||
LED nCRAS F 16.500 3 4.993 M
|
||||
RA[0] RCLK R 10.114 3 2.098 M
|
||||
RA[0] nCRAS F 11.793 3 2.420 M
|
||||
RA[10] RCLK R 8.581 3 1.780 M
|
||||
LED RCLK R 15.407 3 4.713 M
|
||||
LED nCRAS F 17.685 3 5.215 M
|
||||
RA[0] RCLK R 10.436 3 2.152 M
|
||||
RA[0] nCRAS F 11.488 3 2.330 M
|
||||
RA[10] RCLK R 8.093 3 1.668 M
|
||||
RA[11] PHI2 R 9.420 3 1.925 M
|
||||
RA[1] RCLK R 11.717 3 2.429 M
|
||||
RA[1] nCRAS F 12.171 3 2.492 M
|
||||
RA[2] RCLK R 9.514 3 1.971 M
|
||||
RA[2] nCRAS F 11.301 3 2.319 M
|
||||
RA[3] RCLK R 10.525 3 2.169 M
|
||||
RA[3] nCRAS F 12.042 3 2.459 M
|
||||
RA[4] RCLK R 11.387 3 2.343 M
|
||||
RA[4] nCRAS F 12.532 3 2.543 M
|
||||
RA[5] RCLK R 10.114 3 2.098 M
|
||||
RA[5] nCRAS F 10.936 3 2.242 M
|
||||
RA[6] RCLK R 9.514 3 1.971 M
|
||||
RA[6] nCRAS F 10.544 3 2.165 M
|
||||
RA[7] RCLK R 10.933 3 2.261 M
|
||||
RA[7] nCRAS F 11.162 3 2.268 M
|
||||
RA[8] RCLK R 10.591 3 2.178 M
|
||||
RA[8] nCRAS F 11.951 3 2.426 M
|
||||
RA[9] RCLK R 9.668 3 1.989 M
|
||||
RA[9] nCRAS F 10.889 3 2.209 M
|
||||
RBA[0] nCRAS F 8.922 3 1.828 M
|
||||
RBA[1] nCRAS F 10.649 3 2.177 M
|
||||
RCKE RCLK R 8.493 3 1.760 M
|
||||
RDQMH RCLK R 10.817 3 2.273 M
|
||||
RDQML RCLK R 11.739 3 2.471 M
|
||||
RD[0] nCCAS F 9.545 3 2.093 M
|
||||
RD[1] nCCAS F 8.834 3 1.965 M
|
||||
RD[2] nCCAS F 9.535 3 2.092 M
|
||||
RD[3] nCCAS F 9.531 3 2.092 M
|
||||
RD[4] nCCAS F 9.303 3 2.066 M
|
||||
RD[5] nCCAS F 11.766 3 2.555 M
|
||||
RD[6] nCCAS F 9.303 3 2.066 M
|
||||
RD[7] nCCAS F 10.470 3 2.285 M
|
||||
UFMCLK RCLK R 9.190 3 1.937 M
|
||||
RA[1] RCLK R 10.958 3 2.270 M
|
||||
RA[1] nCRAS F 12.371 3 2.529 M
|
||||
RA[2] RCLK R 10.892 3 2.242 M
|
||||
RA[2] nCRAS F 11.786 3 2.402 M
|
||||
RA[3] RCLK R 10.561 3 2.184 M
|
||||
RA[3] nCRAS F 12.541 3 2.560 M
|
||||
RA[4] RCLK R 10.909 3 2.257 M
|
||||
RA[4] nCRAS F 12.060 3 2.456 M
|
||||
RA[5] RCLK R 9.970 3 2.057 M
|
||||
RA[5] nCRAS F 12.271 3 2.508 M
|
||||
RA[6] RCLK R 9.222 3 1.920 M
|
||||
RA[6] nCRAS F 10.844 3 2.210 M
|
||||
RA[7] RCLK R 9.613 3 1.981 M
|
||||
RA[7] nCRAS F 11.686 3 2.379 M
|
||||
RA[8] RCLK R 9.617 3 1.982 M
|
||||
RA[8] nCRAS F 11.487 3 2.339 M
|
||||
RA[9] RCLK R 9.762 3 2.016 M
|
||||
RA[9] nCRAS F 11.488 3 2.337 M
|
||||
RBA[0] nCRAS F 8.925 3 1.828 M
|
||||
RBA[1] nCRAS F 10.608 3 2.153 M
|
||||
RCKE RCLK R 7.609 3 1.570 M
|
||||
RDQMH RCLK R 10.915 3 2.299 M
|
||||
RDQML RCLK R 11.554 3 2.433 M
|
||||
RD[0] nCCAS F 8.539 3 1.899 M
|
||||
RD[1] nCCAS F 9.248 3 2.027 M
|
||||
RD[2] nCCAS F 9.706 3 2.118 M
|
||||
RD[3] nCCAS F 8.539 3 1.899 M
|
||||
RD[4] nCCAS F 9.228 3 2.015 M
|
||||
RD[5] nCCAS F 8.772 3 1.924 M
|
||||
RD[6] nCCAS F 8.539 3 1.899 M
|
||||
RD[7] nCCAS F 9.706 3 2.118 M
|
||||
UFMCLK RCLK R 8.007 3 1.714 M
|
||||
UFMSDI RCLK R 8.007 3 1.714 M
|
||||
nRCAS RCLK R 8.209 3 1.697 M
|
||||
nRCAS RCLK R 8.120 3 1.681 M
|
||||
nRCS RCLK R 6.854 3 1.431 M
|
||||
nRRAS RCLK R 8.021 3 1.650 M
|
||||
nRRAS RCLK R 8.089 3 1.669 M
|
||||
nRWE RCLK R 6.854 3 1.431 M
|
||||
nUFMCS RCLK R 9.650 3 2.046 M
|
||||
nUFMCS RCLK R 8.732 3 1.846 M
|
||||
WARNING: you must also run trce with hold speed: 3
|
||||
WARNING: you must also run trce with setup speed: M
|
||||
|
||||
|
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
@ -23,17 +23,17 @@ Target Vendor: LATTICE
|
|||
Target Device: LCMXO256CTQFP100
|
||||
Target Performance: 3
|
||||
Mapper: mj5g00, version: Diamond (64-bit) 3.12.1.454
|
||||
Mapped on: 09/21/23 05:38:29
|
||||
Mapped on: 01/06/24 06:24:57
|
||||
|
||||
|
||||
<A name="mrp_ds"></A><B><U><big>Design Summary</big></U></B>
|
||||
Number of PFU registers: 92 out of 256 (36%)
|
||||
Number of SLICEs: 69 out of 128 (54%)
|
||||
SLICEs as Logic/ROM: 69 out of 128 (54%)
|
||||
Number of SLICEs: 76 out of 128 (59%)
|
||||
SLICEs as Logic/ROM: 76 out of 128 (59%)
|
||||
SLICEs as RAM: 0 out of 64 (0%)
|
||||
SLICEs as Carry: 9 out of 128 (7%)
|
||||
Number of LUT4s: 137 out of 256 (54%)
|
||||
Number used as logic LUTs: 119
|
||||
Number of LUT4s: 151 out of 256 (59%)
|
||||
Number used as logic LUTs: 133
|
||||
Number used as distributed RAM: 0
|
||||
Number used as ripple logic: 18
|
||||
Number used as shift registers: 0
|
||||
|
@ -56,28 +56,29 @@ Mapped on: 09/21/23 05:38:29
|
|||
Net nCCAS_c: 4 loads, 0 rising, 4 falling (Driver: PIO nCCAS )
|
||||
Number of Clock Enables: 5
|
||||
Net XOR8MEG18: 3 loads, 3 LSLICEs
|
||||
Net N_31: 1 loads, 1 LSLICEs
|
||||
Net N_33: 1 loads, 1 LSLICEs
|
||||
Net N_159_i: 2 loads, 2 LSLICEs
|
||||
Net N_24: 1 loads, 1 LSLICEs
|
||||
Net N_26: 1 loads, 1 LSLICEs
|
||||
Net N_153_i: 2 loads, 2 LSLICEs
|
||||
Net CmdUFMCLK_1_sqmuxa: 2 loads, 2 LSLICEs
|
||||
Number of LSRs: 4
|
||||
Number of LSRs: 5
|
||||
Net RA10s_i: 1 loads, 1 LSLICEs
|
||||
Net nRRAS_0_sqmuxa: 1 loads, 1 LSLICEs
|
||||
Net RASr2: 2 loads, 2 LSLICEs
|
||||
Net RASr2: 1 loads, 1 LSLICEs
|
||||
Net Ready_fast: 7 loads, 7 LSLICEs
|
||||
Net RCKEEN_8_u_0_1_a1_0: 1 loads, 1 LSLICEs
|
||||
Number of nets driven by tri-state buffers: 0
|
||||
Top 10 highest fanout non-clock nets:
|
||||
|
||||
Net InitReady: 16 loads
|
||||
Net Ready: 16 loads
|
||||
Net S[1]: 13 loads
|
||||
Net CO0: 12 loads
|
||||
Top 10 highest fanout non-clock nets:
|
||||
Net Ready: 18 loads
|
||||
Net InitReady: 17 loads
|
||||
Net S[1]: 17 loads
|
||||
Net CO0: 16 loads
|
||||
Net RASr2: 13 loads
|
||||
Net nRowColSel: 12 loads
|
||||
Net RASr2: 11 loads
|
||||
Net Din_c[5]: 10 loads
|
||||
Net Din_c[3]: 9 loads
|
||||
Net IS[0]: 9 loads
|
||||
Net MAin_c[1]: 8 loads
|
||||
Net IS[1]: 8 loads
|
||||
|
||||
|
||||
|
||||
|
@ -126,8 +127,8 @@ Mapped on: 09/21/23 05:38:29
|
|||
| nRWE | OUTPUT | LVCMOS33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| RCKE | OUTPUT | LVCMOS33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| RCLK | INPUT | LVCMOS33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| nRCS | OUTPUT | LVCMOS33 | | |
|
||||
|
@ -183,8 +184,8 @@ Mapped on: 09/21/23 05:38:29
|
|||
| nCCAS | INPUT | LVCMOS33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| Dout[7] | OUTPUT | LVCMOS33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| Dout[6] | OUTPUT | LVCMOS33 | | |
|
||||
+---------------------+-----------+-----------+------------+------------+
|
||||
| Dout[5] | OUTPUT | LVCMOS33 | | |
|
||||
|
@ -243,7 +244,6 @@ Mapped on: 09/21/23 05:38:29
|
|||
|
||||
|
||||
|
||||
|
||||
<A name="mrp_rm"></A><B><U><big>Removed logic</big></U></B>
|
||||
|
||||
Block GSR_INST undriven or does not drive anything - clipped.
|
||||
|
@ -252,7 +252,6 @@ Signal nFWE_c_i was merged into signal nFWE_c
|
|||
Signal nCRAS_c_i_0 was merged into signal nCRAS_c
|
||||
Signal nCCAS_c_i was merged into signal nCCAS_c
|
||||
Signal Ready_fast_i was merged into signal Ready_fast
|
||||
Signal IS_i[0] was merged into signal IS[0]
|
||||
Signal RASr2_i was merged into signal RASr2
|
||||
Signal XOR8MEG.CN was merged into signal PHI2_c
|
||||
Signal GND undriven or does not drive anything - clipped.
|
||||
|
@ -272,8 +271,7 @@ Block nFWE_pad_RNI420B was optimized away.
|
|||
Block RASr_RNO was optimized away.
|
||||
Block nCCAS_pad_RNISUR8 was optimized away.
|
||||
Block Ready_fast_RNI29NA was optimized away.
|
||||
Block IS_i[0] was optimized away.
|
||||
Block RASr2_RNIAFR1 was optimized away.
|
||||
Block S_RNO[1] was optimized away.
|
||||
Block XOR8MEG.CN was optimized away.
|
||||
Block GND was optimized away.
|
||||
Block VCC was optimized away.
|
||||
|
@ -304,6 +302,8 @@ Block VCC was optimized away.
|
|||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
|
|
|
@ -14,7 +14,7 @@ Performance Grade: 3
|
|||
PACKAGE: TQFP100
|
||||
Package Status: Final Version 1.19
|
||||
|
||||
Thu Sep 21 05:38:42 2023
|
||||
Sat Jan 06 06:25:11 2024
|
||||
|
||||
Pinout by Port Name:
|
||||
+-----------+----------+---------------+------+----------------------------------+
|
||||
|
@ -276,7 +276,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Thu Sep 21 05:38:42 2023
|
||||
Sat Jan 06 06:25:11 2024
|
||||
|
||||
|
||||
|
||||
|
|
|
@ -12,7 +12,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
||||
Thu Sep 21 05:38:31 2023
|
||||
Sat Jan 06 06:25:01 2024
|
||||
|
||||
C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2GS_LCMXO256C_impl1.p2t
|
||||
RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.dir
|
||||
|
@ -26,17 +26,17 @@ Preference file: RAM2GS_LCMXO256C_impl1.prf.
|
|||
Level/ Number Worst Timing Worst Timing Run NCD
|
||||
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
|
||||
---------- -------- ----- ------ ----------- ----------- ---- ------
|
||||
5_1 * 0 8.213 0 0.273 0 12 Completed
|
||||
5_1 * 0 6.770 0 0.273 0 11 Completed
|
||||
* : Design saved.
|
||||
|
||||
Total (real) run time for 1-seed: 12 secs
|
||||
Total (real) run time for 1-seed: 11 secs
|
||||
|
||||
par done!
|
||||
|
||||
Note: user must run 'Trace' for timing closure signoff.
|
||||
|
||||
Lattice Place and Route Report for Design "RAM2GS_LCMXO256C_impl1_map.ncd"
|
||||
Thu Sep 21 05:38:31 2023
|
||||
Sat Jan 06 06:25:01 2024
|
||||
|
||||
|
||||
<A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
|
||||
|
@ -65,12 +65,12 @@ Ignore Preference Error(s): True
|
|||
|
||||
PIO (prelim) 67/79 84% used
|
||||
67/78 85% bonded
|
||||
SLICE 69/128 53% used
|
||||
SLICE 76/128 59% used
|
||||
|
||||
|
||||
|
||||
Number of Signals: 251
|
||||
Number of Connections: 633
|
||||
Number of Signals: 266
|
||||
Number of Connections: 681
|
||||
|
||||
Pin Constraint Summary:
|
||||
67 out of 67 pins locked (100% locked).
|
||||
|
@ -84,17 +84,17 @@ The following 1 signal is selected to use the secondary clock routing resources:
|
|||
|
||||
No signal is selected as Global Set/Reset.
|
||||
Starting Placer Phase 0.
|
||||
........
|
||||
......
|
||||
Finished Placer Phase 0. REAL time: 0 secs
|
||||
|
||||
Starting Placer Phase 1.
|
||||
.................
|
||||
Placer score = 582801.
|
||||
Finished Placer Phase 1. REAL time: 10 secs
|
||||
Placer score = 783987.
|
||||
Finished Placer Phase 1. REAL time: 9 secs
|
||||
|
||||
Starting Placer Phase 2.
|
||||
.
|
||||
Placer score = 582334
|
||||
Placer score = 783552
|
||||
Finished Placer Phase 2. REAL time: 10 secs
|
||||
|
||||
|
||||
|
@ -134,7 +134,7 @@ Total placer CPU time: 9 secs
|
|||
|
||||
Dumping design to file RAM2GS_LCMXO256C_impl1.dir/5_1.ncd.
|
||||
|
||||
0 connections routed; 633 unrouted.
|
||||
0 connections routed; 681 unrouted.
|
||||
Starting router resource preassignment
|
||||
WARNING - par: The driver of primary clock net PHI2_c is not placed on one of the PIO sites dedicated for primary clocks. This primary clock will be routed to a H-spine through general routing resource and may suffer from excessive delay or skew.
|
||||
WARNING - par: The driver of secondary clock net nCRAS_c is not placed on one of the PIO sites dedicated for secondary clocks. This secondary clock will be routed through general routing resource and may suffer from excessive delay or skew.
|
||||
|
@ -142,9 +142,9 @@ WARNING - par: The driver of secondary clock net nCRAS_c is not placed on one of
|
|||
WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
|
||||
Signal=nCCAS_c loads=8 clock_loads=4
|
||||
|
||||
Completed router resource preassignment. Real time: 11 secs
|
||||
Completed router resource preassignment. Real time: 10 secs
|
||||
|
||||
Start NBR router at 05:38:42 09/21/23
|
||||
Start NBR router at 06:25:11 01/06/24
|
||||
|
||||
*****************************************************************
|
||||
Info: NBR allows conflicts(one node used by more than one signal)
|
||||
|
@ -159,41 +159,44 @@ Note: NBR uses a different method to calculate timing slacks. The
|
|||
your design.
|
||||
*****************************************************************
|
||||
|
||||
Start NBR special constraint process at 05:38:42 09/21/23
|
||||
Start NBR special constraint process at 06:25:11 01/06/24
|
||||
|
||||
Start NBR section for initial routing at 05:38:42 09/21/23
|
||||
Start NBR section for initial routing at 06:25:11 01/06/24
|
||||
Level 1, iteration 1
|
||||
0(0.00%) conflict; 545(86.10%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 8.344ns/0.000ns; real time: 11 secs
|
||||
0(0.00%) conflict; 593(87.08%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 7.904ns/0.000ns; real time: 10 secs
|
||||
Level 2, iteration 1
|
||||
0(0.00%) conflict; 543(85.78%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 8.344ns/0.000ns; real time: 11 secs
|
||||
0(0.00%) conflict; 592(86.93%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 8.083ns/0.000ns; real time: 10 secs
|
||||
Level 3, iteration 1
|
||||
0(0.00%) conflict; 543(85.78%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 8.405ns/0.000ns; real time: 11 secs
|
||||
0(0.00%) conflict; 591(86.78%) untouched conns; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 7.994ns/0.000ns; real time: 10 secs
|
||||
Level 4, iteration 1
|
||||
10(0.08%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 8.213ns/0.000ns; real time: 11 secs
|
||||
13(0.11%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 7.278ns/0.000ns; real time: 10 secs
|
||||
|
||||
Info: Initial congestion level at 75% usage is 0
|
||||
Info: Initial congestion area at 75% usage is 0 (0.00%)
|
||||
|
||||
Start NBR section for normal routing at 05:38:42 09/21/23
|
||||
Start NBR section for normal routing at 06:25:11 01/06/24
|
||||
Level 4, iteration 1
|
||||
5(0.04%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 8.213ns/0.000ns; real time: 11 secs
|
||||
7(0.06%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 6.770ns/0.000ns; real time: 10 secs
|
||||
Level 4, iteration 2
|
||||
4(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 6.770ns/0.000ns; real time: 10 secs
|
||||
Level 4, iteration 3
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 8.213ns/0.000ns; real time: 11 secs
|
||||
Estimated worst slack/total negative slack<setup>: 6.770ns/0.000ns; real time: 10 secs
|
||||
|
||||
Start NBR section for setup/hold timing optimization with effort level 3 at 05:38:42 09/21/23
|
||||
Start NBR section for setup/hold timing optimization with effort level 3 at 06:25:11 01/06/24
|
||||
|
||||
Start NBR section for re-routing at 05:38:42 09/21/23
|
||||
Start NBR section for re-routing at 06:25:11 01/06/24
|
||||
Level 4, iteration 1
|
||||
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
|
||||
Estimated worst slack/total negative slack<setup>: 8.213ns/0.000ns; real time: 11 secs
|
||||
Estimated worst slack/total negative slack<setup>: 6.770ns/0.000ns; real time: 10 secs
|
||||
|
||||
Start NBR section for post-routing at 05:38:42 09/21/23
|
||||
Start NBR section for post-routing at 06:25:11 01/06/24
|
||||
|
||||
End NBR router with 0 unrouted connection
|
||||
|
||||
|
@ -201,7 +204,7 @@ NBR Summary
|
|||
-----------
|
||||
Number of unrouted connections : 0 (0.00%)
|
||||
Number of connections with timing violations : 0 (0.00%)
|
||||
Estimated worst slack<setup> : 8.213ns
|
||||
Estimated worst slack<setup> : 6.770ns
|
||||
Timing score<setup> : 0
|
||||
-----------
|
||||
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
|
||||
|
@ -212,9 +215,9 @@ WARNING - par: The following clock signals will be routed by using generic routi
|
|||
Signal=nCCAS_c loads=8 clock_loads=4
|
||||
|
||||
Total CPU time 10 secs
|
||||
Total REAL time: 12 secs
|
||||
Total REAL time: 11 secs
|
||||
Completely routed.
|
||||
End of route. 633 routed (100.00%); 0 unrouted.
|
||||
End of route. 681 routed (100.00%); 0 unrouted.
|
||||
|
||||
Hold time timing score: 0, hold timing errors: 0
|
||||
|
||||
|
@ -228,14 +231,14 @@ All signals are completely routed.
|
|||
|
||||
PAR_SUMMARY::Run status = Completed
|
||||
PAR_SUMMARY::Number of unrouted conns = 0
|
||||
PAR_SUMMARY::Worst slack<setup/<ns>> = 8.213
|
||||
PAR_SUMMARY::Worst slack<setup/<ns>> = 6.770
|
||||
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
|
||||
PAR_SUMMARY::Worst slack<hold /<ns>> = 0.273
|
||||
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
|
||||
PAR_SUMMARY::Number of errors = 0
|
||||
|
||||
Total CPU time to completion: 10 secs
|
||||
Total REAL time to completion: 12 secs
|
||||
Total REAL time to completion: 11 secs
|
||||
|
||||
par done!
|
||||
|
||||
|
|
|
@ -13,7 +13,7 @@ Hostname: ZANEMACWIN11
|
|||
|
||||
Implementation : impl1
|
||||
|
||||
# Written on Thu Sep 21 05:38:19 2023
|
||||
# Written on Sat Jan 6 06:24:50 2024
|
||||
|
||||
##### FILES SYNTAX CHECKED ##############################################
|
||||
Constraint File(s): "\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS.sdc"
|
||||
|
|
|
@ -62,7 +62,7 @@
|
|||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Updated:</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2023/09/21 05:38:51</SPAN></TD>
|
||||
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2024/01/06 06:25:20</SPAN></TD>
|
||||
</TR>
|
||||
<TR>
|
||||
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Location:</SPAN></TD>
|
||||
|
|
|
@ -12,7 +12,7 @@
|
|||
#OS: Windows 8 6.2
|
||||
#Hostname: ZANEMACWIN11
|
||||
|
||||
# Thu Sep 21 05:38:16 2023
|
||||
# Sat Jan 6 06:24:47 2024
|
||||
|
||||
#Implementation: impl1
|
||||
|
||||
|
@ -59,19 +59,22 @@ Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 202
|
|||
@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
|
||||
@I::"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-SPI.v" (library work)
|
||||
Verilog syntax check successful!
|
||||
|
||||
Compiler output is up to date. No re-compile necessary
|
||||
|
||||
Selecting top level module RAM2GS
|
||||
@N: CG364 :"\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS-SPI.v":1:7:1:12|Synthesizing module RAM2GS in library work.
|
||||
Running optimization stage 1 on RAM2GS .......
|
||||
Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 100MB)
|
||||
Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 100MB)
|
||||
Running optimization stage 2 on RAM2GS .......
|
||||
Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB)
|
||||
|
||||
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)
|
||||
At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 96MB peak: 97MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:38:17 2023
|
||||
# Sat Jan 6 06:24:47 2024
|
||||
|
||||
###########################################################]
|
||||
###########################################################[
|
||||
|
@ -98,7 +101,7 @@ At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s;
|
|||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:38:17 2023
|
||||
# Sat Jan 6 06:24:48 2024
|
||||
|
||||
###########################################################]
|
||||
|
||||
|
@ -113,7 +116,7 @@ At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory
|
|||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:38:17 2023
|
||||
# Sat Jan 6 06:24:48 2024
|
||||
|
||||
###########################################################]
|
||||
###########################################################[
|
||||
|
@ -134,18 +137,17 @@ Implementation : impl1
|
|||
Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
|
||||
|
||||
@N|Running in 64-bit mode
|
||||
File \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_comp.srs changed - recompiling
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
|
||||
Process completed successfully.
|
||||
# Thu Sep 21 05:38:18 2023
|
||||
# Sat Jan 6 06:24:49 2024
|
||||
|
||||
###########################################################]
|
||||
Premap Report
|
||||
|
||||
# Thu Sep 21 05:38:19 2023
|
||||
# Sat Jan 6 06:24:49 2024
|
||||
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
|
@ -167,7 +169,7 @@ Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built
|
|||
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
|
||||
|
||||
|
||||
Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 140MB)
|
||||
Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 140MB)
|
||||
|
||||
Reading constraint file: \\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS.sdc
|
||||
@L: \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1_scck.rpt
|
||||
|
@ -195,7 +197,6 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h
|
|||
@N: FX493 |Applying initial value "0" on instance CmdLEDEN.
|
||||
@N: FX493 |Applying initial value "0" on instance Cmdn8MEGEN.
|
||||
@N: FX493 |Applying initial value "1" on instance nRCS.
|
||||
@N: FX493 |Applying initial value "0" on instance LEDEN.
|
||||
@N: FX493 |Applying initial value "0" on instance n8MEGEN.
|
||||
@N: FX493 |Applying initial value "1" on instance nRRAS.
|
||||
@N: FX493 |Applying initial value "0" on instance CmdUFMCLK.
|
||||
|
@ -214,17 +215,17 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h
|
|||
Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
|
||||
|
||||
|
||||
Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
|
||||
Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
|
||||
|
||||
|
||||
Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
|
||||
Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
|
||||
|
||||
|
||||
Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
|
||||
Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
|
||||
|
||||
@N: FX1184 |Applying syn_allowed_resources blockrams=0 on top level netlist RAM2GS
|
||||
|
||||
Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 181MB peak: 181MB)
|
||||
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
|
||||
|
||||
|
||||
|
||||
|
@ -291,10 +292,10 @@ Clock Tree ID Driving Element Drive Element Type Fanout Sample I
|
|||
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
|
||||
Finished Pre Mapping Phase.
|
||||
|
||||
Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
|
||||
Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
|
||||
|
||||
|
||||
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
|
||||
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
|
||||
|
||||
|
||||
Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
|
||||
|
@ -303,13 +304,11 @@ Pre-mapping successful!
|
|||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 98MB peak: 184MB)
|
||||
|
||||
Process took 0h:00m:02s realtime, 0h:00m:01s cputime
|
||||
# Thu Sep 21 05:38:21 2023
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Sat Jan 6 06:24:51 2024
|
||||
|
||||
###########################################################]
|
||||
Map & Optimize Report
|
||||
|
||||
# Thu Sep 21 05:38:21 2023
|
||||
# Sat Jan 6 06:24:51 2024
|
||||
|
||||
|
||||
Copyright (C) 1994-2021 Synopsys, Inc.
|
||||
|
@ -328,29 +327,29 @@ Implementation : impl1
|
|||
Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @
|
||||
|
||||
|
||||
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
|
||||
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
|
||||
|
||||
@N: MF916 |Option synthesis_strategy=base is enabled.
|
||||
@N: MF248 |Running in 64-bit mode.
|
||||
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
|
||||
|
||||
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 140MB)
|
||||
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 139MB)
|
||||
|
||||
|
||||
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 140MB)
|
||||
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 139MB)
|
||||
|
||||
|
||||
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB)
|
||||
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
|
||||
|
||||
|
||||
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB)
|
||||
|
||||
|
||||
|
||||
Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 179MB peak: 179MB)
|
||||
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 178MB peak: 178MB)
|
||||
|
||||
|
||||
Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
|
||||
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
|
||||
|
||||
@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":147:4:147:9|Found counter in view:work.RAM2GS(verilog) instance IS[3:0]
|
||||
@N: MO231 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":134:4:134:9|Found counter in view:work.RAM2GS(verilog) instance FS[17:0]
|
||||
|
@ -360,10 +359,10 @@ Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00
|
|||
@N: FX493 |Applying initial value "0" on instance IS[2].
|
||||
@N: FX493 |Applying initial value "0" on instance IS[3].
|
||||
|
||||
Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 184MB peak: 184MB)
|
||||
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 184MB peak: 184MB)
|
||||
|
||||
|
||||
Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB)
|
||||
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 185MB peak: 185MB)
|
||||
|
||||
|
||||
Available hyper_sources - for debug and ip models
|
||||
|
@ -376,64 +375,61 @@ Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CP
|
|||
Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 187MB peak: 187MB)
|
||||
|
||||
|
||||
Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
|
||||
Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
|
||||
|
||||
|
||||
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
|
||||
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
|
||||
|
||||
|
||||
Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
|
||||
Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
|
||||
|
||||
|
||||
Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
|
||||
Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
|
||||
|
||||
Pass CPU time Worst Slack Luts / Registers
|
||||
------------------------------------------------------------
|
||||
1 0h:00m:01s -3.26ns 127 / 89
|
||||
2 0h:00m:01s -3.23ns 123 / 89
|
||||
3 0h:00m:01s -3.23ns 123 / 89
|
||||
4 0h:00m:01s -3.23ns 123 / 89
|
||||
5 0h:00m:01s -3.23ns 124 / 89
|
||||
6 0h:00m:01s -3.23ns 124 / 89
|
||||
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":105:4:105:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 7 loads 1 time to improve timing.
|
||||
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":105:4:105:9|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 5 loads 1 time to improve timing.
|
||||
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":147:4:147:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 15 loads 1 time to improve timing.
|
||||
1 0h:00m:01s -4.01ns 133 / 89
|
||||
2 0h:00m:01s -3.96ns 131 / 89
|
||||
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":105:4:105:9|Replicating instance CBR (in view: work.RAM2GS(verilog)) with 8 loads 1 time to improve timing.
|
||||
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":105:4:105:9|Replicating instance FWEr (in view: work.RAM2GS(verilog)) with 7 loads 1 time to improve timing.
|
||||
@N: FX271 :"\\mac\icloud\repos\ram2gs\cpld\ram2gs-spi.v":147:4:147:9|Replicating instance Ready (in view: work.RAM2GS(verilog)) with 19 loads 1 time to improve timing.
|
||||
Timing driven replication report
|
||||
Added 3 Registers via timing driven replication
|
||||
Added 1 LUTs via timing driven replication
|
||||
|
||||
7 0h:00m:02s -2.99ns 128 / 92
|
||||
3 0h:00m:02s -3.08ns 143 / 92
|
||||
4 0h:00m:02s -3.08ns 141 / 92
|
||||
|
||||
|
||||
8 0h:00m:02s -2.99ns 127 / 92
|
||||
9 0h:00m:02s -3.09ns 127 / 92
|
||||
10 0h:00m:02s -3.19ns 127 / 92
|
||||
11 0h:00m:02s -3.19ns 127 / 92
|
||||
12 0h:00m:02s -3.19ns 127 / 92
|
||||
5 0h:00m:02s -3.08ns 140 / 92
|
||||
6 0h:00m:02s -3.19ns 140 / 92
|
||||
7 0h:00m:02s -3.19ns 140 / 92
|
||||
8 0h:00m:02s -3.19ns 140 / 92
|
||||
9 0h:00m:02s -3.19ns 140 / 92
|
||||
|
||||
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 190MB peak: 190MB)
|
||||
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 191MB peak: 191MB)
|
||||
|
||||
|
||||
Finished restoring hierarchy (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 191MB peak: 191MB)
|
||||
Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 191MB peak: 191MB)
|
||||
|
||||
|
||||
Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 155MB peak: 191MB)
|
||||
Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 155MB peak: 192MB)
|
||||
|
||||
Writing Analyst data base \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO256C\impl1\synwork\RAM2GS_LCMXO256C_impl1_m.srm
|
||||
|
||||
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 192MB peak: 192MB)
|
||||
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 192MB)
|
||||
|
||||
Writing EDIF Netlist and constraint files
|
||||
@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2GS\CPLD\LCMXO256C\impl1\RAM2GS_LCMXO256C_impl1.edi
|
||||
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
|
||||
|
||||
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 196MB peak: 196MB)
|
||||
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 196MB peak: 196MB)
|
||||
|
||||
|
||||
Finished Writing Netlists (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 196MB peak: 196MB)
|
||||
Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 196MB peak: 197MB)
|
||||
|
||||
|
||||
Start final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 194MB peak: 196MB)
|
||||
Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 195MB peak: 197MB)
|
||||
|
||||
@N: MT615 |Found clock RCLK with period 16.00ns
|
||||
@N: MT615 |Found clock PHI2 with period 350.00ns
|
||||
|
@ -442,7 +438,7 @@ Start final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:0
|
|||
|
||||
|
||||
##### START OF TIMING REPORT #####[
|
||||
# Timing report written on Thu Sep 21 05:38:27 2023
|
||||
# Timing report written on Sat Jan 6 06:24:55 2024
|
||||
#
|
||||
|
||||
|
||||
|
@ -475,8 +471,8 @@ nCRAS 2.9 MHz 0.6 MHz 350.000 1613.150 -3.60
|
|||
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
|
||||
|
||||
|
||||
@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.
|
||||
@W: MT117 |Paths from clock (RCLK:r) to clock (PHI2:f) are overconstrained because the required time of 1.00 ns is too small.
|
||||
@W: MT118 |Paths from clock (PHI2:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.
|
||||
@W: MT118 |Paths from clock (nCRAS:f) to clock (RCLK:r) are overconstrained because the required time of 1.00 ns is too small.
|
||||
@W: MT116 |Paths from clock (RCLK:r) to clock (PHI2:r) are overconstrained because the required time of 2.00 ns is too small.
|
||||
@W: MT117 |Paths from clock (RCLK:r) to clock (nCRAS:f) are overconstrained because the required time of 1.00 ns is too small.
|
||||
|
@ -490,10 +486,10 @@ Clocks | rise to rise | fall to fall | rise to
|
|||
---------------------------------------------------------------------------------------------------------------
|
||||
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
|
||||
---------------------------------------------------------------------------------------------------------------
|
||||
RCLK RCLK | 16.000 7.560 | No paths - | No paths - | No paths -
|
||||
RCLK RCLK | 16.000 7.464 | No paths - | No paths - | No paths -
|
||||
RCLK PHI2 | 2.000 -1.216 | No paths - | 1.000 -2.312 | No paths -
|
||||
PHI2 RCLK | No paths - | No paths - | No paths - | 1.000 -3.705
|
||||
PHI2 PHI2 | No paths - | 350.000 343.998 | 175.000 166.500 | 175.000 171.784
|
||||
PHI2 PHI2 | No paths - | 350.000 344.094 | 175.000 165.215 | 175.000 171.784
|
||||
nCRAS RCLK | No paths - | No paths - | No paths - | 1.000 -3.609
|
||||
===============================================================================================================
|
||||
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
|
||||
|
@ -527,10 +523,10 @@ CmdUFMCS PHI2 FD1P3AX Q CmdUFMCS 1.348
|
|||
CmdUFMSDI PHI2 FD1P3AX Q CmdUFMSDI 1.348 -3.297
|
||||
CmdLEDEN PHI2 FD1P3AX Q CmdLEDEN 1.456 -2.216
|
||||
Cmdn8MEGEN PHI2 FD1P3AX Q Cmdn8MEGEN 1.456 -2.216
|
||||
Bank[2] PHI2 FD1S3AX Q Bank[2] 1.348 166.500
|
||||
Bank[3] PHI2 FD1S3AX Q Bank[3] 1.348 166.500
|
||||
Bank[4] PHI2 FD1S3AX Q Bank[4] 1.348 166.500
|
||||
Bank[5] PHI2 FD1S3AX Q Bank[5] 1.348 166.500
|
||||
Bank[0] PHI2 FD1S3AX Q Bank[0] 1.348 165.215
|
||||
Bank[1] PHI2 FD1S3AX Q Bank[1] 1.348 165.215
|
||||
Bank[2] PHI2 FD1S3AX Q Bank[2] 1.348 165.215
|
||||
Bank[3] PHI2 FD1S3AX Q Bank[3] 1.348 165.215
|
||||
=======================================================================================
|
||||
|
||||
|
||||
|
@ -544,13 +540,13 @@ Instance Reference Type Pin Net Time
|
|||
UFMCLK PHI2 FD1S3AX D UFMCLK_RNO -0.003 -3.705
|
||||
UFMSDI PHI2 FD1S3AX D UFMSDI_RNO -0.003 -3.705
|
||||
nUFMCS PHI2 FD1S3AY D nUFMCS_s_0_N_5_i -0.003 -3.705
|
||||
LEDEN PHI2 FD1P3AX SP N_33 0.806 -2.800
|
||||
n8MEGEN PHI2 FD1P3AX SP N_31 0.806 -2.800
|
||||
LEDEN PHI2 FD1P3AX D N_70 -0.003 -2.216
|
||||
n8MEGEN PHI2 FD1P3AX D N_69 -0.003 -2.216
|
||||
CmdSubmitted PHI2 FD1S3AX D N_460_0 173.997 166.500
|
||||
ADSubmitted PHI2 FD1S3AX D ADSubmitted_r 173.997 167.797
|
||||
C1Submitted PHI2 FD1S3AX D C1Submitted_RNO 173.997 167.797
|
||||
LEDEN PHI2 FD1P3AX SP N_26 0.806 -2.800
|
||||
n8MEGEN PHI2 FD1P3AX SP N_24 0.806 -2.800
|
||||
LEDEN PHI2 FD1P3AX D N_49 -0.003 -2.216
|
||||
n8MEGEN PHI2 FD1P3AX D N_48 -0.003 -2.216
|
||||
CmdEnable PHI2 FD1S3AX D CmdEnable_s 173.997 165.215
|
||||
CmdSubmitted PHI2 FD1S3AX D N_428_0 173.997 165.311
|
||||
ADSubmitted PHI2 FD1S3AX D ADSubmitted_r 173.997 166.404
|
||||
============================================================================================
|
||||
|
||||
|
||||
|
@ -582,7 +578,7 @@ CmdSubmitted FD1S3AX Q Out 1.552 1.552 r -
|
|||
CmdSubmitted Net - - - - 3
|
||||
PHI2r3_RNITCN41 ORCALUT4 A In 0.000 1.552 r -
|
||||
PHI2r3_RNITCN41 ORCALUT4 Z Out 1.393 2.945 r -
|
||||
N_139_i Net - - - - 3
|
||||
N_137_i Net - - - - 3
|
||||
UFMCLK_RNO ORCALUT4 A In 0.000 2.945 r -
|
||||
UFMCLK_RNO ORCALUT4 Z Out 0.757 3.702 r -
|
||||
UFMCLK_RNO Net - - - - 1
|
||||
|
@ -613,7 +609,7 @@ CmdSubmitted FD1S3AX Q Out 1.552 1.552 r -
|
|||
CmdSubmitted Net - - - - 3
|
||||
PHI2r3_RNITCN41 ORCALUT4 A In 0.000 1.552 r -
|
||||
PHI2r3_RNITCN41 ORCALUT4 Z Out 1.393 2.945 r -
|
||||
N_139_i Net - - - - 3
|
||||
N_137_i Net - - - - 3
|
||||
nUFMCS_s_0_N_5_i ORCALUT4 A In 0.000 2.945 r -
|
||||
nUFMCS_s_0_N_5_i ORCALUT4 Z Out 0.757 3.702 r -
|
||||
nUFMCS_s_0_N_5_i Net - - - - 1
|
||||
|
@ -644,7 +640,7 @@ CmdSubmitted FD1S3AX Q Out 1.552 1.552 r -
|
|||
CmdSubmitted Net - - - - 3
|
||||
PHI2r3_RNITCN41 ORCALUT4 A In 0.000 1.552 r -
|
||||
PHI2r3_RNITCN41 ORCALUT4 Z Out 1.393 2.945 r -
|
||||
N_139_i Net - - - - 3
|
||||
N_137_i Net - - - - 3
|
||||
UFMSDI_RNO ORCALUT4 A In 0.000 2.945 r -
|
||||
UFMSDI_RNO ORCALUT4 Z Out 0.757 3.702 r -
|
||||
UFMSDI_RNO Net - - - - 1
|
||||
|
@ -663,21 +659,21 @@ Detailed Report for Clock: RCLK
|
|||
Starting Points with Worst Slack
|
||||
********************************
|
||||
|
||||
Starting Arrival
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
-----------------------------------------------------------------------------
|
||||
LEDEN RCLK FD1P3AX Q LEDEN 1.552 -2.312
|
||||
n8MEGEN RCLK FD1P3AX Q n8MEGEN 1.456 -2.216
|
||||
FS[13] RCLK FD1S3AX Q FS[13] 1.552 7.560
|
||||
FS[14] RCLK FD1S3AX Q FS[14] 1.552 7.560
|
||||
FS[15] RCLK FD1S3AX Q FS[15] 1.552 7.560
|
||||
FS[17] RCLK FD1S3AX Q FS[17] 1.552 7.560
|
||||
S[1] RCLK FD1S3IX Q S[1] 1.768 8.533
|
||||
S[0] RCLK FD1S3IX Q CO0 1.756 8.545
|
||||
FS[16] RCLK FD1S3AX Q FS[16] 1.612 8.689
|
||||
FS[12] RCLK FD1S3AX Q FS[12] 1.552 8.749
|
||||
=============================================================================
|
||||
Starting Arrival
|
||||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
--------------------------------------------------------------------------------
|
||||
LEDEN RCLK FD1P3AX Q LEDEN 1.552 -2.312
|
||||
n8MEGEN RCLK FD1P3AX Q n8MEGEN 1.456 -2.216
|
||||
FS[12] RCLK FD1S3AX Q FS[12] 1.552 7.464
|
||||
FS[14] RCLK FD1S3AX Q FS[14] 1.552 7.464
|
||||
FS[15] RCLK FD1S3AX Q FS[15] 1.552 7.464
|
||||
FS[17] RCLK FD1S3AX Q FS[17] 1.552 7.464
|
||||
InitReady RCLK FD1S3AX Q InitReady 1.792 8.569
|
||||
S[1] RCLK FD1S3IX Q S[1] 1.792 8.569
|
||||
S[0] RCLK FD1S3IX Q CO0 1.780 8.581
|
||||
FS[13] RCLK FD1S3AX Q FS[13] 1.612 8.593
|
||||
================================================================================
|
||||
|
||||
|
||||
Ending Points with Worst Slack
|
||||
|
@ -687,16 +683,16 @@ Ending Points with Worst Slack
|
|||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
-----------------------------------------------------------------------------------------
|
||||
CmdLEDEN RCLK FD1P3AX D N_21_i -0.003 -2.312
|
||||
CmdLEDEN RCLK FD1P3AX D N_14_i -0.003 -2.312
|
||||
XOR8MEG RCLK FD1P3AX D XOR8MEG_3 -0.003 -2.312
|
||||
Cmdn8MEGEN RCLK FD1P3AX D N_19_i -0.003 -2.216
|
||||
Cmdn8MEGEN RCLK FD1P3AX D N_12_i -0.003 -2.216
|
||||
RA11 RCLK FD1S3IX D RA11_2 0.997 -1.216
|
||||
UFMSDI RCLK FD1S3AX D UFMSDI_RNO 14.997 7.560
|
||||
UFMSDI RCLK FD1S3AX D UFMSDI_RNO 14.997 7.464
|
||||
UFMCLK RCLK FD1S3AX D UFMCLK_RNO 14.997 7.668
|
||||
LEDEN RCLK FD1P3AX SP N_33 15.806 8.261
|
||||
n8MEGEN RCLK FD1P3AX SP N_31 15.806 8.261
|
||||
nRCS RCLK FD1S3AY D N_28_i 14.997 8.533
|
||||
nRCAS RCLK FD1S3AY D N_46_i 14.997 8.569
|
||||
nUFMCS RCLK FD1S3AY D nUFMCS_s_0_N_5_i 14.997 8.653
|
||||
nRCS RCLK FD1S3AY D N_143_i 14.997 8.881
|
||||
LEDEN RCLK FD1P3AX SP N_26 15.806 9.463
|
||||
=========================================================================================
|
||||
|
||||
|
||||
|
@ -726,9 +722,9 @@ Name Type Name Dir Delay Time Fan Out(s
|
|||
---------------------------------------------------------------------------------
|
||||
LEDEN FD1P3AX Q Out 1.552 1.552 r -
|
||||
LEDEN Net - - - - 3
|
||||
CmdLEDEN_RNO ORCALUT4 A In 0.000 1.552 r -
|
||||
CmdLEDEN_RNO ORCALUT4 B In 0.000 1.552 r -
|
||||
CmdLEDEN_RNO ORCALUT4 Z Out 0.757 2.309 r -
|
||||
N_21_i Net - - - - 1
|
||||
N_14_i Net - - - - 1
|
||||
CmdLEDEN FD1P3AX D In 0.000 2.309 r -
|
||||
=================================================================================
|
||||
|
||||
|
@ -749,16 +745,16 @@ Path information for path number 2:
|
|||
The start point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
|
||||
The end point is clocked by PHI2 [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
-------------------------------------------------------------------------------------
|
||||
LEDEN FD1P3AX Q Out 1.552 1.552 r -
|
||||
LEDEN Net - - - - 3
|
||||
XOR8MEG_3_u_0_a3_3 ORCALUT4 B In 0.000 1.552 r -
|
||||
XOR8MEG_3_u_0_a3_3 ORCALUT4 Z Out 0.757 2.309 f -
|
||||
XOR8MEG_3 Net - - - - 1
|
||||
XOR8MEG FD1P3AX D In 0.000 2.309 f -
|
||||
=====================================================================================
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
---------------------------------------------------------------------------------------
|
||||
LEDEN FD1P3AX Q Out 1.552 1.552 r -
|
||||
LEDEN Net - - - - 3
|
||||
XOR8MEG_3_u_0_a3_0_2 ORCALUT4 B In 0.000 1.552 r -
|
||||
XOR8MEG_3_u_0_a3_0_2 ORCALUT4 Z Out 0.757 2.309 f -
|
||||
XOR8MEG_3 Net - - - - 1
|
||||
XOR8MEG FD1P3AX D In 0.000 2.309 f -
|
||||
=======================================================================================
|
||||
|
||||
|
||||
Path information for path number 3:
|
||||
|
@ -784,7 +780,7 @@ n8MEGEN FD1P3AX Q Out 1.456 1.456 r -
|
|||
n8MEGEN Net - - - - 2
|
||||
Cmdn8MEGEN_RNO ORCALUT4 C In 0.000 1.456 r -
|
||||
Cmdn8MEGEN_RNO ORCALUT4 Z Out 0.757 2.213 r -
|
||||
N_19_i Net - - - - 1
|
||||
N_12_i Net - - - - 1
|
||||
Cmdn8MEGEN FD1P3AX D In 0.000 2.213 r -
|
||||
=================================================================================
|
||||
|
||||
|
@ -804,10 +800,10 @@ Starting Points with Worst Slack
|
|||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
--------------------------------------------------------------------------------
|
||||
CBR nCRAS FD1S3AX Q CBR 1.660 -3.609
|
||||
CBR_fast nCRAS FD1S3AX Q CBR_fast 1.456 -3.513
|
||||
CBR_fast nCRAS FD1S3AX Q CBR_fast 1.552 -3.609
|
||||
CBR nCRAS FD1S3AX Q CBR 1.612 -3.561
|
||||
FWEr nCRAS FD1S3AX Q FWEr 1.552 -3.501
|
||||
FWEr_fast nCRAS FD1S3AX Q FWEr_fast 1.456 -3.405
|
||||
FWEr_fast nCRAS FD1S3AX Q FWEr_fast 1.552 -3.501
|
||||
================================================================================
|
||||
|
||||
|
||||
|
@ -818,11 +814,11 @@ Ending Points with Worst Slack
|
|||
Instance Reference Type Pin Net Time Slack
|
||||
Clock
|
||||
---------------------------------------------------------------------------------------
|
||||
nRWE nCRAS FD1S3AY D N_39_i -0.003 -3.609
|
||||
nRowColSel nCRAS FD1S3IX D nRowColSel_0_0 -0.003 -3.609
|
||||
nRCAS nCRAS FD1S3AY D N_37_i -0.003 -3.513
|
||||
RCKEEN nCRAS FD1S3AX D RCKEEN_8 -0.003 -3.405
|
||||
nRCS nCRAS FD1S3AY D N_28_i -0.003 -3.405
|
||||
nRCAS nCRAS FD1S3AY D N_46_i -0.003 -3.609
|
||||
nRWE nCRAS FD1S3AY D N_144_i -0.003 -3.609
|
||||
nRowColSel nCRAS FD1S3IX D nRowColSel_0_0 -0.003 -3.561
|
||||
RCKEEN nCRAS FD1S3AX D RCKEEN_8 -0.003 -3.501
|
||||
nRCS nCRAS FD1S3AY D N_143_i -0.003 -3.501
|
||||
=======================================================================================
|
||||
|
||||
|
||||
|
@ -842,24 +838,24 @@ Path information for path number 1:
|
|||
= Slack (non-critical) : -3.609
|
||||
|
||||
Number of logic level(s): 2
|
||||
Starting point: CBR / Q
|
||||
Ending point: nRWE / D
|
||||
Starting point: CBR_fast / Q
|
||||
Ending point: nRCAS / D
|
||||
The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
|
||||
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
---------------------------------------------------------------------------------
|
||||
CBR FD1S3AX Q Out 1.660 1.660 r -
|
||||
CBR Net - - - - 5
|
||||
nRWE_RNO_0 ORCALUT4 A In 0.000 1.660 r -
|
||||
nRWE_RNO_0 ORCALUT4 Z Out 1.189 2.849 f -
|
||||
G_17_1 Net - - - - 1
|
||||
nRWE_RNO ORCALUT4 B In 0.000 2.849 f -
|
||||
nRWE_RNO ORCALUT4 Z Out 0.757 3.606 r -
|
||||
N_39_i Net - - - - 1
|
||||
nRWE FD1S3AY D In 0.000 3.606 r -
|
||||
=================================================================================
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
----------------------------------------------------------------------------------------
|
||||
CBR_fast FD1S3AX Q Out 1.552 1.552 r -
|
||||
CBR_fast Net - - - - 3
|
||||
nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 A In 0.000 1.552 r -
|
||||
nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 Z Out 1.297 2.849 r -
|
||||
nRCAS_0_sqmuxa_1 Net - - - - 2
|
||||
nRCAS_RNO ORCALUT4 C In 0.000 2.849 r -
|
||||
nRCAS_RNO ORCALUT4 Z Out 0.757 3.606 f -
|
||||
N_46_i Net - - - - 1
|
||||
nRCAS FD1S3AY D In 0.000 3.606 f -
|
||||
========================================================================================
|
||||
|
||||
|
||||
Path information for path number 2:
|
||||
|
@ -873,24 +869,24 @@ Path information for path number 2:
|
|||
= Slack (non-critical) : -3.609
|
||||
|
||||
Number of logic level(s): 2
|
||||
Starting point: CBR / Q
|
||||
Ending point: nRowColSel / D
|
||||
Starting point: CBR_fast / Q
|
||||
Ending point: nRWE / D
|
||||
The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
|
||||
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
--------------------------------------------------------------------------------------
|
||||
CBR FD1S3AX Q Out 1.660 1.660 r -
|
||||
CBR Net - - - - 5
|
||||
nRowColSel_0_0_a3_0 ORCALUT4 B In 0.000 1.660 r -
|
||||
nRowColSel_0_0_a3_0 ORCALUT4 Z Out 1.189 2.849 f -
|
||||
N_179 Net - - - - 1
|
||||
nRowColSel_0_0 ORCALUT4 B In 0.000 2.849 f -
|
||||
nRowColSel_0_0 ORCALUT4 Z Out 0.757 3.606 f -
|
||||
nRowColSel_0_0 Net - - - - 1
|
||||
nRowColSel FD1S3IX D In 0.000 3.606 f -
|
||||
======================================================================================
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
----------------------------------------------------------------------------------------
|
||||
CBR_fast FD1S3AX Q Out 1.552 1.552 r -
|
||||
CBR_fast Net - - - - 3
|
||||
nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 A In 0.000 1.552 r -
|
||||
nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 Z Out 1.297 2.849 r -
|
||||
nRCAS_0_sqmuxa_1 Net - - - - 2
|
||||
nRWE_RNO ORCALUT4 C In 0.000 2.849 r -
|
||||
nRWE_RNO ORCALUT4 Z Out 0.757 3.606 r -
|
||||
N_144_i Net - - - - 1
|
||||
nRWE FD1S3AY D In 0.000 3.606 r -
|
||||
========================================================================================
|
||||
|
||||
|
||||
Path information for path number 3:
|
||||
|
@ -899,29 +895,29 @@ Path information for path number 3:
|
|||
+ Clock delay at ending point: 0.000 (ideal)
|
||||
= Required time: -0.003
|
||||
|
||||
- Propagation time: 3.510
|
||||
- Propagation time: 3.558
|
||||
- Clock delay at starting point: 0.000 (ideal)
|
||||
= Slack (non-critical) : -3.513
|
||||
= Slack (non-critical) : -3.561
|
||||
|
||||
Number of logic level(s): 2
|
||||
Starting point: CBR_fast / Q
|
||||
Starting point: CBR / Q
|
||||
Ending point: nRCAS / D
|
||||
The start point is clocked by nCRAS [falling] (rise=0.000 fall=175.000 period=350.000) on pin CK
|
||||
The end point is clocked by RCLK [rising] (rise=0.000 fall=8.000 period=16.000) on pin CK
|
||||
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
----------------------------------------------------------------------------------------
|
||||
CBR_fast FD1S3AX Q Out 1.456 1.456 r -
|
||||
CBR_fast Net - - - - 2
|
||||
nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 A In 0.000 1.456 r -
|
||||
nRCAS_0_sqmuxa_1_0_a3 ORCALUT4 Z Out 1.297 2.753 r -
|
||||
nRCAS_0_sqmuxa_1 Net - - - - 2
|
||||
nRCAS_RNO ORCALUT4 B In 0.000 2.753 r -
|
||||
nRCAS_RNO ORCALUT4 Z Out 0.757 3.510 f -
|
||||
N_37_i Net - - - - 1
|
||||
nRCAS FD1S3AY D In 0.000 3.510 f -
|
||||
========================================================================================
|
||||
Instance / Net Pin Pin Arrival No. of
|
||||
Name Type Name Dir Delay Time Fan Out(s)
|
||||
---------------------------------------------------------------------------------
|
||||
CBR FD1S3AX Q Out 1.612 1.612 r -
|
||||
CBR Net - - - - 4
|
||||
nRCAS_RNO_1 ORCALUT4 A In 0.000 1.612 r -
|
||||
nRCAS_RNO_1 ORCALUT4 Z Out 1.189 2.801 f -
|
||||
G_1_1 Net - - - - 1
|
||||
nRCAS_RNO ORCALUT4 B In 0.000 2.801 f -
|
||||
nRCAS_RNO ORCALUT4 Z Out 0.757 3.558 r -
|
||||
N_46_i Net - - - - 1
|
||||
nRCAS FD1S3AY D In 0.000 3.558 r -
|
||||
=================================================================================
|
||||
|
||||
|
||||
|
||||
|
@ -929,10 +925,10 @@ nRCAS FD1S3AY D In 0.000 3.510 f -
|
|||
|
||||
Timing exceptions that could not be applied
|
||||
|
||||
Finished final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 195MB peak: 196MB)
|
||||
Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 196MB peak: 197MB)
|
||||
|
||||
|
||||
Finished timing report (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 195MB peak: 196MB)
|
||||
Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 196MB peak: 197MB)
|
||||
|
||||
---------------------------------------
|
||||
Resource Usage Report
|
||||
|
@ -953,19 +949,19 @@ FD1S3IX: 14
|
|||
FD1S3JX: 3
|
||||
GSR: 1
|
||||
IB: 26
|
||||
INV: 8
|
||||
INV: 7
|
||||
OB: 33
|
||||
ORCALUT4: 119
|
||||
PFUMX: 2
|
||||
ORCALUT4: 133
|
||||
PFUMX: 1
|
||||
PUR: 1
|
||||
VHI: 1
|
||||
VLO: 1
|
||||
Mapper successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 80MB peak: 196MB)
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 78MB peak: 197MB)
|
||||
|
||||
Process took 0h:00m:05s realtime, 0h:00m:04s cputime
|
||||
# Thu Sep 21 05:38:27 2023
|
||||
Process took 0h:00m:03s realtime, 0h:00m:03s cputime
|
||||
# Sat Jan 6 06:24:55 2024
|
||||
|
||||
###########################################################]
|
||||
|
||||
|
|
|
@ -22,7 +22,7 @@ Setup and Hold Report
|
|||
|
||||
--------------------------------------------------------------------------------
|
||||
<A name="Map_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454</big></U></B>
|
||||
Thu Sep 21 05:38:30 2023
|
||||
Sat Jan 06 06:24:59 2024
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
|
@ -41,8 +41,8 @@ Report level: verbose report, limited to 1 item per preference
|
|||
|
||||
<A name="mtw1_set_ps"></A><B><U><big>Preference Summary</big></U></B>
|
||||
|
||||
<LI><A href='#map_twr_pref_0_0' Target='right'>FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)</A></LI> 129 items scored, 0 timing errors detected.
|
||||
Report: 51.046MHz is the maximum frequency for this preference.
|
||||
<LI><A href='#map_twr_pref_0_0' Target='right'>FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)</A></LI> 168 items scored, 0 timing errors detected.
|
||||
Report: 43.077MHz is the maximum frequency for this preference.
|
||||
|
||||
<LI><A href='#map_twr_pref_0_1' Target='right'>FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
|
||||
Report: 400.000MHz is the maximum frequency for this preference.
|
||||
|
@ -50,8 +50,8 @@ Report: 400.000MHz is the maximum frequency for this preference.
|
|||
<LI><A href='#map_twr_pref_0_2' Target='right'>FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
|
||||
Report: 400.000MHz is the maximum frequency for this preference.
|
||||
|
||||
<LI><A href='#map_twr_pref_0_3' Target='right'>FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)</A></LI> 388 items scored, 0 timing errors detected.
|
||||
Report: 88.456MHz is the maximum frequency for this preference.
|
||||
<LI><A href='#map_twr_pref_0_3' Target='right'>FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)</A></LI> 392 items scored, 0 timing errors detected.
|
||||
Report: 102.020MHz is the maximum frequency for this preference.
|
||||
|
||||
BLOCK ASYNCPATHS
|
||||
BLOCK RESETPATHS
|
||||
|
@ -61,46 +61,48 @@ BLOCK RESETPATHS
|
|||
|
||||
================================================================================
|
||||
<A name="map_twr_pref_0_0"></A>Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
|
||||
129 items scored, 0 timing errors detected.
|
||||
168 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 162.619ns (weighted slack = 325.238ns)
|
||||
Passed: The following path meets requirements by 160.807ns (weighted slack = 321.614ns)
|
||||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q Bank[2] (from PHI2_c +)
|
||||
Destination: FF Data in CmdSubmitted (to PHI2_c -)
|
||||
Source: FF Q Bank[6] (from PHI2_c +)
|
||||
Destination: FF Data in CmdEnable (to PHI2_c -)
|
||||
|
||||
Delay: 9.621ns (25.1% logic, 74.9% route), 6 logic levels.
|
||||
Delay: 11.433ns (24.4% logic, 75.6% route), 7 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
9.621ns physical path delay SLICE_71 to SLICE_22 meets
|
||||
11.433ns physical path delay SLICE_75 to SLICE_20 meets
|
||||
172.414ns delay constraint less
|
||||
0.174ns DIN_SET requirement (totaling 172.240ns) by 162.619ns
|
||||
0.174ns DIN_SET requirement (totaling 172.240ns) by 160.807ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path SLICE_71 to SLICE_22:
|
||||
Data path SLICE_75 to SLICE_20:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.560 SLICE_71.CLK to SLICE_71.Q0 SLICE_71 (from PHI2_c)
|
||||
ROUTE 1 e 1.441 SLICE_71.Q0 to SLICE_56.A1 Bank[2]
|
||||
CTOF_DEL --- 0.371 SLICE_56.A1 to SLICE_56.F1 SLICE_56
|
||||
ROUTE 1 e 1.441 SLICE_56.F1 to SLICE_70.D1 C1WR_0_a2_0_11
|
||||
CTOF_DEL --- 0.371 SLICE_70.D1 to SLICE_70.F1 SLICE_70
|
||||
ROUTE 6 e 1.441 SLICE_70.F1 to SLICE_67.D0 N_147
|
||||
CTOF_DEL --- 0.371 SLICE_67.D0 to SLICE_67.F0 SLICE_67
|
||||
ROUTE 5 e 1.441 SLICE_67.F0 to SLICE_82.A0 XOR8MEG18
|
||||
CTOF_DEL --- 0.371 SLICE_82.A0 to SLICE_82.F0 SLICE_82
|
||||
ROUTE 1 e 1.441 SLICE_82.F0 to SLICE_22.A0 CmdSubmitted_1_sqmuxa
|
||||
CTOF_DEL --- 0.371 SLICE_22.A0 to SLICE_22.F0 SLICE_22
|
||||
ROUTE 1 e 0.001 SLICE_22.F0 to SLICE_22.DI0 N_460_0 (to PHI2_c)
|
||||
REG_DEL --- 0.560 SLICE_75.CLK to SLICE_75.Q0 SLICE_75 (from PHI2_c)
|
||||
ROUTE 1 e 1.441 SLICE_75.Q0 to SLICE_77.C1 Bank[6]
|
||||
CTOF_DEL --- 0.371 SLICE_77.C1 to SLICE_77.F1 SLICE_77
|
||||
ROUTE 2 e 1.441 SLICE_77.F1 to SLICE_79.D0 un1_Bank_1_5
|
||||
CTOF_DEL --- 0.371 SLICE_79.D0 to SLICE_79.F0 SLICE_79
|
||||
ROUTE 2 e 1.441 SLICE_79.F0 to SLICE_76.B0 C1WR_7
|
||||
CTOF_DEL --- 0.371 SLICE_76.B0 to SLICE_76.F0 SLICE_76
|
||||
ROUTE 5 e 1.441 SLICE_76.F0 to SLICE_70.B0 C1WR
|
||||
CTOF_DEL --- 0.371 SLICE_70.B0 to SLICE_70.F0 SLICE_70
|
||||
ROUTE 1 e 1.441 SLICE_70.F0 to SLICE_14.C1 N_121
|
||||
CTOF_DEL --- 0.371 SLICE_14.C1 to SLICE_14.F1 SLICE_14
|
||||
ROUTE 1 e 1.441 SLICE_14.F1 to SLICE_20.C0 un1_CmdEnable20_i
|
||||
CTOF_DEL --- 0.371 SLICE_20.C0 to SLICE_20.F0 SLICE_20
|
||||
ROUTE 1 e 0.001 SLICE_20.F0 to SLICE_20.DI0 CmdEnable_s (to PHI2_c)
|
||||
--------
|
||||
9.621 (25.1% logic, 74.9% route), 6 logic levels.
|
||||
11.433 (24.4% logic, 75.6% route), 7 logic levels.
|
||||
|
||||
Report: 51.046MHz is the maximum frequency for this preference.
|
||||
Report: 43.077MHz is the maximum frequency for this preference.
|
||||
|
||||
|
||||
================================================================================
|
||||
|
@ -141,46 +143,46 @@ Report: 400.000MHz is the maximum frequency for this preference.
|
|||
|
||||
================================================================================
|
||||
<A name="map_twr_pref_0_3"></A>Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
|
||||
388 items scored, 0 timing errors detected.
|
||||
392 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Passed: The following path meets requirements by 4.695ns
|
||||
Passed: The following path meets requirements by 6.198ns
|
||||
|
||||
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
||||
|
||||
Source: FF Q FS[17] (from RCLK_c +)
|
||||
Destination: FF Data in LEDEN (to RCLK_c +)
|
||||
Destination: FF Data in UFMSDI (to RCLK_c +)
|
||||
|
||||
Delay: 11.061ns (21.8% logic, 78.2% route), 6 logic levels.
|
||||
Delay: 9.621ns (25.1% logic, 74.9% route), 6 logic levels.
|
||||
|
||||
Constraint Details:
|
||||
|
||||
11.061ns physical path delay SLICE_1 to SLICE_33 meets
|
||||
9.621ns physical path delay SLICE_1 to SLICE_52 meets
|
||||
16.000ns delay constraint less
|
||||
0.244ns CE_SET requirement (totaling 15.756ns) by 4.695ns
|
||||
0.181ns DIN_SET requirement (totaling 15.819ns) by 6.198ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path SLICE_1 to SLICE_33:
|
||||
Data path SLICE_1 to SLICE_52:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.560 SLICE_1.CLK to SLICE_1.Q1 SLICE_1 (from RCLK_c)
|
||||
ROUTE 3 e 1.441 SLICE_1.Q1 to SLICE_81.D1 FS[17]
|
||||
CTOF_DEL --- 0.371 SLICE_81.D1 to SLICE_81.F1 SLICE_81
|
||||
ROUTE 1 e 1.441 SLICE_81.F1 to SLICE_72.C1 UFMSDI_ens2_i_o2_0_3
|
||||
CTOF_DEL --- 0.371 SLICE_72.C1 to SLICE_72.F1 SLICE_72
|
||||
ROUTE 4 e 1.441 SLICE_72.F1 to SLICE_58.C1 N_51
|
||||
ROUTE 3 e 1.441 SLICE_1.Q1 to SLICE_86.D1 FS[17]
|
||||
CTOF_DEL --- 0.371 SLICE_86.D1 to SLICE_86.F1 SLICE_86
|
||||
ROUTE 1 e 1.441 SLICE_86.F1 to SLICE_69.C1 UFMSDI_ens2_i_o2_0_3
|
||||
CTOF_DEL --- 0.371 SLICE_69.C1 to SLICE_69.F1 SLICE_69
|
||||
ROUTE 4 e 1.441 SLICE_69.F1 to SLICE_58.C1 N_128
|
||||
CTOF_DEL --- 0.371 SLICE_58.C1 to SLICE_58.F1 SLICE_58
|
||||
ROUTE 2 e 1.441 SLICE_58.F1 to SLICE_87.D0 N_151
|
||||
CTOF_DEL --- 0.371 SLICE_87.D0 to SLICE_87.F0 SLICE_87
|
||||
ROUTE 2 e 1.441 SLICE_87.F0 to SLICE_69.C0 N_137_8
|
||||
CTOF_DEL --- 0.371 SLICE_69.C0 to SLICE_69.F0 SLICE_69
|
||||
ROUTE 1 e 1.441 SLICE_69.F0 to SLICE_33.CE N_33 (to RCLK_c)
|
||||
ROUTE 3 e 1.441 SLICE_58.F1 to SLICE_55.C0 N_94
|
||||
CTOF_DEL --- 0.371 SLICE_55.C0 to SLICE_55.F0 SLICE_55
|
||||
ROUTE 1 e 1.441 SLICE_55.F0 to SLICE_52.D0 UFMSDI_r_xx_mm_1
|
||||
CTOF_DEL --- 0.371 SLICE_52.D0 to SLICE_52.F0 SLICE_52
|
||||
ROUTE 1 e 0.001 SLICE_52.F0 to SLICE_52.DI0 UFMSDI_RNO (to RCLK_c)
|
||||
--------
|
||||
11.061 (21.8% logic, 78.2% route), 6 logic levels.
|
||||
9.621 (25.1% logic, 74.9% route), 6 logic levels.
|
||||
|
||||
Report: 88.456MHz is the maximum frequency for this preference.
|
||||
Report: 102.020MHz is the maximum frequency for this preference.
|
||||
|
||||
<A name="mtw1_set_rs"></A><B><U><big>Report Summary</big></U></B>
|
||||
--------------
|
||||
|
@ -188,13 +190,13 @@ Report: 88.456MHz is the maximum frequency for this preference.
|
|||
Preference | Constraint| Actual|Levels
|
||||
----------------------------------------------------------------------------
|
||||
| | |
|
||||
FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 51.046 MHz| 6
|
||||
FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 43.077 MHz| 7
|
||||
| | |
|
||||
FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 400.000 MHz| 0
|
||||
| | |
|
||||
FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 400.000 MHz| 0
|
||||
| | |
|
||||
FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 88.456 MHz| 6
|
||||
FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 102.020 MHz| 6
|
||||
| | |
|
||||
----------------------------------------------------------------------------
|
||||
|
||||
|
@ -249,11 +251,11 @@ Clock Domain: PHI2_c Source: PHI2.PAD Loads: 15
|
|||
Timing errors: 0 Score: 0
|
||||
Cumulative negative slack: 0
|
||||
|
||||
Constraints cover 517 paths, 4 nets, and 395 connections (62.40% coverage)
|
||||
Constraints cover 560 paths, 4 nets, and 424 connections (62.26% coverage)
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
<A name="Map_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454</big></U></B>
|
||||
Thu Sep 21 05:38:30 2023
|
||||
Sat Jan 06 06:24:59 2024
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
|
@ -272,13 +274,13 @@ Report level: verbose report, limited to 1 item per preference
|
|||
|
||||
<A name="mtw1_hold_ps"></A><B><U><big>Preference Summary</big></U></B>
|
||||
|
||||
<LI><A href='#map_twr_pref_1_0' Target='right'>FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)</A></LI> 129 items scored, 0 timing errors detected.
|
||||
<LI><A href='#map_twr_pref_1_0' Target='right'>FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)</A></LI> 168 items scored, 0 timing errors detected.
|
||||
|
||||
<LI><A href='#map_twr_pref_1_1' Target='right'>FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
|
||||
|
||||
<LI><A href='#map_twr_pref_1_2' Target='right'>FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
|
||||
|
||||
<LI><A href='#map_twr_pref_1_3' Target='right'>FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)</A></LI> 388 items scored, 0 timing errors detected.
|
||||
<LI><A href='#map_twr_pref_1_3' Target='right'>FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)</A></LI> 392 items scored, 0 timing errors detected.
|
||||
|
||||
BLOCK ASYNCPATHS
|
||||
BLOCK RESETPATHS
|
||||
|
@ -288,7 +290,7 @@ BLOCK RESETPATHS
|
|||
|
||||
================================================================================
|
||||
<A name="map_twr_pref_1_0"></A>Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
|
||||
129 items scored, 0 timing errors detected.
|
||||
168 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
@ -334,7 +336,7 @@ ROUTE 1 e 0.001 SLICE_14.F0 to SLICE_14.DI0 C1Submitted_RNO (to P
|
|||
|
||||
================================================================================
|
||||
<A name="map_twr_pref_1_3"></A>Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
|
||||
388 items scored, 0 timing errors detected.
|
||||
392 items scored, 0 timing errors detected.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
@ -349,17 +351,17 @@ Passed: The following path meets requirements by 0.342ns
|
|||
|
||||
Constraint Details:
|
||||
|
||||
0.325ns physical path delay SLICE_75 to SLICE_75 meets
|
||||
0.325ns physical path delay SLICE_74 to SLICE_74 meets
|
||||
-0.017ns M_HLD and
|
||||
0.000ns delay constraint requirement (totaling -0.017ns) by 0.342ns
|
||||
|
||||
Physical Path Details:
|
||||
|
||||
Data path SLICE_75 to SLICE_75:
|
||||
Data path SLICE_74 to SLICE_74:
|
||||
|
||||
Name Fanout Delay (ns) Site Resource
|
||||
REG_DEL --- 0.126 SLICE_75.CLK to SLICE_75.Q0 SLICE_75 (from RCLK_c)
|
||||
ROUTE 1 e 0.199 SLICE_75.Q0 to SLICE_75.M1 CASr (to RCLK_c)
|
||||
REG_DEL --- 0.126 SLICE_74.CLK to SLICE_74.Q0 SLICE_74 (from RCLK_c)
|
||||
ROUTE 1 e 0.199 SLICE_74.Q0 to SLICE_74.M1 CASr (to RCLK_c)
|
||||
--------
|
||||
0.325 (38.8% logic, 61.2% route), 1 logic levels.
|
||||
|
||||
|
@ -430,7 +432,7 @@ Clock Domain: PHI2_c Source: PHI2.PAD Loads: 15
|
|||
Timing errors: 0 Score: 0
|
||||
Cumulative negative slack: 0
|
||||
|
||||
Constraints cover 517 paths, 4 nets, and 395 connections (62.40% coverage)
|
||||
Constraints cover 560 paths, 4 nets, and 424 connections (62.26% coverage)
|
||||
|
||||
|
||||
|
||||
|
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
@ -2,8 +2,9 @@
|
|||
Starting: parse design source files
|
||||
(VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo.v'
|
||||
(VERI-1482) Analyzing Verilog file '//Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-SPI.v'
|
||||
WARNING - //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-SPI.v(23,47-23,52) (VERI-1875) identifier 'Ready' is used before its declaration
|
||||
INFO - //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-SPI.v(1,8-1,14) (VERI-1018) compiling module 'RAM2GS'
|
||||
INFO - //Mac/iCloud/Repos/RAM2GS/CPLD/RAM2GS-SPI.v(1,1-410,10) (VERI-9000) elaborating module 'RAM2GS'
|
||||
Done: design load finished with (0) errors, and (0) warnings
|
||||
Done: design load finished with (0) errors, and (1) warnings
|
||||
|
||||
</PRE></BODY></HTML>
|
|
@ -29,7 +29,7 @@ Performance Hardware Data Status: Version 1.124.
|
|||
// Package: TQFP100
|
||||
// ncd File: ram2gs_lcmxo256c_impl1.ncd
|
||||
// Version: Diamond (64-bit) 3.12.1.454
|
||||
// Written on Thu Sep 21 05:38:44 2023
|
||||
// Written on Sat Jan 06 06:25:13 2024
|
||||
// M: Minimum Performance Grade
|
||||
// iotiming RAM2GS_LCMXO256C_impl1.ncd RAM2GS_LCMXO256C_impl1.prf -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO256C/promote.xml
|
||||
|
||||
|
@ -41,98 +41,98 @@ Worst Case Results across Performance Grades (M, 5, 4, 3):
|
|||
|
||||
Port Clock Edge Setup Performance_Grade Hold Performance_Grade
|
||||
----------------------------------------------------------------------
|
||||
CROW[0] nCRAS F -0.006 M 1.904 3
|
||||
CROW[1] nCRAS F -0.006 M 1.904 3
|
||||
Din[0] PHI2 F 4.101 3 2.207 3
|
||||
Din[0] nCCAS F 1.552 3 -0.018 M
|
||||
Din[1] PHI2 F 2.668 3 3.026 3
|
||||
Din[1] nCCAS F 0.606 3 0.745 3
|
||||
Din[2] PHI2 F 2.073 3 2.917 3
|
||||
Din[2] nCCAS F 0.500 3 0.619 3
|
||||
Din[3] PHI2 F 2.620 3 3.334 3
|
||||
Din[3] nCCAS F -0.089 M 1.336 3
|
||||
Din[4] PHI2 F 5.116 3 2.411 3
|
||||
Din[4] nCCAS F 0.293 3 1.125 3
|
||||
Din[5] PHI2 F 5.590 3 2.084 3
|
||||
Din[5] nCCAS F 0.435 3 0.979 3
|
||||
Din[6] PHI2 F 5.951 3 1.726 3
|
||||
Din[6] nCCAS F 1.305 3 0.253 3
|
||||
Din[7] PHI2 F 4.412 3 1.404 3
|
||||
Din[7] nCCAS F 0.195 3 1.215 3
|
||||
MAin[0] PHI2 F 3.306 3 1.176 3
|
||||
MAin[0] nCRAS F -0.132 M 2.336 3
|
||||
MAin[1] PHI2 F 2.656 3 2.511 3
|
||||
MAin[1] nCRAS F -0.034 M 2.014 3
|
||||
MAin[2] PHI2 F 6.839 3 -0.310 M
|
||||
MAin[2] nCRAS F -0.154 M 2.424 3
|
||||
MAin[3] PHI2 F 6.871 3 -0.311 M
|
||||
MAin[3] nCRAS F -0.015 M 1.928 3
|
||||
MAin[4] PHI2 F 7.111 3 -0.361 M
|
||||
MAin[4] nCRAS F 0.370 3 1.590 3
|
||||
MAin[5] PHI2 F 7.075 3 -0.353 M
|
||||
MAin[5] nCRAS F -0.126 M 2.320 3
|
||||
MAin[6] PHI2 F 6.794 3 -0.295 M
|
||||
MAin[6] nCRAS F 0.010 3 1.885 3
|
||||
MAin[7] PHI2 F 6.926 3 -0.324 M
|
||||
MAin[7] nCRAS F 0.319 3 1.622 3
|
||||
MAin[8] nCRAS F -0.038 M 2.031 3
|
||||
MAin[9] nCRAS F 0.366 3 1.596 3
|
||||
PHI2 RCLK R 2.295 3 -0.174 M
|
||||
UFMSDO RCLK R 1.364 3 0.511 3
|
||||
nCCAS RCLK R 2.300 3 -0.185 M
|
||||
nCCAS nCRAS F 0.216 3 1.721 3
|
||||
nCRAS RCLK R 4.548 3 -0.507 M
|
||||
nFWE PHI2 F 6.729 3 -0.281 M
|
||||
nFWE nCRAS F -0.037 M 2.025 3
|
||||
CROW[0] nCRAS F -0.006 M 1.907 3
|
||||
CROW[1] nCRAS F -0.006 M 1.907 3
|
||||
Din[0] PHI2 F 4.304 3 2.935 3
|
||||
Din[0] nCCAS F 0.567 3 0.723 3
|
||||
Din[1] PHI2 F 4.920 3 3.034 3
|
||||
Din[1] nCCAS F 0.414 3 0.851 3
|
||||
Din[2] PHI2 F 3.171 3 3.327 3
|
||||
Din[2] nCCAS F 0.909 3 0.432 3
|
||||
Din[3] PHI2 F 4.332 3 2.525 3
|
||||
Din[3] nCCAS F 0.038 3 1.155 3
|
||||
Din[4] PHI2 F 5.624 3 2.635 3
|
||||
Din[4] nCCAS F 1.448 3 -0.041 M
|
||||
Din[5] PHI2 F 4.126 3 2.124 3
|
||||
Din[5] nCCAS F 1.046 3 0.159 3
|
||||
Din[6] PHI2 F 5.565 3 2.394 3
|
||||
Din[6] nCCAS F 0.563 3 0.729 3
|
||||
Din[7] PHI2 F 5.293 3 1.654 3
|
||||
Din[7] nCCAS F 0.719 3 0.583 3
|
||||
MAin[0] PHI2 F 8.072 3 -0.164 M
|
||||
MAin[0] nCRAS F -0.128 M 2.331 3
|
||||
MAin[1] PHI2 F 7.487 3 -0.178 M
|
||||
MAin[1] nCRAS F -0.129 M 2.331 3
|
||||
MAin[2] PHI2 F 6.793 3 -0.034 M
|
||||
MAin[2] nCRAS F -0.129 M 2.331 3
|
||||
MAin[3] PHI2 F 7.235 3 -0.226 M
|
||||
MAin[3] nCRAS F -0.035 M 2.023 3
|
||||
MAin[4] PHI2 F 7.305 3 -0.207 M
|
||||
MAin[4] nCRAS F 0.428 3 1.517 3
|
||||
MAin[5] PHI2 F 7.672 3 -0.236 M
|
||||
MAin[5] nCRAS F -0.037 M 2.028 3
|
||||
MAin[6] PHI2 F 9.015 3 -0.710 M
|
||||
MAin[6] nCRAS F -0.003 M 1.896 3
|
||||
MAin[7] PHI2 F 7.764 3 -0.441 M
|
||||
MAin[7] nCRAS F -0.126 M 2.324 3
|
||||
MAin[8] nCRAS F -0.038 M 2.034 3
|
||||
MAin[9] nCRAS F 0.206 3 1.728 3
|
||||
PHI2 RCLK R 2.769 3 -0.274 M
|
||||
UFMSDO RCLK R 1.753 3 -0.052 M
|
||||
nCCAS RCLK R 1.935 3 -0.108 M
|
||||
nCCAS nCRAS F 0.843 3 1.179 3
|
||||
nCRAS RCLK R 1.093 3 0.277 3
|
||||
nFWE PHI2 F 4.435 3 0.640 3
|
||||
nFWE nCRAS F 1.163 3 0.894 3
|
||||
|
||||
|
||||
// Clock to Output Delay
|
||||
|
||||
Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
|
||||
------------------------------------------------------------------------
|
||||
LED RCLK R 13.764 3 4.455 M
|
||||
LED nCRAS F 16.500 3 4.993 M
|
||||
RA[0] RCLK R 10.114 3 2.098 M
|
||||
RA[0] nCRAS F 11.793 3 2.420 M
|
||||
RA[10] RCLK R 8.581 3 1.780 M
|
||||
LED RCLK R 15.407 3 4.713 M
|
||||
LED nCRAS F 17.685 3 5.215 M
|
||||
RA[0] RCLK R 10.436 3 2.152 M
|
||||
RA[0] nCRAS F 11.488 3 2.330 M
|
||||
RA[10] RCLK R 8.093 3 1.668 M
|
||||
RA[11] PHI2 R 9.420 3 1.925 M
|
||||
RA[1] RCLK R 11.717 3 2.429 M
|
||||
RA[1] nCRAS F 12.171 3 2.492 M
|
||||
RA[2] RCLK R 9.514 3 1.971 M
|
||||
RA[2] nCRAS F 11.301 3 2.319 M
|
||||
RA[3] RCLK R 10.525 3 2.169 M
|
||||
RA[3] nCRAS F 12.042 3 2.459 M
|
||||
RA[4] RCLK R 11.387 3 2.343 M
|
||||
RA[4] nCRAS F 12.532 3 2.543 M
|
||||
RA[5] RCLK R 10.114 3 2.098 M
|
||||
RA[5] nCRAS F 10.936 3 2.242 M
|
||||
RA[6] RCLK R 9.514 3 1.971 M
|
||||
RA[6] nCRAS F 10.544 3 2.165 M
|
||||
RA[7] RCLK R 10.933 3 2.261 M
|
||||
RA[7] nCRAS F 11.162 3 2.268 M
|
||||
RA[8] RCLK R 10.591 3 2.178 M
|
||||
RA[8] nCRAS F 11.951 3 2.426 M
|
||||
RA[9] RCLK R 9.668 3 1.989 M
|
||||
RA[9] nCRAS F 10.889 3 2.209 M
|
||||
RBA[0] nCRAS F 8.922 3 1.828 M
|
||||
RBA[1] nCRAS F 10.649 3 2.177 M
|
||||
RCKE RCLK R 8.493 3 1.760 M
|
||||
RDQMH RCLK R 10.817 3 2.273 M
|
||||
RDQML RCLK R 11.739 3 2.471 M
|
||||
RD[0] nCCAS F 9.545 3 2.093 M
|
||||
RD[1] nCCAS F 8.834 3 1.965 M
|
||||
RD[2] nCCAS F 9.535 3 2.092 M
|
||||
RD[3] nCCAS F 9.531 3 2.092 M
|
||||
RD[4] nCCAS F 9.303 3 2.066 M
|
||||
RD[5] nCCAS F 11.766 3 2.555 M
|
||||
RD[6] nCCAS F 9.303 3 2.066 M
|
||||
RD[7] nCCAS F 10.470 3 2.285 M
|
||||
UFMCLK RCLK R 9.190 3 1.937 M
|
||||
RA[1] RCLK R 10.958 3 2.270 M
|
||||
RA[1] nCRAS F 12.371 3 2.529 M
|
||||
RA[2] RCLK R 10.892 3 2.242 M
|
||||
RA[2] nCRAS F 11.786 3 2.402 M
|
||||
RA[3] RCLK R 10.561 3 2.184 M
|
||||
RA[3] nCRAS F 12.541 3 2.560 M
|
||||
RA[4] RCLK R 10.909 3 2.257 M
|
||||
RA[4] nCRAS F 12.060 3 2.456 M
|
||||
RA[5] RCLK R 9.970 3 2.057 M
|
||||
RA[5] nCRAS F 12.271 3 2.508 M
|
||||
RA[6] RCLK R 9.222 3 1.920 M
|
||||
RA[6] nCRAS F 10.844 3 2.210 M
|
||||
RA[7] RCLK R 9.613 3 1.981 M
|
||||
RA[7] nCRAS F 11.686 3 2.379 M
|
||||
RA[8] RCLK R 9.617 3 1.982 M
|
||||
RA[8] nCRAS F 11.487 3 2.339 M
|
||||
RA[9] RCLK R 9.762 3 2.016 M
|
||||
RA[9] nCRAS F 11.488 3 2.337 M
|
||||
RBA[0] nCRAS F 8.925 3 1.828 M
|
||||
RBA[1] nCRAS F 10.608 3 2.153 M
|
||||
RCKE RCLK R 7.609 3 1.570 M
|
||||
RDQMH RCLK R 10.915 3 2.299 M
|
||||
RDQML RCLK R 11.554 3 2.433 M
|
||||
RD[0] nCCAS F 8.539 3 1.899 M
|
||||
RD[1] nCCAS F 9.248 3 2.027 M
|
||||
RD[2] nCCAS F 9.706 3 2.118 M
|
||||
RD[3] nCCAS F 8.539 3 1.899 M
|
||||
RD[4] nCCAS F 9.228 3 2.015 M
|
||||
RD[5] nCCAS F 8.772 3 1.924 M
|
||||
RD[6] nCCAS F 8.539 3 1.899 M
|
||||
RD[7] nCCAS F 9.706 3 2.118 M
|
||||
UFMCLK RCLK R 8.007 3 1.714 M
|
||||
UFMSDI RCLK R 8.007 3 1.714 M
|
||||
nRCAS RCLK R 8.209 3 1.697 M
|
||||
nRCAS RCLK R 8.120 3 1.681 M
|
||||
nRCS RCLK R 6.854 3 1.431 M
|
||||
nRRAS RCLK R 8.021 3 1.650 M
|
||||
nRRAS RCLK R 8.089 3 1.669 M
|
||||
nRWE RCLK R 6.854 3 1.431 M
|
||||
nUFMCS RCLK R 9.650 3 2.046 M
|
||||
nUFMCS RCLK R 8.732 3 1.846 M
|
||||
WARNING: you must also run trce with hold speed: 3
|
||||
WARNING: you must also run trce with setup speed: M
|
||||
|
|
|
@ -1,3 +1,3 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<userSetting name="//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO256C/promote.xml" version="Diamond (64-bit) 3.12.1.454" date="Thu Sep 21 05:39:05 2023" vendor="Lattice Semiconductor Corporation" >
|
||||
<userSetting name="//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO256C/promote.xml" version="Diamond (64-bit) 3.12.1.454" date="Sat Jan 06 06:29:54 2024" vendor="Lattice Semiconductor Corporation" >
|
||||
</userSetting>
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
<ReportView version="2.0">
|
||||
<Implement name="impl1">
|
||||
<ToolReport id="tooldec" path="" status="0"/>
|
||||
<ToolReport id="toolhle_genhierarchy" path="Y:/Repos/RAM2GS/CPLD/LCMXO256C/impl1/hdla_gen_hierarchy.html" status="1"/>
|
||||
<ToolReport id="toolhle_genhierarchy" path="//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO256C/impl1/hdla_gen_hierarchy.html" status="1"/>
|
||||
<ToolReport id="toolpio" path="" status="2"/>
|
||||
<ToolReport id="toolsso" path="" status="2"/>
|
||||
</Implement>
|
||||
|
|
|
@ -0,0 +1,70 @@
|
|||
<HTML>
|
||||
<HEAD><TITLE>Lattice TCL Log</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="pn231119195557"></A><B><U><big>pn231119195557</big></U></B>
|
||||
#Start recording tcl command: 11/18/2023 02:19:15
|
||||
#Project Location: //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO640C; Project name: RAM2GS_LCMXO640C
|
||||
prj_project open "//Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO640C/RAM2GS_LCMXO640C.ldf"
|
||||
prj_run Export -impl impl1
|
||||
#Stop recording: 11/19/2023 19:55:57
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
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Reference in New Issue