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9 lines
347 B
Verilog
9 lines
347 B
Verilog
/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.12.1.454 */
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/* Module Version: 1.2 */
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/* Thu Sep 21 04:34:49 2023 */
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/* parameterized module instance */
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REFB __ (.wb_clk_i( ), .wb_rst_i( ), .wb_cyc_i( ), .wb_stb_i( ),
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.wb_we_i( ), .wb_adr_i( ), .wb_dat_i( ), .wb_dat_o( ), .wb_ack_o( ),
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.wbc_ufm_irq( ));
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