mirror of
https://github.com/garrettsworkshop/RAM2GS.git
synced 2025-03-01 09:30:19 +00:00
68 lines
4.5 KiB
Plaintext
68 lines
4.5 KiB
Plaintext
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Copyright (C) 1994-2018 Synopsys, Inc.
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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
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and may only be used pursuant to the terms and conditions of a written license agreement
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with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
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Synopsys software or the associated documentation is strictly prohibited.
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Tool: Synplify Pro (R)
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Build: N-2018.03L-SP1-1
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Install: C:\lscc\diamond\3.11_x64\synpbase
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OS: Windows 6.2
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Hostname: ZANEMACWIN11
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Implementation : impl1
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# Written on Sun Jul 14 22:31:10 2024
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##### FILES SYNTAX CHECKED ##############################################
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Constraint File(s): "\\Mac\iCloud\Repos\RAM2GS\CPLD\RAM2GS.sdc"
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#Run constraint checker to find more issues with constraints.
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#########################################################################
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No issues found in constraint syntax.
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Clock Summary
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*************
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Start Requested Requested Clock Clock Clock
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Level Clock Frequency Period Type Group Load
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--------------------------------------------------------------------------------------------------------------
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0 - PHI2 2.9 MHz 350.000 declared default_clkgroup 20
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0 - nCRAS 2.9 MHz 350.000 declared default_clkgroup 15
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0 - nCCAS 2.9 MHz 350.000 declared default_clkgroup 10
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0 - RCLK 62.5 MHz 16.000 declared default_clkgroup 0
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0 - System 100.0 MHz 10.000 system system_clkgroup 0
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0 - RPLL|CLKOP_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_0 65
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==============================================================================================================
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Clock Load Summary
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******************
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Clock Source Clock Pin Non-clock Pin Non-clock Pin
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Clock Load Pin Seq Example Seq Example Comb Example
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------------------------------------------------------------------------------------------------------------------------------
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PHI2 20 PHI2(port) Bank[7:0].C PHI2r.D[0] un1_PHI2.I[0](inv)
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nCRAS 15 nCRAS(port) CBR.C RASr.D[0] RASr_2.I[0](inv)
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nCCAS 10 nCCAS(port) WRD[7:0].C CASr.D[0] CASr_2.I[0](inv)
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RCLK 0 RCLK(port) - - -
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System 0 - - - -
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RPLL|CLKOP_inferred_clock 65 rpll.PLLInst_0.CLKOP(EHXPLLJ) CASr2.C - -
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==============================================================================================================================
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