2741 lines
128 KiB
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2741 lines
128 KiB
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<HEAD><TITLE>Lattice Map TRACE Report</TITLE>
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<PRE><A name="Map_Twr"></A><B><U><big>Map TRACE Report</big></U></B>
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Loading design for application trce from file ram2gs_lcmxo256c_impl1_map.ncd.
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Design name: RAM2GS
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NCD version: 3.3
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Vendor: LATTICE
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Device: LCMXO256C
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Package: TQFP100
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Performance: 3
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Loading device for application trce from file 'mj5g10x6.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
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Package Status: Final Version 1.19.
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Performance Hardware Data Status: Version 1.124.
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Setup and Hold Report
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--------------------------------------------------------------------------------
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<A name="Map_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2</big></U></B>
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Mon Aug 16 21:32:27 2021
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
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<A name="mtw1_set_ri"></A><B><U><big>Report Information</big></U></B>
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------------------
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Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO256C_impl1.tw1 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.prf
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Design file: ram2gs_lcmxo256c_impl1_map.ncd
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Preference file: ram2gs_lcmxo256c_impl1.prf
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Device,speed: LCMXO256C,3
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Report level: verbose report, limited to 1 item per preference
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--------------------------------------------------------------------------------
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<A name="mtw1_set_ps"></A><B><U><big>Preference Summary</big></U></B>
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<LI><A href='#map_twr_pref_0_0' Target='right'>PERIOD NET "PHI2_c" 350.000000 ns (0 errors)</A></LI> 113 items scored, 0 timing errors detected.
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<LI><A href='#map_twr_pref_0_1' Target='right'>PERIOD NET "nCCAS_c" 350.000000 ns (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
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<LI><A href='#map_twr_pref_0_2' Target='right'>PERIOD NET "nCRAS_c" 350.000000 ns (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
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<LI><A href='#map_twr_pref_0_3' Target='right'>PERIOD NET "RCLK_c" 16.000000 ns (0 errors)</A></LI> 395 items scored, 0 timing errors detected.
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<LI><A href='#map_twr_pref_0_4' Target='right'>CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
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<LI><A href='#map_twr_pref_0_5' Target='right'>CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
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<LI><A href='#map_twr_pref_0_6' Target='right'>CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
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<LI><A href='#map_twr_pref_0_7' Target='right'>CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
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<LI><A href='#map_twr_pref_0_8' Target='right'>CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
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<LI><A href='#map_twr_pref_0_9' Target='right'>CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
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<LI><A href='#map_twr_pref_0_10' Target='right'>CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
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<LI><A href='#map_twr_pref_0_11' Target='right'>CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
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<LI><A href='#map_twr_pref_0_12' Target='right'>CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
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<LI><A href='#map_twr_pref_0_13' Target='right'>CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
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<LI><A href='#map_twr_pref_0_14' Target='right'>CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
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<LI><A href='#map_twr_pref_0_15' Target='right'>CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
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<LI><A href='#map_twr_pref_0_16' Target='right'>CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
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<LI><A href='#map_twr_pref_0_17' Target='right'>CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
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<LI><A href='#map_twr_pref_0_18' Target='right'>CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
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<LI><A href='#map_twr_pref_0_19' Target='right'>CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
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<LI><A href='#map_twr_pref_0_20' Target='right'>CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
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<LI><A href='#map_twr_pref_0_21' Target='right'>CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
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<LI><A href='#map_twr_pref_0_22' Target='right'>CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
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<LI><A href='#map_twr_pref_0_23' Target='right'>CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
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<LI><A href='#map_twr_pref_0_24' Target='right'>CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
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<LI><A href='#map_twr_pref_0_25' Target='right'>CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
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<LI><A href='#map_twr_pref_0_26' Target='right'>CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
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<LI><A href='#map_twr_pref_0_27' Target='right'>CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
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<LI><A href='#map_twr_pref_0_28' Target='right'>CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
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<LI><A href='#map_twr_pref_0_29' Target='right'>CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
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<LI><A href='#map_twr_pref_0_30' Target='right'>CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
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<LI><A href='#map_twr_pref_0_31' Target='right'>CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
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<LI><A href='#map_twr_pref_0_32' Target='right'>CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
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<LI><A href='#map_twr_pref_0_33' Target='right'>CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
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<LI><A href='#map_twr_pref_0_34' Target='right'>CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
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<LI><A href='#map_twr_pref_0_35' Target='right'>CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
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<LI><A href='#map_twr_pref_0_36' Target='right'>CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
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<LI><A href='#map_twr_pref_0_37' Target='right'>CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
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<LI><A href='#map_twr_pref_0_38' Target='right'>CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
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<LI><A href='#map_twr_pref_0_39' Target='right'>CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
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<LI><A href='#map_twr_pref_0_40' Target='right'>CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
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BLOCK ASYNCPATHS
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BLOCK RESETPATHS
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--------------------------------------------------------------------------------
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Derating parameters
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-------------------
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Voltage: 3.300 V
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================================================================================
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<A name="map_twr_pref_0_0"></A>Preference: PERIOD NET "PHI2_c" 350.000000 ns ;
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113 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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Passed: The following path meets requirements by 161.862ns (weighted slack = 323.724ns)
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q Bank_i7 (from PHI2_c +)
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Destination: FF Data in CmdSubmitted_384 (to PHI2_c -)
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Delay: 12.873ns (21.6% logic, 78.4% route), 7 logic levels.
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Constraint Details:
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12.873ns physical path delay SLICE_95 to SLICE_19 meets
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175.000ns delay constraint less
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0.265ns CE_SET requirement (totaling 174.735ns) by 161.862ns
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Physical Path Details:
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Data path SLICE_95 to SLICE_19:
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.560 SLICE_95.CLK to SLICE_95.Q1 SLICE_95 (from PHI2_c)
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ROUTE 1 e 1.441 SLICE_95.Q1 to SLICE_67.A1 Bank_7
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CTOF_DEL --- 0.371 SLICE_67.A1 to SLICE_67.F1 SLICE_67
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ROUTE 1 e 1.441 SLICE_67.F1 to SLICE_82.C1 n2154
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CTOF_DEL --- 0.371 SLICE_82.C1 to SLICE_82.F1 SLICE_82
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ROUTE 1 e 1.441 SLICE_82.F1 to SLICE_76.B1 n26
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CTOF_DEL --- 0.371 SLICE_76.B1 to SLICE_76.F1 SLICE_76
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ROUTE 4 e 1.441 SLICE_76.F1 to SLICE_89.B0 n1285
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CTOF_DEL --- 0.371 SLICE_89.B0 to SLICE_89.F0 SLICE_89
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ROUTE 3 e 1.441 SLICE_89.F0 to SLICE_18.D1 n2290
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CTOF_DEL --- 0.371 SLICE_18.D1 to SLICE_18.F1 SLICE_18
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ROUTE 3 e 1.441 SLICE_18.F1 to SLICE_90.C0 XOR8MEG_N_112
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CTOF_DEL --- 0.371 SLICE_90.C0 to SLICE_90.F0 SLICE_90
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ROUTE 2 e 1.441 SLICE_90.F0 to SLICE_19.CE PHI2_N_114_enable_6 (to PHI2_c)
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--------
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12.873 (21.6% logic, 78.4% route), 7 logic levels.
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Report: 26.276ns is the minimum period for this preference.
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================================================================================
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<A name="map_twr_pref_0_1"></A>Preference: PERIOD NET "nCCAS_c" 350.000000 ns ;
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0 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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Passed: The following path meets requirements by 348.000ns
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The internal maximum frequency of the following component is 500.000 MHz
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Logical Details: Cell type Pin name Component name
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Destination: FSLICE CLK SLICE_76
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Delay: 2.000ns -- based on Minimum Pulse Width
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Report: 2.000ns is the minimum period for this preference.
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================================================================================
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<A name="map_twr_pref_0_2"></A>Preference: PERIOD NET "nCRAS_c" 350.000000 ns ;
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0 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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Passed: The following path meets requirements by 348.000ns
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The internal maximum frequency of the following component is 500.000 MHz
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Logical Details: Cell type Pin name Component name
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Destination: FSLICE CLK SLICE_77
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Delay: 2.000ns -- based on Minimum Pulse Width
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Report: 2.000ns is the minimum period for this preference.
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================================================================================
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<A name="map_twr_pref_0_3"></A>Preference: PERIOD NET "RCLK_c" 16.000000 ns ;
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395 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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Passed: The following path meets requirements by 5.575ns
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q FS_577__i14 (from RCLK_c +)
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Destination: FF Data in n8MEGEN_391 (to RCLK_c +)
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Delay: 10.181ns (23.7% logic, 76.3% route), 6 logic levels.
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Constraint Details:
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10.181ns physical path delay SLICE_7 to SLICE_56 meets
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16.000ns delay constraint less
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0.244ns CE_SET requirement (totaling 15.756ns) by 5.575ns
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Physical Path Details:
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Data path SLICE_7 to SLICE_56:
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.560 SLICE_7.CLK to SLICE_7.Q0 SLICE_7 (from RCLK_c)
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ROUTE 3 e 1.441 SLICE_7.Q0 to SLICE_78.A0 FS_14
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CTOF_DEL --- 0.371 SLICE_78.A0 to SLICE_78.F0 SLICE_78
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ROUTE 3 e 1.441 SLICE_78.F0 to SLICE_73.B1 n10
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CTOF_DEL --- 0.371 SLICE_73.B1 to SLICE_73.F1 SLICE_73
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ROUTE 4 e 0.561 SLICE_73.F1 to SLICE_73.B0 n2300
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CTOF_DEL --- 0.371 SLICE_73.B0 to SLICE_73.F0 SLICE_73
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ROUTE 1 e 1.441 SLICE_73.F0 to SLICE_75.C0 n11
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CTOF_DEL --- 0.371 SLICE_75.C0 to SLICE_75.F0 SLICE_75
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ROUTE 2 e 1.441 SLICE_75.F0 to SLICE_33.D1 n2119
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CTOF_DEL --- 0.371 SLICE_33.D1 to SLICE_33.F1 SLICE_33
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ROUTE 1 e 1.441 SLICE_33.F1 to SLICE_56.CE RCLK_c_enable_7 (to RCLK_c)
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--------
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10.181 (23.7% logic, 76.3% route), 6 logic levels.
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Report: 10.425ns is the minimum period for this preference.
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================================================================================
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<A name="map_twr_pref_0_4"></A>Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
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0 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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================================================================================
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<A name="map_twr_pref_0_5"></A>Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
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0 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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================================================================================
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<A name="map_twr_pref_0_6"></A>Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
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0 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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================================================================================
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<A name="map_twr_pref_0_7"></A>Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
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0 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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================================================================================
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<A name="map_twr_pref_0_8"></A>Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
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0 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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================================================================================
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<A name="map_twr_pref_0_9"></A>Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_0_10"></A>Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_0_11"></A>Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_0_12"></A>Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_0_13"></A>Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_0_14"></A>Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_0_15"></A>Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_0_16"></A>Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 4.359ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q RA10_373 (from RCLK_c +)
|
|
Destination: Port Pad RA[10]
|
|
|
|
Data Path Delay: 5.637ns (74.4% logic, 25.6% route), 2 logic levels.
|
|
|
|
Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
2.504ns delay RCLK to SLICE_55 and
|
|
5.637ns delay SLICE_55 to RA[10] (totaling 8.141ns) meets
|
|
12.500ns offset RCLK to RA[10] by 4.359ns
|
|
|
|
Physical Path Details:
|
|
|
|
Clock path RCLK to SLICE_55:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
|
|
ROUTE 39 e 1.441 86.PADDI to SLICE_55.CLK RCLK_c
|
|
--------
|
|
2.504 (42.5% logic, 57.5% route), 1 logic levels.
|
|
|
|
Data path SLICE_55 to RA[10]:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 SLICE_55.CLK to SLICE_55.Q0 SLICE_55 (from RCLK_c)
|
|
ROUTE 1 e 1.441 SLICE_55.Q0 to 87.PADDO n980
|
|
DOPAD_DEL --- 3.636 87.PADDO to 87.PAD RA[10]
|
|
--------
|
|
5.637 (74.4% logic, 25.6% route), 2 logic levels.
|
|
|
|
Report: 8.141ns is the minimum offset for this preference.
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_0_17"></A>Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 2.547ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q nRowColSel_375 (from RCLK_c +)
|
|
Destination: Port Pad RA[9]
|
|
|
|
Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
2.504ns delay RCLK to SLICE_64 and
|
|
7.449ns delay SLICE_64 to RA[9] (totaling 9.953ns) meets
|
|
12.500ns offset RCLK to RA[9] by 2.547ns
|
|
|
|
Physical Path Details:
|
|
|
|
Clock path RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
|
|
ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c
|
|
--------
|
|
2.504 (42.5% logic, 57.5% route), 1 logic levels.
|
|
|
|
Data path SLICE_64 to RA[9]:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
|
|
ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_88.C1 nRowColSel
|
|
CTOF_DEL --- 0.371 SLICE_88.C1 to SLICE_88.F1 SLICE_88
|
|
ROUTE 1 e 1.441 SLICE_88.F1 to 85.PADDO RA_c_9
|
|
DOPAD_DEL --- 3.636 85.PADDO to 85.PAD RA[9]
|
|
--------
|
|
7.449 (61.3% logic, 38.7% route), 3 logic levels.
|
|
|
|
Report: 9.953ns is the minimum offset for this preference.
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_0_18"></A>Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 2.547ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q nRowColSel_375 (from RCLK_c +)
|
|
Destination: Port Pad RA[8]
|
|
|
|
Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
2.504ns delay RCLK to SLICE_64 and
|
|
7.449ns delay SLICE_64 to RA[8] (totaling 9.953ns) meets
|
|
12.500ns offset RCLK to RA[8] by 2.547ns
|
|
|
|
Physical Path Details:
|
|
|
|
Clock path RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
|
|
ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c
|
|
--------
|
|
2.504 (42.5% logic, 57.5% route), 1 logic levels.
|
|
|
|
Data path SLICE_64 to RA[8]:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
|
|
ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_95.C0 nRowColSel
|
|
CTOF_DEL --- 0.371 SLICE_95.C0 to SLICE_95.F0 SLICE_95
|
|
ROUTE 1 e 1.441 SLICE_95.F0 to 96.PADDO RA_c_8
|
|
DOPAD_DEL --- 3.636 96.PADDO to 96.PAD RA[8]
|
|
--------
|
|
7.449 (61.3% logic, 38.7% route), 3 logic levels.
|
|
|
|
Report: 9.953ns is the minimum offset for this preference.
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_0_19"></A>Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 2.547ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q nRowColSel_375 (from RCLK_c +)
|
|
Destination: Port Pad RA[7]
|
|
|
|
Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
2.504ns delay RCLK to SLICE_64 and
|
|
7.449ns delay SLICE_64 to RA[7] (totaling 9.953ns) meets
|
|
12.500ns offset RCLK to RA[7] by 2.547ns
|
|
|
|
Physical Path Details:
|
|
|
|
Clock path RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
|
|
ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c
|
|
--------
|
|
2.504 (42.5% logic, 57.5% route), 1 logic levels.
|
|
|
|
Data path SLICE_64 to RA[7]:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
|
|
ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_97.C0 nRowColSel
|
|
CTOF_DEL --- 0.371 SLICE_97.C0 to SLICE_97.F0 SLICE_97
|
|
ROUTE 1 e 1.441 SLICE_97.F0 to 100.PADDO RA_c_7
|
|
DOPAD_DEL --- 3.636 100.PADDO to 100.PAD RA[7]
|
|
--------
|
|
7.449 (61.3% logic, 38.7% route), 3 logic levels.
|
|
|
|
Report: 9.953ns is the minimum offset for this preference.
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_0_20"></A>Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 2.547ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q nRowColSel_375 (from RCLK_c +)
|
|
Destination: Port Pad RA[6]
|
|
|
|
Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
2.504ns delay RCLK to SLICE_64 and
|
|
7.449ns delay SLICE_64 to RA[6] (totaling 9.953ns) meets
|
|
12.500ns offset RCLK to RA[6] by 2.547ns
|
|
|
|
Physical Path Details:
|
|
|
|
Clock path RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
|
|
ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c
|
|
--------
|
|
2.504 (42.5% logic, 57.5% route), 1 logic levels.
|
|
|
|
Data path SLICE_64 to RA[6]:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
|
|
ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_98.C0 nRowColSel
|
|
CTOF_DEL --- 0.371 SLICE_98.C0 to SLICE_98.F0 SLICE_98
|
|
ROUTE 1 e 1.441 SLICE_98.F0 to 91.PADDO RA_c_6
|
|
DOPAD_DEL --- 3.636 91.PADDO to 91.PAD RA[6]
|
|
--------
|
|
7.449 (61.3% logic, 38.7% route), 3 logic levels.
|
|
|
|
Report: 9.953ns is the minimum offset for this preference.
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_0_21"></A>Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 2.547ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q nRowColSel_375 (from RCLK_c +)
|
|
Destination: Port Pad RA[5]
|
|
|
|
Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
2.504ns delay RCLK to SLICE_64 and
|
|
7.449ns delay SLICE_64 to RA[5] (totaling 9.953ns) meets
|
|
12.500ns offset RCLK to RA[5] by 2.547ns
|
|
|
|
Physical Path Details:
|
|
|
|
Clock path RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
|
|
ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c
|
|
--------
|
|
2.504 (42.5% logic, 57.5% route), 1 logic levels.
|
|
|
|
Data path SLICE_64 to RA[5]:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
|
|
ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_98.C1 nRowColSel
|
|
CTOF_DEL --- 0.371 SLICE_98.C1 to SLICE_98.F1 SLICE_98
|
|
ROUTE 1 e 1.441 SLICE_98.F1 to 95.PADDO RA_c_5
|
|
DOPAD_DEL --- 3.636 95.PADDO to 95.PAD RA[5]
|
|
--------
|
|
7.449 (61.3% logic, 38.7% route), 3 logic levels.
|
|
|
|
Report: 9.953ns is the minimum offset for this preference.
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_0_22"></A>Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 3.427ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q nRowColSel_375 (from RCLK_c +)
|
|
Destination: Port Pad RA[4]
|
|
|
|
Data Path Delay: 6.569ns (69.5% logic, 30.5% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
2.504ns delay RCLK to SLICE_64 and
|
|
6.569ns delay SLICE_64 to RA[4] (totaling 9.073ns) meets
|
|
12.500ns offset RCLK to RA[4] by 3.427ns
|
|
|
|
Physical Path Details:
|
|
|
|
Clock path RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
|
|
ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c
|
|
--------
|
|
2.504 (42.5% logic, 57.5% route), 1 logic levels.
|
|
|
|
Data path SLICE_64 to RA[4]:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
|
|
ROUTE 13 e 0.561 SLICE_64.Q0 to SLICE_64.C1 nRowColSel
|
|
CTOF_DEL --- 0.371 SLICE_64.C1 to SLICE_64.F1 SLICE_64
|
|
ROUTE 1 e 1.441 SLICE_64.F1 to 99.PADDO RA_c_4
|
|
DOPAD_DEL --- 3.636 99.PADDO to 99.PAD RA[4]
|
|
--------
|
|
6.569 (69.5% logic, 30.5% route), 3 logic levels.
|
|
|
|
Report: 9.073ns is the minimum offset for this preference.
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_0_23"></A>Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 2.547ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q nRowColSel_375 (from RCLK_c +)
|
|
Destination: Port Pad RA[3]
|
|
|
|
Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
2.504ns delay RCLK to SLICE_64 and
|
|
7.449ns delay SLICE_64 to RA[3] (totaling 9.953ns) meets
|
|
12.500ns offset RCLK to RA[3] by 2.547ns
|
|
|
|
Physical Path Details:
|
|
|
|
Clock path RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
|
|
ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c
|
|
--------
|
|
2.504 (42.5% logic, 57.5% route), 1 logic levels.
|
|
|
|
Data path SLICE_64 to RA[3]:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
|
|
ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_94.C1 nRowColSel
|
|
CTOF_DEL --- 0.371 SLICE_94.C1 to SLICE_94.F1 SLICE_94
|
|
ROUTE 1 e 1.441 SLICE_94.F1 to 97.PADDO RA_c_3
|
|
DOPAD_DEL --- 3.636 97.PADDO to 97.PAD RA[3]
|
|
--------
|
|
7.449 (61.3% logic, 38.7% route), 3 logic levels.
|
|
|
|
Report: 9.953ns is the minimum offset for this preference.
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_0_24"></A>Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 2.547ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q nRowColSel_375 (from RCLK_c +)
|
|
Destination: Port Pad RA[2]
|
|
|
|
Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
2.504ns delay RCLK to SLICE_64 and
|
|
7.449ns delay SLICE_64 to RA[2] (totaling 9.953ns) meets
|
|
12.500ns offset RCLK to RA[2] by 2.547ns
|
|
|
|
Physical Path Details:
|
|
|
|
Clock path RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
|
|
ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c
|
|
--------
|
|
2.504 (42.5% logic, 57.5% route), 1 logic levels.
|
|
|
|
Data path SLICE_64 to RA[2]:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
|
|
ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_95.C1 nRowColSel
|
|
CTOF_DEL --- 0.371 SLICE_95.C1 to SLICE_95.F1 SLICE_95
|
|
ROUTE 1 e 1.441 SLICE_95.F1 to 94.PADDO RA_c_2
|
|
DOPAD_DEL --- 3.636 94.PADDO to 94.PAD RA[2]
|
|
--------
|
|
7.449 (61.3% logic, 38.7% route), 3 logic levels.
|
|
|
|
Report: 9.953ns is the minimum offset for this preference.
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_0_25"></A>Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 2.547ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q nRowColSel_375 (from RCLK_c +)
|
|
Destination: Port Pad RA[1]
|
|
|
|
Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
2.504ns delay RCLK to SLICE_64 and
|
|
7.449ns delay SLICE_64 to RA[1] (totaling 9.953ns) meets
|
|
12.500ns offset RCLK to RA[1] by 2.547ns
|
|
|
|
Physical Path Details:
|
|
|
|
Clock path RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
|
|
ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c
|
|
--------
|
|
2.504 (42.5% logic, 57.5% route), 1 logic levels.
|
|
|
|
Data path SLICE_64 to RA[1]:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
|
|
ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_94.C0 nRowColSel
|
|
CTOF_DEL --- 0.371 SLICE_94.C0 to SLICE_94.F0 SLICE_94
|
|
ROUTE 1 e 1.441 SLICE_94.F0 to 89.PADDO RA_c_1
|
|
DOPAD_DEL --- 3.636 89.PADDO to 89.PAD RA[1]
|
|
--------
|
|
7.449 (61.3% logic, 38.7% route), 3 logic levels.
|
|
|
|
Report: 9.953ns is the minimum offset for this preference.
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_0_26"></A>Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 2.547ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q nRowColSel_375 (from RCLK_c +)
|
|
Destination: Port Pad RA[0]
|
|
|
|
Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
2.504ns delay RCLK to SLICE_64 and
|
|
7.449ns delay SLICE_64 to RA[0] (totaling 9.953ns) meets
|
|
12.500ns offset RCLK to RA[0] by 2.547ns
|
|
|
|
Physical Path Details:
|
|
|
|
Clock path RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
|
|
ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c
|
|
--------
|
|
2.504 (42.5% logic, 57.5% route), 1 logic levels.
|
|
|
|
Data path SLICE_64 to RA[0]:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
|
|
ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_92.C1 nRowColSel
|
|
CTOF_DEL --- 0.371 SLICE_92.C1 to SLICE_92.F1 SLICE_92
|
|
ROUTE 1 e 1.441 SLICE_92.F1 to 98.PADDO RA_c_0
|
|
DOPAD_DEL --- 3.636 98.PADDO to 98.PAD RA[0]
|
|
--------
|
|
7.449 (61.3% logic, 38.7% route), 3 logic levels.
|
|
|
|
Report: 9.953ns is the minimum offset for this preference.
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_0_27"></A>Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 4.359ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q nRCS_369 (from RCLK_c +)
|
|
Destination: Port Pad nRCS
|
|
|
|
Data Path Delay: 5.637ns (74.4% logic, 25.6% route), 2 logic levels.
|
|
|
|
Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
2.504ns delay RCLK to SLICE_60 and
|
|
5.637ns delay SLICE_60 to nRCS (totaling 8.141ns) meets
|
|
12.500ns offset RCLK to nRCS by 4.359ns
|
|
|
|
Physical Path Details:
|
|
|
|
Clock path RCLK to SLICE_60:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
|
|
ROUTE 39 e 1.441 86.PADDI to SLICE_60.CLK RCLK_c
|
|
--------
|
|
2.504 (42.5% logic, 57.5% route), 1 logic levels.
|
|
|
|
Data path SLICE_60 to nRCS:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 SLICE_60.CLK to SLICE_60.Q0 SLICE_60 (from RCLK_c)
|
|
ROUTE 1 e 1.441 SLICE_60.Q0 to 77.PADDO nRCS_c
|
|
DOPAD_DEL --- 3.636 77.PADDO to 77.PAD nRCS
|
|
--------
|
|
5.637 (74.4% logic, 25.6% route), 2 logic levels.
|
|
|
|
Report: 8.141ns is the minimum offset for this preference.
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_0_28"></A>Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 4.359ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q RCKE_368 (from RCLK_c +)
|
|
Destination: Port Pad RCKE
|
|
|
|
Data Path Delay: 5.637ns (74.4% logic, 25.6% route), 2 logic levels.
|
|
|
|
Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
2.504ns delay RCLK to SLICE_34 and
|
|
5.637ns delay SLICE_34 to RCKE (totaling 8.141ns) meets
|
|
12.500ns offset RCLK to RCKE by 4.359ns
|
|
|
|
Physical Path Details:
|
|
|
|
Clock path RCLK to SLICE_34:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
|
|
ROUTE 39 e 1.441 86.PADDI to SLICE_34.CLK RCLK_c
|
|
--------
|
|
2.504 (42.5% logic, 57.5% route), 1 logic levels.
|
|
|
|
Data path SLICE_34 to RCKE:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 SLICE_34.CLK to SLICE_34.Q0 SLICE_34 (from RCLK_c)
|
|
ROUTE 4 e 1.441 SLICE_34.Q0 to 82.PADDO RCKE_c
|
|
DOPAD_DEL --- 3.636 82.PADDO to 82.PAD RCKE
|
|
--------
|
|
5.637 (74.4% logic, 25.6% route), 2 logic levels.
|
|
|
|
Report: 8.141ns is the minimum offset for this preference.
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_0_29"></A>Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 4.359ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q nRWE_372 (from RCLK_c +)
|
|
Destination: Port Pad nRWE
|
|
|
|
Data Path Delay: 5.637ns (74.4% logic, 25.6% route), 2 logic levels.
|
|
|
|
Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
2.504ns delay RCLK to SLICE_63 and
|
|
5.637ns delay SLICE_63 to nRWE (totaling 8.141ns) meets
|
|
12.500ns offset RCLK to nRWE by 4.359ns
|
|
|
|
Physical Path Details:
|
|
|
|
Clock path RCLK to SLICE_63:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
|
|
ROUTE 39 e 1.441 86.PADDI to SLICE_63.CLK RCLK_c
|
|
--------
|
|
2.504 (42.5% logic, 57.5% route), 1 logic levels.
|
|
|
|
Data path SLICE_63 to nRWE:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c)
|
|
ROUTE 1 e 1.441 SLICE_63.Q0 to 72.PADDO nRWE_c
|
|
DOPAD_DEL --- 3.636 72.PADDO to 72.PAD nRWE
|
|
--------
|
|
5.637 (74.4% logic, 25.6% route), 2 logic levels.
|
|
|
|
Report: 8.141ns is the minimum offset for this preference.
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_0_30"></A>Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 4.359ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q nRRAS_370 (from RCLK_c +)
|
|
Destination: Port Pad nRRAS
|
|
|
|
Data Path Delay: 5.637ns (74.4% logic, 25.6% route), 2 logic levels.
|
|
|
|
Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
2.504ns delay RCLK to SLICE_61 and
|
|
5.637ns delay SLICE_61 to nRRAS (totaling 8.141ns) meets
|
|
12.500ns offset RCLK to nRRAS by 4.359ns
|
|
|
|
Physical Path Details:
|
|
|
|
Clock path RCLK to SLICE_61:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
|
|
ROUTE 39 e 1.441 86.PADDI to SLICE_61.CLK RCLK_c
|
|
--------
|
|
2.504 (42.5% logic, 57.5% route), 1 logic levels.
|
|
|
|
Data path SLICE_61 to nRRAS:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 SLICE_61.CLK to SLICE_61.Q0 SLICE_61 (from RCLK_c)
|
|
ROUTE 2 e 1.441 SLICE_61.Q0 to 73.PADDO nRRAS_c
|
|
DOPAD_DEL --- 3.636 73.PADDO to 73.PAD nRRAS
|
|
--------
|
|
5.637 (74.4% logic, 25.6% route), 2 logic levels.
|
|
|
|
Report: 8.141ns is the minimum offset for this preference.
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_0_31"></A>Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 4.359ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q nRCAS_371 (from RCLK_c +)
|
|
Destination: Port Pad nRCAS
|
|
|
|
Data Path Delay: 5.637ns (74.4% logic, 25.6% route), 2 logic levels.
|
|
|
|
Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
2.504ns delay RCLK to SLICE_58 and
|
|
5.637ns delay SLICE_58 to nRCAS (totaling 8.141ns) meets
|
|
12.500ns offset RCLK to nRCAS by 4.359ns
|
|
|
|
Physical Path Details:
|
|
|
|
Clock path RCLK to SLICE_58:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
|
|
ROUTE 39 e 1.441 86.PADDI to SLICE_58.CLK RCLK_c
|
|
--------
|
|
2.504 (42.5% logic, 57.5% route), 1 logic levels.
|
|
|
|
Data path SLICE_58 to nRCAS:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 SLICE_58.CLK to SLICE_58.Q0 SLICE_58 (from RCLK_c)
|
|
ROUTE 1 e 1.441 SLICE_58.Q0 to 78.PADDO nRCAS_c
|
|
DOPAD_DEL --- 3.636 78.PADDO to 78.PAD nRCAS
|
|
--------
|
|
5.637 (74.4% logic, 25.6% route), 2 logic levels.
|
|
|
|
Report: 8.141ns is the minimum offset for this preference.
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_0_32"></A>Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 2.547ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q nRowColSel_375 (from RCLK_c +)
|
|
Destination: Port Pad RDQMH
|
|
|
|
Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
2.504ns delay RCLK to SLICE_64 and
|
|
7.449ns delay SLICE_64 to RDQMH (totaling 9.953ns) meets
|
|
12.500ns offset RCLK to RDQMH by 2.547ns
|
|
|
|
Physical Path Details:
|
|
|
|
Clock path RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
|
|
ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c
|
|
--------
|
|
2.504 (42.5% logic, 57.5% route), 1 logic levels.
|
|
|
|
Data path SLICE_64 to RDQMH:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
|
|
ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_88.B0 nRowColSel
|
|
CTOF_DEL --- 0.371 SLICE_88.B0 to SLICE_88.F0 SLICE_88
|
|
ROUTE 1 e 1.441 SLICE_88.F0 to 76.PADDO RDQMH_c
|
|
DOPAD_DEL --- 3.636 76.PADDO to 76.PAD RDQMH
|
|
--------
|
|
7.449 (61.3% logic, 38.7% route), 3 logic levels.
|
|
|
|
Report: 9.953ns is the minimum offset for this preference.
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_0_33"></A>Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 2.547ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q nRowColSel_375 (from RCLK_c +)
|
|
Destination: Port Pad RDQML
|
|
|
|
Data Path Delay: 7.449ns (61.3% logic, 38.7% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 2.504ns (42.5% logic, 57.5% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
2.504ns delay RCLK to SLICE_64 and
|
|
7.449ns delay SLICE_64 to RDQML (totaling 9.953ns) meets
|
|
12.500ns offset RCLK to RDQML by 2.547ns
|
|
|
|
Physical Path Details:
|
|
|
|
Clock path RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 1.063 86.PAD to 86.PADDI RCLK
|
|
ROUTE 39 e 1.441 86.PADDI to SLICE_64.CLK RCLK_c
|
|
--------
|
|
2.504 (42.5% logic, 57.5% route), 1 logic levels.
|
|
|
|
Data path SLICE_64 to RDQML:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.560 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
|
|
ROUTE 13 e 1.441 SLICE_64.Q0 to SLICE_92.B0 nRowColSel
|
|
CTOF_DEL --- 0.371 SLICE_92.B0 to SLICE_92.F0 SLICE_92
|
|
ROUTE 1 e 1.441 SLICE_92.F0 to 61.PADDO RDQML_c
|
|
DOPAD_DEL --- 3.636 61.PADDO to 61.PAD RDQML
|
|
--------
|
|
7.449 (61.3% logic, 38.7% route), 3 logic levels.
|
|
|
|
Report: 9.953ns is the minimum offset for this preference.
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_0_34"></A>Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_0_35"></A>Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_0_36"></A>Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_0_37"></A>Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_0_38"></A>Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_0_39"></A>Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_0_40"></A>Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
<A name="mtw1_set_rs"></A><B><U><big>Report Summary</big></U></B>
|
|
--------------
|
|
----------------------------------------------------------------------------
|
|
Preference | Constraint| Actual|Levels
|
|
----------------------------------------------------------------------------
|
|
| | |
|
|
PERIOD NET "PHI2_c" 350.000000 ns ; | 350.000 ns| 26.276 ns| 7
|
|
| | |
|
|
PERIOD NET "nCCAS_c" 350.000000 ns ; | 350.000 ns| 2.000 ns| 0
|
|
| | |
|
|
PERIOD NET "nCRAS_c" 350.000000 ns ; | 350.000 ns| 2.000 ns| 0
|
|
| | |
|
|
PERIOD NET "RCLK_c" 16.000000 ns ; | 16.000 ns| 10.425 ns| 6
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "Dout[0]" 12.500000 | | |
|
|
ns CLKPORT "RCLK" ; | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "Dout[7]" 12.500000 | | |
|
|
ns CLKPORT "RCLK" ; | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "Dout[6]" 12.500000 | | |
|
|
ns CLKPORT "RCLK" ; | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "Dout[5]" 12.500000 | | |
|
|
ns CLKPORT "RCLK" ; | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "Dout[4]" 12.500000 | | |
|
|
ns CLKPORT "RCLK" ; | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "Dout[3]" 12.500000 | | |
|
|
ns CLKPORT "RCLK" ; | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "Dout[2]" 12.500000 | | |
|
|
ns CLKPORT "RCLK" ; | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "Dout[1]" 12.500000 | | |
|
|
ns CLKPORT "RCLK" ; | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; | 12.500 ns| 8.141 ns| 2
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; | 12.500 ns| 9.073 ns| 3
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3
|
|
| | |
|
|
CLOCK_TO_OUT PORT "nRCS" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; | 12.500 ns| 8.141 ns| 2
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RCKE" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; | 12.500 ns| 8.141 ns| 2
|
|
| | |
|
|
CLOCK_TO_OUT PORT "nRWE" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; | 12.500 ns| 8.141 ns| 2
|
|
| | |
|
|
CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; | 12.500 ns| 8.141 ns| 2
|
|
| | |
|
|
CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; | 12.500 ns| 8.141 ns| 2
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RDQML" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; | 12.500 ns| 9.953 ns| 3
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; | -| -| 0
|
|
| | |
|
|
CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns | | |
|
|
CLKPORT "RCLK" ; | -| -| 0
|
|
| | |
|
|
----------------------------------------------------------------------------
|
|
|
|
|
|
All preferences were met.
|
|
|
|
|
|
<A name="mtw1_set_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
|
|
------------------------
|
|
|
|
Found 4 clocks:
|
|
|
|
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9
|
|
No transfer within this clock domain is found
|
|
|
|
Data transfers from:
|
|
Clock Domain: RCLK_c Source: RCLK.PAD
|
|
Not reported because source and destination domains are unrelated.
|
|
To report these transfers please refer to preference CLKSKEWDIFF to define
|
|
external clock skew between clock ports.
|
|
|
|
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 7
|
|
No transfer within this clock domain is found
|
|
|
|
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 39
|
|
Covered under: PERIOD NET "RCLK_c" 16.000000 ns ;
|
|
|
|
Data transfers from:
|
|
Clock Domain: nCRAS_c Source: nCRAS.PAD
|
|
Not reported because source and destination domains are unrelated.
|
|
To report these transfers please refer to preference CLKSKEWDIFF to define
|
|
external clock skew between clock ports.
|
|
|
|
Clock Domain: PHI2_c Source: PHI2.PAD
|
|
Not reported because source and destination domains are unrelated.
|
|
To report these transfers please refer to preference CLKSKEWDIFF to define
|
|
external clock skew between clock ports.
|
|
|
|
Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14
|
|
Covered under: PERIOD NET "PHI2_c" 350.000000 ns ;
|
|
|
|
Data transfers from:
|
|
Clock Domain: RCLK_c Source: RCLK.PAD
|
|
Not reported because source and destination domains are unrelated.
|
|
To report these transfers please refer to preference CLKSKEWDIFF to define
|
|
external clock skew between clock ports.
|
|
|
|
|
|
<A name="mtw1_set_ts"></A><B><U><big>Timing summary (Setup):</big></U></B>
|
|
---------------
|
|
|
|
Timing errors: 0 Score: 0
|
|
Cumulative negative slack: 0
|
|
|
|
Constraints cover 526 paths, 6 nets, and 420 connections (67.96% coverage)
|
|
|
|
--------------------------------------------------------------------------------
|
|
<A name="Map_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2</big></U></B>
|
|
Mon Aug 16 21:32:27 2021
|
|
|
|
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
|
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
|
Copyright (c) 2001 Agere Systems All rights reserved.
|
|
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
|
|
|
|
<A name="mtw1_hold_ri"></A><B><U><big>Report Information</big></U></B>
|
|
------------------
|
|
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2GS_LCMXO256C_impl1.tw1 -gui -msgset C:/Users/Dog/Documents/GitHub/RAM2GS/CPLD/LCMXO/LCMXO256C/promote.xml RAM2GS_LCMXO256C_impl1_map.ncd RAM2GS_LCMXO256C_impl1.prf
|
|
Design file: ram2gs_lcmxo256c_impl1_map.ncd
|
|
Preference file: ram2gs_lcmxo256c_impl1.prf
|
|
Device,speed: LCMXO256C,M
|
|
Report level: verbose report, limited to 1 item per preference
|
|
--------------------------------------------------------------------------------
|
|
|
|
<A name="mtw1_hold_ps"></A><B><U><big>Preference Summary</big></U></B>
|
|
|
|
<LI><A href='#map_twr_pref_1_0' Target='right'>PERIOD NET "PHI2_c" 350.000000 ns (0 errors)</A></LI> 113 items scored, 0 timing errors detected.
|
|
|
|
<LI><A href='#map_twr_pref_1_1' Target='right'>PERIOD NET "nCCAS_c" 350.000000 ns (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
|
|
|
|
<LI><A href='#map_twr_pref_1_2' Target='right'>PERIOD NET "nCRAS_c" 350.000000 ns (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
|
|
|
|
<LI><A href='#map_twr_pref_1_3' Target='right'>PERIOD NET "RCLK_c" 16.000000 ns (0 errors)</A></LI> 395 items scored, 0 timing errors detected.
|
|
|
|
<LI><A href='#map_twr_pref_1_4' Target='right'>CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
|
|
|
|
<LI><A href='#map_twr_pref_1_5' Target='right'>CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
|
|
|
|
<LI><A href='#map_twr_pref_1_6' Target='right'>CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
|
|
|
|
<LI><A href='#map_twr_pref_1_7' Target='right'>CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
|
|
|
|
<LI><A href='#map_twr_pref_1_8' Target='right'>CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
|
|
|
|
<LI><A href='#map_twr_pref_1_9' Target='right'>CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
|
|
|
|
<LI><A href='#map_twr_pref_1_10' Target='right'>CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
|
|
|
|
<LI><A href='#map_twr_pref_1_11' Target='right'>CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
|
|
|
|
<LI><A href='#map_twr_pref_1_12' Target='right'>CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
|
|
|
|
<LI><A href='#map_twr_pref_1_13' Target='right'>CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
|
|
|
|
<LI><A href='#map_twr_pref_1_14' Target='right'>CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
|
|
|
|
<LI><A href='#map_twr_pref_1_15' Target='right'>CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
|
|
|
|
<LI><A href='#map_twr_pref_1_16' Target='right'>CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
|
|
|
|
<LI><A href='#map_twr_pref_1_17' Target='right'>CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
|
|
|
|
<LI><A href='#map_twr_pref_1_18' Target='right'>CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
|
|
|
|
<LI><A href='#map_twr_pref_1_19' Target='right'>CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
|
|
|
|
<LI><A href='#map_twr_pref_1_20' Target='right'>CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
|
|
|
|
<LI><A href='#map_twr_pref_1_21' Target='right'>CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
|
|
|
|
<LI><A href='#map_twr_pref_1_22' Target='right'>CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
|
|
|
|
<LI><A href='#map_twr_pref_1_23' Target='right'>CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
|
|
|
|
<LI><A href='#map_twr_pref_1_24' Target='right'>CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
|
|
|
|
<LI><A href='#map_twr_pref_1_25' Target='right'>CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
|
|
|
|
<LI><A href='#map_twr_pref_1_26' Target='right'>CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
|
|
|
|
<LI><A href='#map_twr_pref_1_27' Target='right'>CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
|
|
|
|
<LI><A href='#map_twr_pref_1_28' Target='right'>CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
|
|
|
|
<LI><A href='#map_twr_pref_1_29' Target='right'>CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
|
|
|
|
<LI><A href='#map_twr_pref_1_30' Target='right'>CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
|
|
|
|
<LI><A href='#map_twr_pref_1_31' Target='right'>CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
|
|
|
|
<LI><A href='#map_twr_pref_1_32' Target='right'>CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
|
|
|
|
<LI><A href='#map_twr_pref_1_33' Target='right'>CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 1 item scored, 0 timing errors detected.
|
|
|
|
<LI><A href='#map_twr_pref_1_34' Target='right'>CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
|
|
|
|
<LI><A href='#map_twr_pref_1_35' Target='right'>CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
|
|
|
|
<LI><A href='#map_twr_pref_1_36' Target='right'>CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
|
|
|
|
<LI><A href='#map_twr_pref_1_37' Target='right'>CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
|
|
|
|
<LI><A href='#map_twr_pref_1_38' Target='right'>CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
|
|
|
|
<LI><A href='#map_twr_pref_1_39' Target='right'>CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
|
|
|
|
<LI><A href='#map_twr_pref_1_40' Target='right'>CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
|
|
|
|
BLOCK ASYNCPATHS
|
|
BLOCK RESETPATHS
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Derating parameters
|
|
-------------------
|
|
Voltage: 3.300 V
|
|
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_1_0"></A>Preference: PERIOD NET "PHI2_c" 350.000000 ns ;
|
|
113 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 0.485ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q ADSubmitted_380 (from PHI2_c -)
|
|
Destination: FF Data in ADSubmitted_380 (to PHI2_c -)
|
|
|
|
Delay: 0.462ns (56.7% logic, 43.3% route), 2 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.462ns physical path delay SLICE_9 to SLICE_9 meets
|
|
-0.023ns DIN_HLD and
|
|
0.000ns delay constraint requirement (totaling -0.023ns) by 0.485ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path SLICE_9 to SLICE_9:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.170 SLICE_9.CLK to SLICE_9.Q0 SLICE_9 (from PHI2_c)
|
|
ROUTE 2 e 0.199 SLICE_9.Q0 to SLICE_9.C0 ADSubmitted
|
|
CTOF_DEL --- 0.092 SLICE_9.C0 to SLICE_9.F0 SLICE_9
|
|
ROUTE 1 e 0.001 SLICE_9.F0 to SLICE_9.DI0 n1361 (to PHI2_c)
|
|
--------
|
|
0.462 (56.7% logic, 43.3% route), 2 logic levels.
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_1_1"></A>Preference: PERIOD NET "nCCAS_c" 350.000000 ns ;
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_1_2"></A>Preference: PERIOD NET "nCRAS_c" 350.000000 ns ;
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_1_3"></A>Preference: PERIOD NET "RCLK_c" 16.000000 ns ;
|
|
395 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 0.377ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q IS_FSM__i11 (from RCLK_c +)
|
|
Destination: FF Data in IS_FSM__i12 (to RCLK_c +)
|
|
|
|
Delay: 0.356ns (44.1% logic, 55.9% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
|
|
0.356ns physical path delay SLICE_72 to SLICE_72 meets
|
|
-0.021ns M_HLD and
|
|
0.000ns delay constraint requirement (totaling -0.021ns) by 0.377ns
|
|
|
|
Physical Path Details:
|
|
|
|
Data path SLICE_72 to SLICE_72:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.157 SLICE_72.CLK to SLICE_72.Q0 SLICE_72 (from RCLK_c)
|
|
ROUTE 1 e 0.199 SLICE_72.Q0 to SLICE_72.M1 n702 (to RCLK_c)
|
|
--------
|
|
0.356 (44.1% logic, 55.9% route), 1 logic levels.
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_1_4"></A>Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_1_5"></A>Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_1_6"></A>Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_1_7"></A>Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_1_8"></A>Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_1_9"></A>Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_1_10"></A>Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_1_11"></A>Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_1_12"></A>Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_1_13"></A>Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_1_14"></A>Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_1_15"></A>Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_1_16"></A>Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 2.559ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q RA10_373 (from RCLK_c +)
|
|
Destination: Port Pad RA[10]
|
|
|
|
Data Path Delay: 1.780ns (71.1% logic, 28.9% route), 2 logic levels.
|
|
|
|
Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
0.779ns delay RCLK to SLICE_55 and
|
|
1.780ns delay SLICE_55 to RA[10] (totaling 2.559ns) meets
|
|
0.000ns hold offset RCLK to RA[10] by 2.559ns
|
|
|
|
Physical Path Details:
|
|
|
|
Clock path RCLK to SLICE_55:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
|
|
ROUTE 39 e 0.515 86.PADDI to SLICE_55.CLK RCLK_c
|
|
--------
|
|
0.779 (33.9% logic, 66.1% route), 1 logic levels.
|
|
|
|
Data path SLICE_55 to RA[10]:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.157 SLICE_55.CLK to SLICE_55.Q0 SLICE_55 (from RCLK_c)
|
|
ROUTE 1 e 0.515 SLICE_55.Q0 to 87.PADDO n980
|
|
DOPAD_DEL --- 1.108 87.PADDO to 87.PAD RA[10]
|
|
--------
|
|
1.780 (71.1% logic, 28.9% route), 2 logic levels.
|
|
|
|
Report: 2.559ns is the maximum offset for this preference.
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_1_17"></A>Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 3.166ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q nRowColSel_375 (from RCLK_c +)
|
|
Destination: Port Pad RA[9]
|
|
|
|
Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
0.779ns delay RCLK to SLICE_64 and
|
|
2.387ns delay SLICE_64 to RA[9] (totaling 3.166ns) meets
|
|
0.000ns hold offset RCLK to RA[9] by 3.166ns
|
|
|
|
Physical Path Details:
|
|
|
|
Clock path RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
|
|
ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c
|
|
--------
|
|
0.779 (33.9% logic, 66.1% route), 1 logic levels.
|
|
|
|
Data path SLICE_64 to RA[9]:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
|
|
ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_88.C1 nRowColSel
|
|
CTOF_DEL --- 0.092 SLICE_88.C1 to SLICE_88.F1 SLICE_88
|
|
ROUTE 1 e 0.515 SLICE_88.F1 to 85.PADDO RA_c_9
|
|
DOPAD_DEL --- 1.108 85.PADDO to 85.PAD RA[9]
|
|
--------
|
|
2.387 (56.8% logic, 43.2% route), 3 logic levels.
|
|
|
|
Report: 3.166ns is the maximum offset for this preference.
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_1_18"></A>Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 3.166ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q nRowColSel_375 (from RCLK_c +)
|
|
Destination: Port Pad RA[8]
|
|
|
|
Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
0.779ns delay RCLK to SLICE_64 and
|
|
2.387ns delay SLICE_64 to RA[8] (totaling 3.166ns) meets
|
|
0.000ns hold offset RCLK to RA[8] by 3.166ns
|
|
|
|
Physical Path Details:
|
|
|
|
Clock path RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
|
|
ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c
|
|
--------
|
|
0.779 (33.9% logic, 66.1% route), 1 logic levels.
|
|
|
|
Data path SLICE_64 to RA[8]:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
|
|
ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_95.C0 nRowColSel
|
|
CTOF_DEL --- 0.092 SLICE_95.C0 to SLICE_95.F0 SLICE_95
|
|
ROUTE 1 e 0.515 SLICE_95.F0 to 96.PADDO RA_c_8
|
|
DOPAD_DEL --- 1.108 96.PADDO to 96.PAD RA[8]
|
|
--------
|
|
2.387 (56.8% logic, 43.2% route), 3 logic levels.
|
|
|
|
Report: 3.166ns is the maximum offset for this preference.
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_1_19"></A>Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 3.166ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q nRowColSel_375 (from RCLK_c +)
|
|
Destination: Port Pad RA[7]
|
|
|
|
Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
0.779ns delay RCLK to SLICE_64 and
|
|
2.387ns delay SLICE_64 to RA[7] (totaling 3.166ns) meets
|
|
0.000ns hold offset RCLK to RA[7] by 3.166ns
|
|
|
|
Physical Path Details:
|
|
|
|
Clock path RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
|
|
ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c
|
|
--------
|
|
0.779 (33.9% logic, 66.1% route), 1 logic levels.
|
|
|
|
Data path SLICE_64 to RA[7]:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
|
|
ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_97.C0 nRowColSel
|
|
CTOF_DEL --- 0.092 SLICE_97.C0 to SLICE_97.F0 SLICE_97
|
|
ROUTE 1 e 0.515 SLICE_97.F0 to 100.PADDO RA_c_7
|
|
DOPAD_DEL --- 1.108 100.PADDO to 100.PAD RA[7]
|
|
--------
|
|
2.387 (56.8% logic, 43.2% route), 3 logic levels.
|
|
|
|
Report: 3.166ns is the maximum offset for this preference.
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_1_20"></A>Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 3.166ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q nRowColSel_375 (from RCLK_c +)
|
|
Destination: Port Pad RA[6]
|
|
|
|
Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
0.779ns delay RCLK to SLICE_64 and
|
|
2.387ns delay SLICE_64 to RA[6] (totaling 3.166ns) meets
|
|
0.000ns hold offset RCLK to RA[6] by 3.166ns
|
|
|
|
Physical Path Details:
|
|
|
|
Clock path RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
|
|
ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c
|
|
--------
|
|
0.779 (33.9% logic, 66.1% route), 1 logic levels.
|
|
|
|
Data path SLICE_64 to RA[6]:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
|
|
ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_98.C0 nRowColSel
|
|
CTOF_DEL --- 0.092 SLICE_98.C0 to SLICE_98.F0 SLICE_98
|
|
ROUTE 1 e 0.515 SLICE_98.F0 to 91.PADDO RA_c_6
|
|
DOPAD_DEL --- 1.108 91.PADDO to 91.PAD RA[6]
|
|
--------
|
|
2.387 (56.8% logic, 43.2% route), 3 logic levels.
|
|
|
|
Report: 3.166ns is the maximum offset for this preference.
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_1_21"></A>Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 3.166ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q nRowColSel_375 (from RCLK_c +)
|
|
Destination: Port Pad RA[5]
|
|
|
|
Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
0.779ns delay RCLK to SLICE_64 and
|
|
2.387ns delay SLICE_64 to RA[5] (totaling 3.166ns) meets
|
|
0.000ns hold offset RCLK to RA[5] by 3.166ns
|
|
|
|
Physical Path Details:
|
|
|
|
Clock path RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
|
|
ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c
|
|
--------
|
|
0.779 (33.9% logic, 66.1% route), 1 logic levels.
|
|
|
|
Data path SLICE_64 to RA[5]:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
|
|
ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_98.C1 nRowColSel
|
|
CTOF_DEL --- 0.092 SLICE_98.C1 to SLICE_98.F1 SLICE_98
|
|
ROUTE 1 e 0.515 SLICE_98.F1 to 95.PADDO RA_c_5
|
|
DOPAD_DEL --- 1.108 95.PADDO to 95.PAD RA[5]
|
|
--------
|
|
2.387 (56.8% logic, 43.2% route), 3 logic levels.
|
|
|
|
Report: 3.166ns is the maximum offset for this preference.
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_1_22"></A>Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 2.850ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q nRowColSel_375 (from RCLK_c +)
|
|
Destination: Port Pad RA[4]
|
|
|
|
Data Path Delay: 2.071ns (65.5% logic, 34.5% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
0.779ns delay RCLK to SLICE_64 and
|
|
2.071ns delay SLICE_64 to RA[4] (totaling 2.850ns) meets
|
|
0.000ns hold offset RCLK to RA[4] by 2.850ns
|
|
|
|
Physical Path Details:
|
|
|
|
Clock path RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
|
|
ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c
|
|
--------
|
|
0.779 (33.9% logic, 66.1% route), 1 logic levels.
|
|
|
|
Data path SLICE_64 to RA[4]:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
|
|
ROUTE 13 e 0.199 SLICE_64.Q0 to SLICE_64.C1 nRowColSel
|
|
CTOF_DEL --- 0.092 SLICE_64.C1 to SLICE_64.F1 SLICE_64
|
|
ROUTE 1 e 0.515 SLICE_64.F1 to 99.PADDO RA_c_4
|
|
DOPAD_DEL --- 1.108 99.PADDO to 99.PAD RA[4]
|
|
--------
|
|
2.071 (65.5% logic, 34.5% route), 3 logic levels.
|
|
|
|
Report: 2.850ns is the maximum offset for this preference.
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_1_23"></A>Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 3.166ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q nRowColSel_375 (from RCLK_c +)
|
|
Destination: Port Pad RA[3]
|
|
|
|
Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
0.779ns delay RCLK to SLICE_64 and
|
|
2.387ns delay SLICE_64 to RA[3] (totaling 3.166ns) meets
|
|
0.000ns hold offset RCLK to RA[3] by 3.166ns
|
|
|
|
Physical Path Details:
|
|
|
|
Clock path RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
|
|
ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c
|
|
--------
|
|
0.779 (33.9% logic, 66.1% route), 1 logic levels.
|
|
|
|
Data path SLICE_64 to RA[3]:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
|
|
ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_94.C1 nRowColSel
|
|
CTOF_DEL --- 0.092 SLICE_94.C1 to SLICE_94.F1 SLICE_94
|
|
ROUTE 1 e 0.515 SLICE_94.F1 to 97.PADDO RA_c_3
|
|
DOPAD_DEL --- 1.108 97.PADDO to 97.PAD RA[3]
|
|
--------
|
|
2.387 (56.8% logic, 43.2% route), 3 logic levels.
|
|
|
|
Report: 3.166ns is the maximum offset for this preference.
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_1_24"></A>Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 3.166ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q nRowColSel_375 (from RCLK_c +)
|
|
Destination: Port Pad RA[2]
|
|
|
|
Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
0.779ns delay RCLK to SLICE_64 and
|
|
2.387ns delay SLICE_64 to RA[2] (totaling 3.166ns) meets
|
|
0.000ns hold offset RCLK to RA[2] by 3.166ns
|
|
|
|
Physical Path Details:
|
|
|
|
Clock path RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
|
|
ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c
|
|
--------
|
|
0.779 (33.9% logic, 66.1% route), 1 logic levels.
|
|
|
|
Data path SLICE_64 to RA[2]:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
|
|
ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_95.C1 nRowColSel
|
|
CTOF_DEL --- 0.092 SLICE_95.C1 to SLICE_95.F1 SLICE_95
|
|
ROUTE 1 e 0.515 SLICE_95.F1 to 94.PADDO RA_c_2
|
|
DOPAD_DEL --- 1.108 94.PADDO to 94.PAD RA[2]
|
|
--------
|
|
2.387 (56.8% logic, 43.2% route), 3 logic levels.
|
|
|
|
Report: 3.166ns is the maximum offset for this preference.
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_1_25"></A>Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 3.166ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q nRowColSel_375 (from RCLK_c +)
|
|
Destination: Port Pad RA[1]
|
|
|
|
Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
0.779ns delay RCLK to SLICE_64 and
|
|
2.387ns delay SLICE_64 to RA[1] (totaling 3.166ns) meets
|
|
0.000ns hold offset RCLK to RA[1] by 3.166ns
|
|
|
|
Physical Path Details:
|
|
|
|
Clock path RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
|
|
ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c
|
|
--------
|
|
0.779 (33.9% logic, 66.1% route), 1 logic levels.
|
|
|
|
Data path SLICE_64 to RA[1]:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
|
|
ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_94.C0 nRowColSel
|
|
CTOF_DEL --- 0.092 SLICE_94.C0 to SLICE_94.F0 SLICE_94
|
|
ROUTE 1 e 0.515 SLICE_94.F0 to 89.PADDO RA_c_1
|
|
DOPAD_DEL --- 1.108 89.PADDO to 89.PAD RA[1]
|
|
--------
|
|
2.387 (56.8% logic, 43.2% route), 3 logic levels.
|
|
|
|
Report: 3.166ns is the maximum offset for this preference.
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_1_26"></A>Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 3.166ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q nRowColSel_375 (from RCLK_c +)
|
|
Destination: Port Pad RA[0]
|
|
|
|
Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
0.779ns delay RCLK to SLICE_64 and
|
|
2.387ns delay SLICE_64 to RA[0] (totaling 3.166ns) meets
|
|
0.000ns hold offset RCLK to RA[0] by 3.166ns
|
|
|
|
Physical Path Details:
|
|
|
|
Clock path RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
|
|
ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c
|
|
--------
|
|
0.779 (33.9% logic, 66.1% route), 1 logic levels.
|
|
|
|
Data path SLICE_64 to RA[0]:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
|
|
ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_92.C1 nRowColSel
|
|
CTOF_DEL --- 0.092 SLICE_92.C1 to SLICE_92.F1 SLICE_92
|
|
ROUTE 1 e 0.515 SLICE_92.F1 to 98.PADDO RA_c_0
|
|
DOPAD_DEL --- 1.108 98.PADDO to 98.PAD RA[0]
|
|
--------
|
|
2.387 (56.8% logic, 43.2% route), 3 logic levels.
|
|
|
|
Report: 3.166ns is the maximum offset for this preference.
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_1_27"></A>Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 2.559ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q nRCS_369 (from RCLK_c +)
|
|
Destination: Port Pad nRCS
|
|
|
|
Data Path Delay: 1.780ns (71.1% logic, 28.9% route), 2 logic levels.
|
|
|
|
Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
0.779ns delay RCLK to SLICE_60 and
|
|
1.780ns delay SLICE_60 to nRCS (totaling 2.559ns) meets
|
|
0.000ns hold offset RCLK to nRCS by 2.559ns
|
|
|
|
Physical Path Details:
|
|
|
|
Clock path RCLK to SLICE_60:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
|
|
ROUTE 39 e 0.515 86.PADDI to SLICE_60.CLK RCLK_c
|
|
--------
|
|
0.779 (33.9% logic, 66.1% route), 1 logic levels.
|
|
|
|
Data path SLICE_60 to nRCS:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.157 SLICE_60.CLK to SLICE_60.Q0 SLICE_60 (from RCLK_c)
|
|
ROUTE 1 e 0.515 SLICE_60.Q0 to 77.PADDO nRCS_c
|
|
DOPAD_DEL --- 1.108 77.PADDO to 77.PAD nRCS
|
|
--------
|
|
1.780 (71.1% logic, 28.9% route), 2 logic levels.
|
|
|
|
Report: 2.559ns is the maximum offset for this preference.
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_1_28"></A>Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 2.559ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q RCKE_368 (from RCLK_c +)
|
|
Destination: Port Pad RCKE
|
|
|
|
Data Path Delay: 1.780ns (71.1% logic, 28.9% route), 2 logic levels.
|
|
|
|
Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
0.779ns delay RCLK to SLICE_34 and
|
|
1.780ns delay SLICE_34 to RCKE (totaling 2.559ns) meets
|
|
0.000ns hold offset RCLK to RCKE by 2.559ns
|
|
|
|
Physical Path Details:
|
|
|
|
Clock path RCLK to SLICE_34:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
|
|
ROUTE 39 e 0.515 86.PADDI to SLICE_34.CLK RCLK_c
|
|
--------
|
|
0.779 (33.9% logic, 66.1% route), 1 logic levels.
|
|
|
|
Data path SLICE_34 to RCKE:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.157 SLICE_34.CLK to SLICE_34.Q0 SLICE_34 (from RCLK_c)
|
|
ROUTE 4 e 0.515 SLICE_34.Q0 to 82.PADDO RCKE_c
|
|
DOPAD_DEL --- 1.108 82.PADDO to 82.PAD RCKE
|
|
--------
|
|
1.780 (71.1% logic, 28.9% route), 2 logic levels.
|
|
|
|
Report: 2.559ns is the maximum offset for this preference.
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_1_29"></A>Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 2.559ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q nRWE_372 (from RCLK_c +)
|
|
Destination: Port Pad nRWE
|
|
|
|
Data Path Delay: 1.780ns (71.1% logic, 28.9% route), 2 logic levels.
|
|
|
|
Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
0.779ns delay RCLK to SLICE_63 and
|
|
1.780ns delay SLICE_63 to nRWE (totaling 2.559ns) meets
|
|
0.000ns hold offset RCLK to nRWE by 2.559ns
|
|
|
|
Physical Path Details:
|
|
|
|
Clock path RCLK to SLICE_63:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
|
|
ROUTE 39 e 0.515 86.PADDI to SLICE_63.CLK RCLK_c
|
|
--------
|
|
0.779 (33.9% logic, 66.1% route), 1 logic levels.
|
|
|
|
Data path SLICE_63 to nRWE:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.157 SLICE_63.CLK to SLICE_63.Q0 SLICE_63 (from RCLK_c)
|
|
ROUTE 1 e 0.515 SLICE_63.Q0 to 72.PADDO nRWE_c
|
|
DOPAD_DEL --- 1.108 72.PADDO to 72.PAD nRWE
|
|
--------
|
|
1.780 (71.1% logic, 28.9% route), 2 logic levels.
|
|
|
|
Report: 2.559ns is the maximum offset for this preference.
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_1_30"></A>Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 2.559ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q nRRAS_370 (from RCLK_c +)
|
|
Destination: Port Pad nRRAS
|
|
|
|
Data Path Delay: 1.780ns (71.1% logic, 28.9% route), 2 logic levels.
|
|
|
|
Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
0.779ns delay RCLK to SLICE_61 and
|
|
1.780ns delay SLICE_61 to nRRAS (totaling 2.559ns) meets
|
|
0.000ns hold offset RCLK to nRRAS by 2.559ns
|
|
|
|
Physical Path Details:
|
|
|
|
Clock path RCLK to SLICE_61:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
|
|
ROUTE 39 e 0.515 86.PADDI to SLICE_61.CLK RCLK_c
|
|
--------
|
|
0.779 (33.9% logic, 66.1% route), 1 logic levels.
|
|
|
|
Data path SLICE_61 to nRRAS:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.157 SLICE_61.CLK to SLICE_61.Q0 SLICE_61 (from RCLK_c)
|
|
ROUTE 2 e 0.515 SLICE_61.Q0 to 73.PADDO nRRAS_c
|
|
DOPAD_DEL --- 1.108 73.PADDO to 73.PAD nRRAS
|
|
--------
|
|
1.780 (71.1% logic, 28.9% route), 2 logic levels.
|
|
|
|
Report: 2.559ns is the maximum offset for this preference.
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_1_31"></A>Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 2.559ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q nRCAS_371 (from RCLK_c +)
|
|
Destination: Port Pad nRCAS
|
|
|
|
Data Path Delay: 1.780ns (71.1% logic, 28.9% route), 2 logic levels.
|
|
|
|
Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
0.779ns delay RCLK to SLICE_58 and
|
|
1.780ns delay SLICE_58 to nRCAS (totaling 2.559ns) meets
|
|
0.000ns hold offset RCLK to nRCAS by 2.559ns
|
|
|
|
Physical Path Details:
|
|
|
|
Clock path RCLK to SLICE_58:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
|
|
ROUTE 39 e 0.515 86.PADDI to SLICE_58.CLK RCLK_c
|
|
--------
|
|
0.779 (33.9% logic, 66.1% route), 1 logic levels.
|
|
|
|
Data path SLICE_58 to nRCAS:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.157 SLICE_58.CLK to SLICE_58.Q0 SLICE_58 (from RCLK_c)
|
|
ROUTE 1 e 0.515 SLICE_58.Q0 to 78.PADDO nRCAS_c
|
|
DOPAD_DEL --- 1.108 78.PADDO to 78.PAD nRCAS
|
|
--------
|
|
1.780 (71.1% logic, 28.9% route), 2 logic levels.
|
|
|
|
Report: 2.559ns is the maximum offset for this preference.
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_1_32"></A>Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 3.166ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q nRowColSel_375 (from RCLK_c +)
|
|
Destination: Port Pad RDQMH
|
|
|
|
Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
0.779ns delay RCLK to SLICE_64 and
|
|
2.387ns delay SLICE_64 to RDQMH (totaling 3.166ns) meets
|
|
0.000ns hold offset RCLK to RDQMH by 3.166ns
|
|
|
|
Physical Path Details:
|
|
|
|
Clock path RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
|
|
ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c
|
|
--------
|
|
0.779 (33.9% logic, 66.1% route), 1 logic levels.
|
|
|
|
Data path SLICE_64 to RDQMH:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
|
|
ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_88.B0 nRowColSel
|
|
CTOF_DEL --- 0.092 SLICE_88.B0 to SLICE_88.F0 SLICE_88
|
|
ROUTE 1 e 0.515 SLICE_88.F0 to 76.PADDO RDQMH_c
|
|
DOPAD_DEL --- 1.108 76.PADDO to 76.PAD RDQMH
|
|
--------
|
|
2.387 (56.8% logic, 43.2% route), 3 logic levels.
|
|
|
|
Report: 3.166ns is the maximum offset for this preference.
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_1_33"></A>Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
|
|
1 item scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
Passed: The following path meets requirements by 3.166ns
|
|
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
|
|
|
Source: FF Q nRowColSel_375 (from RCLK_c +)
|
|
Destination: Port Pad RDQML
|
|
|
|
Data Path Delay: 2.387ns (56.8% logic, 43.2% route), 3 logic levels.
|
|
|
|
Clock Path Delay: 0.779ns (33.9% logic, 66.1% route), 1 logic levels.
|
|
|
|
Constraint Details:
|
|
0.779ns delay RCLK to SLICE_64 and
|
|
2.387ns delay SLICE_64 to RDQML (totaling 3.166ns) meets
|
|
0.000ns hold offset RCLK to RDQML by 3.166ns
|
|
|
|
Physical Path Details:
|
|
|
|
Clock path RCLK to SLICE_64:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
PADI_DEL --- 0.264 86.PAD to 86.PADDI RCLK
|
|
ROUTE 39 e 0.515 86.PADDI to SLICE_64.CLK RCLK_c
|
|
--------
|
|
0.779 (33.9% logic, 66.1% route), 1 logic levels.
|
|
|
|
Data path SLICE_64 to RDQML:
|
|
|
|
Name Fanout Delay (ns) Site Resource
|
|
REG_DEL --- 0.157 SLICE_64.CLK to SLICE_64.Q0 SLICE_64 (from RCLK_c)
|
|
ROUTE 13 e 0.515 SLICE_64.Q0 to SLICE_92.B0 nRowColSel
|
|
CTOF_DEL --- 0.092 SLICE_92.B0 to SLICE_92.F0 SLICE_92
|
|
ROUTE 1 e 0.515 SLICE_92.F0 to 61.PADDO RDQML_c
|
|
DOPAD_DEL --- 1.108 61.PADDO to 61.PAD RDQML
|
|
--------
|
|
2.387 (56.8% logic, 43.2% route), 3 logic levels.
|
|
|
|
Report: 3.166ns is the maximum offset for this preference.
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_1_34"></A>Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_1_35"></A>Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_1_36"></A>Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_1_37"></A>Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_1_38"></A>Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_1_39"></A>Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
|
|
0 items scored, 0 timing errors detected.
|
|
--------------------------------------------------------------------------------
|
|
|
|
|
|
================================================================================
|
|
<A name="map_twr_pref_1_40"></A>Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
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0 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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<A name="mtw1_hold_rs"></A><B><U><big>Report Summary</big></U></B>
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--------------
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----------------------------------------------------------------------------
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Preference(MIN Delays) | Constraint| Actual|Levels
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----------------------------------------------------------------------------
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PERIOD NET "PHI2_c" 350.000000 ns ; | -| -| 2
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PERIOD NET "nCCAS_c" 350.000000 ns ; | -| -| 0
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PERIOD NET "nCRAS_c" 350.000000 ns ; | -| -| 0
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PERIOD NET "RCLK_c" 16.000000 ns ; | -| -| 1
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CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns | | |
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CLKPORT "RCLK" ; | -| -| 0
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CLOCK_TO_OUT PORT "Dout[0]" 12.500000 | | |
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ns CLKPORT "RCLK" ; | -| -| 0
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CLOCK_TO_OUT PORT "Dout[7]" 12.500000 | | |
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ns CLKPORT "RCLK" ; | -| -| 0
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CLOCK_TO_OUT PORT "Dout[6]" 12.500000 | | |
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ns CLKPORT "RCLK" ; | -| -| 0
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CLOCK_TO_OUT PORT "Dout[5]" 12.500000 | | |
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ns CLKPORT "RCLK" ; | -| -| 0
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CLOCK_TO_OUT PORT "Dout[4]" 12.500000 | | |
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ns CLKPORT "RCLK" ; | -| -| 0
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CLOCK_TO_OUT PORT "Dout[3]" 12.500000 | | |
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ns CLKPORT "RCLK" ; | -| -| 0
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CLOCK_TO_OUT PORT "Dout[2]" 12.500000 | | |
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ns CLKPORT "RCLK" ; | -| -| 0
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CLOCK_TO_OUT PORT "Dout[1]" 12.500000 | | |
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ns CLKPORT "RCLK" ; | -| -| 0
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CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns | | |
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CLKPORT "RCLK" ; | -| -| 0
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CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns | | |
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CLKPORT "RCLK" ; | -| -| 0
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CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns | | |
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CLKPORT "RCLK" ; | -| -| 0
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CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns | | |
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CLKPORT "RCLK" ; | 0.000 ns| 2.559 ns| 2
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CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns | | |
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CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3
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CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns | | |
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CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3
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CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns | | |
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CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3
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CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns | | |
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CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3
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CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns | | |
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CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3
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CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns | | |
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CLKPORT "RCLK" ; | 0.000 ns| 2.850 ns| 3
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CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns | | |
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CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3
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CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns | | |
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CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3
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CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns | | |
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CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3
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CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns | | |
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CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3
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CLOCK_TO_OUT PORT "nRCS" 12.500000 ns | | |
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CLKPORT "RCLK" ; | 0.000 ns| 2.559 ns| 2
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CLOCK_TO_OUT PORT "RCKE" 12.500000 ns | | |
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CLKPORT "RCLK" ; | 0.000 ns| 2.559 ns| 2
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CLOCK_TO_OUT PORT "nRWE" 12.500000 ns | | |
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CLKPORT "RCLK" ; | 0.000 ns| 2.559 ns| 2
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CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns | | |
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CLKPORT "RCLK" ; | 0.000 ns| 2.559 ns| 2
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CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns | | |
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CLKPORT "RCLK" ; | 0.000 ns| 2.559 ns| 2
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CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns | | |
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CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3
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CLOCK_TO_OUT PORT "RDQML" 12.500000 ns | | |
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CLKPORT "RCLK" ; | 0.000 ns| 3.166 ns| 3
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CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns | | |
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CLKPORT "RCLK" ; | -| -| 0
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CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns | | |
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CLKPORT "RCLK" ; | -| -| 0
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CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns | | |
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CLKPORT "RCLK" ; | -| -| 0
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CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns | | |
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CLKPORT "RCLK" ; | -| -| 0
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CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns | | |
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CLKPORT "RCLK" ; | -| -| 0
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CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns | | |
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CLKPORT "RCLK" ; | -| -| 0
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CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns | | |
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CLKPORT "RCLK" ; | -| -| 0
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----------------------------------------------------------------------------
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All preferences were met.
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<A name="mtw1_hold_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
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------------------------
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Found 4 clocks:
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Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 9
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No transfer within this clock domain is found
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Data transfers from:
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Clock Domain: RCLK_c Source: RCLK.PAD
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Not reported because source and destination domains are unrelated.
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To report these transfers please refer to preference CLKSKEWDIFF to define
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external clock skew between clock ports.
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Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 7
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No transfer within this clock domain is found
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Clock Domain: RCLK_c Source: RCLK.PAD Loads: 39
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Covered under: PERIOD NET "RCLK_c" 16.000000 ns ;
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Data transfers from:
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Clock Domain: nCRAS_c Source: nCRAS.PAD
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Not reported because source and destination domains are unrelated.
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To report these transfers please refer to preference CLKSKEWDIFF to define
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external clock skew between clock ports.
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Clock Domain: PHI2_c Source: PHI2.PAD
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Not reported because source and destination domains are unrelated.
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To report these transfers please refer to preference CLKSKEWDIFF to define
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external clock skew between clock ports.
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Clock Domain: PHI2_c Source: PHI2.PAD Loads: 14
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Covered under: PERIOD NET "PHI2_c" 350.000000 ns ;
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Data transfers from:
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Clock Domain: RCLK_c Source: RCLK.PAD
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Not reported because source and destination domains are unrelated.
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To report these transfers please refer to preference CLKSKEWDIFF to define
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external clock skew between clock ports.
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<A name="mtw1_hold_ts"></A><B><U><big>Timing summary (Hold):</big></U></B>
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---------------
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Timing errors: 0 Score: 0
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Cumulative negative slack: 0
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Constraints cover 526 paths, 6 nets, and 420 connections (67.96% coverage)
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<A name="mtw1_ts"></A><B><U><big>Timing summary (Setup and Hold):</big></U></B>
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---------------
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Timing errors: 0 (setup), 0 (hold)
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Score: 0 (setup), 0 (hold)
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Cumulative negative slack: 0 (0+0)
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--------------------------------------------------------------------------------
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