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RAM2GS/CPLD/LCMXO/LCMXO640C/impl1/Untitled.tpf_setup.html
Zane Kaminski 3364401289 idk
2021-10-08 21:29:42 -04:00

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--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
Mon Aug 16 20:38:58 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Design file: RAM2GS
Device,speed: LCMXO640C,3
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
Derating parameters
-------------------
Voltage: 3.300 V
</A><A name="PERIOD NET 'PHI2_c' 350.000000 ns"></A>================================================================================
Preference: PERIOD NET "PHI2_c" 350.000000 ns ;
10 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
<font color=#000000>
Passed: The following path meets requirements by 163.925ns (weighted slack = 327.850ns)
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_98">Bank_i6</A> (from <A href="#@net:PHI2_c">PHI2_c</A> +)
Destination: FF Data in <A href="#@comp:SLICE_83">CmdUFMCS_379</A> (to <A href="#@net:PHI2_c">PHI2_c</A> -)
FF <A href="#@net:CmdUFMCLK_380">CmdUFMCLK_380</A>
Delay: 10.810ns (25.8% logic, 74.2% route), 7 logic levels.
Constraint Details:
10.810ns physical path delay SLICE_98 to SLICE_83 meets
175.000ns delay constraint less
0.000ns skew and
0.265ns CE_SET requirement (totaling 174.735ns) by 163.925ns
Physical Path Details:
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:REG_DEL, 0.560,R2C2A.CLK,R2C2A.Q0,SLICE_98:ROUTE, 1.018,R2C2A.Q0,R2C2B.B1,Bank_6:CTOF_DEL, 0.371,R2C2B.B1,R2C2B.F1,SLICE_90:ROUTE, 1.155,R2C2B.F1,R2C5B.D1,n2160:CTOF_DEL, 0.371,R2C5B.D1,R2C5B.F1,SLICE_84:ROUTE, 0.304,R2C5B.F1,R2C5C.D1,n26:CTOF_DEL, 0.371,R2C5C.D1,R2C5C.F1,SLICE_74:ROUTE, 0.924,R2C5C.F1,R4C5C.C1,n1279:CTOF_DEL, 0.371,R4C5C.C1,R4C5C.F1,SLICE_9:ROUTE, 0.320,R4C5C.F1,R4C5B.D1,n2288:CTOF_DEL, 0.371,R4C5B.D1,R4C5B.F1,SLICE_76:ROUTE, 1.282,R4C5B.F1,R5C2A.D1,XOR8MEG_N_112:CTOF_DEL, 0.371,R5C2A.D1,R5C2A.F1,SLICE_73:ROUTE, 3.021,R5C2A.F1,R5C8B.CE,PHI2_N_114_enable_7">Data path</A> SLICE_98 to SLICE_83:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 <A href="#@comp:SLICE_98">SLICE_98</A> (from <A href="#@net:PHI2_c">PHI2_c</A>)
ROUTE 1 1.018<A href="#@net:Bank_6:R2C2A.Q0:R2C2B.B1:1.018"> R2C2A.Q0 to R2C2B.B1 </A> <A href="#@net:Bank_6">Bank_6</A>
CTOF_DEL --- 0.371 R2C2B.B1 to R2C2B.F1 <A href="#@comp:SLICE_90">SLICE_90</A>
ROUTE 1 1.155<A href="#@net:n2160:R2C2B.F1:R2C5B.D1:1.155"> R2C2B.F1 to R2C5B.D1 </A> <A href="#@net:n2160">n2160</A>
CTOF_DEL --- 0.371 R2C5B.D1 to R2C5B.F1 <A href="#@comp:SLICE_84">SLICE_84</A>
ROUTE 1 0.304<A href="#@net:n26:R2C5B.F1:R2C5C.D1:0.304"> R2C5B.F1 to R2C5C.D1 </A> <A href="#@net:n26">n26</A>
CTOF_DEL --- 0.371 R2C5C.D1 to R2C5C.F1 <A href="#@comp:SLICE_74">SLICE_74</A>
ROUTE 5 0.924<A href="#@net:n1279:R2C5C.F1:R4C5C.C1:0.924"> R2C5C.F1 to R4C5C.C1 </A> <A href="#@net:n1279">n1279</A>
CTOF_DEL --- 0.371 R4C5C.C1 to R4C5C.F1 <A href="#@comp:SLICE_9">SLICE_9</A>
ROUTE 2 0.320<A href="#@net:n2288:R4C5C.F1:R4C5B.D1:0.320"> R4C5C.F1 to R4C5B.D1 </A> <A href="#@net:n2288">n2288</A>
CTOF_DEL --- 0.371 R4C5B.D1 to R4C5B.F1 <A href="#@comp:SLICE_76">SLICE_76</A>
ROUTE 3 1.282<A href="#@net:XOR8MEG_N_112:R4C5B.F1:R5C2A.D1:1.282"> R4C5B.F1 to R5C2A.D1 </A> <A href="#@net:XOR8MEG_N_112">XOR8MEG_N_112</A>
CTOF_DEL --- 0.371 R5C2A.D1 to R5C2A.F1 <A href="#@comp:SLICE_73">SLICE_73</A>
ROUTE 2 3.021<A href="#@net:PHI2_N_114_enable_7:R5C2A.F1:R5C8B.CE:3.021"> R5C2A.F1 to R5C8B.CE </A> <A href="#@net:PHI2_N_114_enable_7">PHI2_N_114_enable_7</A> (to <A href="#@net:PHI2_c">PHI2_c</A>)
--------
10.810 (25.8% logic, 74.2% route), 7 logic levels.
Clock Skew Details:
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 3.671,39.PADDI,R2C2A.CLK,PHI2_c">Source Clock Path</A> PHI2 to SLICE_98:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.671<A href="#@net:PHI2_c:39.PADDI:R2C2A.CLK:3.671"> 39.PADDI to R2C2A.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
--------
3.671 (0.0% logic, 100.0% route), 0 logic levels.
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 3.671,39.PADDI,R5C8B.CLK,PHI2_c">Destination Clock Path</A> PHI2 to SLICE_83:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.671<A href="#@net:PHI2_c:39.PADDI:R5C8B.CLK:3.671"> 39.PADDI to R5C8B.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
--------
3.671 (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000>
Passed: The following path meets requirements by 164.114ns (weighted slack = 328.228ns)
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_98">Bank_i7</A> (from <A href="#@net:PHI2_c">PHI2_c</A> +)
Destination: FF Data in <A href="#@comp:SLICE_83">CmdUFMCS_379</A> (to <A href="#@net:PHI2_c">PHI2_c</A> -)
FF <A href="#@net:CmdUFMCLK_380">CmdUFMCLK_380</A>
Delay: 10.621ns (26.2% logic, 73.8% route), 7 logic levels.
Constraint Details:
10.621ns physical path delay SLICE_98 to SLICE_83 meets
175.000ns delay constraint less
0.000ns skew and
0.265ns CE_SET requirement (totaling 174.735ns) by 164.114ns
Physical Path Details:
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:REG_DEL, 0.560,R2C2A.CLK,R2C2A.Q1,SLICE_98:ROUTE, 1.487,R2C2A.Q1,R2C5B.A0,Bank_7:CTOF_DEL, 0.371,R2C5B.A0,R2C5B.F0,SLICE_84:ROUTE, 0.497,R2C5B.F0,R2C5B.C1,n2136:CTOF_DEL, 0.371,R2C5B.C1,R2C5B.F1,SLICE_84:ROUTE, 0.304,R2C5B.F1,R2C5C.D1,n26:CTOF_DEL, 0.371,R2C5C.D1,R2C5C.F1,SLICE_74:ROUTE, 0.924,R2C5C.F1,R4C5C.C1,n1279:CTOF_DEL, 0.371,R4C5C.C1,R4C5C.F1,SLICE_9:ROUTE, 0.320,R4C5C.F1,R4C5B.D1,n2288:CTOF_DEL, 0.371,R4C5B.D1,R4C5B.F1,SLICE_76:ROUTE, 1.282,R4C5B.F1,R5C2A.D1,XOR8MEG_N_112:CTOF_DEL, 0.371,R5C2A.D1,R5C2A.F1,SLICE_73:ROUTE, 3.021,R5C2A.F1,R5C8B.CE,PHI2_N_114_enable_7">Data path</A> SLICE_98 to SLICE_83:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q1 <A href="#@comp:SLICE_98">SLICE_98</A> (from <A href="#@net:PHI2_c">PHI2_c</A>)
ROUTE 1 1.487<A href="#@net:Bank_7:R2C2A.Q1:R2C5B.A0:1.487"> R2C2A.Q1 to R2C5B.A0 </A> <A href="#@net:Bank_7">Bank_7</A>
CTOF_DEL --- 0.371 R2C5B.A0 to R2C5B.F0 <A href="#@comp:SLICE_84">SLICE_84</A>
ROUTE 1 0.497<A href="#@net:n2136:R2C5B.F0:R2C5B.C1:0.497"> R2C5B.F0 to R2C5B.C1 </A> <A href="#@net:n2136">n2136</A>
CTOF_DEL --- 0.371 R2C5B.C1 to R2C5B.F1 <A href="#@comp:SLICE_84">SLICE_84</A>
ROUTE 1 0.304<A href="#@net:n26:R2C5B.F1:R2C5C.D1:0.304"> R2C5B.F1 to R2C5C.D1 </A> <A href="#@net:n26">n26</A>
CTOF_DEL --- 0.371 R2C5C.D1 to R2C5C.F1 <A href="#@comp:SLICE_74">SLICE_74</A>
ROUTE 5 0.924<A href="#@net:n1279:R2C5C.F1:R4C5C.C1:0.924"> R2C5C.F1 to R4C5C.C1 </A> <A href="#@net:n1279">n1279</A>
CTOF_DEL --- 0.371 R4C5C.C1 to R4C5C.F1 <A href="#@comp:SLICE_9">SLICE_9</A>
ROUTE 2 0.320<A href="#@net:n2288:R4C5C.F1:R4C5B.D1:0.320"> R4C5C.F1 to R4C5B.D1 </A> <A href="#@net:n2288">n2288</A>
CTOF_DEL --- 0.371 R4C5B.D1 to R4C5B.F1 <A href="#@comp:SLICE_76">SLICE_76</A>
ROUTE 3 1.282<A href="#@net:XOR8MEG_N_112:R4C5B.F1:R5C2A.D1:1.282"> R4C5B.F1 to R5C2A.D1 </A> <A href="#@net:XOR8MEG_N_112">XOR8MEG_N_112</A>
CTOF_DEL --- 0.371 R5C2A.D1 to R5C2A.F1 <A href="#@comp:SLICE_73">SLICE_73</A>
ROUTE 2 3.021<A href="#@net:PHI2_N_114_enable_7:R5C2A.F1:R5C8B.CE:3.021"> R5C2A.F1 to R5C8B.CE </A> <A href="#@net:PHI2_N_114_enable_7">PHI2_N_114_enable_7</A> (to <A href="#@net:PHI2_c">PHI2_c</A>)
--------
10.621 (26.2% logic, 73.8% route), 7 logic levels.
Clock Skew Details:
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 3.671,39.PADDI,R2C2A.CLK,PHI2_c">Source Clock Path</A> PHI2 to SLICE_98:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.671<A href="#@net:PHI2_c:39.PADDI:R2C2A.CLK:3.671"> 39.PADDI to R2C2A.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
--------
3.671 (0.0% logic, 100.0% route), 0 logic levels.
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 3.671,39.PADDI,R5C8B.CLK,PHI2_c">Destination Clock Path</A> PHI2 to SLICE_83:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.671<A href="#@net:PHI2_c:39.PADDI:R5C8B.CLK:3.671"> 39.PADDI to R5C8B.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
--------
3.671 (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000>
Passed: The following path meets requirements by 164.237ns (weighted slack = 328.474ns)
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_90">Bank_i4</A> (from <A href="#@net:PHI2_c">PHI2_c</A> +)
Destination: FF Data in <A href="#@comp:SLICE_83">CmdUFMCS_379</A> (to <A href="#@net:PHI2_c">PHI2_c</A> -)
FF <A href="#@net:CmdUFMCLK_380">CmdUFMCLK_380</A>
Delay: 10.498ns (23.0% logic, 77.0% route), 6 logic levels.
Constraint Details:
10.498ns physical path delay SLICE_90 to SLICE_83 meets
175.000ns delay constraint less
0.000ns skew and
0.265ns CE_SET requirement (totaling 174.735ns) by 164.237ns
Physical Path Details:
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:REG_DEL, 0.560,R2C2B.CLK,R2C2B.Q0,SLICE_90:ROUTE, 1.643,R2C2B.Q0,R2C6C.B0,Bank_4:CTOF_DEL, 0.371,R2C6C.B0,R2C6C.F0,SLICE_101:ROUTE, 0.893,R2C6C.F0,R2C5C.C1,n2162:CTOF_DEL, 0.371,R2C5C.C1,R2C5C.F1,SLICE_74:ROUTE, 0.924,R2C5C.F1,R4C5C.C1,n1279:CTOF_DEL, 0.371,R4C5C.C1,R4C5C.F1,SLICE_9:ROUTE, 0.320,R4C5C.F1,R4C5B.D1,n2288:CTOF_DEL, 0.371,R4C5B.D1,R4C5B.F1,SLICE_76:ROUTE, 1.282,R4C5B.F1,R5C2A.D1,XOR8MEG_N_112:CTOF_DEL, 0.371,R5C2A.D1,R5C2A.F1,SLICE_73:ROUTE, 3.021,R5C2A.F1,R5C8B.CE,PHI2_N_114_enable_7">Data path</A> SLICE_90 to SLICE_83:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C2B.CLK to R2C2B.Q0 <A href="#@comp:SLICE_90">SLICE_90</A> (from <A href="#@net:PHI2_c">PHI2_c</A>)
ROUTE 1 1.643<A href="#@net:Bank_4:R2C2B.Q0:R2C6C.B0:1.643"> R2C2B.Q0 to R2C6C.B0 </A> <A href="#@net:Bank_4">Bank_4</A>
CTOF_DEL --- 0.371 R2C6C.B0 to R2C6C.F0 <A href="#@comp:SLICE_101">SLICE_101</A>
ROUTE 1 0.893<A href="#@net:n2162:R2C6C.F0:R2C5C.C1:0.893"> R2C6C.F0 to R2C5C.C1 </A> <A href="#@net:n2162">n2162</A>
CTOF_DEL --- 0.371 R2C5C.C1 to R2C5C.F1 <A href="#@comp:SLICE_74">SLICE_74</A>
ROUTE 5 0.924<A href="#@net:n1279:R2C5C.F1:R4C5C.C1:0.924"> R2C5C.F1 to R4C5C.C1 </A> <A href="#@net:n1279">n1279</A>
CTOF_DEL --- 0.371 R4C5C.C1 to R4C5C.F1 <A href="#@comp:SLICE_9">SLICE_9</A>
ROUTE 2 0.320<A href="#@net:n2288:R4C5C.F1:R4C5B.D1:0.320"> R4C5C.F1 to R4C5B.D1 </A> <A href="#@net:n2288">n2288</A>
CTOF_DEL --- 0.371 R4C5B.D1 to R4C5B.F1 <A href="#@comp:SLICE_76">SLICE_76</A>
ROUTE 3 1.282<A href="#@net:XOR8MEG_N_112:R4C5B.F1:R5C2A.D1:1.282"> R4C5B.F1 to R5C2A.D1 </A> <A href="#@net:XOR8MEG_N_112">XOR8MEG_N_112</A>
CTOF_DEL --- 0.371 R5C2A.D1 to R5C2A.F1 <A href="#@comp:SLICE_73">SLICE_73</A>
ROUTE 2 3.021<A href="#@net:PHI2_N_114_enable_7:R5C2A.F1:R5C8B.CE:3.021"> R5C2A.F1 to R5C8B.CE </A> <A href="#@net:PHI2_N_114_enable_7">PHI2_N_114_enable_7</A> (to <A href="#@net:PHI2_c">PHI2_c</A>)
--------
10.498 (23.0% logic, 77.0% route), 6 logic levels.
Clock Skew Details:
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 3.671,39.PADDI,R2C2B.CLK,PHI2_c">Source Clock Path</A> PHI2 to SLICE_90:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.671<A href="#@net:PHI2_c:39.PADDI:R2C2B.CLK:3.671"> 39.PADDI to R2C2B.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
--------
3.671 (0.0% logic, 100.0% route), 0 logic levels.
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 3.671,39.PADDI,R5C8B.CLK,PHI2_c">Destination Clock Path</A> PHI2 to SLICE_83:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.671<A href="#@net:PHI2_c:39.PADDI:R5C8B.CLK:3.671"> 39.PADDI to R5C8B.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
--------
3.671 (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000>
Passed: The following path meets requirements by 164.307ns (weighted slack = 328.614ns)
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_90">Bank_i5</A> (from <A href="#@net:PHI2_c">PHI2_c</A> +)
Destination: FF Data in <A href="#@comp:SLICE_83">CmdUFMCS_379</A> (to <A href="#@net:PHI2_c">PHI2_c</A> -)
FF <A href="#@net:CmdUFMCLK_380">CmdUFMCLK_380</A>
Delay: 10.428ns (26.7% logic, 73.3% route), 7 logic levels.
Constraint Details:
10.428ns physical path delay SLICE_90 to SLICE_83 meets
175.000ns delay constraint less
0.000ns skew and
0.265ns CE_SET requirement (totaling 174.735ns) by 164.307ns
Physical Path Details:
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:REG_DEL, 0.560,R2C2B.CLK,R2C2B.Q1,SLICE_90:ROUTE, 0.636,R2C2B.Q1,R2C2B.A1,Bank_5:CTOF_DEL, 0.371,R2C2B.A1,R2C2B.F1,SLICE_90:ROUTE, 1.155,R2C2B.F1,R2C5B.D1,n2160:CTOF_DEL, 0.371,R2C5B.D1,R2C5B.F1,SLICE_84:ROUTE, 0.304,R2C5B.F1,R2C5C.D1,n26:CTOF_DEL, 0.371,R2C5C.D1,R2C5C.F1,SLICE_74:ROUTE, 0.924,R2C5C.F1,R4C5C.C1,n1279:CTOF_DEL, 0.371,R4C5C.C1,R4C5C.F1,SLICE_9:ROUTE, 0.320,R4C5C.F1,R4C5B.D1,n2288:CTOF_DEL, 0.371,R4C5B.D1,R4C5B.F1,SLICE_76:ROUTE, 1.282,R4C5B.F1,R5C2A.D1,XOR8MEG_N_112:CTOF_DEL, 0.371,R5C2A.D1,R5C2A.F1,SLICE_73:ROUTE, 3.021,R5C2A.F1,R5C8B.CE,PHI2_N_114_enable_7">Data path</A> SLICE_90 to SLICE_83:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C2B.CLK to R2C2B.Q1 <A href="#@comp:SLICE_90">SLICE_90</A> (from <A href="#@net:PHI2_c">PHI2_c</A>)
ROUTE 1 0.636<A href="#@net:Bank_5:R2C2B.Q1:R2C2B.A1:0.636"> R2C2B.Q1 to R2C2B.A1 </A> <A href="#@net:Bank_5">Bank_5</A>
CTOF_DEL --- 0.371 R2C2B.A1 to R2C2B.F1 <A href="#@comp:SLICE_90">SLICE_90</A>
ROUTE 1 1.155<A href="#@net:n2160:R2C2B.F1:R2C5B.D1:1.155"> R2C2B.F1 to R2C5B.D1 </A> <A href="#@net:n2160">n2160</A>
CTOF_DEL --- 0.371 R2C5B.D1 to R2C5B.F1 <A href="#@comp:SLICE_84">SLICE_84</A>
ROUTE 1 0.304<A href="#@net:n26:R2C5B.F1:R2C5C.D1:0.304"> R2C5B.F1 to R2C5C.D1 </A> <A href="#@net:n26">n26</A>
CTOF_DEL --- 0.371 R2C5C.D1 to R2C5C.F1 <A href="#@comp:SLICE_74">SLICE_74</A>
ROUTE 5 0.924<A href="#@net:n1279:R2C5C.F1:R4C5C.C1:0.924"> R2C5C.F1 to R4C5C.C1 </A> <A href="#@net:n1279">n1279</A>
CTOF_DEL --- 0.371 R4C5C.C1 to R4C5C.F1 <A href="#@comp:SLICE_9">SLICE_9</A>
ROUTE 2 0.320<A href="#@net:n2288:R4C5C.F1:R4C5B.D1:0.320"> R4C5C.F1 to R4C5B.D1 </A> <A href="#@net:n2288">n2288</A>
CTOF_DEL --- 0.371 R4C5B.D1 to R4C5B.F1 <A href="#@comp:SLICE_76">SLICE_76</A>
ROUTE 3 1.282<A href="#@net:XOR8MEG_N_112:R4C5B.F1:R5C2A.D1:1.282"> R4C5B.F1 to R5C2A.D1 </A> <A href="#@net:XOR8MEG_N_112">XOR8MEG_N_112</A>
CTOF_DEL --- 0.371 R5C2A.D1 to R5C2A.F1 <A href="#@comp:SLICE_73">SLICE_73</A>
ROUTE 2 3.021<A href="#@net:PHI2_N_114_enable_7:R5C2A.F1:R5C8B.CE:3.021"> R5C2A.F1 to R5C8B.CE </A> <A href="#@net:PHI2_N_114_enable_7">PHI2_N_114_enable_7</A> (to <A href="#@net:PHI2_c">PHI2_c</A>)
--------
10.428 (26.7% logic, 73.3% route), 7 logic levels.
Clock Skew Details:
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 3.671,39.PADDI,R2C2B.CLK,PHI2_c">Source Clock Path</A> PHI2 to SLICE_90:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.671<A href="#@net:PHI2_c:39.PADDI:R2C2B.CLK:3.671"> 39.PADDI to R2C2B.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
--------
3.671 (0.0% logic, 100.0% route), 0 logic levels.
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 3.671,39.PADDI,R5C8B.CLK,PHI2_c">Destination Clock Path</A> PHI2 to SLICE_83:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.671<A href="#@net:PHI2_c:39.PADDI:R5C8B.CLK:3.671"> 39.PADDI to R5C8B.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
--------
3.671 (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000>
Passed: The following path meets requirements by 164.317ns (weighted slack = 328.634ns)
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_93">Bank_i0</A> (from <A href="#@net:PHI2_c">PHI2_c</A> +)
Destination: FF Data in <A href="#@comp:SLICE_83">CmdUFMCS_379</A> (to <A href="#@net:PHI2_c">PHI2_c</A> -)
FF <A href="#@net:CmdUFMCLK_380">CmdUFMCLK_380</A>
Delay: 10.418ns (26.7% logic, 73.3% route), 7 logic levels.
Constraint Details:
10.418ns physical path delay SLICE_93 to SLICE_83 meets
175.000ns delay constraint less
0.000ns skew and
0.265ns CE_SET requirement (totaling 174.735ns) by 164.317ns
Physical Path Details:
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:REG_DEL, 0.560,R2C2C.CLK,R2C2C.Q0,SLICE_93:ROUTE, 0.626,R2C2C.Q0,R2C2B.D1,Bank_0:CTOF_DEL, 0.371,R2C2B.D1,R2C2B.F1,SLICE_90:ROUTE, 1.155,R2C2B.F1,R2C5B.D1,n2160:CTOF_DEL, 0.371,R2C5B.D1,R2C5B.F1,SLICE_84:ROUTE, 0.304,R2C5B.F1,R2C5C.D1,n26:CTOF_DEL, 0.371,R2C5C.D1,R2C5C.F1,SLICE_74:ROUTE, 0.924,R2C5C.F1,R4C5C.C1,n1279:CTOF_DEL, 0.371,R4C5C.C1,R4C5C.F1,SLICE_9:ROUTE, 0.320,R4C5C.F1,R4C5B.D1,n2288:CTOF_DEL, 0.371,R4C5B.D1,R4C5B.F1,SLICE_76:ROUTE, 1.282,R4C5B.F1,R5C2A.D1,XOR8MEG_N_112:CTOF_DEL, 0.371,R5C2A.D1,R5C2A.F1,SLICE_73:ROUTE, 3.021,R5C2A.F1,R5C8B.CE,PHI2_N_114_enable_7">Data path</A> SLICE_93 to SLICE_83:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C2C.CLK to R2C2C.Q0 <A href="#@comp:SLICE_93">SLICE_93</A> (from <A href="#@net:PHI2_c">PHI2_c</A>)
ROUTE 1 0.626<A href="#@net:Bank_0:R2C2C.Q0:R2C2B.D1:0.626"> R2C2C.Q0 to R2C2B.D1 </A> <A href="#@net:Bank_0">Bank_0</A>
CTOF_DEL --- 0.371 R2C2B.D1 to R2C2B.F1 <A href="#@comp:SLICE_90">SLICE_90</A>
ROUTE 1 1.155<A href="#@net:n2160:R2C2B.F1:R2C5B.D1:1.155"> R2C2B.F1 to R2C5B.D1 </A> <A href="#@net:n2160">n2160</A>
CTOF_DEL --- 0.371 R2C5B.D1 to R2C5B.F1 <A href="#@comp:SLICE_84">SLICE_84</A>
ROUTE 1 0.304<A href="#@net:n26:R2C5B.F1:R2C5C.D1:0.304"> R2C5B.F1 to R2C5C.D1 </A> <A href="#@net:n26">n26</A>
CTOF_DEL --- 0.371 R2C5C.D1 to R2C5C.F1 <A href="#@comp:SLICE_74">SLICE_74</A>
ROUTE 5 0.924<A href="#@net:n1279:R2C5C.F1:R4C5C.C1:0.924"> R2C5C.F1 to R4C5C.C1 </A> <A href="#@net:n1279">n1279</A>
CTOF_DEL --- 0.371 R4C5C.C1 to R4C5C.F1 <A href="#@comp:SLICE_9">SLICE_9</A>
ROUTE 2 0.320<A href="#@net:n2288:R4C5C.F1:R4C5B.D1:0.320"> R4C5C.F1 to R4C5B.D1 </A> <A href="#@net:n2288">n2288</A>
CTOF_DEL --- 0.371 R4C5B.D1 to R4C5B.F1 <A href="#@comp:SLICE_76">SLICE_76</A>
ROUTE 3 1.282<A href="#@net:XOR8MEG_N_112:R4C5B.F1:R5C2A.D1:1.282"> R4C5B.F1 to R5C2A.D1 </A> <A href="#@net:XOR8MEG_N_112">XOR8MEG_N_112</A>
CTOF_DEL --- 0.371 R5C2A.D1 to R5C2A.F1 <A href="#@comp:SLICE_73">SLICE_73</A>
ROUTE 2 3.021<A href="#@net:PHI2_N_114_enable_7:R5C2A.F1:R5C8B.CE:3.021"> R5C2A.F1 to R5C8B.CE </A> <A href="#@net:PHI2_N_114_enable_7">PHI2_N_114_enable_7</A> (to <A href="#@net:PHI2_c">PHI2_c</A>)
--------
10.418 (26.7% logic, 73.3% route), 7 logic levels.
Clock Skew Details:
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 3.671,39.PADDI,R2C2C.CLK,PHI2_c">Source Clock Path</A> PHI2 to SLICE_93:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.671<A href="#@net:PHI2_c:39.PADDI:R2C2C.CLK:3.671"> 39.PADDI to R2C2C.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
--------
3.671 (0.0% logic, 100.0% route), 0 logic levels.
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 3.671,39.PADDI,R5C8B.CLK,PHI2_c">Destination Clock Path</A> PHI2 to SLICE_83:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.671<A href="#@net:PHI2_c:39.PADDI:R5C8B.CLK:3.671"> 39.PADDI to R5C8B.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
--------
3.671 (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000>
Passed: The following path meets requirements by 164.386ns (weighted slack = 328.772ns)
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_98">Bank_i6</A> (from <A href="#@net:PHI2_c">PHI2_c</A> +)
Destination: FF Data in <A href="#@comp:SLICE_77">CmdUFMSDI_381</A> (to <A href="#@net:PHI2_c">PHI2_c</A> -)
Delay: 10.349ns (26.9% logic, 73.1% route), 7 logic levels.
Constraint Details:
10.349ns physical path delay SLICE_98 to SLICE_77 meets
175.000ns delay constraint less
0.000ns skew and
0.265ns CE_SET requirement (totaling 174.735ns) by 164.386ns
Physical Path Details:
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:REG_DEL, 0.560,R2C2A.CLK,R2C2A.Q0,SLICE_98:ROUTE, 1.018,R2C2A.Q0,R2C2B.B1,Bank_6:CTOF_DEL, 0.371,R2C2B.B1,R2C2B.F1,SLICE_90:ROUTE, 1.155,R2C2B.F1,R2C5B.D1,n2160:CTOF_DEL, 0.371,R2C5B.D1,R2C5B.F1,SLICE_84:ROUTE, 0.304,R2C5B.F1,R2C5C.D1,n26:CTOF_DEL, 0.371,R2C5C.D1,R2C5C.F1,SLICE_74:ROUTE, 0.924,R2C5C.F1,R4C5C.C1,n1279:CTOF_DEL, 0.371,R4C5C.C1,R4C5C.F1,SLICE_9:ROUTE, 0.320,R4C5C.F1,R4C5B.D1,n2288:CTOF_DEL, 0.371,R4C5B.D1,R4C5B.F1,SLICE_76:ROUTE, 1.282,R4C5B.F1,R5C2A.D1,XOR8MEG_N_112:CTOF_DEL, 0.371,R5C2A.D1,R5C2A.F1,SLICE_73:ROUTE, 2.560,R5C2A.F1,R9C9A.CE,PHI2_N_114_enable_7">Data path</A> SLICE_98 to SLICE_77:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q0 <A href="#@comp:SLICE_98">SLICE_98</A> (from <A href="#@net:PHI2_c">PHI2_c</A>)
ROUTE 1 1.018<A href="#@net:Bank_6:R2C2A.Q0:R2C2B.B1:1.018"> R2C2A.Q0 to R2C2B.B1 </A> <A href="#@net:Bank_6">Bank_6</A>
CTOF_DEL --- 0.371 R2C2B.B1 to R2C2B.F1 <A href="#@comp:SLICE_90">SLICE_90</A>
ROUTE 1 1.155<A href="#@net:n2160:R2C2B.F1:R2C5B.D1:1.155"> R2C2B.F1 to R2C5B.D1 </A> <A href="#@net:n2160">n2160</A>
CTOF_DEL --- 0.371 R2C5B.D1 to R2C5B.F1 <A href="#@comp:SLICE_84">SLICE_84</A>
ROUTE 1 0.304<A href="#@net:n26:R2C5B.F1:R2C5C.D1:0.304"> R2C5B.F1 to R2C5C.D1 </A> <A href="#@net:n26">n26</A>
CTOF_DEL --- 0.371 R2C5C.D1 to R2C5C.F1 <A href="#@comp:SLICE_74">SLICE_74</A>
ROUTE 5 0.924<A href="#@net:n1279:R2C5C.F1:R4C5C.C1:0.924"> R2C5C.F1 to R4C5C.C1 </A> <A href="#@net:n1279">n1279</A>
CTOF_DEL --- 0.371 R4C5C.C1 to R4C5C.F1 <A href="#@comp:SLICE_9">SLICE_9</A>
ROUTE 2 0.320<A href="#@net:n2288:R4C5C.F1:R4C5B.D1:0.320"> R4C5C.F1 to R4C5B.D1 </A> <A href="#@net:n2288">n2288</A>
CTOF_DEL --- 0.371 R4C5B.D1 to R4C5B.F1 <A href="#@comp:SLICE_76">SLICE_76</A>
ROUTE 3 1.282<A href="#@net:XOR8MEG_N_112:R4C5B.F1:R5C2A.D1:1.282"> R4C5B.F1 to R5C2A.D1 </A> <A href="#@net:XOR8MEG_N_112">XOR8MEG_N_112</A>
CTOF_DEL --- 0.371 R5C2A.D1 to R5C2A.F1 <A href="#@comp:SLICE_73">SLICE_73</A>
ROUTE 2 2.560<A href="#@net:PHI2_N_114_enable_7:R5C2A.F1:R9C9A.CE:2.560"> R5C2A.F1 to R9C9A.CE </A> <A href="#@net:PHI2_N_114_enable_7">PHI2_N_114_enable_7</A> (to <A href="#@net:PHI2_c">PHI2_c</A>)
--------
10.349 (26.9% logic, 73.1% route), 7 logic levels.
Clock Skew Details:
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 3.671,39.PADDI,R2C2A.CLK,PHI2_c">Source Clock Path</A> PHI2 to SLICE_98:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.671<A href="#@net:PHI2_c:39.PADDI:R2C2A.CLK:3.671"> 39.PADDI to R2C2A.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
--------
3.671 (0.0% logic, 100.0% route), 0 logic levels.
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 3.671,39.PADDI,R9C9A.CLK,PHI2_c">Destination Clock Path</A> PHI2 to SLICE_77:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.671<A href="#@net:PHI2_c:39.PADDI:R9C9A.CLK:3.671"> 39.PADDI to R9C9A.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
--------
3.671 (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000>
Passed: The following path meets requirements by 164.575ns (weighted slack = 329.150ns)
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_98">Bank_i7</A> (from <A href="#@net:PHI2_c">PHI2_c</A> +)
Destination: FF Data in <A href="#@comp:SLICE_77">CmdUFMSDI_381</A> (to <A href="#@net:PHI2_c">PHI2_c</A> -)
Delay: 10.160ns (27.4% logic, 72.6% route), 7 logic levels.
Constraint Details:
10.160ns physical path delay SLICE_98 to SLICE_77 meets
175.000ns delay constraint less
0.000ns skew and
0.265ns CE_SET requirement (totaling 174.735ns) by 164.575ns
Physical Path Details:
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:REG_DEL, 0.560,R2C2A.CLK,R2C2A.Q1,SLICE_98:ROUTE, 1.487,R2C2A.Q1,R2C5B.A0,Bank_7:CTOF_DEL, 0.371,R2C5B.A0,R2C5B.F0,SLICE_84:ROUTE, 0.497,R2C5B.F0,R2C5B.C1,n2136:CTOF_DEL, 0.371,R2C5B.C1,R2C5B.F1,SLICE_84:ROUTE, 0.304,R2C5B.F1,R2C5C.D1,n26:CTOF_DEL, 0.371,R2C5C.D1,R2C5C.F1,SLICE_74:ROUTE, 0.924,R2C5C.F1,R4C5C.C1,n1279:CTOF_DEL, 0.371,R4C5C.C1,R4C5C.F1,SLICE_9:ROUTE, 0.320,R4C5C.F1,R4C5B.D1,n2288:CTOF_DEL, 0.371,R4C5B.D1,R4C5B.F1,SLICE_76:ROUTE, 1.282,R4C5B.F1,R5C2A.D1,XOR8MEG_N_112:CTOF_DEL, 0.371,R5C2A.D1,R5C2A.F1,SLICE_73:ROUTE, 2.560,R5C2A.F1,R9C9A.CE,PHI2_N_114_enable_7">Data path</A> SLICE_98 to SLICE_77:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C2A.CLK to R2C2A.Q1 <A href="#@comp:SLICE_98">SLICE_98</A> (from <A href="#@net:PHI2_c">PHI2_c</A>)
ROUTE 1 1.487<A href="#@net:Bank_7:R2C2A.Q1:R2C5B.A0:1.487"> R2C2A.Q1 to R2C5B.A0 </A> <A href="#@net:Bank_7">Bank_7</A>
CTOF_DEL --- 0.371 R2C5B.A0 to R2C5B.F0 <A href="#@comp:SLICE_84">SLICE_84</A>
ROUTE 1 0.497<A href="#@net:n2136:R2C5B.F0:R2C5B.C1:0.497"> R2C5B.F0 to R2C5B.C1 </A> <A href="#@net:n2136">n2136</A>
CTOF_DEL --- 0.371 R2C5B.C1 to R2C5B.F1 <A href="#@comp:SLICE_84">SLICE_84</A>
ROUTE 1 0.304<A href="#@net:n26:R2C5B.F1:R2C5C.D1:0.304"> R2C5B.F1 to R2C5C.D1 </A> <A href="#@net:n26">n26</A>
CTOF_DEL --- 0.371 R2C5C.D1 to R2C5C.F1 <A href="#@comp:SLICE_74">SLICE_74</A>
ROUTE 5 0.924<A href="#@net:n1279:R2C5C.F1:R4C5C.C1:0.924"> R2C5C.F1 to R4C5C.C1 </A> <A href="#@net:n1279">n1279</A>
CTOF_DEL --- 0.371 R4C5C.C1 to R4C5C.F1 <A href="#@comp:SLICE_9">SLICE_9</A>
ROUTE 2 0.320<A href="#@net:n2288:R4C5C.F1:R4C5B.D1:0.320"> R4C5C.F1 to R4C5B.D1 </A> <A href="#@net:n2288">n2288</A>
CTOF_DEL --- 0.371 R4C5B.D1 to R4C5B.F1 <A href="#@comp:SLICE_76">SLICE_76</A>
ROUTE 3 1.282<A href="#@net:XOR8MEG_N_112:R4C5B.F1:R5C2A.D1:1.282"> R4C5B.F1 to R5C2A.D1 </A> <A href="#@net:XOR8MEG_N_112">XOR8MEG_N_112</A>
CTOF_DEL --- 0.371 R5C2A.D1 to R5C2A.F1 <A href="#@comp:SLICE_73">SLICE_73</A>
ROUTE 2 2.560<A href="#@net:PHI2_N_114_enable_7:R5C2A.F1:R9C9A.CE:2.560"> R5C2A.F1 to R9C9A.CE </A> <A href="#@net:PHI2_N_114_enable_7">PHI2_N_114_enable_7</A> (to <A href="#@net:PHI2_c">PHI2_c</A>)
--------
10.160 (27.4% logic, 72.6% route), 7 logic levels.
Clock Skew Details:
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 3.671,39.PADDI,R2C2A.CLK,PHI2_c">Source Clock Path</A> PHI2 to SLICE_98:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.671<A href="#@net:PHI2_c:39.PADDI:R2C2A.CLK:3.671"> 39.PADDI to R2C2A.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
--------
3.671 (0.0% logic, 100.0% route), 0 logic levels.
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 3.671,39.PADDI,R9C9A.CLK,PHI2_c">Destination Clock Path</A> PHI2 to SLICE_77:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.671<A href="#@net:PHI2_c:39.PADDI:R9C9A.CLK:3.671"> 39.PADDI to R9C9A.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
--------
3.671 (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000>
Passed: The following path meets requirements by 164.629ns (weighted slack = 329.258ns)
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_93">Bank_i1</A> (from <A href="#@net:PHI2_c">PHI2_c</A> +)
Destination: FF Data in <A href="#@comp:SLICE_83">CmdUFMCS_379</A> (to <A href="#@net:PHI2_c">PHI2_c</A> -)
FF <A href="#@net:CmdUFMCLK_380">CmdUFMCLK_380</A>
Delay: 10.106ns (23.9% logic, 76.1% route), 6 logic levels.
Constraint Details:
10.106ns physical path delay SLICE_93 to SLICE_83 meets
175.000ns delay constraint less
0.000ns skew and
0.265ns CE_SET requirement (totaling 174.735ns) by 164.629ns
Physical Path Details:
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:REG_DEL, 0.560,R2C2C.CLK,R2C2C.Q1,SLICE_93:ROUTE, 1.251,R2C2C.Q1,R2C6C.D0,Bank_1:CTOF_DEL, 0.371,R2C6C.D0,R2C6C.F0,SLICE_101:ROUTE, 0.893,R2C6C.F0,R2C5C.C1,n2162:CTOF_DEL, 0.371,R2C5C.C1,R2C5C.F1,SLICE_74:ROUTE, 0.924,R2C5C.F1,R4C5C.C1,n1279:CTOF_DEL, 0.371,R4C5C.C1,R4C5C.F1,SLICE_9:ROUTE, 0.320,R4C5C.F1,R4C5B.D1,n2288:CTOF_DEL, 0.371,R4C5B.D1,R4C5B.F1,SLICE_76:ROUTE, 1.282,R4C5B.F1,R5C2A.D1,XOR8MEG_N_112:CTOF_DEL, 0.371,R5C2A.D1,R5C2A.F1,SLICE_73:ROUTE, 3.021,R5C2A.F1,R5C8B.CE,PHI2_N_114_enable_7">Data path</A> SLICE_93 to SLICE_83:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C2C.CLK to R2C2C.Q1 <A href="#@comp:SLICE_93">SLICE_93</A> (from <A href="#@net:PHI2_c">PHI2_c</A>)
ROUTE 1 1.251<A href="#@net:Bank_1:R2C2C.Q1:R2C6C.D0:1.251"> R2C2C.Q1 to R2C6C.D0 </A> <A href="#@net:Bank_1">Bank_1</A>
CTOF_DEL --- 0.371 R2C6C.D0 to R2C6C.F0 <A href="#@comp:SLICE_101">SLICE_101</A>
ROUTE 1 0.893<A href="#@net:n2162:R2C6C.F0:R2C5C.C1:0.893"> R2C6C.F0 to R2C5C.C1 </A> <A href="#@net:n2162">n2162</A>
CTOF_DEL --- 0.371 R2C5C.C1 to R2C5C.F1 <A href="#@comp:SLICE_74">SLICE_74</A>
ROUTE 5 0.924<A href="#@net:n1279:R2C5C.F1:R4C5C.C1:0.924"> R2C5C.F1 to R4C5C.C1 </A> <A href="#@net:n1279">n1279</A>
CTOF_DEL --- 0.371 R4C5C.C1 to R4C5C.F1 <A href="#@comp:SLICE_9">SLICE_9</A>
ROUTE 2 0.320<A href="#@net:n2288:R4C5C.F1:R4C5B.D1:0.320"> R4C5C.F1 to R4C5B.D1 </A> <A href="#@net:n2288">n2288</A>
CTOF_DEL --- 0.371 R4C5B.D1 to R4C5B.F1 <A href="#@comp:SLICE_76">SLICE_76</A>
ROUTE 3 1.282<A href="#@net:XOR8MEG_N_112:R4C5B.F1:R5C2A.D1:1.282"> R4C5B.F1 to R5C2A.D1 </A> <A href="#@net:XOR8MEG_N_112">XOR8MEG_N_112</A>
CTOF_DEL --- 0.371 R5C2A.D1 to R5C2A.F1 <A href="#@comp:SLICE_73">SLICE_73</A>
ROUTE 2 3.021<A href="#@net:PHI2_N_114_enable_7:R5C2A.F1:R5C8B.CE:3.021"> R5C2A.F1 to R5C8B.CE </A> <A href="#@net:PHI2_N_114_enable_7">PHI2_N_114_enable_7</A> (to <A href="#@net:PHI2_c">PHI2_c</A>)
--------
10.106 (23.9% logic, 76.1% route), 6 logic levels.
Clock Skew Details:
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 3.671,39.PADDI,R2C2C.CLK,PHI2_c">Source Clock Path</A> PHI2 to SLICE_93:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.671<A href="#@net:PHI2_c:39.PADDI:R2C2C.CLK:3.671"> 39.PADDI to R2C2C.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
--------
3.671 (0.0% logic, 100.0% route), 0 logic levels.
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 3.671,39.PADDI,R5C8B.CLK,PHI2_c">Destination Clock Path</A> PHI2 to SLICE_83:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.671<A href="#@net:PHI2_c:39.PADDI:R5C8B.CLK:3.671"> 39.PADDI to R5C8B.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
--------
3.671 (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000>
Passed: The following path meets requirements by 164.698ns (weighted slack = 329.396ns)
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_90">Bank_i4</A> (from <A href="#@net:PHI2_c">PHI2_c</A> +)
Destination: FF Data in <A href="#@comp:SLICE_77">CmdUFMSDI_381</A> (to <A href="#@net:PHI2_c">PHI2_c</A> -)
Delay: 10.037ns (24.1% logic, 75.9% route), 6 logic levels.
Constraint Details:
10.037ns physical path delay SLICE_90 to SLICE_77 meets
175.000ns delay constraint less
0.000ns skew and
0.265ns CE_SET requirement (totaling 174.735ns) by 164.698ns
Physical Path Details:
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:REG_DEL, 0.560,R2C2B.CLK,R2C2B.Q0,SLICE_90:ROUTE, 1.643,R2C2B.Q0,R2C6C.B0,Bank_4:CTOF_DEL, 0.371,R2C6C.B0,R2C6C.F0,SLICE_101:ROUTE, 0.893,R2C6C.F0,R2C5C.C1,n2162:CTOF_DEL, 0.371,R2C5C.C1,R2C5C.F1,SLICE_74:ROUTE, 0.924,R2C5C.F1,R4C5C.C1,n1279:CTOF_DEL, 0.371,R4C5C.C1,R4C5C.F1,SLICE_9:ROUTE, 0.320,R4C5C.F1,R4C5B.D1,n2288:CTOF_DEL, 0.371,R4C5B.D1,R4C5B.F1,SLICE_76:ROUTE, 1.282,R4C5B.F1,R5C2A.D1,XOR8MEG_N_112:CTOF_DEL, 0.371,R5C2A.D1,R5C2A.F1,SLICE_73:ROUTE, 2.560,R5C2A.F1,R9C9A.CE,PHI2_N_114_enable_7">Data path</A> SLICE_90 to SLICE_77:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C2B.CLK to R2C2B.Q0 <A href="#@comp:SLICE_90">SLICE_90</A> (from <A href="#@net:PHI2_c">PHI2_c</A>)
ROUTE 1 1.643<A href="#@net:Bank_4:R2C2B.Q0:R2C6C.B0:1.643"> R2C2B.Q0 to R2C6C.B0 </A> <A href="#@net:Bank_4">Bank_4</A>
CTOF_DEL --- 0.371 R2C6C.B0 to R2C6C.F0 <A href="#@comp:SLICE_101">SLICE_101</A>
ROUTE 1 0.893<A href="#@net:n2162:R2C6C.F0:R2C5C.C1:0.893"> R2C6C.F0 to R2C5C.C1 </A> <A href="#@net:n2162">n2162</A>
CTOF_DEL --- 0.371 R2C5C.C1 to R2C5C.F1 <A href="#@comp:SLICE_74">SLICE_74</A>
ROUTE 5 0.924<A href="#@net:n1279:R2C5C.F1:R4C5C.C1:0.924"> R2C5C.F1 to R4C5C.C1 </A> <A href="#@net:n1279">n1279</A>
CTOF_DEL --- 0.371 R4C5C.C1 to R4C5C.F1 <A href="#@comp:SLICE_9">SLICE_9</A>
ROUTE 2 0.320<A href="#@net:n2288:R4C5C.F1:R4C5B.D1:0.320"> R4C5C.F1 to R4C5B.D1 </A> <A href="#@net:n2288">n2288</A>
CTOF_DEL --- 0.371 R4C5B.D1 to R4C5B.F1 <A href="#@comp:SLICE_76">SLICE_76</A>
ROUTE 3 1.282<A href="#@net:XOR8MEG_N_112:R4C5B.F1:R5C2A.D1:1.282"> R4C5B.F1 to R5C2A.D1 </A> <A href="#@net:XOR8MEG_N_112">XOR8MEG_N_112</A>
CTOF_DEL --- 0.371 R5C2A.D1 to R5C2A.F1 <A href="#@comp:SLICE_73">SLICE_73</A>
ROUTE 2 2.560<A href="#@net:PHI2_N_114_enable_7:R5C2A.F1:R9C9A.CE:2.560"> R5C2A.F1 to R9C9A.CE </A> <A href="#@net:PHI2_N_114_enable_7">PHI2_N_114_enable_7</A> (to <A href="#@net:PHI2_c">PHI2_c</A>)
--------
10.037 (24.1% logic, 75.9% route), 6 logic levels.
Clock Skew Details:
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 3.671,39.PADDI,R2C2B.CLK,PHI2_c">Source Clock Path</A> PHI2 to SLICE_90:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.671<A href="#@net:PHI2_c:39.PADDI:R2C2B.CLK:3.671"> 39.PADDI to R2C2B.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
--------
3.671 (0.0% logic, 100.0% route), 0 logic levels.
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 3.671,39.PADDI,R9C9A.CLK,PHI2_c">Destination Clock Path</A> PHI2 to SLICE_77:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.671<A href="#@net:PHI2_c:39.PADDI:R9C9A.CLK:3.671"> 39.PADDI to R9C9A.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
--------
3.671 (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000>
Passed: The following path meets requirements by 164.768ns (weighted slack = 329.536ns)
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_90">Bank_i5</A> (from <A href="#@net:PHI2_c">PHI2_c</A> +)
Destination: FF Data in <A href="#@comp:SLICE_77">CmdUFMSDI_381</A> (to <A href="#@net:PHI2_c">PHI2_c</A> -)
Delay: 9.967ns (28.0% logic, 72.0% route), 7 logic levels.
Constraint Details:
9.967ns physical path delay SLICE_90 to SLICE_77 meets
175.000ns delay constraint less
0.000ns skew and
0.265ns CE_SET requirement (totaling 174.735ns) by 164.768ns
Physical Path Details:
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:REG_DEL, 0.560,R2C2B.CLK,R2C2B.Q1,SLICE_90:ROUTE, 0.636,R2C2B.Q1,R2C2B.A1,Bank_5:CTOF_DEL, 0.371,R2C2B.A1,R2C2B.F1,SLICE_90:ROUTE, 1.155,R2C2B.F1,R2C5B.D1,n2160:CTOF_DEL, 0.371,R2C5B.D1,R2C5B.F1,SLICE_84:ROUTE, 0.304,R2C5B.F1,R2C5C.D1,n26:CTOF_DEL, 0.371,R2C5C.D1,R2C5C.F1,SLICE_74:ROUTE, 0.924,R2C5C.F1,R4C5C.C1,n1279:CTOF_DEL, 0.371,R4C5C.C1,R4C5C.F1,SLICE_9:ROUTE, 0.320,R4C5C.F1,R4C5B.D1,n2288:CTOF_DEL, 0.371,R4C5B.D1,R4C5B.F1,SLICE_76:ROUTE, 1.282,R4C5B.F1,R5C2A.D1,XOR8MEG_N_112:CTOF_DEL, 0.371,R5C2A.D1,R5C2A.F1,SLICE_73:ROUTE, 2.560,R5C2A.F1,R9C9A.CE,PHI2_N_114_enable_7">Data path</A> SLICE_90 to SLICE_77:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C2B.CLK to R2C2B.Q1 <A href="#@comp:SLICE_90">SLICE_90</A> (from <A href="#@net:PHI2_c">PHI2_c</A>)
ROUTE 1 0.636<A href="#@net:Bank_5:R2C2B.Q1:R2C2B.A1:0.636"> R2C2B.Q1 to R2C2B.A1 </A> <A href="#@net:Bank_5">Bank_5</A>
CTOF_DEL --- 0.371 R2C2B.A1 to R2C2B.F1 <A href="#@comp:SLICE_90">SLICE_90</A>
ROUTE 1 1.155<A href="#@net:n2160:R2C2B.F1:R2C5B.D1:1.155"> R2C2B.F1 to R2C5B.D1 </A> <A href="#@net:n2160">n2160</A>
CTOF_DEL --- 0.371 R2C5B.D1 to R2C5B.F1 <A href="#@comp:SLICE_84">SLICE_84</A>
ROUTE 1 0.304<A href="#@net:n26:R2C5B.F1:R2C5C.D1:0.304"> R2C5B.F1 to R2C5C.D1 </A> <A href="#@net:n26">n26</A>
CTOF_DEL --- 0.371 R2C5C.D1 to R2C5C.F1 <A href="#@comp:SLICE_74">SLICE_74</A>
ROUTE 5 0.924<A href="#@net:n1279:R2C5C.F1:R4C5C.C1:0.924"> R2C5C.F1 to R4C5C.C1 </A> <A href="#@net:n1279">n1279</A>
CTOF_DEL --- 0.371 R4C5C.C1 to R4C5C.F1 <A href="#@comp:SLICE_9">SLICE_9</A>
ROUTE 2 0.320<A href="#@net:n2288:R4C5C.F1:R4C5B.D1:0.320"> R4C5C.F1 to R4C5B.D1 </A> <A href="#@net:n2288">n2288</A>
CTOF_DEL --- 0.371 R4C5B.D1 to R4C5B.F1 <A href="#@comp:SLICE_76">SLICE_76</A>
ROUTE 3 1.282<A href="#@net:XOR8MEG_N_112:R4C5B.F1:R5C2A.D1:1.282"> R4C5B.F1 to R5C2A.D1 </A> <A href="#@net:XOR8MEG_N_112">XOR8MEG_N_112</A>
CTOF_DEL --- 0.371 R5C2A.D1 to R5C2A.F1 <A href="#@comp:SLICE_73">SLICE_73</A>
ROUTE 2 2.560<A href="#@net:PHI2_N_114_enable_7:R5C2A.F1:R9C9A.CE:2.560"> R5C2A.F1 to R9C9A.CE </A> <A href="#@net:PHI2_N_114_enable_7">PHI2_N_114_enable_7</A> (to <A href="#@net:PHI2_c">PHI2_c</A>)
--------
9.967 (28.0% logic, 72.0% route), 7 logic levels.
Clock Skew Details:
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 3.671,39.PADDI,R2C2B.CLK,PHI2_c">Source Clock Path</A> PHI2 to SLICE_90:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.671<A href="#@net:PHI2_c:39.PADDI:R2C2B.CLK:3.671"> 39.PADDI to R2C2B.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
--------
3.671 (0.0% logic, 100.0% route), 0 logic levels.
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 3.671,39.PADDI,R9C9A.CLK,PHI2_c">Destination Clock Path</A> PHI2 to SLICE_77:
Name Fanout Delay (ns) Site Resource
ROUTE 14 3.671<A href="#@net:PHI2_c:39.PADDI:R9C9A.CLK:3.671"> 39.PADDI to R9C9A.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
--------
3.671 (0.0% logic, 100.0% route), 0 logic levels.
Report: 22.150ns is the minimum period for this preference.
</A><A name="PERIOD NET 'nCCAS_c' 350.000000 ns"></A>================================================================================
Preference: PERIOD NET "nCCAS_c" 350.000000 ns ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 348.000ns
The internal maximum frequency of the following component is 500.000 MHz
Logical Details: Cell type Pin name Component name
Destination: FSLICE CLK <A href="#@comp:SLICE_73">SLICE_73</A>
Delay: 2.000ns -- based on Minimum Pulse Width
Report: 2.000ns is the minimum period for this preference.
</A><A name="PERIOD NET 'nCRAS_c' 350.000000 ns"></A>================================================================================
Preference: PERIOD NET "nCRAS_c" 350.000000 ns ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 348.000ns
The internal maximum frequency of the following component is 500.000 MHz
Logical Details: Cell type Pin name Component name
Destination: FSLICE CLK <A href="#@comp:SLICE_74">SLICE_74</A>
Delay: 2.000ns -- based on Minimum Pulse Width
Report: 2.000ns is the minimum period for this preference.
</A><A name="PERIOD NET 'RCLK_c' 16.000000 ns"></A>================================================================================
Preference: PERIOD NET "RCLK_c" 16.000000 ns ;
10 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
<font color=#000000>
Passed: The following path meets requirements by 7.341ns
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_7">FS_571__i15</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: FF Data in <A href="#@comp:SLICE_56">n8MEGEN_385</A> (to <A href="#@net:RCLK_c">RCLK_c</A> +)
Delay: 8.415ns (28.7% logic, 71.3% route), 6 logic levels.
Constraint Details:
8.415ns physical path delay SLICE_7 to SLICE_56 meets
16.000ns delay constraint less
0.000ns skew and
0.244ns CE_SET requirement (totaling 15.756ns) by 7.341ns
Physical Path Details:
<A href="#@path:PERIOD NET 'RCLK_c' 16.000000 ns ;:REG_DEL, 0.560,R8C8D.CLK,R8C8D.Q1,SLICE_7:ROUTE, 1.475,R8C8D.Q1,R8C9D.B1,FS_15:CTOF_DEL, 0.371,R8C9D.B1,R8C9D.F1,SLICE_78:ROUTE, 1.057,R8C9D.F1,R6C9B.A1,n10:CTOF_DEL, 0.371,R6C9B.A1,R6C9B.F1,SLICE_75:ROUTE, 0.528,R6C9B.F1,R6C9B.C0,n2298:CTOF_DEL, 0.371,R6C9B.C0,R6C9B.F0,SLICE_75:ROUTE, 1.155,R6C9B.F0,R9C9A.D1,n11:CTOF_DEL, 0.371,R9C9A.D1,R9C9A.F1,SLICE_77:ROUTE, 0.712,R9C9A.F1,R9C9A.B0,n2111:CTOF_DEL, 0.371,R9C9A.B0,R9C9A.F0,SLICE_77:ROUTE, 1.073,R9C9A.F0,R9C8D.CE,RCLK_c_enable_7">Data path</A> SLICE_7 to SLICE_56:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R8C8D.CLK to R8C8D.Q1 <A href="#@comp:SLICE_7">SLICE_7</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 3 1.475<A href="#@net:FS_15:R8C8D.Q1:R8C9D.B1:1.475"> R8C8D.Q1 to R8C9D.B1 </A> <A href="#@net:FS_15">FS_15</A>
CTOF_DEL --- 0.371 R8C9D.B1 to R8C9D.F1 <A href="#@comp:SLICE_78">SLICE_78</A>
ROUTE 3 1.057<A href="#@net:n10:R8C9D.F1:R6C9B.A1:1.057"> R8C9D.F1 to R6C9B.A1 </A> <A href="#@net:n10">n10</A>
CTOF_DEL --- 0.371 R6C9B.A1 to R6C9B.F1 <A href="#@comp:SLICE_75">SLICE_75</A>
ROUTE 4 0.528<A href="#@net:n2298:R6C9B.F1:R6C9B.C0:0.528"> R6C9B.F1 to R6C9B.C0 </A> <A href="#@net:n2298">n2298</A>
CTOF_DEL --- 0.371 R6C9B.C0 to R6C9B.F0 <A href="#@comp:SLICE_75">SLICE_75</A>
ROUTE 1 1.155<A href="#@net:n11:R6C9B.F0:R9C9A.D1:1.155"> R6C9B.F0 to R9C9A.D1 </A> <A href="#@net:n11">n11</A>
CTOF_DEL --- 0.371 R9C9A.D1 to R9C9A.F1 <A href="#@comp:SLICE_77">SLICE_77</A>
ROUTE 2 0.712<A href="#@net:n2111:R9C9A.F1:R9C9A.B0:0.712"> R9C9A.F1 to R9C9A.B0 </A> <A href="#@net:n2111">n2111</A>
CTOF_DEL --- 0.371 R9C9A.B0 to R9C9A.F0 <A href="#@comp:SLICE_77">SLICE_77</A>
ROUTE 1 1.073<A href="#@net:RCLK_c_enable_7:R9C9A.F0:R9C8D.CE:1.073"> R9C9A.F0 to R9C8D.CE </A> <A href="#@net:RCLK_c_enable_7">RCLK_c_enable_7</A> (to <A href="#@net:RCLK_c">RCLK_c</A>)
--------
8.415 (28.7% logic, 71.3% route), 6 logic levels.
Clock Skew Details:
<A href="#@path:PERIOD NET 'RCLK_c' 16.000000 ns ;:ROUTE, 1.425,86.PADDI,R8C8D.CLK,RCLK_c">Source Clock Path</A> RCLK to SLICE_7:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.425<A href="#@net:RCLK_c:86.PADDI:R8C8D.CLK:1.425"> 86.PADDI to R8C8D.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
<A href="#@path:PERIOD NET 'RCLK_c' 16.000000 ns ;:ROUTE, 1.425,86.PADDI,R9C8D.CLK,RCLK_c">Destination Clock Path</A> RCLK to SLICE_56:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.425<A href="#@net:RCLK_c:86.PADDI:R9C8D.CLK:1.425"> 86.PADDI to R9C8D.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000>
Passed: The following path meets requirements by 7.520ns
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_7">FS_571__i15</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: FF Data in <A href="#@comp:SLICE_85">LEDEN_386</A> (to <A href="#@net:RCLK_c">RCLK_c</A> +)
Delay: 8.236ns (29.3% logic, 70.7% route), 6 logic levels.
Constraint Details:
8.236ns physical path delay SLICE_7 to SLICE_85 meets
16.000ns delay constraint less
0.000ns skew and
0.244ns CE_SET requirement (totaling 15.756ns) by 7.520ns
Physical Path Details:
<A href="#@path:PERIOD NET 'RCLK_c' 16.000000 ns ;:REG_DEL, 0.560,R8C8D.CLK,R8C8D.Q1,SLICE_7:ROUTE, 1.475,R8C8D.Q1,R8C9D.B1,FS_15:CTOF_DEL, 0.371,R8C9D.B1,R8C9D.F1,SLICE_78:ROUTE, 1.057,R8C9D.F1,R6C9B.A1,n10:CTOF_DEL, 0.371,R6C9B.A1,R6C9B.F1,SLICE_75:ROUTE, 0.528,R6C9B.F1,R6C9B.C0,n2298:CTOF_DEL, 0.371,R6C9B.C0,R6C9B.F0,SLICE_75:ROUTE, 1.155,R6C9B.F0,R9C9A.D1,n11:CTOF_DEL, 0.371,R9C9A.D1,R9C9A.F1,SLICE_77:ROUTE, 0.903,R9C9A.F1,R10C9A.C1,n2111:CTOF_DEL, 0.371,R10C9A.C1,R10C9A.F1,SLICE_100:ROUTE, 0.703,R10C9A.F1,R9C9D.CE,RCLK_c_enable_25">Data path</A> SLICE_7 to SLICE_85:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R8C8D.CLK to R8C8D.Q1 <A href="#@comp:SLICE_7">SLICE_7</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 3 1.475<A href="#@net:FS_15:R8C8D.Q1:R8C9D.B1:1.475"> R8C8D.Q1 to R8C9D.B1 </A> <A href="#@net:FS_15">FS_15</A>
CTOF_DEL --- 0.371 R8C9D.B1 to R8C9D.F1 <A href="#@comp:SLICE_78">SLICE_78</A>
ROUTE 3 1.057<A href="#@net:n10:R8C9D.F1:R6C9B.A1:1.057"> R8C9D.F1 to R6C9B.A1 </A> <A href="#@net:n10">n10</A>
CTOF_DEL --- 0.371 R6C9B.A1 to R6C9B.F1 <A href="#@comp:SLICE_75">SLICE_75</A>
ROUTE 4 0.528<A href="#@net:n2298:R6C9B.F1:R6C9B.C0:0.528"> R6C9B.F1 to R6C9B.C0 </A> <A href="#@net:n2298">n2298</A>
CTOF_DEL --- 0.371 R6C9B.C0 to R6C9B.F0 <A href="#@comp:SLICE_75">SLICE_75</A>
ROUTE 1 1.155<A href="#@net:n11:R6C9B.F0:R9C9A.D1:1.155"> R6C9B.F0 to R9C9A.D1 </A> <A href="#@net:n11">n11</A>
CTOF_DEL --- 0.371 R9C9A.D1 to R9C9A.F1 <A href="#@comp:SLICE_77">SLICE_77</A>
ROUTE 2 0.903<A href="#@net:n2111:R9C9A.F1:R10C9A.C1:0.903"> R9C9A.F1 to R10C9A.C1 </A> <A href="#@net:n2111">n2111</A>
CTOF_DEL --- 0.371 R10C9A.C1 to R10C9A.F1 <A href="#@comp:SLICE_100">SLICE_100</A>
ROUTE 1 0.703<A href="#@net:RCLK_c_enable_25:R10C9A.F1:R9C9D.CE:0.703"> R10C9A.F1 to R9C9D.CE </A> <A href="#@net:RCLK_c_enable_25">RCLK_c_enable_25</A> (to <A href="#@net:RCLK_c">RCLK_c</A>)
--------
8.236 (29.3% logic, 70.7% route), 6 logic levels.
Clock Skew Details:
<A href="#@path:PERIOD NET 'RCLK_c' 16.000000 ns ;:ROUTE, 1.425,86.PADDI,R8C8D.CLK,RCLK_c">Source Clock Path</A> RCLK to SLICE_7:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.425<A href="#@net:RCLK_c:86.PADDI:R8C8D.CLK:1.425"> 86.PADDI to R8C8D.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
<A href="#@path:PERIOD NET 'RCLK_c' 16.000000 ns ;:ROUTE, 1.425,86.PADDI,R9C9D.CLK,RCLK_c">Destination Clock Path</A> RCLK to SLICE_85:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.425<A href="#@net:RCLK_c:86.PADDI:R9C9D.CLK:1.425"> 86.PADDI to R9C9D.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000>
Passed: The following path meets requirements by 7.549ns
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_7">FS_571__i14</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: FF Data in <A href="#@comp:SLICE_56">n8MEGEN_385</A> (to <A href="#@net:RCLK_c">RCLK_c</A> +)
Delay: 8.207ns (29.4% logic, 70.6% route), 6 logic levels.
Constraint Details:
8.207ns physical path delay SLICE_7 to SLICE_56 meets
16.000ns delay constraint less
0.000ns skew and
0.244ns CE_SET requirement (totaling 15.756ns) by 7.549ns
Physical Path Details:
<A href="#@path:PERIOD NET 'RCLK_c' 16.000000 ns ;:REG_DEL, 0.560,R8C8D.CLK,R8C8D.Q0,SLICE_7:ROUTE, 1.267,R8C8D.Q0,R8C9D.C1,FS_14:CTOF_DEL, 0.371,R8C9D.C1,R8C9D.F1,SLICE_78:ROUTE, 1.057,R8C9D.F1,R6C9B.A1,n10:CTOF_DEL, 0.371,R6C9B.A1,R6C9B.F1,SLICE_75:ROUTE, 0.528,R6C9B.F1,R6C9B.C0,n2298:CTOF_DEL, 0.371,R6C9B.C0,R6C9B.F0,SLICE_75:ROUTE, 1.155,R6C9B.F0,R9C9A.D1,n11:CTOF_DEL, 0.371,R9C9A.D1,R9C9A.F1,SLICE_77:ROUTE, 0.712,R9C9A.F1,R9C9A.B0,n2111:CTOF_DEL, 0.371,R9C9A.B0,R9C9A.F0,SLICE_77:ROUTE, 1.073,R9C9A.F0,R9C8D.CE,RCLK_c_enable_7">Data path</A> SLICE_7 to SLICE_56:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R8C8D.CLK to R8C8D.Q0 <A href="#@comp:SLICE_7">SLICE_7</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 3 1.267<A href="#@net:FS_14:R8C8D.Q0:R8C9D.C1:1.267"> R8C8D.Q0 to R8C9D.C1 </A> <A href="#@net:FS_14">FS_14</A>
CTOF_DEL --- 0.371 R8C9D.C1 to R8C9D.F1 <A href="#@comp:SLICE_78">SLICE_78</A>
ROUTE 3 1.057<A href="#@net:n10:R8C9D.F1:R6C9B.A1:1.057"> R8C9D.F1 to R6C9B.A1 </A> <A href="#@net:n10">n10</A>
CTOF_DEL --- 0.371 R6C9B.A1 to R6C9B.F1 <A href="#@comp:SLICE_75">SLICE_75</A>
ROUTE 4 0.528<A href="#@net:n2298:R6C9B.F1:R6C9B.C0:0.528"> R6C9B.F1 to R6C9B.C0 </A> <A href="#@net:n2298">n2298</A>
CTOF_DEL --- 0.371 R6C9B.C0 to R6C9B.F0 <A href="#@comp:SLICE_75">SLICE_75</A>
ROUTE 1 1.155<A href="#@net:n11:R6C9B.F0:R9C9A.D1:1.155"> R6C9B.F0 to R9C9A.D1 </A> <A href="#@net:n11">n11</A>
CTOF_DEL --- 0.371 R9C9A.D1 to R9C9A.F1 <A href="#@comp:SLICE_77">SLICE_77</A>
ROUTE 2 0.712<A href="#@net:n2111:R9C9A.F1:R9C9A.B0:0.712"> R9C9A.F1 to R9C9A.B0 </A> <A href="#@net:n2111">n2111</A>
CTOF_DEL --- 0.371 R9C9A.B0 to R9C9A.F0 <A href="#@comp:SLICE_77">SLICE_77</A>
ROUTE 1 1.073<A href="#@net:RCLK_c_enable_7:R9C9A.F0:R9C8D.CE:1.073"> R9C9A.F0 to R9C8D.CE </A> <A href="#@net:RCLK_c_enable_7">RCLK_c_enable_7</A> (to <A href="#@net:RCLK_c">RCLK_c</A>)
--------
8.207 (29.4% logic, 70.6% route), 6 logic levels.
Clock Skew Details:
<A href="#@path:PERIOD NET 'RCLK_c' 16.000000 ns ;:ROUTE, 1.425,86.PADDI,R8C8D.CLK,RCLK_c">Source Clock Path</A> RCLK to SLICE_7:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.425<A href="#@net:RCLK_c:86.PADDI:R8C8D.CLK:1.425"> 86.PADDI to R8C8D.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
<A href="#@path:PERIOD NET 'RCLK_c' 16.000000 ns ;:ROUTE, 1.425,86.PADDI,R9C8D.CLK,RCLK_c">Destination Clock Path</A> RCLK to SLICE_56:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.425<A href="#@net:RCLK_c:86.PADDI:R9C8D.CLK:1.425"> 86.PADDI to R9C8D.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000>
Passed: The following path meets requirements by 7.728ns
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_7">FS_571__i14</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: FF Data in <A href="#@comp:SLICE_85">LEDEN_386</A> (to <A href="#@net:RCLK_c">RCLK_c</A> +)
Delay: 8.028ns (30.1% logic, 69.9% route), 6 logic levels.
Constraint Details:
8.028ns physical path delay SLICE_7 to SLICE_85 meets
16.000ns delay constraint less
0.000ns skew and
0.244ns CE_SET requirement (totaling 15.756ns) by 7.728ns
Physical Path Details:
<A href="#@path:PERIOD NET 'RCLK_c' 16.000000 ns ;:REG_DEL, 0.560,R8C8D.CLK,R8C8D.Q0,SLICE_7:ROUTE, 1.267,R8C8D.Q0,R8C9D.C1,FS_14:CTOF_DEL, 0.371,R8C9D.C1,R8C9D.F1,SLICE_78:ROUTE, 1.057,R8C9D.F1,R6C9B.A1,n10:CTOF_DEL, 0.371,R6C9B.A1,R6C9B.F1,SLICE_75:ROUTE, 0.528,R6C9B.F1,R6C9B.C0,n2298:CTOF_DEL, 0.371,R6C9B.C0,R6C9B.F0,SLICE_75:ROUTE, 1.155,R6C9B.F0,R9C9A.D1,n11:CTOF_DEL, 0.371,R9C9A.D1,R9C9A.F1,SLICE_77:ROUTE, 0.903,R9C9A.F1,R10C9A.C1,n2111:CTOF_DEL, 0.371,R10C9A.C1,R10C9A.F1,SLICE_100:ROUTE, 0.703,R10C9A.F1,R9C9D.CE,RCLK_c_enable_25">Data path</A> SLICE_7 to SLICE_85:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R8C8D.CLK to R8C8D.Q0 <A href="#@comp:SLICE_7">SLICE_7</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 3 1.267<A href="#@net:FS_14:R8C8D.Q0:R8C9D.C1:1.267"> R8C8D.Q0 to R8C9D.C1 </A> <A href="#@net:FS_14">FS_14</A>
CTOF_DEL --- 0.371 R8C9D.C1 to R8C9D.F1 <A href="#@comp:SLICE_78">SLICE_78</A>
ROUTE 3 1.057<A href="#@net:n10:R8C9D.F1:R6C9B.A1:1.057"> R8C9D.F1 to R6C9B.A1 </A> <A href="#@net:n10">n10</A>
CTOF_DEL --- 0.371 R6C9B.A1 to R6C9B.F1 <A href="#@comp:SLICE_75">SLICE_75</A>
ROUTE 4 0.528<A href="#@net:n2298:R6C9B.F1:R6C9B.C0:0.528"> R6C9B.F1 to R6C9B.C0 </A> <A href="#@net:n2298">n2298</A>
CTOF_DEL --- 0.371 R6C9B.C0 to R6C9B.F0 <A href="#@comp:SLICE_75">SLICE_75</A>
ROUTE 1 1.155<A href="#@net:n11:R6C9B.F0:R9C9A.D1:1.155"> R6C9B.F0 to R9C9A.D1 </A> <A href="#@net:n11">n11</A>
CTOF_DEL --- 0.371 R9C9A.D1 to R9C9A.F1 <A href="#@comp:SLICE_77">SLICE_77</A>
ROUTE 2 0.903<A href="#@net:n2111:R9C9A.F1:R10C9A.C1:0.903"> R9C9A.F1 to R10C9A.C1 </A> <A href="#@net:n2111">n2111</A>
CTOF_DEL --- 0.371 R10C9A.C1 to R10C9A.F1 <A href="#@comp:SLICE_100">SLICE_100</A>
ROUTE 1 0.703<A href="#@net:RCLK_c_enable_25:R10C9A.F1:R9C9D.CE:0.703"> R10C9A.F1 to R9C9D.CE </A> <A href="#@net:RCLK_c_enable_25">RCLK_c_enable_25</A> (to <A href="#@net:RCLK_c">RCLK_c</A>)
--------
8.028 (30.1% logic, 69.9% route), 6 logic levels.
Clock Skew Details:
<A href="#@path:PERIOD NET 'RCLK_c' 16.000000 ns ;:ROUTE, 1.425,86.PADDI,R8C8D.CLK,RCLK_c">Source Clock Path</A> RCLK to SLICE_7:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.425<A href="#@net:RCLK_c:86.PADDI:R8C8D.CLK:1.425"> 86.PADDI to R8C8D.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
<A href="#@path:PERIOD NET 'RCLK_c' 16.000000 ns ;:ROUTE, 1.425,86.PADDI,R9C9D.CLK,RCLK_c">Destination Clock Path</A> RCLK to SLICE_85:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.425<A href="#@net:RCLK_c:86.PADDI:R9C9D.CLK:1.425"> 86.PADDI to R9C9D.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000>
Passed: The following path meets requirements by 7.768ns
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_8">FS_571__i13</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: FF Data in <A href="#@comp:SLICE_56">n8MEGEN_385</A> (to <A href="#@net:RCLK_c">RCLK_c</A> +)
Delay: 7.988ns (30.2% logic, 69.8% route), 6 logic levels.
Constraint Details:
7.988ns physical path delay SLICE_8 to SLICE_56 meets
16.000ns delay constraint less
0.000ns skew and
0.244ns CE_SET requirement (totaling 15.756ns) by 7.768ns
Physical Path Details:
<A href="#@path:PERIOD NET 'RCLK_c' 16.000000 ns ;:REG_DEL, 0.560,R8C8C.CLK,R8C8C.Q1,SLICE_8:ROUTE, 1.048,R8C8C.Q1,R8C9D.A1,FS_13:CTOF_DEL, 0.371,R8C9D.A1,R8C9D.F1,SLICE_78:ROUTE, 1.057,R8C9D.F1,R6C9B.A1,n10:CTOF_DEL, 0.371,R6C9B.A1,R6C9B.F1,SLICE_75:ROUTE, 0.528,R6C9B.F1,R6C9B.C0,n2298:CTOF_DEL, 0.371,R6C9B.C0,R6C9B.F0,SLICE_75:ROUTE, 1.155,R6C9B.F0,R9C9A.D1,n11:CTOF_DEL, 0.371,R9C9A.D1,R9C9A.F1,SLICE_77:ROUTE, 0.712,R9C9A.F1,R9C9A.B0,n2111:CTOF_DEL, 0.371,R9C9A.B0,R9C9A.F0,SLICE_77:ROUTE, 1.073,R9C9A.F0,R9C8D.CE,RCLK_c_enable_7">Data path</A> SLICE_8 to SLICE_56:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R8C8C.CLK to R8C8C.Q1 <A href="#@comp:SLICE_8">SLICE_8</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 3 1.048<A href="#@net:FS_13:R8C8C.Q1:R8C9D.A1:1.048"> R8C8C.Q1 to R8C9D.A1 </A> <A href="#@net:FS_13">FS_13</A>
CTOF_DEL --- 0.371 R8C9D.A1 to R8C9D.F1 <A href="#@comp:SLICE_78">SLICE_78</A>
ROUTE 3 1.057<A href="#@net:n10:R8C9D.F1:R6C9B.A1:1.057"> R8C9D.F1 to R6C9B.A1 </A> <A href="#@net:n10">n10</A>
CTOF_DEL --- 0.371 R6C9B.A1 to R6C9B.F1 <A href="#@comp:SLICE_75">SLICE_75</A>
ROUTE 4 0.528<A href="#@net:n2298:R6C9B.F1:R6C9B.C0:0.528"> R6C9B.F1 to R6C9B.C0 </A> <A href="#@net:n2298">n2298</A>
CTOF_DEL --- 0.371 R6C9B.C0 to R6C9B.F0 <A href="#@comp:SLICE_75">SLICE_75</A>
ROUTE 1 1.155<A href="#@net:n11:R6C9B.F0:R9C9A.D1:1.155"> R6C9B.F0 to R9C9A.D1 </A> <A href="#@net:n11">n11</A>
CTOF_DEL --- 0.371 R9C9A.D1 to R9C9A.F1 <A href="#@comp:SLICE_77">SLICE_77</A>
ROUTE 2 0.712<A href="#@net:n2111:R9C9A.F1:R9C9A.B0:0.712"> R9C9A.F1 to R9C9A.B0 </A> <A href="#@net:n2111">n2111</A>
CTOF_DEL --- 0.371 R9C9A.B0 to R9C9A.F0 <A href="#@comp:SLICE_77">SLICE_77</A>
ROUTE 1 1.073<A href="#@net:RCLK_c_enable_7:R9C9A.F0:R9C8D.CE:1.073"> R9C9A.F0 to R9C8D.CE </A> <A href="#@net:RCLK_c_enable_7">RCLK_c_enable_7</A> (to <A href="#@net:RCLK_c">RCLK_c</A>)
--------
7.988 (30.2% logic, 69.8% route), 6 logic levels.
Clock Skew Details:
<A href="#@path:PERIOD NET 'RCLK_c' 16.000000 ns ;:ROUTE, 1.425,86.PADDI,R8C8C.CLK,RCLK_c">Source Clock Path</A> RCLK to SLICE_8:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.425<A href="#@net:RCLK_c:86.PADDI:R8C8C.CLK:1.425"> 86.PADDI to R8C8C.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
<A href="#@path:PERIOD NET 'RCLK_c' 16.000000 ns ;:ROUTE, 1.425,86.PADDI,R9C8D.CLK,RCLK_c">Destination Clock Path</A> RCLK to SLICE_56:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.425<A href="#@net:RCLK_c:86.PADDI:R9C8D.CLK:1.425"> 86.PADDI to R9C8D.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000>
Passed: The following path meets requirements by 7.947ns
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_8">FS_571__i13</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: FF Data in <A href="#@comp:SLICE_85">LEDEN_386</A> (to <A href="#@net:RCLK_c">RCLK_c</A> +)
Delay: 7.809ns (30.9% logic, 69.1% route), 6 logic levels.
Constraint Details:
7.809ns physical path delay SLICE_8 to SLICE_85 meets
16.000ns delay constraint less
0.000ns skew and
0.244ns CE_SET requirement (totaling 15.756ns) by 7.947ns
Physical Path Details:
<A href="#@path:PERIOD NET 'RCLK_c' 16.000000 ns ;:REG_DEL, 0.560,R8C8C.CLK,R8C8C.Q1,SLICE_8:ROUTE, 1.048,R8C8C.Q1,R8C9D.A1,FS_13:CTOF_DEL, 0.371,R8C9D.A1,R8C9D.F1,SLICE_78:ROUTE, 1.057,R8C9D.F1,R6C9B.A1,n10:CTOF_DEL, 0.371,R6C9B.A1,R6C9B.F1,SLICE_75:ROUTE, 0.528,R6C9B.F1,R6C9B.C0,n2298:CTOF_DEL, 0.371,R6C9B.C0,R6C9B.F0,SLICE_75:ROUTE, 1.155,R6C9B.F0,R9C9A.D1,n11:CTOF_DEL, 0.371,R9C9A.D1,R9C9A.F1,SLICE_77:ROUTE, 0.903,R9C9A.F1,R10C9A.C1,n2111:CTOF_DEL, 0.371,R10C9A.C1,R10C9A.F1,SLICE_100:ROUTE, 0.703,R10C9A.F1,R9C9D.CE,RCLK_c_enable_25">Data path</A> SLICE_8 to SLICE_85:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R8C8C.CLK to R8C8C.Q1 <A href="#@comp:SLICE_8">SLICE_8</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 3 1.048<A href="#@net:FS_13:R8C8C.Q1:R8C9D.A1:1.048"> R8C8C.Q1 to R8C9D.A1 </A> <A href="#@net:FS_13">FS_13</A>
CTOF_DEL --- 0.371 R8C9D.A1 to R8C9D.F1 <A href="#@comp:SLICE_78">SLICE_78</A>
ROUTE 3 1.057<A href="#@net:n10:R8C9D.F1:R6C9B.A1:1.057"> R8C9D.F1 to R6C9B.A1 </A> <A href="#@net:n10">n10</A>
CTOF_DEL --- 0.371 R6C9B.A1 to R6C9B.F1 <A href="#@comp:SLICE_75">SLICE_75</A>
ROUTE 4 0.528<A href="#@net:n2298:R6C9B.F1:R6C9B.C0:0.528"> R6C9B.F1 to R6C9B.C0 </A> <A href="#@net:n2298">n2298</A>
CTOF_DEL --- 0.371 R6C9B.C0 to R6C9B.F0 <A href="#@comp:SLICE_75">SLICE_75</A>
ROUTE 1 1.155<A href="#@net:n11:R6C9B.F0:R9C9A.D1:1.155"> R6C9B.F0 to R9C9A.D1 </A> <A href="#@net:n11">n11</A>
CTOF_DEL --- 0.371 R9C9A.D1 to R9C9A.F1 <A href="#@comp:SLICE_77">SLICE_77</A>
ROUTE 2 0.903<A href="#@net:n2111:R9C9A.F1:R10C9A.C1:0.903"> R9C9A.F1 to R10C9A.C1 </A> <A href="#@net:n2111">n2111</A>
CTOF_DEL --- 0.371 R10C9A.C1 to R10C9A.F1 <A href="#@comp:SLICE_100">SLICE_100</A>
ROUTE 1 0.703<A href="#@net:RCLK_c_enable_25:R10C9A.F1:R9C9D.CE:0.703"> R10C9A.F1 to R9C9D.CE </A> <A href="#@net:RCLK_c_enable_25">RCLK_c_enable_25</A> (to <A href="#@net:RCLK_c">RCLK_c</A>)
--------
7.809 (30.9% logic, 69.1% route), 6 logic levels.
Clock Skew Details:
<A href="#@path:PERIOD NET 'RCLK_c' 16.000000 ns ;:ROUTE, 1.425,86.PADDI,R8C8C.CLK,RCLK_c">Source Clock Path</A> RCLK to SLICE_8:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.425<A href="#@net:RCLK_c:86.PADDI:R8C8C.CLK:1.425"> 86.PADDI to R8C8C.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
<A href="#@path:PERIOD NET 'RCLK_c' 16.000000 ns ;:ROUTE, 1.425,86.PADDI,R9C9D.CLK,RCLK_c">Destination Clock Path</A> RCLK to SLICE_85:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.425<A href="#@net:RCLK_c:86.PADDI:R9C9D.CLK:1.425"> 86.PADDI to R9C9D.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000>
Passed: The following path meets requirements by 8.079ns
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_7">FS_571__i15</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: FF Data in <A href="#@comp:SLICE_56">n8MEGEN_385</A> (to <A href="#@net:RCLK_c">RCLK_c</A> +)
Delay: 7.677ns (26.6% logic, 73.4% route), 5 logic levels.
Constraint Details:
7.677ns physical path delay SLICE_7 to SLICE_56 meets
16.000ns delay constraint less
0.000ns skew and
0.244ns CE_SET requirement (totaling 15.756ns) by 8.079ns
Physical Path Details:
<A href="#@path:PERIOD NET 'RCLK_c' 16.000000 ns ;:REG_DEL, 0.560,R8C8D.CLK,R8C8D.Q1,SLICE_7:ROUTE, 1.475,R8C8D.Q1,R8C9D.B1,FS_15:CTOF_DEL, 0.371,R8C9D.B1,R8C9D.F1,SLICE_78:ROUTE, 0.989,R8C9D.F1,R8C9B.A1,n10:CTOF_DEL, 0.371,R8C9B.A1,R8C9B.F1,SLICE_94:ROUTE, 1.384,R8C9B.F1,R9C9A.A1,n2292:CTOF_DEL, 0.371,R9C9A.A1,R9C9A.F1,SLICE_77:ROUTE, 0.712,R9C9A.F1,R9C9A.B0,n2111:CTOF_DEL, 0.371,R9C9A.B0,R9C9A.F0,SLICE_77:ROUTE, 1.073,R9C9A.F0,R9C8D.CE,RCLK_c_enable_7">Data path</A> SLICE_7 to SLICE_56:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R8C8D.CLK to R8C8D.Q1 <A href="#@comp:SLICE_7">SLICE_7</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 3 1.475<A href="#@net:FS_15:R8C8D.Q1:R8C9D.B1:1.475"> R8C8D.Q1 to R8C9D.B1 </A> <A href="#@net:FS_15">FS_15</A>
CTOF_DEL --- 0.371 R8C9D.B1 to R8C9D.F1 <A href="#@comp:SLICE_78">SLICE_78</A>
ROUTE 3 0.989<A href="#@net:n10:R8C9D.F1:R8C9B.A1:0.989"> R8C9D.F1 to R8C9B.A1 </A> <A href="#@net:n10">n10</A>
CTOF_DEL --- 0.371 R8C9B.A1 to R8C9B.F1 <A href="#@comp:SLICE_94">SLICE_94</A>
ROUTE 1 1.384<A href="#@net:n2292:R8C9B.F1:R9C9A.A1:1.384"> R8C9B.F1 to R9C9A.A1 </A> <A href="#@net:n2292">n2292</A>
CTOF_DEL --- 0.371 R9C9A.A1 to R9C9A.F1 <A href="#@comp:SLICE_77">SLICE_77</A>
ROUTE 2 0.712<A href="#@net:n2111:R9C9A.F1:R9C9A.B0:0.712"> R9C9A.F1 to R9C9A.B0 </A> <A href="#@net:n2111">n2111</A>
CTOF_DEL --- 0.371 R9C9A.B0 to R9C9A.F0 <A href="#@comp:SLICE_77">SLICE_77</A>
ROUTE 1 1.073<A href="#@net:RCLK_c_enable_7:R9C9A.F0:R9C8D.CE:1.073"> R9C9A.F0 to R9C8D.CE </A> <A href="#@net:RCLK_c_enable_7">RCLK_c_enable_7</A> (to <A href="#@net:RCLK_c">RCLK_c</A>)
--------
7.677 (26.6% logic, 73.4% route), 5 logic levels.
Clock Skew Details:
<A href="#@path:PERIOD NET 'RCLK_c' 16.000000 ns ;:ROUTE, 1.425,86.PADDI,R8C8D.CLK,RCLK_c">Source Clock Path</A> RCLK to SLICE_7:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.425<A href="#@net:RCLK_c:86.PADDI:R8C8D.CLK:1.425"> 86.PADDI to R8C8D.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
<A href="#@path:PERIOD NET 'RCLK_c' 16.000000 ns ;:ROUTE, 1.425,86.PADDI,R9C8D.CLK,RCLK_c">Destination Clock Path</A> RCLK to SLICE_56:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.425<A href="#@net:RCLK_c:86.PADDI:R9C8D.CLK:1.425"> 86.PADDI to R9C8D.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000>
Passed: The following path meets requirements by 8.092ns
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_8">FS_571__i12</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: FF Data in <A href="#@comp:SLICE_56">n8MEGEN_385</A> (to <A href="#@net:RCLK_c">RCLK_c</A> +)
Delay: 7.664ns (31.5% logic, 68.5% route), 6 logic levels.
Constraint Details:
7.664ns physical path delay SLICE_8 to SLICE_56 meets
16.000ns delay constraint less
0.000ns skew and
0.244ns CE_SET requirement (totaling 15.756ns) by 8.092ns
Physical Path Details:
<A href="#@path:PERIOD NET 'RCLK_c' 16.000000 ns ;:REG_DEL, 0.560,R8C8C.CLK,R8C8C.Q0,SLICE_8:ROUTE, 0.724,R8C8C.Q0,R8C9D.D1,FS_12:CTOF_DEL, 0.371,R8C9D.D1,R8C9D.F1,SLICE_78:ROUTE, 1.057,R8C9D.F1,R6C9B.A1,n10:CTOF_DEL, 0.371,R6C9B.A1,R6C9B.F1,SLICE_75:ROUTE, 0.528,R6C9B.F1,R6C9B.C0,n2298:CTOF_DEL, 0.371,R6C9B.C0,R6C9B.F0,SLICE_75:ROUTE, 1.155,R6C9B.F0,R9C9A.D1,n11:CTOF_DEL, 0.371,R9C9A.D1,R9C9A.F1,SLICE_77:ROUTE, 0.712,R9C9A.F1,R9C9A.B0,n2111:CTOF_DEL, 0.371,R9C9A.B0,R9C9A.F0,SLICE_77:ROUTE, 1.073,R9C9A.F0,R9C8D.CE,RCLK_c_enable_7">Data path</A> SLICE_8 to SLICE_56:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R8C8C.CLK to R8C8C.Q0 <A href="#@comp:SLICE_8">SLICE_8</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 3 0.724<A href="#@net:FS_12:R8C8C.Q0:R8C9D.D1:0.724"> R8C8C.Q0 to R8C9D.D1 </A> <A href="#@net:FS_12">FS_12</A>
CTOF_DEL --- 0.371 R8C9D.D1 to R8C9D.F1 <A href="#@comp:SLICE_78">SLICE_78</A>
ROUTE 3 1.057<A href="#@net:n10:R8C9D.F1:R6C9B.A1:1.057"> R8C9D.F1 to R6C9B.A1 </A> <A href="#@net:n10">n10</A>
CTOF_DEL --- 0.371 R6C9B.A1 to R6C9B.F1 <A href="#@comp:SLICE_75">SLICE_75</A>
ROUTE 4 0.528<A href="#@net:n2298:R6C9B.F1:R6C9B.C0:0.528"> R6C9B.F1 to R6C9B.C0 </A> <A href="#@net:n2298">n2298</A>
CTOF_DEL --- 0.371 R6C9B.C0 to R6C9B.F0 <A href="#@comp:SLICE_75">SLICE_75</A>
ROUTE 1 1.155<A href="#@net:n11:R6C9B.F0:R9C9A.D1:1.155"> R6C9B.F0 to R9C9A.D1 </A> <A href="#@net:n11">n11</A>
CTOF_DEL --- 0.371 R9C9A.D1 to R9C9A.F1 <A href="#@comp:SLICE_77">SLICE_77</A>
ROUTE 2 0.712<A href="#@net:n2111:R9C9A.F1:R9C9A.B0:0.712"> R9C9A.F1 to R9C9A.B0 </A> <A href="#@net:n2111">n2111</A>
CTOF_DEL --- 0.371 R9C9A.B0 to R9C9A.F0 <A href="#@comp:SLICE_77">SLICE_77</A>
ROUTE 1 1.073<A href="#@net:RCLK_c_enable_7:R9C9A.F0:R9C8D.CE:1.073"> R9C9A.F0 to R9C8D.CE </A> <A href="#@net:RCLK_c_enable_7">RCLK_c_enable_7</A> (to <A href="#@net:RCLK_c">RCLK_c</A>)
--------
7.664 (31.5% logic, 68.5% route), 6 logic levels.
Clock Skew Details:
<A href="#@path:PERIOD NET 'RCLK_c' 16.000000 ns ;:ROUTE, 1.425,86.PADDI,R8C8C.CLK,RCLK_c">Source Clock Path</A> RCLK to SLICE_8:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.425<A href="#@net:RCLK_c:86.PADDI:R8C8C.CLK:1.425"> 86.PADDI to R8C8C.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
<A href="#@path:PERIOD NET 'RCLK_c' 16.000000 ns ;:ROUTE, 1.425,86.PADDI,R9C8D.CLK,RCLK_c">Destination Clock Path</A> RCLK to SLICE_56:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.425<A href="#@net:RCLK_c:86.PADDI:R9C8D.CLK:1.425"> 86.PADDI to R9C8D.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000>
Passed: The following path meets requirements by 8.177ns
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_5">FS_571__i1</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: FF Data in <A href="#@comp:SLICE_56">n8MEGEN_385</A> (to <A href="#@net:RCLK_c">RCLK_c</A> +)
Delay: 7.579ns (27.0% logic, 73.0% route), 5 logic levels.
Constraint Details:
7.579ns physical path delay SLICE_5 to SLICE_56 meets
16.000ns delay constraint less
0.000ns skew and
0.244ns CE_SET requirement (totaling 15.756ns) by 8.177ns
Physical Path Details:
<A href="#@path:PERIOD NET 'RCLK_c' 16.000000 ns ;:REG_DEL, 0.560,R8C7A.CLK,R8C7A.Q1,SLICE_5:ROUTE, 1.108,R8C7A.Q1,R7C7D.B1,FS_1:CTOF_DEL, 0.371,R7C7D.B1,R7C7D.F1,SLICE_68:ROUTE, 1.487,R7C7D.F1,R6C9B.A0,n2164:CTOF_DEL, 0.371,R6C9B.A0,R6C9B.F0,SLICE_75:ROUTE, 1.155,R6C9B.F0,R9C9A.D1,n11:CTOF_DEL, 0.371,R9C9A.D1,R9C9A.F1,SLICE_77:ROUTE, 0.712,R9C9A.F1,R9C9A.B0,n2111:CTOF_DEL, 0.371,R9C9A.B0,R9C9A.F0,SLICE_77:ROUTE, 1.073,R9C9A.F0,R9C8D.CE,RCLK_c_enable_7">Data path</A> SLICE_5 to SLICE_56:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R8C7A.CLK to R8C7A.Q1 <A href="#@comp:SLICE_5">SLICE_5</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 2 1.108<A href="#@net:FS_1:R8C7A.Q1:R7C7D.B1:1.108"> R8C7A.Q1 to R7C7D.B1 </A> <A href="#@net:FS_1">FS_1</A>
CTOF_DEL --- 0.371 R7C7D.B1 to R7C7D.F1 <A href="#@comp:SLICE_68">SLICE_68</A>
ROUTE 1 1.487<A href="#@net:n2164:R7C7D.F1:R6C9B.A0:1.487"> R7C7D.F1 to R6C9B.A0 </A> <A href="#@net:n2164">n2164</A>
CTOF_DEL --- 0.371 R6C9B.A0 to R6C9B.F0 <A href="#@comp:SLICE_75">SLICE_75</A>
ROUTE 1 1.155<A href="#@net:n11:R6C9B.F0:R9C9A.D1:1.155"> R6C9B.F0 to R9C9A.D1 </A> <A href="#@net:n11">n11</A>
CTOF_DEL --- 0.371 R9C9A.D1 to R9C9A.F1 <A href="#@comp:SLICE_77">SLICE_77</A>
ROUTE 2 0.712<A href="#@net:n2111:R9C9A.F1:R9C9A.B0:0.712"> R9C9A.F1 to R9C9A.B0 </A> <A href="#@net:n2111">n2111</A>
CTOF_DEL --- 0.371 R9C9A.B0 to R9C9A.F0 <A href="#@comp:SLICE_77">SLICE_77</A>
ROUTE 1 1.073<A href="#@net:RCLK_c_enable_7:R9C9A.F0:R9C8D.CE:1.073"> R9C9A.F0 to R9C8D.CE </A> <A href="#@net:RCLK_c_enable_7">RCLK_c_enable_7</A> (to <A href="#@net:RCLK_c">RCLK_c</A>)
--------
7.579 (27.0% logic, 73.0% route), 5 logic levels.
Clock Skew Details:
<A href="#@path:PERIOD NET 'RCLK_c' 16.000000 ns ;:ROUTE, 1.425,86.PADDI,R8C7A.CLK,RCLK_c">Source Clock Path</A> RCLK to SLICE_5:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.425<A href="#@net:RCLK_c:86.PADDI:R8C7A.CLK:1.425"> 86.PADDI to R8C7A.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
<A href="#@path:PERIOD NET 'RCLK_c' 16.000000 ns ;:ROUTE, 1.425,86.PADDI,R9C8D.CLK,RCLK_c">Destination Clock Path</A> RCLK to SLICE_56:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.425<A href="#@net:RCLK_c:86.PADDI:R9C8D.CLK:1.425"> 86.PADDI to R9C8D.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000>
Passed: The following path meets requirements by 8.243ns
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_4">FS_571__i2</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: FF Data in <A href="#@comp:SLICE_56">n8MEGEN_385</A> (to <A href="#@net:RCLK_c">RCLK_c</A> +)
Delay: 7.513ns (27.2% logic, 72.8% route), 5 logic levels.
Constraint Details:
7.513ns physical path delay SLICE_4 to SLICE_56 meets
16.000ns delay constraint less
0.000ns skew and
0.244ns CE_SET requirement (totaling 15.756ns) by 8.243ns
Physical Path Details:
<A href="#@path:PERIOD NET 'RCLK_c' 16.000000 ns ;:REG_DEL, 0.560,R8C7B.CLK,R8C7B.Q0,SLICE_4:ROUTE, 1.042,R8C7B.Q0,R7C7D.A1,FS_2:CTOF_DEL, 0.371,R7C7D.A1,R7C7D.F1,SLICE_68:ROUTE, 1.487,R7C7D.F1,R6C9B.A0,n2164:CTOF_DEL, 0.371,R6C9B.A0,R6C9B.F0,SLICE_75:ROUTE, 1.155,R6C9B.F0,R9C9A.D1,n11:CTOF_DEL, 0.371,R9C9A.D1,R9C9A.F1,SLICE_77:ROUTE, 0.712,R9C9A.F1,R9C9A.B0,n2111:CTOF_DEL, 0.371,R9C9A.B0,R9C9A.F0,SLICE_77:ROUTE, 1.073,R9C9A.F0,R9C8D.CE,RCLK_c_enable_7">Data path</A> SLICE_4 to SLICE_56:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R8C7B.CLK to R8C7B.Q0 <A href="#@comp:SLICE_4">SLICE_4</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 2 1.042<A href="#@net:FS_2:R8C7B.Q0:R7C7D.A1:1.042"> R8C7B.Q0 to R7C7D.A1 </A> <A href="#@net:FS_2">FS_2</A>
CTOF_DEL --- 0.371 R7C7D.A1 to R7C7D.F1 <A href="#@comp:SLICE_68">SLICE_68</A>
ROUTE 1 1.487<A href="#@net:n2164:R7C7D.F1:R6C9B.A0:1.487"> R7C7D.F1 to R6C9B.A0 </A> <A href="#@net:n2164">n2164</A>
CTOF_DEL --- 0.371 R6C9B.A0 to R6C9B.F0 <A href="#@comp:SLICE_75">SLICE_75</A>
ROUTE 1 1.155<A href="#@net:n11:R6C9B.F0:R9C9A.D1:1.155"> R6C9B.F0 to R9C9A.D1 </A> <A href="#@net:n11">n11</A>
CTOF_DEL --- 0.371 R9C9A.D1 to R9C9A.F1 <A href="#@comp:SLICE_77">SLICE_77</A>
ROUTE 2 0.712<A href="#@net:n2111:R9C9A.F1:R9C9A.B0:0.712"> R9C9A.F1 to R9C9A.B0 </A> <A href="#@net:n2111">n2111</A>
CTOF_DEL --- 0.371 R9C9A.B0 to R9C9A.F0 <A href="#@comp:SLICE_77">SLICE_77</A>
ROUTE 1 1.073<A href="#@net:RCLK_c_enable_7:R9C9A.F0:R9C8D.CE:1.073"> R9C9A.F0 to R9C8D.CE </A> <A href="#@net:RCLK_c_enable_7">RCLK_c_enable_7</A> (to <A href="#@net:RCLK_c">RCLK_c</A>)
--------
7.513 (27.2% logic, 72.8% route), 5 logic levels.
Clock Skew Details:
<A href="#@path:PERIOD NET 'RCLK_c' 16.000000 ns ;:ROUTE, 1.425,86.PADDI,R8C7B.CLK,RCLK_c">Source Clock Path</A> RCLK to SLICE_4:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.425<A href="#@net:RCLK_c:86.PADDI:R8C7B.CLK:1.425"> 86.PADDI to R8C7B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
<A href="#@path:PERIOD NET 'RCLK_c' 16.000000 ns ;:ROUTE, 1.425,86.PADDI,R9C8D.CLK,RCLK_c">Destination Clock Path</A> RCLK to SLICE_56:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.425<A href="#@net:RCLK_c:86.PADDI:R9C8D.CLK:1.425"> 86.PADDI to R9C8D.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
1.425 (0.0% logic, 100.0% route), 0 logic levels.
Report: 8.659ns is the minimum period for this preference.
</A><A name="CLOCK_TO_OUT PORT 'RD[0]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'RD[0]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'Dout[0]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'Dout[0]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'Dout[7]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'Dout[7]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'Dout[6]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'Dout[6]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'Dout[5]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'Dout[5]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'Dout[4]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'Dout[4]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'Dout[3]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'Dout[3]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'Dout[2]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'Dout[2]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'Dout[1]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'Dout[1]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'RBA[1]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'RBA[1]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'RBA[0]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'RBA[0]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'RA[11]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'RA[11]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'RA[10]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 4.999ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_55">RA10_368</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:RA[10]">RA[10]</A>
Data Path Delay: 5.013ns (83.7% logic, 16.3% route), 2 logic levels.
Clock Path Delay: 2.488ns (42.7% logic, 57.3% route), 1 logic levels.
Constraint Details:
2.488ns delay RCLK to SLICE_55 and
5.013ns delay SLICE_55 to RA[10] (totaling 7.501ns) meets
12.500ns offset RCLK to RA[10] by 4.999ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'RA[10]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 1.063,86.PAD,86.PADDI,RCLK:ROUTE, 1.425,86.PADDI,R2C5A.CLK,RCLK_c">Clock path</A> RCLK to SLICE_55:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 1.425<A href="#@net:RCLK_c:86.PADDI:R2C5A.CLK:1.425"> 86.PADDI to R2C5A.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
2.488 (42.7% logic, 57.3% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'RA[10]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.560,R2C5A.CLK,R2C5A.Q0,SLICE_55:ROUTE, 0.817,R2C5A.Q0,87.PADDO,n974:DOPAD_DEL, 3.636,87.PADDO,87.PAD,RA[10]">Data path</A> SLICE_55 to RA[10]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C5A.CLK to R2C5A.Q0 <A href="#@comp:SLICE_55">SLICE_55</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 1 0.817<A href="#@net:n974:R2C5A.Q0:87.PADDO:0.817"> R2C5A.Q0 to 87.PADDO </A> <A href="#@net:n974">n974</A>
DOPAD_DEL --- 3.636 87.PADDO to 87.PAD <A href="#@comp:RA[10]">RA[10]</A>
--------
5.013 (83.7% logic, 16.3% route), 2 logic levels.
Report: 7.501ns is the minimum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'RA[10]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 6.396ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_55">RA10_368</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:RA[10]">RA[10]</A>
Data Path Delay: 4.797ns (86.5% logic, 13.5% route), 2 logic levels.
Clock Path Delay: 1.599ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
1.599ns delay RCLK to SLICE_55 and
4.797ns delay SLICE_55 to RA[10] (totaling 6.396ns) meets
0.000ns hold offset RCLK to RA[10] by 6.396ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'RA[10]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.867,86.PAD,86.PADDI,RCLK:ROUTE, 0.732,86.PADDI,R2C5A.CLK,RCLK_c">Clock path</A> RCLK to SLICE_55:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.867 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 0.732<A href="#@net:RCLK_c:86.PADDI:R2C5A.CLK:0.732"> 86.PADDI to R2C5A.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
1.599 (54.2% logic, 45.8% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'RA[10]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.515,R2C5A.CLK,R2C5A.Q0,SLICE_55:ROUTE, 0.646,R2C5A.Q0,87.PADDO,n974:DOPAD_DEL, 3.636,87.PADDO,87.PAD,RA[10]">Data path</A> SLICE_55 to RA[10]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.515 R2C5A.CLK to R2C5A.Q0 <A href="#@comp:SLICE_55">SLICE_55</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 1 0.646<A href="#@net:n974:R2C5A.Q0:87.PADDO:0.646"> R2C5A.Q0 to 87.PADDO </A> <A href="#@net:n974">n974</A>
DOPAD_DEL --- 3.636 87.PADDO to 87.PAD <A href="#@comp:RA[10]">RA[10]</A>
--------
4.797 (86.5% logic, 13.5% route), 2 logic levels.
Report: 6.396ns is the maximum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'RA[9]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 1.477ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:RA[9]">RA[9]</A>
Data Path Delay: 8.535ns (53.5% logic, 46.5% route), 3 logic levels.
Clock Path Delay: 2.488ns (42.7% logic, 57.3% route), 1 logic levels.
Constraint Details:
2.488ns delay RCLK to SLICE_64 and
8.535ns delay SLICE_64 to RA[9] (totaling 11.023ns) meets
12.500ns offset RCLK to RA[9] by 1.477ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'RA[9]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 1.063,86.PAD,86.PADDI,RCLK:ROUTE, 1.425,86.PADDI,R2C6A.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 1.425<A href="#@net:RCLK_c:86.PADDI:R2C6A.CLK:1.425"> 86.PADDI to R2C6A.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
2.488 (42.7% logic, 57.3% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'RA[9]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.560,R2C6A.CLK,R2C6A.Q0,SLICE_64:ROUTE, 1.796,R2C6A.Q0,R6C9A.D1,nRowColSel:CTOF_DEL, 0.371,R6C9A.D1,R6C9A.F1,SLICE_87:ROUTE, 2.172,R6C9A.F1,85.PADDO,RA_c_9:DOPAD_DEL, 3.636,85.PADDO,85.PAD,RA[9]">Data path</A> SLICE_64 to RA[9]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C6A.CLK to R2C6A.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 13 1.796<A href="#@net:nRowColSel:R2C6A.Q0:R6C9A.D1:1.796"> R2C6A.Q0 to R6C9A.D1 </A> <A href="#@net:nRowColSel">nRowColSel</A>
CTOF_DEL --- 0.371 R6C9A.D1 to R6C9A.F1 <A href="#@comp:SLICE_87">SLICE_87</A>
ROUTE 1 2.172<A href="#@net:RA_c_9:R6C9A.F1:85.PADDO:2.172"> R6C9A.F1 to 85.PADDO </A> <A href="#@net:RA_c_9">RA_c_9</A>
DOPAD_DEL --- 3.636 85.PADDO to 85.PAD <A href="#@comp:RA[9]">RA[9]</A>
--------
8.535 (53.5% logic, 46.5% route), 3 logic levels.
Report: 11.023ns is the minimum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'RA[9]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 9.323ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:RA[9]">RA[9]</A>
Data Path Delay: 7.724ns (57.6% logic, 42.4% route), 3 logic levels.
Clock Path Delay: 1.599ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
1.599ns delay RCLK to SLICE_64 and
7.724ns delay SLICE_64 to RA[9] (totaling 9.323ns) meets
0.000ns hold offset RCLK to RA[9] by 9.323ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'RA[9]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.867,86.PAD,86.PADDI,RCLK:ROUTE, 0.732,86.PADDI,R2C6A.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.867 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 0.732<A href="#@net:RCLK_c:86.PADDI:R2C6A.CLK:0.732"> 86.PADDI to R2C6A.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
1.599 (54.2% logic, 45.8% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'RA[9]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.515,R2C6A.CLK,R2C6A.Q0,SLICE_64:ROUTE, 1.549,R2C6A.Q0,R6C9A.D1,nRowColSel:CTOF_DEL, 0.301,R6C9A.D1,R6C9A.F1,SLICE_87:ROUTE, 1.723,R6C9A.F1,85.PADDO,RA_c_9:DOPAD_DEL, 3.636,85.PADDO,85.PAD,RA[9]">Data path</A> SLICE_64 to RA[9]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.515 R2C6A.CLK to R2C6A.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 13 1.549<A href="#@net:nRowColSel:R2C6A.Q0:R6C9A.D1:1.549"> R2C6A.Q0 to R6C9A.D1 </A> <A href="#@net:nRowColSel">nRowColSel</A>
CTOF_DEL --- 0.301 R6C9A.D1 to R6C9A.F1 <A href="#@comp:SLICE_87">SLICE_87</A>
ROUTE 1 1.723<A href="#@net:RA_c_9:R6C9A.F1:85.PADDO:1.723"> R6C9A.F1 to 85.PADDO </A> <A href="#@net:RA_c_9">RA_c_9</A>
DOPAD_DEL --- 3.636 85.PADDO to 85.PAD <A href="#@comp:RA[9]">RA[9]</A>
--------
7.724 (57.6% logic, 42.4% route), 3 logic levels.
Report: 9.323ns is the maximum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'RA[8]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.460ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:RA[8]">RA[8]</A>
Data Path Delay: 7.552ns (60.5% logic, 39.5% route), 3 logic levels.
Clock Path Delay: 2.488ns (42.7% logic, 57.3% route), 1 logic levels.
Constraint Details:
2.488ns delay RCLK to SLICE_64 and
7.552ns delay SLICE_64 to RA[8] (totaling 10.040ns) meets
12.500ns offset RCLK to RA[8] by 2.460ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'RA[8]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 1.063,86.PAD,86.PADDI,RCLK:ROUTE, 1.425,86.PADDI,R2C6A.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 1.425<A href="#@net:RCLK_c:86.PADDI:R2C6A.CLK:1.425"> 86.PADDI to R2C6A.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
2.488 (42.7% logic, 57.3% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'RA[8]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.560,R2C6A.CLK,R2C6A.Q0,SLICE_64:ROUTE, 1.459,R2C6A.Q0,R2C2A.C0,nRowColSel:CTOF_DEL, 0.371,R2C2A.C0,R2C2A.F0,SLICE_98:ROUTE, 1.526,R2C2A.F0,96.PADDO,RA_c_8:DOPAD_DEL, 3.636,96.PADDO,96.PAD,RA[8]">Data path</A> SLICE_64 to RA[8]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C6A.CLK to R2C6A.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 13 1.459<A href="#@net:nRowColSel:R2C6A.Q0:R2C2A.C0:1.459"> R2C6A.Q0 to R2C2A.C0 </A> <A href="#@net:nRowColSel">nRowColSel</A>
CTOF_DEL --- 0.371 R2C2A.C0 to R2C2A.F0 <A href="#@comp:SLICE_98">SLICE_98</A>
ROUTE 1 1.526<A href="#@net:RA_c_8:R2C2A.F0:96.PADDO:1.526"> R2C2A.F0 to 96.PADDO </A> <A href="#@net:RA_c_8">RA_c_8</A>
DOPAD_DEL --- 3.636 96.PADDO to 96.PAD <A href="#@comp:RA[8]">RA[8]</A>
--------
7.552 (60.5% logic, 39.5% route), 3 logic levels.
Report: 10.040ns is the minimum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'RA[8]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 8.446ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:RA[8]">RA[8]</A>
Data Path Delay: 6.847ns (65.0% logic, 35.0% route), 3 logic levels.
Clock Path Delay: 1.599ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
1.599ns delay RCLK to SLICE_64 and
6.847ns delay SLICE_64 to RA[8] (totaling 8.446ns) meets
0.000ns hold offset RCLK to RA[8] by 8.446ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'RA[8]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.867,86.PAD,86.PADDI,RCLK:ROUTE, 0.732,86.PADDI,R2C6A.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.867 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 0.732<A href="#@net:RCLK_c:86.PADDI:R2C6A.CLK:0.732"> 86.PADDI to R2C6A.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
1.599 (54.2% logic, 45.8% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'RA[8]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.515,R2C6A.CLK,R2C6A.Q0,SLICE_64:ROUTE, 1.230,R2C6A.Q0,R2C2A.C0,nRowColSel:CTOF_DEL, 0.301,R2C2A.C0,R2C2A.F0,SLICE_98:ROUTE, 1.165,R2C2A.F0,96.PADDO,RA_c_8:DOPAD_DEL, 3.636,96.PADDO,96.PAD,RA[8]">Data path</A> SLICE_64 to RA[8]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.515 R2C6A.CLK to R2C6A.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 13 1.230<A href="#@net:nRowColSel:R2C6A.Q0:R2C2A.C0:1.230"> R2C6A.Q0 to R2C2A.C0 </A> <A href="#@net:nRowColSel">nRowColSel</A>
CTOF_DEL --- 0.301 R2C2A.C0 to R2C2A.F0 <A href="#@comp:SLICE_98">SLICE_98</A>
ROUTE 1 1.165<A href="#@net:RA_c_8:R2C2A.F0:96.PADDO:1.165"> R2C2A.F0 to 96.PADDO </A> <A href="#@net:RA_c_8">RA_c_8</A>
DOPAD_DEL --- 3.636 96.PADDO to 96.PAD <A href="#@comp:RA[8]">RA[8]</A>
--------
6.847 (65.0% logic, 35.0% route), 3 logic levels.
Report: 8.446ns is the maximum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'RA[7]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.106ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:RA[7]">RA[7]</A>
Data Path Delay: 7.906ns (57.8% logic, 42.2% route), 3 logic levels.
Clock Path Delay: 2.488ns (42.7% logic, 57.3% route), 1 logic levels.
Constraint Details:
2.488ns delay RCLK to SLICE_64 and
7.906ns delay SLICE_64 to RA[7] (totaling 10.394ns) meets
12.500ns offset RCLK to RA[7] by 2.106ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'RA[7]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 1.063,86.PAD,86.PADDI,RCLK:ROUTE, 1.425,86.PADDI,R2C6A.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 1.425<A href="#@net:RCLK_c:86.PADDI:R2C6A.CLK:1.425"> 86.PADDI to R2C6A.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
2.488 (42.7% logic, 57.3% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'RA[7]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.560,R2C6A.CLK,R2C6A.Q0,SLICE_64:ROUTE, 0.895,R2C6A.Q0,R2C6A.C1,nRowColSel:CTOF_DEL, 0.371,R2C6A.C1,R2C6A.F1,SLICE_64:ROUTE, 2.444,R2C6A.F1,100.PADDO,RA_c_7:DOPAD_DEL, 3.636,100.PADDO,100.PAD,RA[7]">Data path</A> SLICE_64 to RA[7]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C6A.CLK to R2C6A.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 13 0.895<A href="#@net:nRowColSel:R2C6A.Q0:R2C6A.C1:0.895"> R2C6A.Q0 to R2C6A.C1 </A> <A href="#@net:nRowColSel">nRowColSel</A>
CTOF_DEL --- 0.371 R2C6A.C1 to R2C6A.F1 <A href="#@comp:SLICE_64">SLICE_64</A>
ROUTE 1 2.444<A href="#@net:RA_c_7:R2C6A.F1:100.PADDO:2.444"> R2C6A.F1 to 100.PADDO </A> <A href="#@net:RA_c_7">RA_c_7</A>
DOPAD_DEL --- 3.636 100.PADDO to 100.PAD <A href="#@comp:RA[7]">RA[7]</A>
--------
7.906 (57.8% logic, 42.2% route), 3 logic levels.
Report: 10.394ns is the minimum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'RA[7]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 8.766ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:RA[7]">RA[7]</A>
Data Path Delay: 7.167ns (62.1% logic, 37.9% route), 3 logic levels.
Clock Path Delay: 1.599ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
1.599ns delay RCLK to SLICE_64 and
7.167ns delay SLICE_64 to RA[7] (totaling 8.766ns) meets
0.000ns hold offset RCLK to RA[7] by 8.766ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'RA[7]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.867,86.PAD,86.PADDI,RCLK:ROUTE, 0.732,86.PADDI,R2C6A.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.867 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 0.732<A href="#@net:RCLK_c:86.PADDI:R2C6A.CLK:0.732"> 86.PADDI to R2C6A.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
1.599 (54.2% logic, 45.8% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'RA[7]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.515,R2C6A.CLK,R2C6A.Q0,SLICE_64:ROUTE, 0.741,R2C6A.Q0,R2C6A.C1,nRowColSel:CTOF_DEL, 0.301,R2C6A.C1,R2C6A.F1,SLICE_64:ROUTE, 1.974,R2C6A.F1,100.PADDO,RA_c_7:DOPAD_DEL, 3.636,100.PADDO,100.PAD,RA[7]">Data path</A> SLICE_64 to RA[7]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.515 R2C6A.CLK to R2C6A.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 13 0.741<A href="#@net:nRowColSel:R2C6A.Q0:R2C6A.C1:0.741"> R2C6A.Q0 to R2C6A.C1 </A> <A href="#@net:nRowColSel">nRowColSel</A>
CTOF_DEL --- 0.301 R2C6A.C1 to R2C6A.F1 <A href="#@comp:SLICE_64">SLICE_64</A>
ROUTE 1 1.974<A href="#@net:RA_c_7:R2C6A.F1:100.PADDO:1.974"> R2C6A.F1 to 100.PADDO </A> <A href="#@net:RA_c_7">RA_c_7</A>
DOPAD_DEL --- 3.636 100.PADDO to 100.PAD <A href="#@comp:RA[7]">RA[7]</A>
--------
7.167 (62.1% logic, 37.9% route), 3 logic levels.
Report: 8.766ns is the maximum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'RA[6]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.002ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:RA[6]">RA[6]</A>
Data Path Delay: 8.010ns (57.0% logic, 43.0% route), 3 logic levels.
Clock Path Delay: 2.488ns (42.7% logic, 57.3% route), 1 logic levels.
Constraint Details:
2.488ns delay RCLK to SLICE_64 and
8.010ns delay SLICE_64 to RA[6] (totaling 10.498ns) meets
12.500ns offset RCLK to RA[6] by 2.002ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'RA[6]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 1.063,86.PAD,86.PADDI,RCLK:ROUTE, 1.425,86.PADDI,R2C6A.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 1.425<A href="#@net:RCLK_c:86.PADDI:R2C6A.CLK:1.425"> 86.PADDI to R2C6A.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
2.488 (42.7% logic, 57.3% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'RA[6]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.560,R2C6A.CLK,R2C6A.Q0,SLICE_64:ROUTE, 1.459,R2C6A.Q0,R2C2A.C1,nRowColSel:CTOF_DEL, 0.371,R2C2A.C1,R2C2A.F1,SLICE_98:ROUTE, 1.984,R2C2A.F1,91.PADDO,RA_c_6:DOPAD_DEL, 3.636,91.PADDO,91.PAD,RA[6]">Data path</A> SLICE_64 to RA[6]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C6A.CLK to R2C6A.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 13 1.459<A href="#@net:nRowColSel:R2C6A.Q0:R2C2A.C1:1.459"> R2C6A.Q0 to R2C2A.C1 </A> <A href="#@net:nRowColSel">nRowColSel</A>
CTOF_DEL --- 0.371 R2C2A.C1 to R2C2A.F1 <A href="#@comp:SLICE_98">SLICE_98</A>
ROUTE 1 1.984<A href="#@net:RA_c_6:R2C2A.F1:91.PADDO:1.984"> R2C2A.F1 to 91.PADDO </A> <A href="#@net:RA_c_6">RA_c_6</A>
DOPAD_DEL --- 3.636 91.PADDO to 91.PAD <A href="#@comp:RA[6]">RA[6]</A>
--------
8.010 (57.0% logic, 43.0% route), 3 logic levels.
Report: 10.498ns is the minimum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'RA[6]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 8.813ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:RA[6]">RA[6]</A>
Data Path Delay: 7.214ns (61.7% logic, 38.3% route), 3 logic levels.
Clock Path Delay: 1.599ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
1.599ns delay RCLK to SLICE_64 and
7.214ns delay SLICE_64 to RA[6] (totaling 8.813ns) meets
0.000ns hold offset RCLK to RA[6] by 8.813ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'RA[6]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.867,86.PAD,86.PADDI,RCLK:ROUTE, 0.732,86.PADDI,R2C6A.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.867 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 0.732<A href="#@net:RCLK_c:86.PADDI:R2C6A.CLK:0.732"> 86.PADDI to R2C6A.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
1.599 (54.2% logic, 45.8% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'RA[6]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.515,R2C6A.CLK,R2C6A.Q0,SLICE_64:ROUTE, 1.230,R2C6A.Q0,R2C2A.C1,nRowColSel:CTOF_DEL, 0.301,R2C2A.C1,R2C2A.F1,SLICE_98:ROUTE, 1.532,R2C2A.F1,91.PADDO,RA_c_6:DOPAD_DEL, 3.636,91.PADDO,91.PAD,RA[6]">Data path</A> SLICE_64 to RA[6]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.515 R2C6A.CLK to R2C6A.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 13 1.230<A href="#@net:nRowColSel:R2C6A.Q0:R2C2A.C1:1.230"> R2C6A.Q0 to R2C2A.C1 </A> <A href="#@net:nRowColSel">nRowColSel</A>
CTOF_DEL --- 0.301 R2C2A.C1 to R2C2A.F1 <A href="#@comp:SLICE_98">SLICE_98</A>
ROUTE 1 1.532<A href="#@net:RA_c_6:R2C2A.F1:91.PADDO:1.532"> R2C2A.F1 to 91.PADDO </A> <A href="#@net:RA_c_6">RA_c_6</A>
DOPAD_DEL --- 3.636 91.PADDO to 91.PAD <A href="#@comp:RA[6]">RA[6]</A>
--------
7.214 (61.7% logic, 38.3% route), 3 logic levels.
Report: 8.813ns is the maximum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'RA[5]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 1.141ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:RA[5]">RA[5]</A>
Data Path Delay: 8.871ns (51.5% logic, 48.5% route), 3 logic levels.
Clock Path Delay: 2.488ns (42.7% logic, 57.3% route), 1 logic levels.
Constraint Details:
2.488ns delay RCLK to SLICE_64 and
8.871ns delay SLICE_64 to RA[5] (totaling 11.359ns) meets
12.500ns offset RCLK to RA[5] by 1.141ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'RA[5]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 1.063,86.PAD,86.PADDI,RCLK:ROUTE, 1.425,86.PADDI,R2C6A.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 1.425<A href="#@net:RCLK_c:86.PADDI:R2C6A.CLK:1.425"> 86.PADDI to R2C6A.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
2.488 (42.7% logic, 57.3% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'RA[5]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.560,R2C6A.CLK,R2C6A.Q0,SLICE_64:ROUTE, 1.736,R2C6A.Q0,R8C9C.D1,nRowColSel:CTOF_DEL, 0.371,R8C9C.D1,R8C9C.F1,SLICE_95:ROUTE, 2.568,R8C9C.F1,95.PADDO,RA_c_5:DOPAD_DEL, 3.636,95.PADDO,95.PAD,RA[5]">Data path</A> SLICE_64 to RA[5]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C6A.CLK to R2C6A.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 13 1.736<A href="#@net:nRowColSel:R2C6A.Q0:R8C9C.D1:1.736"> R2C6A.Q0 to R8C9C.D1 </A> <A href="#@net:nRowColSel">nRowColSel</A>
CTOF_DEL --- 0.371 R8C9C.D1 to R8C9C.F1 <A href="#@comp:SLICE_95">SLICE_95</A>
ROUTE 1 2.568<A href="#@net:RA_c_5:R8C9C.F1:95.PADDO:2.568"> R8C9C.F1 to 95.PADDO </A> <A href="#@net:RA_c_5">RA_c_5</A>
DOPAD_DEL --- 3.636 95.PADDO to 95.PAD <A href="#@comp:RA[5]">RA[5]</A>
--------
8.871 (51.5% logic, 48.5% route), 3 logic levels.
Report: 11.359ns is the minimum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'RA[5]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 9.559ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:RA[5]">RA[5]</A>
Data Path Delay: 7.960ns (55.9% logic, 44.1% route), 3 logic levels.
Clock Path Delay: 1.599ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
1.599ns delay RCLK to SLICE_64 and
7.960ns delay SLICE_64 to RA[5] (totaling 9.559ns) meets
0.000ns hold offset RCLK to RA[5] by 9.559ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'RA[5]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.867,86.PAD,86.PADDI,RCLK:ROUTE, 0.732,86.PADDI,R2C6A.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.867 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 0.732<A href="#@net:RCLK_c:86.PADDI:R2C6A.CLK:0.732"> 86.PADDI to R2C6A.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
1.599 (54.2% logic, 45.8% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'RA[5]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.515,R2C6A.CLK,R2C6A.Q0,SLICE_64:ROUTE, 1.466,R2C6A.Q0,R8C9C.D1,nRowColSel:CTOF_DEL, 0.301,R8C9C.D1,R8C9C.F1,SLICE_95:ROUTE, 2.042,R8C9C.F1,95.PADDO,RA_c_5:DOPAD_DEL, 3.636,95.PADDO,95.PAD,RA[5]">Data path</A> SLICE_64 to RA[5]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.515 R2C6A.CLK to R2C6A.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 13 1.466<A href="#@net:nRowColSel:R2C6A.Q0:R8C9C.D1:1.466"> R2C6A.Q0 to R8C9C.D1 </A> <A href="#@net:nRowColSel">nRowColSel</A>
CTOF_DEL --- 0.301 R8C9C.D1 to R8C9C.F1 <A href="#@comp:SLICE_95">SLICE_95</A>
ROUTE 1 2.042<A href="#@net:RA_c_5:R8C9C.F1:95.PADDO:2.042"> R8C9C.F1 to 95.PADDO </A> <A href="#@net:RA_c_5">RA_c_5</A>
DOPAD_DEL --- 3.636 95.PADDO to 95.PAD <A href="#@comp:RA[5]">RA[5]</A>
--------
7.960 (55.9% logic, 44.1% route), 3 logic levels.
Report: 9.559ns is the maximum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'RA[4]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.458ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:RA[4]">RA[4]</A>
Data Path Delay: 7.554ns (60.5% logic, 39.5% route), 3 logic levels.
Clock Path Delay: 2.488ns (42.7% logic, 57.3% route), 1 logic levels.
Constraint Details:
2.488ns delay RCLK to SLICE_64 and
7.554ns delay SLICE_64 to RA[4] (totaling 10.042ns) meets
12.500ns offset RCLK to RA[4] by 2.458ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'RA[4]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 1.063,86.PAD,86.PADDI,RCLK:ROUTE, 1.425,86.PADDI,R2C6A.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 1.425<A href="#@net:RCLK_c:86.PADDI:R2C6A.CLK:1.425"> 86.PADDI to R2C6A.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
2.488 (42.7% logic, 57.3% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'RA[4]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.560,R2C6A.CLK,R2C6A.Q0,SLICE_64:ROUTE, 1.459,R2C6A.Q0,R2C2C.C1,nRowColSel:CTOF_DEL, 0.371,R2C2C.C1,R2C2C.F1,SLICE_93:ROUTE, 1.528,R2C2C.F1,99.PADDO,RA_c_4:DOPAD_DEL, 3.636,99.PADDO,99.PAD,RA[4]">Data path</A> SLICE_64 to RA[4]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C6A.CLK to R2C6A.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 13 1.459<A href="#@net:nRowColSel:R2C6A.Q0:R2C2C.C1:1.459"> R2C6A.Q0 to R2C2C.C1 </A> <A href="#@net:nRowColSel">nRowColSel</A>
CTOF_DEL --- 0.371 R2C2C.C1 to R2C2C.F1 <A href="#@comp:SLICE_93">SLICE_93</A>
ROUTE 1 1.528<A href="#@net:RA_c_4:R2C2C.F1:99.PADDO:1.528"> R2C2C.F1 to 99.PADDO </A> <A href="#@net:RA_c_4">RA_c_4</A>
DOPAD_DEL --- 3.636 99.PADDO to 99.PAD <A href="#@comp:RA[4]">RA[4]</A>
--------
7.554 (60.5% logic, 39.5% route), 3 logic levels.
Report: 10.042ns is the minimum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'RA[4]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 8.445ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:RA[4]">RA[4]</A>
Data Path Delay: 6.846ns (65.0% logic, 35.0% route), 3 logic levels.
Clock Path Delay: 1.599ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
1.599ns delay RCLK to SLICE_64 and
6.846ns delay SLICE_64 to RA[4] (totaling 8.445ns) meets
0.000ns hold offset RCLK to RA[4] by 8.445ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'RA[4]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.867,86.PAD,86.PADDI,RCLK:ROUTE, 0.732,86.PADDI,R2C6A.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.867 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 0.732<A href="#@net:RCLK_c:86.PADDI:R2C6A.CLK:0.732"> 86.PADDI to R2C6A.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
1.599 (54.2% logic, 45.8% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'RA[4]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.515,R2C6A.CLK,R2C6A.Q0,SLICE_64:ROUTE, 1.230,R2C6A.Q0,R2C2C.C1,nRowColSel:CTOF_DEL, 0.301,R2C2C.C1,R2C2C.F1,SLICE_93:ROUTE, 1.164,R2C2C.F1,99.PADDO,RA_c_4:DOPAD_DEL, 3.636,99.PADDO,99.PAD,RA[4]">Data path</A> SLICE_64 to RA[4]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.515 R2C6A.CLK to R2C6A.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 13 1.230<A href="#@net:nRowColSel:R2C6A.Q0:R2C2C.C1:1.230"> R2C6A.Q0 to R2C2C.C1 </A> <A href="#@net:nRowColSel">nRowColSel</A>
CTOF_DEL --- 0.301 R2C2C.C1 to R2C2C.F1 <A href="#@comp:SLICE_93">SLICE_93</A>
ROUTE 1 1.164<A href="#@net:RA_c_4:R2C2C.F1:99.PADDO:1.164"> R2C2C.F1 to 99.PADDO </A> <A href="#@net:RA_c_4">RA_c_4</A>
DOPAD_DEL --- 3.636 99.PADDO to 99.PAD <A href="#@comp:RA[4]">RA[4]</A>
--------
6.846 (65.0% logic, 35.0% route), 3 logic levels.
Report: 8.445ns is the maximum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'RA[3]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.216ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:RA[3]">RA[3]</A>
Data Path Delay: 7.796ns (58.6% logic, 41.4% route), 3 logic levels.
Clock Path Delay: 2.488ns (42.7% logic, 57.3% route), 1 logic levels.
Constraint Details:
2.488ns delay RCLK to SLICE_64 and
7.796ns delay SLICE_64 to RA[3] (totaling 10.284ns) meets
12.500ns offset RCLK to RA[3] by 2.216ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'RA[3]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 1.063,86.PAD,86.PADDI,RCLK:ROUTE, 1.425,86.PADDI,R2C6A.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 1.425<A href="#@net:RCLK_c:86.PADDI:R2C6A.CLK:1.425"> 86.PADDI to R2C6A.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
2.488 (42.7% logic, 57.3% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'RA[3]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.560,R2C6A.CLK,R2C6A.Q0,SLICE_64:ROUTE, 1.245,R2C6A.Q0,R2C3A.D1,nRowColSel:CTOF_DEL, 0.371,R2C3A.D1,R2C3A.F1,SLICE_92:ROUTE, 1.984,R2C3A.F1,97.PADDO,RA_c_3:DOPAD_DEL, 3.636,97.PADDO,97.PAD,RA[3]">Data path</A> SLICE_64 to RA[3]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C6A.CLK to R2C6A.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 13 1.245<A href="#@net:nRowColSel:R2C6A.Q0:R2C3A.D1:1.245"> R2C6A.Q0 to R2C3A.D1 </A> <A href="#@net:nRowColSel">nRowColSel</A>
CTOF_DEL --- 0.371 R2C3A.D1 to R2C3A.F1 <A href="#@comp:SLICE_92">SLICE_92</A>
ROUTE 1 1.984<A href="#@net:RA_c_3:R2C3A.F1:97.PADDO:1.984"> R2C3A.F1 to 97.PADDO </A> <A href="#@net:RA_c_3">RA_c_3</A>
DOPAD_DEL --- 3.636 97.PADDO to 97.PAD <A href="#@comp:RA[3]">RA[3]</A>
--------
7.796 (58.6% logic, 41.4% route), 3 logic levels.
Report: 10.284ns is the minimum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'RA[3]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 8.599ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:RA[3]">RA[3]</A>
Data Path Delay: 7.000ns (63.6% logic, 36.4% route), 3 logic levels.
Clock Path Delay: 1.599ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
1.599ns delay RCLK to SLICE_64 and
7.000ns delay SLICE_64 to RA[3] (totaling 8.599ns) meets
0.000ns hold offset RCLK to RA[3] by 8.599ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'RA[3]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.867,86.PAD,86.PADDI,RCLK:ROUTE, 0.732,86.PADDI,R2C6A.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.867 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 0.732<A href="#@net:RCLK_c:86.PADDI:R2C6A.CLK:0.732"> 86.PADDI to R2C6A.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
1.599 (54.2% logic, 45.8% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'RA[3]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.515,R2C6A.CLK,R2C6A.Q0,SLICE_64:ROUTE, 1.016,R2C6A.Q0,R2C3A.D1,nRowColSel:CTOF_DEL, 0.301,R2C3A.D1,R2C3A.F1,SLICE_92:ROUTE, 1.532,R2C3A.F1,97.PADDO,RA_c_3:DOPAD_DEL, 3.636,97.PADDO,97.PAD,RA[3]">Data path</A> SLICE_64 to RA[3]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.515 R2C6A.CLK to R2C6A.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 13 1.016<A href="#@net:nRowColSel:R2C6A.Q0:R2C3A.D1:1.016"> R2C6A.Q0 to R2C3A.D1 </A> <A href="#@net:nRowColSel">nRowColSel</A>
CTOF_DEL --- 0.301 R2C3A.D1 to R2C3A.F1 <A href="#@comp:SLICE_92">SLICE_92</A>
ROUTE 1 1.532<A href="#@net:RA_c_3:R2C3A.F1:97.PADDO:1.532"> R2C3A.F1 to 97.PADDO </A> <A href="#@net:RA_c_3">RA_c_3</A>
DOPAD_DEL --- 3.636 97.PADDO to 97.PAD <A href="#@comp:RA[3]">RA[3]</A>
--------
7.000 (63.6% logic, 36.4% route), 3 logic levels.
Report: 8.599ns is the maximum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'RA[2]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 1.999ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:RA[2]">RA[2]</A>
Data Path Delay: 8.013ns (57.0% logic, 43.0% route), 3 logic levels.
Clock Path Delay: 2.488ns (42.7% logic, 57.3% route), 1 logic levels.
Constraint Details:
2.488ns delay RCLK to SLICE_64 and
8.013ns delay SLICE_64 to RA[2] (totaling 10.501ns) meets
12.500ns offset RCLK to RA[2] by 1.999ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'RA[2]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 1.063,86.PAD,86.PADDI,RCLK:ROUTE, 1.425,86.PADDI,R2C6A.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 1.425<A href="#@net:RCLK_c:86.PADDI:R2C6A.CLK:1.425"> 86.PADDI to R2C6A.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
2.488 (42.7% logic, 57.3% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'RA[2]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.560,R2C6A.CLK,R2C6A.Q0,SLICE_64:ROUTE, 1.459,R2C6A.Q0,R2C2B.C0,nRowColSel:CTOF_DEL, 0.371,R2C2B.C0,R2C2B.F0,SLICE_90:ROUTE, 1.987,R2C2B.F0,94.PADDO,RA_c_2:DOPAD_DEL, 3.636,94.PADDO,94.PAD,RA[2]">Data path</A> SLICE_64 to RA[2]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C6A.CLK to R2C6A.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 13 1.459<A href="#@net:nRowColSel:R2C6A.Q0:R2C2B.C0:1.459"> R2C6A.Q0 to R2C2B.C0 </A> <A href="#@net:nRowColSel">nRowColSel</A>
CTOF_DEL --- 0.371 R2C2B.C0 to R2C2B.F0 <A href="#@comp:SLICE_90">SLICE_90</A>
ROUTE 1 1.987<A href="#@net:RA_c_2:R2C2B.F0:94.PADDO:1.987"> R2C2B.F0 to 94.PADDO </A> <A href="#@net:RA_c_2">RA_c_2</A>
DOPAD_DEL --- 3.636 94.PADDO to 94.PAD <A href="#@comp:RA[2]">RA[2]</A>
--------
8.013 (57.0% logic, 43.0% route), 3 logic levels.
Report: 10.501ns is the minimum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'RA[2]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 8.849ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:RA[2]">RA[2]</A>
Data Path Delay: 7.250ns (61.4% logic, 38.6% route), 3 logic levels.
Clock Path Delay: 1.599ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
1.599ns delay RCLK to SLICE_64 and
7.250ns delay SLICE_64 to RA[2] (totaling 8.849ns) meets
0.000ns hold offset RCLK to RA[2] by 8.849ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'RA[2]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.867,86.PAD,86.PADDI,RCLK:ROUTE, 0.732,86.PADDI,R2C6A.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.867 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 0.732<A href="#@net:RCLK_c:86.PADDI:R2C6A.CLK:0.732"> 86.PADDI to R2C6A.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
1.599 (54.2% logic, 45.8% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'RA[2]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.515,R2C6A.CLK,R2C6A.Q0,SLICE_64:ROUTE, 1.230,R2C6A.Q0,R2C2B.C0,nRowColSel:CTOF_DEL, 0.301,R2C2B.C0,R2C2B.F0,SLICE_90:ROUTE, 1.568,R2C2B.F0,94.PADDO,RA_c_2:DOPAD_DEL, 3.636,94.PADDO,94.PAD,RA[2]">Data path</A> SLICE_64 to RA[2]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.515 R2C6A.CLK to R2C6A.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 13 1.230<A href="#@net:nRowColSel:R2C6A.Q0:R2C2B.C0:1.230"> R2C6A.Q0 to R2C2B.C0 </A> <A href="#@net:nRowColSel">nRowColSel</A>
CTOF_DEL --- 0.301 R2C2B.C0 to R2C2B.F0 <A href="#@comp:SLICE_90">SLICE_90</A>
ROUTE 1 1.568<A href="#@net:RA_c_2:R2C2B.F0:94.PADDO:1.568"> R2C2B.F0 to 94.PADDO </A> <A href="#@net:RA_c_2">RA_c_2</A>
DOPAD_DEL --- 3.636 94.PADDO to 94.PAD <A href="#@comp:RA[2]">RA[2]</A>
--------
7.250 (61.4% logic, 38.6% route), 3 logic levels.
Report: 8.849ns is the maximum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'RA[1]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.216ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:RA[1]">RA[1]</A>
Data Path Delay: 7.796ns (58.6% logic, 41.4% route), 3 logic levels.
Clock Path Delay: 2.488ns (42.7% logic, 57.3% route), 1 logic levels.
Constraint Details:
2.488ns delay RCLK to SLICE_64 and
7.796ns delay SLICE_64 to RA[1] (totaling 10.284ns) meets
12.500ns offset RCLK to RA[1] by 2.216ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'RA[1]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 1.063,86.PAD,86.PADDI,RCLK:ROUTE, 1.425,86.PADDI,R2C6A.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 1.425<A href="#@net:RCLK_c:86.PADDI:R2C6A.CLK:1.425"> 86.PADDI to R2C6A.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
2.488 (42.7% logic, 57.3% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'RA[1]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.560,R2C6A.CLK,R2C6A.Q0,SLICE_64:ROUTE, 1.245,R2C6A.Q0,R2C3A.D0,nRowColSel:CTOF_DEL, 0.371,R2C3A.D0,R2C3A.F0,SLICE_92:ROUTE, 1.984,R2C3A.F0,89.PADDO,RA_c_1:DOPAD_DEL, 3.636,89.PADDO,89.PAD,RA[1]">Data path</A> SLICE_64 to RA[1]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C6A.CLK to R2C6A.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 13 1.245<A href="#@net:nRowColSel:R2C6A.Q0:R2C3A.D0:1.245"> R2C6A.Q0 to R2C3A.D0 </A> <A href="#@net:nRowColSel">nRowColSel</A>
CTOF_DEL --- 0.371 R2C3A.D0 to R2C3A.F0 <A href="#@comp:SLICE_92">SLICE_92</A>
ROUTE 1 1.984<A href="#@net:RA_c_1:R2C3A.F0:89.PADDO:1.984"> R2C3A.F0 to 89.PADDO </A> <A href="#@net:RA_c_1">RA_c_1</A>
DOPAD_DEL --- 3.636 89.PADDO to 89.PAD <A href="#@comp:RA[1]">RA[1]</A>
--------
7.796 (58.6% logic, 41.4% route), 3 logic levels.
Report: 10.284ns is the minimum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'RA[1]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 8.599ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:RA[1]">RA[1]</A>
Data Path Delay: 7.000ns (63.6% logic, 36.4% route), 3 logic levels.
Clock Path Delay: 1.599ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
1.599ns delay RCLK to SLICE_64 and
7.000ns delay SLICE_64 to RA[1] (totaling 8.599ns) meets
0.000ns hold offset RCLK to RA[1] by 8.599ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'RA[1]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.867,86.PAD,86.PADDI,RCLK:ROUTE, 0.732,86.PADDI,R2C6A.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.867 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 0.732<A href="#@net:RCLK_c:86.PADDI:R2C6A.CLK:0.732"> 86.PADDI to R2C6A.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
1.599 (54.2% logic, 45.8% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'RA[1]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.515,R2C6A.CLK,R2C6A.Q0,SLICE_64:ROUTE, 1.016,R2C6A.Q0,R2C3A.D0,nRowColSel:CTOF_DEL, 0.301,R2C3A.D0,R2C3A.F0,SLICE_92:ROUTE, 1.532,R2C3A.F0,89.PADDO,RA_c_1:DOPAD_DEL, 3.636,89.PADDO,89.PAD,RA[1]">Data path</A> SLICE_64 to RA[1]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.515 R2C6A.CLK to R2C6A.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 13 1.016<A href="#@net:nRowColSel:R2C6A.Q0:R2C3A.D0:1.016"> R2C6A.Q0 to R2C3A.D0 </A> <A href="#@net:nRowColSel">nRowColSel</A>
CTOF_DEL --- 0.301 R2C3A.D0 to R2C3A.F0 <A href="#@comp:SLICE_92">SLICE_92</A>
ROUTE 1 1.532<A href="#@net:RA_c_1:R2C3A.F0:89.PADDO:1.532"> R2C3A.F0 to 89.PADDO </A> <A href="#@net:RA_c_1">RA_c_1</A>
DOPAD_DEL --- 3.636 89.PADDO to 89.PAD <A href="#@comp:RA[1]">RA[1]</A>
--------
7.000 (63.6% logic, 36.4% route), 3 logic levels.
Report: 8.599ns is the maximum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'RA[0]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.454ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:RA[0]">RA[0]</A>
Data Path Delay: 7.558ns (60.4% logic, 39.6% route), 3 logic levels.
Clock Path Delay: 2.488ns (42.7% logic, 57.3% route), 1 logic levels.
Constraint Details:
2.488ns delay RCLK to SLICE_64 and
7.558ns delay SLICE_64 to RA[0] (totaling 10.046ns) meets
12.500ns offset RCLK to RA[0] by 2.454ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'RA[0]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 1.063,86.PAD,86.PADDI,RCLK:ROUTE, 1.425,86.PADDI,R2C6A.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 1.425<A href="#@net:RCLK_c:86.PADDI:R2C6A.CLK:1.425"> 86.PADDI to R2C6A.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
2.488 (42.7% logic, 57.3% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'RA[0]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.560,R2C6A.CLK,R2C6A.Q0,SLICE_64:ROUTE, 1.459,R2C6A.Q0,R2C2C.C0,nRowColSel:CTOF_DEL, 0.371,R2C2C.C0,R2C2C.F0,SLICE_93:ROUTE, 1.532,R2C2C.F0,98.PADDO,RA_c_0:DOPAD_DEL, 3.636,98.PADDO,98.PAD,RA[0]">Data path</A> SLICE_64 to RA[0]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C6A.CLK to R2C6A.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 13 1.459<A href="#@net:nRowColSel:R2C6A.Q0:R2C2C.C0:1.459"> R2C6A.Q0 to R2C2C.C0 </A> <A href="#@net:nRowColSel">nRowColSel</A>
CTOF_DEL --- 0.371 R2C2C.C0 to R2C2C.F0 <A href="#@comp:SLICE_93">SLICE_93</A>
ROUTE 1 1.532<A href="#@net:RA_c_0:R2C2C.F0:98.PADDO:1.532"> R2C2C.F0 to 98.PADDO </A> <A href="#@net:RA_c_0">RA_c_0</A>
DOPAD_DEL --- 3.636 98.PADDO to 98.PAD <A href="#@comp:RA[0]">RA[0]</A>
--------
7.558 (60.4% logic, 39.6% route), 3 logic levels.
Report: 10.046ns is the minimum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'RA[0]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 8.442ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:RA[0]">RA[0]</A>
Data Path Delay: 6.843ns (65.1% logic, 34.9% route), 3 logic levels.
Clock Path Delay: 1.599ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
1.599ns delay RCLK to SLICE_64 and
6.843ns delay SLICE_64 to RA[0] (totaling 8.442ns) meets
0.000ns hold offset RCLK to RA[0] by 8.442ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'RA[0]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.867,86.PAD,86.PADDI,RCLK:ROUTE, 0.732,86.PADDI,R2C6A.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.867 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 0.732<A href="#@net:RCLK_c:86.PADDI:R2C6A.CLK:0.732"> 86.PADDI to R2C6A.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
1.599 (54.2% logic, 45.8% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'RA[0]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.515,R2C6A.CLK,R2C6A.Q0,SLICE_64:ROUTE, 1.230,R2C6A.Q0,R2C2C.C0,nRowColSel:CTOF_DEL, 0.301,R2C2C.C0,R2C2C.F0,SLICE_93:ROUTE, 1.161,R2C2C.F0,98.PADDO,RA_c_0:DOPAD_DEL, 3.636,98.PADDO,98.PAD,RA[0]">Data path</A> SLICE_64 to RA[0]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.515 R2C6A.CLK to R2C6A.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 13 1.230<A href="#@net:nRowColSel:R2C6A.Q0:R2C2C.C0:1.230"> R2C6A.Q0 to R2C2C.C0 </A> <A href="#@net:nRowColSel">nRowColSel</A>
CTOF_DEL --- 0.301 R2C2C.C0 to R2C2C.F0 <A href="#@comp:SLICE_93">SLICE_93</A>
ROUTE 1 1.161<A href="#@net:RA_c_0:R2C2C.F0:98.PADDO:1.161"> R2C2C.F0 to 98.PADDO </A> <A href="#@net:RA_c_0">RA_c_0</A>
DOPAD_DEL --- 3.636 98.PADDO to 98.PAD <A href="#@comp:RA[0]">RA[0]</A>
--------
6.843 (65.1% logic, 34.9% route), 3 logic levels.
Report: 8.442ns is the maximum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'nRCS' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 4.999ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_60">nRCS_364</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:nRCS">nRCS</A>
Data Path Delay: 5.013ns (83.7% logic, 16.3% route), 2 logic levels.
Clock Path Delay: 2.488ns (42.7% logic, 57.3% route), 1 logic levels.
Constraint Details:
2.488ns delay RCLK to SLICE_60 and
5.013ns delay SLICE_60 to nRCS (totaling 7.501ns) meets
12.500ns offset RCLK to nRCS by 4.999ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'nRCS' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 1.063,86.PAD,86.PADDI,RCLK:ROUTE, 1.425,86.PADDI,R2C9C.CLK,RCLK_c">Clock path</A> RCLK to SLICE_60:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 1.425<A href="#@net:RCLK_c:86.PADDI:R2C9C.CLK:1.425"> 86.PADDI to R2C9C.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
2.488 (42.7% logic, 57.3% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'nRCS' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.560,R2C9C.CLK,R2C9C.Q0,SLICE_60:ROUTE, 0.817,R2C9C.Q0,77.PADDO,nRCS_c:DOPAD_DEL, 3.636,77.PADDO,77.PAD,nRCS">Data path</A> SLICE_60 to nRCS:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C9C.CLK to R2C9C.Q0 <A href="#@comp:SLICE_60">SLICE_60</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 1 0.817<A href="#@net:nRCS_c:R2C9C.Q0:77.PADDO:0.817"> R2C9C.Q0 to 77.PADDO </A> <A href="#@net:nRCS_c">nRCS_c</A>
DOPAD_DEL --- 3.636 77.PADDO to 77.PAD <A href="#@comp:nRCS">nRCS</A>
--------
5.013 (83.7% logic, 16.3% route), 2 logic levels.
Report: 7.501ns is the minimum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'nRCS' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 6.396ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_60">nRCS_364</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:nRCS">nRCS</A>
Data Path Delay: 4.797ns (86.5% logic, 13.5% route), 2 logic levels.
Clock Path Delay: 1.599ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
1.599ns delay RCLK to SLICE_60 and
4.797ns delay SLICE_60 to nRCS (totaling 6.396ns) meets
0.000ns hold offset RCLK to nRCS by 6.396ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'nRCS' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.867,86.PAD,86.PADDI,RCLK:ROUTE, 0.732,86.PADDI,R2C9C.CLK,RCLK_c">Clock path</A> RCLK to SLICE_60:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.867 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 0.732<A href="#@net:RCLK_c:86.PADDI:R2C9C.CLK:0.732"> 86.PADDI to R2C9C.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
1.599 (54.2% logic, 45.8% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'nRCS' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.515,R2C9C.CLK,R2C9C.Q0,SLICE_60:ROUTE, 0.646,R2C9C.Q0,77.PADDO,nRCS_c:DOPAD_DEL, 3.636,77.PADDO,77.PAD,nRCS">Data path</A> SLICE_60 to nRCS:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.515 R2C9C.CLK to R2C9C.Q0 <A href="#@comp:SLICE_60">SLICE_60</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 1 0.646<A href="#@net:nRCS_c:R2C9C.Q0:77.PADDO:0.646"> R2C9C.Q0 to 77.PADDO </A> <A href="#@net:nRCS_c">nRCS_c</A>
DOPAD_DEL --- 3.636 77.PADDO to 77.PAD <A href="#@comp:nRCS">nRCS</A>
--------
4.797 (86.5% logic, 13.5% route), 2 logic levels.
Report: 6.396ns is the maximum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'RCKE' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 4.999ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_34">RCKE_363</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:RCKE">RCKE</A>
Data Path Delay: 5.013ns (83.7% logic, 16.3% route), 2 logic levels.
Clock Path Delay: 2.488ns (42.7% logic, 57.3% route), 1 logic levels.
Constraint Details:
2.488ns delay RCLK to SLICE_34 and
5.013ns delay SLICE_34 to RCKE (totaling 7.501ns) meets
12.500ns offset RCLK to RCKE by 4.999ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'RCKE' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 1.063,86.PAD,86.PADDI,RCLK:ROUTE, 1.425,86.PADDI,R2C7C.CLK,RCLK_c">Clock path</A> RCLK to SLICE_34:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 1.425<A href="#@net:RCLK_c:86.PADDI:R2C7C.CLK:1.425"> 86.PADDI to R2C7C.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
2.488 (42.7% logic, 57.3% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'RCKE' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.560,R2C7C.CLK,R2C7C.Q0,SLICE_34:ROUTE, 0.817,R2C7C.Q0,82.PADDO,RCKE_c:DOPAD_DEL, 3.636,82.PADDO,82.PAD,RCKE">Data path</A> SLICE_34 to RCKE:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C7C.CLK to R2C7C.Q0 <A href="#@comp:SLICE_34">SLICE_34</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 4 0.817<A href="#@net:RCKE_c:R2C7C.Q0:82.PADDO:0.817"> R2C7C.Q0 to 82.PADDO </A> <A href="#@net:RCKE_c">RCKE_c</A>
DOPAD_DEL --- 3.636 82.PADDO to 82.PAD <A href="#@comp:RCKE">RCKE</A>
--------
5.013 (83.7% logic, 16.3% route), 2 logic levels.
Report: 7.501ns is the minimum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'RCKE' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 6.396ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_34">RCKE_363</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:RCKE">RCKE</A>
Data Path Delay: 4.797ns (86.5% logic, 13.5% route), 2 logic levels.
Clock Path Delay: 1.599ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
1.599ns delay RCLK to SLICE_34 and
4.797ns delay SLICE_34 to RCKE (totaling 6.396ns) meets
0.000ns hold offset RCLK to RCKE by 6.396ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'RCKE' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.867,86.PAD,86.PADDI,RCLK:ROUTE, 0.732,86.PADDI,R2C7C.CLK,RCLK_c">Clock path</A> RCLK to SLICE_34:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.867 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 0.732<A href="#@net:RCLK_c:86.PADDI:R2C7C.CLK:0.732"> 86.PADDI to R2C7C.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
1.599 (54.2% logic, 45.8% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'RCKE' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.515,R2C7C.CLK,R2C7C.Q0,SLICE_34:ROUTE, 0.646,R2C7C.Q0,82.PADDO,RCKE_c:DOPAD_DEL, 3.636,82.PADDO,82.PAD,RCKE">Data path</A> SLICE_34 to RCKE:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.515 R2C7C.CLK to R2C7C.Q0 <A href="#@comp:SLICE_34">SLICE_34</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 4 0.646<A href="#@net:RCKE_c:R2C7C.Q0:82.PADDO:0.646"> R2C7C.Q0 to 82.PADDO </A> <A href="#@net:RCKE_c">RCKE_c</A>
DOPAD_DEL --- 3.636 82.PADDO to 82.PAD <A href="#@comp:RCKE">RCKE</A>
--------
4.797 (86.5% logic, 13.5% route), 2 logic levels.
Report: 6.396ns is the maximum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'nRWE' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.833ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_63">nRWE_367</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:nRWE">nRWE</A>
Data Path Delay: 6.179ns (67.9% logic, 32.1% route), 2 logic levels.
Clock Path Delay: 2.488ns (42.7% logic, 57.3% route), 1 logic levels.
Constraint Details:
2.488ns delay RCLK to SLICE_63 and
6.179ns delay SLICE_63 to nRWE (totaling 8.667ns) meets
12.500ns offset RCLK to nRWE by 3.833ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'nRWE' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 1.063,86.PAD,86.PADDI,RCLK:ROUTE, 1.425,86.PADDI,R2C7A.CLK,RCLK_c">Clock path</A> RCLK to SLICE_63:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 1.425<A href="#@net:RCLK_c:86.PADDI:R2C7A.CLK:1.425"> 86.PADDI to R2C7A.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
2.488 (42.7% logic, 57.3% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'nRWE' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.560,R2C7A.CLK,R2C7A.Q0,SLICE_63:ROUTE, 1.983,R2C7A.Q0,72.PADDO,nRWE_c:DOPAD_DEL, 3.636,72.PADDO,72.PAD,nRWE">Data path</A> SLICE_63 to nRWE:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C7A.CLK to R2C7A.Q0 <A href="#@comp:SLICE_63">SLICE_63</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 1 1.983<A href="#@net:nRWE_c:R2C7A.Q0:72.PADDO:1.983"> R2C7A.Q0 to 72.PADDO </A> <A href="#@net:nRWE_c">nRWE_c</A>
DOPAD_DEL --- 3.636 72.PADDO to 72.PAD <A href="#@comp:nRWE">nRWE</A>
--------
6.179 (67.9% logic, 32.1% route), 2 logic levels.
Report: 8.667ns is the minimum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'nRWE' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 7.321ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_63">nRWE_367</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:nRWE">nRWE</A>
Data Path Delay: 5.722ns (72.5% logic, 27.5% route), 2 logic levels.
Clock Path Delay: 1.599ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
1.599ns delay RCLK to SLICE_63 and
5.722ns delay SLICE_63 to nRWE (totaling 7.321ns) meets
0.000ns hold offset RCLK to nRWE by 7.321ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'nRWE' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.867,86.PAD,86.PADDI,RCLK:ROUTE, 0.732,86.PADDI,R2C7A.CLK,RCLK_c">Clock path</A> RCLK to SLICE_63:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.867 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 0.732<A href="#@net:RCLK_c:86.PADDI:R2C7A.CLK:0.732"> 86.PADDI to R2C7A.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
1.599 (54.2% logic, 45.8% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'nRWE' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.515,R2C7A.CLK,R2C7A.Q0,SLICE_63:ROUTE, 1.571,R2C7A.Q0,72.PADDO,nRWE_c:DOPAD_DEL, 3.636,72.PADDO,72.PAD,nRWE">Data path</A> SLICE_63 to nRWE:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.515 R2C7A.CLK to R2C7A.Q0 <A href="#@comp:SLICE_63">SLICE_63</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 1 1.571<A href="#@net:nRWE_c:R2C7A.Q0:72.PADDO:1.571"> R2C7A.Q0 to 72.PADDO </A> <A href="#@net:nRWE_c">nRWE_c</A>
DOPAD_DEL --- 3.636 72.PADDO to 72.PAD <A href="#@comp:nRWE">nRWE</A>
--------
5.722 (72.5% logic, 27.5% route), 2 logic levels.
Report: 7.321ns is the maximum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'nRRAS' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.813ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_61">nRRAS_365</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:nRRAS">nRRAS</A>
Data Path Delay: 6.199ns (67.7% logic, 32.3% route), 2 logic levels.
Clock Path Delay: 2.488ns (42.7% logic, 57.3% route), 1 logic levels.
Constraint Details:
2.488ns delay RCLK to SLICE_61 and
6.199ns delay SLICE_61 to nRRAS (totaling 8.687ns) meets
12.500ns offset RCLK to nRRAS by 3.813ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'nRRAS' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 1.063,86.PAD,86.PADDI,RCLK:ROUTE, 1.425,86.PADDI,R4C9B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_61:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 1.425<A href="#@net:RCLK_c:86.PADDI:R4C9B.CLK:1.425"> 86.PADDI to R4C9B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
2.488 (42.7% logic, 57.3% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'nRRAS' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.560,R4C9B.CLK,R4C9B.Q0,SLICE_61:ROUTE, 2.003,R4C9B.Q0,73.PADDO,nRRAS_c:DOPAD_DEL, 3.636,73.PADDO,73.PAD,nRRAS">Data path</A> SLICE_61 to nRRAS:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R4C9B.CLK to R4C9B.Q0 <A href="#@comp:SLICE_61">SLICE_61</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 2 2.003<A href="#@net:nRRAS_c:R4C9B.Q0:73.PADDO:2.003"> R4C9B.Q0 to 73.PADDO </A> <A href="#@net:nRRAS_c">nRRAS_c</A>
DOPAD_DEL --- 3.636 73.PADDO to 73.PAD <A href="#@comp:nRRAS">nRRAS</A>
--------
6.199 (67.7% logic, 32.3% route), 2 logic levels.
Report: 8.687ns is the minimum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'nRRAS' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 7.334ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_61">nRRAS_365</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:nRRAS">nRRAS</A>
Data Path Delay: 5.735ns (72.4% logic, 27.6% route), 2 logic levels.
Clock Path Delay: 1.599ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
1.599ns delay RCLK to SLICE_61 and
5.735ns delay SLICE_61 to nRRAS (totaling 7.334ns) meets
0.000ns hold offset RCLK to nRRAS by 7.334ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'nRRAS' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.867,86.PAD,86.PADDI,RCLK:ROUTE, 0.732,86.PADDI,R4C9B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_61:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.867 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 0.732<A href="#@net:RCLK_c:86.PADDI:R4C9B.CLK:0.732"> 86.PADDI to R4C9B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
1.599 (54.2% logic, 45.8% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'nRRAS' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.515,R4C9B.CLK,R4C9B.Q0,SLICE_61:ROUTE, 1.584,R4C9B.Q0,73.PADDO,nRRAS_c:DOPAD_DEL, 3.636,73.PADDO,73.PAD,nRRAS">Data path</A> SLICE_61 to nRRAS:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.515 R4C9B.CLK to R4C9B.Q0 <A href="#@comp:SLICE_61">SLICE_61</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 2 1.584<A href="#@net:nRRAS_c:R4C9B.Q0:73.PADDO:1.584"> R4C9B.Q0 to 73.PADDO </A> <A href="#@net:nRRAS_c">nRRAS_c</A>
DOPAD_DEL --- 3.636 73.PADDO to 73.PAD <A href="#@comp:nRRAS">nRRAS</A>
--------
5.735 (72.4% logic, 27.6% route), 2 logic levels.
Report: 7.334ns is the maximum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'nRCAS' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 4.999ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_58">nRCAS_366</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:nRCAS">nRCAS</A>
Data Path Delay: 5.013ns (83.7% logic, 16.3% route), 2 logic levels.
Clock Path Delay: 2.488ns (42.7% logic, 57.3% route), 1 logic levels.
Constraint Details:
2.488ns delay RCLK to SLICE_58 and
5.013ns delay SLICE_58 to nRCAS (totaling 7.501ns) meets
12.500ns offset RCLK to nRCAS by 4.999ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'nRCAS' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 1.063,86.PAD,86.PADDI,RCLK:ROUTE, 1.425,86.PADDI,R2C9B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_58:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 1.425<A href="#@net:RCLK_c:86.PADDI:R2C9B.CLK:1.425"> 86.PADDI to R2C9B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
2.488 (42.7% logic, 57.3% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'nRCAS' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.560,R2C9B.CLK,R2C9B.Q0,SLICE_58:ROUTE, 0.817,R2C9B.Q0,78.PADDO,nRCAS_c:DOPAD_DEL, 3.636,78.PADDO,78.PAD,nRCAS">Data path</A> SLICE_58 to nRCAS:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C9B.CLK to R2C9B.Q0 <A href="#@comp:SLICE_58">SLICE_58</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 1 0.817<A href="#@net:nRCAS_c:R2C9B.Q0:78.PADDO:0.817"> R2C9B.Q0 to 78.PADDO </A> <A href="#@net:nRCAS_c">nRCAS_c</A>
DOPAD_DEL --- 3.636 78.PADDO to 78.PAD <A href="#@comp:nRCAS">nRCAS</A>
--------
5.013 (83.7% logic, 16.3% route), 2 logic levels.
Report: 7.501ns is the minimum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'nRCAS' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 6.396ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_58">nRCAS_366</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:nRCAS">nRCAS</A>
Data Path Delay: 4.797ns (86.5% logic, 13.5% route), 2 logic levels.
Clock Path Delay: 1.599ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
1.599ns delay RCLK to SLICE_58 and
4.797ns delay SLICE_58 to nRCAS (totaling 6.396ns) meets
0.000ns hold offset RCLK to nRCAS by 6.396ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'nRCAS' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.867,86.PAD,86.PADDI,RCLK:ROUTE, 0.732,86.PADDI,R2C9B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_58:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.867 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 0.732<A href="#@net:RCLK_c:86.PADDI:R2C9B.CLK:0.732"> 86.PADDI to R2C9B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
1.599 (54.2% logic, 45.8% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'nRCAS' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.515,R2C9B.CLK,R2C9B.Q0,SLICE_58:ROUTE, 0.646,R2C9B.Q0,78.PADDO,nRCAS_c:DOPAD_DEL, 3.636,78.PADDO,78.PAD,nRCAS">Data path</A> SLICE_58 to nRCAS:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.515 R2C9B.CLK to R2C9B.Q0 <A href="#@comp:SLICE_58">SLICE_58</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 1 0.646<A href="#@net:nRCAS_c:R2C9B.Q0:78.PADDO:0.646"> R2C9B.Q0 to 78.PADDO </A> <A href="#@net:nRCAS_c">nRCAS_c</A>
DOPAD_DEL --- 3.636 78.PADDO to 78.PAD <A href="#@comp:nRCAS">nRCAS</A>
--------
4.797 (86.5% logic, 13.5% route), 2 logic levels.
Report: 6.396ns is the maximum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'RDQMH' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 1.989ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:RDQMH">RDQMH</A>
Data Path Delay: 8.023ns (56.9% logic, 43.1% route), 3 logic levels.
Clock Path Delay: 2.488ns (42.7% logic, 57.3% route), 1 logic levels.
Constraint Details:
2.488ns delay RCLK to SLICE_64 and
8.023ns delay SLICE_64 to RDQMH (totaling 10.511ns) meets
12.500ns offset RCLK to RDQMH by 1.989ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'RDQMH' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 1.063,86.PAD,86.PADDI,RCLK:ROUTE, 1.425,86.PADDI,R2C6A.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 1.425<A href="#@net:RCLK_c:86.PADDI:R2C6A.CLK:1.425"> 86.PADDI to R2C6A.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
2.488 (42.7% logic, 57.3% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'RDQMH' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.560,R2C6A.CLK,R2C6A.Q0,SLICE_64:ROUTE, 1.796,R2C6A.Q0,R6C9A.D0,nRowColSel:CTOF_DEL, 0.371,R6C9A.D0,R6C9A.F0,SLICE_87:ROUTE, 1.660,R6C9A.F0,76.PADDO,RDQMH_c:DOPAD_DEL, 3.636,76.PADDO,76.PAD,RDQMH">Data path</A> SLICE_64 to RDQMH:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C6A.CLK to R2C6A.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 13 1.796<A href="#@net:nRowColSel:R2C6A.Q0:R6C9A.D0:1.796"> R2C6A.Q0 to R6C9A.D0 </A> <A href="#@net:nRowColSel">nRowColSel</A>
CTOF_DEL --- 0.371 R6C9A.D0 to R6C9A.F0 <A href="#@comp:SLICE_87">SLICE_87</A>
ROUTE 1 1.660<A href="#@net:RDQMH_c:R6C9A.F0:76.PADDO:1.660"> R6C9A.F0 to 76.PADDO </A> <A href="#@net:RDQMH_c">RDQMH_c</A>
DOPAD_DEL --- 3.636 76.PADDO to 76.PAD <A href="#@comp:RDQMH">RDQMH</A>
--------
8.023 (56.9% logic, 43.1% route), 3 logic levels.
Report: 10.511ns is the minimum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'RDQMH' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 8.888ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:RDQMH">RDQMH</A>
Data Path Delay: 7.289ns (61.1% logic, 38.9% route), 3 logic levels.
Clock Path Delay: 1.599ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
1.599ns delay RCLK to SLICE_64 and
7.289ns delay SLICE_64 to RDQMH (totaling 8.888ns) meets
0.000ns hold offset RCLK to RDQMH by 8.888ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'RDQMH' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.867,86.PAD,86.PADDI,RCLK:ROUTE, 0.732,86.PADDI,R2C6A.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.867 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 0.732<A href="#@net:RCLK_c:86.PADDI:R2C6A.CLK:0.732"> 86.PADDI to R2C6A.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
1.599 (54.2% logic, 45.8% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'RDQMH' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.515,R2C6A.CLK,R2C6A.Q0,SLICE_64:ROUTE, 1.549,R2C6A.Q0,R6C9A.D0,nRowColSel:CTOF_DEL, 0.301,R6C9A.D0,R6C9A.F0,SLICE_87:ROUTE, 1.288,R6C9A.F0,76.PADDO,RDQMH_c:DOPAD_DEL, 3.636,76.PADDO,76.PAD,RDQMH">Data path</A> SLICE_64 to RDQMH:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.515 R2C6A.CLK to R2C6A.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 13 1.549<A href="#@net:nRowColSel:R2C6A.Q0:R6C9A.D0:1.549"> R2C6A.Q0 to R6C9A.D0 </A> <A href="#@net:nRowColSel">nRowColSel</A>
CTOF_DEL --- 0.301 R6C9A.D0 to R6C9A.F0 <A href="#@comp:SLICE_87">SLICE_87</A>
ROUTE 1 1.288<A href="#@net:RDQMH_c:R6C9A.F0:76.PADDO:1.288"> R6C9A.F0 to 76.PADDO </A> <A href="#@net:RDQMH_c">RDQMH_c</A>
DOPAD_DEL --- 3.636 76.PADDO to 76.PAD <A href="#@comp:RDQMH">RDQMH</A>
--------
7.289 (61.1% logic, 38.9% route), 3 logic levels.
Report: 8.888ns is the maximum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'RDQML' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.892ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:RDQML">RDQML</A>
Data Path Delay: 7.120ns (64.1% logic, 35.9% route), 3 logic levels.
Clock Path Delay: 2.488ns (42.7% logic, 57.3% route), 1 logic levels.
Constraint Details:
2.488ns delay RCLK to SLICE_64 and
7.120ns delay SLICE_64 to RDQML (totaling 9.608ns) meets
12.500ns offset RCLK to RDQML by 2.892ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'RDQML' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 1.063,86.PAD,86.PADDI,RCLK:ROUTE, 1.425,86.PADDI,R2C6A.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 1.063 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 1.425<A href="#@net:RCLK_c:86.PADDI:R2C6A.CLK:1.425"> 86.PADDI to R2C6A.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
2.488 (42.7% logic, 57.3% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'RDQML' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.560,R2C6A.CLK,R2C6A.Q0,SLICE_64:ROUTE, 1.736,R2C6A.Q0,R8C9C.D0,nRowColSel:CTOF_DEL, 0.371,R8C9C.D0,R8C9C.F0,SLICE_95:ROUTE, 0.817,R8C9C.F0,61.PADDO,RDQML_c:DOPAD_DEL, 3.636,61.PADDO,61.PAD,RDQML">Data path</A> SLICE_64 to RDQML:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.560 R2C6A.CLK to R2C6A.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 13 1.736<A href="#@net:nRowColSel:R2C6A.Q0:R8C9C.D0:1.736"> R2C6A.Q0 to R8C9C.D0 </A> <A href="#@net:nRowColSel">nRowColSel</A>
CTOF_DEL --- 0.371 R8C9C.D0 to R8C9C.F0 <A href="#@comp:SLICE_95">SLICE_95</A>
ROUTE 1 0.817<A href="#@net:RDQML_c:R8C9C.F0:61.PADDO:0.817"> R8C9C.F0 to 61.PADDO </A> <A href="#@net:RDQML_c">RDQML_c</A>
DOPAD_DEL --- 3.636 61.PADDO to 61.PAD <A href="#@comp:RDQML">RDQML</A>
--------
7.120 (64.1% logic, 35.9% route), 3 logic levels.
Report: 9.608ns is the minimum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'RDQML' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 8.163ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:RDQML">RDQML</A>
Data Path Delay: 6.564ns (67.8% logic, 32.2% route), 3 logic levels.
Clock Path Delay: 1.599ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
1.599ns delay RCLK to SLICE_64 and
6.564ns delay SLICE_64 to RDQML (totaling 8.163ns) meets
0.000ns hold offset RCLK to RDQML by 8.163ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'RDQML' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.867,86.PAD,86.PADDI,RCLK:ROUTE, 0.732,86.PADDI,R2C6A.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.867 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 0.732<A href="#@net:RCLK_c:86.PADDI:R2C6A.CLK:0.732"> 86.PADDI to R2C6A.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
1.599 (54.2% logic, 45.8% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'RDQML' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.515,R2C6A.CLK,R2C6A.Q0,SLICE_64:ROUTE, 1.466,R2C6A.Q0,R8C9C.D0,nRowColSel:CTOF_DEL, 0.301,R8C9C.D0,R8C9C.F0,SLICE_95:ROUTE, 0.646,R8C9C.F0,61.PADDO,RDQML_c:DOPAD_DEL, 3.636,61.PADDO,61.PAD,RDQML">Data path</A> SLICE_64 to RDQML:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.515 R2C6A.CLK to R2C6A.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 13 1.466<A href="#@net:nRowColSel:R2C6A.Q0:R8C9C.D0:1.466"> R2C6A.Q0 to R8C9C.D0 </A> <A href="#@net:nRowColSel">nRowColSel</A>
CTOF_DEL --- 0.301 R8C9C.D0 to R8C9C.F0 <A href="#@comp:SLICE_95">SLICE_95</A>
ROUTE 1 0.646<A href="#@net:RDQML_c:R8C9C.F0:61.PADDO:0.646"> R8C9C.F0 to 61.PADDO </A> <A href="#@net:RDQML_c">RDQML_c</A>
DOPAD_DEL --- 3.636 61.PADDO to 61.PAD <A href="#@comp:RDQML">RDQML</A>
--------
6.564 (67.8% logic, 32.2% route), 3 logic levels.
Report: 8.163ns is the maximum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'RD[7]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'RD[7]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'RD[6]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'RD[6]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'RD[5]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'RD[5]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'RD[4]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'RD[4]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'RD[3]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'RD[3]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'RD[2]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'RD[2]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'RD[1]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; Setup Analysis.
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'RD[1]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ; Hold Analysis.
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
<A name="Report Summary"></A><B><U><big>Report Summary</big></U></B>
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
PERIOD NET "PHI2_c" 350.000000 ns ; | 350.000 ns| 22.150 ns| 7
| | |
PERIOD NET "nCCAS_c" 350.000000 ns ; | 350.000 ns| 2.000 ns| 0
| | |
PERIOD NET "nCRAS_c" 350.000000 ns ; | 350.000 ns| 2.000 ns| 0
| | |
PERIOD NET "RCLK_c" 16.000000 ns ; | 16.000 ns| 8.659 ns| 6
| | |
CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns | | |
CLKPORT "RCLK" ; Setup Analysis. | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns | | |
CLKPORT "RCLK" ; Hold Analysis. | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[0]" 12.500000 | | |
ns CLKPORT "RCLK" ; Setup Analysis. | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[0]" 12.500000 | | |
ns CLKPORT "RCLK" ; Hold Analysis. | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[7]" 12.500000 | | |
ns CLKPORT "RCLK" ; Setup Analysis. | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[7]" 12.500000 | | |
ns CLKPORT "RCLK" ; Hold Analysis. | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[6]" 12.500000 | | |
ns CLKPORT "RCLK" ; Setup Analysis. | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[6]" 12.500000 | | |
ns CLKPORT "RCLK" ; Hold Analysis. | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[5]" 12.500000 | | |
ns CLKPORT "RCLK" ; Setup Analysis. | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[5]" 12.500000 | | |
ns CLKPORT "RCLK" ; Hold Analysis. | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[4]" 12.500000 | | |
ns CLKPORT "RCLK" ; Setup Analysis. | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[4]" 12.500000 | | |
ns CLKPORT "RCLK" ; Hold Analysis. | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[3]" 12.500000 | | |
ns CLKPORT "RCLK" ; Setup Analysis. | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[3]" 12.500000 | | |
ns CLKPORT "RCLK" ; Hold Analysis. | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[2]" 12.500000 | | |
ns CLKPORT "RCLK" ; Setup Analysis. | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[2]" 12.500000 | | |
ns CLKPORT "RCLK" ; Hold Analysis. | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[1]" 12.500000 | | |
ns CLKPORT "RCLK" ; Setup Analysis. | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[1]" 12.500000 | | |
ns CLKPORT "RCLK" ; Hold Analysis. | -| -| 0
| | |
CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns | | |
CLKPORT "RCLK" ; Setup Analysis. | -| -| 0
| | |
CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns | | |
CLKPORT "RCLK" ; Hold Analysis. | -| -| 0
| | |
CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns | | |
CLKPORT "RCLK" ; Setup Analysis. | -| -| 0
| | |
CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns | | |
CLKPORT "RCLK" ; Hold Analysis. | -| -| 0
| | |
CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns | | |
CLKPORT "RCLK" ; Setup Analysis. | -| -| 0
| | |
CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns | | |
CLKPORT "RCLK" ; Hold Analysis. | -| -| 0
| | |
CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns | | |
CLKPORT "RCLK" ; Setup Analysis. | 12.500 ns| 7.501 ns| 2
| | |
CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns | | |
CLKPORT "RCLK" ; Hold Analysis. | 0.000 ns| 6.396 ns| 2
| | |
CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns | | |
CLKPORT "RCLK" ; Setup Analysis. | 12.500 ns| 11.023 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns | | |
CLKPORT "RCLK" ; Hold Analysis. | 0.000 ns| 9.323 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns | | |
CLKPORT "RCLK" ; Setup Analysis. | 12.500 ns| 10.040 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns | | |
CLKPORT "RCLK" ; Hold Analysis. | 0.000 ns| 8.446 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns | | |
CLKPORT "RCLK" ; Setup Analysis. | 12.500 ns| 10.394 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns | | |
CLKPORT "RCLK" ; Hold Analysis. | 0.000 ns| 8.766 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns | | |
CLKPORT "RCLK" ; Setup Analysis. | 12.500 ns| 10.498 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns | | |
CLKPORT "RCLK" ; Hold Analysis. | 0.000 ns| 8.813 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns | | |
CLKPORT "RCLK" ; Setup Analysis. | 12.500 ns| 11.359 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns | | |
CLKPORT "RCLK" ; Hold Analysis. | 0.000 ns| 9.559 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns | | |
CLKPORT "RCLK" ; Setup Analysis. | 12.500 ns| 10.042 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns | | |
CLKPORT "RCLK" ; Hold Analysis. | 0.000 ns| 8.445 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns | | |
CLKPORT "RCLK" ; Setup Analysis. | 12.500 ns| 10.284 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns | | |
CLKPORT "RCLK" ; Hold Analysis. | 0.000 ns| 8.599 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns | | |
CLKPORT "RCLK" ; Setup Analysis. | 12.500 ns| 10.501 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns | | |
CLKPORT "RCLK" ; Hold Analysis. | 0.000 ns| 8.849 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns | | |
CLKPORT "RCLK" ; Setup Analysis. | 12.500 ns| 10.284 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns | | |
CLKPORT "RCLK" ; Hold Analysis. | 0.000 ns| 8.599 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns | | |
CLKPORT "RCLK" ; Setup Analysis. | 12.500 ns| 10.046 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns | | |
CLKPORT "RCLK" ; Hold Analysis. | 0.000 ns| 8.442 ns| 3
| | |
CLOCK_TO_OUT PORT "nRCS" 12.500000 ns | | |
CLKPORT "RCLK" ; Setup Analysis. | 12.500 ns| 7.501 ns| 2
| | |
CLOCK_TO_OUT PORT "nRCS" 12.500000 ns | | |
CLKPORT "RCLK" ; Hold Analysis. | 0.000 ns| 6.396 ns| 2
| | |
CLOCK_TO_OUT PORT "RCKE" 12.500000 ns | | |
CLKPORT "RCLK" ; Setup Analysis. | 12.500 ns| 7.501 ns| 2
| | |
CLOCK_TO_OUT PORT "RCKE" 12.500000 ns | | |
CLKPORT "RCLK" ; Hold Analysis. | 0.000 ns| 6.396 ns| 2
| | |
CLOCK_TO_OUT PORT "nRWE" 12.500000 ns | | |
CLKPORT "RCLK" ; Setup Analysis. | 12.500 ns| 8.667 ns| 2
| | |
CLOCK_TO_OUT PORT "nRWE" 12.500000 ns | | |
CLKPORT "RCLK" ; Hold Analysis. | 0.000 ns| 7.321 ns| 2
| | |
CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns | | |
CLKPORT "RCLK" ; Setup Analysis. | 12.500 ns| 8.687 ns| 2
| | |
CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns | | |
CLKPORT "RCLK" ; Hold Analysis. | 0.000 ns| 7.334 ns| 2
| | |
CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns | | |
CLKPORT "RCLK" ; Setup Analysis. | 12.500 ns| 7.501 ns| 2
| | |
CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns | | |
CLKPORT "RCLK" ; Hold Analysis. | 0.000 ns| 6.396 ns| 2
| | |
CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns | | |
CLKPORT "RCLK" ; Setup Analysis. | 12.500 ns| 10.511 ns| 3
| | |
CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns | | |
CLKPORT "RCLK" ; Hold Analysis. | 0.000 ns| 8.888 ns| 3
| | |
CLOCK_TO_OUT PORT "RDQML" 12.500000 ns | | |
CLKPORT "RCLK" ; Setup Analysis. | 12.500 ns| 9.608 ns| 3
| | |
CLOCK_TO_OUT PORT "RDQML" 12.500000 ns | | |
CLKPORT "RCLK" ; Hold Analysis. | 0.000 ns| 8.163 ns| 3
| | |
CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns | | |
CLKPORT "RCLK" ; Setup Analysis. | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns | | |
CLKPORT "RCLK" ; Hold Analysis. | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns | | |
CLKPORT "RCLK" ; Setup Analysis. | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns | | |
CLKPORT "RCLK" ; Hold Analysis. | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns | | |
CLKPORT "RCLK" ; Setup Analysis. | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns | | |
CLKPORT "RCLK" ; Hold Analysis. | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns | | |
CLKPORT "RCLK" ; Setup Analysis. | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns | | |
CLKPORT "RCLK" ; Hold Analysis. | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns | | |
CLKPORT "RCLK" ; Setup Analysis. | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns | | |
CLKPORT "RCLK" ; Hold Analysis. | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns | | |
CLKPORT "RCLK" ; Setup Analysis. | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns | | |
CLKPORT "RCLK" ; Hold Analysis. | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns | | |
CLKPORT "RCLK" ; Setup Analysis. | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns | | |
CLKPORT "RCLK" ; Hold Analysis. | -| -| 0
| | |
----------------------------------------------------------------------------
All preferences were met.
<A name="Clock Domains Analysis"></A><B><U><big>Clock Domains Analysis</big></U></B>
------------------------
Found 4 clocks:
Clock Domain: <A href="#@net:nCRAS_c">nCRAS_c</A> Source: nCRAS.PAD Loads: 9
No transfer within this clock domain is found
Data transfers from:
Clock Domain: <A href="#@net:RCLK_c">RCLK_c</A> Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: <A href="#@net:nCCAS_c">nCCAS_c</A> Source: nCCAS.PAD Loads: 7
No transfer within this clock domain is found
Clock Domain: <A href="#@net:RCLK_c">RCLK_c</A> Source: RCLK.PAD Loads: 39
Covered under: PERIOD NET "RCLK_c" 16.000000 ns ;
Data transfers from:
Clock Domain: <A href="#@net:nCRAS_c">nCRAS_c</A> Source: nCRAS.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: <A href="#@net:PHI2_c">PHI2_c</A> Source: PHI2.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: <A href="#@net:PHI2_c">PHI2_c</A> Source: PHI2.PAD Loads: 14
Covered under: PERIOD NET "PHI2_c" 350.000000 ns ;
Data transfers from:
Clock Domain: <A href="#@net:RCLK_c">RCLK_c</A> Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Timing summary (Setup):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 538 paths, 6 nets, and 440 connections (71.54% coverage)
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