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--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
Mon Aug 16 20:23:38 2021
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Design file: RAM2GS
Device,speed: LCMXO256C,M
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
Derating parameters
-------------------
Voltage: 3.300 V
</A><A name="PERIOD NET 'PHI2_c' 350.000000 ns"></A>================================================================================
Preference: PERIOD NET "PHI2_c" 350.000000 ns ;
10 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
<font color=#000000>
Passed: The following path meets requirements by 0.540ns
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_9">ADSubmitted_375</A> (from <A href="#@net:PHI2_c">PHI2_c</A> -)
Destination: FF Data in <A href="#@comp:SLICE_9">ADSubmitted_375</A> (to <A href="#@net:PHI2_c">PHI2_c</A> -)
Delay: 0.517ns (50.7% logic, 49.3% route), 2 logic levels.
Constraint Details:
0.517ns physical path delay SLICE_9 to SLICE_9 meets
-0.023ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.023ns) by 0.540ns
Physical Path Details:
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:REG_DEL, 0.170,R6C3C.CLK,R6C3C.Q0,SLICE_9:ROUTE, 0.255,R6C3C.Q0,R6C3C.B0,ADSubmitted:CTOF_DEL, 0.092,R6C3C.B0,R6C3C.F0,SLICE_9:ROUTE, 0.000,R6C3C.F0,R6C3C.DI0,n1355">Data path</A> SLICE_9 to SLICE_9:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.170 R6C3C.CLK to R6C3C.Q0 <A href="#@comp:SLICE_9">SLICE_9</A> (from <A href="#@net:PHI2_c">PHI2_c</A>)
ROUTE 2 0.255<A href="#@net:ADSubmitted:R6C3C.Q0:R6C3C.B0:0.255"> R6C3C.Q0 to R6C3C.B0 </A> <A href="#@net:ADSubmitted">ADSubmitted</A>
CTOF_DEL --- 0.092 R6C3C.B0 to R6C3C.F0 <A href="#@comp:SLICE_9">SLICE_9</A>
ROUTE 1 0.000<A href="#@net:n1355:R6C3C.F0:R6C3C.DI0:0.000"> R6C3C.F0 to R6C3C.DI0 </A> <A href="#@net:n1355">n1355</A> (to <A href="#@net:PHI2_c">PHI2_c</A>)
--------
0.517 (50.7% logic, 49.3% route), 2 logic levels.
Clock Skew Details:
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 1.200,39.PADDI,R6C3C.CLK,PHI2_c">Source Clock Path</A> PHI2 to SLICE_9:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.200<A href="#@net:PHI2_c:39.PADDI:R6C3C.CLK:1.200"> 39.PADDI to R6C3C.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
--------
1.200 (0.0% logic, 100.0% route), 0 logic levels.
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 1.200,39.PADDI,R6C3C.CLK,PHI2_c">Destination Clock Path</A> PHI2 to SLICE_9:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.200<A href="#@net:PHI2_c:39.PADDI:R6C3C.CLK:1.200"> 39.PADDI to R6C3C.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
--------
1.200 (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000>
Passed: The following path meets requirements by 1.089ns
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_18">CmdEnable_373</A> (from <A href="#@net:PHI2_c">PHI2_c</A> -)
Destination: FF Data in <A href="#@comp:SLICE_83">CmdUFMCS_379</A> (to <A href="#@net:PHI2_c">PHI2_c</A> -)
FF <A href="#@net:CmdUFMCLK_380">CmdUFMCLK_380</A>
Delay: 1.060ns (33.4% logic, 66.6% route), 3 logic levels.
Constraint Details:
1.060ns physical path delay SLICE_18 to SLICE_83 meets
-0.029ns CE_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.029ns) by 1.089ns
Physical Path Details:
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:REG_DEL, 0.170,R6C4D.CLK,R6C4D.Q0,SLICE_18:ROUTE, 0.174,R6C4D.Q0,R6C3A.D1,CmdEnable:CTOF_DEL, 0.092,R6C3A.D1,R6C3A.F1,SLICE_76:ROUTE, 0.354,R6C3A.F1,R4C5A.C1,XOR8MEG_N_112:CTOF_DEL, 0.092,R4C5A.C1,R4C5A.F1,SLICE_73:ROUTE, 0.178,R4C5A.F1,R5C5D.CE,PHI2_N_114_enable_7">Data path</A> SLICE_18 to SLICE_83:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.170 R6C4D.CLK to R6C4D.Q0 <A href="#@comp:SLICE_18">SLICE_18</A> (from <A href="#@net:PHI2_c">PHI2_c</A>)
ROUTE 1 0.174<A href="#@net:CmdEnable:R6C4D.Q0:R6C3A.D1:0.174"> R6C4D.Q0 to R6C3A.D1 </A> <A href="#@net:CmdEnable">CmdEnable</A>
CTOF_DEL --- 0.092 R6C3A.D1 to R6C3A.F1 <A href="#@comp:SLICE_76">SLICE_76</A>
ROUTE 3 0.354<A href="#@net:XOR8MEG_N_112:R6C3A.F1:R4C5A.C1:0.354"> R6C3A.F1 to R4C5A.C1 </A> <A href="#@net:XOR8MEG_N_112">XOR8MEG_N_112</A>
CTOF_DEL --- 0.092 R4C5A.C1 to R4C5A.F1 <A href="#@comp:SLICE_73">SLICE_73</A>
ROUTE 2 0.178<A href="#@net:PHI2_N_114_enable_7:R4C5A.F1:R5C5D.CE:0.178"> R4C5A.F1 to R5C5D.CE </A> <A href="#@net:PHI2_N_114_enable_7">PHI2_N_114_enable_7</A> (to <A href="#@net:PHI2_c">PHI2_c</A>)
--------
1.060 (33.4% logic, 66.6% route), 3 logic levels.
Clock Skew Details:
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 1.200,39.PADDI,R6C4D.CLK,PHI2_c">Source Clock Path</A> PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.200<A href="#@net:PHI2_c:39.PADDI:R6C4D.CLK:1.200"> 39.PADDI to R6C4D.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
--------
1.200 (0.0% logic, 100.0% route), 0 logic levels.
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 1.200,39.PADDI,R5C5D.CLK,PHI2_c">Destination Clock Path</A> PHI2 to SLICE_83:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.200<A href="#@net:PHI2_c:39.PADDI:R5C5D.CLK:1.200"> 39.PADDI to R5C5D.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
--------
1.200 (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000>
Passed: The following path meets requirements by 1.165ns
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_18">CmdEnable_373</A> (from <A href="#@net:PHI2_c">PHI2_c</A> -)
Destination: FF Data in <A href="#@comp:SLICE_19">CmdSubmitted_378</A> (to <A href="#@net:PHI2_c">PHI2_c</A> -)
Delay: 1.136ns (31.2% logic, 68.8% route), 3 logic levels.
Constraint Details:
1.136ns physical path delay SLICE_18 to SLICE_19 meets
-0.029ns CE_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.029ns) by 1.165ns
Physical Path Details:
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:REG_DEL, 0.170,R6C4D.CLK,R6C4D.Q0,SLICE_18:ROUTE, 0.174,R6C4D.Q0,R6C3A.D1,CmdEnable:CTOF_DEL, 0.092,R6C3A.D1,R6C3A.F1,SLICE_76:ROUTE, 0.181,R6C3A.F1,R6C3A.B0,XOR8MEG_N_112:CTOF_DEL, 0.092,R6C3A.B0,R6C3A.F0,SLICE_76:ROUTE, 0.427,R6C3A.F0,R7C4D.CE,PHI2_N_114_enable_6">Data path</A> SLICE_18 to SLICE_19:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.170 R6C4D.CLK to R6C4D.Q0 <A href="#@comp:SLICE_18">SLICE_18</A> (from <A href="#@net:PHI2_c">PHI2_c</A>)
ROUTE 1 0.174<A href="#@net:CmdEnable:R6C4D.Q0:R6C3A.D1:0.174"> R6C4D.Q0 to R6C3A.D1 </A> <A href="#@net:CmdEnable">CmdEnable</A>
CTOF_DEL --- 0.092 R6C3A.D1 to R6C3A.F1 <A href="#@comp:SLICE_76">SLICE_76</A>
ROUTE 3 0.181<A href="#@net:XOR8MEG_N_112:R6C3A.F1:R6C3A.B0:0.181"> R6C3A.F1 to R6C3A.B0 </A> <A href="#@net:XOR8MEG_N_112">XOR8MEG_N_112</A>
CTOF_DEL --- 0.092 R6C3A.B0 to R6C3A.F0 <A href="#@comp:SLICE_76">SLICE_76</A>
ROUTE 2 0.427<A href="#@net:PHI2_N_114_enable_6:R6C3A.F0:R7C4D.CE:0.427"> R6C3A.F0 to R7C4D.CE </A> <A href="#@net:PHI2_N_114_enable_6">PHI2_N_114_enable_6</A> (to <A href="#@net:PHI2_c">PHI2_c</A>)
--------
1.136 (31.2% logic, 68.8% route), 3 logic levels.
Clock Skew Details:
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 1.200,39.PADDI,R6C4D.CLK,PHI2_c">Source Clock Path</A> PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.200<A href="#@net:PHI2_c:39.PADDI:R6C4D.CLK:1.200"> 39.PADDI to R6C4D.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
--------
1.200 (0.0% logic, 100.0% route), 0 logic levels.
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 1.200,39.PADDI,R7C4D.CLK,PHI2_c">Destination Clock Path</A> PHI2 to SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.200<A href="#@net:PHI2_c:39.PADDI:R7C4D.CLK:1.200"> 39.PADDI to R7C4D.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
--------
1.200 (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000>
Passed: The following path meets requirements by 1.212ns
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_18">CmdEnable_373</A> (from <A href="#@net:PHI2_c">PHI2_c</A> -)
Destination: FF Data in <A href="#@comp:SLICE_77">CmdUFMSDI_381</A> (to <A href="#@net:PHI2_c">PHI2_c</A> -)
Delay: 1.183ns (29.9% logic, 70.1% route), 3 logic levels.
Constraint Details:
1.183ns physical path delay SLICE_18 to SLICE_77 meets
-0.029ns CE_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.029ns) by 1.212ns
Physical Path Details:
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:REG_DEL, 0.170,R6C4D.CLK,R6C4D.Q0,SLICE_18:ROUTE, 0.174,R6C4D.Q0,R6C3A.D1,CmdEnable:CTOF_DEL, 0.092,R6C3A.D1,R6C3A.F1,SLICE_76:ROUTE, 0.354,R6C3A.F1,R4C5A.C1,XOR8MEG_N_112:CTOF_DEL, 0.092,R4C5A.C1,R4C5A.F1,SLICE_73:ROUTE, 0.301,R4C5A.F1,R7C5C.CE,PHI2_N_114_enable_7">Data path</A> SLICE_18 to SLICE_77:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.170 R6C4D.CLK to R6C4D.Q0 <A href="#@comp:SLICE_18">SLICE_18</A> (from <A href="#@net:PHI2_c">PHI2_c</A>)
ROUTE 1 0.174<A href="#@net:CmdEnable:R6C4D.Q0:R6C3A.D1:0.174"> R6C4D.Q0 to R6C3A.D1 </A> <A href="#@net:CmdEnable">CmdEnable</A>
CTOF_DEL --- 0.092 R6C3A.D1 to R6C3A.F1 <A href="#@comp:SLICE_76">SLICE_76</A>
ROUTE 3 0.354<A href="#@net:XOR8MEG_N_112:R6C3A.F1:R4C5A.C1:0.354"> R6C3A.F1 to R4C5A.C1 </A> <A href="#@net:XOR8MEG_N_112">XOR8MEG_N_112</A>
CTOF_DEL --- 0.092 R4C5A.C1 to R4C5A.F1 <A href="#@comp:SLICE_73">SLICE_73</A>
ROUTE 2 0.301<A href="#@net:PHI2_N_114_enable_7:R4C5A.F1:R7C5C.CE:0.301"> R4C5A.F1 to R7C5C.CE </A> <A href="#@net:PHI2_N_114_enable_7">PHI2_N_114_enable_7</A> (to <A href="#@net:PHI2_c">PHI2_c</A>)
--------
1.183 (29.9% logic, 70.1% route), 3 logic levels.
Clock Skew Details:
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 1.200,39.PADDI,R6C4D.CLK,PHI2_c">Source Clock Path</A> PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.200<A href="#@net:PHI2_c:39.PADDI:R6C4D.CLK:1.200"> 39.PADDI to R6C4D.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
--------
1.200 (0.0% logic, 100.0% route), 0 logic levels.
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 1.200,39.PADDI,R7C5C.CLK,PHI2_c">Destination Clock Path</A> PHI2 to SLICE_77:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.200<A href="#@net:PHI2_c:39.PADDI:R7C5C.CLK:1.200"> 39.PADDI to R7C5C.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
--------
1.200 (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000>
Passed: The following path meets requirements by 1.247ns
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_18">CmdEnable_373</A> (from <A href="#@net:PHI2_c">PHI2_c</A> -)
Destination: FF Data in <A href="#@comp:SLICE_94">XOR8MEG_376</A> (to <A href="#@net:PHI2_c">PHI2_c</A> -)
Delay: 1.218ns (29.1% logic, 70.9% route), 3 logic levels.
Constraint Details:
1.218ns physical path delay SLICE_18 to SLICE_94 meets
-0.029ns CE_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.029ns) by 1.247ns
Physical Path Details:
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:REG_DEL, 0.170,R6C4D.CLK,R6C4D.Q0,SLICE_18:ROUTE, 0.174,R6C4D.Q0,R6C3A.D1,CmdEnable:CTOF_DEL, 0.092,R6C3A.D1,R6C3A.F1,SLICE_76:ROUTE, 0.266,R6C3A.F1,R7C3C.A0,XOR8MEG_N_112:CTOF_DEL, 0.092,R7C3C.A0,R7C3C.F0,SLICE_97:ROUTE, 0.424,R7C3C.F0,R8C5C.CE,PHI2_N_114_enable_2">Data path</A> SLICE_18 to SLICE_94:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.170 R6C4D.CLK to R6C4D.Q0 <A href="#@comp:SLICE_18">SLICE_18</A> (from <A href="#@net:PHI2_c">PHI2_c</A>)
ROUTE 1 0.174<A href="#@net:CmdEnable:R6C4D.Q0:R6C3A.D1:0.174"> R6C4D.Q0 to R6C3A.D1 </A> <A href="#@net:CmdEnable">CmdEnable</A>
CTOF_DEL --- 0.092 R6C3A.D1 to R6C3A.F1 <A href="#@comp:SLICE_76">SLICE_76</A>
ROUTE 3 0.266<A href="#@net:XOR8MEG_N_112:R6C3A.F1:R7C3C.A0:0.266"> R6C3A.F1 to R7C3C.A0 </A> <A href="#@net:XOR8MEG_N_112">XOR8MEG_N_112</A>
CTOF_DEL --- 0.092 R7C3C.A0 to R7C3C.F0 <A href="#@comp:SLICE_97">SLICE_97</A>
ROUTE 1 0.424<A href="#@net:PHI2_N_114_enable_2:R7C3C.F0:R8C5C.CE:0.424"> R7C3C.F0 to R8C5C.CE </A> <A href="#@net:PHI2_N_114_enable_2">PHI2_N_114_enable_2</A> (to <A href="#@net:PHI2_c">PHI2_c</A>)
--------
1.218 (29.1% logic, 70.9% route), 3 logic levels.
Clock Skew Details:
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 1.200,39.PADDI,R6C4D.CLK,PHI2_c">Source Clock Path</A> PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.200<A href="#@net:PHI2_c:39.PADDI:R6C4D.CLK:1.200"> 39.PADDI to R6C4D.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
--------
1.200 (0.0% logic, 100.0% route), 0 logic levels.
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 1.200,39.PADDI,R8C5C.CLK,PHI2_c">Destination Clock Path</A> PHI2 to SLICE_94:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.200<A href="#@net:PHI2_c:39.PADDI:R8C5C.CLK:1.200"> 39.PADDI to R8C5C.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
--------
1.200 (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000>
Passed: The following path meets requirements by 1.288ns
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_18">CmdEnable_373</A> (from <A href="#@net:PHI2_c">PHI2_c</A> -)
Destination: FF Data in <A href="#@comp:SLICE_23">Cmdn8MEGEN_377</A> (to <A href="#@net:PHI2_c">PHI2_c</A> -)
Delay: 1.259ns (28.1% logic, 71.9% route), 3 logic levels.
Constraint Details:
1.259ns physical path delay SLICE_18 to SLICE_23 meets
-0.029ns CE_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.029ns) by 1.288ns
Physical Path Details:
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:REG_DEL, 0.170,R6C4D.CLK,R6C4D.Q0,SLICE_18:ROUTE, 0.174,R6C4D.Q0,R6C3A.D1,CmdEnable:CTOF_DEL, 0.092,R6C3A.D1,R6C3A.F1,SLICE_76:ROUTE, 0.181,R6C3A.F1,R6C3A.B0,XOR8MEG_N_112:CTOF_DEL, 0.092,R6C3A.B0,R6C3A.F0,SLICE_76:ROUTE, 0.550,R6C3A.F0,R7C3A.CE,PHI2_N_114_enable_6">Data path</A> SLICE_18 to SLICE_23:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.170 R6C4D.CLK to R6C4D.Q0 <A href="#@comp:SLICE_18">SLICE_18</A> (from <A href="#@net:PHI2_c">PHI2_c</A>)
ROUTE 1 0.174<A href="#@net:CmdEnable:R6C4D.Q0:R6C3A.D1:0.174"> R6C4D.Q0 to R6C3A.D1 </A> <A href="#@net:CmdEnable">CmdEnable</A>
CTOF_DEL --- 0.092 R6C3A.D1 to R6C3A.F1 <A href="#@comp:SLICE_76">SLICE_76</A>
ROUTE 3 0.181<A href="#@net:XOR8MEG_N_112:R6C3A.F1:R6C3A.B0:0.181"> R6C3A.F1 to R6C3A.B0 </A> <A href="#@net:XOR8MEG_N_112">XOR8MEG_N_112</A>
CTOF_DEL --- 0.092 R6C3A.B0 to R6C3A.F0 <A href="#@comp:SLICE_76">SLICE_76</A>
ROUTE 2 0.550<A href="#@net:PHI2_N_114_enable_6:R6C3A.F0:R7C3A.CE:0.550"> R6C3A.F0 to R7C3A.CE </A> <A href="#@net:PHI2_N_114_enable_6">PHI2_N_114_enable_6</A> (to <A href="#@net:PHI2_c">PHI2_c</A>)
--------
1.259 (28.1% logic, 71.9% route), 3 logic levels.
Clock Skew Details:
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 1.200,39.PADDI,R6C4D.CLK,PHI2_c">Source Clock Path</A> PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.200<A href="#@net:PHI2_c:39.PADDI:R6C4D.CLK:1.200"> 39.PADDI to R6C4D.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
--------
1.200 (0.0% logic, 100.0% route), 0 logic levels.
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 1.200,39.PADDI,R7C3A.CLK,PHI2_c">Destination Clock Path</A> PHI2 to SLICE_23:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.200<A href="#@net:PHI2_c:39.PADDI:R7C3A.CLK:1.200"> 39.PADDI to R7C3A.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
--------
1.200 (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000>
Passed: The following path meets requirements by 1.392ns
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_14">C1Submitted_374</A> (from <A href="#@net:PHI2_c">PHI2_c</A> -)
Destination: FF Data in <A href="#@comp:SLICE_18">CmdEnable_373</A> (to <A href="#@net:PHI2_c">PHI2_c</A> -)
Delay: 1.363ns (37.1% logic, 62.9% route), 4 logic levels.
Constraint Details:
1.363ns physical path delay SLICE_14 to SLICE_18 meets
-0.029ns CE_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.029ns) by 1.392ns
Physical Path Details:
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:REG_DEL, 0.170,R6C4C.CLK,R6C4C.Q0,SLICE_14:ROUTE, 0.256,R6C4C.Q0,R6C3D.A1,C1Submitted:CTOOFX_DEL, 0.151,R6C3D.A1,R6C3D.OFX0,i26/SLICE_70:ROUTE, 0.269,R6C3D.OFX0,R6C4A.B1,n13:CTOF_DEL, 0.092,R6C4A.B1,R6C4A.F1,SLICE_80:ROUTE, 0.172,R6C4A.F1,R6C4A.B0,n6:CTOF_DEL, 0.092,R6C4A.B0,R6C4A.F0,SLICE_80:ROUTE, 0.161,R6C4A.F0,R6C4D.CE,PHI2_N_114_enable_8">Data path</A> SLICE_14 to SLICE_18:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.170 R6C4C.CLK to R6C4C.Q0 <A href="#@comp:SLICE_14">SLICE_14</A> (from <A href="#@net:PHI2_c">PHI2_c</A>)
ROUTE 1 0.256<A href="#@net:C1Submitted:R6C4C.Q0:R6C3D.A1:0.256"> R6C4C.Q0 to R6C3D.A1 </A> <A href="#@net:C1Submitted">C1Submitted</A>
CTOOFX_DEL --- 0.151 R6C3D.A1 to R6C3D.OFX0 <A href="#@comp:i26/SLICE_70">i26/SLICE_70</A>
ROUTE 1 0.269<A href="#@net:n13:R6C3D.OFX0:R6C4A.B1:0.269"> R6C3D.OFX0 to R6C4A.B1 </A> <A href="#@net:n13">n13</A>
CTOF_DEL --- 0.092 R6C4A.B1 to R6C4A.F1 <A href="#@comp:SLICE_80">SLICE_80</A>
ROUTE 1 0.172<A href="#@net:n6:R6C4A.F1:R6C4A.B0:0.172"> R6C4A.F1 to R6C4A.B0 </A> <A href="#@net:n6">n6</A>
CTOF_DEL --- 0.092 R6C4A.B0 to R6C4A.F0 <A href="#@comp:SLICE_80">SLICE_80</A>
ROUTE 1 0.161<A href="#@net:PHI2_N_114_enable_8:R6C4A.F0:R6C4D.CE:0.161"> R6C4A.F0 to R6C4D.CE </A> <A href="#@net:PHI2_N_114_enable_8">PHI2_N_114_enable_8</A> (to <A href="#@net:PHI2_c">PHI2_c</A>)
--------
1.363 (37.1% logic, 62.9% route), 4 logic levels.
Clock Skew Details:
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 1.200,39.PADDI,R6C4C.CLK,PHI2_c">Source Clock Path</A> PHI2 to SLICE_14:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.200<A href="#@net:PHI2_c:39.PADDI:R6C4C.CLK:1.200"> 39.PADDI to R6C4C.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
--------
1.200 (0.0% logic, 100.0% route), 0 logic levels.
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 1.200,39.PADDI,R6C4D.CLK,PHI2_c">Destination Clock Path</A> PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.200<A href="#@net:PHI2_c:39.PADDI:R6C4D.CLK:1.200"> 39.PADDI to R6C4D.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
--------
1.200 (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000>
Passed: The following path meets requirements by 1.395ns
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_9">ADSubmitted_375</A> (from <A href="#@net:PHI2_c">PHI2_c</A> -)
Destination: FF Data in <A href="#@comp:SLICE_18">CmdEnable_373</A> (to <A href="#@net:PHI2_c">PHI2_c</A> -)
Delay: 1.366ns (37.3% logic, 62.7% route), 4 logic levels.
Constraint Details:
1.366ns physical path delay SLICE_9 to SLICE_18 meets
-0.029ns CE_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.029ns) by 1.395ns
Physical Path Details:
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:REG_DEL, 0.170,R6C3C.CLK,R6C3C.Q0,SLICE_9:ROUTE, 0.255,R6C3C.Q0,R6C3D.B0,ADSubmitted:CTOOFX_DEL, 0.155,R6C3D.B0,R6C3D.OFX0,i26/SLICE_70:ROUTE, 0.269,R6C3D.OFX0,R6C4A.B1,n13:CTOF_DEL, 0.092,R6C4A.B1,R6C4A.F1,SLICE_80:ROUTE, 0.172,R6C4A.F1,R6C4A.B0,n6:CTOF_DEL, 0.092,R6C4A.B0,R6C4A.F0,SLICE_80:ROUTE, 0.161,R6C4A.F0,R6C4D.CE,PHI2_N_114_enable_8">Data path</A> SLICE_9 to SLICE_18:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.170 R6C3C.CLK to R6C3C.Q0 <A href="#@comp:SLICE_9">SLICE_9</A> (from <A href="#@net:PHI2_c">PHI2_c</A>)
ROUTE 2 0.255<A href="#@net:ADSubmitted:R6C3C.Q0:R6C3D.B0:0.255"> R6C3C.Q0 to R6C3D.B0 </A> <A href="#@net:ADSubmitted">ADSubmitted</A>
CTOOFX_DEL --- 0.155 R6C3D.B0 to R6C3D.OFX0 <A href="#@comp:i26/SLICE_70">i26/SLICE_70</A>
ROUTE 1 0.269<A href="#@net:n13:R6C3D.OFX0:R6C4A.B1:0.269"> R6C3D.OFX0 to R6C4A.B1 </A> <A href="#@net:n13">n13</A>
CTOF_DEL --- 0.092 R6C4A.B1 to R6C4A.F1 <A href="#@comp:SLICE_80">SLICE_80</A>
ROUTE 1 0.172<A href="#@net:n6:R6C4A.F1:R6C4A.B0:0.172"> R6C4A.F1 to R6C4A.B0 </A> <A href="#@net:n6">n6</A>
CTOF_DEL --- 0.092 R6C4A.B0 to R6C4A.F0 <A href="#@comp:SLICE_80">SLICE_80</A>
ROUTE 1 0.161<A href="#@net:PHI2_N_114_enable_8:R6C4A.F0:R6C4D.CE:0.161"> R6C4A.F0 to R6C4D.CE </A> <A href="#@net:PHI2_N_114_enable_8">PHI2_N_114_enable_8</A> (to <A href="#@net:PHI2_c">PHI2_c</A>)
--------
1.366 (37.3% logic, 62.7% route), 4 logic levels.
Clock Skew Details:
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 1.200,39.PADDI,R6C3C.CLK,PHI2_c">Source Clock Path</A> PHI2 to SLICE_9:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.200<A href="#@net:PHI2_c:39.PADDI:R6C3C.CLK:1.200"> 39.PADDI to R6C3C.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
--------
1.200 (0.0% logic, 100.0% route), 0 logic levels.
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 1.200,39.PADDI,R6C4D.CLK,PHI2_c">Destination Clock Path</A> PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.200<A href="#@net:PHI2_c:39.PADDI:R6C4D.CLK:1.200"> 39.PADDI to R6C4D.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
--------
1.200 (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000>
Passed: The following path meets requirements by 175.744ns (weighted slack = 351.488ns)
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_94">XOR8MEG_376</A> (from <A href="#@net:PHI2_c">PHI2_c</A> -)
Destination: FF Data in <A href="#@comp:SLICE_31">RA11_353</A> (to <A href="#@net:PHI2_c">PHI2_c</A> +)
Delay: 0.733ns (35.7% logic, 64.3% route), 2 logic levels.
Constraint Details:
0.733ns physical path delay SLICE_94 to SLICE_31 meets
-0.011ns DIN_HLD and
-175.000ns delay constraint less
0.000ns skew requirement (totaling -175.011ns) by 175.744ns
Physical Path Details:
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:REG_DEL, 0.170,R8C5C.CLK,R8C5C.Q0,SLICE_94:ROUTE, 0.471,R8C5C.Q0,R2C5A.C0,XOR8MEG:CTOF_DEL, 0.092,R2C5A.C0,R2C5A.F0,SLICE_31:ROUTE, 0.000,R2C5A.F0,R2C5A.DI0,RA11_N_180">Data path</A> SLICE_94 to SLICE_31:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.170 R8C5C.CLK to R8C5C.Q0 <A href="#@comp:SLICE_94">SLICE_94</A> (from <A href="#@net:PHI2_c">PHI2_c</A>)
ROUTE 1 0.471<A href="#@net:XOR8MEG:R8C5C.Q0:R2C5A.C0:0.471"> R8C5C.Q0 to R2C5A.C0 </A> <A href="#@net:XOR8MEG">XOR8MEG</A>
CTOF_DEL --- 0.092 R2C5A.C0 to R2C5A.F0 <A href="#@comp:SLICE_31">SLICE_31</A>
ROUTE 1 0.000<A href="#@net:RA11_N_180:R2C5A.F0:R2C5A.DI0:0.000"> R2C5A.F0 to R2C5A.DI0 </A> <A href="#@net:RA11_N_180">RA11_N_180</A> (to <A href="#@net:PHI2_c">PHI2_c</A>)
--------
0.733 (35.7% logic, 64.3% route), 2 logic levels.
Clock Skew Details:
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 1.200,39.PADDI,R8C5C.CLK,PHI2_c">Source Clock Path</A> PHI2 to SLICE_94:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.200<A href="#@net:PHI2_c:39.PADDI:R8C5C.CLK:1.200"> 39.PADDI to R8C5C.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
--------
1.200 (0.0% logic, 100.0% route), 0 logic levels.
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 1.200,39.PADDI,R2C5A.CLK,PHI2_c">Destination Clock Path</A> PHI2 to SLICE_31:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.200<A href="#@net:PHI2_c:39.PADDI:R2C5A.CLK:1.200"> 39.PADDI to R2C5A.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
--------
1.200 (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000>
Passed: The following path meets requirements by 176.433ns (weighted slack = 352.866ns)
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_92">Bank_i3</A> (from <A href="#@net:PHI2_c">PHI2_c</A> +)
Destination: FF Data in <A href="#@comp:SLICE_14">C1Submitted_374</A> (to <A href="#@net:PHI2_c">PHI2_c</A> -)
Delay: 1.404ns (24.3% logic, 75.7% route), 3 logic levels.
Constraint Details:
1.404ns physical path delay SLICE_92 to SLICE_14 meets
-0.029ns CE_HLD and
-175.000ns delay constraint less
0.000ns skew requirement (totaling -175.029ns) by 176.433ns
Physical Path Details:
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:REG_DEL, 0.157,R2C3B.CLK,R2C3B.Q1,SLICE_92:ROUTE, 0.502,R2C3B.Q1,R5C4B.A1,Bank_3:CTOF_DEL, 0.092,R5C4B.A1,R5C4B.F1,SLICE_74:ROUTE, 0.137,R5C4B.F1,R5C4B.C0,n1279:CTOF_DEL, 0.092,R5C4B.C0,R5C4B.F0,SLICE_74:ROUTE, 0.424,R5C4B.F0,R6C4C.CE,PHI2_N_114_enable_1">Data path</A> SLICE_92 to SLICE_14:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R2C3B.CLK to R2C3B.Q1 <A href="#@comp:SLICE_92">SLICE_92</A> (from <A href="#@net:PHI2_c">PHI2_c</A>)
ROUTE 1 0.502<A href="#@net:Bank_3:R2C3B.Q1:R5C4B.A1:0.502"> R2C3B.Q1 to R5C4B.A1 </A> <A href="#@net:Bank_3">Bank_3</A>
CTOF_DEL --- 0.092 R5C4B.A1 to R5C4B.F1 <A href="#@comp:SLICE_74">SLICE_74</A>
ROUTE 5 0.137<A href="#@net:n1279:R5C4B.F1:R5C4B.C0:0.137"> R5C4B.F1 to R5C4B.C0 </A> <A href="#@net:n1279">n1279</A>
CTOF_DEL --- 0.092 R5C4B.C0 to R5C4B.F0 <A href="#@comp:SLICE_74">SLICE_74</A>
ROUTE 1 0.424<A href="#@net:PHI2_N_114_enable_1:R5C4B.F0:R6C4C.CE:0.424"> R5C4B.F0 to R6C4C.CE </A> <A href="#@net:PHI2_N_114_enable_1">PHI2_N_114_enable_1</A> (to <A href="#@net:PHI2_c">PHI2_c</A>)
--------
1.404 (24.3% logic, 75.7% route), 3 logic levels.
Clock Skew Details:
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 1.200,39.PADDI,R2C3B.CLK,PHI2_c">Source Clock Path</A> PHI2 to SLICE_92:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.200<A href="#@net:PHI2_c:39.PADDI:R2C3B.CLK:1.200"> 39.PADDI to R2C3B.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
--------
1.200 (0.0% logic, 100.0% route), 0 logic levels.
<A href="#@path:PERIOD NET 'PHI2_c' 350.000000 ns ;:ROUTE, 1.200,39.PADDI,R6C4C.CLK,PHI2_c">Destination Clock Path</A> PHI2 to SLICE_14:
Name Fanout Delay (ns) Site Resource
ROUTE 14 1.200<A href="#@net:PHI2_c:39.PADDI:R6C4C.CLK:1.200"> 39.PADDI to R6C4C.CLK </A> <A href="#@net:PHI2_c">PHI2_c</A>
--------
1.200 (0.0% logic, 100.0% route), 0 logic levels.
</A><A name="PERIOD NET 'nCCAS_c' 350.000000 ns"></A>================================================================================
Preference: PERIOD NET "nCCAS_c" 350.000000 ns ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="PERIOD NET 'nCRAS_c' 350.000000 ns"></A>================================================================================
Preference: PERIOD NET "nCRAS_c" 350.000000 ns ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="PERIOD NET 'RCLK_c' 15.000000 ns"></A>================================================================================
Preference: PERIOD NET "RCLK_c" 15.000000 ns ;
10 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
<font color=#000000>
Passed: The following path meets requirements by 0.339ns
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_101">IS_FSM__i2</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: FF Data in <A href="#@comp:SLICE_101">IS_FSM__i3</A> (to <A href="#@net:RCLK_c">RCLK_c</A> +)
Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels.
Constraint Details:
0.318ns physical path delay SLICE_101 to SLICE_101 meets
-0.021ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.021ns) by 0.339ns
Physical Path Details:
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:REG_DEL, 0.157,R5C4C.CLK,R5C4C.Q0,SLICE_101:ROUTE, 0.161,R5C4C.Q0,R5C4C.M1,n705">Data path</A> SLICE_101 to SLICE_101:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R5C4C.CLK to R5C4C.Q0 <A href="#@comp:SLICE_101">SLICE_101</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 1 0.161<A href="#@net:n705:R5C4C.Q0:R5C4C.M1:0.161"> R5C4C.Q0 to R5C4C.M1 </A> <A href="#@net:n705">n705</A> (to <A href="#@net:RCLK_c">RCLK_c</A>)
--------
0.318 (49.4% logic, 50.6% route), 1 logic levels.
Clock Skew Details:
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:ROUTE, 0.413,86.PADDI,R5C4C.CLK,RCLK_c">Source Clock Path</A> RCLK to SLICE_101:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413<A href="#@net:RCLK_c:86.PADDI:R5C4C.CLK:0.413"> 86.PADDI to R5C4C.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:ROUTE, 0.413,86.PADDI,R5C4C.CLK,RCLK_c">Destination Clock Path</A> RCLK to SLICE_101:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413<A href="#@net:RCLK_c:86.PADDI:R5C4C.CLK:0.413"> 86.PADDI to R5C4C.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000>
Passed: The following path meets requirements by 0.339ns
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_81">IS_FSM__i4</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: FF Data in <A href="#@comp:SLICE_81">IS_FSM__i5</A> (to <A href="#@net:RCLK_c">RCLK_c</A> +)
Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels.
Constraint Details:
0.318ns physical path delay SLICE_81 to SLICE_81 meets
-0.021ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.021ns) by 0.339ns
Physical Path Details:
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:REG_DEL, 0.157,R4C4C.CLK,R4C4C.Q0,SLICE_81:ROUTE, 0.161,R4C4C.Q0,R4C4C.M1,n703">Data path</A> SLICE_81 to SLICE_81:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R4C4C.CLK to R4C4C.Q0 <A href="#@comp:SLICE_81">SLICE_81</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 1 0.161<A href="#@net:n703:R4C4C.Q0:R4C4C.M1:0.161"> R4C4C.Q0 to R4C4C.M1 </A> <A href="#@net:n703">n703</A> (to <A href="#@net:RCLK_c">RCLK_c</A>)
--------
0.318 (49.4% logic, 50.6% route), 1 logic levels.
Clock Skew Details:
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:ROUTE, 0.413,86.PADDI,R4C4C.CLK,RCLK_c">Source Clock Path</A> RCLK to SLICE_81:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413<A href="#@net:RCLK_c:86.PADDI:R4C4C.CLK:0.413"> 86.PADDI to R4C4C.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:ROUTE, 0.413,86.PADDI,R4C4C.CLK,RCLK_c">Destination Clock Path</A> RCLK to SLICE_81:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413<A href="#@net:RCLK_c:86.PADDI:R4C4C.CLK:0.413"> 86.PADDI to R4C4C.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000>
Passed: The following path meets requirements by 0.339ns
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_84">IS_FSM__i12</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: FF Data in <A href="#@comp:SLICE_84">IS_FSM__i13</A> (to <A href="#@net:RCLK_c">RCLK_c</A> +)
Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels.
Constraint Details:
0.318ns physical path delay SLICE_84 to SLICE_84 meets
-0.021ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.021ns) by 0.339ns
Physical Path Details:
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:REG_DEL, 0.157,R5C4D.CLK,R5C4D.Q0,SLICE_84:ROUTE, 0.161,R5C4D.Q0,R5C4D.M1,n695">Data path</A> SLICE_84 to SLICE_84:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R5C4D.CLK to R5C4D.Q0 <A href="#@comp:SLICE_84">SLICE_84</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 1 0.161<A href="#@net:n695:R5C4D.Q0:R5C4D.M1:0.161"> R5C4D.Q0 to R5C4D.M1 </A> <A href="#@net:n695">n695</A> (to <A href="#@net:RCLK_c">RCLK_c</A>)
--------
0.318 (49.4% logic, 50.6% route), 1 logic levels.
Clock Skew Details:
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:ROUTE, 0.413,86.PADDI,R5C4D.CLK,RCLK_c">Source Clock Path</A> RCLK to SLICE_84:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413<A href="#@net:RCLK_c:86.PADDI:R5C4D.CLK:0.413"> 86.PADDI to R5C4D.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:ROUTE, 0.413,86.PADDI,R5C4D.CLK,RCLK_c">Destination Clock Path</A> RCLK to SLICE_84:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413<A href="#@net:RCLK_c:86.PADDI:R5C4D.CLK:0.413"> 86.PADDI to R5C4D.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000>
Passed: The following path meets requirements by 0.339ns
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_95">IS_FSM__i8</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: FF Data in <A href="#@comp:SLICE_95">IS_FSM__i9</A> (to <A href="#@net:RCLK_c">RCLK_c</A> +)
Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels.
Constraint Details:
0.318ns physical path delay SLICE_95 to SLICE_95 meets
-0.021ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.021ns) by 0.339ns
Physical Path Details:
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:REG_DEL, 0.157,R6C2A.CLK,R6C2A.Q0,SLICE_95:ROUTE, 0.161,R6C2A.Q0,R6C2A.M1,n699">Data path</A> SLICE_95 to SLICE_95:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R6C2A.CLK to R6C2A.Q0 <A href="#@comp:SLICE_95">SLICE_95</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 1 0.161<A href="#@net:n699:R6C2A.Q0:R6C2A.M1:0.161"> R6C2A.Q0 to R6C2A.M1 </A> <A href="#@net:n699">n699</A> (to <A href="#@net:RCLK_c">RCLK_c</A>)
--------
0.318 (49.4% logic, 50.6% route), 1 logic levels.
Clock Skew Details:
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:ROUTE, 0.413,86.PADDI,R6C2A.CLK,RCLK_c">Source Clock Path</A> RCLK to SLICE_95:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413<A href="#@net:RCLK_c:86.PADDI:R6C2A.CLK:0.413"> 86.PADDI to R6C2A.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:ROUTE, 0.413,86.PADDI,R6C2A.CLK,RCLK_c">Destination Clock Path</A> RCLK to SLICE_95:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413<A href="#@net:RCLK_c:86.PADDI:R6C2A.CLK:0.413"> 86.PADDI to R6C2A.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000>
Passed: The following path meets requirements by 0.339ns
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_96">IS_FSM__i11</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: FF Data in <A href="#@comp:SLICE_84">IS_FSM__i12</A> (to <A href="#@net:RCLK_c">RCLK_c</A> +)
Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels.
Constraint Details:
0.318ns physical path delay SLICE_96 to SLICE_84 meets
-0.021ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.021ns) by 0.339ns
Physical Path Details:
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:REG_DEL, 0.157,R5C4A.CLK,R5C4A.Q1,SLICE_96:ROUTE, 0.161,R5C4A.Q1,R5C4D.M0,n696">Data path</A> SLICE_96 to SLICE_84:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R5C4A.CLK to R5C4A.Q1 <A href="#@comp:SLICE_96">SLICE_96</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 1 0.161<A href="#@net:n696:R5C4A.Q1:R5C4D.M0:0.161"> R5C4A.Q1 to R5C4D.M0 </A> <A href="#@net:n696">n696</A> (to <A href="#@net:RCLK_c">RCLK_c</A>)
--------
0.318 (49.4% logic, 50.6% route), 1 logic levels.
Clock Skew Details:
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:ROUTE, 0.413,86.PADDI,R5C4A.CLK,RCLK_c">Source Clock Path</A> RCLK to SLICE_96:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413<A href="#@net:RCLK_c:86.PADDI:R5C4A.CLK:0.413"> 86.PADDI to R5C4A.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:ROUTE, 0.413,86.PADDI,R5C4D.CLK,RCLK_c">Destination Clock Path</A> RCLK to SLICE_84:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413<A href="#@net:RCLK_c:86.PADDI:R5C4D.CLK:0.413"> 86.PADDI to R5C4D.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000>
Passed: The following path meets requirements by 0.339ns
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_96">IS_FSM__i10</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: FF Data in <A href="#@comp:SLICE_96">IS_FSM__i11</A> (to <A href="#@net:RCLK_c">RCLK_c</A> +)
Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels.
Constraint Details:
0.318ns physical path delay SLICE_96 to SLICE_96 meets
-0.021ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.021ns) by 0.339ns
Physical Path Details:
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:REG_DEL, 0.157,R5C4A.CLK,R5C4A.Q0,SLICE_96:ROUTE, 0.161,R5C4A.Q0,R5C4A.M1,n697">Data path</A> SLICE_96 to SLICE_96:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R5C4A.CLK to R5C4A.Q0 <A href="#@comp:SLICE_96">SLICE_96</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 1 0.161<A href="#@net:n697:R5C4A.Q0:R5C4A.M1:0.161"> R5C4A.Q0 to R5C4A.M1 </A> <A href="#@net:n697">n697</A> (to <A href="#@net:RCLK_c">RCLK_c</A>)
--------
0.318 (49.4% logic, 50.6% route), 1 logic levels.
Clock Skew Details:
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:ROUTE, 0.413,86.PADDI,R5C4A.CLK,RCLK_c">Source Clock Path</A> RCLK to SLICE_96:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413<A href="#@net:RCLK_c:86.PADDI:R5C4A.CLK:0.413"> 86.PADDI to R5C4A.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:ROUTE, 0.413,86.PADDI,R5C4A.CLK,RCLK_c">Destination Clock Path</A> RCLK to SLICE_96:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413<A href="#@net:RCLK_c:86.PADDI:R5C4A.CLK:0.413"> 86.PADDI to R5C4A.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000>
Passed: The following path meets requirements by 0.339ns
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_97">PHI2r_344</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: FF Data in <A href="#@comp:SLICE_88">PHI2r2_345</A> (to <A href="#@net:RCLK_c">RCLK_c</A> +)
Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels.
Constraint Details:
0.318ns physical path delay SLICE_97 to SLICE_88 meets
-0.021ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.021ns) by 0.339ns
Physical Path Details:
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:REG_DEL, 0.157,R7C3C.CLK,R7C3C.Q1,SLICE_97:ROUTE, 0.161,R7C3C.Q1,R7C3B.M1,PHI2r">Data path</A> SLICE_97 to SLICE_88:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R7C3C.CLK to R7C3C.Q1 <A href="#@comp:SLICE_97">SLICE_97</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 1 0.161<A href="#@net:PHI2r:R7C3C.Q1:R7C3B.M1:0.161"> R7C3C.Q1 to R7C3B.M1 </A> <A href="#@net:PHI2r">PHI2r</A> (to <A href="#@net:RCLK_c">RCLK_c</A>)
--------
0.318 (49.4% logic, 50.6% route), 1 logic levels.
Clock Skew Details:
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:ROUTE, 0.413,86.PADDI,R7C3C.CLK,RCLK_c">Source Clock Path</A> RCLK to SLICE_97:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413<A href="#@net:RCLK_c:86.PADDI:R7C3C.CLK:0.413"> 86.PADDI to R7C3C.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:ROUTE, 0.413,86.PADDI,R7C3B.CLK,RCLK_c">Destination Clock Path</A> RCLK to SLICE_88:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413<A href="#@net:RCLK_c:86.PADDI:R7C3B.CLK:0.413"> 86.PADDI to R7C3B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000>
Passed: The following path meets requirements by 0.339ns
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_99">IS_FSM__i14</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: FF Data in <A href="#@comp:SLICE_99">IS_FSM__i15</A> (to <A href="#@net:RCLK_c">RCLK_c</A> +)
Delay: 0.318ns (49.4% logic, 50.6% route), 1 logic levels.
Constraint Details:
0.318ns physical path delay SLICE_99 to SLICE_99 meets
-0.021ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.021ns) by 0.339ns
Physical Path Details:
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:REG_DEL, 0.157,R3C5C.CLK,R3C5C.Q0,SLICE_99:ROUTE, 0.161,R3C5C.Q0,R3C5C.M1,n693">Data path</A> SLICE_99 to SLICE_99:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R3C5C.CLK to R3C5C.Q0 <A href="#@comp:SLICE_99">SLICE_99</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 1 0.161<A href="#@net:n693:R3C5C.Q0:R3C5C.M1:0.161"> R3C5C.Q0 to R3C5C.M1 </A> <A href="#@net:n693">n693</A> (to <A href="#@net:RCLK_c">RCLK_c</A>)
--------
0.318 (49.4% logic, 50.6% route), 1 logic levels.
Clock Skew Details:
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:ROUTE, 0.413,86.PADDI,R3C5C.CLK,RCLK_c">Source Clock Path</A> RCLK to SLICE_99:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413<A href="#@net:RCLK_c:86.PADDI:R3C5C.CLK:0.413"> 86.PADDI to R3C5C.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:ROUTE, 0.413,86.PADDI,R3C5C.CLK,RCLK_c">Destination Clock Path</A> RCLK to SLICE_99:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413<A href="#@net:RCLK_c:86.PADDI:R3C5C.CLK:0.413"> 86.PADDI to R3C5C.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000>
Passed: The following path meets requirements by 0.345ns
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_88">PHI2r2_345</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: FF Data in <A href="#@comp:SLICE_97">PHI2r3_346</A> (to <A href="#@net:RCLK_c">RCLK_c</A> +)
Delay: 0.324ns (48.5% logic, 51.5% route), 1 logic levels.
Constraint Details:
0.324ns physical path delay SLICE_88 to SLICE_97 meets
-0.021ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.021ns) by 0.345ns
Physical Path Details:
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:REG_DEL, 0.157,R7C3B.CLK,R7C3B.Q1,SLICE_88:ROUTE, 0.167,R7C3B.Q1,R7C3C.M0,PHI2r2">Data path</A> SLICE_88 to SLICE_97:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R7C3B.CLK to R7C3B.Q1 <A href="#@comp:SLICE_88">SLICE_88</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 3 0.167<A href="#@net:PHI2r2:R7C3B.Q1:R7C3C.M0:0.167"> R7C3B.Q1 to R7C3C.M0 </A> <A href="#@net:PHI2r2">PHI2r2</A> (to <A href="#@net:RCLK_c">RCLK_c</A>)
--------
0.324 (48.5% logic, 51.5% route), 1 logic levels.
Clock Skew Details:
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:ROUTE, 0.413,86.PADDI,R7C3B.CLK,RCLK_c">Source Clock Path</A> RCLK to SLICE_88:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413<A href="#@net:RCLK_c:86.PADDI:R7C3B.CLK:0.413"> 86.PADDI to R7C3B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:ROUTE, 0.413,86.PADDI,R7C3C.CLK,RCLK_c">Destination Clock Path</A> RCLK to SLICE_97:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413<A href="#@net:RCLK_c:86.PADDI:R7C3C.CLK:0.413"> 86.PADDI to R7C3C.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
<font color=#000000>
Passed: The following path meets requirements by 0.345ns
</font>
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_99">IS_FSM__i15</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: FF Data in <A href="#@comp:SLICE_87">IS_FSM__i0</A> (to <A href="#@net:RCLK_c">RCLK_c</A> +)
Delay: 0.324ns (48.5% logic, 51.5% route), 1 logic levels.
Constraint Details:
0.324ns physical path delay SLICE_99 to SLICE_87 meets
-0.021ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.021ns) by 0.345ns
Physical Path Details:
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:REG_DEL, 0.157,R3C5C.CLK,R3C5C.Q1,SLICE_99:ROUTE, 0.167,R3C5C.Q1,R3C5A.M0,Ready_N_272">Data path</A> SLICE_99 to SLICE_87:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R3C5C.CLK to R3C5C.Q1 <A href="#@comp:SLICE_99">SLICE_99</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 2 0.167<A href="#@net:Ready_N_272:R3C5C.Q1:R3C5A.M0:0.167"> R3C5C.Q1 to R3C5A.M0 </A> <A href="#@net:Ready_N_272">Ready_N_272</A> (to <A href="#@net:RCLK_c">RCLK_c</A>)
--------
0.324 (48.5% logic, 51.5% route), 1 logic levels.
Clock Skew Details:
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:ROUTE, 0.413,86.PADDI,R3C5C.CLK,RCLK_c">Source Clock Path</A> RCLK to SLICE_99:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413<A href="#@net:RCLK_c:86.PADDI:R3C5C.CLK:0.413"> 86.PADDI to R3C5C.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
<A href="#@path:PERIOD NET 'RCLK_c' 15.000000 ns ;:ROUTE, 0.413,86.PADDI,R3C5A.CLK,RCLK_c">Destination Clock Path</A> RCLK to SLICE_87:
Name Fanout Delay (ns) Site Resource
ROUTE 39 0.413<A href="#@net:RCLK_c:86.PADDI:R3C5A.CLK:0.413"> 86.PADDI to R3C5A.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
0.413 (0.0% logic, 100.0% route), 0 logic levels.
</A><A name="CLOCK_TO_OUT PORT 'RD[0]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'Dout[0]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[0]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'Dout[7]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[7]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'Dout[6]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[6]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'Dout[5]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[5]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'Dout[4]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[4]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'Dout[3]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[3]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'Dout[2]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[2]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'Dout[1]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "Dout[1]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'RBA[1]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'RBA[0]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'RA[11]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'RA[10]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.220ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_55">RA10_368</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:RA[10]">RA[10]</A>
Data Path Delay: 1.733ns (73.0% logic, 27.0% route), 2 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_55 and
1.733ns delay SLICE_55 to RA[10] (totaling 2.220ns) meets
0.000ns hold offset RCLK to RA[10] by 2.220ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'RA[10]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.264,86.PAD,86.PADDI,RCLK:ROUTE, 0.223,86.PADDI,R2C4B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_55:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 0.223<A href="#@net:RCLK_c:86.PADDI:R2C4B.CLK:0.223"> 86.PADDI to R2C4B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'RA[10]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.157,R2C4B.CLK,R2C4B.Q0,SLICE_55:ROUTE, 0.468,R2C4B.Q0,87.PADDO,n974:DOPAD_DEL, 1.108,87.PADDO,87.PAD,RA[10]">Data path</A> SLICE_55 to RA[10]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R2C4B.CLK to R2C4B.Q0 <A href="#@comp:SLICE_55">SLICE_55</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 1 0.468<A href="#@net:n974:R2C4B.Q0:87.PADDO:0.468"> R2C4B.Q0 to 87.PADDO </A> <A href="#@net:n974">n974</A>
DOPAD_DEL --- 1.108 87.PADDO to 87.PAD <A href="#@comp:RA[10]">RA[10]</A>
--------
1.733 (73.0% logic, 27.0% route), 2 logic levels.
Report: 2.220ns is the maximum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'RA[9]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.805ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:RA[9]">RA[9]</A>
Data Path Delay: 2.318ns (58.5% logic, 41.5% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
2.318ns delay SLICE_64 to RA[9] (totaling 2.805ns) meets
0.000ns hold offset RCLK to RA[9] by 2.805ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'RA[9]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.264,86.PAD,86.PADDI,RCLK:ROUTE, 0.223,86.PADDI,R7C2B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 0.223<A href="#@net:RCLK_c:86.PADDI:R7C2B.CLK:0.223"> 86.PADDI to R7C2B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'RA[9]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.157,R7C2B.CLK,R7C2B.Q0,SLICE_64:ROUTE, 0.469,R7C2B.Q0,R3C5A.D1,nRowColSel:CTOF_DEL, 0.092,R3C5A.D1,R3C5A.F1,SLICE_87:ROUTE, 0.492,R3C5A.F1,85.PADDO,RA_c_9:DOPAD_DEL, 1.108,85.PADDO,85.PAD,RA[9]">Data path</A> SLICE_64 to RA[9]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R7C2B.CLK to R7C2B.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 13 0.469<A href="#@net:nRowColSel:R7C2B.Q0:R3C5A.D1:0.469"> R7C2B.Q0 to R3C5A.D1 </A> <A href="#@net:nRowColSel">nRowColSel</A>
CTOF_DEL --- 0.092 R3C5A.D1 to R3C5A.F1 <A href="#@comp:SLICE_87">SLICE_87</A>
ROUTE 1 0.492<A href="#@net:RA_c_9:R3C5A.F1:85.PADDO:0.492"> R3C5A.F1 to 85.PADDO </A> <A href="#@net:RA_c_9">RA_c_9</A>
DOPAD_DEL --- 1.108 85.PADDO to 85.PAD <A href="#@comp:RA[9]">RA[9]</A>
--------
2.318 (58.5% logic, 41.5% route), 3 logic levels.
Report: 2.805ns is the maximum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'RA[8]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.476ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:RA[8]">RA[8]</A>
Data Path Delay: 1.989ns (68.2% logic, 31.8% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
1.989ns delay SLICE_64 to RA[8] (totaling 2.476ns) meets
0.000ns hold offset RCLK to RA[8] by 2.476ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'RA[8]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.264,86.PAD,86.PADDI,RCLK:ROUTE, 0.223,86.PADDI,R7C2B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 0.223<A href="#@net:RCLK_c:86.PADDI:R7C2B.CLK:0.223"> 86.PADDI to R7C2B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'RA[8]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.157,R7C2B.CLK,R7C2B.Q0,SLICE_64:ROUTE, 0.435,R7C2B.Q0,R2C2C.D0,nRowColSel:CTOF_DEL, 0.092,R2C2C.D0,R2C2C.F0,SLICE_98:ROUTE, 0.197,R2C2C.F0,96.PADDO,RA_c_8:DOPAD_DEL, 1.108,96.PADDO,96.PAD,RA[8]">Data path</A> SLICE_64 to RA[8]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R7C2B.CLK to R7C2B.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 13 0.435<A href="#@net:nRowColSel:R7C2B.Q0:R2C2C.D0:0.435"> R7C2B.Q0 to R2C2C.D0 </A> <A href="#@net:nRowColSel">nRowColSel</A>
CTOF_DEL --- 0.092 R2C2C.D0 to R2C2C.F0 <A href="#@comp:SLICE_98">SLICE_98</A>
ROUTE 1 0.197<A href="#@net:RA_c_8:R2C2C.F0:96.PADDO:0.197"> R2C2C.F0 to 96.PADDO </A> <A href="#@net:RA_c_8">RA_c_8</A>
DOPAD_DEL --- 1.108 96.PADDO to 96.PAD <A href="#@comp:RA[8]">RA[8]</A>
--------
1.989 (68.2% logic, 31.8% route), 3 logic levels.
Report: 2.476ns is the maximum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'RA[7]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.460ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:RA[7]">RA[7]</A>
Data Path Delay: 1.973ns (68.8% logic, 31.2% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
1.973ns delay SLICE_64 to RA[7] (totaling 2.460ns) meets
0.000ns hold offset RCLK to RA[7] by 2.460ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'RA[7]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.264,86.PAD,86.PADDI,RCLK:ROUTE, 0.223,86.PADDI,R7C2B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 0.223<A href="#@net:RCLK_c:86.PADDI:R7C2B.CLK:0.223"> 86.PADDI to R7C2B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'RA[7]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.157,R7C2B.CLK,R7C2B.Q0,SLICE_64:ROUTE, 0.222,R7C2B.Q0,R7C2B.C1,nRowColSel:CTOF_DEL, 0.092,R7C2B.C1,R7C2B.F1,SLICE_64:ROUTE, 0.394,R7C2B.F1,100.PADDO,RA_c_7:DOPAD_DEL, 1.108,100.PADDO,100.PAD,RA[7]">Data path</A> SLICE_64 to RA[7]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R7C2B.CLK to R7C2B.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 13 0.222<A href="#@net:nRowColSel:R7C2B.Q0:R7C2B.C1:0.222"> R7C2B.Q0 to R7C2B.C1 </A> <A href="#@net:nRowColSel">nRowColSel</A>
CTOF_DEL --- 0.092 R7C2B.C1 to R7C2B.F1 <A href="#@comp:SLICE_64">SLICE_64</A>
ROUTE 1 0.394<A href="#@net:RA_c_7:R7C2B.F1:100.PADDO:0.394"> R7C2B.F1 to 100.PADDO </A> <A href="#@net:RA_c_7">RA_c_7</A>
DOPAD_DEL --- 1.108 100.PADDO to 100.PAD <A href="#@comp:RA[7]">RA[7]</A>
--------
1.973 (68.8% logic, 31.2% route), 3 logic levels.
Report: 2.460ns is the maximum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'RA[6]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.759ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:RA[6]">RA[6]</A>
Data Path Delay: 2.272ns (59.7% logic, 40.3% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
2.272ns delay SLICE_64 to RA[6] (totaling 2.759ns) meets
0.000ns hold offset RCLK to RA[6] by 2.759ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'RA[6]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.264,86.PAD,86.PADDI,RCLK:ROUTE, 0.223,86.PADDI,R7C2B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 0.223<A href="#@net:RCLK_c:86.PADDI:R7C2B.CLK:0.223"> 86.PADDI to R7C2B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'RA[6]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.157,R7C2B.CLK,R7C2B.Q0,SLICE_64:ROUTE, 0.435,R7C2B.Q0,R2C2C.D1,nRowColSel:CTOF_DEL, 0.092,R2C2C.D1,R2C2C.F1,SLICE_98:ROUTE, 0.480,R2C2C.F1,91.PADDO,RA_c_6:DOPAD_DEL, 1.108,91.PADDO,91.PAD,RA[6]">Data path</A> SLICE_64 to RA[6]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R7C2B.CLK to R7C2B.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 13 0.435<A href="#@net:nRowColSel:R7C2B.Q0:R2C2C.D1:0.435"> R7C2B.Q0 to R2C2C.D1 </A> <A href="#@net:nRowColSel">nRowColSel</A>
CTOF_DEL --- 0.092 R2C2C.D1 to R2C2C.F1 <A href="#@comp:SLICE_98">SLICE_98</A>
ROUTE 1 0.480<A href="#@net:RA_c_6:R2C2C.F1:91.PADDO:0.480"> R2C2C.F1 to 91.PADDO </A> <A href="#@net:RA_c_6">RA_c_6</A>
DOPAD_DEL --- 1.108 91.PADDO to 91.PAD <A href="#@comp:RA[6]">RA[6]</A>
--------
2.272 (59.7% logic, 40.3% route), 3 logic levels.
Report: 2.759ns is the maximum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'RA[5]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.516ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:RA[5]">RA[5]</A>
Data Path Delay: 2.029ns (66.9% logic, 33.1% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
2.029ns delay SLICE_64 to RA[5] (totaling 2.516ns) meets
0.000ns hold offset RCLK to RA[5] by 2.516ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'RA[5]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.264,86.PAD,86.PADDI,RCLK:ROUTE, 0.223,86.PADDI,R7C2B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 0.223<A href="#@net:RCLK_c:86.PADDI:R7C2B.CLK:0.223"> 86.PADDI to R7C2B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'RA[5]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.157,R7C2B.CLK,R7C2B.Q0,SLICE_64:ROUTE, 0.278,R7C2B.Q0,R6C2A.A1,nRowColSel:CTOF_DEL, 0.092,R6C2A.A1,R6C2A.F1,SLICE_95:ROUTE, 0.394,R6C2A.F1,95.PADDO,RA_c_5:DOPAD_DEL, 1.108,95.PADDO,95.PAD,RA[5]">Data path</A> SLICE_64 to RA[5]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R7C2B.CLK to R7C2B.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 13 0.278<A href="#@net:nRowColSel:R7C2B.Q0:R6C2A.A1:0.278"> R7C2B.Q0 to R6C2A.A1 </A> <A href="#@net:nRowColSel">nRowColSel</A>
CTOF_DEL --- 0.092 R6C2A.A1 to R6C2A.F1 <A href="#@comp:SLICE_95">SLICE_95</A>
ROUTE 1 0.394<A href="#@net:RA_c_5:R6C2A.F1:95.PADDO:0.394"> R6C2A.F1 to 95.PADDO </A> <A href="#@net:RA_c_5">RA_c_5</A>
DOPAD_DEL --- 1.108 95.PADDO to 95.PAD <A href="#@comp:RA[5]">RA[5]</A>
--------
2.029 (66.9% logic, 33.1% route), 3 logic levels.
Report: 2.516ns is the maximum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'RA[4]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.635ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:RA[4]">RA[4]</A>
Data Path Delay: 2.148ns (63.2% logic, 36.8% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
2.148ns delay SLICE_64 to RA[4] (totaling 2.635ns) meets
0.000ns hold offset RCLK to RA[4] by 2.635ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'RA[4]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.264,86.PAD,86.PADDI,RCLK:ROUTE, 0.223,86.PADDI,R7C2B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 0.223<A href="#@net:RCLK_c:86.PADDI:R7C2B.CLK:0.223"> 86.PADDI to R7C2B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'RA[4]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.157,R7C2B.CLK,R7C2B.Q0,SLICE_64:ROUTE, 0.435,R7C2B.Q0,R2C2B.D1,nRowColSel:CTOF_DEL, 0.092,R2C2B.D1,R2C2B.F1,SLICE_93:ROUTE, 0.356,R2C2B.F1,99.PADDO,RA_c_4:DOPAD_DEL, 1.108,99.PADDO,99.PAD,RA[4]">Data path</A> SLICE_64 to RA[4]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R7C2B.CLK to R7C2B.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 13 0.435<A href="#@net:nRowColSel:R7C2B.Q0:R2C2B.D1:0.435"> R7C2B.Q0 to R2C2B.D1 </A> <A href="#@net:nRowColSel">nRowColSel</A>
CTOF_DEL --- 0.092 R2C2B.D1 to R2C2B.F1 <A href="#@comp:SLICE_93">SLICE_93</A>
ROUTE 1 0.356<A href="#@net:RA_c_4:R2C2B.F1:99.PADDO:0.356"> R2C2B.F1 to 99.PADDO </A> <A href="#@net:RA_c_4">RA_c_4</A>
DOPAD_DEL --- 1.108 99.PADDO to 99.PAD <A href="#@comp:RA[4]">RA[4]</A>
--------
2.148 (63.2% logic, 36.8% route), 3 logic levels.
Report: 2.635ns is the maximum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'RA[3]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.758ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:RA[3]">RA[3]</A>
Data Path Delay: 2.271ns (59.8% logic, 40.2% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
2.271ns delay SLICE_64 to RA[3] (totaling 2.758ns) meets
0.000ns hold offset RCLK to RA[3] by 2.758ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'RA[3]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.264,86.PAD,86.PADDI,RCLK:ROUTE, 0.223,86.PADDI,R7C2B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 0.223<A href="#@net:RCLK_c:86.PADDI:R7C2B.CLK:0.223"> 86.PADDI to R7C2B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'RA[3]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.157,R7C2B.CLK,R7C2B.Q0,SLICE_64:ROUTE, 0.446,R7C2B.Q0,R2C3B.D1,nRowColSel:CTOF_DEL, 0.092,R2C3B.D1,R2C3B.F1,SLICE_92:ROUTE, 0.468,R2C3B.F1,97.PADDO,RA_c_3:DOPAD_DEL, 1.108,97.PADDO,97.PAD,RA[3]">Data path</A> SLICE_64 to RA[3]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R7C2B.CLK to R7C2B.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 13 0.446<A href="#@net:nRowColSel:R7C2B.Q0:R2C3B.D1:0.446"> R7C2B.Q0 to R2C3B.D1 </A> <A href="#@net:nRowColSel">nRowColSel</A>
CTOF_DEL --- 0.092 R2C3B.D1 to R2C3B.F1 <A href="#@comp:SLICE_92">SLICE_92</A>
ROUTE 1 0.468<A href="#@net:RA_c_3:R2C3B.F1:97.PADDO:0.468"> R2C3B.F1 to 97.PADDO </A> <A href="#@net:RA_c_3">RA_c_3</A>
DOPAD_DEL --- 1.108 97.PADDO to 97.PAD <A href="#@comp:RA[3]">RA[3]</A>
--------
2.271 (59.8% logic, 40.2% route), 3 logic levels.
Report: 2.758ns is the maximum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'RA[2]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.487ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:RA[2]">RA[2]</A>
Data Path Delay: 2.000ns (67.8% logic, 32.1% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
2.000ns delay SLICE_64 to RA[2] (totaling 2.487ns) meets
0.000ns hold offset RCLK to RA[2] by 2.487ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'RA[2]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.264,86.PAD,86.PADDI,RCLK:ROUTE, 0.223,86.PADDI,R7C2B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 0.223<A href="#@net:RCLK_c:86.PADDI:R7C2B.CLK:0.223"> 86.PADDI to R7C2B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'RA[2]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.157,R7C2B.CLK,R7C2B.Q0,SLICE_64:ROUTE, 0.446,R7C2B.Q0,R2C3A.D0,nRowColSel:CTOF_DEL, 0.092,R2C3A.D0,R2C3A.F0,SLICE_90:ROUTE, 0.197,R2C3A.F0,94.PADDO,RA_c_2:DOPAD_DEL, 1.108,94.PADDO,94.PAD,RA[2]">Data path</A> SLICE_64 to RA[2]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R7C2B.CLK to R7C2B.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 13 0.446<A href="#@net:nRowColSel:R7C2B.Q0:R2C3A.D0:0.446"> R7C2B.Q0 to R2C3A.D0 </A> <A href="#@net:nRowColSel">nRowColSel</A>
CTOF_DEL --- 0.092 R2C3A.D0 to R2C3A.F0 <A href="#@comp:SLICE_90">SLICE_90</A>
ROUTE 1 0.197<A href="#@net:RA_c_2:R2C3A.F0:94.PADDO:0.197"> R2C3A.F0 to 94.PADDO </A> <A href="#@net:RA_c_2">RA_c_2</A>
DOPAD_DEL --- 1.108 94.PADDO to 94.PAD <A href="#@comp:RA[2]">RA[2]</A>
--------
2.000 (67.8% logic, 32.1% route), 3 logic levels.
Report: 2.487ns is the maximum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'RA[1]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.487ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:RA[1]">RA[1]</A>
Data Path Delay: 2.000ns (67.8% logic, 32.1% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
2.000ns delay SLICE_64 to RA[1] (totaling 2.487ns) meets
0.000ns hold offset RCLK to RA[1] by 2.487ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'RA[1]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.264,86.PAD,86.PADDI,RCLK:ROUTE, 0.223,86.PADDI,R7C2B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 0.223<A href="#@net:RCLK_c:86.PADDI:R7C2B.CLK:0.223"> 86.PADDI to R7C2B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'RA[1]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.157,R7C2B.CLK,R7C2B.Q0,SLICE_64:ROUTE, 0.446,R7C2B.Q0,R2C3B.D0,nRowColSel:CTOF_DEL, 0.092,R2C3B.D0,R2C3B.F0,SLICE_92:ROUTE, 0.197,R2C3B.F0,89.PADDO,RA_c_1:DOPAD_DEL, 1.108,89.PADDO,89.PAD,RA[1]">Data path</A> SLICE_64 to RA[1]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R7C2B.CLK to R7C2B.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 13 0.446<A href="#@net:nRowColSel:R7C2B.Q0:R2C3B.D0:0.446"> R7C2B.Q0 to R2C3B.D0 </A> <A href="#@net:nRowColSel">nRowColSel</A>
CTOF_DEL --- 0.092 R2C3B.D0 to R2C3B.F0 <A href="#@comp:SLICE_92">SLICE_92</A>
ROUTE 1 0.197<A href="#@net:RA_c_1:R2C3B.F0:89.PADDO:0.197"> R2C3B.F0 to 89.PADDO </A> <A href="#@net:RA_c_1">RA_c_1</A>
DOPAD_DEL --- 1.108 89.PADDO to 89.PAD <A href="#@comp:RA[1]">RA[1]</A>
--------
2.000 (67.8% logic, 32.1% route), 3 logic levels.
Report: 2.487ns is the maximum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'RA[0]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.476ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:RA[0]">RA[0]</A>
Data Path Delay: 1.989ns (68.2% logic, 31.8% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
1.989ns delay SLICE_64 to RA[0] (totaling 2.476ns) meets
0.000ns hold offset RCLK to RA[0] by 2.476ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'RA[0]' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.264,86.PAD,86.PADDI,RCLK:ROUTE, 0.223,86.PADDI,R7C2B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 0.223<A href="#@net:RCLK_c:86.PADDI:R7C2B.CLK:0.223"> 86.PADDI to R7C2B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'RA[0]' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.157,R7C2B.CLK,R7C2B.Q0,SLICE_64:ROUTE, 0.435,R7C2B.Q0,R2C2B.D0,nRowColSel:CTOF_DEL, 0.092,R2C2B.D0,R2C2B.F0,SLICE_93:ROUTE, 0.197,R2C2B.F0,98.PADDO,RA_c_0:DOPAD_DEL, 1.108,98.PADDO,98.PAD,RA[0]">Data path</A> SLICE_64 to RA[0]:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R7C2B.CLK to R7C2B.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 13 0.435<A href="#@net:nRowColSel:R7C2B.Q0:R2C2B.D0:0.435"> R7C2B.Q0 to R2C2B.D0 </A> <A href="#@net:nRowColSel">nRowColSel</A>
CTOF_DEL --- 0.092 R2C2B.D0 to R2C2B.F0 <A href="#@comp:SLICE_93">SLICE_93</A>
ROUTE 1 0.197<A href="#@net:RA_c_0:R2C2B.F0:98.PADDO:0.197"> R2C2B.F0 to 98.PADDO </A> <A href="#@net:RA_c_0">RA_c_0</A>
DOPAD_DEL --- 1.108 98.PADDO to 98.PAD <A href="#@comp:RA[0]">RA[0]</A>
--------
1.989 (68.2% logic, 31.8% route), 3 logic levels.
Report: 2.476ns is the maximum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'nRCS' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "nRCS" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 1.949ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_60">nRCS_364</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:nRCS">nRCS</A>
Data Path Delay: 1.462ns (86.5% logic, 13.5% route), 2 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_60 and
1.462ns delay SLICE_60 to nRCS (totaling 1.949ns) meets
0.000ns hold offset RCLK to nRCS by 1.949ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'nRCS' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.264,86.PAD,86.PADDI,RCLK:ROUTE, 0.223,86.PADDI,R2C5B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_60:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 0.223<A href="#@net:RCLK_c:86.PADDI:R2C5B.CLK:0.223"> 86.PADDI to R2C5B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'nRCS' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.157,R2C5B.CLK,R2C5B.Q0,SLICE_60:ROUTE, 0.197,R2C5B.Q0,77.PADDO,nRCS_c:DOPAD_DEL, 1.108,77.PADDO,77.PAD,nRCS">Data path</A> SLICE_60 to nRCS:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R2C5B.CLK to R2C5B.Q0 <A href="#@comp:SLICE_60">SLICE_60</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 1 0.197<A href="#@net:nRCS_c:R2C5B.Q0:77.PADDO:0.197"> R2C5B.Q0 to 77.PADDO </A> <A href="#@net:nRCS_c">nRCS_c</A>
DOPAD_DEL --- 1.108 77.PADDO to 77.PAD <A href="#@comp:nRCS">nRCS</A>
--------
1.462 (86.5% logic, 13.5% route), 2 logic levels.
Report: 1.949ns is the maximum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'RCKE' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RCKE" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.252ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_34">RCKE_363</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:RCKE">RCKE</A>
Data Path Delay: 1.765ns (71.7% logic, 28.3% route), 2 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_34 and
1.765ns delay SLICE_34 to RCKE (totaling 2.252ns) meets
0.000ns hold offset RCLK to RCKE by 2.252ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'RCKE' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.264,86.PAD,86.PADDI,RCLK:ROUTE, 0.223,86.PADDI,R6C5B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_34:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 0.223<A href="#@net:RCLK_c:86.PADDI:R6C5B.CLK:0.223"> 86.PADDI to R6C5B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'RCKE' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.157,R6C5B.CLK,R6C5B.Q0,SLICE_34:ROUTE, 0.500,R6C5B.Q0,82.PADDO,RCKE_c:DOPAD_DEL, 1.108,82.PADDO,82.PAD,RCKE">Data path</A> SLICE_34 to RCKE:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R6C5B.CLK to R6C5B.Q0 <A href="#@comp:SLICE_34">SLICE_34</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 4 0.500<A href="#@net:RCKE_c:R6C5B.Q0:82.PADDO:0.500"> R6C5B.Q0 to 82.PADDO </A> <A href="#@net:RCKE_c">RCKE_c</A>
DOPAD_DEL --- 1.108 82.PADDO to 82.PAD <A href="#@comp:RCKE">RCKE</A>
--------
1.765 (71.7% logic, 28.3% route), 2 logic levels.
Report: 2.252ns is the maximum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'nRWE' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "nRWE" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 1.949ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_63">nRWE_367</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:nRWE">nRWE</A>
Data Path Delay: 1.462ns (86.5% logic, 13.5% route), 2 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_63 and
1.462ns delay SLICE_63 to nRWE (totaling 1.949ns) meets
0.000ns hold offset RCLK to nRWE by 1.949ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'nRWE' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.264,86.PAD,86.PADDI,RCLK:ROUTE, 0.223,86.PADDI,R3C5B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_63:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 0.223<A href="#@net:RCLK_c:86.PADDI:R3C5B.CLK:0.223"> 86.PADDI to R3C5B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'nRWE' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.157,R3C5B.CLK,R3C5B.Q0,SLICE_63:ROUTE, 0.197,R3C5B.Q0,72.PADDO,nRWE_c:DOPAD_DEL, 1.108,72.PADDO,72.PAD,nRWE">Data path</A> SLICE_63 to nRWE:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R3C5B.CLK to R3C5B.Q0 <A href="#@comp:SLICE_63">SLICE_63</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 1 0.197<A href="#@net:nRWE_c:R3C5B.Q0:72.PADDO:0.197"> R3C5B.Q0 to 72.PADDO </A> <A href="#@net:nRWE_c">nRWE_c</A>
DOPAD_DEL --- 1.108 72.PADDO to 72.PAD <A href="#@comp:nRWE">nRWE</A>
--------
1.462 (86.5% logic, 13.5% route), 2 logic levels.
Report: 1.949ns is the maximum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'nRRAS' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.111ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_61">nRRAS_365</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:nRRAS">nRRAS</A>
Data Path Delay: 1.624ns (77.9% logic, 22.1% route), 2 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_61 and
1.624ns delay SLICE_61 to nRRAS (totaling 2.111ns) meets
0.000ns hold offset RCLK to nRRAS by 2.111ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'nRRAS' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.264,86.PAD,86.PADDI,RCLK:ROUTE, 0.223,86.PADDI,R2C4C.CLK,RCLK_c">Clock path</A> RCLK to SLICE_61:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 0.223<A href="#@net:RCLK_c:86.PADDI:R2C4C.CLK:0.223"> 86.PADDI to R2C4C.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'nRRAS' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.157,R2C4C.CLK,R2C4C.Q0,SLICE_61:ROUTE, 0.359,R2C4C.Q0,73.PADDO,nRRAS_c:DOPAD_DEL, 1.108,73.PADDO,73.PAD,nRRAS">Data path</A> SLICE_61 to nRRAS:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R2C4C.CLK to R2C4C.Q0 <A href="#@comp:SLICE_61">SLICE_61</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 2 0.359<A href="#@net:nRRAS_c:R2C4C.Q0:73.PADDO:0.359"> R2C4C.Q0 to 73.PADDO </A> <A href="#@net:nRRAS_c">nRRAS_c</A>
DOPAD_DEL --- 1.108 73.PADDO to 73.PAD <A href="#@comp:nRRAS">nRRAS</A>
--------
1.624 (77.9% logic, 22.1% route), 2 logic levels.
Report: 2.111ns is the maximum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'nRCAS' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.220ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_58">nRCAS_366</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:nRCAS">nRCAS</A>
Data Path Delay: 1.733ns (73.0% logic, 27.0% route), 2 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_58 and
1.733ns delay SLICE_58 to nRCAS (totaling 2.220ns) meets
0.000ns hold offset RCLK to nRCAS by 2.220ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'nRCAS' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.264,86.PAD,86.PADDI,RCLK:ROUTE, 0.223,86.PADDI,R2C4A.CLK,RCLK_c">Clock path</A> RCLK to SLICE_58:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 0.223<A href="#@net:RCLK_c:86.PADDI:R2C4A.CLK:0.223"> 86.PADDI to R2C4A.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'nRCAS' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.157,R2C4A.CLK,R2C4A.Q0,SLICE_58:ROUTE, 0.468,R2C4A.Q0,78.PADDO,nRCAS_c:DOPAD_DEL, 1.108,78.PADDO,78.PAD,nRCAS">Data path</A> SLICE_58 to nRCAS:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R2C4A.CLK to R2C4A.Q0 <A href="#@comp:SLICE_58">SLICE_58</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 1 0.468<A href="#@net:nRCAS_c:R2C4A.Q0:78.PADDO:0.468"> R2C4A.Q0 to 78.PADDO </A> <A href="#@net:nRCAS_c">nRCAS_c</A>
DOPAD_DEL --- 1.108 78.PADDO to 78.PAD <A href="#@comp:nRCAS">nRCAS</A>
--------
1.733 (73.0% logic, 27.0% route), 2 logic levels.
Report: 2.220ns is the maximum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'RDQMH' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.510ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:RDQMH">RDQMH</A>
Data Path Delay: 2.023ns (67.1% logic, 32.9% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
2.023ns delay SLICE_64 to RDQMH (totaling 2.510ns) meets
0.000ns hold offset RCLK to RDQMH by 2.510ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'RDQMH' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.264,86.PAD,86.PADDI,RCLK:ROUTE, 0.223,86.PADDI,R7C2B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 0.223<A href="#@net:RCLK_c:86.PADDI:R7C2B.CLK:0.223"> 86.PADDI to R7C2B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'RDQMH' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.157,R7C2B.CLK,R7C2B.Q0,SLICE_64:ROUTE, 0.469,R7C2B.Q0,R3C5A.D0,nRowColSel:CTOF_DEL, 0.092,R3C5A.D0,R3C5A.F0,SLICE_87:ROUTE, 0.197,R3C5A.F0,76.PADDO,RDQMH_c:DOPAD_DEL, 1.108,76.PADDO,76.PAD,RDQMH">Data path</A> SLICE_64 to RDQMH:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R7C2B.CLK to R7C2B.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 13 0.469<A href="#@net:nRowColSel:R7C2B.Q0:R3C5A.D0:0.469"> R7C2B.Q0 to R3C5A.D0 </A> <A href="#@net:nRowColSel">nRowColSel</A>
CTOF_DEL --- 0.092 R3C5A.D0 to R3C5A.F0 <A href="#@comp:SLICE_87">SLICE_87</A>
ROUTE 1 0.197<A href="#@net:RDQMH_c:R3C5A.F0:76.PADDO:0.197"> R3C5A.F0 to 76.PADDO </A> <A href="#@net:RDQMH_c">RDQMH_c</A>
DOPAD_DEL --- 1.108 76.PADDO to 76.PAD <A href="#@comp:RDQMH">RDQMH</A>
--------
2.023 (67.1% logic, 32.9% route), 3 logic levels.
Report: 2.510ns is the maximum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'RDQML' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RDQML" 12.500000 ns CLKPORT "RCLK" ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.602ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q <A href="#@comp:SLICE_64">nRowColSel_370</A> (from <A href="#@net:RCLK_c">RCLK_c</A> +)
Destination: Port Pad <A href="#@comp:RDQML">RDQML</A>
Data Path Delay: 2.115ns (64.2% logic, 35.8% route), 3 logic levels.
Clock Path Delay: 0.487ns (54.2% logic, 45.8% route), 1 logic levels.
Constraint Details:
0.487ns delay RCLK to SLICE_64 and
2.115ns delay SLICE_64 to RDQML (totaling 2.602ns) meets
0.000ns hold offset RCLK to RDQML by 2.602ns
Physical Path Details:
<A href="#@path:CLOCK_TO_OUT PORT 'RDQML' 12.500000 ns CLKPORT 'RCLK' ;:PADI_DEL, 0.264,86.PAD,86.PADDI,RCLK:ROUTE, 0.223,86.PADDI,R7C2B.CLK,RCLK_c">Clock path</A> RCLK to SLICE_64:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.264 86.PAD to 86.PADDI <A href="#@comp:RCLK">RCLK</A>
ROUTE 39 0.223<A href="#@net:RCLK_c:86.PADDI:R7C2B.CLK:0.223"> 86.PADDI to R7C2B.CLK </A> <A href="#@net:RCLK_c">RCLK_c</A>
--------
0.487 (54.2% logic, 45.8% route), 1 logic levels.
<A href="#@path:CLOCK_TO_OUT PORT 'RDQML' 12.500000 ns CLKPORT 'RCLK' ;:REG_DEL, 0.157,R7C2B.CLK,R7C2B.Q0,SLICE_64:ROUTE, 0.278,R7C2B.Q0,R6C2A.A0,nRowColSel:CTOF_DEL, 0.092,R6C2A.A0,R6C2A.F0,SLICE_95:ROUTE, 0.480,R6C2A.F0,61.PADDO,RDQML_c:DOPAD_DEL, 1.108,61.PADDO,61.PAD,RDQML">Data path</A> SLICE_64 to RDQML:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.157 R7C2B.CLK to R7C2B.Q0 <A href="#@comp:SLICE_64">SLICE_64</A> (from <A href="#@net:RCLK_c">RCLK_c</A>)
ROUTE 13 0.278<A href="#@net:nRowColSel:R7C2B.Q0:R6C2A.A0:0.278"> R7C2B.Q0 to R6C2A.A0 </A> <A href="#@net:nRowColSel">nRowColSel</A>
CTOF_DEL --- 0.092 R6C2A.A0 to R6C2A.F0 <A href="#@comp:SLICE_95">SLICE_95</A>
ROUTE 1 0.480<A href="#@net:RDQML_c:R6C2A.F0:61.PADDO:0.480"> R6C2A.F0 to 61.PADDO </A> <A href="#@net:RDQML_c">RDQML_c</A>
DOPAD_DEL --- 1.108 61.PADDO to 61.PAD <A href="#@comp:RDQML">RDQML</A>
--------
2.115 (64.2% logic, 35.8% route), 3 logic levels.
Report: 2.602ns is the maximum offset for this preference.
</A><A name="CLOCK_TO_OUT PORT 'RD[7]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'RD[6]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'RD[5]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'RD[4]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'RD[3]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'RD[2]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
</A><A name="CLOCK_TO_OUT PORT 'RD[1]' 12.500000 ns CLKPORT 'RCLK"></A>================================================================================
Preference: CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns CLKPORT "RCLK" ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
<A name="Report Summary"></A><B><U><big>Report Summary</big></U></B>
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
PERIOD NET "PHI2_c" 350.000000 ns ; | -| -| 2
| | |
PERIOD NET "nCCAS_c" 350.000000 ns ; | -| -| 0
| | |
PERIOD NET "nCRAS_c" 350.000000 ns ; | -| -| 0
| | |
PERIOD NET "RCLK_c" 15.000000 ns ; | -| -| 1
| | |
CLOCK_TO_OUT PORT "RD[0]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[0]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[7]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[6]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[5]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[4]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[3]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[2]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "Dout[1]" 12.500000 | | |
ns CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RBA[1]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RBA[0]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RA[11]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RA[10]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.220 ns| 2
| | |
CLOCK_TO_OUT PORT "RA[9]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.805 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[8]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.476 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[7]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.460 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[6]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.759 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[5]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.516 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[4]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.635 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[3]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.758 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[2]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.487 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[1]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.487 ns| 3
| | |
CLOCK_TO_OUT PORT "RA[0]" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.476 ns| 3
| | |
CLOCK_TO_OUT PORT "nRCS" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 1.949 ns| 2
| | |
CLOCK_TO_OUT PORT "RCKE" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.252 ns| 2
| | |
CLOCK_TO_OUT PORT "nRWE" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 1.949 ns| 2
| | |
CLOCK_TO_OUT PORT "nRRAS" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.111 ns| 2
| | |
CLOCK_TO_OUT PORT "nRCAS" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.220 ns| 2
| | |
CLOCK_TO_OUT PORT "RDQMH" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.510 ns| 3
| | |
CLOCK_TO_OUT PORT "RDQML" 12.500000 ns | | |
CLKPORT "RCLK" ; | 0.000 ns| 2.602 ns| 3
| | |
CLOCK_TO_OUT PORT "RD[7]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[6]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[5]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[4]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[3]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[2]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
CLOCK_TO_OUT PORT "RD[1]" 12.500000 ns | | |
CLKPORT "RCLK" ; | -| -| 0
| | |
----------------------------------------------------------------------------
All preferences were met.
<A name="Clock Domains Analysis"></A><B><U><big>Clock Domains Analysis</big></U></B>
------------------------
Found 4 clocks:
Clock Domain: <A href="#@net:nCRAS_c">nCRAS_c</A> Source: nCRAS.PAD Loads: 9
No transfer within this clock domain is found
Data transfers from:
Clock Domain: <A href="#@net:RCLK_c">RCLK_c</A> Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: <A href="#@net:nCCAS_c">nCCAS_c</A> Source: nCCAS.PAD Loads: 7
No transfer within this clock domain is found
Clock Domain: <A href="#@net:RCLK_c">RCLK_c</A> Source: RCLK.PAD Loads: 39
Covered under: PERIOD NET "RCLK_c" 15.000000 ns ;
Data transfers from:
Clock Domain: <A href="#@net:nCRAS_c">nCRAS_c</A> Source: nCRAS.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: <A href="#@net:PHI2_c">PHI2_c</A> Source: PHI2.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: <A href="#@net:PHI2_c">PHI2_c</A> Source: PHI2.PAD Loads: 14
Covered under: PERIOD NET "PHI2_c" 350.000000 ns ;
Data transfers from:
Clock Domain: <A href="#@net:RCLK_c">RCLK_c</A> Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 520 paths, 6 nets, and 436 connections (70.89% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
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