mirror of
https://github.com/garrettsworkshop/RAM2GS.git
synced 2024-11-28 21:49:21 +00:00
88 lines
1.4 KiB
Plaintext
88 lines
1.4 KiB
Plaintext
[Device]
|
|
Family=machxo2
|
|
PartType=LCMXO2-1200HC
|
|
PartName=LCMXO2-1200HC-4TG100C
|
|
SpeedGrade=4
|
|
Package=TQFP100
|
|
OperatingCondition=COM
|
|
Status=S
|
|
|
|
[IP]
|
|
VendorName=Lattice Semiconductor Corporation
|
|
CoreType=LPM
|
|
CoreStatus=Demo
|
|
CoreName=PLL
|
|
CoreRevision=5.8
|
|
ModuleName=RPLL
|
|
SourceFormat=Verilog HDL
|
|
ParameterFileVersion=1.0
|
|
Date=07/14/2024
|
|
Time=22:23:22
|
|
|
|
[Parameters]
|
|
Verilog=1
|
|
VHDL=0
|
|
EDIF=1
|
|
Destination=Synplicity
|
|
Expression=None
|
|
Order=None
|
|
IO=0
|
|
mode=Frequency
|
|
CLKI=133.0
|
|
CLKI_DIV=13
|
|
BW=0.955
|
|
VCO=491.077
|
|
fb_mode=CLKOP
|
|
CLKFB_DIV=6
|
|
FRACN_ENABLE=0
|
|
FRACN_DIV=0
|
|
DynamicPhase=STATIC
|
|
ClkEnable=0
|
|
Standby=0
|
|
Enable_sel=0
|
|
PLLRst=0
|
|
PLLMRst=0
|
|
ClkOS2Rst=0
|
|
ClkOS3Rst=0
|
|
LockSig=0
|
|
LockStk=0
|
|
WBProt=0
|
|
OPBypass=0
|
|
OPUseDiv=0
|
|
CLKOP_DIV=8
|
|
FREQ_PIN_CLKOP=61
|
|
OP_Tol=1.0
|
|
CLKOP_AFREQ=61.384615
|
|
CLKOP_PHASEADJ=0
|
|
CLKOP_TRIM_POL=Rising
|
|
CLKOP_TRIM_DELAY=0
|
|
EnCLKOS=0
|
|
OSBypass=0
|
|
OSUseDiv=0
|
|
CLKOS_DIV=1
|
|
FREQ_PIN_CLKOS=100
|
|
OS_Tol=0.0
|
|
CLKOS_AFREQ=
|
|
CLKOS_PHASEADJ=0
|
|
CLKOS_TRIM_POL=Rising
|
|
CLKOS_TRIM_DELAY=0
|
|
EnCLKOS2=0
|
|
OS2Bypass=0
|
|
OS2UseDiv=0
|
|
CLKOS2_DIV=1
|
|
FREQ_PIN_CLKOS2=100
|
|
OS2_Tol=0.0
|
|
CLKOS2_AFREQ=
|
|
CLKOS2_PHASEADJ=0
|
|
EnCLKOS3=0
|
|
OS3Bypass=0
|
|
OS3UseDiv=0
|
|
CLKOS3_DIV=1
|
|
FREQ_PIN_CLKOS3=100
|
|
OS3_Tol=0.0
|
|
CLKOS3_AFREQ=
|
|
CLKOS3_PHASEADJ=0
|
|
|
|
[Command]
|
|
cmd_line= -w -n RPLL -lang verilog -synth synplify -arch xo2c00 -type pll -fin 133.0 -fclkop 61 -fclkop_tol 1.0 -trimp 0 -phasep 0 -trimp_r -phase_cntl STATIC -fb_mode 1
|