mirror of
https://github.com/garrettsworkshop/RAM2GS.git
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135 lines
6.4 KiB
Plaintext
135 lines
6.4 KiB
Plaintext
Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
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Design name: RAM2GS
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NCD version: 3.3
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Vendor: LATTICE
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Device: LCMXO2-640HC
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Package: TQFP100
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Performance: 5
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Package Status: Final Version 1.39.
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Performance Hardware Data Status: Final Version 34.4.
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Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
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Design name: RAM2GS
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NCD version: 3.3
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Vendor: LATTICE
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Device: LCMXO2-640HC
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Package: TQFP100
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Performance: 6
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Package Status: Final Version 1.39.
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Performance Hardware Data Status: Final Version 34.4.
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Loading design for application iotiming from file ram2gs_lcmxo2_640hc_impl1.ncd.
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Design name: RAM2GS
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NCD version: 3.3
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Vendor: LATTICE
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Device: LCMXO2-640HC
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Package: TQFP100
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Performance: M
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Package Status: Final Version 1.39.
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Performance Hardware Data Status: Final Version 34.4.
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// Design: RAM2GS
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// Package: TQFP100
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// ncd File: ram2gs_lcmxo2_640hc_impl1.ncd
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// Version: Diamond (64-bit) 3.12.1.454
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// Written on Thu Sep 21 05:40:03 2023
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// M: Minimum Performance Grade
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// iotiming RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf -gui -msgset //Mac/iCloud/Repos/RAM2GS/CPLD/LCMXO2-640HC/promote.xml
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I/O Timing Report (All units are in ns)
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Worst Case Results across Performance Grades (M, 6, 5, 4):
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// Input Setup and Hold Times
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Port Clock Edge Setup Performance_Grade Hold Performance_Grade
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----------------------------------------------------------------------
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CROW[0] nCRAS F 2.429 4 -0.163 M
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CROW[1] nCRAS F 1.927 4 -0.005 M
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Din[0] PHI2 F 5.424 4 3.636 4
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Din[0] nCCAS F 1.913 4 -0.130 M
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Din[1] PHI2 F 5.162 4 3.516 4
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Din[1] nCCAS F 2.007 4 -0.156 M
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Din[2] PHI2 F 5.078 4 3.516 4
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Din[2] nCCAS F 0.876 4 0.346 4
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Din[3] PHI2 F 6.152 4 3.516 4
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Din[3] nCCAS F 0.245 4 0.869 4
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Din[4] PHI2 F 5.240 4 3.516 4
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Din[4] nCCAS F 0.714 4 0.460 4
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Din[5] PHI2 F 6.035 4 3.516 4
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Din[5] nCCAS F 0.751 4 0.419 4
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Din[6] PHI2 F 4.496 4 3.636 4
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Din[6] nCCAS F 1.518 4 -0.020 M
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Din[7] PHI2 F 4.936 4 3.636 4
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Din[7] nCCAS F 1.852 4 -0.081 M
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MAin[0] PHI2 F 5.207 4 0.531 4
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MAin[0] nCRAS F 1.658 4 0.036 M
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MAin[1] PHI2 F 3.450 4 0.460 4
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MAin[1] nCRAS F 2.014 4 -0.043 M
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MAin[2] PHI2 F 7.941 4 -0.604 M
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MAin[2] nCRAS F 1.001 4 0.498 4
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MAin[3] PHI2 F 8.770 4 -0.865 M
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MAin[3] nCRAS F 2.190 4 -0.151 M
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MAin[4] PHI2 F 9.575 4 -1.072 M
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MAin[4] nCRAS F 1.331 4 0.186 4
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MAin[5] PHI2 F 9.093 4 -0.925 M
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MAin[5] nCRAS F 1.329 4 0.186 4
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MAin[6] PHI2 F 9.450 4 -1.036 M
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MAin[6] nCRAS F 1.323 4 0.191 4
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MAin[7] PHI2 F 8.247 4 -0.706 M
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MAin[7] nCRAS F 1.258 4 0.267 4
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MAin[8] nCRAS F 0.994 4 0.504 4
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MAin[9] nCRAS F 0.614 4 0.830 4
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PHI2 RCLK R -0.005 M 2.116 4
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nCCAS RCLK R 3.191 4 -0.531 M
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nCCAS nCRAS F 3.195 4 -0.341 M
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nCRAS RCLK R 2.797 4 -0.402 M
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nFWE PHI2 F 8.238 4 -0.666 M
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nFWE nCRAS F 1.140 4 0.400 4
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// Clock to Output Delay
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Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade
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------------------------------------------------------------------------
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LED RCLK R 10.962 4 3.218 M
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LED nCRAS F 10.815 4 3.159 M
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RA[0] RCLK R 10.143 4 3.128 M
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RA[0] nCRAS F 11.178 4 3.358 M
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RA[10] RCLK R 7.578 4 2.578 M
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RA[11] PHI2 R 9.098 4 3.021 M
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RA[1] RCLK R 10.676 4 3.248 M
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RA[1] nCRAS F 11.215 4 3.370 M
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RA[2] RCLK R 11.199 4 3.402 M
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RA[2] nCRAS F 11.518 4 3.451 M
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RA[3] RCLK R 10.446 4 3.209 M
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RA[3] nCRAS F 11.264 4 3.364 M
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RA[4] RCLK R 10.446 4 3.209 M
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RA[4] nCRAS F 11.484 4 3.438 M
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RA[5] RCLK R 11.199 4 3.402 M
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RA[5] nCRAS F 11.264 4 3.364 M
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RA[6] RCLK R 11.424 4 3.444 M
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RA[6] nCRAS F 11.388 4 3.388 M
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RA[7] RCLK R 11.112 4 3.370 M
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RA[7] nCRAS F 11.608 4 3.487 M
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RA[8] RCLK R 10.916 4 3.308 M
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RA[8] nCRAS F 11.380 4 3.415 M
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RA[9] RCLK R 11.115 4 3.362 M
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RA[9] nCRAS F 11.201 4 3.380 M
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RBA[0] nCRAS F 8.645 4 2.828 M
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RBA[1] nCRAS F 8.645 4 2.828 M
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RCKE RCLK R 8.593 4 2.793 M
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RDQMH RCLK R 10.909 4 3.327 M
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RDQML RCLK R 10.348 4 3.207 M
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RD[0] nCCAS F 8.761 4 2.984 M
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RD[1] nCCAS F 8.761 4 2.984 M
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RD[2] nCCAS F 8.761 4 2.984 M
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RD[3] nCCAS F 8.761 4 2.984 M
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RD[4] nCCAS F 8.761 4 2.984 M
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RD[5] nCCAS F 8.761 4 2.984 M
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RD[6] nCCAS F 8.761 4 2.984 M
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RD[7] nCCAS F 8.761 4 2.984 M
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nRCAS RCLK R 7.578 4 2.578 M
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nRCS RCLK R 7.578 4 2.578 M
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nRRAS RCLK R 7.578 4 2.578 M
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nRWE RCLK R 7.558 4 2.585 M
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WARNING: you must also run trce with hold speed: 4
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WARNING: you must also run trce with setup speed: M
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