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RAM2GS/CPLD/LCMXO2-640HC/impl1/RAM2GS_LCMXO2_640HC_impl1_twr.html
Zane Kaminski 8cbf2f47ad RC?
2023-08-16 05:11:25 -04:00

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<HEAD><TITLE>Lattice TRACE Report</TITLE>
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<PRE><A name="Par_Twr"></A><B><U><big>Place & Route TRACE Report</big></U></B>
Loading design for application trce from file ram2gs_lcmxo2_640hc_impl1.ncd.
Design name: RAM2GS
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-640HC
Package: TQFP100
Performance: 4
Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status: Final Version 1.39.
Performance Hardware Data Status: Final Version 34.4.
Setup and Hold Report
--------------------------------------------------------------------------------
<A name="Par_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454</big></U></B>
Tue Aug 15 22:56:39 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
<A name="ptwr_set_ri"></A><B><U><big>Report Information</big></U></B>
------------------
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
Design file: ram2gs_lcmxo2_640hc_impl1.ncd
Preference file: ram2gs_lcmxo2_640hc_impl1.prf
Device,speed: LCMXO2-640HC,4
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
<A name="ptwr_set_ps"></A><B><U><big>Preference Summary</big></U></B>
<LI><A href='#par_twr_pref_0_0' Target='right'>FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)</A></LI> 170 items scored, 0 timing errors detected.
Report: 55.475MHz is the maximum frequency for this preference.
<LI><A href='#par_twr_pref_0_1' Target='right'>FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
Report: 150.150MHz is the maximum frequency for this preference.
<LI><A href='#par_twr_pref_0_2' Target='right'>FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
Report: 150.150MHz is the maximum frequency for this preference.
<LI><A href='#par_twr_pref_0_3' Target='right'>FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)</A></LI> 590 items scored, 0 timing errors detected.
Report: 101.286MHz is the maximum frequency for this preference.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_0_0"></A>Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
170 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 163.401ns (weighted slack = 326.802ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[3] (from PHI2_c +)
Destination: FF Data in CmdUFMSDI (to PHI2_c -)
Delay: 8.950ns (28.6% logic, 71.4% route), 5 logic levels.
Constraint Details:
8.950ns physical path delay Din[3]_MGIOL to Din[0]_MGIOL meets
172.414ns delay constraint less
0.000ns skew and
0.063ns CE_SET requirement (totaling 172.351ns) by 163.401ns
Physical Path Details:
Data path Din[3]_MGIOL to Din[0]_MGIOL:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_T6C.CLK to IOL_T6C.IN Din[3]_MGIOL (from PHI2_c)
ROUTE 1 1.496 IOL_T6C.IN to R4C6A.C1 Bank[3]
CTOF_DEL --- 0.495 R4C6A.C1 to R4C6A.F1 SLICE_43
ROUTE 1 0.623 R4C6A.F1 to R3C6A.D0 un1_Bank_1_4
CTOF_DEL --- 0.495 R3C6A.D0 to R3C6A.F0 SLICE_69
ROUTE 5 1.213 R3C6A.F0 to R4C8A.C0 un1_Bank_1
CTOF_DEL --- 0.495 R4C8A.C0 to R4C8A.F0 SLICE_57
ROUTE 5 0.710 R4C8A.F0 to R4C8B.B1 XOR8MEG18
CTOF_DEL --- 0.495 R4C8B.B1 to R4C8B.F1 SLICE_20
ROUTE 3 2.351 R4C8B.F1 to IOL_L2C.CE CmdUFMCLK_1_sqmuxa (to PHI2_c)
--------
8.950 (28.6% logic, 71.4% route), 5 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to Din[3]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 19 3.712 8.PADDI to IOL_T6C.CLK PHI2_c
--------
3.712 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to Din[0]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 19 3.712 8.PADDI to IOL_L2C.CLK PHI2_c
--------
3.712 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 163.452ns (weighted slack = 326.904ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[7] (from PHI2_c +)
Destination: FF Data in CmdUFMSDI (to PHI2_c -)
Delay: 8.899ns (28.7% logic, 71.3% route), 5 logic levels.
Constraint Details:
8.899ns physical path delay Din[7]_MGIOL to Din[0]_MGIOL meets
172.414ns delay constraint less
0.000ns skew and
0.063ns CE_SET requirement (totaling 172.351ns) by 163.452ns
Physical Path Details:
Data path Din[7]_MGIOL to Din[0]_MGIOL:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_L2A.CLK to IOL_L2A.IN Din[7]_MGIOL (from PHI2_c)
ROUTE 1 1.375 IOL_L2A.IN to R3C6A.D1 Bank[7]
CTOF_DEL --- 0.495 R3C6A.D1 to R3C6A.F1 SLICE_69
ROUTE 1 0.693 R3C6A.F1 to R3C6A.B0 un1_Bank_1_3
CTOF_DEL --- 0.495 R3C6A.B0 to R3C6A.F0 SLICE_69
ROUTE 5 1.213 R3C6A.F0 to R4C8A.C0 un1_Bank_1
CTOF_DEL --- 0.495 R4C8A.C0 to R4C8A.F0 SLICE_57
ROUTE 5 0.710 R4C8A.F0 to R4C8B.B1 XOR8MEG18
CTOF_DEL --- 0.495 R4C8B.B1 to R4C8B.F1 SLICE_20
ROUTE 3 2.351 R4C8B.F1 to IOL_L2C.CE CmdUFMCLK_1_sqmuxa (to PHI2_c)
--------
8.899 (28.7% logic, 71.3% route), 5 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to Din[7]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 19 3.712 8.PADDI to IOL_L2A.CLK PHI2_c
--------
3.712 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to Din[0]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 19 3.712 8.PADDI to IOL_L2C.CLK PHI2_c
--------
3.712 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 163.522ns (weighted slack = 327.044ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[4] (from PHI2_c +)
Destination: FF Data in CmdUFMSDI (to PHI2_c -)
Delay: 8.829ns (29.0% logic, 71.0% route), 5 logic levels.
Constraint Details:
8.829ns physical path delay Din[4]_MGIOL to Din[0]_MGIOL meets
172.414ns delay constraint less
0.000ns skew and
0.063ns CE_SET requirement (totaling 172.351ns) by 163.522ns
Physical Path Details:
Data path Din[4]_MGIOL to Din[0]_MGIOL:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_T6A.CLK to IOL_T6A.IN Din[4]_MGIOL (from PHI2_c)
ROUTE 1 1.375 IOL_T6A.IN to R4C6A.D1 Bank[4]
CTOF_DEL --- 0.495 R4C6A.D1 to R4C6A.F1 SLICE_43
ROUTE 1 0.623 R4C6A.F1 to R3C6A.D0 un1_Bank_1_4
CTOF_DEL --- 0.495 R3C6A.D0 to R3C6A.F0 SLICE_69
ROUTE 5 1.213 R3C6A.F0 to R4C8A.C0 un1_Bank_1
CTOF_DEL --- 0.495 R4C8A.C0 to R4C8A.F0 SLICE_57
ROUTE 5 0.710 R4C8A.F0 to R4C8B.B1 XOR8MEG18
CTOF_DEL --- 0.495 R4C8B.B1 to R4C8B.F1 SLICE_20
ROUTE 3 2.351 R4C8B.F1 to IOL_L2C.CE CmdUFMCLK_1_sqmuxa (to PHI2_c)
--------
8.829 (29.0% logic, 71.0% route), 5 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to Din[4]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 19 3.712 8.PADDI to IOL_T6A.CLK PHI2_c
--------
3.712 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to Din[0]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 19 3.712 8.PADDI to IOL_L2C.CLK PHI2_c
--------
3.712 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 163.573ns (weighted slack = 327.146ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[3] (from PHI2_c +)
Destination: FF Data in CmdEnable (to PHI2_c -)
Delay: 8.502ns (44.4% logic, 55.6% route), 7 logic levels.
Constraint Details:
8.502ns physical path delay Din[3]_MGIOL to SLICE_18 meets
172.414ns delay constraint less
0.173ns skew and
0.166ns DIN_SET requirement (totaling 172.075ns) by 163.573ns
Physical Path Details:
Data path Din[3]_MGIOL to SLICE_18:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_T6C.CLK to IOL_T6C.IN Din[3]_MGIOL (from PHI2_c)
ROUTE 1 1.496 IOL_T6C.IN to R4C6A.C1 Bank[3]
CTOF_DEL --- 0.495 R4C6A.C1 to R4C6A.F1 SLICE_43
ROUTE 1 0.623 R4C6A.F1 to R3C6A.D0 un1_Bank_1_4
CTOF_DEL --- 0.495 R3C6A.D0 to R3C6A.F0 SLICE_69
ROUTE 5 1.092 R3C6A.F0 to R4C8D.D0 un1_Bank_1
CTOF_DEL --- 0.495 R4C8D.D0 to R4C8D.F0 SLICE_60
ROUTE 2 0.758 R4C8D.F0 to R3C8D.C1 ADWR
CTOF_DEL --- 0.495 R3C8D.C1 to R3C8D.F1 SLICE_46
ROUTE 3 0.445 R3C8D.F1 to R3C8D.C0 un1_ADWR
CTOF_DEL --- 0.495 R3C8D.C0 to R3C8D.F0 SLICE_46
ROUTE 1 0.315 R3C8D.F0 to R3C8C.D0 un1_CMDWR
CTOOFX_DEL --- 0.721 R3C8C.D0 to R3C8C.OFX0 SLICE_18
ROUTE 1 0.000 R3C8C.OFX0 to R3C8C.DI0 CmdEnable_s (to PHI2_c)
--------
8.502 (44.4% logic, 55.6% route), 7 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to Din[3]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 19 3.712 8.PADDI to IOL_T6C.CLK PHI2_c
--------
3.712 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 19 3.539 8.PADDI to R3C8C.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 163.624ns (weighted slack = 327.248ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[7] (from PHI2_c +)
Destination: FF Data in CmdEnable (to PHI2_c -)
Delay: 8.451ns (44.6% logic, 55.4% route), 7 logic levels.
Constraint Details:
8.451ns physical path delay Din[7]_MGIOL to SLICE_18 meets
172.414ns delay constraint less
0.173ns skew and
0.166ns DIN_SET requirement (totaling 172.075ns) by 163.624ns
Physical Path Details:
Data path Din[7]_MGIOL to SLICE_18:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_L2A.CLK to IOL_L2A.IN Din[7]_MGIOL (from PHI2_c)
ROUTE 1 1.375 IOL_L2A.IN to R3C6A.D1 Bank[7]
CTOF_DEL --- 0.495 R3C6A.D1 to R3C6A.F1 SLICE_69
ROUTE 1 0.693 R3C6A.F1 to R3C6A.B0 un1_Bank_1_3
CTOF_DEL --- 0.495 R3C6A.B0 to R3C6A.F0 SLICE_69
ROUTE 5 1.092 R3C6A.F0 to R4C8D.D0 un1_Bank_1
CTOF_DEL --- 0.495 R4C8D.D0 to R4C8D.F0 SLICE_60
ROUTE 2 0.758 R4C8D.F0 to R3C8D.C1 ADWR
CTOF_DEL --- 0.495 R3C8D.C1 to R3C8D.F1 SLICE_46
ROUTE 3 0.445 R3C8D.F1 to R3C8D.C0 un1_ADWR
CTOF_DEL --- 0.495 R3C8D.C0 to R3C8D.F0 SLICE_46
ROUTE 1 0.315 R3C8D.F0 to R3C8C.D0 un1_CMDWR
CTOOFX_DEL --- 0.721 R3C8C.D0 to R3C8C.OFX0 SLICE_18
ROUTE 1 0.000 R3C8C.OFX0 to R3C8C.DI0 CmdEnable_s (to PHI2_c)
--------
8.451 (44.6% logic, 55.4% route), 7 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to Din[7]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 19 3.712 8.PADDI to IOL_L2A.CLK PHI2_c
--------
3.712 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 19 3.539 8.PADDI to R3C8C.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 163.694ns (weighted slack = 327.388ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[4] (from PHI2_c +)
Destination: FF Data in CmdEnable (to PHI2_c -)
Delay: 8.381ns (45.0% logic, 55.0% route), 7 logic levels.
Constraint Details:
8.381ns physical path delay Din[4]_MGIOL to SLICE_18 meets
172.414ns delay constraint less
0.173ns skew and
0.166ns DIN_SET requirement (totaling 172.075ns) by 163.694ns
Physical Path Details:
Data path Din[4]_MGIOL to SLICE_18:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_T6A.CLK to IOL_T6A.IN Din[4]_MGIOL (from PHI2_c)
ROUTE 1 1.375 IOL_T6A.IN to R4C6A.D1 Bank[4]
CTOF_DEL --- 0.495 R4C6A.D1 to R4C6A.F1 SLICE_43
ROUTE 1 0.623 R4C6A.F1 to R3C6A.D0 un1_Bank_1_4
CTOF_DEL --- 0.495 R3C6A.D0 to R3C6A.F0 SLICE_69
ROUTE 5 1.092 R3C6A.F0 to R4C8D.D0 un1_Bank_1
CTOF_DEL --- 0.495 R4C8D.D0 to R4C8D.F0 SLICE_60
ROUTE 2 0.758 R4C8D.F0 to R3C8D.C1 ADWR
CTOF_DEL --- 0.495 R3C8D.C1 to R3C8D.F1 SLICE_46
ROUTE 3 0.445 R3C8D.F1 to R3C8D.C0 un1_ADWR
CTOF_DEL --- 0.495 R3C8D.C0 to R3C8D.F0 SLICE_46
ROUTE 1 0.315 R3C8D.F0 to R3C8C.D0 un1_CMDWR
CTOOFX_DEL --- 0.721 R3C8C.D0 to R3C8C.OFX0 SLICE_18
ROUTE 1 0.000 R3C8C.OFX0 to R3C8C.DI0 CmdEnable_s (to PHI2_c)
--------
8.381 (45.0% logic, 55.0% route), 7 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to Din[4]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 19 3.712 8.PADDI to IOL_T6A.CLK PHI2_c
--------
3.712 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 19 3.539 8.PADDI to R3C8C.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 163.812ns (weighted slack = 327.624ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[0] (from PHI2_c +)
Destination: FF Data in CmdUFMSDI (to PHI2_c -)
Delay: 8.712ns (27.9% logic, 72.1% route), 5 logic levels.
Constraint Details:
8.712ns physical path delay SLICE_63 to Din[0]_MGIOL meets
172.414ns delay constraint less
-0.173ns skew and
0.063ns CE_SET requirement (totaling 172.524ns) by 163.812ns
Physical Path Details:
Data path SLICE_63 to Din[0]_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R4C7A.CLK to R4C7A.Q0 SLICE_63 (from PHI2_c)
ROUTE 1 1.383 R4C7A.Q0 to R4C6A.A1 Bank[0]
CTOF_DEL --- 0.495 R4C6A.A1 to R4C6A.F1 SLICE_43
ROUTE 1 0.623 R4C6A.F1 to R3C6A.D0 un1_Bank_1_4
CTOF_DEL --- 0.495 R3C6A.D0 to R3C6A.F0 SLICE_69
ROUTE 5 1.213 R3C6A.F0 to R4C8A.C0 un1_Bank_1
CTOF_DEL --- 0.495 R4C8A.C0 to R4C8A.F0 SLICE_57
ROUTE 5 0.710 R4C8A.F0 to R4C8B.B1 XOR8MEG18
CTOF_DEL --- 0.495 R4C8B.B1 to R4C8B.F1 SLICE_20
ROUTE 3 2.351 R4C8B.F1 to IOL_L2C.CE CmdUFMCLK_1_sqmuxa (to PHI2_c)
--------
8.712 (27.9% logic, 72.1% route), 5 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_63:
Name Fanout Delay (ns) Site Resource
ROUTE 19 3.539 8.PADDI to R4C7A.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to Din[0]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 19 3.712 8.PADDI to IOL_L2C.CLK PHI2_c
--------
3.712 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 163.984ns (weighted slack = 327.968ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[0] (from PHI2_c +)
Destination: FF Data in CmdEnable (to PHI2_c -)
Delay: 8.264ns (44.1% logic, 55.9% route), 7 logic levels.
Constraint Details:
8.264ns physical path delay SLICE_63 to SLICE_18 meets
172.414ns delay constraint less
0.000ns skew and
0.166ns DIN_SET requirement (totaling 172.248ns) by 163.984ns
Physical Path Details:
Data path SLICE_63 to SLICE_18:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R4C7A.CLK to R4C7A.Q0 SLICE_63 (from PHI2_c)
ROUTE 1 1.383 R4C7A.Q0 to R4C6A.A1 Bank[0]
CTOF_DEL --- 0.495 R4C6A.A1 to R4C6A.F1 SLICE_43
ROUTE 1 0.623 R4C6A.F1 to R3C6A.D0 un1_Bank_1_4
CTOF_DEL --- 0.495 R3C6A.D0 to R3C6A.F0 SLICE_69
ROUTE 5 1.092 R3C6A.F0 to R4C8D.D0 un1_Bank_1
CTOF_DEL --- 0.495 R4C8D.D0 to R4C8D.F0 SLICE_60
ROUTE 2 0.758 R4C8D.F0 to R3C8D.C1 ADWR
CTOF_DEL --- 0.495 R3C8D.C1 to R3C8D.F1 SLICE_46
ROUTE 3 0.445 R3C8D.F1 to R3C8D.C0 un1_ADWR
CTOF_DEL --- 0.495 R3C8D.C0 to R3C8D.F0 SLICE_46
ROUTE 1 0.315 R3C8D.F0 to R3C8C.D0 un1_CMDWR
CTOOFX_DEL --- 0.721 R3C8C.D0 to R3C8C.OFX0 SLICE_18
ROUTE 1 0.000 R3C8C.OFX0 to R3C8C.DI0 CmdEnable_s (to PHI2_c)
--------
8.264 (44.1% logic, 55.9% route), 7 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_63:
Name Fanout Delay (ns) Site Resource
ROUTE 19 3.539 8.PADDI to R4C7A.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 19 3.539 8.PADDI to R3C8C.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 164.041ns (weighted slack = 328.082ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[3] (from PHI2_c +)
Destination: FF Data in ADSubmitted (to PHI2_c -)
Delay: 8.034ns (38.0% logic, 62.0% route), 6 logic levels.
Constraint Details:
8.034ns physical path delay Din[3]_MGIOL to SLICE_10 meets
172.414ns delay constraint less
0.173ns skew and
0.166ns DIN_SET requirement (totaling 172.075ns) by 164.041ns
Physical Path Details:
Data path Din[3]_MGIOL to SLICE_10:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_T6C.CLK to IOL_T6C.IN Din[3]_MGIOL (from PHI2_c)
ROUTE 1 1.496 IOL_T6C.IN to R4C6A.C1 Bank[3]
CTOF_DEL --- 0.495 R4C6A.C1 to R4C6A.F1 SLICE_43
ROUTE 1 0.623 R4C6A.F1 to R3C6A.D0 un1_Bank_1_4
CTOF_DEL --- 0.495 R3C6A.D0 to R3C6A.F0 SLICE_69
ROUTE 5 1.092 R3C6A.F0 to R4C8D.D0 un1_Bank_1
CTOF_DEL --- 0.495 R4C8D.D0 to R4C8D.F0 SLICE_60
ROUTE 2 0.758 R4C8D.F0 to R3C8B.C1 ADWR
CTOF_DEL --- 0.495 R3C8B.C1 to R3C8B.F1 SLICE_10
ROUTE 2 1.013 R3C8B.F1 to R3C8B.B0 CmdEnable17
CTOF_DEL --- 0.495 R3C8B.B0 to R3C8B.F0 SLICE_10
ROUTE 1 0.000 R3C8B.F0 to R3C8B.DI0 ADSubmitted_r (to PHI2_c)
--------
8.034 (38.0% logic, 62.0% route), 6 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to Din[3]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 19 3.712 8.PADDI to IOL_T6C.CLK PHI2_c
--------
3.712 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_10:
Name Fanout Delay (ns) Site Resource
ROUTE 19 3.539 8.PADDI to R3C8B.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 164.046ns (weighted slack = 328.092ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Bank_0io[2] (from PHI2_c +)
Destination: FF Data in CmdUFMSDI (to PHI2_c -)
Delay: 8.478ns (28.7% logic, 71.3% route), 5 logic levels.
Constraint Details:
8.478ns physical path delay SLICE_68 to Din[0]_MGIOL meets
172.414ns delay constraint less
-0.173ns skew and
0.063ns CE_SET requirement (totaling 172.524ns) by 164.046ns
Physical Path Details:
Data path SLICE_68 to Din[0]_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R3C9C.CLK to R3C9C.Q0 SLICE_68 (from PHI2_c)
ROUTE 1 1.079 R3C9C.Q0 to R3C6A.C1 Bank[2]
CTOF_DEL --- 0.495 R3C6A.C1 to R3C6A.F1 SLICE_69
ROUTE 1 0.693 R3C6A.F1 to R3C6A.B0 un1_Bank_1_3
CTOF_DEL --- 0.495 R3C6A.B0 to R3C6A.F0 SLICE_69
ROUTE 5 1.213 R3C6A.F0 to R4C8A.C0 un1_Bank_1
CTOF_DEL --- 0.495 R4C8A.C0 to R4C8A.F0 SLICE_57
ROUTE 5 0.710 R4C8A.F0 to R4C8B.B1 XOR8MEG18
CTOF_DEL --- 0.495 R4C8B.B1 to R4C8B.F1 SLICE_20
ROUTE 3 2.351 R4C8B.F1 to IOL_L2C.CE CmdUFMCLK_1_sqmuxa (to PHI2_c)
--------
8.478 (28.7% logic, 71.3% route), 5 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_68:
Name Fanout Delay (ns) Site Resource
ROUTE 19 3.539 8.PADDI to R3C9C.CLK PHI2_c
--------
3.539 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to Din[0]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 19 3.712 8.PADDI to IOL_L2C.CLK PHI2_c
--------
3.712 (0.0% logic, 100.0% route), 0 logic levels.
Report: 55.475MHz is the maximum frequency for this preference.
================================================================================
<A name="par_twr_pref_0_1"></A>Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 338.168ns
The internal maximum frequency of the following component is 150.150 MHz
Logical Details: Cell type Pin name Component name
Destination: PIO PAD nCCAS
Delay: 6.660ns -- based on Minimum Pulse Width
Report: 150.150MHz is the maximum frequency for this preference.
================================================================================
<A name="par_twr_pref_0_2"></A>Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 338.168ns
The internal maximum frequency of the following component is 150.150 MHz
Logical Details: Cell type Pin name Component name
Destination: PIO PAD nCRAS
Delay: 6.660ns -- based on Minimum Pulse Width
Report: 150.150MHz is the maximum frequency for this preference.
================================================================================
<A name="par_twr_pref_0_3"></A>Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
590 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 6.127ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[12] (from RCLK_c +)
Destination: FF Data in LEDEN (to RCLK_c +)
Delay: 9.591ns (35.7% logic, 64.3% route), 7 logic levels.
Constraint Details:
9.591ns physical path delay SLICE_4 to SLICE_27 meets
16.000ns delay constraint less
0.000ns skew and
0.282ns CE_SET requirement (totaling 15.718ns) by 6.127ns
Physical Path Details:
Data path SLICE_4 to SLICE_27:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R6C4C.CLK to R6C4C.Q1 SLICE_4 (from RCLK_c)
ROUTE 3 1.177 R6C4C.Q1 to R6C5D.C1 FS[12]
CTOF_DEL --- 0.495 R6C5D.C1 to R6C5D.F1 SLICE_72
ROUTE 1 0.315 R6C5D.F1 to R6C5C.D1 UFMSDI_ens2_i_o2_0_3
CTOF_DEL --- 0.495 R6C5C.D1 to R6C5C.F1 SLICE_64
ROUTE 4 0.988 R6C5C.F1 to R5C4C.D1 N_129
CTOF_DEL --- 0.495 R5C4C.D1 to R5C4C.F1 SLICE_59
ROUTE 2 0.445 R5C4C.F1 to R5C4C.C0 N_145
CTOF_DEL --- 0.495 R5C4C.C0 to R5C4C.F0 SLICE_59
ROUTE 2 0.753 R5C4C.F0 to R5C3A.C0 N_139_8
CTOF_DEL --- 0.495 R5C3A.C0 to R5C3A.F0 SLICE_56
ROUTE 1 1.079 R5C3A.F0 to R4C4D.C0 N_140
CTOF_DEL --- 0.495 R4C4D.C0 to R4C4D.F0 SLICE_54
ROUTE 1 1.412 R4C4D.F0 to R5C7B.CE N_28 (to RCLK_c)
--------
9.591 (35.7% logic, 64.3% route), 7 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_4:
Name Fanout Delay (ns) Site Resource
ROUTE 39 3.070 62.PADDI to R6C4C.CLK RCLK_c
--------
3.070 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_27:
Name Fanout Delay (ns) Site Resource
ROUTE 39 3.070 62.PADDI to R5C7B.CLK RCLK_c
--------
3.070 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 6.287ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[17] (from RCLK_c +)
Destination: FF Data in LEDEN (to RCLK_c +)
Delay: 9.431ns (36.3% logic, 63.7% route), 7 logic levels.
Constraint Details:
9.431ns physical path delay SLICE_1 to SLICE_27 meets
16.000ns delay constraint less
0.000ns skew and
0.282ns CE_SET requirement (totaling 15.718ns) by 6.287ns
Physical Path Details:
Data path SLICE_1 to SLICE_27:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R6C5B.CLK to R6C5B.Q0 SLICE_1 (from RCLK_c)
ROUTE 3 1.017 R6C5B.Q0 to R6C5D.B1 FS[17]
CTOF_DEL --- 0.495 R6C5D.B1 to R6C5D.F1 SLICE_72
ROUTE 1 0.315 R6C5D.F1 to R6C5C.D1 UFMSDI_ens2_i_o2_0_3
CTOF_DEL --- 0.495 R6C5C.D1 to R6C5C.F1 SLICE_64
ROUTE 4 0.988 R6C5C.F1 to R5C4C.D1 N_129
CTOF_DEL --- 0.495 R5C4C.D1 to R5C4C.F1 SLICE_59
ROUTE 2 0.445 R5C4C.F1 to R5C4C.C0 N_145
CTOF_DEL --- 0.495 R5C4C.C0 to R5C4C.F0 SLICE_59
ROUTE 2 0.753 R5C4C.F0 to R5C3A.C0 N_139_8
CTOF_DEL --- 0.495 R5C3A.C0 to R5C3A.F0 SLICE_56
ROUTE 1 1.079 R5C3A.F0 to R4C4D.C0 N_140
CTOF_DEL --- 0.495 R4C4D.C0 to R4C4D.F0 SLICE_54
ROUTE 1 1.412 R4C4D.F0 to R5C7B.CE N_28 (to RCLK_c)
--------
9.431 (36.3% logic, 63.7% route), 7 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_1:
Name Fanout Delay (ns) Site Resource
ROUTE 39 3.070 62.PADDI to R6C5B.CLK RCLK_c
--------
3.070 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_27:
Name Fanout Delay (ns) Site Resource
ROUTE 39 3.070 62.PADDI to R5C7B.CLK RCLK_c
--------
3.070 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 6.319ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[13] (from RCLK_c +)
Destination: FF Data in LEDEN (to RCLK_c +)
Delay: 9.399ns (36.4% logic, 63.6% route), 7 logic levels.
Constraint Details:
9.399ns physical path delay SLICE_3 to SLICE_27 meets
16.000ns delay constraint less
0.000ns skew and
0.282ns CE_SET requirement (totaling 15.718ns) by 6.319ns
Physical Path Details:
Data path SLICE_3 to SLICE_27:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R6C4D.CLK to R6C4D.Q0 SLICE_3 (from RCLK_c)
ROUTE 3 0.985 R6C4D.Q0 to R6C5D.A1 FS[13]
CTOF_DEL --- 0.495 R6C5D.A1 to R6C5D.F1 SLICE_72
ROUTE 1 0.315 R6C5D.F1 to R6C5C.D1 UFMSDI_ens2_i_o2_0_3
CTOF_DEL --- 0.495 R6C5C.D1 to R6C5C.F1 SLICE_64
ROUTE 4 0.988 R6C5C.F1 to R5C4C.D1 N_129
CTOF_DEL --- 0.495 R5C4C.D1 to R5C4C.F1 SLICE_59
ROUTE 2 0.445 R5C4C.F1 to R5C4C.C0 N_145
CTOF_DEL --- 0.495 R5C4C.C0 to R5C4C.F0 SLICE_59
ROUTE 2 0.753 R5C4C.F0 to R5C3A.C0 N_139_8
CTOF_DEL --- 0.495 R5C3A.C0 to R5C3A.F0 SLICE_56
ROUTE 1 1.079 R5C3A.F0 to R4C4D.C0 N_140
CTOF_DEL --- 0.495 R4C4D.C0 to R4C4D.F0 SLICE_54
ROUTE 1 1.412 R4C4D.F0 to R5C7B.CE N_28 (to RCLK_c)
--------
9.399 (36.4% logic, 63.6% route), 7 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_3:
Name Fanout Delay (ns) Site Resource
ROUTE 39 3.070 62.PADDI to R6C4D.CLK RCLK_c
--------
3.070 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_27:
Name Fanout Delay (ns) Site Resource
ROUTE 39 3.070 62.PADDI to R5C7B.CLK RCLK_c
--------
3.070 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 6.646ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[14] (from RCLK_c +)
Destination: FF Data in LEDEN (to RCLK_c +)
Delay: 9.072ns (37.7% logic, 62.3% route), 7 logic levels.
Constraint Details:
9.072ns physical path delay SLICE_3 to SLICE_27 meets
16.000ns delay constraint less
0.000ns skew and
0.282ns CE_SET requirement (totaling 15.718ns) by 6.646ns
Physical Path Details:
Data path SLICE_3 to SLICE_27:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R6C4D.CLK to R6C4D.Q1 SLICE_3 (from RCLK_c)
ROUTE 3 0.658 R6C4D.Q1 to R6C5D.D1 FS[14]
CTOF_DEL --- 0.495 R6C5D.D1 to R6C5D.F1 SLICE_72
ROUTE 1 0.315 R6C5D.F1 to R6C5C.D1 UFMSDI_ens2_i_o2_0_3
CTOF_DEL --- 0.495 R6C5C.D1 to R6C5C.F1 SLICE_64
ROUTE 4 0.988 R6C5C.F1 to R5C4C.D1 N_129
CTOF_DEL --- 0.495 R5C4C.D1 to R5C4C.F1 SLICE_59
ROUTE 2 0.445 R5C4C.F1 to R5C4C.C0 N_145
CTOF_DEL --- 0.495 R5C4C.C0 to R5C4C.F0 SLICE_59
ROUTE 2 0.753 R5C4C.F0 to R5C3A.C0 N_139_8
CTOF_DEL --- 0.495 R5C3A.C0 to R5C3A.F0 SLICE_56
ROUTE 1 1.079 R5C3A.F0 to R4C4D.C0 N_140
CTOF_DEL --- 0.495 R4C4D.C0 to R4C4D.F0 SLICE_54
ROUTE 1 1.412 R4C4D.F0 to R5C7B.CE N_28 (to RCLK_c)
--------
9.072 (37.7% logic, 62.3% route), 7 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_3:
Name Fanout Delay (ns) Site Resource
ROUTE 39 3.070 62.PADDI to R6C4D.CLK RCLK_c
--------
3.070 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_27:
Name Fanout Delay (ns) Site Resource
ROUTE 39 3.070 62.PADDI to R5C7B.CLK RCLK_c
--------
3.070 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 6.977ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[12] (from RCLK_c +)
Destination: FF Data in n8MEGEN (to RCLK_c +)
Delay: 8.741ns (39.1% logic, 60.9% route), 7 logic levels.
Constraint Details:
8.741ns physical path delay SLICE_4 to SLICE_43 meets
16.000ns delay constraint less
0.000ns skew and
0.282ns CE_SET requirement (totaling 15.718ns) by 6.977ns
Physical Path Details:
Data path SLICE_4 to SLICE_43:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R6C4C.CLK to R6C4C.Q1 SLICE_4 (from RCLK_c)
ROUTE 3 1.177 R6C4C.Q1 to R6C5D.C1 FS[12]
CTOF_DEL --- 0.495 R6C5D.C1 to R6C5D.F1 SLICE_72
ROUTE 1 0.315 R6C5D.F1 to R6C5C.D1 UFMSDI_ens2_i_o2_0_3
CTOF_DEL --- 0.495 R6C5C.D1 to R6C5C.F1 SLICE_64
ROUTE 4 0.988 R6C5C.F1 to R5C4C.D1 N_129
CTOF_DEL --- 0.495 R5C4C.D1 to R5C4C.F1 SLICE_59
ROUTE 2 0.445 R5C4C.F1 to R5C4C.C0 N_145
CTOF_DEL --- 0.495 R5C4C.C0 to R5C4C.F0 SLICE_59
ROUTE 2 0.632 R5C4C.F0 to R4C4A.D1 N_139_8
CTOF_DEL --- 0.495 R4C4A.D1 to R4C4A.F1 SLICE_55
ROUTE 1 0.693 R4C4A.F1 to R4C4A.B0 N_139
CTOF_DEL --- 0.495 R4C4A.B0 to R4C4A.F0 SLICE_55
ROUTE 1 1.069 R4C4A.F0 to R4C6A.CE N_26 (to RCLK_c)
--------
8.741 (39.1% logic, 60.9% route), 7 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_4:
Name Fanout Delay (ns) Site Resource
ROUTE 39 3.070 62.PADDI to R6C4C.CLK RCLK_c
--------
3.070 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_43:
Name Fanout Delay (ns) Site Resource
ROUTE 39 3.070 62.PADDI to R4C6A.CLK RCLK_c
--------
3.070 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.097ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[16] (from RCLK_c +)
Destination: FF Data in LEDEN (to RCLK_c +)
Delay: 8.621ns (34.0% logic, 66.0% route), 6 logic levels.
Constraint Details:
8.621ns physical path delay SLICE_2 to SLICE_27 meets
16.000ns delay constraint less
0.000ns skew and
0.282ns CE_SET requirement (totaling 15.718ns) by 7.097ns
Physical Path Details:
Data path SLICE_2 to SLICE_27:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R6C5A.CLK to R6C5A.Q1 SLICE_2 (from RCLK_c)
ROUTE 4 1.017 R6C5A.Q1 to R6C5C.B1 FS[16]
CTOF_DEL --- 0.495 R6C5C.B1 to R6C5C.F1 SLICE_64
ROUTE 4 0.988 R6C5C.F1 to R5C4C.D1 N_129
CTOF_DEL --- 0.495 R5C4C.D1 to R5C4C.F1 SLICE_59
ROUTE 2 0.445 R5C4C.F1 to R5C4C.C0 N_145
CTOF_DEL --- 0.495 R5C4C.C0 to R5C4C.F0 SLICE_59
ROUTE 2 0.753 R5C4C.F0 to R5C3A.C0 N_139_8
CTOF_DEL --- 0.495 R5C3A.C0 to R5C3A.F0 SLICE_56
ROUTE 1 1.079 R5C3A.F0 to R4C4D.C0 N_140
CTOF_DEL --- 0.495 R4C4D.C0 to R4C4D.F0 SLICE_54
ROUTE 1 1.412 R4C4D.F0 to R5C7B.CE N_28 (to RCLK_c)
--------
8.621 (34.0% logic, 66.0% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_2:
Name Fanout Delay (ns) Site Resource
ROUTE 39 3.070 62.PADDI to R6C5A.CLK RCLK_c
--------
3.070 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_27:
Name Fanout Delay (ns) Site Resource
ROUTE 39 3.070 62.PADDI to R5C7B.CLK RCLK_c
--------
3.070 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.137ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[17] (from RCLK_c +)
Destination: FF Data in n8MEGEN (to RCLK_c +)
Delay: 8.581ns (39.9% logic, 60.1% route), 7 logic levels.
Constraint Details:
8.581ns physical path delay SLICE_1 to SLICE_43 meets
16.000ns delay constraint less
0.000ns skew and
0.282ns CE_SET requirement (totaling 15.718ns) by 7.137ns
Physical Path Details:
Data path SLICE_1 to SLICE_43:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R6C5B.CLK to R6C5B.Q0 SLICE_1 (from RCLK_c)
ROUTE 3 1.017 R6C5B.Q0 to R6C5D.B1 FS[17]
CTOF_DEL --- 0.495 R6C5D.B1 to R6C5D.F1 SLICE_72
ROUTE 1 0.315 R6C5D.F1 to R6C5C.D1 UFMSDI_ens2_i_o2_0_3
CTOF_DEL --- 0.495 R6C5C.D1 to R6C5C.F1 SLICE_64
ROUTE 4 0.988 R6C5C.F1 to R5C4C.D1 N_129
CTOF_DEL --- 0.495 R5C4C.D1 to R5C4C.F1 SLICE_59
ROUTE 2 0.445 R5C4C.F1 to R5C4C.C0 N_145
CTOF_DEL --- 0.495 R5C4C.C0 to R5C4C.F0 SLICE_59
ROUTE 2 0.632 R5C4C.F0 to R4C4A.D1 N_139_8
CTOF_DEL --- 0.495 R4C4A.D1 to R4C4A.F1 SLICE_55
ROUTE 1 0.693 R4C4A.F1 to R4C4A.B0 N_139
CTOF_DEL --- 0.495 R4C4A.B0 to R4C4A.F0 SLICE_55
ROUTE 1 1.069 R4C4A.F0 to R4C6A.CE N_26 (to RCLK_c)
--------
8.581 (39.9% logic, 60.1% route), 7 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_1:
Name Fanout Delay (ns) Site Resource
ROUTE 39 3.070 62.PADDI to R6C5B.CLK RCLK_c
--------
3.070 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_43:
Name Fanout Delay (ns) Site Resource
ROUTE 39 3.070 62.PADDI to R4C6A.CLK RCLK_c
--------
3.070 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.169ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[13] (from RCLK_c +)
Destination: FF Data in n8MEGEN (to RCLK_c +)
Delay: 8.549ns (40.0% logic, 60.0% route), 7 logic levels.
Constraint Details:
8.549ns physical path delay SLICE_3 to SLICE_43 meets
16.000ns delay constraint less
0.000ns skew and
0.282ns CE_SET requirement (totaling 15.718ns) by 7.169ns
Physical Path Details:
Data path SLICE_3 to SLICE_43:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R6C4D.CLK to R6C4D.Q0 SLICE_3 (from RCLK_c)
ROUTE 3 0.985 R6C4D.Q0 to R6C5D.A1 FS[13]
CTOF_DEL --- 0.495 R6C5D.A1 to R6C5D.F1 SLICE_72
ROUTE 1 0.315 R6C5D.F1 to R6C5C.D1 UFMSDI_ens2_i_o2_0_3
CTOF_DEL --- 0.495 R6C5C.D1 to R6C5C.F1 SLICE_64
ROUTE 4 0.988 R6C5C.F1 to R5C4C.D1 N_129
CTOF_DEL --- 0.495 R5C4C.D1 to R5C4C.F1 SLICE_59
ROUTE 2 0.445 R5C4C.F1 to R5C4C.C0 N_145
CTOF_DEL --- 0.495 R5C4C.C0 to R5C4C.F0 SLICE_59
ROUTE 2 0.632 R5C4C.F0 to R4C4A.D1 N_139_8
CTOF_DEL --- 0.495 R4C4A.D1 to R4C4A.F1 SLICE_55
ROUTE 1 0.693 R4C4A.F1 to R4C4A.B0 N_139
CTOF_DEL --- 0.495 R4C4A.B0 to R4C4A.F0 SLICE_55
ROUTE 1 1.069 R4C4A.F0 to R4C6A.CE N_26 (to RCLK_c)
--------
8.549 (40.0% logic, 60.0% route), 7 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_3:
Name Fanout Delay (ns) Site Resource
ROUTE 39 3.070 62.PADDI to R6C4D.CLK RCLK_c
--------
3.070 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_43:
Name Fanout Delay (ns) Site Resource
ROUTE 39 3.070 62.PADDI to R4C6A.CLK RCLK_c
--------
3.070 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.281ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[12] (from RCLK_c +)
Destination: FF Data in UFMCLK_0io (to RCLK_c +)
Delay: 8.739ns (27.8% logic, 72.2% route), 5 logic levels.
Constraint Details:
8.739ns physical path delay SLICE_4 to UFMCLK_MGIOL meets
16.000ns delay constraint less
-0.173ns skew and
0.153ns DO_SET requirement (totaling 16.020ns) by 7.281ns
Physical Path Details:
Data path SLICE_4 to UFMCLK_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R6C4C.CLK to R6C4C.Q1 SLICE_4 (from RCLK_c)
ROUTE 3 1.434 R6C4C.Q1 to R6C5D.B0 FS[12]
CTOF_DEL --- 0.495 R6C5D.B0 to R6C5D.F0 SLICE_72
ROUTE 2 1.902 R6C5D.F0 to R5C5C.A1 N_137_5
CTOF_DEL --- 0.495 R5C5C.A1 to R5C5C.F1 SLICE_48
ROUTE 2 0.982 R5C5C.F1 to R5C5C.A0 UFMCLK_r_i_a2_2_2
CTOF_DEL --- 0.495 R5C5C.A0 to R5C5C.F0 SLICE_48
ROUTE 1 0.693 R5C5C.F0 to R5C5D.B0 d_m3_0_a2_0
CTOF_DEL --- 0.495 R5C5D.B0 to R5C5D.F0 SLICE_47
ROUTE 1 1.296 R5C5D.F0 to IOL_B4C.OPOS i1_i (to RCLK_c)
--------
8.739 (27.8% logic, 72.2% route), 5 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_4:
Name Fanout Delay (ns) Site Resource
ROUTE 39 3.070 62.PADDI to R6C4C.CLK RCLK_c
--------
3.070 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to UFMCLK_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 39 3.243 62.PADDI to IOL_B4C.CLK RCLK_c
--------
3.243 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.354ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[15] (from RCLK_c +)
Destination: FF Data in LEDEN (to RCLK_c +)
Delay: 8.364ns (35.0% logic, 65.0% route), 6 logic levels.
Constraint Details:
8.364ns physical path delay SLICE_2 to SLICE_27 meets
16.000ns delay constraint less
0.000ns skew and
0.282ns CE_SET requirement (totaling 15.718ns) by 7.354ns
Physical Path Details:
Data path SLICE_2 to SLICE_27:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R6C5A.CLK to R6C5A.Q0 SLICE_2 (from RCLK_c)
ROUTE 3 0.760 R6C5A.Q0 to R6C5C.C1 FS[15]
CTOF_DEL --- 0.495 R6C5C.C1 to R6C5C.F1 SLICE_64
ROUTE 4 0.988 R6C5C.F1 to R5C4C.D1 N_129
CTOF_DEL --- 0.495 R5C4C.D1 to R5C4C.F1 SLICE_59
ROUTE 2 0.445 R5C4C.F1 to R5C4C.C0 N_145
CTOF_DEL --- 0.495 R5C4C.C0 to R5C4C.F0 SLICE_59
ROUTE 2 0.753 R5C4C.F0 to R5C3A.C0 N_139_8
CTOF_DEL --- 0.495 R5C3A.C0 to R5C3A.F0 SLICE_56
ROUTE 1 1.079 R5C3A.F0 to R4C4D.C0 N_140
CTOF_DEL --- 0.495 R4C4D.C0 to R4C4D.F0 SLICE_54
ROUTE 1 1.412 R4C4D.F0 to R5C7B.CE N_28 (to RCLK_c)
--------
8.364 (35.0% logic, 65.0% route), 6 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_2:
Name Fanout Delay (ns) Site Resource
ROUTE 39 3.070 62.PADDI to R6C5A.CLK RCLK_c
--------
3.070 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_27:
Name Fanout Delay (ns) Site Resource
ROUTE 39 3.070 62.PADDI to R5C7B.CLK RCLK_c
--------
3.070 (0.0% logic, 100.0% route), 0 logic levels.
Report: 101.286MHz is the maximum frequency for this preference.
<A name="ptwr_set_rs"></A><B><U><big>Report Summary</big></U></B>
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "PHI2" 2.900000 MHz ; | 2.900 MHz| 55.475 MHz| 5
| | |
FREQUENCY PORT "nCCAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
| | |
FREQUENCY PORT "nCRAS" 2.900000 MHz ; | 2.900 MHz| 150.150 MHz| 0
| | |
FREQUENCY PORT "RCLK" 62.500000 MHz ; | 62.500 MHz| 101.286 MHz| 7
| | |
----------------------------------------------------------------------------
All preferences were met.
<A name="ptwr_set_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
------------------------
Found 4 clocks:
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12
No transfer within this clock domain is found
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
No transfer within this clock domain is found
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 39
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
Data transfers from:
Clock Domain: nCRAS_c Source: nCRAS.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD Loads: 19
Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
<A name="ptwr_set_ts"></A><B><U><big>Timing summary (Setup):</big></U></B>
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 760 paths, 4 nets, and 439 connections (62.45% coverage)
--------------------------------------------------------------------------------
<A name="Par_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454</big></U></B>
Tue Aug 15 22:56:39 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
<A name="ptwr_hold_ri"></A><B><U><big>Report Information</big></U></B>
------------------
Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2GS_LCMXO2_640HC_impl1.twr -gui -msgset D:/OneDrive/Documents/GitHub/RAM2GS/CPLD/LCMXO2-640HC/promote.xml RAM2GS_LCMXO2_640HC_impl1.ncd RAM2GS_LCMXO2_640HC_impl1.prf
Design file: ram2gs_lcmxo2_640hc_impl1.ncd
Preference file: ram2gs_lcmxo2_640hc_impl1.prf
Device,speed: LCMXO2-640HC,m
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
<A name="ptwr_hold_ps"></A><B><U><big>Preference Summary</big></U></B>
<LI><A href='#par_twr_pref_1_0' Target='right'>FREQUENCY PORT "PHI2" 2.900000 MHz (0 errors)</A></LI> 170 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_1' Target='right'>FREQUENCY PORT "nCCAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_2' Target='right'>FREQUENCY PORT "nCRAS" 2.900000 MHz (0 errors)</A></LI> 0 items scored, 0 timing errors detected.
<LI><A href='#par_twr_pref_1_3' Target='right'>FREQUENCY PORT "RCLK" 62.500000 MHz (0 errors)</A></LI> 590 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_0"></A>Preference: FREQUENCY PORT "PHI2" 2.900000 MHz ;
170 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ADSubmitted (from PHI2_c -)
Destination: FF Data in ADSubmitted (to PHI2_c -)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_10 to SLICE_10 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_10 to SLICE_10:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R3C8B.CLK to R3C8B.Q0 SLICE_10 (from PHI2_c)
ROUTE 2 0.132 R3C8B.Q0 to R3C8B.A0 ADSubmitted
CTOF_DEL --- 0.101 R3C8B.A0 to R3C8B.F0 SLICE_10
ROUTE 1 0.000 R3C8B.F0 to R3C8B.DI0 ADSubmitted_r (to PHI2_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_10:
Name Fanout Delay (ns) Site Resource
ROUTE 19 1.240 8.PADDI to R3C8B.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_10:
Name Fanout Delay (ns) Site Resource
ROUTE 19 1.240 8.PADDI to R3C8B.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q C1Submitted (from PHI2_c -)
Destination: FF Data in C1Submitted (to PHI2_c -)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_13 to SLICE_13 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_13 to SLICE_13:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R3C8A.CLK to R3C8A.Q0 SLICE_13 (from PHI2_c)
ROUTE 2 0.132 R3C8A.Q0 to R3C8A.A0 C1Submitted
CTOF_DEL --- 0.101 R3C8A.A0 to R3C8A.F0 SLICE_13
ROUTE 1 0.000 R3C8A.F0 to R3C8A.DI0 C1Submitted_s (to PHI2_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_13:
Name Fanout Delay (ns) Site Resource
ROUTE 19 1.240 8.PADDI to R3C8A.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_13:
Name Fanout Delay (ns) Site Resource
ROUTE 19 1.240 8.PADDI to R3C8A.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdSubmitted (from PHI2_c -)
Destination: FF Data in CmdSubmitted (to PHI2_c -)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_20 to SLICE_20 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_20 to SLICE_20:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R4C8B.CLK to R4C8B.Q0 SLICE_20 (from PHI2_c)
ROUTE 4 0.132 R4C8B.Q0 to R4C8B.A0 CmdSubmitted
CTOF_DEL --- 0.101 R4C8B.A0 to R4C8B.F0 SLICE_20
ROUTE 1 0.000 R4C8B.F0 to R4C8B.DI0 N_412_0 (to PHI2_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 19 1.240 8.PADDI to R4C8B.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_20:
Name Fanout Delay (ns) Site Resource
ROUTE 19 1.240 8.PADDI to R4C8B.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q XOR8MEG (from PHI2_c -)
Destination: FF Data in XOR8MEG (to PHI2_c -)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_42 to SLICE_42 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_42 to SLICE_42:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C9B.CLK to R5C9B.Q0 SLICE_42 (from PHI2_c)
ROUTE 2 0.132 R5C9B.Q0 to R5C9B.A0 XOR8MEG
CTOF_DEL --- 0.101 R5C9B.A0 to R5C9B.F0 SLICE_42
ROUTE 1 0.000 R5C9B.F0 to R5C9B.DI0 XOR8MEG_3 (to PHI2_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_42:
Name Fanout Delay (ns) Site Resource
ROUTE 19 1.240 8.PADDI to R5C9B.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_42:
Name Fanout Delay (ns) Site Resource
ROUTE 19 1.240 8.PADDI to R5C9B.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.435ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdEnable (from PHI2_c -)
Destination: FF Data in CmdEnable (to PHI2_c -)
Delay: 0.422ns (68.5% logic, 31.5% route), 2 logic levels.
Constraint Details:
0.422ns physical path delay SLICE_18 to SLICE_18 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.435ns
Physical Path Details:
Data path SLICE_18 to SLICE_18:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R3C8C.CLK to R3C8C.Q0 SLICE_18 (from PHI2_c)
ROUTE 3 0.133 R3C8C.Q0 to R3C8C.A0 CmdEnable
CTOOFX_DEL --- 0.156 R3C8C.A0 to R3C8C.OFX0 SLICE_18
ROUTE 1 0.000 R3C8C.OFX0 to R3C8C.DI0 CmdEnable_s (to PHI2_c)
--------
0.422 (68.5% logic, 31.5% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 19 1.240 8.PADDI to R3C8C.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 19 1.240 8.PADDI to R3C8C.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.440ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ADSubmitted (from PHI2_c -)
Destination: FF Data in CmdEnable (to PHI2_c -)
Delay: 0.427ns (67.7% logic, 32.3% route), 2 logic levels.
Constraint Details:
0.427ns physical path delay SLICE_10 to SLICE_18 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.440ns
Physical Path Details:
Data path SLICE_10 to SLICE_18:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R3C8B.CLK to R3C8B.Q0 SLICE_10 (from PHI2_c)
ROUTE 2 0.138 R3C8B.Q0 to R3C8C.C1 ADSubmitted
CTOOFX_DEL --- 0.156 R3C8C.C1 to R3C8C.OFX0 SLICE_18
ROUTE 1 0.000 R3C8C.OFX0 to R3C8C.DI0 CmdEnable_s (to PHI2_c)
--------
0.427 (67.7% logic, 32.3% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_10:
Name Fanout Delay (ns) Site Resource
ROUTE 19 1.240 8.PADDI to R3C8B.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 19 1.240 8.PADDI to R3C8C.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.526ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q C1Submitted (from PHI2_c -)
Destination: FF Data in CmdEnable (to PHI2_c -)
Delay: 0.513ns (56.3% logic, 43.7% route), 2 logic levels.
Constraint Details:
0.513ns physical path delay SLICE_13 to SLICE_18 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.526ns
Physical Path Details:
Data path SLICE_13 to SLICE_18:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R3C8A.CLK to R3C8A.Q0 SLICE_13 (from PHI2_c)
ROUTE 2 0.224 R3C8A.Q0 to R3C8C.B0 C1Submitted
CTOOFX_DEL --- 0.156 R3C8C.B0 to R3C8C.OFX0 SLICE_18
ROUTE 1 0.000 R3C8C.OFX0 to R3C8C.DI0 CmdEnable_s (to PHI2_c)
--------
0.513 (56.3% logic, 43.7% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_13:
Name Fanout Delay (ns) Site Resource
ROUTE 19 1.240 8.PADDI to R3C8A.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 19 1.240 8.PADDI to R3C8C.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.527ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdEnable (from PHI2_c -)
Destination: FF Data in CmdEnable (to PHI2_c -)
Delay: 0.514ns (56.2% logic, 43.8% route), 2 logic levels.
Constraint Details:
0.514ns physical path delay SLICE_18 to SLICE_18 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.527ns
Physical Path Details:
Data path SLICE_18 to SLICE_18:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R3C8C.CLK to R3C8C.Q0 SLICE_18 (from PHI2_c)
ROUTE 3 0.225 R3C8C.Q0 to R3C8C.B1 CmdEnable
CTOOFX_DEL --- 0.156 R3C8C.B1 to R3C8C.OFX0 SLICE_18
ROUTE 1 0.000 R3C8C.OFX0 to R3C8C.DI0 CmdEnable_s (to PHI2_c)
--------
0.514 (56.2% logic, 43.8% route), 2 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 19 1.240 8.PADDI to R3C8C.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 19 1.240 8.PADDI to R3C8C.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.616ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CmdLEDEN (from PHI2_c -)
Destination: FF Data in CmdLEDEN (to PHI2_c -)
Delay: 0.603ns (55.6% logic, 44.4% route), 3 logic levels.
Constraint Details:
0.603ns physical path delay SLICE_19 to SLICE_19 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.616ns
Physical Path Details:
Data path SLICE_19 to SLICE_19:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C8B.CLK to R5C8B.Q0 SLICE_19 (from PHI2_c)
ROUTE 2 0.212 R5C8B.Q0 to R5C8A.A1 CmdLEDEN
CTOF_DEL --- 0.101 R5C8A.A1 to R5C8A.F1 SLICE_70
ROUTE 1 0.056 R5C8A.F1 to R5C8B.C0 N_59
CTOF_DEL --- 0.101 R5C8B.C0 to R5C8B.F0 SLICE_19
ROUTE 1 0.000 R5C8B.F0 to R5C8B.DI0 N_14_i (to PHI2_c)
--------
0.603 (55.6% logic, 44.4% route), 3 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 19 1.240 8.PADDI to R5C8B.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_19:
Name Fanout Delay (ns) Site Resource
ROUTE 19 1.240 8.PADDI to R5C8B.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.702ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Cmdn8MEGEN (from PHI2_c -)
Destination: FF Data in Cmdn8MEGEN (to PHI2_c -)
Delay: 0.689ns (48.6% logic, 51.4% route), 3 logic levels.
Constraint Details:
0.689ns physical path delay SLICE_21 to SLICE_21 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.702ns
Physical Path Details:
Data path SLICE_21 to SLICE_21:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C8D.CLK to R5C8D.Q0 SLICE_21 (from PHI2_c)
ROUTE 2 0.224 R5C8D.Q0 to R5C8C.B1 Cmdn8MEGEN
CTOF_DEL --- 0.101 R5C8C.B1 to R5C8C.F1 SLICE_50
ROUTE 1 0.130 R5C8C.F1 to R5C8D.A0 Cmdn8MEGEN_4_u_i_0
CTOF_DEL --- 0.101 R5C8D.A0 to R5C8D.F0 SLICE_21
ROUTE 1 0.000 R5C8D.F0 to R5C8D.DI0 N_12_i (to PHI2_c)
--------
0.689 (48.6% logic, 51.4% route), 3 logic levels.
Clock Skew Details:
Source Clock Path PHI2 to SLICE_21:
Name Fanout Delay (ns) Site Resource
ROUTE 19 1.240 8.PADDI to R5C8D.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path PHI2 to SLICE_21:
Name Fanout Delay (ns) Site Resource
ROUTE 19 1.240 8.PADDI to R5C8D.CLK PHI2_c
--------
1.240 (0.0% logic, 100.0% route), 0 logic levels.
================================================================================
<A name="par_twr_pref_1_1"></A>Preference: FREQUENCY PORT "nCCAS" 2.900000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_2"></A>Preference: FREQUENCY PORT "nCRAS" 2.900000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref_1_3"></A>Preference: FREQUENCY PORT "RCLK" 62.500000 MHz ;
590 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q CASr (from RCLK_c +)
Destination: FF Data in CASr2 (to RCLK_c +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay SLICE_14 to SLICE_14 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path SLICE_14 to SLICE_14:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C9A.CLK to R5C9A.Q0 SLICE_14 (from RCLK_c)
ROUTE 1 0.152 R5C9A.Q0 to R5C9A.M1 CASr (to RCLK_c)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_14:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.059 62.PADDI to R5C9A.CLK RCLK_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_14:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.059 62.PADDI to R5C9A.CLK RCLK_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.309ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RASr (from RCLK_c +)
Destination: FF Data in RASr2 (to RCLK_c +)
Delay: 0.290ns (45.9% logic, 54.1% route), 1 logic levels.
Constraint Details:
0.290ns physical path delay SLICE_29 to SLICE_29 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.309ns
Physical Path Details:
Data path SLICE_29 to SLICE_29:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R6C12B.CLK to R6C12B.Q0 SLICE_29 (from RCLK_c)
ROUTE 2 0.157 R6C12B.Q0 to R6C12B.M1 RASr (to RCLK_c)
--------
0.290 (45.9% logic, 54.1% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_29:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.059 62.PADDI to R6C12B.CLK RCLK_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_29:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.059 62.PADDI to R6C12B.CLK RCLK_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.311ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RASr2 (from RCLK_c +)
Destination: FF Data in RASr3 (to RCLK_c +)
Delay: 0.292ns (45.5% logic, 54.5% route), 1 logic levels.
Constraint Details:
0.292ns physical path delay SLICE_29 to SLICE_32 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.311ns
Physical Path Details:
Data path SLICE_29 to SLICE_32:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R6C12B.CLK to R6C12B.Q1 SLICE_29 (from RCLK_c)
ROUTE 10 0.159 R6C12B.Q1 to R6C12A.M1 RASr2 (to RCLK_c)
--------
0.292 (45.5% logic, 54.5% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_29:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.059 62.PADDI to R6C12B.CLK RCLK_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_32:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.059 62.PADDI to R6C12A.CLK RCLK_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.311ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q PHI2r2 (from RCLK_c +)
Destination: FF Data in PHI2r3 (to RCLK_c +)
Delay: 0.292ns (45.5% logic, 54.5% route), 1 logic levels.
Constraint Details:
0.292ns physical path delay SLICE_65 to SLICE_65 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.311ns
Physical Path Details:
Data path SLICE_65 to SLICE_65:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R4C4B.CLK to R4C4B.Q0 SLICE_65 (from RCLK_c)
ROUTE 3 0.159 R4C4B.Q0 to R4C4B.M1 PHI2r2 (to RCLK_c)
--------
0.292 (45.5% logic, 54.5% route), 1 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_65:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.059 62.PADDI to R4C4B.CLK RCLK_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_65:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.059 62.PADDI to R4C4B.CLK RCLK_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[0] (from RCLK_c +)
Destination: FF Data in FS[0] (to RCLK_c +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_0 to SLICE_0 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_0 to SLICE_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R6C3A.CLK to R6C3A.Q1 SLICE_0 (from RCLK_c)
ROUTE 3 0.132 R6C3A.Q1 to R6C3A.A1 FS[0]
CTOF_DEL --- 0.101 R6C3A.A1 to R6C3A.F1 SLICE_0
ROUTE 1 0.000 R6C3A.F1 to R6C3A.DI1 FS_s[0] (to RCLK_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_0:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.059 62.PADDI to R6C3A.CLK RCLK_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_0:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.059 62.PADDI to R6C3A.CLK RCLK_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[13] (from RCLK_c +)
Destination: FF Data in FS[13] (to RCLK_c +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_3 to SLICE_3 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_3 to SLICE_3:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R6C4D.CLK to R6C4D.Q0 SLICE_3 (from RCLK_c)
ROUTE 3 0.132 R6C4D.Q0 to R6C4D.A0 FS[13]
CTOF_DEL --- 0.101 R6C4D.A0 to R6C4D.F0 SLICE_3
ROUTE 1 0.000 R6C4D.F0 to R6C4D.DI0 FS_s[13] (to RCLK_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_3:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.059 62.PADDI to R6C4D.CLK RCLK_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_3:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.059 62.PADDI to R6C4D.CLK RCLK_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Ready_fast (from RCLK_c +)
Destination: FF Data in Ready_fast (to RCLK_c +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_34 to SLICE_34 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_34 to SLICE_34:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R4C13C.CLK to R4C13C.Q0 SLICE_34 (from RCLK_c)
ROUTE 14 0.132 R4C13C.Q0 to R4C13C.A0 Ready_fast
CTOF_DEL --- 0.101 R4C13C.A0 to R4C13C.F0 SLICE_34
ROUTE 1 0.000 R4C13C.F0 to R4C13C.DI0 N_415_0 (to RCLK_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_34:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.059 62.PADDI to R4C13C.CLK RCLK_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_34:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.059 62.PADDI to R4C13C.CLK RCLK_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[12] (from RCLK_c +)
Destination: FF Data in FS[12] (to RCLK_c +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_4 to SLICE_4 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_4 to SLICE_4:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R6C4C.CLK to R6C4C.Q1 SLICE_4 (from RCLK_c)
ROUTE 3 0.132 R6C4C.Q1 to R6C4C.A1 FS[12]
CTOF_DEL --- 0.101 R6C4C.A1 to R6C4C.F1 SLICE_4
ROUTE 1 0.000 R6C4C.F1 to R6C4C.DI1 FS_s[12] (to RCLK_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_4:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.059 62.PADDI to R6C4C.CLK RCLK_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_4:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.059 62.PADDI to R6C4C.CLK RCLK_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q nUFMCS (from RCLK_c +)
Destination: FF Data in nUFMCS (to RCLK_c +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_45 to SLICE_45 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_45 to SLICE_45:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C5A.CLK to R5C5A.Q0 SLICE_45 (from RCLK_c)
ROUTE 1 0.130 R5C5A.Q0 to R5C5A.A0 nUFMCS_c
CTOF_DEL --- 0.101 R5C5A.A0 to R5C5A.F0 SLICE_45
ROUTE 2 0.002 R5C5A.F0 to R5C5A.DI0 nUFMCS_s_0_N_5_i (to RCLK_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_45:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.059 62.PADDI to R5C5A.CLK RCLK_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_45:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.059 62.PADDI to R5C5A.CLK RCLK_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q FS[9] (from RCLK_c +)
Destination: FF Data in FS[9] (to RCLK_c +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_5 to SLICE_5 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_5 to SLICE_5:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R6C4B.CLK to R6C4B.Q0 SLICE_5 (from RCLK_c)
ROUTE 3 0.132 R6C4B.Q0 to R6C4B.A0 FS[9]
CTOF_DEL --- 0.101 R6C4B.A0 to R6C4B.F0 SLICE_5
ROUTE 1 0.000 R6C4B.F0 to R6C4B.DI0 FS_s[9] (to RCLK_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path RCLK to SLICE_5:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.059 62.PADDI to R6C4B.CLK RCLK_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path RCLK to SLICE_5:
Name Fanout Delay (ns) Site Resource
ROUTE 39 1.059 62.PADDI to R6C4B.CLK RCLK_c
--------
1.059 (0.0% logic, 100.0% route), 0 logic levels.
<A name="ptwr_hold_rs"></A><B><U><big>Report Summary</big></U></B>
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "PHI2" 2.900000 MHz ; | -| -| 2
| | |
FREQUENCY PORT "nCCAS" 2.900000 MHz ; | -| -| 0
| | |
FREQUENCY PORT "nCRAS" 2.900000 MHz ; | -| -| 0
| | |
FREQUENCY PORT "RCLK" 62.500000 MHz ; | -| -| 1
| | |
----------------------------------------------------------------------------
All preferences were met.
<A name="ptwr_hold_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
------------------------
Found 4 clocks:
Clock Domain: nCRAS_c Source: nCRAS.PAD Loads: 12
No transfer within this clock domain is found
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: nCCAS_c Source: nCCAS.PAD Loads: 10
No transfer within this clock domain is found
Clock Domain: RCLK_c Source: RCLK.PAD Loads: 39
Covered under: FREQUENCY PORT "RCLK" 62.500000 MHz ;
Data transfers from:
Clock Domain: nCRAS_c Source: nCRAS.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
Clock Domain: PHI2_c Source: PHI2.PAD Loads: 19
Covered under: FREQUENCY PORT "PHI2" 2.900000 MHz ;
Data transfers from:
Clock Domain: RCLK_c Source: RCLK.PAD
Not reported because source and destination domains are unrelated.
To report these transfers please refer to preference CLKSKEWDIFF to define
external clock skew between clock ports.
<A name="ptwr_hold_ts"></A><B><U><big>Timing summary (Hold):</big></U></B>
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 760 paths, 4 nets, and 439 connections (62.45% coverage)
<A name="ptwr_ts"></A><B><U><big>Timing summary (Setup and Hold):</big></U></B>
---------------
Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
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