mirror of
https://github.com/garrettsworkshop/RAM2GS.git
synced 2024-11-28 21:49:21 +00:00
113 lines
4.7 KiB
Plaintext
113 lines
4.7 KiB
Plaintext
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Copyright (C) 1994-2021 Synopsys, Inc.
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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
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and may only be used pursuant to the terms and conditions of a written license agreement
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with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
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Synopsys software or the associated documentation is strictly prohibited.
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Tool: Synplify Pro (R)
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Build: R-2021.03L-SP1
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Install: C:\lscc\diamond\3.12\synpbase
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OS: Windows 6.2
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Hostname: ZANEPC
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Implementation : impl1
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Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
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@N|Running in 64-bit mode
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###########################################################[
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Copyright (C) 1994-2021 Synopsys, Inc.
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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
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and may only be used pursuant to the terms and conditions of a written license agreement
|
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with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
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Synopsys software or the associated documentation is strictly prohibited.
|
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Tool: Synplify Pro (R)
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Build: R-2021.03L-SP1
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Install: C:\lscc\diamond\3.12\synpbase
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OS: Windows 6.2
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Hostname: ZANEPC
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Implementation : impl1
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Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
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@N|Running in 64-bit mode
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@N: CG1349 : | Running Verilog Compiler in System Verilog mode
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@N: CG1350 : | Running Verilog Compiler in Multiple File Compilation Unit mode
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@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v" (library work)
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@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
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@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
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@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
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@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
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@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
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@I::"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v" (library work)
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Verilog syntax check successful!
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Options changed - recompiling
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Selecting top level module RAM2GS
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@N: CG364 :"D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\RAM2GS-SPI.v":1:7:1:12|Synthesizing module RAM2GS in library work.
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Running optimization stage 1 on RAM2GS .......
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Finished optimization stage 1 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 93MB)
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Running optimization stage 2 on RAM2GS .......
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Finished optimization stage 2 on RAM2GS (CPU Time 0h:00m:00s, Memory Used current: 93MB peak: 94MB)
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For a summary of runtime and memory usage per design unit, please see file:
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==========================================================
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@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\layer0.rt.csv
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At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 93MB peak: 94MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Tue Aug 15 22:34:18 2023
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###########################################################]
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###########################################################[
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Copyright (C) 1994-2021 Synopsys, Inc.
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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
|
|
and may only be used pursuant to the terms and conditions of a written license agreement
|
|
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
|
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Synopsys software or the associated documentation is strictly prohibited.
|
|
Tool: Synplify Pro (R)
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Build: R-2021.03L-SP1
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Install: C:\lscc\diamond\3.12\synpbase
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OS: Windows 6.2
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Hostname: ZANEPC
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Implementation : impl1
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Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
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@N|Running in 64-bit mode
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@N: NF107 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":1:7:1:12|Selected library: work cell: RAM2GS view verilog as top level
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@N: NF107 :"d:\onedrive\documents\github\ram2gs\cpld\ram2gs-spi.v":1:7:1:12|Selected library: work cell: RAM2GS view verilog as top level
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At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Tue Aug 15 22:34:18 2023
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###########################################################]
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For a summary of runtime and memory usage for all design units, please see file:
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==========================================================
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@L: D:\OneDrive\Documents\GitHub\RAM2GS\CPLD\LCMXO2-640HC\impl1\synwork\impl1_comp.rt.csv
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@END
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At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 23MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Tue Aug 15 22:34:18 2023
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###########################################################]
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