mirror of
https://github.com/garrettsworkshop/RAM2GS.git
synced 2025-02-20 09:29:07 +00:00
67 lines
1.6 KiB
Tcl
67 lines
1.6 KiB
Tcl
#-- Lattice Semiconductor Corporation Ltd.
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#-- Synplify OEM project file
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#device options
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set_option -technology MACHXO2
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set_option -part LCMXO2_640HC
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set_option -package TG100C
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set_option -speed_grade -4
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#compilation/mapping options
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set_option -symbolic_fsm_compiler true
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set_option -resource_sharing true
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#use verilog 2001 standard option
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set_option -vlog_std v2001
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#map options
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set_option -frequency 100
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set_option -maxfan 1000
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set_option -auto_constrain_io 0
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set_option -disable_io_insertion false
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set_option -retiming false; set_option -pipe true
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set_option -force_gsr false
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set_option -compiler_compatible 0
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set_option -dup false
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add_file -constraint {Y:/Repos/RAM2GS/CPLD/RAM2GS.sdc}
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set_option -default_enum_encoding default
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#simulation options
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#timing analysis options
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#automatic place and route (vendor) options
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set_option -write_apr_constraint 1
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#synplifyPro options
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set_option -fix_gated_and_generated_clocks 1
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set_option -update_models_cp 0
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set_option -resolve_multiple_driver 0
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set_option -seqshift_no_replicate 0
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#-- add_file options
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set_option -include_path {Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC}
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add_file -verilog -vlog_std v2001 {Y:/Repos/RAM2GS/CPLD/RAM2GS-LCMXO2.v}
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add_file -verilog -vlog_std v2001 {Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/REFB.v}
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#-- top module name
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set_option -top_module RAM2GS
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#-- set result format/file last
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project -result_file {Y:/Repos/RAM2GS/CPLD/LCMXO2-640HC/impl1/LCMXO2_640HC_impl1.edi}
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#-- error message log file
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project -log_file {LCMXO2_640HC_impl1.srf}
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#-- set any command lines input by customer
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#-- run Synplify with 'arrange HDL file'
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project -run -clean
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