RAM2GS/CPLD/LCMXO2-640HC/impl1/lcmxo2_640hc_impl1_trce.asd

18 lines
381 B
Common Lisp

[ActiveSupport TRCE]
; Setup Analysis
Fmax_0 = 47.556 MHz (2.900 MHz);
Fmax_1 = 150.150 MHz (2.900 MHz);
Fmax_2 = 150.150 MHz (2.900 MHz);
Fmax_3 = 102.312 MHz (62.500 MHz);
Failed = 0 (Total 4);
Clock_ports = 4;
Clock_nets = 4;
; Hold Analysis
Fmax_0 = - (-);
Fmax_1 = - (-);
Fmax_2 = - (-);
Fmax_3 = - (-);
Failed = 0 (Total 4);
Clock_ports = 4;
Clock_nets = 4;